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[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
39 void (*emit_func)(struct si_context *ctx, struct r600_atom *state),
40 unsigned num_dw)
41 {
42 atom->emit = (void*)emit_func;
43 atom->num_dw = num_dw;
44 atom->dirty = false;
45 *list_elem = atom;
46 }
47
48 unsigned si_array_mode(unsigned mode)
49 {
50 switch (mode) {
51 case RADEON_SURF_MODE_LINEAR_ALIGNED:
52 return V_009910_ARRAY_LINEAR_ALIGNED;
53 case RADEON_SURF_MODE_1D:
54 return V_009910_ARRAY_1D_TILED_THIN1;
55 case RADEON_SURF_MODE_2D:
56 return V_009910_ARRAY_2D_TILED_THIN1;
57 default:
58 case RADEON_SURF_MODE_LINEAR:
59 return V_009910_ARRAY_LINEAR_GENERAL;
60 }
61 }
62
63 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
64 {
65 if (sscreen->b.chip_class >= CIK &&
66 sscreen->b.info.cik_macrotile_mode_array_valid) {
67 unsigned index, tileb;
68
69 tileb = 8 * 8 * tex->surface.bpe;
70 tileb = MIN2(tex->surface.tile_split, tileb);
71
72 for (index = 0; tileb > 64; index++) {
73 tileb >>= 1;
74 }
75 assert(index < 16);
76
77 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
78 }
79
80 if (sscreen->b.chip_class == SI &&
81 sscreen->b.info.si_tile_mode_array_valid) {
82 /* Don't use stencil_tiling_index, because num_banks is always
83 * read from the depth mode. */
84 unsigned tile_mode_index = tex->surface.tiling_index[0];
85 assert(tile_mode_index < 32);
86
87 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
88 }
89
90 /* The old way. */
91 switch (sscreen->b.tiling_info.num_banks) {
92 case 2:
93 return V_02803C_ADDR_SURF_2_BANK;
94 case 4:
95 return V_02803C_ADDR_SURF_4_BANK;
96 case 8:
97 default:
98 return V_02803C_ADDR_SURF_8_BANK;
99 case 16:
100 return V_02803C_ADDR_SURF_16_BANK;
101 }
102 }
103
104 unsigned cik_tile_split(unsigned tile_split)
105 {
106 switch (tile_split) {
107 case 64:
108 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
109 break;
110 case 128:
111 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
112 break;
113 case 256:
114 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
115 break;
116 case 512:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
118 break;
119 default:
120 case 1024:
121 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
122 break;
123 case 2048:
124 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
125 break;
126 case 4096:
127 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
128 break;
129 }
130 return tile_split;
131 }
132
133 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
134 {
135 switch (macro_tile_aspect) {
136 default:
137 case 1:
138 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
139 break;
140 case 2:
141 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
142 break;
143 case 4:
144 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
145 break;
146 case 8:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
148 break;
149 }
150 return macro_tile_aspect;
151 }
152
153 unsigned cik_bank_wh(unsigned bankwh)
154 {
155 switch (bankwh) {
156 default:
157 case 1:
158 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
159 break;
160 case 2:
161 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
162 break;
163 case 4:
164 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
165 break;
166 case 8:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
168 break;
169 }
170 return bankwh;
171 }
172
173 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
174 {
175 if (sscreen->b.info.si_tile_mode_array_valid) {
176 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
177
178 return G_009910_PIPE_CONFIG(gb_tile_mode);
179 }
180
181 /* This is probably broken for a lot of chips, but it's only used
182 * if the kernel cannot return the tile mode array for CIK. */
183 switch (sscreen->b.info.r600_num_tile_pipes) {
184 case 16:
185 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
186 case 8:
187 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
188 case 4:
189 default:
190 if (sscreen->b.info.r600_num_backends == 4)
191 return V_02803C_X_ADDR_SURF_P4_16X16;
192 else
193 return V_02803C_X_ADDR_SURF_P4_8X16;
194 case 2:
195 return V_02803C_ADDR_SURF_P2;
196 }
197 }
198
199 static unsigned si_map_swizzle(unsigned swizzle)
200 {
201 switch (swizzle) {
202 case UTIL_FORMAT_SWIZZLE_Y:
203 return V_008F0C_SQ_SEL_Y;
204 case UTIL_FORMAT_SWIZZLE_Z:
205 return V_008F0C_SQ_SEL_Z;
206 case UTIL_FORMAT_SWIZZLE_W:
207 return V_008F0C_SQ_SEL_W;
208 case UTIL_FORMAT_SWIZZLE_0:
209 return V_008F0C_SQ_SEL_0;
210 case UTIL_FORMAT_SWIZZLE_1:
211 return V_008F0C_SQ_SEL_1;
212 default: /* UTIL_FORMAT_SWIZZLE_X */
213 return V_008F0C_SQ_SEL_X;
214 }
215 }
216
217 static uint32_t S_FIXED(float value, uint32_t frac_bits)
218 {
219 return value * (1 << frac_bits);
220 }
221
222 /* 12.4 fixed-point */
223 static unsigned si_pack_float_12p4(float x)
224 {
225 return x <= 0 ? 0 :
226 x >= 4096 ? 0xffff : x * 16;
227 }
228
229 /*
230 * Inferred framebuffer and blender state.
231 *
232 * One of the reasons this must be derived from the framebuffer state is that:
233 * - The blend state mask is 0xf most of the time.
234 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
235 * so COLOR1 is enabled pretty much all the time.
236 * So CB_TARGET_MASK is the only register that can disable COLOR1.
237 *
238 * Another reason is to avoid a hang with dual source blending.
239 */
240 void si_update_fb_blend_state(struct si_context *sctx)
241 {
242 struct si_pm4_state *pm4;
243 struct si_state_blend *blend = sctx->queued.named.blend;
244 uint32_t mask = 0, i;
245
246 if (blend == NULL)
247 return;
248
249 pm4 = CALLOC_STRUCT(si_pm4_state);
250 if (pm4 == NULL)
251 return;
252
253 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
254 if (sctx->framebuffer.state.cbufs[i])
255 mask |= 0xf << (4*i);
256 mask &= blend->cb_target_mask;
257
258 /* Avoid a hang that happens when dual source blending is enabled
259 * but there is not enough color outputs. This is undefined behavior,
260 * so disable color writes completely.
261 *
262 * Reproducible with Unigine Heaven 4.0 and drirc missing.
263 */
264 if (blend->dual_src_blend &&
265 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
266 mask = 0;
267
268 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
269 si_pm4_set_state(sctx, fb_blend, pm4);
270 }
271
272 /*
273 * Blender functions
274 */
275
276 static uint32_t si_translate_blend_function(int blend_func)
277 {
278 switch (blend_func) {
279 case PIPE_BLEND_ADD:
280 return V_028780_COMB_DST_PLUS_SRC;
281 case PIPE_BLEND_SUBTRACT:
282 return V_028780_COMB_SRC_MINUS_DST;
283 case PIPE_BLEND_REVERSE_SUBTRACT:
284 return V_028780_COMB_DST_MINUS_SRC;
285 case PIPE_BLEND_MIN:
286 return V_028780_COMB_MIN_DST_SRC;
287 case PIPE_BLEND_MAX:
288 return V_028780_COMB_MAX_DST_SRC;
289 default:
290 R600_ERR("Unknown blend function %d\n", blend_func);
291 assert(0);
292 break;
293 }
294 return 0;
295 }
296
297 static uint32_t si_translate_blend_factor(int blend_fact)
298 {
299 switch (blend_fact) {
300 case PIPE_BLENDFACTOR_ONE:
301 return V_028780_BLEND_ONE;
302 case PIPE_BLENDFACTOR_SRC_COLOR:
303 return V_028780_BLEND_SRC_COLOR;
304 case PIPE_BLENDFACTOR_SRC_ALPHA:
305 return V_028780_BLEND_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_DST_ALPHA:
307 return V_028780_BLEND_DST_ALPHA;
308 case PIPE_BLENDFACTOR_DST_COLOR:
309 return V_028780_BLEND_DST_COLOR;
310 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
311 return V_028780_BLEND_SRC_ALPHA_SATURATE;
312 case PIPE_BLENDFACTOR_CONST_COLOR:
313 return V_028780_BLEND_CONSTANT_COLOR;
314 case PIPE_BLENDFACTOR_CONST_ALPHA:
315 return V_028780_BLEND_CONSTANT_ALPHA;
316 case PIPE_BLENDFACTOR_ZERO:
317 return V_028780_BLEND_ZERO;
318 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
319 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
322 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
323 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
324 case PIPE_BLENDFACTOR_INV_DST_COLOR:
325 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
326 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
327 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
328 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
329 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
330 case PIPE_BLENDFACTOR_SRC1_COLOR:
331 return V_028780_BLEND_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_SRC1_ALPHA:
333 return V_028780_BLEND_SRC1_ALPHA;
334 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
335 return V_028780_BLEND_INV_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
337 return V_028780_BLEND_INV_SRC1_ALPHA;
338 default:
339 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
340 assert(0);
341 break;
342 }
343 return 0;
344 }
345
346 static void *si_create_blend_state_mode(struct pipe_context *ctx,
347 const struct pipe_blend_state *state,
348 unsigned mode)
349 {
350 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
351 struct si_pm4_state *pm4 = &blend->pm4;
352
353 uint32_t color_control = 0;
354
355 if (blend == NULL)
356 return NULL;
357
358 blend->alpha_to_one = state->alpha_to_one;
359 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
360
361 if (state->logicop_enable) {
362 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
363 } else {
364 color_control |= S_028808_ROP3(0xcc);
365 }
366
367 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
368 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
369 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
370 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
371 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
372 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
373
374 blend->cb_target_mask = 0;
375 for (int i = 0; i < 8; i++) {
376 /* state->rt entries > 0 only written if independent blending */
377 const int j = state->independent_blend_enable ? i : 0;
378
379 unsigned eqRGB = state->rt[j].rgb_func;
380 unsigned srcRGB = state->rt[j].rgb_src_factor;
381 unsigned dstRGB = state->rt[j].rgb_dst_factor;
382 unsigned eqA = state->rt[j].alpha_func;
383 unsigned srcA = state->rt[j].alpha_src_factor;
384 unsigned dstA = state->rt[j].alpha_dst_factor;
385
386 unsigned blend_cntl = 0;
387
388 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
389 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
390
391 if (!state->rt[j].blend_enable) {
392 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
393 continue;
394 }
395
396 blend_cntl |= S_028780_ENABLE(1);
397 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
398 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
399 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
400
401 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
402 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
403 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
404 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
405 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
406 }
407 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
408 }
409
410 if (blend->cb_target_mask) {
411 color_control |= S_028808_MODE(mode);
412 } else {
413 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
414 }
415 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
416
417 return blend;
418 }
419
420 static void *si_create_blend_state(struct pipe_context *ctx,
421 const struct pipe_blend_state *state)
422 {
423 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
424 }
425
426 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
427 {
428 struct si_context *sctx = (struct si_context *)ctx;
429 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
430 si_update_fb_blend_state(sctx);
431 }
432
433 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
434 {
435 struct si_context *sctx = (struct si_context *)ctx;
436 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
437 }
438
439 static void si_set_blend_color(struct pipe_context *ctx,
440 const struct pipe_blend_color *state)
441 {
442 struct si_context *sctx = (struct si_context *)ctx;
443 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
444
445 if (pm4 == NULL)
446 return;
447
448 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
449 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
450 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
451 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
452
453 si_pm4_set_state(sctx, blend_color, pm4);
454 }
455
456 /*
457 * Clipping, scissors and viewport
458 */
459
460 static void si_set_clip_state(struct pipe_context *ctx,
461 const struct pipe_clip_state *state)
462 {
463 struct si_context *sctx = (struct si_context *)ctx;
464 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
465 struct pipe_constant_buffer cb;
466
467 if (pm4 == NULL)
468 return;
469
470 for (int i = 0; i < 6; i++) {
471 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
472 fui(state->ucp[i][0]));
473 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
474 fui(state->ucp[i][1]));
475 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
476 fui(state->ucp[i][2]));
477 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
478 fui(state->ucp[i][3]));
479 }
480
481 cb.buffer = NULL;
482 cb.user_buffer = state->ucp;
483 cb.buffer_offset = 0;
484 cb.buffer_size = 4*4*8;
485 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
486 pipe_resource_reference(&cb.buffer, NULL);
487
488 si_pm4_set_state(sctx, clip, pm4);
489 }
490
491 #define SIX_BITS 0x3F
492
493 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
494 {
495 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
496 struct tgsi_shader_info *info = si_get_vs_info(sctx);
497 unsigned window_space =
498 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
499 unsigned clipdist_mask =
500 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
501
502 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
503 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
504 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
505 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
506 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
507 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
508 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
509 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
510 info->writes_edgeflag ||
511 info->writes_layer ||
512 info->writes_viewport_index) |
513 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
514 (sctx->queued.named.rasterizer->clip_plane_enable &
515 clipdist_mask));
516 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
517 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
518 (clipdist_mask ? 0 :
519 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
520 S_028810_CLIP_DISABLE(window_space));
521 }
522
523 static void si_set_scissor_states(struct pipe_context *ctx,
524 unsigned start_slot,
525 unsigned num_scissors,
526 const struct pipe_scissor_state *state)
527 {
528 struct si_context *sctx = (struct si_context *)ctx;
529 int i;
530
531 for (i = 0; i < num_scissors; i++)
532 sctx->scissors.states[start_slot + i] = state[i];
533
534 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
535 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
536 }
537
538 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
539 {
540 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
541 struct pipe_scissor_state *states = sctx->scissors.states;
542 unsigned mask = sctx->scissors.dirty_mask;
543
544 /* The simple case: Only 1 viewport is active. */
545 if (mask & 1 &&
546 !si_get_vs_info(sctx)->writes_viewport_index) {
547 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
548 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
549 S_028250_TL_Y(states[0].miny) |
550 S_028250_WINDOW_OFFSET_DISABLE(1));
551 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
552 S_028254_BR_Y(states[0].maxy));
553 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
554 return;
555 }
556
557 while (mask) {
558 int start, count, i;
559
560 u_bit_scan_consecutive_range(&mask, &start, &count);
561
562 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
563 start * 4 * 2, count * 2);
564 for (i = start; i < start+count; i++) {
565 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
566 S_028250_TL_Y(states[i].miny) |
567 S_028250_WINDOW_OFFSET_DISABLE(1));
568 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
569 S_028254_BR_Y(states[i].maxy));
570 }
571 }
572 sctx->scissors.dirty_mask = 0;
573 }
574
575 static void si_set_viewport_states(struct pipe_context *ctx,
576 unsigned start_slot,
577 unsigned num_viewports,
578 const struct pipe_viewport_state *state)
579 {
580 struct si_context *sctx = (struct si_context *)ctx;
581 struct si_state_viewport *viewport;
582 struct si_pm4_state *pm4;
583 int i;
584
585 for (i = start_slot; i < start_slot + num_viewports; i++) {
586 int idx = i - start_slot;
587 int offset = i * 4 * 6;
588
589 viewport = CALLOC_STRUCT(si_state_viewport);
590 if (!viewport)
591 return;
592 pm4 = &viewport->pm4;
593
594 viewport->viewport = state[idx];
595 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE + offset, fui(state[idx].scale[0]));
596 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET + offset, fui(state[idx].translate[0]));
597 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE + offset, fui(state[idx].scale[1]));
598 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET + offset, fui(state[idx].translate[1]));
599 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE + offset, fui(state[idx].scale[2]));
600 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET + offset, fui(state[idx].translate[2]));
601
602 si_pm4_set_state(sctx, viewport[i], viewport);
603 }
604 }
605
606 /*
607 * inferred state between framebuffer and rasterizer
608 */
609 static void si_update_fb_rs_state(struct si_context *sctx)
610 {
611 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
612 struct si_pm4_state *pm4;
613 float offset_units;
614
615 if (!rs || !sctx->framebuffer.state.zsbuf)
616 return;
617
618 offset_units = sctx->queued.named.rasterizer->offset_units;
619 switch (sctx->framebuffer.state.zsbuf->texture->format) {
620 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
621 case PIPE_FORMAT_X8Z24_UNORM:
622 case PIPE_FORMAT_Z24X8_UNORM:
623 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
624 offset_units *= 2.0f;
625 break;
626 case PIPE_FORMAT_Z32_FLOAT:
627 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
628 offset_units *= 1.0f;
629 break;
630 case PIPE_FORMAT_Z16_UNORM:
631 offset_units *= 4.0f;
632 break;
633 default:
634 return;
635 }
636
637 pm4 = CALLOC_STRUCT(si_pm4_state);
638
639 if (pm4 == NULL)
640 return;
641
642 /* FIXME some of those reg can be computed with cso */
643 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
644 fui(sctx->queued.named.rasterizer->offset_scale));
645 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
646 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
647 fui(sctx->queued.named.rasterizer->offset_scale));
648 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
649
650 si_pm4_set_state(sctx, fb_rs, pm4);
651 }
652
653 /*
654 * Rasterizer
655 */
656
657 static uint32_t si_translate_fill(uint32_t func)
658 {
659 switch(func) {
660 case PIPE_POLYGON_MODE_FILL:
661 return V_028814_X_DRAW_TRIANGLES;
662 case PIPE_POLYGON_MODE_LINE:
663 return V_028814_X_DRAW_LINES;
664 case PIPE_POLYGON_MODE_POINT:
665 return V_028814_X_DRAW_POINTS;
666 default:
667 assert(0);
668 return V_028814_X_DRAW_POINTS;
669 }
670 }
671
672 static void *si_create_rs_state(struct pipe_context *ctx,
673 const struct pipe_rasterizer_state *state)
674 {
675 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
676 struct si_pm4_state *pm4 = &rs->pm4;
677 unsigned tmp;
678 float psize_min, psize_max;
679
680 if (rs == NULL) {
681 return NULL;
682 }
683
684 rs->two_side = state->light_twoside;
685 rs->multisample_enable = state->multisample;
686 rs->clip_plane_enable = state->clip_plane_enable;
687 rs->line_stipple_enable = state->line_stipple_enable;
688 rs->poly_stipple_enable = state->poly_stipple_enable;
689 rs->line_smooth = state->line_smooth;
690 rs->poly_smooth = state->poly_smooth;
691
692 rs->flatshade = state->flatshade;
693 rs->sprite_coord_enable = state->sprite_coord_enable;
694 rs->pa_sc_line_stipple = state->line_stipple_enable ?
695 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
696 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
697 rs->pa_cl_clip_cntl =
698 S_028810_PS_UCP_MODE(3) |
699 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
700 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
701 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
702 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
703 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
704
705 /* offset */
706 rs->offset_units = state->offset_units;
707 rs->offset_scale = state->offset_scale * 16.0f;
708
709 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
710 S_0286D4_FLAT_SHADE_ENA(1) |
711 S_0286D4_PNT_SPRITE_ENA(1) |
712 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
713 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
714 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
715 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
716 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
717
718 /* point size 12.4 fixed point */
719 tmp = (unsigned)(state->point_size * 8.0);
720 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
721
722 if (state->point_size_per_vertex) {
723 psize_min = util_get_min_point_size(state);
724 psize_max = 8192;
725 } else {
726 /* Force the point size to be as if the vertex output was disabled. */
727 psize_min = state->point_size;
728 psize_max = state->point_size;
729 }
730 /* Divide by two, because 0.5 = 1 pixel. */
731 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
732 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
733 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
734
735 tmp = (unsigned)state->line_width * 8;
736 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
737 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
738 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
739 S_028A48_MSAA_ENABLE(state->multisample ||
740 state->poly_smooth ||
741 state->line_smooth) |
742 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
743
744 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
745 S_028BE4_PIX_CENTER(state->half_pixel_center) |
746 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
747
748 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
749 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
750 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
751 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
752 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
753 S_028814_FACE(!state->front_ccw) |
754 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
755 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
756 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
757 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
758 state->fill_back != PIPE_POLYGON_MODE_FILL) |
759 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
760 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
761 return rs;
762 }
763
764 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
765 {
766 struct si_context *sctx = (struct si_context *)ctx;
767 struct si_state_rasterizer *old_rs =
768 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
769 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
770
771 if (state == NULL)
772 return;
773
774 if (sctx->framebuffer.nr_samples > 1 &&
775 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
776 si_mark_atom_dirty(sctx, &sctx->db_render_state);
777
778 si_pm4_bind_state(sctx, rasterizer, rs);
779 si_update_fb_rs_state(sctx);
780
781 si_mark_atom_dirty(sctx, &sctx->clip_regs);
782 }
783
784 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
785 {
786 struct si_context *sctx = (struct si_context *)ctx;
787 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
788 }
789
790 /*
791 * infeered state between dsa and stencil ref
792 */
793 static void si_update_dsa_stencil_ref(struct si_context *sctx)
794 {
795 struct si_pm4_state *pm4;
796 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
797 struct si_state_dsa *dsa = sctx->queued.named.dsa;
798
799 if (!dsa)
800 return;
801
802 pm4 = CALLOC_STRUCT(si_pm4_state);
803 if (pm4 == NULL)
804 return;
805
806 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
807 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
808 S_028430_STENCILMASK(dsa->valuemask[0]) |
809 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
810 S_028430_STENCILOPVAL(1));
811 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
812 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
813 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
814 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
815 S_028434_STENCILOPVAL_BF(1));
816
817 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
818 }
819
820 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
821 const struct pipe_stencil_ref *state)
822 {
823 struct si_context *sctx = (struct si_context *)ctx;
824 sctx->stencil_ref = *state;
825 si_update_dsa_stencil_ref(sctx);
826 }
827
828
829 /*
830 * DSA
831 */
832
833 static uint32_t si_translate_stencil_op(int s_op)
834 {
835 switch (s_op) {
836 case PIPE_STENCIL_OP_KEEP:
837 return V_02842C_STENCIL_KEEP;
838 case PIPE_STENCIL_OP_ZERO:
839 return V_02842C_STENCIL_ZERO;
840 case PIPE_STENCIL_OP_REPLACE:
841 return V_02842C_STENCIL_REPLACE_TEST;
842 case PIPE_STENCIL_OP_INCR:
843 return V_02842C_STENCIL_ADD_CLAMP;
844 case PIPE_STENCIL_OP_DECR:
845 return V_02842C_STENCIL_SUB_CLAMP;
846 case PIPE_STENCIL_OP_INCR_WRAP:
847 return V_02842C_STENCIL_ADD_WRAP;
848 case PIPE_STENCIL_OP_DECR_WRAP:
849 return V_02842C_STENCIL_SUB_WRAP;
850 case PIPE_STENCIL_OP_INVERT:
851 return V_02842C_STENCIL_INVERT;
852 default:
853 R600_ERR("Unknown stencil op %d", s_op);
854 assert(0);
855 break;
856 }
857 return 0;
858 }
859
860 static void *si_create_dsa_state(struct pipe_context *ctx,
861 const struct pipe_depth_stencil_alpha_state *state)
862 {
863 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
864 struct si_pm4_state *pm4 = &dsa->pm4;
865 unsigned db_depth_control;
866 uint32_t db_stencil_control = 0;
867
868 if (dsa == NULL) {
869 return NULL;
870 }
871
872 dsa->valuemask[0] = state->stencil[0].valuemask;
873 dsa->valuemask[1] = state->stencil[1].valuemask;
874 dsa->writemask[0] = state->stencil[0].writemask;
875 dsa->writemask[1] = state->stencil[1].writemask;
876
877 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
878 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
879 S_028800_ZFUNC(state->depth.func) |
880 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
881
882 /* stencil */
883 if (state->stencil[0].enabled) {
884 db_depth_control |= S_028800_STENCIL_ENABLE(1);
885 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
886 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
887 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
888 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
889
890 if (state->stencil[1].enabled) {
891 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
892 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
893 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
894 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
895 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
896 }
897 }
898
899 /* alpha */
900 if (state->alpha.enabled) {
901 dsa->alpha_func = state->alpha.func;
902
903 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
904 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
905 } else {
906 dsa->alpha_func = PIPE_FUNC_ALWAYS;
907 }
908
909 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
910 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
911 if (state->depth.bounds_test) {
912 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
913 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
914 }
915
916 return dsa;
917 }
918
919 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
920 {
921 struct si_context *sctx = (struct si_context *)ctx;
922 struct si_state_dsa *dsa = state;
923
924 if (state == NULL)
925 return;
926
927 si_pm4_bind_state(sctx, dsa, dsa);
928 si_update_dsa_stencil_ref(sctx);
929 }
930
931 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
932 {
933 struct si_context *sctx = (struct si_context *)ctx;
934 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
935 }
936
937 static void *si_create_db_flush_dsa(struct si_context *sctx)
938 {
939 struct pipe_depth_stencil_alpha_state dsa = {};
940
941 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
942 }
943
944 /* DB RENDER STATE */
945
946 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
947 {
948 struct si_context *sctx = (struct si_context*)ctx;
949
950 si_mark_atom_dirty(sctx, &sctx->db_render_state);
951 }
952
953 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
954 {
955 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
956 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
957 unsigned db_shader_control;
958
959 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
960
961 /* DB_RENDER_CONTROL */
962 if (sctx->dbcb_depth_copy_enabled ||
963 sctx->dbcb_stencil_copy_enabled) {
964 radeon_emit(cs,
965 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
966 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
967 S_028000_COPY_CENTROID(1) |
968 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
969 } else if (sctx->db_inplace_flush_enabled) {
970 radeon_emit(cs,
971 S_028000_DEPTH_COMPRESS_DISABLE(1) |
972 S_028000_STENCIL_COMPRESS_DISABLE(1));
973 } else if (sctx->db_depth_clear) {
974 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
975 } else {
976 radeon_emit(cs, 0);
977 }
978
979 /* DB_COUNT_CONTROL (occlusion queries) */
980 if (sctx->b.num_occlusion_queries > 0) {
981 if (sctx->b.chip_class >= CIK) {
982 radeon_emit(cs,
983 S_028004_PERFECT_ZPASS_COUNTS(1) |
984 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
985 S_028004_ZPASS_ENABLE(1) |
986 S_028004_SLICE_EVEN_ENABLE(1) |
987 S_028004_SLICE_ODD_ENABLE(1));
988 } else {
989 radeon_emit(cs,
990 S_028004_PERFECT_ZPASS_COUNTS(1) |
991 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
992 }
993 } else {
994 /* Disable occlusion queries. */
995 if (sctx->b.chip_class >= CIK) {
996 radeon_emit(cs, 0);
997 } else {
998 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
999 }
1000 }
1001
1002 /* DB_RENDER_OVERRIDE2 */
1003 if (sctx->db_depth_disable_expclear) {
1004 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1005 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1006 } else {
1007 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1008 }
1009
1010 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1011 sctx->ps_db_shader_control;
1012
1013 /* Bug workaround for smoothing (overrasterization) on SI. */
1014 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1015 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1016 else
1017 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1018
1019 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1020 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1021 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1022
1023 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1024 db_shader_control);
1025 }
1026
1027 /*
1028 * format translation
1029 */
1030 static uint32_t si_translate_colorformat(enum pipe_format format)
1031 {
1032 const struct util_format_description *desc = util_format_description(format);
1033
1034 #define HAS_SIZE(x,y,z,w) \
1035 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1036 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1037
1038 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1039 return V_028C70_COLOR_10_11_11;
1040
1041 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1042 return V_028C70_COLOR_INVALID;
1043
1044 switch (desc->nr_channels) {
1045 case 1:
1046 switch (desc->channel[0].size) {
1047 case 8:
1048 return V_028C70_COLOR_8;
1049 case 16:
1050 return V_028C70_COLOR_16;
1051 case 32:
1052 return V_028C70_COLOR_32;
1053 }
1054 break;
1055 case 2:
1056 if (desc->channel[0].size == desc->channel[1].size) {
1057 switch (desc->channel[0].size) {
1058 case 8:
1059 return V_028C70_COLOR_8_8;
1060 case 16:
1061 return V_028C70_COLOR_16_16;
1062 case 32:
1063 return V_028C70_COLOR_32_32;
1064 }
1065 } else if (HAS_SIZE(8,24,0,0)) {
1066 return V_028C70_COLOR_24_8;
1067 } else if (HAS_SIZE(24,8,0,0)) {
1068 return V_028C70_COLOR_8_24;
1069 }
1070 break;
1071 case 3:
1072 if (HAS_SIZE(5,6,5,0)) {
1073 return V_028C70_COLOR_5_6_5;
1074 } else if (HAS_SIZE(32,8,24,0)) {
1075 return V_028C70_COLOR_X24_8_32_FLOAT;
1076 }
1077 break;
1078 case 4:
1079 if (desc->channel[0].size == desc->channel[1].size &&
1080 desc->channel[0].size == desc->channel[2].size &&
1081 desc->channel[0].size == desc->channel[3].size) {
1082 switch (desc->channel[0].size) {
1083 case 4:
1084 return V_028C70_COLOR_4_4_4_4;
1085 case 8:
1086 return V_028C70_COLOR_8_8_8_8;
1087 case 16:
1088 return V_028C70_COLOR_16_16_16_16;
1089 case 32:
1090 return V_028C70_COLOR_32_32_32_32;
1091 }
1092 } else if (HAS_SIZE(5,5,5,1)) {
1093 return V_028C70_COLOR_1_5_5_5;
1094 } else if (HAS_SIZE(10,10,10,2)) {
1095 return V_028C70_COLOR_2_10_10_10;
1096 }
1097 break;
1098 }
1099 return V_028C70_COLOR_INVALID;
1100 }
1101
1102 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1103 {
1104 if (SI_BIG_ENDIAN) {
1105 switch(colorformat) {
1106 /* 8-bit buffers. */
1107 case V_028C70_COLOR_8:
1108 return V_028C70_ENDIAN_NONE;
1109
1110 /* 16-bit buffers. */
1111 case V_028C70_COLOR_5_6_5:
1112 case V_028C70_COLOR_1_5_5_5:
1113 case V_028C70_COLOR_4_4_4_4:
1114 case V_028C70_COLOR_16:
1115 case V_028C70_COLOR_8_8:
1116 return V_028C70_ENDIAN_8IN16;
1117
1118 /* 32-bit buffers. */
1119 case V_028C70_COLOR_8_8_8_8:
1120 case V_028C70_COLOR_2_10_10_10:
1121 case V_028C70_COLOR_8_24:
1122 case V_028C70_COLOR_24_8:
1123 case V_028C70_COLOR_16_16:
1124 return V_028C70_ENDIAN_8IN32;
1125
1126 /* 64-bit buffers. */
1127 case V_028C70_COLOR_16_16_16_16:
1128 return V_028C70_ENDIAN_8IN16;
1129
1130 case V_028C70_COLOR_32_32:
1131 return V_028C70_ENDIAN_8IN32;
1132
1133 /* 128-bit buffers. */
1134 case V_028C70_COLOR_32_32_32_32:
1135 return V_028C70_ENDIAN_8IN32;
1136 default:
1137 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1138 }
1139 } else {
1140 return V_028C70_ENDIAN_NONE;
1141 }
1142 }
1143
1144 /* Returns the size in bits of the widest component of a CB format */
1145 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1146 {
1147 switch(colorformat) {
1148 case V_028C70_COLOR_4_4_4_4:
1149 return 4;
1150
1151 case V_028C70_COLOR_1_5_5_5:
1152 case V_028C70_COLOR_5_5_5_1:
1153 return 5;
1154
1155 case V_028C70_COLOR_5_6_5:
1156 return 6;
1157
1158 case V_028C70_COLOR_8:
1159 case V_028C70_COLOR_8_8:
1160 case V_028C70_COLOR_8_8_8_8:
1161 return 8;
1162
1163 case V_028C70_COLOR_10_10_10_2:
1164 case V_028C70_COLOR_2_10_10_10:
1165 return 10;
1166
1167 case V_028C70_COLOR_10_11_11:
1168 case V_028C70_COLOR_11_11_10:
1169 return 11;
1170
1171 case V_028C70_COLOR_16:
1172 case V_028C70_COLOR_16_16:
1173 case V_028C70_COLOR_16_16_16_16:
1174 return 16;
1175
1176 case V_028C70_COLOR_8_24:
1177 case V_028C70_COLOR_24_8:
1178 return 24;
1179
1180 case V_028C70_COLOR_32:
1181 case V_028C70_COLOR_32_32:
1182 case V_028C70_COLOR_32_32_32_32:
1183 case V_028C70_COLOR_X24_8_32_FLOAT:
1184 return 32;
1185 }
1186
1187 assert(!"Unknown maximum component size");
1188 return 0;
1189 }
1190
1191 static uint32_t si_translate_dbformat(enum pipe_format format)
1192 {
1193 switch (format) {
1194 case PIPE_FORMAT_Z16_UNORM:
1195 return V_028040_Z_16;
1196 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1197 case PIPE_FORMAT_X8Z24_UNORM:
1198 case PIPE_FORMAT_Z24X8_UNORM:
1199 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1200 return V_028040_Z_24; /* deprecated on SI */
1201 case PIPE_FORMAT_Z32_FLOAT:
1202 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1203 return V_028040_Z_32_FLOAT;
1204 default:
1205 return V_028040_Z_INVALID;
1206 }
1207 }
1208
1209 /*
1210 * Texture translation
1211 */
1212
1213 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1214 enum pipe_format format,
1215 const struct util_format_description *desc,
1216 int first_non_void)
1217 {
1218 struct si_screen *sscreen = (struct si_screen*)screen;
1219 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1220 sscreen->b.info.drm_minor >= 31) ||
1221 sscreen->b.info.drm_major == 3;
1222 boolean uniform = TRUE;
1223 int i;
1224
1225 /* Colorspace (return non-RGB formats directly). */
1226 switch (desc->colorspace) {
1227 /* Depth stencil formats */
1228 case UTIL_FORMAT_COLORSPACE_ZS:
1229 switch (format) {
1230 case PIPE_FORMAT_Z16_UNORM:
1231 return V_008F14_IMG_DATA_FORMAT_16;
1232 case PIPE_FORMAT_X24S8_UINT:
1233 case PIPE_FORMAT_Z24X8_UNORM:
1234 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1235 return V_008F14_IMG_DATA_FORMAT_8_24;
1236 case PIPE_FORMAT_X8Z24_UNORM:
1237 case PIPE_FORMAT_S8X24_UINT:
1238 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1239 return V_008F14_IMG_DATA_FORMAT_24_8;
1240 case PIPE_FORMAT_S8_UINT:
1241 return V_008F14_IMG_DATA_FORMAT_8;
1242 case PIPE_FORMAT_Z32_FLOAT:
1243 return V_008F14_IMG_DATA_FORMAT_32;
1244 case PIPE_FORMAT_X32_S8X24_UINT:
1245 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1246 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1247 default:
1248 goto out_unknown;
1249 }
1250
1251 case UTIL_FORMAT_COLORSPACE_YUV:
1252 goto out_unknown; /* TODO */
1253
1254 case UTIL_FORMAT_COLORSPACE_SRGB:
1255 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1256 goto out_unknown;
1257 break;
1258
1259 default:
1260 break;
1261 }
1262
1263 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1264 if (!enable_compressed_formats)
1265 goto out_unknown;
1266
1267 switch (format) {
1268 case PIPE_FORMAT_RGTC1_SNORM:
1269 case PIPE_FORMAT_LATC1_SNORM:
1270 case PIPE_FORMAT_RGTC1_UNORM:
1271 case PIPE_FORMAT_LATC1_UNORM:
1272 return V_008F14_IMG_DATA_FORMAT_BC4;
1273 case PIPE_FORMAT_RGTC2_SNORM:
1274 case PIPE_FORMAT_LATC2_SNORM:
1275 case PIPE_FORMAT_RGTC2_UNORM:
1276 case PIPE_FORMAT_LATC2_UNORM:
1277 return V_008F14_IMG_DATA_FORMAT_BC5;
1278 default:
1279 goto out_unknown;
1280 }
1281 }
1282
1283 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1284 if (!enable_compressed_formats)
1285 goto out_unknown;
1286
1287 switch (format) {
1288 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1289 case PIPE_FORMAT_BPTC_SRGBA:
1290 return V_008F14_IMG_DATA_FORMAT_BC7;
1291 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1292 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1293 return V_008F14_IMG_DATA_FORMAT_BC6;
1294 default:
1295 goto out_unknown;
1296 }
1297 }
1298
1299 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1300 switch (format) {
1301 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1302 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1303 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1304 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1305 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1306 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1307 default:
1308 goto out_unknown;
1309 }
1310 }
1311
1312 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1313 if (!enable_compressed_formats)
1314 goto out_unknown;
1315
1316 if (!util_format_s3tc_enabled) {
1317 goto out_unknown;
1318 }
1319
1320 switch (format) {
1321 case PIPE_FORMAT_DXT1_RGB:
1322 case PIPE_FORMAT_DXT1_RGBA:
1323 case PIPE_FORMAT_DXT1_SRGB:
1324 case PIPE_FORMAT_DXT1_SRGBA:
1325 return V_008F14_IMG_DATA_FORMAT_BC1;
1326 case PIPE_FORMAT_DXT3_RGBA:
1327 case PIPE_FORMAT_DXT3_SRGBA:
1328 return V_008F14_IMG_DATA_FORMAT_BC2;
1329 case PIPE_FORMAT_DXT5_RGBA:
1330 case PIPE_FORMAT_DXT5_SRGBA:
1331 return V_008F14_IMG_DATA_FORMAT_BC3;
1332 default:
1333 goto out_unknown;
1334 }
1335 }
1336
1337 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1338 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1339 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1340 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1341 }
1342
1343 /* R8G8Bx_SNORM - TODO CxV8U8 */
1344
1345 /* See whether the components are of the same size. */
1346 for (i = 1; i < desc->nr_channels; i++) {
1347 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1348 }
1349
1350 /* Non-uniform formats. */
1351 if (!uniform) {
1352 switch(desc->nr_channels) {
1353 case 3:
1354 if (desc->channel[0].size == 5 &&
1355 desc->channel[1].size == 6 &&
1356 desc->channel[2].size == 5) {
1357 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1358 }
1359 goto out_unknown;
1360 case 4:
1361 if (desc->channel[0].size == 5 &&
1362 desc->channel[1].size == 5 &&
1363 desc->channel[2].size == 5 &&
1364 desc->channel[3].size == 1) {
1365 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1366 }
1367 if (desc->channel[0].size == 10 &&
1368 desc->channel[1].size == 10 &&
1369 desc->channel[2].size == 10 &&
1370 desc->channel[3].size == 2) {
1371 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1372 }
1373 goto out_unknown;
1374 }
1375 goto out_unknown;
1376 }
1377
1378 if (first_non_void < 0 || first_non_void > 3)
1379 goto out_unknown;
1380
1381 /* uniform formats */
1382 switch (desc->channel[first_non_void].size) {
1383 case 4:
1384 switch (desc->nr_channels) {
1385 #if 0 /* Not supported for render targets */
1386 case 2:
1387 return V_008F14_IMG_DATA_FORMAT_4_4;
1388 #endif
1389 case 4:
1390 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1391 }
1392 break;
1393 case 8:
1394 switch (desc->nr_channels) {
1395 case 1:
1396 return V_008F14_IMG_DATA_FORMAT_8;
1397 case 2:
1398 return V_008F14_IMG_DATA_FORMAT_8_8;
1399 case 4:
1400 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1401 }
1402 break;
1403 case 16:
1404 switch (desc->nr_channels) {
1405 case 1:
1406 return V_008F14_IMG_DATA_FORMAT_16;
1407 case 2:
1408 return V_008F14_IMG_DATA_FORMAT_16_16;
1409 case 4:
1410 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1411 }
1412 break;
1413 case 32:
1414 switch (desc->nr_channels) {
1415 case 1:
1416 return V_008F14_IMG_DATA_FORMAT_32;
1417 case 2:
1418 return V_008F14_IMG_DATA_FORMAT_32_32;
1419 #if 0 /* Not supported for render targets */
1420 case 3:
1421 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1422 #endif
1423 case 4:
1424 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1425 }
1426 }
1427
1428 out_unknown:
1429 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1430 return ~0;
1431 }
1432
1433 static unsigned si_tex_wrap(unsigned wrap)
1434 {
1435 switch (wrap) {
1436 default:
1437 case PIPE_TEX_WRAP_REPEAT:
1438 return V_008F30_SQ_TEX_WRAP;
1439 case PIPE_TEX_WRAP_CLAMP:
1440 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1441 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1442 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1443 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1444 return V_008F30_SQ_TEX_CLAMP_BORDER;
1445 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1446 return V_008F30_SQ_TEX_MIRROR;
1447 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1448 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1449 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1450 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1451 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1452 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1453 }
1454 }
1455
1456 static unsigned si_tex_filter(unsigned filter)
1457 {
1458 switch (filter) {
1459 default:
1460 case PIPE_TEX_FILTER_NEAREST:
1461 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1462 case PIPE_TEX_FILTER_LINEAR:
1463 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1464 }
1465 }
1466
1467 static unsigned si_tex_mipfilter(unsigned filter)
1468 {
1469 switch (filter) {
1470 case PIPE_TEX_MIPFILTER_NEAREST:
1471 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1472 case PIPE_TEX_MIPFILTER_LINEAR:
1473 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1474 default:
1475 case PIPE_TEX_MIPFILTER_NONE:
1476 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1477 }
1478 }
1479
1480 static unsigned si_tex_compare(unsigned compare)
1481 {
1482 switch (compare) {
1483 default:
1484 case PIPE_FUNC_NEVER:
1485 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1486 case PIPE_FUNC_LESS:
1487 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1488 case PIPE_FUNC_EQUAL:
1489 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1490 case PIPE_FUNC_LEQUAL:
1491 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1492 case PIPE_FUNC_GREATER:
1493 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1494 case PIPE_FUNC_NOTEQUAL:
1495 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1496 case PIPE_FUNC_GEQUAL:
1497 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1498 case PIPE_FUNC_ALWAYS:
1499 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1500 }
1501 }
1502
1503 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1504 {
1505 switch (dim) {
1506 default:
1507 case PIPE_TEXTURE_1D:
1508 return V_008F1C_SQ_RSRC_IMG_1D;
1509 case PIPE_TEXTURE_1D_ARRAY:
1510 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1511 case PIPE_TEXTURE_2D:
1512 case PIPE_TEXTURE_RECT:
1513 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1514 V_008F1C_SQ_RSRC_IMG_2D;
1515 case PIPE_TEXTURE_2D_ARRAY:
1516 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1517 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1518 case PIPE_TEXTURE_3D:
1519 return V_008F1C_SQ_RSRC_IMG_3D;
1520 case PIPE_TEXTURE_CUBE:
1521 case PIPE_TEXTURE_CUBE_ARRAY:
1522 return V_008F1C_SQ_RSRC_IMG_CUBE;
1523 }
1524 }
1525
1526 /*
1527 * Format support testing
1528 */
1529
1530 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1531 {
1532 return si_translate_texformat(screen, format, util_format_description(format),
1533 util_format_get_first_non_void_channel(format)) != ~0U;
1534 }
1535
1536 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1537 const struct util_format_description *desc,
1538 int first_non_void)
1539 {
1540 unsigned type = desc->channel[first_non_void].type;
1541 int i;
1542
1543 if (type == UTIL_FORMAT_TYPE_FIXED)
1544 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1545
1546 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1547 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1548
1549 if (desc->nr_channels == 4 &&
1550 desc->channel[0].size == 10 &&
1551 desc->channel[1].size == 10 &&
1552 desc->channel[2].size == 10 &&
1553 desc->channel[3].size == 2)
1554 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1555
1556 /* See whether the components are of the same size. */
1557 for (i = 0; i < desc->nr_channels; i++) {
1558 if (desc->channel[first_non_void].size != desc->channel[i].size)
1559 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1560 }
1561
1562 switch (desc->channel[first_non_void].size) {
1563 case 8:
1564 switch (desc->nr_channels) {
1565 case 1:
1566 return V_008F0C_BUF_DATA_FORMAT_8;
1567 case 2:
1568 return V_008F0C_BUF_DATA_FORMAT_8_8;
1569 case 3:
1570 case 4:
1571 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1572 }
1573 break;
1574 case 16:
1575 switch (desc->nr_channels) {
1576 case 1:
1577 return V_008F0C_BUF_DATA_FORMAT_16;
1578 case 2:
1579 return V_008F0C_BUF_DATA_FORMAT_16_16;
1580 case 3:
1581 case 4:
1582 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1583 }
1584 break;
1585 case 32:
1586 /* From the Southern Islands ISA documentation about MTBUF:
1587 * 'Memory reads of data in memory that is 32 or 64 bits do not
1588 * undergo any format conversion.'
1589 */
1590 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1591 !desc->channel[first_non_void].pure_integer)
1592 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1593
1594 switch (desc->nr_channels) {
1595 case 1:
1596 return V_008F0C_BUF_DATA_FORMAT_32;
1597 case 2:
1598 return V_008F0C_BUF_DATA_FORMAT_32_32;
1599 case 3:
1600 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1601 case 4:
1602 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1603 }
1604 break;
1605 }
1606
1607 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1608 }
1609
1610 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1611 const struct util_format_description *desc,
1612 int first_non_void)
1613 {
1614 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1615 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1616
1617 switch (desc->channel[first_non_void].type) {
1618 case UTIL_FORMAT_TYPE_SIGNED:
1619 if (desc->channel[first_non_void].normalized)
1620 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1621 else if (desc->channel[first_non_void].pure_integer)
1622 return V_008F0C_BUF_NUM_FORMAT_SINT;
1623 else
1624 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1625 break;
1626 case UTIL_FORMAT_TYPE_UNSIGNED:
1627 if (desc->channel[first_non_void].normalized)
1628 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1629 else if (desc->channel[first_non_void].pure_integer)
1630 return V_008F0C_BUF_NUM_FORMAT_UINT;
1631 else
1632 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1633 break;
1634 case UTIL_FORMAT_TYPE_FLOAT:
1635 default:
1636 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1637 }
1638 }
1639
1640 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1641 {
1642 const struct util_format_description *desc;
1643 int first_non_void;
1644 unsigned data_format;
1645
1646 desc = util_format_description(format);
1647 first_non_void = util_format_get_first_non_void_channel(format);
1648 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1649 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1650 }
1651
1652 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1653 {
1654 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1655 r600_translate_colorswap(format) != ~0U;
1656 }
1657
1658 static bool si_is_zs_format_supported(enum pipe_format format)
1659 {
1660 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1661 }
1662
1663 boolean si_is_format_supported(struct pipe_screen *screen,
1664 enum pipe_format format,
1665 enum pipe_texture_target target,
1666 unsigned sample_count,
1667 unsigned usage)
1668 {
1669 unsigned retval = 0;
1670
1671 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1672 R600_ERR("r600: unsupported texture type %d\n", target);
1673 return FALSE;
1674 }
1675
1676 if (!util_format_is_supported(format, usage))
1677 return FALSE;
1678
1679 if (sample_count > 1) {
1680 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1681 return FALSE;
1682
1683 switch (sample_count) {
1684 case 2:
1685 case 4:
1686 case 8:
1687 break;
1688 default:
1689 return FALSE;
1690 }
1691 }
1692
1693 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1694 if (target == PIPE_BUFFER) {
1695 if (si_is_vertex_format_supported(screen, format))
1696 retval |= PIPE_BIND_SAMPLER_VIEW;
1697 } else {
1698 if (si_is_sampler_format_supported(screen, format))
1699 retval |= PIPE_BIND_SAMPLER_VIEW;
1700 }
1701 }
1702
1703 if ((usage & (PIPE_BIND_RENDER_TARGET |
1704 PIPE_BIND_DISPLAY_TARGET |
1705 PIPE_BIND_SCANOUT |
1706 PIPE_BIND_SHARED |
1707 PIPE_BIND_BLENDABLE)) &&
1708 si_is_colorbuffer_format_supported(format)) {
1709 retval |= usage &
1710 (PIPE_BIND_RENDER_TARGET |
1711 PIPE_BIND_DISPLAY_TARGET |
1712 PIPE_BIND_SCANOUT |
1713 PIPE_BIND_SHARED);
1714 if (!util_format_is_pure_integer(format) &&
1715 !util_format_is_depth_or_stencil(format))
1716 retval |= usage & PIPE_BIND_BLENDABLE;
1717 }
1718
1719 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1720 si_is_zs_format_supported(format)) {
1721 retval |= PIPE_BIND_DEPTH_STENCIL;
1722 }
1723
1724 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1725 si_is_vertex_format_supported(screen, format)) {
1726 retval |= PIPE_BIND_VERTEX_BUFFER;
1727 }
1728
1729 if (usage & PIPE_BIND_TRANSFER_READ)
1730 retval |= PIPE_BIND_TRANSFER_READ;
1731 if (usage & PIPE_BIND_TRANSFER_WRITE)
1732 retval |= PIPE_BIND_TRANSFER_WRITE;
1733
1734 return retval == usage;
1735 }
1736
1737 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1738 {
1739 unsigned tile_mode_index = 0;
1740
1741 if (stencil) {
1742 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1743 } else {
1744 tile_mode_index = rtex->surface.tiling_index[level];
1745 }
1746 return tile_mode_index;
1747 }
1748
1749 /*
1750 * framebuffer handling
1751 */
1752
1753 static void si_initialize_color_surface(struct si_context *sctx,
1754 struct r600_surface *surf)
1755 {
1756 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1757 unsigned level = surf->base.u.tex.level;
1758 uint64_t offset = rtex->surface.level[level].offset;
1759 unsigned pitch, slice;
1760 unsigned color_info, color_attrib, color_pitch, color_view;
1761 unsigned tile_mode_index;
1762 unsigned format, swap, ntype, endian;
1763 const struct util_format_description *desc;
1764 int i;
1765 unsigned blend_clamp = 0, blend_bypass = 0;
1766 unsigned max_comp_size;
1767
1768 /* Layered rendering doesn't work with LINEAR_GENERAL.
1769 * (LINEAR_ALIGNED and others work) */
1770 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1771 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1772 offset += rtex->surface.level[level].slice_size *
1773 surf->base.u.tex.first_layer;
1774 color_view = 0;
1775 } else {
1776 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1777 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1778 }
1779
1780 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1781 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1782 if (slice) {
1783 slice = slice - 1;
1784 }
1785
1786 tile_mode_index = si_tile_mode_index(rtex, level, false);
1787
1788 desc = util_format_description(surf->base.format);
1789 for (i = 0; i < 4; i++) {
1790 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1791 break;
1792 }
1793 }
1794 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1795 ntype = V_028C70_NUMBER_FLOAT;
1796 } else {
1797 ntype = V_028C70_NUMBER_UNORM;
1798 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1799 ntype = V_028C70_NUMBER_SRGB;
1800 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1801 if (desc->channel[i].pure_integer) {
1802 ntype = V_028C70_NUMBER_SINT;
1803 } else {
1804 assert(desc->channel[i].normalized);
1805 ntype = V_028C70_NUMBER_SNORM;
1806 }
1807 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1808 if (desc->channel[i].pure_integer) {
1809 ntype = V_028C70_NUMBER_UINT;
1810 } else {
1811 assert(desc->channel[i].normalized);
1812 ntype = V_028C70_NUMBER_UNORM;
1813 }
1814 }
1815 }
1816
1817 format = si_translate_colorformat(surf->base.format);
1818 if (format == V_028C70_COLOR_INVALID) {
1819 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1820 }
1821 assert(format != V_028C70_COLOR_INVALID);
1822 swap = r600_translate_colorswap(surf->base.format);
1823 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1824 endian = V_028C70_ENDIAN_NONE;
1825 } else {
1826 endian = si_colorformat_endian_swap(format);
1827 }
1828
1829 /* blend clamp should be set for all NORM/SRGB types */
1830 if (ntype == V_028C70_NUMBER_UNORM ||
1831 ntype == V_028C70_NUMBER_SNORM ||
1832 ntype == V_028C70_NUMBER_SRGB)
1833 blend_clamp = 1;
1834
1835 /* set blend bypass according to docs if SINT/UINT or
1836 8/24 COLOR variants */
1837 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1838 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1839 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1840 blend_clamp = 0;
1841 blend_bypass = 1;
1842 }
1843
1844 color_info = S_028C70_FORMAT(format) |
1845 S_028C70_COMP_SWAP(swap) |
1846 S_028C70_BLEND_CLAMP(blend_clamp) |
1847 S_028C70_BLEND_BYPASS(blend_bypass) |
1848 S_028C70_NUMBER_TYPE(ntype) |
1849 S_028C70_ENDIAN(endian);
1850
1851 color_pitch = S_028C64_TILE_MAX(pitch);
1852
1853 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1854 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1855
1856 if (rtex->resource.b.b.nr_samples > 1) {
1857 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1858
1859 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1860 S_028C74_NUM_FRAGMENTS(log_samples);
1861
1862 if (rtex->fmask.size) {
1863 color_info |= S_028C70_COMPRESSION(1);
1864 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1865
1866 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1867
1868 if (sctx->b.chip_class == SI) {
1869 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1870 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1871 }
1872 if (sctx->b.chip_class >= CIK) {
1873 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1874 }
1875 }
1876 }
1877
1878 offset += rtex->resource.gpu_address;
1879
1880 surf->cb_color_base = offset >> 8;
1881 surf->cb_color_pitch = color_pitch;
1882 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1883 surf->cb_color_view = color_view;
1884 surf->cb_color_info = color_info;
1885 surf->cb_color_attrib = color_attrib;
1886
1887 if (sctx->b.chip_class >= VI)
1888 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1889
1890 if (rtex->fmask.size) {
1891 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1892 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1893 } else {
1894 /* This must be set for fast clear to work without FMASK. */
1895 surf->cb_color_fmask = surf->cb_color_base;
1896 surf->cb_color_fmask_slice = surf->cb_color_slice;
1897 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1898
1899 if (sctx->b.chip_class == SI) {
1900 unsigned bankh = util_logbase2(rtex->surface.bankh);
1901 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1902 }
1903
1904 if (sctx->b.chip_class >= CIK) {
1905 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1906 }
1907 }
1908
1909 /* Determine pixel shader export format */
1910 max_comp_size = si_colorformat_max_comp_size(format);
1911 if (ntype == V_028C70_NUMBER_SRGB ||
1912 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1913 max_comp_size <= 10) ||
1914 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1915 surf->export_16bpc = true;
1916 }
1917
1918 surf->color_initialized = true;
1919 }
1920
1921 static void si_init_depth_surface(struct si_context *sctx,
1922 struct r600_surface *surf)
1923 {
1924 struct si_screen *sscreen = sctx->screen;
1925 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1926 unsigned level = surf->base.u.tex.level;
1927 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1928 unsigned format, tile_mode_index, array_mode;
1929 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1930 uint32_t z_info, s_info, db_depth_info;
1931 uint64_t z_offs, s_offs;
1932 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1933
1934 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1935 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1936 case PIPE_FORMAT_X8Z24_UNORM:
1937 case PIPE_FORMAT_Z24X8_UNORM:
1938 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1939 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1940 break;
1941 case PIPE_FORMAT_Z32_FLOAT:
1942 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1943 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1944 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1945 break;
1946 case PIPE_FORMAT_Z16_UNORM:
1947 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1948 break;
1949 default:
1950 assert(0);
1951 }
1952
1953 format = si_translate_dbformat(rtex->resource.b.b.format);
1954
1955 if (format == V_028040_Z_INVALID) {
1956 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1957 }
1958 assert(format != V_028040_Z_INVALID);
1959
1960 s_offs = z_offs = rtex->resource.gpu_address;
1961 z_offs += rtex->surface.level[level].offset;
1962 s_offs += rtex->surface.stencil_level[level].offset;
1963
1964 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1965
1966 z_info = S_028040_FORMAT(format);
1967 if (rtex->resource.b.b.nr_samples > 1) {
1968 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1969 }
1970
1971 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1972 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1973 else
1974 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1975
1976 if (sctx->b.chip_class >= CIK) {
1977 switch (rtex->surface.level[level].mode) {
1978 case RADEON_SURF_MODE_2D:
1979 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1980 break;
1981 case RADEON_SURF_MODE_1D:
1982 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1983 case RADEON_SURF_MODE_LINEAR:
1984 default:
1985 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1986 break;
1987 }
1988 tile_split = rtex->surface.tile_split;
1989 stile_split = rtex->surface.stencil_tile_split;
1990 macro_aspect = rtex->surface.mtilea;
1991 bankw = rtex->surface.bankw;
1992 bankh = rtex->surface.bankh;
1993 tile_split = cik_tile_split(tile_split);
1994 stile_split = cik_tile_split(stile_split);
1995 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1996 bankw = cik_bank_wh(bankw);
1997 bankh = cik_bank_wh(bankh);
1998 nbanks = si_num_banks(sscreen, rtex);
1999 tile_mode_index = si_tile_mode_index(rtex, level, false);
2000 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2001
2002 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2003 S_02803C_PIPE_CONFIG(pipe_config) |
2004 S_02803C_BANK_WIDTH(bankw) |
2005 S_02803C_BANK_HEIGHT(bankh) |
2006 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2007 S_02803C_NUM_BANKS(nbanks);
2008 z_info |= S_028040_TILE_SPLIT(tile_split);
2009 s_info |= S_028044_TILE_SPLIT(stile_split);
2010 } else {
2011 tile_mode_index = si_tile_mode_index(rtex, level, false);
2012 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2013 tile_mode_index = si_tile_mode_index(rtex, level, true);
2014 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2015 }
2016
2017 /* HiZ aka depth buffer htile */
2018 /* use htile only for first level */
2019 if (rtex->htile_buffer && !level) {
2020 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2021 S_028040_ALLOW_EXPCLEAR(1);
2022
2023 /* Use all of the htile_buffer for depth, because we don't
2024 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2025 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2026
2027 uint64_t va = rtex->htile_buffer->gpu_address;
2028 db_htile_data_base = va >> 8;
2029 db_htile_surface = S_028ABC_FULL_CACHE(1);
2030 } else {
2031 db_htile_data_base = 0;
2032 db_htile_surface = 0;
2033 }
2034
2035 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2036
2037 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2038 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2039 surf->db_htile_data_base = db_htile_data_base;
2040 surf->db_depth_info = db_depth_info;
2041 surf->db_z_info = z_info;
2042 surf->db_stencil_info = s_info;
2043 surf->db_depth_base = z_offs >> 8;
2044 surf->db_stencil_base = s_offs >> 8;
2045 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2046 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2047 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2048 levelinfo->nblk_y) / 64 - 1);
2049 surf->db_htile_surface = db_htile_surface;
2050 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2051
2052 surf->depth_initialized = true;
2053 }
2054
2055 static void si_set_framebuffer_state(struct pipe_context *ctx,
2056 const struct pipe_framebuffer_state *state)
2057 {
2058 struct si_context *sctx = (struct si_context *)ctx;
2059 struct pipe_constant_buffer constbuf = {0};
2060 struct r600_surface *surf = NULL;
2061 struct r600_texture *rtex;
2062 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2063 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2064 int i;
2065
2066 /* Only flush TC when changing the framebuffer state, because
2067 * the only client not using TC that can change textures is
2068 * the framebuffer.
2069 *
2070 * Flush all CB and DB caches here because all buffers can be used
2071 * for write by both TC (with shader image stores) and CB/DB.
2072 */
2073 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2074 SI_CONTEXT_INV_TC_L2 |
2075 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2076
2077 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2078
2079 sctx->framebuffer.export_16bpc = 0;
2080 sctx->framebuffer.compressed_cb_mask = 0;
2081 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2082 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2083 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2084 util_format_is_pure_integer(state->cbufs[0]->format);
2085
2086 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2087 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2088
2089 for (i = 0; i < state->nr_cbufs; i++) {
2090 if (!state->cbufs[i])
2091 continue;
2092
2093 surf = (struct r600_surface*)state->cbufs[i];
2094 rtex = (struct r600_texture*)surf->base.texture;
2095
2096 if (!surf->color_initialized) {
2097 si_initialize_color_surface(sctx, surf);
2098 }
2099
2100 if (surf->export_16bpc) {
2101 sctx->framebuffer.export_16bpc |= 1 << i;
2102 }
2103
2104 if (rtex->fmask.size && rtex->cmask.size) {
2105 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2106 }
2107 r600_context_add_resource_size(ctx, surf->base.texture);
2108 }
2109 /* Set the 16BPC export for possible dual-src blending. */
2110 if (i == 1 && surf && surf->export_16bpc) {
2111 sctx->framebuffer.export_16bpc |= 1 << 1;
2112 }
2113
2114 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2115
2116 if (state->zsbuf) {
2117 surf = (struct r600_surface*)state->zsbuf;
2118
2119 if (!surf->depth_initialized) {
2120 si_init_depth_surface(sctx, surf);
2121 }
2122 r600_context_add_resource_size(ctx, surf->base.texture);
2123 }
2124
2125 si_update_fb_rs_state(sctx);
2126 si_update_fb_blend_state(sctx);
2127
2128 sctx->framebuffer.atom.num_dw = state->nr_cbufs*16 + (8 - state->nr_cbufs)*3;
2129 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2130 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2131 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2132 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2133
2134 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2135 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2136 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2137
2138 /* Set sample locations as fragment shader constants. */
2139 switch (sctx->framebuffer.nr_samples) {
2140 case 1:
2141 constbuf.user_buffer = sctx->b.sample_locations_1x;
2142 break;
2143 case 2:
2144 constbuf.user_buffer = sctx->b.sample_locations_2x;
2145 break;
2146 case 4:
2147 constbuf.user_buffer = sctx->b.sample_locations_4x;
2148 break;
2149 case 8:
2150 constbuf.user_buffer = sctx->b.sample_locations_8x;
2151 break;
2152 case 16:
2153 constbuf.user_buffer = sctx->b.sample_locations_16x;
2154 break;
2155 default:
2156 assert(0);
2157 }
2158 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2159 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2160 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2161
2162 /* Smoothing (only possible with nr_samples == 1) uses the same
2163 * sample locations as the MSAA it simulates.
2164 *
2165 * Therefore, don't update the sample locations when
2166 * transitioning from no AA to smoothing-equivalent AA, and
2167 * vice versa.
2168 */
2169 if ((sctx->framebuffer.nr_samples != 1 ||
2170 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2171 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2172 old_nr_samples != 1))
2173 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2174 }
2175 }
2176
2177 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2178 {
2179 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2180 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2181 unsigned i, nr_cbufs = state->nr_cbufs;
2182 struct r600_texture *tex = NULL;
2183 struct r600_surface *cb = NULL;
2184
2185 /* Colorbuffers. */
2186 for (i = 0; i < nr_cbufs; i++) {
2187 cb = (struct r600_surface*)state->cbufs[i];
2188 if (!cb) {
2189 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2190 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2191 continue;
2192 }
2193
2194 tex = (struct r600_texture *)cb->base.texture;
2195 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2196 &tex->resource, RADEON_USAGE_READWRITE,
2197 tex->surface.nsamples > 1 ?
2198 RADEON_PRIO_COLOR_BUFFER_MSAA :
2199 RADEON_PRIO_COLOR_BUFFER);
2200
2201 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2202 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2203 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2204 RADEON_PRIO_COLOR_META);
2205 }
2206
2207 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2208 sctx->b.chip_class >= VI ? 14 : 13);
2209 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2210 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2211 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2212 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2213 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2214 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2215 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2216 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2217 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2218 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2219 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2220 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2221 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2222
2223 if (sctx->b.chip_class >= VI)
2224 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2225 }
2226 /* set CB_COLOR1_INFO for possible dual-src blending */
2227 if (i == 1 && state->cbufs[0]) {
2228 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2229 cb->cb_color_info | tex->cb_color_info);
2230 i++;
2231 }
2232 for (; i < 8 ; i++) {
2233 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2234 }
2235
2236 /* ZS buffer. */
2237 if (state->zsbuf) {
2238 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2239 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2240
2241 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2242 &rtex->resource, RADEON_USAGE_READWRITE,
2243 zb->base.texture->nr_samples > 1 ?
2244 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2245 RADEON_PRIO_DEPTH_BUFFER);
2246
2247 if (zb->db_htile_data_base) {
2248 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2249 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2250 RADEON_PRIO_DEPTH_META);
2251 }
2252
2253 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2254 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2255
2256 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2257 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2258 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2259 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2260 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2261 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2262 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2263 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2264 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2265 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2266 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2267
2268 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2269 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2270 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2271 zb->pa_su_poly_offset_db_fmt_cntl);
2272 } else {
2273 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2274 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2275 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2276 }
2277
2278 /* Framebuffer dimensions. */
2279 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2280 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2281 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2282 }
2283
2284 static void si_emit_msaa_sample_locs(struct r600_common_context *rctx,
2285 struct r600_atom *atom)
2286 {
2287 struct si_context *sctx = (struct si_context *)rctx;
2288 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2289 unsigned nr_samples = sctx->framebuffer.nr_samples;
2290
2291 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2292 SI_NUM_SMOOTH_AA_SAMPLES);
2293 }
2294
2295 const struct r600_atom si_atom_msaa_sample_locs = { si_emit_msaa_sample_locs, 18 }; /* number of CS dwords */
2296
2297 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2298 {
2299 struct si_context *sctx = (struct si_context *)rctx;
2300 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2301
2302 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2303 sctx->ps_iter_samples,
2304 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2305 }
2306
2307 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2308
2309 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2310 {
2311 struct si_context *sctx = (struct si_context *)ctx;
2312
2313 if (sctx->ps_iter_samples == min_samples)
2314 return;
2315
2316 sctx->ps_iter_samples = min_samples;
2317
2318 if (sctx->framebuffer.nr_samples > 1)
2319 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2320 }
2321
2322 /*
2323 * Samplers
2324 */
2325
2326 /**
2327 * Create a sampler view.
2328 *
2329 * @param ctx context
2330 * @param texture texture
2331 * @param state sampler view template
2332 * @param width0 width0 override (for compressed textures as int)
2333 * @param height0 height0 override (for compressed textures as int)
2334 * @param force_level set the base address to the level (for compressed textures)
2335 */
2336 struct pipe_sampler_view *
2337 si_create_sampler_view_custom(struct pipe_context *ctx,
2338 struct pipe_resource *texture,
2339 const struct pipe_sampler_view *state,
2340 unsigned width0, unsigned height0,
2341 unsigned force_level)
2342 {
2343 struct si_context *sctx = (struct si_context*)ctx;
2344 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2345 struct r600_texture *tmp = (struct r600_texture*)texture;
2346 const struct util_format_description *desc;
2347 unsigned format, num_format, base_level, first_level, last_level;
2348 uint32_t pitch = 0;
2349 unsigned char state_swizzle[4], swizzle[4];
2350 unsigned height, depth, width;
2351 enum pipe_format pipe_format = state->format;
2352 struct radeon_surf_level *surflevel;
2353 int first_non_void;
2354 uint64_t va;
2355
2356 if (view == NULL)
2357 return NULL;
2358
2359 /* initialize base object */
2360 view->base = *state;
2361 view->base.texture = NULL;
2362 view->base.reference.count = 1;
2363 view->base.context = ctx;
2364
2365 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2366 if (!texture) {
2367 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2368 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2369 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2370 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2371 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2372 return &view->base;
2373 }
2374
2375 pipe_resource_reference(&view->base.texture, texture);
2376 view->resource = &tmp->resource;
2377
2378 /* Buffer resource. */
2379 if (texture->target == PIPE_BUFFER) {
2380 unsigned stride, num_records;
2381
2382 desc = util_format_description(state->format);
2383 first_non_void = util_format_get_first_non_void_channel(state->format);
2384 stride = desc->block.bits / 8;
2385 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2386 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2387 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2388
2389 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2390 num_records = MIN2(num_records, texture->width0 / stride);
2391
2392 if (sctx->b.chip_class >= VI)
2393 num_records *= stride;
2394
2395 view->state[4] = va;
2396 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2397 S_008F04_STRIDE(stride);
2398 view->state[6] = num_records;
2399 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2400 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2401 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2402 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2403 S_008F0C_NUM_FORMAT(num_format) |
2404 S_008F0C_DATA_FORMAT(format);
2405
2406 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2407 return &view->base;
2408 }
2409
2410 state_swizzle[0] = state->swizzle_r;
2411 state_swizzle[1] = state->swizzle_g;
2412 state_swizzle[2] = state->swizzle_b;
2413 state_swizzle[3] = state->swizzle_a;
2414
2415 surflevel = tmp->surface.level;
2416
2417 /* Texturing with separate depth and stencil. */
2418 if (tmp->is_depth && !tmp->is_flushing_texture) {
2419 switch (pipe_format) {
2420 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2421 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2422 break;
2423 case PIPE_FORMAT_X8Z24_UNORM:
2424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2425 /* Z24 is always stored like this. */
2426 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2427 break;
2428 case PIPE_FORMAT_X24S8_UINT:
2429 case PIPE_FORMAT_S8X24_UINT:
2430 case PIPE_FORMAT_X32_S8X24_UINT:
2431 pipe_format = PIPE_FORMAT_S8_UINT;
2432 surflevel = tmp->surface.stencil_level;
2433 break;
2434 default:;
2435 }
2436 }
2437
2438 desc = util_format_description(pipe_format);
2439
2440 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2441 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2442 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2443
2444 switch (pipe_format) {
2445 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2446 case PIPE_FORMAT_X24S8_UINT:
2447 case PIPE_FORMAT_X32_S8X24_UINT:
2448 case PIPE_FORMAT_X8Z24_UNORM:
2449 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2450 break;
2451 default:
2452 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2453 }
2454 } else {
2455 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2456 }
2457
2458 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2459
2460 switch (pipe_format) {
2461 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2462 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2463 break;
2464 default:
2465 if (first_non_void < 0) {
2466 if (util_format_is_compressed(pipe_format)) {
2467 switch (pipe_format) {
2468 case PIPE_FORMAT_DXT1_SRGB:
2469 case PIPE_FORMAT_DXT1_SRGBA:
2470 case PIPE_FORMAT_DXT3_SRGBA:
2471 case PIPE_FORMAT_DXT5_SRGBA:
2472 case PIPE_FORMAT_BPTC_SRGBA:
2473 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2474 break;
2475 case PIPE_FORMAT_RGTC1_SNORM:
2476 case PIPE_FORMAT_LATC1_SNORM:
2477 case PIPE_FORMAT_RGTC2_SNORM:
2478 case PIPE_FORMAT_LATC2_SNORM:
2479 /* implies float, so use SNORM/UNORM to determine
2480 whether data is signed or not */
2481 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2482 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2483 break;
2484 default:
2485 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2486 break;
2487 }
2488 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2489 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2490 } else {
2491 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2492 }
2493 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2494 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2495 } else {
2496 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2497
2498 switch (desc->channel[first_non_void].type) {
2499 case UTIL_FORMAT_TYPE_FLOAT:
2500 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2501 break;
2502 case UTIL_FORMAT_TYPE_SIGNED:
2503 if (desc->channel[first_non_void].normalized)
2504 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2505 else if (desc->channel[first_non_void].pure_integer)
2506 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2507 else
2508 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2509 break;
2510 case UTIL_FORMAT_TYPE_UNSIGNED:
2511 if (desc->channel[first_non_void].normalized)
2512 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2513 else if (desc->channel[first_non_void].pure_integer)
2514 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2515 else
2516 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2517 }
2518 }
2519 }
2520
2521 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2522 if (format == ~0) {
2523 format = 0;
2524 }
2525
2526 base_level = 0;
2527 first_level = state->u.tex.first_level;
2528 last_level = state->u.tex.last_level;
2529 width = width0;
2530 height = height0;
2531 depth = texture->depth0;
2532
2533 if (force_level) {
2534 assert(force_level == first_level &&
2535 force_level == last_level);
2536 base_level = force_level;
2537 first_level = 0;
2538 last_level = 0;
2539 width = u_minify(width, force_level);
2540 height = u_minify(height, force_level);
2541 depth = u_minify(depth, force_level);
2542 }
2543
2544 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2545
2546 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2547 height = 1;
2548 depth = texture->array_size;
2549 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2550 depth = texture->array_size;
2551 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2552 depth = texture->array_size / 6;
2553
2554 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2555
2556 view->state[0] = va >> 8;
2557 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2558 S_008F14_DATA_FORMAT(format) |
2559 S_008F14_NUM_FORMAT(num_format));
2560 view->state[2] = (S_008F18_WIDTH(width - 1) |
2561 S_008F18_HEIGHT(height - 1));
2562 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2563 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2564 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2565 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2566 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2567 0 : first_level) |
2568 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2569 util_logbase2(texture->nr_samples) :
2570 last_level) |
2571 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2572 S_008F1C_POW2_PAD(texture->last_level > 0) |
2573 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2574 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2575 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2576 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2577 view->state[6] = 0;
2578 view->state[7] = 0;
2579
2580 /* Initialize the sampler view for FMASK. */
2581 if (tmp->fmask.size) {
2582 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2583 uint32_t fmask_format;
2584
2585 switch (texture->nr_samples) {
2586 case 2:
2587 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2588 break;
2589 case 4:
2590 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2591 break;
2592 case 8:
2593 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2594 break;
2595 default:
2596 assert(0);
2597 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2598 }
2599
2600 view->fmask_state[0] = va >> 8;
2601 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2602 S_008F14_DATA_FORMAT(fmask_format) |
2603 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2604 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2605 S_008F18_HEIGHT(height - 1);
2606 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2607 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2608 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2609 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2610 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2611 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2612 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2613 S_008F20_PITCH(tmp->fmask.pitch - 1);
2614 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2615 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2616 view->fmask_state[6] = 0;
2617 view->fmask_state[7] = 0;
2618 }
2619
2620 return &view->base;
2621 }
2622
2623 static struct pipe_sampler_view *
2624 si_create_sampler_view(struct pipe_context *ctx,
2625 struct pipe_resource *texture,
2626 const struct pipe_sampler_view *state)
2627 {
2628 return si_create_sampler_view_custom(ctx, texture, state,
2629 texture ? texture->width0 : 0,
2630 texture ? texture->height0 : 0, 0);
2631 }
2632
2633 static void si_sampler_view_destroy(struct pipe_context *ctx,
2634 struct pipe_sampler_view *state)
2635 {
2636 struct si_sampler_view *view = (struct si_sampler_view *)state;
2637
2638 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2639 LIST_DELINIT(&view->list);
2640
2641 pipe_resource_reference(&state->texture, NULL);
2642 FREE(view);
2643 }
2644
2645 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2646 {
2647 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2648 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2649 (linear_filter &&
2650 (wrap == PIPE_TEX_WRAP_CLAMP ||
2651 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2652 }
2653
2654 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2655 {
2656 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2657 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2658
2659 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2660 state->border_color.ui[2] || state->border_color.ui[3]) &&
2661 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2662 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2663 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2664 }
2665
2666 static void *si_create_sampler_state(struct pipe_context *ctx,
2667 const struct pipe_sampler_state *state)
2668 {
2669 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2670 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2671 unsigned border_color_type;
2672
2673 if (rstate == NULL) {
2674 return NULL;
2675 }
2676
2677 if (sampler_state_needs_border_color(state))
2678 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2679 else
2680 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2681
2682 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2683 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2684 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2685 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2686 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2687 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2688 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2689 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2690 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2691 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2692 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2693 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2694 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2695 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2696
2697 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2698 memcpy(rstate->border_color, state->border_color.ui,
2699 sizeof(rstate->border_color));
2700 }
2701
2702 return rstate;
2703 }
2704
2705 /* Upload border colors and update the pointers in resource descriptors.
2706 * There can only be 4096 border colors per context.
2707 *
2708 * XXX: This is broken if the buffer gets reallocated.
2709 */
2710 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2711 void **states)
2712 {
2713 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2714 uint32_t *border_color_table = NULL;
2715 int i, j;
2716
2717 for (i = 0; i < count; i++) {
2718 if (rstates[i] &&
2719 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2720 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2721 if (!sctx->border_color_table ||
2722 ((sctx->border_color_offset + count - i) &
2723 C_008F3C_BORDER_COLOR_PTR)) {
2724 r600_resource_reference(&sctx->border_color_table, NULL);
2725 sctx->border_color_offset = 0;
2726
2727 sctx->border_color_table =
2728 si_resource_create_custom(&sctx->screen->b.b,
2729 PIPE_USAGE_DYNAMIC,
2730 4096 * 4 * 4);
2731 }
2732
2733 if (!border_color_table) {
2734 border_color_table =
2735 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2736 sctx->b.rings.gfx.cs,
2737 PIPE_TRANSFER_WRITE |
2738 PIPE_TRANSFER_UNSYNCHRONIZED);
2739 }
2740
2741 for (j = 0; j < 4; j++) {
2742 border_color_table[4 * sctx->border_color_offset + j] =
2743 util_le32_to_cpu(rstates[i]->border_color[j]);
2744 }
2745
2746 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2747 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2748 }
2749 }
2750
2751 if (border_color_table) {
2752 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2753
2754 uint64_t va_offset = sctx->border_color_table->gpu_address;
2755
2756 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2757 if (sctx->b.chip_class >= CIK)
2758 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2759 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2760 RADEON_PRIO_SHADER_DATA);
2761 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2762 }
2763 }
2764
2765 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2766 unsigned start, unsigned count,
2767 void **states)
2768 {
2769 struct si_context *sctx = (struct si_context *)ctx;
2770
2771 if (!count || shader >= SI_NUM_SHADERS)
2772 return;
2773
2774 si_set_border_colors(sctx, count, states);
2775 si_set_sampler_descriptors(sctx, shader, start, count, states);
2776 }
2777
2778 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2779 {
2780 struct si_context *sctx = (struct si_context *)ctx;
2781 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2782 struct si_pm4_state *pm4 = &state->pm4;
2783 uint16_t mask = sample_mask;
2784
2785 if (state == NULL)
2786 return;
2787
2788 state->sample_mask = mask;
2789 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2790 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2791
2792 si_pm4_set_state(sctx, sample_mask, state);
2793 }
2794
2795 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2796 {
2797 free(state);
2798 }
2799
2800 /*
2801 * Vertex elements & buffers
2802 */
2803
2804 static void *si_create_vertex_elements(struct pipe_context *ctx,
2805 unsigned count,
2806 const struct pipe_vertex_element *elements)
2807 {
2808 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2809 int i;
2810
2811 assert(count < SI_MAX_ATTRIBS);
2812 if (!v)
2813 return NULL;
2814
2815 v->count = count;
2816 for (i = 0; i < count; ++i) {
2817 const struct util_format_description *desc;
2818 unsigned data_format, num_format;
2819 int first_non_void;
2820
2821 desc = util_format_description(elements[i].src_format);
2822 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2823 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2824 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2825
2826 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2827 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2828 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2829 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2830 S_008F0C_NUM_FORMAT(num_format) |
2831 S_008F0C_DATA_FORMAT(data_format);
2832 v->format_size[i] = desc->block.bits / 8;
2833 }
2834 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2835
2836 return v;
2837 }
2838
2839 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2840 {
2841 struct si_context *sctx = (struct si_context *)ctx;
2842 struct si_vertex_element *v = (struct si_vertex_element*)state;
2843
2844 sctx->vertex_elements = v;
2845 sctx->vertex_buffers_dirty = true;
2846 }
2847
2848 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2849 {
2850 struct si_context *sctx = (struct si_context *)ctx;
2851
2852 if (sctx->vertex_elements == state)
2853 sctx->vertex_elements = NULL;
2854 FREE(state);
2855 }
2856
2857 static void si_set_vertex_buffers(struct pipe_context *ctx,
2858 unsigned start_slot, unsigned count,
2859 const struct pipe_vertex_buffer *buffers)
2860 {
2861 struct si_context *sctx = (struct si_context *)ctx;
2862 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2863 int i;
2864
2865 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2866
2867 if (buffers) {
2868 for (i = 0; i < count; i++) {
2869 const struct pipe_vertex_buffer *src = buffers + i;
2870 struct pipe_vertex_buffer *dsti = dst + i;
2871
2872 pipe_resource_reference(&dsti->buffer, src->buffer);
2873 dsti->buffer_offset = src->buffer_offset;
2874 dsti->stride = src->stride;
2875 r600_context_add_resource_size(ctx, src->buffer);
2876 }
2877 } else {
2878 for (i = 0; i < count; i++) {
2879 pipe_resource_reference(&dst[i].buffer, NULL);
2880 }
2881 }
2882 sctx->vertex_buffers_dirty = true;
2883 }
2884
2885 static void si_set_index_buffer(struct pipe_context *ctx,
2886 const struct pipe_index_buffer *ib)
2887 {
2888 struct si_context *sctx = (struct si_context *)ctx;
2889
2890 if (ib) {
2891 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2892 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2893 r600_context_add_resource_size(ctx, ib->buffer);
2894 } else {
2895 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2896 }
2897 }
2898
2899 /*
2900 * Misc
2901 */
2902 static void si_set_polygon_stipple(struct pipe_context *ctx,
2903 const struct pipe_poly_stipple *state)
2904 {
2905 struct si_context *sctx = (struct si_context *)ctx;
2906 struct pipe_resource *tex;
2907 struct pipe_sampler_view *view;
2908 bool is_zero = true;
2909 bool is_one = true;
2910 int i;
2911
2912 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2913 * the resource is NULL/invalid. Take advantage of this fact and skip
2914 * texture allocation if the stipple pattern is constant.
2915 *
2916 * This is an optimization for the common case when stippling isn't
2917 * used but set_polygon_stipple is still called by st/mesa.
2918 */
2919 for (i = 0; i < Elements(state->stipple); i++) {
2920 is_zero = is_zero && state->stipple[i] == 0;
2921 is_one = is_one && state->stipple[i] == 0xffffffff;
2922 }
2923
2924 if (is_zero || is_one) {
2925 struct pipe_sampler_view templ = {{0}};
2926
2927 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2928 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2929 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2930 /* The pattern should be inverted in the texture. */
2931 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2932
2933 view = ctx->create_sampler_view(ctx, NULL, &templ);
2934 } else {
2935 /* Create a new texture. */
2936 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2937 if (!tex)
2938 return;
2939
2940 view = util_pstipple_create_sampler_view(ctx, tex);
2941 pipe_resource_reference(&tex, NULL);
2942 }
2943
2944 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2945 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2946 pipe_sampler_view_reference(&view, NULL);
2947
2948 /* Bind the sampler state if needed. */
2949 if (!sctx->pstipple_sampler_state) {
2950 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2951 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2952 SI_POLY_STIPPLE_SAMPLER, 1,
2953 &sctx->pstipple_sampler_state);
2954 }
2955 }
2956
2957 static void si_set_tess_state(struct pipe_context *ctx,
2958 const float default_outer_level[4],
2959 const float default_inner_level[2])
2960 {
2961 struct si_context *sctx = (struct si_context *)ctx;
2962 struct pipe_constant_buffer cb;
2963 float array[8];
2964
2965 memcpy(array, default_outer_level, sizeof(float) * 4);
2966 memcpy(array+4, default_inner_level, sizeof(float) * 2);
2967
2968 cb.buffer = NULL;
2969 cb.user_buffer = NULL;
2970 cb.buffer_size = sizeof(array);
2971
2972 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
2973 (void*)array, sizeof(array),
2974 &cb.buffer_offset);
2975
2976 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
2977 SI_DRIVER_STATE_CONST_BUF, &cb);
2978 pipe_resource_reference(&cb.buffer, NULL);
2979 }
2980
2981 static void si_texture_barrier(struct pipe_context *ctx)
2982 {
2983 struct si_context *sctx = (struct si_context *)ctx;
2984
2985 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2986 SI_CONTEXT_INV_TC_L2 |
2987 SI_CONTEXT_FLUSH_AND_INV_CB;
2988 }
2989
2990 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2991 {
2992 struct pipe_blend_state blend;
2993
2994 memset(&blend, 0, sizeof(blend));
2995 blend.independent_blend_enable = true;
2996 blend.rt[0].colormask = 0xf;
2997 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2998 }
2999
3000 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3001 bool include_draw_vbo)
3002 {
3003 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3004 }
3005
3006 static void si_init_config(struct si_context *sctx);
3007
3008 void si_init_state_functions(struct si_context *sctx)
3009 {
3010 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
3011 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
3012 si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
3013 si_init_atom(&sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors, 16*4);
3014
3015 sctx->b.b.create_blend_state = si_create_blend_state;
3016 sctx->b.b.bind_blend_state = si_bind_blend_state;
3017 sctx->b.b.delete_blend_state = si_delete_blend_state;
3018 sctx->b.b.set_blend_color = si_set_blend_color;
3019
3020 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3021 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3022 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3023
3024 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3025 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3026 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3027
3028 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3029 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3030 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3031 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3032
3033 sctx->b.b.set_clip_state = si_set_clip_state;
3034 sctx->b.b.set_scissor_states = si_set_scissor_states;
3035 sctx->b.b.set_viewport_states = si_set_viewport_states;
3036 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3037
3038 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3039 sctx->b.b.get_sample_position = cayman_get_sample_position;
3040
3041 sctx->b.b.create_sampler_state = si_create_sampler_state;
3042 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3043 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3044
3045 sctx->b.b.create_sampler_view = si_create_sampler_view;
3046 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3047
3048 sctx->b.b.set_sample_mask = si_set_sample_mask;
3049
3050 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3051 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3052 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3053 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3054 sctx->b.b.set_index_buffer = si_set_index_buffer;
3055
3056 sctx->b.b.texture_barrier = si_texture_barrier;
3057 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3058 sctx->b.b.set_min_samples = si_set_min_samples;
3059 sctx->b.b.set_tess_state = si_set_tess_state;
3060
3061 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3062 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3063
3064 sctx->b.b.draw_vbo = si_draw_vbo;
3065
3066 if (sctx->b.chip_class >= CIK) {
3067 sctx->b.dma_copy = cik_sdma_copy;
3068 } else {
3069 sctx->b.dma_copy = si_dma_copy;
3070 }
3071
3072 si_init_config(sctx);
3073 }
3074
3075 static void
3076 si_write_harvested_raster_configs(struct si_context *sctx,
3077 struct si_pm4_state *pm4,
3078 unsigned raster_config,
3079 unsigned raster_config_1)
3080 {
3081 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3082 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3083 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3084 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3085 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3086 unsigned rb_per_se = num_rb / num_se;
3087 unsigned se_mask[4];
3088 unsigned se;
3089
3090 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3091 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3092 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3093 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3094
3095 assert(num_se == 1 || num_se == 2 || num_se == 4);
3096 assert(sh_per_se == 1 || sh_per_se == 2);
3097 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3098
3099 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3100 * fields are for, so I'm leaving them as their default
3101 * values. */
3102
3103 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3104 (!se_mask[2] && !se_mask[3]))) {
3105 raster_config_1 &= C_028354_SE_PAIR_MAP;
3106
3107 if (!se_mask[0] && !se_mask[1]) {
3108 raster_config_1 |=
3109 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3110 } else {
3111 raster_config_1 |=
3112 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3113 }
3114 }
3115
3116 for (se = 0; se < num_se; se++) {
3117 unsigned raster_config_se = raster_config;
3118 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3119 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3120 int idx = (se / 2) * 2;
3121
3122 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3123 raster_config_se &= C_028350_SE_MAP;
3124
3125 if (!se_mask[idx]) {
3126 raster_config_se |=
3127 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3128 } else {
3129 raster_config_se |=
3130 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3131 }
3132 }
3133
3134 pkr0_mask &= rb_mask;
3135 pkr1_mask &= rb_mask;
3136 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3137 raster_config_se &= C_028350_PKR_MAP;
3138
3139 if (!pkr0_mask) {
3140 raster_config_se |=
3141 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3142 } else {
3143 raster_config_se |=
3144 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3145 }
3146 }
3147
3148 if (rb_per_se >= 2) {
3149 unsigned rb0_mask = 1 << (se * rb_per_se);
3150 unsigned rb1_mask = rb0_mask << 1;
3151
3152 rb0_mask &= rb_mask;
3153 rb1_mask &= rb_mask;
3154 if (!rb0_mask || !rb1_mask) {
3155 raster_config_se &= C_028350_RB_MAP_PKR0;
3156
3157 if (!rb0_mask) {
3158 raster_config_se |=
3159 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3160 } else {
3161 raster_config_se |=
3162 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3163 }
3164 }
3165
3166 if (rb_per_se > 2) {
3167 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3168 rb1_mask = rb0_mask << 1;
3169 rb0_mask &= rb_mask;
3170 rb1_mask &= rb_mask;
3171 if (!rb0_mask || !rb1_mask) {
3172 raster_config_se &= C_028350_RB_MAP_PKR1;
3173
3174 if (!rb0_mask) {
3175 raster_config_se |=
3176 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3177 } else {
3178 raster_config_se |=
3179 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3180 }
3181 }
3182 }
3183 }
3184
3185 /* GRBM_GFX_INDEX is privileged on VI */
3186 if (sctx->b.chip_class <= CIK)
3187 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3188 SE_INDEX(se) | SH_BROADCAST_WRITES |
3189 INSTANCE_BROADCAST_WRITES);
3190 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3191 if (sctx->b.chip_class >= CIK)
3192 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3193 }
3194
3195 /* GRBM_GFX_INDEX is privileged on VI */
3196 if (sctx->b.chip_class <= CIK)
3197 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3198 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3199 INSTANCE_BROADCAST_WRITES);
3200 }
3201
3202 static void si_init_config(struct si_context *sctx)
3203 {
3204 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3205 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3206 unsigned raster_config, raster_config_1;
3207 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3208 int i;
3209
3210 if (pm4 == NULL)
3211 return;
3212
3213 si_cmd_context_control(pm4);
3214
3215 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3216 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3217
3218 /* FIXME calculate these values somehow ??? */
3219 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3220 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3221 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3222
3223 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3224 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3225 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3226
3227 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3228 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3229 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3230 if (sctx->b.chip_class < CIK)
3231 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3232 S_008A14_CLIP_VTX_REORDER_ENA(1));
3233
3234 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3235 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3236
3237 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3238
3239 for (i = 0; i < 16; i++) {
3240 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3241 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3242 }
3243
3244 switch (sctx->screen->b.family) {
3245 case CHIP_TAHITI:
3246 case CHIP_PITCAIRN:
3247 raster_config = 0x2a00126a;
3248 raster_config_1 = 0x00000000;
3249 break;
3250 case CHIP_VERDE:
3251 raster_config = 0x0000124a;
3252 raster_config_1 = 0x00000000;
3253 break;
3254 case CHIP_OLAND:
3255 raster_config = 0x00000082;
3256 raster_config_1 = 0x00000000;
3257 break;
3258 case CHIP_HAINAN:
3259 raster_config = 0x00000000;
3260 raster_config_1 = 0x00000000;
3261 break;
3262 case CHIP_BONAIRE:
3263 raster_config = 0x16000012;
3264 raster_config_1 = 0x00000000;
3265 break;
3266 case CHIP_HAWAII:
3267 raster_config = 0x3a00161a;
3268 raster_config_1 = 0x0000002e;
3269 break;
3270 case CHIP_FIJI:
3271 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3272 raster_config = 0x16000012; /* 0x3a00161a */
3273 raster_config_1 = 0x0000002a; /* 0x0000002e */
3274 break;
3275 case CHIP_TONGA:
3276 raster_config = 0x16000012;
3277 raster_config_1 = 0x0000002a;
3278 break;
3279 case CHIP_ICELAND:
3280 raster_config = 0x00000002;
3281 raster_config_1 = 0x00000000;
3282 break;
3283 case CHIP_CARRIZO:
3284 raster_config = 0x00000002;
3285 raster_config_1 = 0x00000000;
3286 break;
3287 case CHIP_KAVERI:
3288 /* KV should be 0x00000002, but that causes problems with radeon */
3289 raster_config = 0x00000000; /* 0x00000002 */
3290 raster_config_1 = 0x00000000;
3291 break;
3292 case CHIP_KABINI:
3293 case CHIP_MULLINS:
3294 raster_config = 0x00000000;
3295 raster_config_1 = 0x00000000;
3296 break;
3297 default:
3298 fprintf(stderr,
3299 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3300 raster_config = 0x00000000;
3301 raster_config_1 = 0x00000000;
3302 break;
3303 }
3304
3305 /* Always use the default config when all backends are enabled
3306 * (or when we failed to determine the enabled backends).
3307 */
3308 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3309 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3310 raster_config);
3311 if (sctx->b.chip_class >= CIK)
3312 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3313 raster_config_1);
3314 } else {
3315 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3316 }
3317
3318 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3319 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3320 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3321 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3322 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3323 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3324 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3325
3326 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3327 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3328 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3329 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3330 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3331 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3332 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3333 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3334 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3335 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3336 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3337 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3338 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3339
3340 /* There is a hang if stencil is used and fast stencil is enabled
3341 * regardless of whether HTILE is depth-only or not.
3342 */
3343 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3344 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3345 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3346 S_02800C_FAST_STENCIL_DISABLE(1));
3347
3348 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3349 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3350 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3351
3352 if (sctx->b.chip_class >= CIK) {
3353 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3354 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3355 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3356 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3357 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3358 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3359 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3360 }
3361
3362 if (sctx->b.chip_class >= VI) {
3363 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3364 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3365 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3366 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3367 }
3368
3369 sctx->init_config = pm4;
3370 }