2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
37 static unsigned si_map_swizzle(unsigned swizzle
)
41 return V_008F0C_SQ_SEL_Y
;
43 return V_008F0C_SQ_SEL_Z
;
45 return V_008F0C_SQ_SEL_W
;
47 return V_008F0C_SQ_SEL_0
;
49 return V_008F0C_SQ_SEL_1
;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X
;
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x
)
59 x
>= 4096 ? 0xffff : x
* 16;
63 * Inferred framebuffer and blender state.
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
68 static void si_emit_cb_render_state(struct si_context
*sctx
)
70 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
71 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
78 cb_target_mask
&= blend
->cb_target_mask
;
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
86 if (blend
&& blend
->dual_src_blend
&&
87 sctx
->ps_shader
.cso
&&
88 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
91 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
92 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
94 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
95 * I think we don't have to do anything between IBs.
97 if (sctx
->screen
->dfsm_allowed
&&
98 sctx
->last_cb_target_mask
!= cb_target_mask
) {
99 sctx
->last_cb_target_mask
= cb_target_mask
;
101 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
102 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
105 if (sctx
->chip_class
>= VI
) {
106 /* DCC MSAA workaround for blending.
107 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
108 * COMBINER_DISABLE, but that would be more complicated.
110 bool oc_disable
= (sctx
->chip_class
== VI
||
111 sctx
->chip_class
== GFX9
) &&
113 blend
->blend_enable_4bit
& cb_target_mask
&&
114 sctx
->framebuffer
.nr_samples
>= 2;
116 radeon_opt_set_context_reg(
117 sctx
, R_028424_CB_DCC_CONTROL
,
118 SI_TRACKED_CB_DCC_CONTROL
,
119 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
120 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
121 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
));
124 /* RB+ register settings. */
125 if (sctx
->screen
->rbplus_allowed
) {
126 unsigned spi_shader_col_format
=
127 sctx
->ps_shader
.cso
?
128 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
129 unsigned sx_ps_downconvert
= 0;
130 unsigned sx_blend_opt_epsilon
= 0;
131 unsigned sx_blend_opt_control
= 0;
133 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
134 struct si_surface
*surf
=
135 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
136 unsigned format
, swap
, spi_format
, colormask
;
137 bool has_alpha
, has_rgb
;
142 format
= G_028C70_FORMAT(surf
->cb_color_info
);
143 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
144 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
145 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
147 /* Set if RGB and A are present. */
148 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
150 if (format
== V_028C70_COLOR_8
||
151 format
== V_028C70_COLOR_16
||
152 format
== V_028C70_COLOR_32
)
153 has_rgb
= !has_alpha
;
157 /* Check the colormask and export format. */
158 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
160 if (!(colormask
& PIPE_MASK_A
))
163 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
168 /* Disable value checking for disabled channels. */
170 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
172 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
174 /* Enable down-conversion for 32bpp and smaller formats. */
176 case V_028C70_COLOR_8
:
177 case V_028C70_COLOR_8_8
:
178 case V_028C70_COLOR_8_8_8_8
:
179 /* For 1 and 2-channel formats, use the superset thereof. */
180 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
181 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
182 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
183 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
184 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
188 case V_028C70_COLOR_5_6_5
:
189 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
190 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
191 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
195 case V_028C70_COLOR_1_5_5_5
:
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
197 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
198 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
202 case V_028C70_COLOR_4_4_4_4
:
203 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
204 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
205 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
209 case V_028C70_COLOR_32
:
210 if (swap
== V_028C70_SWAP_STD
&&
211 spi_format
== V_028714_SPI_SHADER_32_R
)
212 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
213 else if (swap
== V_028C70_SWAP_ALT_REV
&&
214 spi_format
== V_028714_SPI_SHADER_32_AR
)
215 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
218 case V_028C70_COLOR_16
:
219 case V_028C70_COLOR_16_16
:
220 /* For 1-channel formats, use the superset thereof. */
221 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
222 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
223 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
224 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
225 if (swap
== V_028C70_SWAP_STD
||
226 swap
== V_028C70_SWAP_STD_REV
)
227 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
229 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
233 case V_028C70_COLOR_10_11_11
:
234 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
235 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
236 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
240 case V_028C70_COLOR_2_10_10_10
:
241 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
242 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
243 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
249 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
250 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
251 SI_TRACKED_SX_PS_DOWNCONVERT
,
252 sx_ps_downconvert
, sx_blend_opt_epsilon
,
253 sx_blend_opt_control
);
261 static uint32_t si_translate_blend_function(int blend_func
)
263 switch (blend_func
) {
265 return V_028780_COMB_DST_PLUS_SRC
;
266 case PIPE_BLEND_SUBTRACT
:
267 return V_028780_COMB_SRC_MINUS_DST
;
268 case PIPE_BLEND_REVERSE_SUBTRACT
:
269 return V_028780_COMB_DST_MINUS_SRC
;
271 return V_028780_COMB_MIN_DST_SRC
;
273 return V_028780_COMB_MAX_DST_SRC
;
275 PRINT_ERR("Unknown blend function %d\n", blend_func
);
282 static uint32_t si_translate_blend_factor(int blend_fact
)
284 switch (blend_fact
) {
285 case PIPE_BLENDFACTOR_ONE
:
286 return V_028780_BLEND_ONE
;
287 case PIPE_BLENDFACTOR_SRC_COLOR
:
288 return V_028780_BLEND_SRC_COLOR
;
289 case PIPE_BLENDFACTOR_SRC_ALPHA
:
290 return V_028780_BLEND_SRC_ALPHA
;
291 case PIPE_BLENDFACTOR_DST_ALPHA
:
292 return V_028780_BLEND_DST_ALPHA
;
293 case PIPE_BLENDFACTOR_DST_COLOR
:
294 return V_028780_BLEND_DST_COLOR
;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
297 case PIPE_BLENDFACTOR_CONST_COLOR
:
298 return V_028780_BLEND_CONSTANT_COLOR
;
299 case PIPE_BLENDFACTOR_CONST_ALPHA
:
300 return V_028780_BLEND_CONSTANT_ALPHA
;
301 case PIPE_BLENDFACTOR_ZERO
:
302 return V_028780_BLEND_ZERO
;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
315 case PIPE_BLENDFACTOR_SRC1_COLOR
:
316 return V_028780_BLEND_SRC1_COLOR
;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
318 return V_028780_BLEND_SRC1_ALPHA
;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
320 return V_028780_BLEND_INV_SRC1_COLOR
;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
322 return V_028780_BLEND_INV_SRC1_ALPHA
;
324 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
331 static uint32_t si_translate_blend_opt_function(int blend_func
)
333 switch (blend_func
) {
335 return V_028760_OPT_COMB_ADD
;
336 case PIPE_BLEND_SUBTRACT
:
337 return V_028760_OPT_COMB_SUBTRACT
;
338 case PIPE_BLEND_REVERSE_SUBTRACT
:
339 return V_028760_OPT_COMB_REVSUBTRACT
;
341 return V_028760_OPT_COMB_MIN
;
343 return V_028760_OPT_COMB_MAX
;
345 return V_028760_OPT_COMB_BLEND_DISABLED
;
349 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
351 switch (blend_fact
) {
352 case PIPE_BLENDFACTOR_ZERO
:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
354 case PIPE_BLENDFACTOR_ONE
:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
356 case PIPE_BLENDFACTOR_SRC_COLOR
:
357 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
360 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
362 case PIPE_BLENDFACTOR_SRC_ALPHA
:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
367 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
374 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
375 struct si_state_blend
*blend
,
376 enum pipe_blend_func func
,
377 enum pipe_blendfactor src
,
378 enum pipe_blendfactor dst
,
381 /* Src factor is allowed when it does not depend on Dst */
382 static const uint32_t src_allowed
=
383 (1u << PIPE_BLENDFACTOR_ONE
) |
384 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
386 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
387 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
388 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
389 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
391 (1u << PIPE_BLENDFACTOR_ZERO
) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
393 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
395 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
399 if (dst
== PIPE_BLENDFACTOR_ONE
&&
400 (src_allowed
& (1u << src
))) {
401 /* Addition is commutative, but floating point addition isn't
402 * associative: subtle changes can be introduced via different
405 * Out-of-order is also non-deterministic, which means that
406 * this breaks OpenGL invariance requirements. So only enable
407 * out-of-order additive blending if explicitly allowed by a
410 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
411 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
412 blend
->commutative_4bit
|= chanmask
;
417 * Get rid of DST in the blend factors by commuting the operands:
418 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
420 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
421 unsigned *dst_factor
, unsigned expected_dst
,
422 unsigned replacement_src
)
424 if (*src_factor
== expected_dst
&&
425 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
426 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
427 *dst_factor
= replacement_src
;
429 /* Commuting the operands requires reversing subtractions. */
430 if (*func
== PIPE_BLEND_SUBTRACT
)
431 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
432 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
433 *func
= PIPE_BLEND_SUBTRACT
;
437 static bool si_blend_factor_uses_dst(unsigned factor
)
439 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
440 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
441 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
442 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
443 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
446 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
447 const struct pipe_blend_state
*state
,
450 struct si_context
*sctx
= (struct si_context
*)ctx
;
451 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
452 struct si_pm4_state
*pm4
= &blend
->pm4
;
453 uint32_t sx_mrt_blend_opt
[8] = {0};
454 uint32_t color_control
= 0;
459 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
460 blend
->alpha_to_one
= state
->alpha_to_one
;
461 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
462 blend
->logicop_enable
= state
->logicop_enable
;
464 if (state
->logicop_enable
) {
465 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
467 color_control
|= S_028808_ROP3(0xcc);
470 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
471 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
472 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
475 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
477 if (state
->alpha_to_coverage
)
478 blend
->need_src_alpha_4bit
|= 0xf;
480 blend
->cb_target_mask
= 0;
481 blend
->cb_target_enabled_4bit
= 0;
483 for (int i
= 0; i
< 8; i
++) {
484 /* state->rt entries > 0 only written if independent blending */
485 const int j
= state
->independent_blend_enable
? i
: 0;
487 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
488 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
489 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
490 unsigned eqA
= state
->rt
[j
].alpha_func
;
491 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
492 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
494 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
495 unsigned blend_cntl
= 0;
497 sx_mrt_blend_opt
[i
] =
498 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
499 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
501 /* Only set dual source blending for MRT0 to avoid a hang. */
502 if (i
>= 1 && blend
->dual_src_blend
) {
503 /* Vulkan does this for dual source blending. */
505 blend_cntl
|= S_028780_ENABLE(1);
507 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
511 /* Only addition and subtraction equations are supported with
512 * dual source blending.
514 if (blend
->dual_src_blend
&&
515 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
516 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
517 assert(!"Unsupported equation for dual source blending");
518 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
522 /* cb_render_state will disable unused ones */
523 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
524 if (state
->rt
[j
].colormask
)
525 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
527 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
528 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
532 si_blend_check_commutativity(sctx
->screen
, blend
,
533 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
534 si_blend_check_commutativity(sctx
->screen
, blend
,
535 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
537 /* Blending optimizations for RB+.
538 * These transformations don't change the behavior.
540 * First, get rid of DST in the blend factors:
541 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
543 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
544 PIPE_BLENDFACTOR_DST_COLOR
,
545 PIPE_BLENDFACTOR_SRC_COLOR
);
546 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
547 PIPE_BLENDFACTOR_DST_COLOR
,
548 PIPE_BLENDFACTOR_SRC_COLOR
);
549 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
550 PIPE_BLENDFACTOR_DST_ALPHA
,
551 PIPE_BLENDFACTOR_SRC_ALPHA
);
553 /* Look up the ideal settings from tables. */
554 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
555 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
556 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
557 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
559 /* Handle interdependencies. */
560 if (si_blend_factor_uses_dst(srcRGB
))
561 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
562 if (si_blend_factor_uses_dst(srcA
))
563 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
565 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
566 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
567 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
568 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
569 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
571 /* Set the final value. */
572 sx_mrt_blend_opt
[i
] =
573 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
574 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
575 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
576 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
577 S_028760_ALPHA_DST_OPT(dstA_opt
) |
578 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
580 /* Set blend state. */
581 blend_cntl
|= S_028780_ENABLE(1);
582 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
583 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
584 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
586 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
587 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
588 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
589 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
590 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
592 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
594 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
596 /* This is only important for formats without alpha. */
597 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
598 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
599 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
600 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
601 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
602 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
603 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
606 if (blend
->cb_target_mask
) {
607 color_control
|= S_028808_MODE(mode
);
609 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
612 if (sctx
->screen
->rbplus_allowed
) {
613 /* Disable RB+ blend optimizations for dual source blending.
616 if (blend
->dual_src_blend
) {
617 for (int i
= 0; i
< 8; i
++) {
618 sx_mrt_blend_opt
[i
] =
619 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
620 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
624 for (int i
= 0; i
< 8; i
++)
625 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
626 sx_mrt_blend_opt
[i
]);
628 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
629 if (blend
->dual_src_blend
|| state
->logicop_enable
||
630 mode
== V_028808_CB_RESOLVE
)
631 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
634 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
638 static void *si_create_blend_state(struct pipe_context
*ctx
,
639 const struct pipe_blend_state
*state
)
641 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
644 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
646 struct si_context
*sctx
= (struct si_context
*)ctx
;
647 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
648 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
653 si_pm4_bind_state(sctx
, blend
, state
);
656 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
657 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
658 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
659 sctx
->framebuffer
.nr_samples
>= 2 &&
660 sctx
->screen
->dcc_msaa_allowed
))
661 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
664 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
665 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
666 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
667 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
668 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
669 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
670 sctx
->do_update_shaders
= true;
672 if (sctx
->screen
->dpbb_allowed
&&
674 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
675 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
676 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
677 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
679 if (sctx
->screen
->has_out_of_order_rast
&&
681 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
682 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
683 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
684 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
685 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
688 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
690 struct si_context
*sctx
= (struct si_context
*)ctx
;
691 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
694 static void si_set_blend_color(struct pipe_context
*ctx
,
695 const struct pipe_blend_color
*state
)
697 struct si_context
*sctx
= (struct si_context
*)ctx
;
698 static const struct pipe_blend_color zeros
;
700 sctx
->blend_color
.state
= *state
;
701 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
702 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
705 static void si_emit_blend_color(struct si_context
*sctx
)
707 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
709 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
710 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
717 static void si_set_clip_state(struct pipe_context
*ctx
,
718 const struct pipe_clip_state
*state
)
720 struct si_context
*sctx
= (struct si_context
*)ctx
;
721 struct pipe_constant_buffer cb
;
722 static const struct pipe_clip_state zeros
;
724 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
727 sctx
->clip_state
.state
= *state
;
728 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
729 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
732 cb
.user_buffer
= state
->ucp
;
733 cb
.buffer_offset
= 0;
734 cb
.buffer_size
= 4*4*8;
735 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
736 pipe_resource_reference(&cb
.buffer
, NULL
);
739 static void si_emit_clip_state(struct si_context
*sctx
)
741 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
743 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
744 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
747 static void si_emit_clip_regs(struct si_context
*sctx
)
749 struct si_shader
*vs
= si_get_vs_state(sctx
);
750 struct si_shader_selector
*vs_sel
= vs
->selector
;
751 struct tgsi_shader_info
*info
= &vs_sel
->info
;
752 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
753 unsigned window_space
=
754 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
755 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
756 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
757 unsigned culldist_mask
= vs_sel
->culldist_mask
;
760 if (vs
->key
.opt
.clip_disable
) {
761 assert(!info
->culldist_writemask
);
765 total_mask
= clipdist_mask
| culldist_mask
;
767 /* Clip distances on points have no effect, so need to be implemented
768 * as cull distances. This applies for the clipvertex case as well.
770 * Setting this for primitives other than points should have no adverse
773 clipdist_mask
&= rs
->clip_plane_enable
;
774 culldist_mask
|= clipdist_mask
;
776 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
777 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
778 vs_sel
->pa_cl_vs_out_cntl
|
779 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
780 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
781 clipdist_mask
| (culldist_mask
<< 8));
782 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
783 SI_TRACKED_PA_CL_CLIP_CNTL
,
784 rs
->pa_cl_clip_cntl
|
786 S_028810_CLIP_DISABLE(window_space
));
790 * inferred state between framebuffer and rasterizer
792 static void si_update_poly_offset_state(struct si_context
*sctx
)
794 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
796 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
797 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
801 /* Use the user format, not db_render_format, so that the polygon
802 * offset behaves as expected by applications.
804 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
805 case PIPE_FORMAT_Z16_UNORM
:
806 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
808 default: /* 24-bit */
809 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
811 case PIPE_FORMAT_Z32_FLOAT
:
812 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
813 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
822 static uint32_t si_translate_fill(uint32_t func
)
825 case PIPE_POLYGON_MODE_FILL
:
826 return V_028814_X_DRAW_TRIANGLES
;
827 case PIPE_POLYGON_MODE_LINE
:
828 return V_028814_X_DRAW_LINES
;
829 case PIPE_POLYGON_MODE_POINT
:
830 return V_028814_X_DRAW_POINTS
;
833 return V_028814_X_DRAW_POINTS
;
837 static void *si_create_rs_state(struct pipe_context
*ctx
,
838 const struct pipe_rasterizer_state
*state
)
840 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
841 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
842 struct si_pm4_state
*pm4
= &rs
->pm4
;
844 float psize_min
, psize_max
;
850 rs
->scissor_enable
= state
->scissor
;
851 rs
->clip_halfz
= state
->clip_halfz
;
852 rs
->two_side
= state
->light_twoside
;
853 rs
->multisample_enable
= state
->multisample
;
854 rs
->force_persample_interp
= state
->force_persample_interp
;
855 rs
->clip_plane_enable
= state
->clip_plane_enable
;
856 rs
->half_pixel_center
= state
->half_pixel_center
;
857 rs
->line_stipple_enable
= state
->line_stipple_enable
;
858 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
859 rs
->line_smooth
= state
->line_smooth
;
860 rs
->line_width
= state
->line_width
;
861 rs
->poly_smooth
= state
->poly_smooth
;
862 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
864 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
865 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
866 rs
->flatshade
= state
->flatshade
;
867 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
868 rs
->rasterizer_discard
= state
->rasterizer_discard
;
869 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
870 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
871 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
872 rs
->pa_cl_clip_cntl
=
873 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
874 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
875 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
876 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
877 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
879 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
880 S_0286D4_FLAT_SHADE_ENA(1) |
881 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
882 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
883 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
884 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
885 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
886 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
888 /* point size 12.4 fixed point */
889 tmp
= (unsigned)(state
->point_size
* 8.0);
890 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
892 if (state
->point_size_per_vertex
) {
893 psize_min
= util_get_min_point_size(state
);
896 /* Force the point size to be as if the vertex output was disabled. */
897 psize_min
= state
->point_size
;
898 psize_max
= state
->point_size
;
900 rs
->max_point_size
= psize_max
;
902 /* Divide by two, because 0.5 = 1 pixel. */
903 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
904 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
905 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
907 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
908 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
909 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
910 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
911 S_028A48_MSAA_ENABLE(state
->multisample
||
912 state
->poly_smooth
||
913 state
->line_smooth
) |
914 S_028A48_VPORT_SCISSOR_ENABLE(1) |
915 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
917 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
918 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
919 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
920 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
921 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
922 S_028814_FACE(!state
->front_ccw
) |
923 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
924 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
925 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
926 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
927 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
928 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
929 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
931 if (!rs
->uses_poly_offset
)
934 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
935 if (!rs
->pm4_poly_offset
) {
940 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
941 for (i
= 0; i
< 3; i
++) {
942 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
943 float offset_units
= state
->offset_units
;
944 float offset_scale
= state
->offset_scale
* 16.0f
;
945 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
947 if (!state
->offset_units_unscaled
) {
949 case 0: /* 16-bit zbuffer */
950 offset_units
*= 4.0f
;
951 pa_su_poly_offset_db_fmt_cntl
=
952 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
954 case 1: /* 24-bit zbuffer */
955 offset_units
*= 2.0f
;
956 pa_su_poly_offset_db_fmt_cntl
=
957 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
959 case 2: /* 32-bit zbuffer */
960 offset_units
*= 1.0f
;
961 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
962 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
967 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
969 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
971 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
973 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
975 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
976 pa_su_poly_offset_db_fmt_cntl
);
982 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
984 struct si_context
*sctx
= (struct si_context
*)ctx
;
985 struct si_state_rasterizer
*old_rs
=
986 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
987 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
992 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
993 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
995 /* Update the small primitive filter workaround if necessary. */
996 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
997 sctx
->framebuffer
.nr_samples
> 1)
998 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1001 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1002 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1004 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1005 si_update_poly_offset_state(sctx
);
1008 old_rs
->scissor_enable
!= rs
->scissor_enable
) {
1009 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1010 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1014 old_rs
->line_width
!= rs
->line_width
||
1015 old_rs
->max_point_size
!= rs
->max_point_size
||
1016 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1017 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1020 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1021 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1022 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1026 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1027 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1028 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1030 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1031 rs
->line_stipple_enable
;
1034 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1035 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1036 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1037 old_rs
->flatshade
!= rs
->flatshade
||
1038 old_rs
->two_side
!= rs
->two_side
||
1039 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1040 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1041 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1042 old_rs
->line_smooth
!= rs
->line_smooth
||
1043 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1044 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1045 sctx
->do_update_shaders
= true;
1048 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1050 struct si_context
*sctx
= (struct si_context
*)ctx
;
1051 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1053 if (sctx
->queued
.named
.rasterizer
== state
)
1054 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1056 FREE(rs
->pm4_poly_offset
);
1057 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1061 * infeered state between dsa and stencil ref
1063 static void si_emit_stencil_ref(struct si_context
*sctx
)
1065 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1066 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1067 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1069 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1070 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1071 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1072 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1073 S_028430_STENCILOPVAL(1));
1074 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1075 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1076 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1077 S_028434_STENCILOPVAL_BF(1));
1080 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1081 const struct pipe_stencil_ref
*state
)
1083 struct si_context
*sctx
= (struct si_context
*)ctx
;
1085 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1088 sctx
->stencil_ref
.state
= *state
;
1089 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1097 static uint32_t si_translate_stencil_op(int s_op
)
1100 case PIPE_STENCIL_OP_KEEP
:
1101 return V_02842C_STENCIL_KEEP
;
1102 case PIPE_STENCIL_OP_ZERO
:
1103 return V_02842C_STENCIL_ZERO
;
1104 case PIPE_STENCIL_OP_REPLACE
:
1105 return V_02842C_STENCIL_REPLACE_TEST
;
1106 case PIPE_STENCIL_OP_INCR
:
1107 return V_02842C_STENCIL_ADD_CLAMP
;
1108 case PIPE_STENCIL_OP_DECR
:
1109 return V_02842C_STENCIL_SUB_CLAMP
;
1110 case PIPE_STENCIL_OP_INCR_WRAP
:
1111 return V_02842C_STENCIL_ADD_WRAP
;
1112 case PIPE_STENCIL_OP_DECR_WRAP
:
1113 return V_02842C_STENCIL_SUB_WRAP
;
1114 case PIPE_STENCIL_OP_INVERT
:
1115 return V_02842C_STENCIL_INVERT
;
1117 PRINT_ERR("Unknown stencil op %d", s_op
);
1124 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1126 return s
->enabled
&& s
->writemask
&&
1127 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1128 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1129 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1132 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1134 /* REPLACE is normally order invariant, except when the stencil
1135 * reference value is written by the fragment shader. Tracking this
1136 * interaction does not seem worth the effort, so be conservative. */
1137 return op
!= PIPE_STENCIL_OP_INCR
&&
1138 op
!= PIPE_STENCIL_OP_DECR
&&
1139 op
!= PIPE_STENCIL_OP_REPLACE
;
1142 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1143 * invariant in the sense that the set of passing fragments as well as the
1144 * final stencil buffer result does not depend on the order of fragments. */
1145 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1147 return !state
->enabled
|| !state
->writemask
||
1148 /* The following assumes that Z writes are disabled. */
1149 (state
->func
== PIPE_FUNC_ALWAYS
&&
1150 si_order_invariant_stencil_op(state
->zpass_op
) &&
1151 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1152 (state
->func
== PIPE_FUNC_NEVER
&&
1153 si_order_invariant_stencil_op(state
->fail_op
));
1156 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1157 const struct pipe_depth_stencil_alpha_state
*state
)
1159 struct si_context
*sctx
= (struct si_context
*)ctx
;
1160 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1161 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1162 unsigned db_depth_control
;
1163 uint32_t db_stencil_control
= 0;
1169 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1170 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1171 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1172 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1174 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1175 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1176 S_028800_ZFUNC(state
->depth
.func
) |
1177 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1180 if (state
->stencil
[0].enabled
) {
1181 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1182 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1183 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1184 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1185 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1187 if (state
->stencil
[1].enabled
) {
1188 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1189 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1190 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1191 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1192 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1197 if (state
->alpha
.enabled
) {
1198 dsa
->alpha_func
= state
->alpha
.func
;
1200 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1201 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1203 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1206 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1207 if (state
->stencil
[0].enabled
)
1208 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1209 if (state
->depth
.bounds_test
) {
1210 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1211 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1214 dsa
->depth_enabled
= state
->depth
.enabled
;
1215 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1216 state
->depth
.writemask
;
1217 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1218 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1219 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1220 si_dsa_writes_stencil(&state
->stencil
[1]));
1221 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1222 dsa
->stencil_write_enabled
;
1224 bool zfunc_is_ordered
=
1225 state
->depth
.func
== PIPE_FUNC_NEVER
||
1226 state
->depth
.func
== PIPE_FUNC_LESS
||
1227 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1228 state
->depth
.func
== PIPE_FUNC_GREATER
||
1229 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1231 bool nozwrite_and_order_invariant_stencil
=
1232 !dsa
->db_can_write
||
1233 (!dsa
->depth_write_enabled
&&
1234 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1235 si_order_invariant_stencil_state(&state
->stencil
[1]));
1237 dsa
->order_invariance
[1].zs
=
1238 nozwrite_and_order_invariant_stencil
||
1239 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1240 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1242 dsa
->order_invariance
[1].pass_set
=
1243 nozwrite_and_order_invariant_stencil
||
1244 (!dsa
->stencil_write_enabled
&&
1245 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1246 state
->depth
.func
== PIPE_FUNC_NEVER
));
1247 dsa
->order_invariance
[0].pass_set
=
1248 !dsa
->depth_write_enabled
||
1249 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1250 state
->depth
.func
== PIPE_FUNC_NEVER
);
1252 dsa
->order_invariance
[1].pass_last
=
1253 sctx
->screen
->assume_no_z_fights
&&
1254 !dsa
->stencil_write_enabled
&&
1255 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1256 dsa
->order_invariance
[0].pass_last
=
1257 sctx
->screen
->assume_no_z_fights
&&
1258 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1263 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1265 struct si_context
*sctx
= (struct si_context
*)ctx
;
1266 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1267 struct si_state_dsa
*dsa
= state
;
1272 si_pm4_bind_state(sctx
, dsa
, dsa
);
1274 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1275 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1276 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1277 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1280 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1281 sctx
->do_update_shaders
= true;
1283 if (sctx
->screen
->dpbb_allowed
&&
1285 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1286 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1287 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1288 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1290 if (sctx
->screen
->has_out_of_order_rast
&&
1292 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1293 sizeof(old_dsa
->order_invariance
))))
1294 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1297 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1299 struct si_context
*sctx
= (struct si_context
*)ctx
;
1300 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1303 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1305 struct pipe_depth_stencil_alpha_state dsa
= {};
1307 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1310 /* DB RENDER STATE */
1312 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1314 struct si_context
*sctx
= (struct si_context
*)ctx
;
1316 /* Pipeline stat & streamout queries. */
1318 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1319 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1321 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1322 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1325 /* Occlusion queries. */
1326 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1327 sctx
->occlusion_queries_disabled
= !enable
;
1328 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1332 void si_set_occlusion_query_state(struct si_context
*sctx
,
1333 bool old_perfect_enable
)
1335 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1337 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1339 if (perfect_enable
!= old_perfect_enable
)
1340 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1343 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1345 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1347 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1348 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1351 static void si_emit_db_render_state(struct si_context
*sctx
)
1353 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1354 unsigned db_shader_control
, db_render_control
, db_count_control
;
1356 /* DB_RENDER_CONTROL */
1357 if (sctx
->dbcb_depth_copy_enabled
||
1358 sctx
->dbcb_stencil_copy_enabled
) {
1360 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1361 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1362 S_028000_COPY_CENTROID(1) |
1363 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1364 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1366 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1367 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1370 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1371 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1374 /* DB_COUNT_CONTROL (occlusion queries) */
1375 if (sctx
->num_occlusion_queries
> 0 &&
1376 !sctx
->occlusion_queries_disabled
) {
1377 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1379 if (sctx
->chip_class
>= CIK
) {
1380 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1382 /* Stoney doesn't increment occlusion query counters
1383 * if the sample rate is 16x. Use 8x sample rate instead.
1385 if (sctx
->family
== CHIP_STONEY
)
1386 log_sample_rate
= MIN2(log_sample_rate
, 3);
1389 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1390 S_028004_SAMPLE_RATE(log_sample_rate
) |
1391 S_028004_ZPASS_ENABLE(1) |
1392 S_028004_SLICE_EVEN_ENABLE(1) |
1393 S_028004_SLICE_ODD_ENABLE(1);
1396 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1397 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1400 /* Disable occlusion queries. */
1401 if (sctx
->chip_class
>= CIK
) {
1402 db_count_control
= 0;
1404 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1408 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1409 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1412 /* DB_RENDER_OVERRIDE2 */
1413 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1414 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1415 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1416 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1417 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1419 db_shader_control
= sctx
->ps_db_shader_control
;
1421 /* Bug workaround for smoothing (overrasterization) on SI. */
1422 if (sctx
->chip_class
== SI
&& sctx
->smoothing_enabled
) {
1423 db_shader_control
&= C_02880C_Z_ORDER
;
1424 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1427 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1428 if (!rs
->multisample_enable
)
1429 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1431 if (sctx
->screen
->has_rbplus
&&
1432 !sctx
->screen
->rbplus_allowed
)
1433 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1435 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1436 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1440 * format translation
1442 static uint32_t si_translate_colorformat(enum pipe_format format
)
1444 const struct util_format_description
*desc
= util_format_description(format
);
1446 return V_028C70_COLOR_INVALID
;
1448 #define HAS_SIZE(x,y,z,w) \
1449 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1450 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1452 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1453 return V_028C70_COLOR_10_11_11
;
1455 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1456 return V_028C70_COLOR_INVALID
;
1458 /* hw cannot support mixed formats (except depth/stencil, since
1459 * stencil is not written to). */
1460 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1461 return V_028C70_COLOR_INVALID
;
1463 switch (desc
->nr_channels
) {
1465 switch (desc
->channel
[0].size
) {
1467 return V_028C70_COLOR_8
;
1469 return V_028C70_COLOR_16
;
1471 return V_028C70_COLOR_32
;
1475 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1476 switch (desc
->channel
[0].size
) {
1478 return V_028C70_COLOR_8_8
;
1480 return V_028C70_COLOR_16_16
;
1482 return V_028C70_COLOR_32_32
;
1484 } else if (HAS_SIZE(8,24,0,0)) {
1485 return V_028C70_COLOR_24_8
;
1486 } else if (HAS_SIZE(24,8,0,0)) {
1487 return V_028C70_COLOR_8_24
;
1491 if (HAS_SIZE(5,6,5,0)) {
1492 return V_028C70_COLOR_5_6_5
;
1493 } else if (HAS_SIZE(32,8,24,0)) {
1494 return V_028C70_COLOR_X24_8_32_FLOAT
;
1498 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1499 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1500 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1501 switch (desc
->channel
[0].size
) {
1503 return V_028C70_COLOR_4_4_4_4
;
1505 return V_028C70_COLOR_8_8_8_8
;
1507 return V_028C70_COLOR_16_16_16_16
;
1509 return V_028C70_COLOR_32_32_32_32
;
1511 } else if (HAS_SIZE(5,5,5,1)) {
1512 return V_028C70_COLOR_1_5_5_5
;
1513 } else if (HAS_SIZE(1,5,5,5)) {
1514 return V_028C70_COLOR_5_5_5_1
;
1515 } else if (HAS_SIZE(10,10,10,2)) {
1516 return V_028C70_COLOR_2_10_10_10
;
1520 return V_028C70_COLOR_INVALID
;
1523 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1525 if (SI_BIG_ENDIAN
) {
1526 switch(colorformat
) {
1527 /* 8-bit buffers. */
1528 case V_028C70_COLOR_8
:
1529 return V_028C70_ENDIAN_NONE
;
1531 /* 16-bit buffers. */
1532 case V_028C70_COLOR_5_6_5
:
1533 case V_028C70_COLOR_1_5_5_5
:
1534 case V_028C70_COLOR_4_4_4_4
:
1535 case V_028C70_COLOR_16
:
1536 case V_028C70_COLOR_8_8
:
1537 return V_028C70_ENDIAN_8IN16
;
1539 /* 32-bit buffers. */
1540 case V_028C70_COLOR_8_8_8_8
:
1541 case V_028C70_COLOR_2_10_10_10
:
1542 case V_028C70_COLOR_8_24
:
1543 case V_028C70_COLOR_24_8
:
1544 case V_028C70_COLOR_16_16
:
1545 return V_028C70_ENDIAN_8IN32
;
1547 /* 64-bit buffers. */
1548 case V_028C70_COLOR_16_16_16_16
:
1549 return V_028C70_ENDIAN_8IN16
;
1551 case V_028C70_COLOR_32_32
:
1552 return V_028C70_ENDIAN_8IN32
;
1554 /* 128-bit buffers. */
1555 case V_028C70_COLOR_32_32_32_32
:
1556 return V_028C70_ENDIAN_8IN32
;
1558 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1561 return V_028C70_ENDIAN_NONE
;
1565 static uint32_t si_translate_dbformat(enum pipe_format format
)
1568 case PIPE_FORMAT_Z16_UNORM
:
1569 return V_028040_Z_16
;
1570 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1571 case PIPE_FORMAT_X8Z24_UNORM
:
1572 case PIPE_FORMAT_Z24X8_UNORM
:
1573 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1574 return V_028040_Z_24
; /* deprecated on SI */
1575 case PIPE_FORMAT_Z32_FLOAT
:
1576 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1577 return V_028040_Z_32_FLOAT
;
1579 return V_028040_Z_INVALID
;
1584 * Texture translation
1587 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1588 enum pipe_format format
,
1589 const struct util_format_description
*desc
,
1592 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1593 bool uniform
= true;
1596 /* Colorspace (return non-RGB formats directly). */
1597 switch (desc
->colorspace
) {
1598 /* Depth stencil formats */
1599 case UTIL_FORMAT_COLORSPACE_ZS
:
1601 case PIPE_FORMAT_Z16_UNORM
:
1602 return V_008F14_IMG_DATA_FORMAT_16
;
1603 case PIPE_FORMAT_X24S8_UINT
:
1604 case PIPE_FORMAT_S8X24_UINT
:
1606 * Implemented as an 8_8_8_8 data format to fix texture
1607 * gathers in stencil sampling. This affects at least
1608 * GL45-CTS.texture_cube_map_array.sampling on VI.
1610 if (sscreen
->info
.chip_class
<= VI
)
1611 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1613 if (format
== PIPE_FORMAT_X24S8_UINT
)
1614 return V_008F14_IMG_DATA_FORMAT_8_24
;
1616 return V_008F14_IMG_DATA_FORMAT_24_8
;
1617 case PIPE_FORMAT_Z24X8_UNORM
:
1618 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1619 return V_008F14_IMG_DATA_FORMAT_8_24
;
1620 case PIPE_FORMAT_X8Z24_UNORM
:
1621 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1622 return V_008F14_IMG_DATA_FORMAT_24_8
;
1623 case PIPE_FORMAT_S8_UINT
:
1624 return V_008F14_IMG_DATA_FORMAT_8
;
1625 case PIPE_FORMAT_Z32_FLOAT
:
1626 return V_008F14_IMG_DATA_FORMAT_32
;
1627 case PIPE_FORMAT_X32_S8X24_UINT
:
1628 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1629 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1634 case UTIL_FORMAT_COLORSPACE_YUV
:
1635 goto out_unknown
; /* TODO */
1637 case UTIL_FORMAT_COLORSPACE_SRGB
:
1638 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1646 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1647 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1651 case PIPE_FORMAT_RGTC1_SNORM
:
1652 case PIPE_FORMAT_LATC1_SNORM
:
1653 case PIPE_FORMAT_RGTC1_UNORM
:
1654 case PIPE_FORMAT_LATC1_UNORM
:
1655 return V_008F14_IMG_DATA_FORMAT_BC4
;
1656 case PIPE_FORMAT_RGTC2_SNORM
:
1657 case PIPE_FORMAT_LATC2_SNORM
:
1658 case PIPE_FORMAT_RGTC2_UNORM
:
1659 case PIPE_FORMAT_LATC2_UNORM
:
1660 return V_008F14_IMG_DATA_FORMAT_BC5
;
1666 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1667 (sscreen
->info
.family
== CHIP_STONEY
||
1668 sscreen
->info
.family
== CHIP_VEGA10
||
1669 sscreen
->info
.family
== CHIP_RAVEN
)) {
1671 case PIPE_FORMAT_ETC1_RGB8
:
1672 case PIPE_FORMAT_ETC2_RGB8
:
1673 case PIPE_FORMAT_ETC2_SRGB8
:
1674 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1675 case PIPE_FORMAT_ETC2_RGB8A1
:
1676 case PIPE_FORMAT_ETC2_SRGB8A1
:
1677 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1678 case PIPE_FORMAT_ETC2_RGBA8
:
1679 case PIPE_FORMAT_ETC2_SRGBA8
:
1680 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1681 case PIPE_FORMAT_ETC2_R11_UNORM
:
1682 case PIPE_FORMAT_ETC2_R11_SNORM
:
1683 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1684 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1685 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1686 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1692 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1693 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1697 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1698 case PIPE_FORMAT_BPTC_SRGBA
:
1699 return V_008F14_IMG_DATA_FORMAT_BC7
;
1700 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1701 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1702 return V_008F14_IMG_DATA_FORMAT_BC6
;
1708 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1710 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1711 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1712 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1713 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1714 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1715 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1721 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1722 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1726 case PIPE_FORMAT_DXT1_RGB
:
1727 case PIPE_FORMAT_DXT1_RGBA
:
1728 case PIPE_FORMAT_DXT1_SRGB
:
1729 case PIPE_FORMAT_DXT1_SRGBA
:
1730 return V_008F14_IMG_DATA_FORMAT_BC1
;
1731 case PIPE_FORMAT_DXT3_RGBA
:
1732 case PIPE_FORMAT_DXT3_SRGBA
:
1733 return V_008F14_IMG_DATA_FORMAT_BC2
;
1734 case PIPE_FORMAT_DXT5_RGBA
:
1735 case PIPE_FORMAT_DXT5_SRGBA
:
1736 return V_008F14_IMG_DATA_FORMAT_BC3
;
1742 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1743 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1744 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1745 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1748 /* R8G8Bx_SNORM - TODO CxV8U8 */
1750 /* hw cannot support mixed formats (except depth/stencil, since only
1752 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1755 /* See whether the components are of the same size. */
1756 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1757 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1760 /* Non-uniform formats. */
1762 switch(desc
->nr_channels
) {
1764 if (desc
->channel
[0].size
== 5 &&
1765 desc
->channel
[1].size
== 6 &&
1766 desc
->channel
[2].size
== 5) {
1767 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1771 if (desc
->channel
[0].size
== 5 &&
1772 desc
->channel
[1].size
== 5 &&
1773 desc
->channel
[2].size
== 5 &&
1774 desc
->channel
[3].size
== 1) {
1775 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1777 if (desc
->channel
[0].size
== 1 &&
1778 desc
->channel
[1].size
== 5 &&
1779 desc
->channel
[2].size
== 5 &&
1780 desc
->channel
[3].size
== 5) {
1781 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1783 if (desc
->channel
[0].size
== 10 &&
1784 desc
->channel
[1].size
== 10 &&
1785 desc
->channel
[2].size
== 10 &&
1786 desc
->channel
[3].size
== 2) {
1787 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1794 if (first_non_void
< 0 || first_non_void
> 3)
1797 /* uniform formats */
1798 switch (desc
->channel
[first_non_void
].size
) {
1800 switch (desc
->nr_channels
) {
1801 #if 0 /* Not supported for render targets */
1803 return V_008F14_IMG_DATA_FORMAT_4_4
;
1806 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1810 switch (desc
->nr_channels
) {
1812 return V_008F14_IMG_DATA_FORMAT_8
;
1814 return V_008F14_IMG_DATA_FORMAT_8_8
;
1816 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1820 switch (desc
->nr_channels
) {
1822 return V_008F14_IMG_DATA_FORMAT_16
;
1824 return V_008F14_IMG_DATA_FORMAT_16_16
;
1826 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1830 switch (desc
->nr_channels
) {
1832 return V_008F14_IMG_DATA_FORMAT_32
;
1834 return V_008F14_IMG_DATA_FORMAT_32_32
;
1835 #if 0 /* Not supported for render targets */
1837 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1840 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1848 static unsigned si_tex_wrap(unsigned wrap
)
1852 case PIPE_TEX_WRAP_REPEAT
:
1853 return V_008F30_SQ_TEX_WRAP
;
1854 case PIPE_TEX_WRAP_CLAMP
:
1855 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1856 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1857 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1858 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1859 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1860 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1861 return V_008F30_SQ_TEX_MIRROR
;
1862 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1863 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1864 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1865 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1866 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1867 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1871 static unsigned si_tex_mipfilter(unsigned filter
)
1874 case PIPE_TEX_MIPFILTER_NEAREST
:
1875 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1876 case PIPE_TEX_MIPFILTER_LINEAR
:
1877 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1879 case PIPE_TEX_MIPFILTER_NONE
:
1880 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1884 static unsigned si_tex_compare(unsigned compare
)
1888 case PIPE_FUNC_NEVER
:
1889 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1890 case PIPE_FUNC_LESS
:
1891 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1892 case PIPE_FUNC_EQUAL
:
1893 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1894 case PIPE_FUNC_LEQUAL
:
1895 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1896 case PIPE_FUNC_GREATER
:
1897 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1898 case PIPE_FUNC_NOTEQUAL
:
1899 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1900 case PIPE_FUNC_GEQUAL
:
1901 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1902 case PIPE_FUNC_ALWAYS
:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1907 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1908 unsigned view_target
, unsigned nr_samples
)
1910 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1912 if (view_target
== PIPE_TEXTURE_CUBE
||
1913 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1914 res_target
= view_target
;
1915 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1916 else if (res_target
== PIPE_TEXTURE_CUBE
||
1917 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1918 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1920 /* GFX9 allocates 1D textures as 2D. */
1921 if ((res_target
== PIPE_TEXTURE_1D
||
1922 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1923 sscreen
->info
.chip_class
>= GFX9
&&
1924 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1925 if (res_target
== PIPE_TEXTURE_1D
)
1926 res_target
= PIPE_TEXTURE_2D
;
1928 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1931 switch (res_target
) {
1933 case PIPE_TEXTURE_1D
:
1934 return V_008F1C_SQ_RSRC_IMG_1D
;
1935 case PIPE_TEXTURE_1D_ARRAY
:
1936 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1937 case PIPE_TEXTURE_2D
:
1938 case PIPE_TEXTURE_RECT
:
1939 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1940 V_008F1C_SQ_RSRC_IMG_2D
;
1941 case PIPE_TEXTURE_2D_ARRAY
:
1942 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1943 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1944 case PIPE_TEXTURE_3D
:
1945 return V_008F1C_SQ_RSRC_IMG_3D
;
1946 case PIPE_TEXTURE_CUBE
:
1947 case PIPE_TEXTURE_CUBE_ARRAY
:
1948 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1953 * Format support testing
1956 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1958 const struct util_format_description
*desc
= util_format_description(format
);
1962 return si_translate_texformat(screen
, format
, desc
,
1963 util_format_get_first_non_void_channel(format
)) != ~0U;
1966 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1967 const struct util_format_description
*desc
,
1972 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1973 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1975 assert(first_non_void
>= 0);
1977 if (desc
->nr_channels
== 4 &&
1978 desc
->channel
[0].size
== 10 &&
1979 desc
->channel
[1].size
== 10 &&
1980 desc
->channel
[2].size
== 10 &&
1981 desc
->channel
[3].size
== 2)
1982 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1984 /* See whether the components are of the same size. */
1985 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1986 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1987 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1990 switch (desc
->channel
[first_non_void
].size
) {
1992 switch (desc
->nr_channels
) {
1994 case 3: /* 3 loads */
1995 return V_008F0C_BUF_DATA_FORMAT_8
;
1997 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1999 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2003 switch (desc
->nr_channels
) {
2005 case 3: /* 3 loads */
2006 return V_008F0C_BUF_DATA_FORMAT_16
;
2008 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2010 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2014 switch (desc
->nr_channels
) {
2016 return V_008F0C_BUF_DATA_FORMAT_32
;
2018 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2020 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2022 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2026 /* Legacy double formats. */
2027 switch (desc
->nr_channels
) {
2028 case 1: /* 1 load */
2029 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2030 case 2: /* 1 load */
2031 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2032 case 3: /* 3 loads */
2033 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2034 case 4: /* 2 loads */
2035 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2040 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2043 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2044 const struct util_format_description
*desc
,
2047 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2048 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2050 assert(first_non_void
>= 0);
2052 switch (desc
->channel
[first_non_void
].type
) {
2053 case UTIL_FORMAT_TYPE_SIGNED
:
2054 case UTIL_FORMAT_TYPE_FIXED
:
2055 if (desc
->channel
[first_non_void
].size
>= 32 ||
2056 desc
->channel
[first_non_void
].pure_integer
)
2057 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2058 else if (desc
->channel
[first_non_void
].normalized
)
2059 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2061 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2063 case UTIL_FORMAT_TYPE_UNSIGNED
:
2064 if (desc
->channel
[first_non_void
].size
>= 32 ||
2065 desc
->channel
[first_non_void
].pure_integer
)
2066 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2067 else if (desc
->channel
[first_non_void
].normalized
)
2068 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2070 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2072 case UTIL_FORMAT_TYPE_FLOAT
:
2074 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2078 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2079 enum pipe_format format
,
2082 const struct util_format_description
*desc
;
2084 unsigned data_format
;
2086 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2087 PIPE_BIND_SAMPLER_VIEW
|
2088 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2090 desc
= util_format_description(format
);
2094 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2095 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2096 * for read-only access (with caveats surrounding bounds checks), but
2097 * obviously fails for write access which we have to implement for
2098 * shader images. Luckily, OpenGL doesn't expect this to be supported
2099 * anyway, and so the only impact is on PBO uploads / downloads, which
2100 * shouldn't be expected to be fast for GL_RGB anyway.
2102 if (desc
->block
.bits
== 3 * 8 ||
2103 desc
->block
.bits
== 3 * 16) {
2104 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2105 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2111 first_non_void
= util_format_get_first_non_void_channel(format
);
2112 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2113 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2119 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2121 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2122 si_translate_colorswap(format
, false) != ~0U;
2125 static bool si_is_zs_format_supported(enum pipe_format format
)
2127 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2130 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2131 enum pipe_format format
,
2132 enum pipe_texture_target target
,
2133 unsigned sample_count
,
2134 unsigned storage_sample_count
,
2137 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2138 unsigned retval
= 0;
2140 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2141 PRINT_ERR("r600: unsupported texture type %d\n", target
);
2145 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2148 if (sample_count
> 1) {
2149 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2152 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2155 /* Only power-of-two sample counts are supported. */
2156 if (!util_is_power_of_two_or_zero(sample_count
) ||
2157 !util_is_power_of_two_or_zero(storage_sample_count
))
2160 /* MSAA support without framebuffer attachments. */
2161 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2164 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2165 util_format_is_depth_or_stencil(format
)) {
2166 /* Color without EQAA or depth/stencil. */
2167 if (sample_count
> 8 ||
2168 sample_count
!= storage_sample_count
)
2171 /* Color with EQAA. */
2172 if (sample_count
> 16 ||
2173 storage_sample_count
> 8)
2178 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2179 PIPE_BIND_SHADER_IMAGE
)) {
2180 if (target
== PIPE_BUFFER
) {
2181 retval
|= si_is_vertex_format_supported(
2182 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2183 PIPE_BIND_SHADER_IMAGE
));
2185 if (si_is_sampler_format_supported(screen
, format
))
2186 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2187 PIPE_BIND_SHADER_IMAGE
);
2191 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2192 PIPE_BIND_DISPLAY_TARGET
|
2195 PIPE_BIND_BLENDABLE
)) &&
2196 si_is_colorbuffer_format_supported(format
)) {
2198 (PIPE_BIND_RENDER_TARGET
|
2199 PIPE_BIND_DISPLAY_TARGET
|
2202 if (!util_format_is_pure_integer(format
) &&
2203 !util_format_is_depth_or_stencil(format
))
2204 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2207 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2208 si_is_zs_format_supported(format
)) {
2209 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2212 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2213 retval
|= si_is_vertex_format_supported(screen
, format
,
2214 PIPE_BIND_VERTEX_BUFFER
);
2217 if ((usage
& PIPE_BIND_LINEAR
) &&
2218 !util_format_is_compressed(format
) &&
2219 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2220 retval
|= PIPE_BIND_LINEAR
;
2222 return retval
== usage
;
2226 * framebuffer handling
2229 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2230 unsigned format
, unsigned swap
,
2231 unsigned ntype
, bool is_depth
)
2233 /* Alpha is needed for alpha-to-coverage.
2234 * Blending may be with or without alpha.
2236 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2237 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2238 unsigned blend
= 0; /* supports blending, but may not export alpha */
2239 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2241 /* Choose the SPI color formats. These are required values for RB+.
2242 * Other chips have multiple choices, though they are not necessarily better.
2245 case V_028C70_COLOR_5_6_5
:
2246 case V_028C70_COLOR_1_5_5_5
:
2247 case V_028C70_COLOR_5_5_5_1
:
2248 case V_028C70_COLOR_4_4_4_4
:
2249 case V_028C70_COLOR_10_11_11
:
2250 case V_028C70_COLOR_11_11_10
:
2251 case V_028C70_COLOR_8
:
2252 case V_028C70_COLOR_8_8
:
2253 case V_028C70_COLOR_8_8_8_8
:
2254 case V_028C70_COLOR_10_10_10_2
:
2255 case V_028C70_COLOR_2_10_10_10
:
2256 if (ntype
== V_028C70_NUMBER_UINT
)
2257 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2258 else if (ntype
== V_028C70_NUMBER_SINT
)
2259 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2261 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2264 case V_028C70_COLOR_16
:
2265 case V_028C70_COLOR_16_16
:
2266 case V_028C70_COLOR_16_16_16_16
:
2267 if (ntype
== V_028C70_NUMBER_UNORM
||
2268 ntype
== V_028C70_NUMBER_SNORM
) {
2269 /* UNORM16 and SNORM16 don't support blending */
2270 if (ntype
== V_028C70_NUMBER_UNORM
)
2271 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2273 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2275 /* Use 32 bits per channel for blending. */
2276 if (format
== V_028C70_COLOR_16
) {
2277 if (swap
== V_028C70_SWAP_STD
) { /* R */
2278 blend
= V_028714_SPI_SHADER_32_R
;
2279 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2280 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2281 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2284 } else if (format
== V_028C70_COLOR_16_16
) {
2285 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2286 blend
= V_028714_SPI_SHADER_32_GR
;
2287 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2288 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2289 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2292 } else /* 16_16_16_16 */
2293 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2294 } else if (ntype
== V_028C70_NUMBER_UINT
)
2295 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2296 else if (ntype
== V_028C70_NUMBER_SINT
)
2297 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2298 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2299 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2304 case V_028C70_COLOR_32
:
2305 if (swap
== V_028C70_SWAP_STD
) { /* R */
2306 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2307 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2308 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2309 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2314 case V_028C70_COLOR_32_32
:
2315 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2316 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2317 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2318 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2319 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2324 case V_028C70_COLOR_32_32_32_32
:
2325 case V_028C70_COLOR_8_24
:
2326 case V_028C70_COLOR_24_8
:
2327 case V_028C70_COLOR_X24_8_32_FLOAT
:
2328 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2336 /* The DB->CB copy needs 32_ABGR. */
2338 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2340 surf
->spi_shader_col_format
= normal
;
2341 surf
->spi_shader_col_format_alpha
= alpha
;
2342 surf
->spi_shader_col_format_blend
= blend
;
2343 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2346 static void si_initialize_color_surface(struct si_context
*sctx
,
2347 struct si_surface
*surf
)
2349 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2350 unsigned color_info
, color_attrib
;
2351 unsigned format
, swap
, ntype
, endian
;
2352 const struct util_format_description
*desc
;
2354 unsigned blend_clamp
= 0, blend_bypass
= 0;
2356 desc
= util_format_description(surf
->base
.format
);
2357 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2358 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2362 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2363 ntype
= V_028C70_NUMBER_FLOAT
;
2365 ntype
= V_028C70_NUMBER_UNORM
;
2366 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2367 ntype
= V_028C70_NUMBER_SRGB
;
2368 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2369 if (desc
->channel
[firstchan
].pure_integer
) {
2370 ntype
= V_028C70_NUMBER_SINT
;
2372 assert(desc
->channel
[firstchan
].normalized
);
2373 ntype
= V_028C70_NUMBER_SNORM
;
2375 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2376 if (desc
->channel
[firstchan
].pure_integer
) {
2377 ntype
= V_028C70_NUMBER_UINT
;
2379 assert(desc
->channel
[firstchan
].normalized
);
2380 ntype
= V_028C70_NUMBER_UNORM
;
2385 format
= si_translate_colorformat(surf
->base
.format
);
2386 if (format
== V_028C70_COLOR_INVALID
) {
2387 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2389 assert(format
!= V_028C70_COLOR_INVALID
);
2390 swap
= si_translate_colorswap(surf
->base
.format
, false);
2391 endian
= si_colorformat_endian_swap(format
);
2393 /* blend clamp should be set for all NORM/SRGB types */
2394 if (ntype
== V_028C70_NUMBER_UNORM
||
2395 ntype
== V_028C70_NUMBER_SNORM
||
2396 ntype
== V_028C70_NUMBER_SRGB
)
2399 /* set blend bypass according to docs if SINT/UINT or
2400 8/24 COLOR variants */
2401 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2402 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2403 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2408 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2409 if (format
== V_028C70_COLOR_8
||
2410 format
== V_028C70_COLOR_8_8
||
2411 format
== V_028C70_COLOR_8_8_8_8
)
2412 surf
->color_is_int8
= true;
2413 else if (format
== V_028C70_COLOR_10_10_10_2
||
2414 format
== V_028C70_COLOR_2_10_10_10
)
2415 surf
->color_is_int10
= true;
2418 color_info
= S_028C70_FORMAT(format
) |
2419 S_028C70_COMP_SWAP(swap
) |
2420 S_028C70_BLEND_CLAMP(blend_clamp
) |
2421 S_028C70_BLEND_BYPASS(blend_bypass
) |
2422 S_028C70_SIMPLE_FLOAT(1) |
2423 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2424 ntype
!= V_028C70_NUMBER_SNORM
&&
2425 ntype
!= V_028C70_NUMBER_SRGB
&&
2426 format
!= V_028C70_COLOR_8_24
&&
2427 format
!= V_028C70_COLOR_24_8
) |
2428 S_028C70_NUMBER_TYPE(ntype
) |
2429 S_028C70_ENDIAN(endian
);
2431 /* Intensity is implemented as Red, so treat it that way. */
2432 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2433 util_format_is_intensity(surf
->base
.format
));
2435 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2436 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2437 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2439 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2440 S_028C74_NUM_FRAGMENTS(log_fragments
);
2442 if (tex
->surface
.fmask_size
) {
2443 color_info
|= S_028C70_COMPRESSION(1);
2444 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2446 if (sctx
->chip_class
== SI
) {
2447 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2448 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2453 if (sctx
->chip_class
>= VI
) {
2454 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2455 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2457 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2458 64 for APU because all of our APUs to date use DIMMs which have
2459 a request granularity size of 64B while all other chips have a
2461 if (!sctx
->screen
->info
.has_dedicated_vram
)
2462 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2464 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2465 if (tex
->surface
.bpe
== 1)
2466 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2467 else if (tex
->surface
.bpe
== 2)
2468 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2471 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2472 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2473 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2476 /* This must be set for fast clear to work without FMASK. */
2477 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== SI
) {
2478 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2479 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2482 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2483 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2485 if (sctx
->chip_class
>= GFX9
) {
2486 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2488 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2489 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2490 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2491 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2492 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2493 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2496 surf
->cb_color_view
= color_view
;
2497 surf
->cb_color_info
= color_info
;
2498 surf
->cb_color_attrib
= color_attrib
;
2500 /* Determine pixel shader export format */
2501 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2503 surf
->color_initialized
= true;
2506 static void si_init_depth_surface(struct si_context
*sctx
,
2507 struct si_surface
*surf
)
2509 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2510 unsigned level
= surf
->base
.u
.tex
.level
;
2511 unsigned format
, stencil_format
;
2512 uint32_t z_info
, s_info
;
2514 format
= si_translate_dbformat(tex
->db_render_format
);
2515 stencil_format
= tex
->surface
.has_stencil
?
2516 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2518 assert(format
!= V_028040_Z_INVALID
);
2519 if (format
== V_028040_Z_INVALID
)
2520 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2522 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2523 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2524 surf
->db_htile_data_base
= 0;
2525 surf
->db_htile_surface
= 0;
2527 if (sctx
->chip_class
>= GFX9
) {
2528 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2529 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2530 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2531 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2532 z_info
= S_028038_FORMAT(format
) |
2533 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2534 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2535 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2536 s_info
= S_02803C_FORMAT(stencil_format
) |
2537 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2538 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2539 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2540 surf
->db_depth_view
|= S_028008_MIPID(level
);
2541 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2542 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2544 if (si_htile_enabled(tex
, level
)) {
2545 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2546 S_028038_ALLOW_EXPCLEAR(1);
2548 if (tex
->tc_compatible_htile
) {
2549 unsigned max_zplanes
= 4;
2551 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2552 tex
->buffer
.b
.b
.nr_samples
> 1)
2555 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2556 S_028038_ITERATE_FLUSH(1);
2557 s_info
|= S_02803C_ITERATE_FLUSH(1);
2560 if (tex
->surface
.has_stencil
) {
2561 /* Stencil buffer workaround ported from the SI-CI-VI code.
2562 * See that for explanation.
2564 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2566 /* Use all HTILE for depth if there's no stencil. */
2567 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2570 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2571 tex
->htile_offset
) >> 8;
2572 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2573 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2574 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2578 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2580 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2582 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2583 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2584 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2585 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2587 z_info
= S_028040_FORMAT(format
) |
2588 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2589 s_info
= S_028044_FORMAT(stencil_format
);
2590 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2592 if (sctx
->chip_class
>= CIK
) {
2593 struct radeon_info
*info
= &sctx
->screen
->info
;
2594 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2595 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2596 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2597 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2598 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2599 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2601 surf
->db_depth_info
|=
2602 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2603 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2604 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2605 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2606 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2607 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2608 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2609 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2611 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2612 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2613 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2614 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2617 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2618 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2619 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2620 levelinfo
->nblk_y
) / 64 - 1);
2622 if (si_htile_enabled(tex
, level
)) {
2623 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2624 S_028040_ALLOW_EXPCLEAR(1);
2626 if (tex
->surface
.has_stencil
) {
2627 /* Workaround: For a not yet understood reason, the
2628 * combination of MSAA, fast stencil clear and stencil
2629 * decompress messes with subsequent stencil buffer
2630 * uses. Problem was reproduced on Verde, Bonaire,
2631 * Tonga, and Carrizo.
2633 * Disabling EXPCLEAR works around the problem.
2635 * Check piglit's arb_texture_multisample-stencil-clear
2636 * test if you want to try changing this.
2638 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2639 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2640 } else if (!tex
->tc_compatible_htile
) {
2641 /* Use all of the htile_buffer for depth if there's no stencil.
2642 * This must not be set when TC-compatible HTILE is enabled
2645 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2648 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2649 tex
->htile_offset
) >> 8;
2650 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2652 if (tex
->tc_compatible_htile
) {
2653 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2655 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2656 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2657 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2658 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2659 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2661 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2666 surf
->db_z_info
= z_info
;
2667 surf
->db_stencil_info
= s_info
;
2669 surf
->depth_initialized
= true;
2672 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2674 if (sctx
->decompression_enabled
)
2677 if (sctx
->framebuffer
.state
.zsbuf
) {
2678 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2679 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2681 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2683 if (tex
->surface
.has_stencil
)
2684 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2687 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2688 while (compressed_cb_mask
) {
2689 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2690 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2691 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2693 if (tex
->surface
.fmask_size
)
2694 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2695 if (tex
->dcc_gather_statistics
)
2696 tex
->separate_dcc_dirty
= true;
2700 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2702 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2703 struct si_surface
*surf
= NULL
;
2704 struct si_texture
*tex
;
2706 if (!state
->cbufs
[i
])
2708 surf
= (struct si_surface
*)state
->cbufs
[i
];
2709 tex
= (struct si_texture
*)surf
->base
.texture
;
2711 p_atomic_dec(&tex
->framebuffers_bound
);
2715 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2716 const struct pipe_framebuffer_state
*state
)
2718 struct si_context
*sctx
= (struct si_context
*)ctx
;
2719 struct si_surface
*surf
= NULL
;
2720 struct si_texture
*tex
;
2721 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2722 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2723 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2724 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2725 bool old_has_stencil
=
2727 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2728 bool unbound
= false;
2731 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2732 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2733 * We could implement the full workaround here, but it's a useless case.
2735 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2736 unreachable("the framebuffer shouldn't have zero area");
2740 si_update_fb_dirtiness_after_rendering(sctx
);
2742 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2743 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2746 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2747 if (tex
->dcc_gather_statistics
)
2748 vi_separate_dcc_stop_query(sctx
, tex
);
2751 /* Disable DCC if the formats are incompatible. */
2752 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2753 if (!state
->cbufs
[i
])
2756 surf
= (struct si_surface
*)state
->cbufs
[i
];
2757 tex
= (struct si_texture
*)surf
->base
.texture
;
2759 if (!surf
->dcc_incompatible
)
2762 /* Since the DCC decompression calls back into set_framebuffer-
2763 * _state, we need to unbind the framebuffer, so that
2764 * vi_separate_dcc_stop_query isn't called twice with the same
2768 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2772 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2773 if (!si_texture_disable_dcc(sctx
, tex
))
2774 si_decompress_dcc(sctx
, tex
);
2776 surf
->dcc_incompatible
= false;
2779 /* Only flush TC when changing the framebuffer state, because
2780 * the only client not using TC that can change textures is
2783 * Wait for compute shaders because of possible transitions:
2784 * - FB write -> shader read
2785 * - shader write -> FB read
2787 * DB caches are flushed on demand (using si_decompress_textures).
2789 * When MSAA is enabled, CB and TC caches are flushed on demand
2790 * (after FMASK decompression). Shader write -> FB read transitions
2791 * cannot happen for MSAA textures, because MSAA shader images are
2794 * Only flush and wait for CB if there is actually a bound color buffer.
2796 if (sctx
->framebuffer
.uncompressed_cb_mask
)
2797 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2798 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2800 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2802 /* u_blitter doesn't invoke depth decompression when it does multiple
2803 * blits in a row, but the only case when it matters for DB is when
2804 * doing generate_mipmap. So here we flush DB manually between
2805 * individual generate_mipmap blits.
2806 * Note that lower mipmap levels aren't compressed.
2808 if (sctx
->generate_mipmap_for_depth
) {
2809 si_make_DB_shader_coherent(sctx
, 1, false,
2810 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2811 } else if (sctx
->chip_class
== GFX9
) {
2812 /* It appears that DB metadata "leaks" in a sequence of:
2814 * - DCC decompress for shader image writes (with DB disabled)
2815 * - render with DEPTH_BEFORE_SHADER=1
2816 * Flushing DB metadata works around the problem.
2818 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2821 /* Take the maximum of the old and new count. If the new count is lower,
2822 * dirtying is needed to disable the unbound colorbuffers.
2824 sctx
->framebuffer
.dirty_cbufs
|=
2825 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2826 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2828 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2829 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2831 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2832 sctx
->framebuffer
.spi_shader_col_format
= 0;
2833 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2834 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2835 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2836 sctx
->framebuffer
.color_is_int8
= 0;
2837 sctx
->framebuffer
.color_is_int10
= 0;
2839 sctx
->framebuffer
.compressed_cb_mask
= 0;
2840 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2841 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2842 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2843 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2844 sctx
->framebuffer
.any_dst_linear
= false;
2845 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2846 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2848 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2849 if (!state
->cbufs
[i
])
2852 surf
= (struct si_surface
*)state
->cbufs
[i
];
2853 tex
= (struct si_texture
*)surf
->base
.texture
;
2855 if (!surf
->color_initialized
) {
2856 si_initialize_color_surface(sctx
, surf
);
2859 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2860 sctx
->framebuffer
.spi_shader_col_format
|=
2861 surf
->spi_shader_col_format
<< (i
* 4);
2862 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2863 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2864 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2865 surf
->spi_shader_col_format_blend
<< (i
* 4);
2866 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2867 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2869 if (surf
->color_is_int8
)
2870 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2871 if (surf
->color_is_int10
)
2872 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2874 if (tex
->surface
.fmask_size
)
2875 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2877 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2879 /* Don't update nr_color_samples for non-AA buffers.
2880 * (e.g. destination of MSAA resolve)
2882 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2883 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2884 sctx
->framebuffer
.nr_color_samples
=
2885 MIN2(sctx
->framebuffer
.nr_color_samples
,
2886 tex
->buffer
.b
.b
.nr_storage_samples
);
2887 sctx
->framebuffer
.nr_color_samples
=
2888 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2891 if (tex
->surface
.is_linear
)
2892 sctx
->framebuffer
.any_dst_linear
= true;
2894 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2895 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2897 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2899 p_atomic_inc(&tex
->framebuffers_bound
);
2901 if (tex
->dcc_gather_statistics
) {
2902 /* Dirty tracking must be enabled for DCC usage analysis. */
2903 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2904 vi_separate_dcc_start_query(sctx
, tex
);
2908 struct si_texture
*zstex
= NULL
;
2911 surf
= (struct si_surface
*)state
->zsbuf
;
2912 zstex
= (struct si_texture
*)surf
->base
.texture
;
2914 if (!surf
->depth_initialized
) {
2915 si_init_depth_surface(sctx
, surf
);
2918 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2919 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2921 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2924 si_update_ps_colorbuf0_slot(sctx
);
2925 si_update_poly_offset_state(sctx
);
2926 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2927 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2929 if (sctx
->screen
->dpbb_allowed
)
2930 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2932 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2933 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2935 if (sctx
->screen
->has_out_of_order_rast
&&
2936 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2937 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2938 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2939 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2941 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2942 struct pipe_constant_buffer constbuf
= {0};
2944 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2945 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2947 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2949 /* Set sample locations as fragment shader constants. */
2950 switch (sctx
->framebuffer
.nr_samples
) {
2952 constbuf
.buffer_offset
= 0;
2955 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
2956 (ubyte
*)sctx
->sample_positions
.x1
;
2959 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
2960 (ubyte
*)sctx
->sample_positions
.x1
;
2963 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
2964 (ubyte
*)sctx
->sample_positions
.x1
;
2967 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
2968 (ubyte
*)sctx
->sample_positions
.x1
;
2971 PRINT_ERR("Requested an invalid number of samples %i.\n",
2972 sctx
->framebuffer
.nr_samples
);
2975 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2976 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2978 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2981 sctx
->do_update_shaders
= true;
2983 if (!sctx
->decompression_enabled
) {
2984 /* Prevent textures decompression when the framebuffer state
2985 * changes come from the decompression passes themselves.
2987 sctx
->need_check_render_feedback
= true;
2991 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2993 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2994 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2995 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2996 struct si_texture
*tex
= NULL
;
2997 struct si_surface
*cb
= NULL
;
2998 unsigned cb_color_info
= 0;
3001 for (i
= 0; i
< nr_cbufs
; i
++) {
3002 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3003 unsigned cb_color_attrib
;
3005 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3008 cb
= (struct si_surface
*)state
->cbufs
[i
];
3010 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3011 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3015 tex
= (struct si_texture
*)cb
->base
.texture
;
3016 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3017 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3018 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3019 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3020 RADEON_PRIO_COLOR_BUFFER
);
3022 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3023 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3024 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3025 RADEON_PRIO_SEPARATE_META
);
3028 if (tex
->dcc_separate_buffer
)
3029 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3030 tex
->dcc_separate_buffer
,
3031 RADEON_USAGE_READWRITE
,
3032 RADEON_PRIO_SEPARATE_META
);
3034 /* Compute mutable surface parameters. */
3035 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3037 cb_color_cmask
= tex
->cmask_base_address_reg
;
3039 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3040 cb_color_attrib
= cb
->cb_color_attrib
;
3042 if (cb
->base
.u
.tex
.level
> 0)
3043 cb_color_info
&= C_028C70_FAST_CLEAR
;
3045 if (tex
->surface
.fmask_size
) {
3046 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3047 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3051 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3052 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3053 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3054 state
->cbufs
[1] == &cb
->base
&&
3055 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3057 if (!is_msaa_resolve_dst
)
3058 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3060 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3061 tex
->dcc_offset
) >> 8;
3062 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3065 if (sctx
->chip_class
>= GFX9
) {
3066 struct gfx9_surf_meta_flags meta
;
3068 if (tex
->dcc_offset
)
3069 meta
= tex
->surface
.u
.gfx9
.dcc
;
3071 meta
= tex
->surface
.u
.gfx9
.cmask
;
3073 /* Set mutable surface parameters. */
3074 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3075 cb_color_base
|= tex
->surface
.tile_swizzle
;
3076 if (!tex
->surface
.fmask_size
)
3077 cb_color_fmask
= cb_color_base
;
3078 if (cb
->base
.u
.tex
.level
> 0)
3079 cb_color_cmask
= cb_color_base
;
3080 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3081 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3082 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3083 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3085 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3086 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3087 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3088 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3089 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3090 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3091 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3092 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3093 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3094 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3095 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3096 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3097 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3098 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3099 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3100 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3102 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3103 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3105 /* Compute mutable surface parameters (SI-CI-VI). */
3106 const struct legacy_surf_level
*level_info
=
3107 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3108 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3109 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3111 cb_color_base
+= level_info
->offset
>> 8;
3112 /* Only macrotiled modes can set tile swizzle. */
3113 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3114 cb_color_base
|= tex
->surface
.tile_swizzle
;
3116 if (!tex
->surface
.fmask_size
)
3117 cb_color_fmask
= cb_color_base
;
3118 if (cb
->base
.u
.tex
.level
> 0)
3119 cb_color_cmask
= cb_color_base
;
3121 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3123 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3124 slice_tile_max
= level_info
->nblk_x
*
3125 level_info
->nblk_y
/ 64 - 1;
3126 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3128 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3129 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3130 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3132 if (tex
->surface
.fmask_size
) {
3133 if (sctx
->chip_class
>= CIK
)
3134 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3135 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3136 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3138 /* This must be set for fast clear to work without FMASK. */
3139 if (sctx
->chip_class
>= CIK
)
3140 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3141 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3142 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3145 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3146 sctx
->chip_class
>= VI
? 14 : 13);
3147 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3148 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3149 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3150 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3151 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3152 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3153 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3154 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3155 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3156 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3157 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3158 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3159 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3161 if (sctx
->chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3162 radeon_emit(cs
, cb_dcc_base
);
3166 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3167 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3170 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3171 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3172 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3174 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3175 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3176 zb
->base
.texture
->nr_samples
> 1 ?
3177 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3178 RADEON_PRIO_DEPTH_BUFFER
);
3180 if (sctx
->chip_class
>= GFX9
) {
3181 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3182 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3183 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3184 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3186 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3187 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3188 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3189 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3190 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3191 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3192 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3193 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3194 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3195 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3196 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3197 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3199 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3200 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3201 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3203 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3205 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3206 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3207 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3208 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3209 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3210 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3211 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3212 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3213 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3214 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3215 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3218 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3219 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3220 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3222 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3223 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3224 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3225 if (sctx
->chip_class
>= GFX9
)
3226 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3228 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3230 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3231 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3234 /* Framebuffer dimensions. */
3235 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3236 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3237 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3239 if (sctx
->screen
->dfsm_allowed
) {
3240 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3241 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3244 sctx
->framebuffer
.dirty_cbufs
= 0;
3245 sctx
->framebuffer
.dirty_zsbuf
= false;
3248 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3250 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3251 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3252 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3253 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3255 /* Smoothing (only possible with nr_samples == 1) uses the same
3256 * sample locations as the MSAA it simulates.
3258 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3259 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3261 /* On Polaris, the small primitive filter uses the sample locations
3262 * even when MSAA is off, so we need to make sure they're set to 0.
3264 if (has_msaa_sample_loc_bug
)
3265 nr_samples
= MAX2(nr_samples
, 1);
3267 if (nr_samples
!= sctx
->sample_locs_num_samples
) {
3268 sctx
->sample_locs_num_samples
= nr_samples
;
3269 si_emit_sample_locations(cs
, nr_samples
);
3272 if (sctx
->family
>= CHIP_POLARIS10
) {
3273 unsigned small_prim_filter_cntl
=
3274 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3276 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3278 /* The alternative of setting sample locations to 0 would
3279 * require a DB flush to avoid Z errors, see
3280 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3282 if (has_msaa_sample_loc_bug
&&
3283 sctx
->framebuffer
.nr_samples
> 1 &&
3284 !rs
->multisample_enable
)
3285 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3287 radeon_opt_set_context_reg(sctx
,
3288 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3289 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3290 small_prim_filter_cntl
);
3293 /* The exclusion bits can be set to improve rasterization efficiency
3294 * if no sample lies on the pixel boundary (-8 sample offset).
3296 bool exclusion
= sctx
->chip_class
>= CIK
&&
3297 (!rs
->multisample_enable
|| nr_samples
!= 16);
3298 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3299 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3300 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3301 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3304 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3306 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3307 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3309 if (!sctx
->screen
->has_out_of_order_rast
)
3312 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3315 colormask
&= blend
->cb_target_enabled_4bit
;
3320 /* Conservative: No logic op. */
3321 if (colormask
&& blend
->logicop_enable
)
3324 struct si_dsa_order_invariance dsa_order_invariant
= {
3325 .zs
= true, .pass_set
= true, .pass_last
= false
3328 if (sctx
->framebuffer
.state
.zsbuf
) {
3329 struct si_texture
*zstex
=
3330 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3331 bool has_stencil
= zstex
->surface
.has_stencil
;
3332 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3333 if (!dsa_order_invariant
.zs
)
3336 /* The set of PS invocations is always order invariant,
3337 * except when early Z/S tests are requested. */
3338 if (sctx
->ps_shader
.cso
&&
3339 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3340 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3341 !dsa_order_invariant
.pass_set
)
3344 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3345 !dsa_order_invariant
.pass_set
)
3352 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3355 /* Only commutative blending. */
3356 if (blendmask
& ~blend
->commutative_4bit
)
3359 if (!dsa_order_invariant
.pass_set
)
3363 if (colormask
& ~blendmask
) {
3364 if (!dsa_order_invariant
.pass_last
)
3371 static void si_emit_msaa_config(struct si_context
*sctx
)
3373 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3374 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3375 /* 33% faster rendering to linear color buffers */
3376 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3377 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3378 unsigned sc_mode_cntl_1
=
3379 S_028A4C_WALK_SIZE(dst_is_linear
) |
3380 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3381 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3382 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3383 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3385 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3386 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3387 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3388 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3389 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3390 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3391 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3392 S_028804_INCOHERENT_EQAA_READS(1) |
3393 S_028804_INTERPOLATE_COMP_Z(1) |
3394 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3395 unsigned coverage_samples
, color_samples
, z_samples
;
3397 /* S: Coverage samples (up to 16x):
3398 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3399 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3401 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3402 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3403 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3404 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3405 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3408 * F: Color samples (up to 8x, must be <= coverage samples):
3409 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3410 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3412 * Can be anything between coverage and color samples:
3413 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3414 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3415 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3416 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3417 * # All are currently set the same as coverage samples.
3419 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3420 * flag for undefined color samples. A shader-based resolve must handle unknowns
3421 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3422 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3423 * useful. The CB resolve always drops unknowns.
3425 * Sensible AA configurations:
3426 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3427 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3428 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3429 * EQAA 8s 8z 8f = 8x MSAA
3430 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3431 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3432 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3433 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3434 * EQAA 4s 4z 4f = 4x MSAA
3435 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3436 * EQAA 2s 2z 2f = 2x MSAA
3438 if (sctx
->framebuffer
.nr_samples
> 1) {
3439 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3440 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3442 if (sctx
->framebuffer
.state
.zsbuf
) {
3443 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3444 z_samples
= MAX2(1, z_samples
);
3446 z_samples
= coverage_samples
;
3448 } else if (sctx
->smoothing_enabled
) {
3449 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3451 coverage_samples
= color_samples
= z_samples
= 1;
3454 /* Required by OpenGL line rasterization.
3456 * TODO: We should also enable perpendicular endcaps for AA lines,
3457 * but that requires implementing line stippling in the pixel
3458 * shader. SC can only do line stippling with axis-aligned
3461 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3462 unsigned sc_aa_config
= 0;
3464 if (coverage_samples
> 1) {
3465 /* distance from the pixel center, indexed by log2(nr_samples) */
3466 static unsigned max_dist
[] = {
3473 unsigned log_samples
= util_logbase2(coverage_samples
);
3474 unsigned log_z_samples
= util_logbase2(z_samples
);
3475 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3476 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3478 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3479 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3480 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3481 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3483 if (sctx
->framebuffer
.nr_samples
> 1) {
3484 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3485 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3486 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3487 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3488 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3489 } else if (sctx
->smoothing_enabled
) {
3490 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3494 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3495 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3496 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3498 /* R_028804_DB_EQAA */
3499 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3501 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3502 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3503 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3505 /* GFX9: Flush DFSM when the AA mode changes. */
3506 if (sctx
->screen
->dfsm_allowed
) {
3507 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3508 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3512 void si_update_ps_iter_samples(struct si_context
*sctx
)
3514 if (sctx
->framebuffer
.nr_samples
> 1)
3515 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3516 if (sctx
->screen
->dpbb_allowed
)
3517 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3520 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3522 struct si_context
*sctx
= (struct si_context
*)ctx
;
3524 /* The hardware can only do sample shading with 2^n samples. */
3525 min_samples
= util_next_power_of_two(min_samples
);
3527 if (sctx
->ps_iter_samples
== min_samples
)
3530 sctx
->ps_iter_samples
= min_samples
;
3531 sctx
->do_update_shaders
= true;
3533 si_update_ps_iter_samples(sctx
);
3541 * Build the sampler view descriptor for a buffer texture.
3542 * @param state 256-bit descriptor; only the high 128 bits are filled in
3545 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3546 enum pipe_format format
,
3547 unsigned offset
, unsigned size
,
3550 const struct util_format_description
*desc
;
3553 unsigned num_records
;
3554 unsigned num_format
, data_format
;
3556 desc
= util_format_description(format
);
3557 first_non_void
= util_format_get_first_non_void_channel(format
);
3558 stride
= desc
->block
.bits
/ 8;
3559 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3560 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3562 num_records
= size
/ stride
;
3563 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3565 /* The NUM_RECORDS field has a different meaning depending on the chip,
3566 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3569 * - If STRIDE == 0, it's in byte units.
3570 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3573 * - For SMEM and STRIDE == 0, it's in byte units.
3574 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3575 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3576 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3577 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3578 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3579 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3580 * That way the same descriptor can be used by both SMEM and VMEM.
3583 * - For SMEM and STRIDE == 0, it's in byte units.
3584 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3585 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3586 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3588 if (screen
->info
.chip_class
>= GFX9
)
3589 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3590 * from STRIDE to bytes. This works around it by setting
3591 * NUM_RECORDS to at least the size of one element, so that
3592 * the first element is readable when IDXEN == 0.
3594 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3595 * IDXEN is enforced?
3597 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3598 else if (screen
->info
.chip_class
== VI
)
3599 num_records
*= stride
;
3602 state
[5] = S_008F04_STRIDE(stride
);
3603 state
[6] = num_records
;
3604 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3605 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3606 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3607 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3608 S_008F0C_NUM_FORMAT(num_format
) |
3609 S_008F0C_DATA_FORMAT(data_format
);
3612 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3614 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3616 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3617 /* For the pre-defined border color values (white, opaque
3618 * black, transparent black), the only thing that matters is
3619 * that the alpha channel winds up in the correct place
3620 * (because the RGB channels are all the same) so either of
3621 * these enumerations will work.
3623 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3624 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3626 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3627 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3628 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3629 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3631 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3632 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3633 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3634 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3635 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3642 * Build the sampler view descriptor for a texture.
3645 si_make_texture_descriptor(struct si_screen
*screen
,
3646 struct si_texture
*tex
,
3648 enum pipe_texture_target target
,
3649 enum pipe_format pipe_format
,
3650 const unsigned char state_swizzle
[4],
3651 unsigned first_level
, unsigned last_level
,
3652 unsigned first_layer
, unsigned last_layer
,
3653 unsigned width
, unsigned height
, unsigned depth
,
3655 uint32_t *fmask_state
)
3657 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3658 const struct util_format_description
*desc
;
3659 unsigned char swizzle
[4];
3661 unsigned num_format
, data_format
, type
, num_samples
;
3664 desc
= util_format_description(pipe_format
);
3666 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
3667 MAX2(1, res
->nr_samples
) :
3668 MAX2(1, res
->nr_storage_samples
);
3670 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3671 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3672 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3673 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3675 switch (pipe_format
) {
3676 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3677 case PIPE_FORMAT_X32_S8X24_UINT
:
3678 case PIPE_FORMAT_X8Z24_UNORM
:
3679 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3681 case PIPE_FORMAT_X24S8_UINT
:
3683 * X24S8 is implemented as an 8_8_8_8 data format, to
3684 * fix texture gathers. This affects at least
3685 * GL45-CTS.texture_cube_map_array.sampling on VI.
3687 if (screen
->info
.chip_class
<= VI
)
3688 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3690 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3693 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3696 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3699 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3701 switch (pipe_format
) {
3702 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3703 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3706 if (first_non_void
< 0) {
3707 if (util_format_is_compressed(pipe_format
)) {
3708 switch (pipe_format
) {
3709 case PIPE_FORMAT_DXT1_SRGB
:
3710 case PIPE_FORMAT_DXT1_SRGBA
:
3711 case PIPE_FORMAT_DXT3_SRGBA
:
3712 case PIPE_FORMAT_DXT5_SRGBA
:
3713 case PIPE_FORMAT_BPTC_SRGBA
:
3714 case PIPE_FORMAT_ETC2_SRGB8
:
3715 case PIPE_FORMAT_ETC2_SRGB8A1
:
3716 case PIPE_FORMAT_ETC2_SRGBA8
:
3717 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3719 case PIPE_FORMAT_RGTC1_SNORM
:
3720 case PIPE_FORMAT_LATC1_SNORM
:
3721 case PIPE_FORMAT_RGTC2_SNORM
:
3722 case PIPE_FORMAT_LATC2_SNORM
:
3723 case PIPE_FORMAT_ETC2_R11_SNORM
:
3724 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3725 /* implies float, so use SNORM/UNORM to determine
3726 whether data is signed or not */
3727 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3728 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3731 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3734 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3735 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3737 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3739 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3740 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3742 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3744 switch (desc
->channel
[first_non_void
].type
) {
3745 case UTIL_FORMAT_TYPE_FLOAT
:
3746 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3748 case UTIL_FORMAT_TYPE_SIGNED
:
3749 if (desc
->channel
[first_non_void
].normalized
)
3750 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3751 else if (desc
->channel
[first_non_void
].pure_integer
)
3752 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3754 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3756 case UTIL_FORMAT_TYPE_UNSIGNED
:
3757 if (desc
->channel
[first_non_void
].normalized
)
3758 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3759 else if (desc
->channel
[first_non_void
].pure_integer
)
3760 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3762 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3767 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3768 if (data_format
== ~0) {
3772 /* S8 with Z32 HTILE needs a special format. */
3773 if (screen
->info
.chip_class
>= GFX9
&&
3774 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3775 tex
->tc_compatible_htile
)
3776 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3779 (res
->target
== PIPE_TEXTURE_CUBE
||
3780 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3781 (screen
->info
.chip_class
<= VI
&&
3782 res
->target
== PIPE_TEXTURE_3D
))) {
3783 /* For the purpose of shader images, treat cube maps and 3D
3784 * textures as 2D arrays. For 3D textures, the address
3785 * calculations for mipmaps are different, so we rely on the
3786 * caller to effectively disable mipmaps.
3788 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3790 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3792 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
3795 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3797 depth
= res
->array_size
;
3798 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3799 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3800 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3801 depth
= res
->array_size
;
3802 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3803 depth
= res
->array_size
/ 6;
3806 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3807 S_008F14_NUM_FORMAT_GFX6(num_format
));
3808 state
[2] = (S_008F18_WIDTH(width
- 1) |
3809 S_008F18_HEIGHT(height
- 1) |
3810 S_008F18_PERF_MOD(4));
3811 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3812 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3813 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3814 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3815 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
3816 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
3817 util_logbase2(num_samples
) :
3819 S_008F1C_TYPE(type
));
3821 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3825 if (screen
->info
.chip_class
>= GFX9
) {
3826 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3828 /* Depth is the the last accessible layer on Gfx9.
3829 * The hw doesn't need to know the total number of layers.
3831 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3832 state
[4] |= S_008F20_DEPTH(depth
- 1);
3834 state
[4] |= S_008F20_DEPTH(last_layer
);
3836 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3837 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
3838 util_logbase2(num_samples
) :
3839 tex
->buffer
.b
.b
.last_level
);
3841 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3842 state
[4] |= S_008F20_DEPTH(depth
- 1);
3843 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3846 if (tex
->dcc_offset
) {
3847 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
3849 /* The last dword is unused by hw. The shader uses it to clear
3850 * bits in the first dword of sampler state.
3852 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3853 if (first_level
== last_level
)
3854 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3856 state
[7] = 0xffffffff;
3860 /* Initialize the sampler view for FMASK. */
3861 if (tex
->surface
.fmask_size
) {
3862 uint32_t data_format
, num_format
;
3864 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3866 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3867 if (screen
->info
.chip_class
>= GFX9
) {
3868 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3869 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3871 num_format
= V_008F14_IMG_FMASK_8_2_1
;
3874 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3877 num_format
= V_008F14_IMG_FMASK_8_4_1
;
3880 num_format
= V_008F14_IMG_FMASK_8_4_2
;
3883 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3886 num_format
= V_008F14_IMG_FMASK_8_8_1
;
3889 num_format
= V_008F14_IMG_FMASK_16_8_2
;
3892 num_format
= V_008F14_IMG_FMASK_32_8_4
;
3895 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3898 num_format
= V_008F14_IMG_FMASK_16_16_1
;
3901 num_format
= V_008F14_IMG_FMASK_32_16_2
;
3904 num_format
= V_008F14_IMG_FMASK_64_16_4
;
3907 num_format
= V_008F14_IMG_FMASK_64_16_8
;
3910 unreachable("invalid nr_samples");
3913 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3915 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
3918 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3921 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
3924 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
3927 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3930 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
3933 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
3936 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
3939 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3942 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
3945 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
3948 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
3951 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
3954 unreachable("invalid nr_samples");
3956 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3960 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3961 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3962 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3963 S_008F14_NUM_FORMAT_GFX6(num_format
);
3964 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3965 S_008F18_HEIGHT(height
- 1);
3966 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3967 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3968 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3969 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3970 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3972 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3976 if (screen
->info
.chip_class
>= GFX9
) {
3977 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3978 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3979 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3980 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3981 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3983 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3984 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3985 S_008F20_PITCH_GFX6(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
3986 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3992 * Create a sampler view.
3994 * @param ctx context
3995 * @param texture texture
3996 * @param state sampler view template
3997 * @param width0 width0 override (for compressed textures as int)
3998 * @param height0 height0 override (for compressed textures as int)
3999 * @param force_level set the base address to the level (for compressed textures)
4001 struct pipe_sampler_view
*
4002 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4003 struct pipe_resource
*texture
,
4004 const struct pipe_sampler_view
*state
,
4005 unsigned width0
, unsigned height0
,
4006 unsigned force_level
)
4008 struct si_context
*sctx
= (struct si_context
*)ctx
;
4009 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4010 struct si_texture
*tex
= (struct si_texture
*)texture
;
4011 unsigned base_level
, first_level
, last_level
;
4012 unsigned char state_swizzle
[4];
4013 unsigned height
, depth
, width
;
4014 unsigned last_layer
= state
->u
.tex
.last_layer
;
4015 enum pipe_format pipe_format
;
4016 const struct legacy_surf_level
*surflevel
;
4021 /* initialize base object */
4022 view
->base
= *state
;
4023 view
->base
.texture
= NULL
;
4024 view
->base
.reference
.count
= 1;
4025 view
->base
.context
= ctx
;
4028 pipe_resource_reference(&view
->base
.texture
, texture
);
4030 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4031 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4032 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4033 state
->format
== PIPE_FORMAT_S8_UINT
)
4034 view
->is_stencil_sampler
= true;
4036 /* Buffer resource. */
4037 if (texture
->target
== PIPE_BUFFER
) {
4038 si_make_buffer_descriptor(sctx
->screen
,
4039 r600_resource(texture
),
4041 state
->u
.buf
.offset
,
4047 state_swizzle
[0] = state
->swizzle_r
;
4048 state_swizzle
[1] = state
->swizzle_g
;
4049 state_swizzle
[2] = state
->swizzle_b
;
4050 state_swizzle
[3] = state
->swizzle_a
;
4053 first_level
= state
->u
.tex
.first_level
;
4054 last_level
= state
->u
.tex
.last_level
;
4057 depth
= texture
->depth0
;
4059 if (sctx
->chip_class
<= VI
&& force_level
) {
4060 assert(force_level
== first_level
&&
4061 force_level
== last_level
);
4062 base_level
= force_level
;
4065 width
= u_minify(width
, force_level
);
4066 height
= u_minify(height
, force_level
);
4067 depth
= u_minify(depth
, force_level
);
4070 /* This is not needed if state trackers set last_layer correctly. */
4071 if (state
->target
== PIPE_TEXTURE_1D
||
4072 state
->target
== PIPE_TEXTURE_2D
||
4073 state
->target
== PIPE_TEXTURE_RECT
||
4074 state
->target
== PIPE_TEXTURE_CUBE
)
4075 last_layer
= state
->u
.tex
.first_layer
;
4077 /* Texturing with separate depth and stencil. */
4078 pipe_format
= state
->format
;
4080 /* Depth/stencil texturing sometimes needs separate texture. */
4081 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4082 if (!tex
->flushed_depth_texture
&&
4083 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
4084 pipe_resource_reference(&view
->base
.texture
, NULL
);
4089 assert(tex
->flushed_depth_texture
);
4091 /* Override format for the case where the flushed texture
4092 * contains only Z or only S.
4094 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4095 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4097 tex
= tex
->flushed_depth_texture
;
4100 surflevel
= tex
->surface
.u
.legacy
.level
;
4102 if (tex
->db_compatible
) {
4103 if (!view
->is_stencil_sampler
)
4104 pipe_format
= tex
->db_render_format
;
4106 switch (pipe_format
) {
4107 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4108 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4110 case PIPE_FORMAT_X8Z24_UNORM
:
4111 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4112 /* Z24 is always stored like this for DB
4115 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4117 case PIPE_FORMAT_X24S8_UINT
:
4118 case PIPE_FORMAT_S8X24_UINT
:
4119 case PIPE_FORMAT_X32_S8X24_UINT
:
4120 pipe_format
= PIPE_FORMAT_S8_UINT
;
4121 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4127 view
->dcc_incompatible
=
4128 vi_dcc_formats_are_incompatible(texture
,
4129 state
->u
.tex
.first_level
,
4132 si_make_texture_descriptor(sctx
->screen
, tex
, true,
4133 state
->target
, pipe_format
, state_swizzle
,
4134 first_level
, last_level
,
4135 state
->u
.tex
.first_layer
, last_layer
,
4136 width
, height
, depth
,
4137 view
->state
, view
->fmask_state
);
4139 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
4141 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
4142 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
4143 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
4144 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
4145 view
->base_level_info
= &surflevel
[base_level
];
4146 view
->base_level
= base_level
;
4147 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4151 static struct pipe_sampler_view
*
4152 si_create_sampler_view(struct pipe_context
*ctx
,
4153 struct pipe_resource
*texture
,
4154 const struct pipe_sampler_view
*state
)
4156 return si_create_sampler_view_custom(ctx
, texture
, state
,
4157 texture
? texture
->width0
: 0,
4158 texture
? texture
->height0
: 0, 0);
4161 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4162 struct pipe_sampler_view
*state
)
4164 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4166 pipe_resource_reference(&state
->texture
, NULL
);
4170 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4172 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4173 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4175 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4176 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4179 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4180 const struct pipe_sampler_state
*state
,
4181 const union pipe_color_union
*color
,
4184 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4185 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4187 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4188 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4189 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4190 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4192 #define simple_border_types(elt) \
4194 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4195 color->elt[2] == 0 && color->elt[3] == 0) \
4196 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4197 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4198 color->elt[2] == 0 && color->elt[3] == 1) \
4199 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4200 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4201 color->elt[2] == 1 && color->elt[3] == 1) \
4202 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4206 simple_border_types(ui
);
4208 simple_border_types(f
);
4210 #undef simple_border_types
4214 /* Check if the border has been uploaded already. */
4215 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4216 if (memcmp(&sctx
->border_color_table
[i
], color
,
4217 sizeof(*color
)) == 0)
4220 if (i
>= SI_MAX_BORDER_COLORS
) {
4221 /* Getting 4096 unique border colors is very unlikely. */
4222 fprintf(stderr
, "radeonsi: The border color table is full. "
4223 "Any new border colors will be just black. "
4224 "Please file a bug.\n");
4225 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4228 if (i
== sctx
->border_color_count
) {
4229 /* Upload a new border color. */
4230 memcpy(&sctx
->border_color_table
[i
], color
,
4232 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4233 color
, sizeof(*color
));
4234 sctx
->border_color_count
++;
4237 return S_008F3C_BORDER_COLOR_PTR(i
) |
4238 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4241 static inline int S_FIXED(float value
, unsigned frac_bits
)
4243 return value
* (1 << frac_bits
);
4246 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4248 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4249 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4250 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4252 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4253 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4256 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4269 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4270 const struct pipe_sampler_state
*state
)
4272 struct si_context
*sctx
= (struct si_context
*)ctx
;
4273 struct si_screen
*sscreen
= sctx
->screen
;
4274 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4275 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4276 : state
->max_anisotropy
;
4277 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4278 union pipe_color_union clamped_border_color
;
4285 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4287 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4288 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4289 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4290 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4291 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4292 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4293 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4294 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4295 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4296 S_008F30_COMPAT_MODE(sctx
->chip_class
>= VI
));
4297 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4298 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4299 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4300 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4301 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4302 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4303 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4304 S_008F38_MIP_POINT_PRECLAMP(0) |
4305 S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= VI
) |
4306 S_008F38_FILTER_PREC_FIX(1) |
4307 S_008F38_ANISO_OVERRIDE(sctx
->chip_class
>= VI
));
4308 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4310 /* Create sampler resource for integer textures. */
4311 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4312 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4314 /* Create sampler resource for upgraded depth textures. */
4315 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4317 for (unsigned i
= 0; i
< 4; ++i
) {
4318 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4319 * when the border color is 1.0. */
4320 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4323 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4324 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4326 rstate
->upgraded_depth_val
[3] =
4327 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4328 S_008F3C_UPGRADED_DEPTH(1);
4333 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4335 struct si_context
*sctx
= (struct si_context
*)ctx
;
4337 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4340 sctx
->sample_mask
= sample_mask
;
4341 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4344 static void si_emit_sample_mask(struct si_context
*sctx
)
4346 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4347 unsigned mask
= sctx
->sample_mask
;
4349 /* Needed for line and polygon smoothing as well as for the Polaris
4350 * small primitive filter. We expect the state tracker to take care of
4353 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4354 (mask
& 1 && sctx
->blitter
->running
));
4356 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4357 radeon_emit(cs
, mask
| (mask
<< 16));
4358 radeon_emit(cs
, mask
| (mask
<< 16));
4361 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4364 struct si_sampler_state
*s
= state
;
4366 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4373 * Vertex elements & buffers
4376 struct util_fast_udiv_info32
{
4377 unsigned multiplier
; /* the "magic number" multiplier */
4378 unsigned pre_shift
; /* shift for the dividend before multiplying */
4379 unsigned post_shift
; /* shift for the dividend after multiplying */
4380 int increment
; /* 0 or 1; if set then increment the numerator, using one of
4381 the two strategies */
4384 static struct util_fast_udiv_info32
4385 util_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4387 struct util_fast_udiv_info info
=
4388 util_compute_fast_udiv_info(D
, num_bits
, 32);
4390 struct util_fast_udiv_info32 result
= {
4399 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4401 const struct pipe_vertex_element
*elements
)
4403 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4404 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4405 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4406 struct util_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4407 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32
) == 16);
4408 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4409 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4410 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4411 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4414 assert(count
<= SI_MAX_ATTRIBS
);
4419 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4421 for (i
= 0; i
< count
; ++i
) {
4422 const struct util_format_description
*desc
;
4423 const struct util_format_channel_description
*channel
;
4424 unsigned data_format
, num_format
;
4426 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4427 unsigned char swizzle
[4];
4429 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4434 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4435 if (instance_divisor
) {
4436 v
->uses_instance_divisors
= true;
4438 if (instance_divisor
== 1) {
4439 v
->instance_divisor_is_one
|= 1u << i
;
4441 v
->instance_divisor_is_fetched
|= 1u << i
;
4442 divisor_factors
[i
] =
4443 util_compute_fast_udiv_info32(instance_divisor
, 32);
4447 if (!used
[vbo_index
]) {
4448 v
->first_vb_use_mask
|= 1 << i
;
4449 used
[vbo_index
] = true;
4452 desc
= util_format_description(elements
[i
].src_format
);
4453 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4454 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4455 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4456 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4457 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4459 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4460 v
->src_offset
[i
] = elements
[i
].src_offset
;
4461 v
->vertex_buffer_index
[i
] = vbo_index
;
4463 /* The hardware always treats the 2-bit alpha channel as
4464 * unsigned, so a shader workaround is needed. The affected
4465 * chips are VI and older except Stoney (GFX8.1).
4467 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4468 sscreen
->info
.chip_class
<= VI
&&
4469 sscreen
->info
.family
!= CHIP_STONEY
) {
4470 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4471 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4472 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4473 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4474 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4475 /* This isn't actually used in OpenGL. */
4476 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4478 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4479 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4480 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4482 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4483 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4484 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4485 if (channel
->normalized
) {
4486 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4487 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4489 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4491 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4493 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4494 if (channel
->normalized
) {
4495 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4496 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4498 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4500 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4503 } else if (channel
&& channel
->size
== 64 &&
4504 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4505 switch (desc
->nr_channels
) {
4508 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4509 swizzle
[0] = PIPE_SWIZZLE_X
;
4510 swizzle
[1] = PIPE_SWIZZLE_Y
;
4511 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4512 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4515 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4516 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4517 swizzle
[1] = PIPE_SWIZZLE_Y
;
4518 swizzle
[2] = PIPE_SWIZZLE_0
;
4519 swizzle
[3] = PIPE_SWIZZLE_0
;
4522 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4523 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4524 swizzle
[1] = PIPE_SWIZZLE_Y
;
4525 swizzle
[2] = PIPE_SWIZZLE_Z
;
4526 swizzle
[3] = PIPE_SWIZZLE_W
;
4531 } else if (channel
&& desc
->nr_channels
== 3) {
4532 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4534 if (channel
->size
== 8) {
4535 if (channel
->pure_integer
)
4536 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4538 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4539 } else if (channel
->size
== 16) {
4540 if (channel
->pure_integer
)
4541 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4543 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4547 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4548 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4549 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4550 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4551 S_008F0C_NUM_FORMAT(num_format
) |
4552 S_008F0C_DATA_FORMAT(data_format
);
4555 if (v
->instance_divisor_is_fetched
) {
4556 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4558 v
->instance_divisor_factor_buffer
=
4559 (struct r600_resource
*)
4560 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
4561 num_divisors
* sizeof(divisor_factors
[0]));
4562 if (!v
->instance_divisor_factor_buffer
) {
4566 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
4567 NULL
, PIPE_TRANSFER_WRITE
);
4568 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4573 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4575 struct si_context
*sctx
= (struct si_context
*)ctx
;
4576 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4577 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4579 sctx
->vertex_elements
= v
;
4580 sctx
->vertex_buffers_dirty
= true;
4584 old
->count
!= v
->count
||
4585 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4586 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4587 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4588 sctx
->do_update_shaders
= true;
4590 if (v
&& v
->instance_divisor_is_fetched
) {
4591 struct pipe_constant_buffer cb
;
4593 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4594 cb
.user_buffer
= NULL
;
4595 cb
.buffer_offset
= 0;
4596 cb
.buffer_size
= 0xffffffff;
4597 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4601 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4603 struct si_context
*sctx
= (struct si_context
*)ctx
;
4604 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4606 if (sctx
->vertex_elements
== state
)
4607 sctx
->vertex_elements
= NULL
;
4608 r600_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4612 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4613 unsigned start_slot
, unsigned count
,
4614 const struct pipe_vertex_buffer
*buffers
)
4616 struct si_context
*sctx
= (struct si_context
*)ctx
;
4617 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4620 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4623 for (i
= 0; i
< count
; i
++) {
4624 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4625 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4626 struct pipe_resource
*buf
= src
->buffer
.resource
;
4628 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4629 dsti
->buffer_offset
= src
->buffer_offset
;
4630 dsti
->stride
= src
->stride
;
4631 si_context_add_resource_size(sctx
, buf
);
4633 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4636 for (i
= 0; i
< count
; i
++) {
4637 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4640 sctx
->vertex_buffers_dirty
= true;
4647 static void si_set_tess_state(struct pipe_context
*ctx
,
4648 const float default_outer_level
[4],
4649 const float default_inner_level
[2])
4651 struct si_context
*sctx
= (struct si_context
*)ctx
;
4652 struct pipe_constant_buffer cb
;
4655 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4656 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4659 cb
.user_buffer
= NULL
;
4660 cb
.buffer_size
= sizeof(array
);
4662 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4663 (void*)array
, sizeof(array
),
4666 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4667 pipe_resource_reference(&cb
.buffer
, NULL
);
4670 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4672 struct si_context
*sctx
= (struct si_context
*)ctx
;
4674 si_update_fb_dirtiness_after_rendering(sctx
);
4676 /* Multisample surfaces are flushed in si_decompress_textures. */
4677 if (sctx
->framebuffer
.uncompressed_cb_mask
)
4678 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4679 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4682 /* This only ensures coherency for shader image/buffer stores. */
4683 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4685 struct si_context
*sctx
= (struct si_context
*)ctx
;
4687 /* Subsequent commands must wait for all shader invocations to
4689 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4690 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4692 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4693 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
|
4694 SI_CONTEXT_INV_VMEM_L1
;
4696 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4697 PIPE_BARRIER_SHADER_BUFFER
|
4698 PIPE_BARRIER_TEXTURE
|
4699 PIPE_BARRIER_IMAGE
|
4700 PIPE_BARRIER_STREAMOUT_BUFFER
|
4701 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4702 /* As far as I can tell, L1 contents are written back to L2
4703 * automatically at end of shader, but the contents of other
4704 * L1 caches might still be stale. */
4705 sctx
->flags
|= SI_CONTEXT_INV_VMEM_L1
;
4708 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4709 /* Indices are read through TC L2 since VI.
4712 if (sctx
->screen
->info
.chip_class
<= CIK
)
4713 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4716 /* MSAA color, any depth and any stencil are flushed in
4717 * si_decompress_textures when needed.
4719 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4720 sctx
->framebuffer
.uncompressed_cb_mask
) {
4721 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4723 if (sctx
->chip_class
<= VI
)
4724 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4727 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4728 if (sctx
->screen
->info
.chip_class
<= VI
&&
4729 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4730 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4733 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4735 struct pipe_blend_state blend
;
4737 memset(&blend
, 0, sizeof(blend
));
4738 blend
.independent_blend_enable
= true;
4739 blend
.rt
[0].colormask
= 0xf;
4740 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4743 static void si_init_config(struct si_context
*sctx
);
4745 void si_init_state_functions(struct si_context
*sctx
)
4747 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
4748 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
4749 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
4750 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
4751 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
4752 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
4753 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
4754 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
4755 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
4756 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
4757 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
4759 sctx
->b
.create_blend_state
= si_create_blend_state
;
4760 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4761 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4762 sctx
->b
.set_blend_color
= si_set_blend_color
;
4764 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4765 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4766 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4768 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4769 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4770 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4772 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4773 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4774 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4775 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4776 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4778 sctx
->b
.set_clip_state
= si_set_clip_state
;
4779 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
4781 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
4783 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4784 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4786 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4787 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4789 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
4791 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
4792 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4793 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4794 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
4796 sctx
->b
.texture_barrier
= si_texture_barrier
;
4797 sctx
->b
.memory_barrier
= si_memory_barrier
;
4798 sctx
->b
.set_min_samples
= si_set_min_samples
;
4799 sctx
->b
.set_tess_state
= si_set_tess_state
;
4801 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
4803 sctx
->b
.draw_vbo
= si_draw_vbo
;
4805 si_init_config(sctx
);
4808 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4810 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4813 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4814 struct si_pm4_state
*pm4
, unsigned value
)
4816 unsigned reg
= sctx
->chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4817 R_00802C_GRBM_GFX_INDEX
;
4818 si_pm4_set_reg(pm4
, reg
, value
);
4821 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4822 struct si_pm4_state
*pm4
, unsigned se
)
4824 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4825 si_set_grbm_gfx_index(sctx
, pm4
,
4826 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4827 S_030800_SE_INDEX(se
)) |
4828 S_030800_SH_BROADCAST_WRITES(1) |
4829 S_030800_INSTANCE_BROADCAST_WRITES(1));
4833 si_write_harvested_raster_configs(struct si_context
*sctx
,
4834 struct si_pm4_state
*pm4
,
4835 unsigned raster_config
,
4836 unsigned raster_config_1
)
4838 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4839 unsigned raster_config_se
[4];
4842 ac_get_harvested_configs(&sctx
->screen
->info
,
4847 for (se
= 0; se
< num_se
; se
++) {
4848 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4849 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
4851 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4853 if (sctx
->chip_class
>= CIK
) {
4854 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4858 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4860 struct si_screen
*sscreen
= sctx
->screen
;
4861 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
4862 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
4863 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
4864 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
4866 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4867 /* Always use the default config when all backends are enabled
4868 * (or when we failed to determine the enabled backends).
4870 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4872 if (sctx
->chip_class
>= CIK
)
4873 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4876 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4880 static void si_init_config(struct si_context
*sctx
)
4882 struct si_screen
*sscreen
= sctx
->screen
;
4883 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4884 bool has_clear_state
= sscreen
->has_clear_state
;
4885 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4887 /* Only SI can disable CLEAR_STATE for now. */
4888 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
);
4893 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4894 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4895 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4896 si_pm4_cmd_end(pm4
, false);
4898 if (has_clear_state
) {
4899 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4900 si_pm4_cmd_add(pm4
, 0);
4901 si_pm4_cmd_end(pm4
, false);
4904 if (sctx
->chip_class
<= VI
)
4905 si_set_raster_config(sctx
, pm4
);
4907 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4908 if (!has_clear_state
)
4909 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4911 /* FIXME calculate these values somehow ??? */
4912 if (sctx
->chip_class
<= VI
) {
4913 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4914 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4917 if (!has_clear_state
) {
4918 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4919 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4920 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4923 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4924 if (!has_clear_state
)
4925 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4926 if (sctx
->chip_class
< CIK
)
4927 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4928 S_008A14_CLIP_VTX_REORDER_ENA(1));
4930 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4931 * I don't know why. Deduced by trial and error.
4933 if (sctx
->chip_class
<= CIK
) {
4934 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4935 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4936 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4937 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4938 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4939 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4940 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4941 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4944 if (!has_clear_state
) {
4945 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4946 S_028230_ER_TRI(0xA) |
4947 S_028230_ER_POINT(0xA) |
4948 S_028230_ER_RECT(0xA) |
4949 /* Required by DX10_DIAMOND_TEST_ENA: */
4950 S_028230_ER_LINE_LR(0x1A) |
4951 S_028230_ER_LINE_RL(0x26) |
4952 S_028230_ER_LINE_TB(0xA) |
4953 S_028230_ER_LINE_BT(0xA));
4954 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4955 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4956 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4957 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4958 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4961 if (sctx
->chip_class
>= GFX9
) {
4962 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4963 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4964 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4966 /* These registers, when written, also overwrite the CLEAR_STATE
4967 * context, so we can't rely on CLEAR_STATE setting them.
4968 * It would be an issue if there was another UMD changing them.
4970 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4971 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4972 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4975 if (sctx
->chip_class
>= CIK
) {
4976 if (sctx
->chip_class
>= GFX9
) {
4977 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4978 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4980 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4981 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4982 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4983 S_00B41C_WAVE_LIMIT(0x3F));
4984 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
4985 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4987 /* If this is 0, Bonaire can hang even if GS isn't being used.
4988 * Other chips are unaffected. These are suboptimal values,
4989 * but we don't use on-chip GS.
4991 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4992 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4993 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4995 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
4996 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4998 /* Compute LATE_ALLOC_VS.LIMIT. */
4999 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5000 unsigned late_alloc_limit
; /* The limit is per SH. */
5002 if (sctx
->family
== CHIP_KABINI
) {
5003 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5004 } else if (num_cu_per_sh
<= 4) {
5005 /* Too few available compute units per SH. Disallowing
5006 * VS to run on one CU could hurt us more than late VS
5007 * allocation would help.
5009 * 2 is the highest safe number that allows us to keep
5012 late_alloc_limit
= 2;
5014 /* This is a good initial value, allowing 1 late_alloc
5015 * wave per SIMD on num_cu - 2.
5017 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5019 /* The limit is 0-based, so 0 means 1. */
5020 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
5021 late_alloc_limit
-= 1;
5024 /* VS can't execute on one CU if the limit is > 2. */
5025 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5026 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
5027 S_00B118_WAVE_LIMIT(0x3F));
5028 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5029 S_00B11C_LIMIT(late_alloc_limit
));
5030 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5031 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5034 if (sctx
->chip_class
>= VI
) {
5035 unsigned vgt_tess_distribution
;
5037 vgt_tess_distribution
=
5038 S_028B50_ACCUM_ISOLINE(32) |
5039 S_028B50_ACCUM_TRI(11) |
5040 S_028B50_ACCUM_QUAD(11) |
5041 S_028B50_DONUT_SPLIT(16);
5043 /* Testing with Unigine Heaven extreme tesselation yielded best results
5044 * with TRAP_SPLIT = 3.
5046 if (sctx
->family
== CHIP_FIJI
||
5047 sctx
->family
>= CHIP_POLARIS10
)
5048 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5050 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5051 } else if (!has_clear_state
) {
5052 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5053 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5056 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5057 if (sctx
->chip_class
>= CIK
) {
5058 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5059 S_028084_ADDRESS(border_color_va
>> 40));
5061 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5062 RADEON_PRIO_BORDER_COLORS
);
5064 if (sctx
->chip_class
>= GFX9
) {
5065 unsigned num_se
= sscreen
->info
.max_se
;
5066 unsigned pc_lines
= 0;
5068 switch (sctx
->family
) {
5081 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5082 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5083 S_028C48_MAX_PRIM_PER_BATCH(1023));
5084 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5085 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5086 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5089 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5090 sctx
->init_config
= pm4
;