2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 unsigned img_format
:9;
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
46 #include "gfx10_format_table.h"
48 static unsigned si_map_swizzle(unsigned swizzle
)
52 return V_008F0C_SQ_SEL_Y
;
54 return V_008F0C_SQ_SEL_Z
;
56 return V_008F0C_SQ_SEL_W
;
58 return V_008F0C_SQ_SEL_0
;
60 return V_008F0C_SQ_SEL_1
;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X
;
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x
)
70 x
>= 4096 ? 0xffff : x
* 16;
74 * Inferred framebuffer and blender state.
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
79 static void si_emit_cb_render_state(struct si_context
*sctx
)
81 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
82 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
&
86 blend
->cb_target_mask
;
89 /* Avoid a hang that happens when dual source blending is enabled
90 * but there is not enough color outputs. This is undefined behavior,
91 * so disable color writes completely.
93 * Reproducible with Unigine Heaven 4.0 and drirc missing.
95 if (blend
->dual_src_blend
&&
96 sctx
->ps_shader
.cso
&&
97 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
100 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
101 * I think we don't have to do anything between IBs.
103 if (sctx
->screen
->dpbb_allowed
&&
104 sctx
->last_cb_target_mask
!= cb_target_mask
) {
105 sctx
->last_cb_target_mask
= cb_target_mask
;
107 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
108 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
111 unsigned initial_cdw
= cs
->current
.cdw
;
112 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
113 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
115 if (sctx
->chip_class
>= GFX8
) {
116 /* DCC MSAA workaround.
117 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
118 * COMBINER_DISABLE, but that would be more complicated.
120 bool oc_disable
= blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&&
121 sctx
->framebuffer
.nr_samples
>= 2;
122 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
124 radeon_opt_set_context_reg(
125 sctx
, R_028424_CB_DCC_CONTROL
,
126 SI_TRACKED_CB_DCC_CONTROL
,
127 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
128 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
129 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
130 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
133 /* RB+ register settings. */
134 if (sctx
->screen
->info
.rbplus_allowed
) {
135 unsigned spi_shader_col_format
=
136 sctx
->ps_shader
.cso
?
137 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
138 unsigned sx_ps_downconvert
= 0;
139 unsigned sx_blend_opt_epsilon
= 0;
140 unsigned sx_blend_opt_control
= 0;
142 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
143 struct si_surface
*surf
=
144 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
145 unsigned format
, swap
, spi_format
, colormask
;
146 bool has_alpha
, has_rgb
;
149 /* If the color buffer is not set, the driver sets 32_R
150 * as the SPI color format, because the hw doesn't allow
151 * holes between color outputs, so also set this to
154 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
158 format
= G_028C70_FORMAT(surf
->cb_color_info
);
159 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
160 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
161 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
163 /* Set if RGB and A are present. */
164 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
166 if (format
== V_028C70_COLOR_8
||
167 format
== V_028C70_COLOR_16
||
168 format
== V_028C70_COLOR_32
)
169 has_rgb
= !has_alpha
;
173 /* Check the colormask and export format. */
174 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
176 if (!(colormask
& PIPE_MASK_A
))
179 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
184 /* Disable value checking for disabled channels. */
186 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
188 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
190 /* Enable down-conversion for 32bpp and smaller formats. */
192 case V_028C70_COLOR_8
:
193 case V_028C70_COLOR_8_8
:
194 case V_028C70_COLOR_8_8_8_8
:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
197 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
198 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
199 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
200 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
204 case V_028C70_COLOR_5_6_5
:
205 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
207 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
211 case V_028C70_COLOR_1_5_5_5
:
212 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
213 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
214 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
218 case V_028C70_COLOR_4_4_4_4
:
219 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
220 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
221 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
225 case V_028C70_COLOR_32
:
226 if (swap
== V_028C70_SWAP_STD
&&
227 spi_format
== V_028714_SPI_SHADER_32_R
)
228 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
229 else if (swap
== V_028C70_SWAP_ALT_REV
&&
230 spi_format
== V_028714_SPI_SHADER_32_AR
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
234 case V_028C70_COLOR_16
:
235 case V_028C70_COLOR_16_16
:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
238 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
239 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
240 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
241 if (swap
== V_028C70_SWAP_STD
||
242 swap
== V_028C70_SWAP_STD_REV
)
243 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
249 case V_028C70_COLOR_10_11_11
:
250 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
251 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
254 case V_028C70_COLOR_2_10_10_10
:
255 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
256 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
257 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
263 /* If there are no color outputs, the first color export is
264 * always enabled as 32_R, so also set this to enable RB+.
266 if (!sx_ps_downconvert
)
267 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
269 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
270 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
271 SI_TRACKED_SX_PS_DOWNCONVERT
,
272 sx_ps_downconvert
, sx_blend_opt_epsilon
,
273 sx_blend_opt_control
);
275 if (initial_cdw
!= cs
->current
.cdw
)
276 sctx
->context_roll
= true;
283 static uint32_t si_translate_blend_function(int blend_func
)
285 switch (blend_func
) {
287 return V_028780_COMB_DST_PLUS_SRC
;
288 case PIPE_BLEND_SUBTRACT
:
289 return V_028780_COMB_SRC_MINUS_DST
;
290 case PIPE_BLEND_REVERSE_SUBTRACT
:
291 return V_028780_COMB_DST_MINUS_SRC
;
293 return V_028780_COMB_MIN_DST_SRC
;
295 return V_028780_COMB_MAX_DST_SRC
;
297 PRINT_ERR("Unknown blend function %d\n", blend_func
);
304 static uint32_t si_translate_blend_factor(int blend_fact
)
306 switch (blend_fact
) {
307 case PIPE_BLENDFACTOR_ONE
:
308 return V_028780_BLEND_ONE
;
309 case PIPE_BLENDFACTOR_SRC_COLOR
:
310 return V_028780_BLEND_SRC_COLOR
;
311 case PIPE_BLENDFACTOR_SRC_ALPHA
:
312 return V_028780_BLEND_SRC_ALPHA
;
313 case PIPE_BLENDFACTOR_DST_ALPHA
:
314 return V_028780_BLEND_DST_ALPHA
;
315 case PIPE_BLENDFACTOR_DST_COLOR
:
316 return V_028780_BLEND_DST_COLOR
;
317 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
318 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
319 case PIPE_BLENDFACTOR_CONST_COLOR
:
320 return V_028780_BLEND_CONSTANT_COLOR
;
321 case PIPE_BLENDFACTOR_CONST_ALPHA
:
322 return V_028780_BLEND_CONSTANT_ALPHA
;
323 case PIPE_BLENDFACTOR_ZERO
:
324 return V_028780_BLEND_ZERO
;
325 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
326 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
327 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
328 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
329 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
330 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
331 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
333 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
335 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
336 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
337 case PIPE_BLENDFACTOR_SRC1_COLOR
:
338 return V_028780_BLEND_SRC1_COLOR
;
339 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
340 return V_028780_BLEND_SRC1_ALPHA
;
341 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
342 return V_028780_BLEND_INV_SRC1_COLOR
;
343 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
344 return V_028780_BLEND_INV_SRC1_ALPHA
;
346 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
353 static uint32_t si_translate_blend_opt_function(int blend_func
)
355 switch (blend_func
) {
357 return V_028760_OPT_COMB_ADD
;
358 case PIPE_BLEND_SUBTRACT
:
359 return V_028760_OPT_COMB_SUBTRACT
;
360 case PIPE_BLEND_REVERSE_SUBTRACT
:
361 return V_028760_OPT_COMB_REVSUBTRACT
;
363 return V_028760_OPT_COMB_MIN
;
365 return V_028760_OPT_COMB_MAX
;
367 return V_028760_OPT_COMB_BLEND_DISABLED
;
371 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
373 switch (blend_fact
) {
374 case PIPE_BLENDFACTOR_ZERO
:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
376 case PIPE_BLENDFACTOR_ONE
:
377 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
378 case PIPE_BLENDFACTOR_SRC_COLOR
:
379 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
380 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
381 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
382 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
383 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
384 case PIPE_BLENDFACTOR_SRC_ALPHA
:
385 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
386 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
387 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
388 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
389 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
390 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
396 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
397 struct si_state_blend
*blend
,
398 enum pipe_blend_func func
,
399 enum pipe_blendfactor src
,
400 enum pipe_blendfactor dst
,
403 /* Src factor is allowed when it does not depend on Dst */
404 static const uint32_t src_allowed
=
405 (1u << PIPE_BLENDFACTOR_ONE
) |
406 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
408 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
409 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
412 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
413 (1u << PIPE_BLENDFACTOR_ZERO
) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
417 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
419 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
421 if (dst
== PIPE_BLENDFACTOR_ONE
&&
422 (src_allowed
& (1u << src
))) {
423 /* Addition is commutative, but floating point addition isn't
424 * associative: subtle changes can be introduced via different
427 * Out-of-order is also non-deterministic, which means that
428 * this breaks OpenGL invariance requirements. So only enable
429 * out-of-order additive blending if explicitly allowed by a
432 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
433 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
434 blend
->commutative_4bit
|= chanmask
;
439 * Get rid of DST in the blend factors by commuting the operands:
440 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
442 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
443 unsigned *dst_factor
, unsigned expected_dst
,
444 unsigned replacement_src
)
446 if (*src_factor
== expected_dst
&&
447 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
448 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
449 *dst_factor
= replacement_src
;
451 /* Commuting the operands requires reversing subtractions. */
452 if (*func
== PIPE_BLEND_SUBTRACT
)
453 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
454 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
455 *func
= PIPE_BLEND_SUBTRACT
;
459 static bool si_blend_factor_uses_dst(unsigned factor
)
461 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
462 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
463 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
464 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
465 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
468 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
469 const struct pipe_blend_state
*state
,
472 struct si_context
*sctx
= (struct si_context
*)ctx
;
473 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
474 struct si_pm4_state
*pm4
= &blend
->pm4
;
475 uint32_t sx_mrt_blend_opt
[8] = {0};
476 uint32_t color_control
= 0;
477 bool logicop_enable
= state
->logicop_enable
&&
478 state
->logicop_func
!= PIPE_LOGICOP_COPY
;
483 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
484 blend
->alpha_to_one
= state
->alpha_to_one
;
485 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
486 blend
->logicop_enable
= logicop_enable
;
488 if (logicop_enable
) {
489 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
491 color_control
|= S_028808_ROP3(0xcc);
494 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
495 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
496 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
497 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
498 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
499 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
500 S_028B70_OFFSET_ROUND(1));
502 if (state
->alpha_to_coverage
)
503 blend
->need_src_alpha_4bit
|= 0xf;
505 blend
->cb_target_mask
= 0;
506 blend
->cb_target_enabled_4bit
= 0;
508 for (int i
= 0; i
< 8; i
++) {
509 /* state->rt entries > 0 only written if independent blending */
510 const int j
= state
->independent_blend_enable
? i
: 0;
512 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
513 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
514 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
515 unsigned eqA
= state
->rt
[j
].alpha_func
;
516 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
517 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
519 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
520 unsigned blend_cntl
= 0;
522 sx_mrt_blend_opt
[i
] =
523 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
524 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
526 /* Only set dual source blending for MRT0 to avoid a hang. */
527 if (i
>= 1 && blend
->dual_src_blend
) {
528 /* Vulkan does this for dual source blending. */
530 blend_cntl
|= S_028780_ENABLE(1);
532 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
536 /* Only addition and subtraction equations are supported with
537 * dual source blending.
539 if (blend
->dual_src_blend
&&
540 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
541 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
542 assert(!"Unsupported equation for dual source blending");
543 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
547 /* cb_render_state will disable unused ones */
548 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
549 if (state
->rt
[j
].colormask
)
550 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
552 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
553 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
557 si_blend_check_commutativity(sctx
->screen
, blend
,
558 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
559 si_blend_check_commutativity(sctx
->screen
, blend
,
560 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
562 /* Blending optimizations for RB+.
563 * These transformations don't change the behavior.
565 * First, get rid of DST in the blend factors:
566 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
568 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
569 PIPE_BLENDFACTOR_DST_COLOR
,
570 PIPE_BLENDFACTOR_SRC_COLOR
);
571 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
572 PIPE_BLENDFACTOR_DST_COLOR
,
573 PIPE_BLENDFACTOR_SRC_COLOR
);
574 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
575 PIPE_BLENDFACTOR_DST_ALPHA
,
576 PIPE_BLENDFACTOR_SRC_ALPHA
);
578 /* Look up the ideal settings from tables. */
579 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
580 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
581 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
582 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
584 /* Handle interdependencies. */
585 if (si_blend_factor_uses_dst(srcRGB
))
586 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
587 if (si_blend_factor_uses_dst(srcA
))
588 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
590 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
591 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
592 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
593 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
594 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
596 /* Set the final value. */
597 sx_mrt_blend_opt
[i
] =
598 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
599 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
600 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
601 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
602 S_028760_ALPHA_DST_OPT(dstA_opt
) |
603 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
605 /* Set blend state. */
606 blend_cntl
|= S_028780_ENABLE(1);
607 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
608 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
609 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
611 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
612 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
613 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
614 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
615 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
617 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
619 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
621 if (sctx
->family
<= CHIP_NAVI14
)
622 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
624 /* This is only important for formats without alpha. */
625 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
626 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
627 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
628 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
629 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
630 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
631 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
634 if (sctx
->family
<= CHIP_NAVI14
&& logicop_enable
)
635 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
637 if (blend
->cb_target_mask
) {
638 color_control
|= S_028808_MODE(mode
);
640 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
643 if (sctx
->screen
->info
.rbplus_allowed
) {
644 /* Disable RB+ blend optimizations for dual source blending.
647 if (blend
->dual_src_blend
) {
648 for (int i
= 0; i
< 8; i
++) {
649 sx_mrt_blend_opt
[i
] =
650 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
651 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
655 for (int i
= 0; i
< 8; i
++)
656 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
657 sx_mrt_blend_opt
[i
]);
659 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
660 if (blend
->dual_src_blend
|| logicop_enable
||
661 mode
== V_028808_CB_RESOLVE
)
662 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
665 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
669 static void *si_create_blend_state(struct pipe_context
*ctx
,
670 const struct pipe_blend_state
*state
)
672 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
675 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
677 struct si_context
*sctx
= (struct si_context
*)ctx
;
678 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
679 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
682 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
684 si_pm4_bind_state(sctx
, blend
, blend
);
686 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
687 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
688 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
689 sctx
->framebuffer
.nr_samples
>= 2 &&
690 sctx
->screen
->dcc_msaa_allowed
))
691 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
693 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
694 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
695 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
696 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
697 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
698 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
699 sctx
->do_update_shaders
= true;
701 if (sctx
->screen
->dpbb_allowed
&&
702 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
703 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
704 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
705 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
707 if (sctx
->screen
->has_out_of_order_rast
&&
708 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
709 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
710 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
711 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
712 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
715 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
717 struct si_context
*sctx
= (struct si_context
*)ctx
;
719 if (sctx
->queued
.named
.blend
== state
)
720 si_bind_blend_state(ctx
, sctx
->noop_blend
);
722 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
725 static void si_set_blend_color(struct pipe_context
*ctx
,
726 const struct pipe_blend_color
*state
)
728 struct si_context
*sctx
= (struct si_context
*)ctx
;
729 static const struct pipe_blend_color zeros
;
731 sctx
->blend_color
.state
= *state
;
732 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
733 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
736 static void si_emit_blend_color(struct si_context
*sctx
)
738 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
740 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
741 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
748 static void si_set_clip_state(struct pipe_context
*ctx
,
749 const struct pipe_clip_state
*state
)
751 struct si_context
*sctx
= (struct si_context
*)ctx
;
752 struct pipe_constant_buffer cb
;
753 static const struct pipe_clip_state zeros
;
755 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
758 sctx
->clip_state
.state
= *state
;
759 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
760 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
763 cb
.user_buffer
= state
->ucp
;
764 cb
.buffer_offset
= 0;
765 cb
.buffer_size
= 4*4*8;
766 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
767 pipe_resource_reference(&cb
.buffer
, NULL
);
770 static void si_emit_clip_state(struct si_context
*sctx
)
772 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
774 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
775 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
778 static void si_emit_clip_regs(struct si_context
*sctx
)
780 struct si_shader
*vs
= si_get_vs_state(sctx
);
781 struct si_shader_selector
*vs_sel
= vs
->selector
;
782 struct tgsi_shader_info
*info
= &vs_sel
->info
;
783 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
784 unsigned window_space
=
785 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
786 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
787 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
788 unsigned culldist_mask
= vs_sel
->culldist_mask
;
791 if (vs
->key
.opt
.clip_disable
) {
792 assert(!info
->culldist_writemask
);
796 total_mask
= clipdist_mask
| culldist_mask
;
798 /* Clip distances on points have no effect, so need to be implemented
799 * as cull distances. This applies for the clipvertex case as well.
801 * Setting this for primitives other than points should have no adverse
804 clipdist_mask
&= rs
->clip_plane_enable
;
805 culldist_mask
|= clipdist_mask
;
807 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
808 unsigned pa_cl_cntl
= S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
809 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
810 clipdist_mask
| (culldist_mask
<< 8);
812 if (sctx
->chip_class
>= GFX10
) {
813 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
814 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
816 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
818 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
819 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
820 vs_sel
->pa_cl_vs_out_cntl
| pa_cl_cntl
);
822 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
823 SI_TRACKED_PA_CL_CLIP_CNTL
,
824 rs
->pa_cl_clip_cntl
|
826 S_028810_CLIP_DISABLE(window_space
));
828 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
829 sctx
->context_roll
= true;
833 * inferred state between framebuffer and rasterizer
835 static void si_update_poly_offset_state(struct si_context
*sctx
)
837 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
839 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
840 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
844 /* Use the user format, not db_render_format, so that the polygon
845 * offset behaves as expected by applications.
847 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
848 case PIPE_FORMAT_Z16_UNORM
:
849 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
851 default: /* 24-bit */
852 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
854 case PIPE_FORMAT_Z32_FLOAT
:
855 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
856 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
865 static uint32_t si_translate_fill(uint32_t func
)
868 case PIPE_POLYGON_MODE_FILL
:
869 return V_028814_X_DRAW_TRIANGLES
;
870 case PIPE_POLYGON_MODE_LINE
:
871 return V_028814_X_DRAW_LINES
;
872 case PIPE_POLYGON_MODE_POINT
:
873 return V_028814_X_DRAW_POINTS
;
876 return V_028814_X_DRAW_POINTS
;
880 static void *si_create_rs_state(struct pipe_context
*ctx
,
881 const struct pipe_rasterizer_state
*state
)
883 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
884 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
885 struct si_pm4_state
*pm4
= &rs
->pm4
;
887 float psize_min
, psize_max
;
893 if (!state
->front_ccw
) {
894 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
895 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
897 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
898 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
900 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
901 rs
->provoking_vertex_first
= state
->flatshade_first
;
902 rs
->scissor_enable
= state
->scissor
;
903 rs
->clip_halfz
= state
->clip_halfz
;
904 rs
->two_side
= state
->light_twoside
;
905 rs
->multisample_enable
= state
->multisample
;
906 rs
->force_persample_interp
= state
->force_persample_interp
;
907 rs
->clip_plane_enable
= state
->clip_plane_enable
;
908 rs
->half_pixel_center
= state
->half_pixel_center
;
909 rs
->line_stipple_enable
= state
->line_stipple_enable
;
910 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
911 rs
->line_smooth
= state
->line_smooth
;
912 rs
->line_width
= state
->line_width
;
913 rs
->poly_smooth
= state
->poly_smooth
;
914 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
916 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
917 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
918 rs
->flatshade
= state
->flatshade
;
919 rs
->flatshade_first
= state
->flatshade_first
;
920 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
921 rs
->rasterizer_discard
= state
->rasterizer_discard
;
922 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
923 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
924 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
925 rs
->pa_cl_clip_cntl
=
926 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
927 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
928 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
929 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
930 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
932 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
933 S_0286D4_FLAT_SHADE_ENA(1) |
934 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
935 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
936 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
937 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
938 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
939 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
941 /* point size 12.4 fixed point */
942 tmp
= (unsigned)(state
->point_size
* 8.0);
943 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
945 if (state
->point_size_per_vertex
) {
946 psize_min
= util_get_min_point_size(state
);
947 psize_max
= SI_MAX_POINT_SIZE
;
949 /* Force the point size to be as if the vertex output was disabled. */
950 psize_min
= state
->point_size
;
951 psize_max
= state
->point_size
;
953 rs
->max_point_size
= psize_max
;
955 /* Divide by two, because 0.5 = 1 pixel. */
956 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
957 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
958 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
960 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
961 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
962 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
963 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
964 S_028A48_MSAA_ENABLE(state
->multisample
||
965 state
->poly_smooth
||
966 state
->line_smooth
) |
967 S_028A48_VPORT_SCISSOR_ENABLE(1) |
968 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
970 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
971 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
972 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
973 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
974 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
975 S_028814_FACE(!state
->front_ccw
) |
976 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
977 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
978 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
979 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
980 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
981 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
982 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
984 if (!rs
->uses_poly_offset
)
987 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
988 if (!rs
->pm4_poly_offset
) {
993 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
994 for (i
= 0; i
< 3; i
++) {
995 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
996 float offset_units
= state
->offset_units
;
997 float offset_scale
= state
->offset_scale
* 16.0f
;
998 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
1000 if (!state
->offset_units_unscaled
) {
1002 case 0: /* 16-bit zbuffer */
1003 offset_units
*= 4.0f
;
1004 pa_su_poly_offset_db_fmt_cntl
=
1005 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1007 case 1: /* 24-bit zbuffer */
1008 offset_units
*= 2.0f
;
1009 pa_su_poly_offset_db_fmt_cntl
=
1010 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1012 case 2: /* 32-bit zbuffer */
1013 offset_units
*= 1.0f
;
1014 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1015 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1020 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1022 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1024 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1026 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1028 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1029 pa_su_poly_offset_db_fmt_cntl
);
1035 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1037 struct si_context
*sctx
= (struct si_context
*)ctx
;
1038 struct si_state_rasterizer
*old_rs
=
1039 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1040 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1043 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
1045 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1046 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1048 /* Update the small primitive filter workaround if necessary. */
1049 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&&
1050 sctx
->framebuffer
.nr_samples
> 1)
1051 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1054 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1055 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1057 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1058 si_update_poly_offset_state(sctx
);
1060 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1061 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1063 if (old_rs
->line_width
!= rs
->line_width
||
1064 old_rs
->max_point_size
!= rs
->max_point_size
||
1065 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1066 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1068 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1069 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1071 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1072 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1073 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1075 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1076 rs
->line_stipple_enable
;
1078 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1079 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1080 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1081 old_rs
->flatshade
!= rs
->flatshade
||
1082 old_rs
->two_side
!= rs
->two_side
||
1083 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1084 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1085 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1086 old_rs
->line_smooth
!= rs
->line_smooth
||
1087 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1088 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1089 sctx
->do_update_shaders
= true;
1092 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1094 struct si_context
*sctx
= (struct si_context
*)ctx
;
1095 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1097 if (sctx
->queued
.named
.rasterizer
== state
)
1098 si_bind_rs_state(ctx
, sctx
->discard_rasterizer_state
);
1100 FREE(rs
->pm4_poly_offset
);
1101 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1105 * infeered state between dsa and stencil ref
1107 static void si_emit_stencil_ref(struct si_context
*sctx
)
1109 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1110 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1111 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1113 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1114 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1115 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1116 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1117 S_028430_STENCILOPVAL(1));
1118 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1119 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1120 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1121 S_028434_STENCILOPVAL_BF(1));
1124 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1125 const struct pipe_stencil_ref
*state
)
1127 struct si_context
*sctx
= (struct si_context
*)ctx
;
1129 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1132 sctx
->stencil_ref
.state
= *state
;
1133 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1141 static uint32_t si_translate_stencil_op(int s_op
)
1144 case PIPE_STENCIL_OP_KEEP
:
1145 return V_02842C_STENCIL_KEEP
;
1146 case PIPE_STENCIL_OP_ZERO
:
1147 return V_02842C_STENCIL_ZERO
;
1148 case PIPE_STENCIL_OP_REPLACE
:
1149 return V_02842C_STENCIL_REPLACE_TEST
;
1150 case PIPE_STENCIL_OP_INCR
:
1151 return V_02842C_STENCIL_ADD_CLAMP
;
1152 case PIPE_STENCIL_OP_DECR
:
1153 return V_02842C_STENCIL_SUB_CLAMP
;
1154 case PIPE_STENCIL_OP_INCR_WRAP
:
1155 return V_02842C_STENCIL_ADD_WRAP
;
1156 case PIPE_STENCIL_OP_DECR_WRAP
:
1157 return V_02842C_STENCIL_SUB_WRAP
;
1158 case PIPE_STENCIL_OP_INVERT
:
1159 return V_02842C_STENCIL_INVERT
;
1161 PRINT_ERR("Unknown stencil op %d", s_op
);
1168 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1170 return s
->enabled
&& s
->writemask
&&
1171 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1172 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1173 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1176 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1178 /* REPLACE is normally order invariant, except when the stencil
1179 * reference value is written by the fragment shader. Tracking this
1180 * interaction does not seem worth the effort, so be conservative. */
1181 return op
!= PIPE_STENCIL_OP_INCR
&&
1182 op
!= PIPE_STENCIL_OP_DECR
&&
1183 op
!= PIPE_STENCIL_OP_REPLACE
;
1186 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1187 * invariant in the sense that the set of passing fragments as well as the
1188 * final stencil buffer result does not depend on the order of fragments. */
1189 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1191 return !state
->enabled
|| !state
->writemask
||
1192 /* The following assumes that Z writes are disabled. */
1193 (state
->func
== PIPE_FUNC_ALWAYS
&&
1194 si_order_invariant_stencil_op(state
->zpass_op
) &&
1195 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1196 (state
->func
== PIPE_FUNC_NEVER
&&
1197 si_order_invariant_stencil_op(state
->fail_op
));
1200 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1201 const struct pipe_depth_stencil_alpha_state
*state
)
1203 struct si_context
*sctx
= (struct si_context
*)ctx
;
1204 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1205 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1206 unsigned db_depth_control
;
1207 uint32_t db_stencil_control
= 0;
1213 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1214 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1215 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1216 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1218 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1219 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1220 S_028800_ZFUNC(state
->depth
.func
) |
1221 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1224 if (state
->stencil
[0].enabled
) {
1225 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1226 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1227 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1228 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1229 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1231 if (state
->stencil
[1].enabled
) {
1232 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1233 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1234 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1235 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1236 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1241 if (state
->alpha
.enabled
) {
1242 dsa
->alpha_func
= state
->alpha
.func
;
1244 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1245 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1247 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1250 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1251 if (state
->stencil
[0].enabled
)
1252 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1253 if (state
->depth
.bounds_test
) {
1254 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1255 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1258 dsa
->depth_enabled
= state
->depth
.enabled
;
1259 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1260 state
->depth
.writemask
;
1261 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1262 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1263 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1264 si_dsa_writes_stencil(&state
->stencil
[1]));
1265 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1266 dsa
->stencil_write_enabled
;
1268 bool zfunc_is_ordered
=
1269 state
->depth
.func
== PIPE_FUNC_NEVER
||
1270 state
->depth
.func
== PIPE_FUNC_LESS
||
1271 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1272 state
->depth
.func
== PIPE_FUNC_GREATER
||
1273 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1275 bool nozwrite_and_order_invariant_stencil
=
1276 !dsa
->db_can_write
||
1277 (!dsa
->depth_write_enabled
&&
1278 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1279 si_order_invariant_stencil_state(&state
->stencil
[1]));
1281 dsa
->order_invariance
[1].zs
=
1282 nozwrite_and_order_invariant_stencil
||
1283 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1284 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1286 dsa
->order_invariance
[1].pass_set
=
1287 nozwrite_and_order_invariant_stencil
||
1288 (!dsa
->stencil_write_enabled
&&
1289 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1290 state
->depth
.func
== PIPE_FUNC_NEVER
));
1291 dsa
->order_invariance
[0].pass_set
=
1292 !dsa
->depth_write_enabled
||
1293 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1294 state
->depth
.func
== PIPE_FUNC_NEVER
);
1296 dsa
->order_invariance
[1].pass_last
=
1297 sctx
->screen
->assume_no_z_fights
&&
1298 !dsa
->stencil_write_enabled
&&
1299 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1300 dsa
->order_invariance
[0].pass_last
=
1301 sctx
->screen
->assume_no_z_fights
&&
1302 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1307 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1309 struct si_context
*sctx
= (struct si_context
*)ctx
;
1310 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1311 struct si_state_dsa
*dsa
= state
;
1314 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1316 si_pm4_bind_state(sctx
, dsa
, dsa
);
1318 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1319 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1320 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1321 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1324 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1325 sctx
->do_update_shaders
= true;
1327 if (sctx
->screen
->dpbb_allowed
&&
1328 ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1329 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1330 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1331 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1333 if (sctx
->screen
->has_out_of_order_rast
&&
1334 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1335 sizeof(old_dsa
->order_invariance
))))
1336 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1339 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1341 struct si_context
*sctx
= (struct si_context
*)ctx
;
1343 if (sctx
->queued
.named
.dsa
== state
)
1344 si_bind_dsa_state(ctx
, sctx
->noop_dsa
);
1346 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1349 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1351 struct pipe_depth_stencil_alpha_state dsa
= {};
1353 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1356 /* DB RENDER STATE */
1358 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1360 struct si_context
*sctx
= (struct si_context
*)ctx
;
1362 /* Pipeline stat & streamout queries. */
1364 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1365 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1367 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1368 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1371 /* Occlusion queries. */
1372 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1373 sctx
->occlusion_queries_disabled
= !enable
;
1374 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1378 void si_set_occlusion_query_state(struct si_context
*sctx
,
1379 bool old_perfect_enable
)
1381 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1383 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1385 if (perfect_enable
!= old_perfect_enable
)
1386 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1389 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1391 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1393 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1394 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1396 st
->saved_ssbo_writable_mask
= 0;
1398 for (unsigned i
= 0; i
< 3; i
++) {
1399 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1400 (1u << si_get_shaderbuf_slot(i
)))
1401 st
->saved_ssbo_writable_mask
|= 1 << i
;
1405 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1407 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1409 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1410 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1412 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1413 st
->saved_ssbo_writable_mask
);
1414 for (unsigned i
= 0; i
< 3; ++i
)
1415 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1418 static void si_emit_db_render_state(struct si_context
*sctx
)
1420 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1421 unsigned db_shader_control
, db_render_control
, db_count_control
;
1422 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1424 /* DB_RENDER_CONTROL */
1425 if (sctx
->dbcb_depth_copy_enabled
||
1426 sctx
->dbcb_stencil_copy_enabled
) {
1428 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1429 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1430 S_028000_COPY_CENTROID(1) |
1431 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1432 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1434 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1435 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1438 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1439 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1442 /* DB_COUNT_CONTROL (occlusion queries) */
1443 if (sctx
->num_occlusion_queries
> 0 &&
1444 !sctx
->occlusion_queries_disabled
) {
1445 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1446 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1448 if (sctx
->chip_class
>= GFX7
) {
1449 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1451 /* Stoney doesn't increment occlusion query counters
1452 * if the sample rate is 16x. Use 8x sample rate instead.
1454 if (sctx
->family
== CHIP_STONEY
)
1455 log_sample_rate
= MIN2(log_sample_rate
, 3);
1458 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1459 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1460 S_028004_SAMPLE_RATE(log_sample_rate
) |
1461 S_028004_ZPASS_ENABLE(1) |
1462 S_028004_SLICE_EVEN_ENABLE(1) |
1463 S_028004_SLICE_ODD_ENABLE(1);
1466 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1467 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1470 /* Disable occlusion queries. */
1471 if (sctx
->chip_class
>= GFX7
) {
1472 db_count_control
= 0;
1474 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1478 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1479 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1482 /* DB_RENDER_OVERRIDE2 */
1483 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1484 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1485 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1486 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1487 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1489 db_shader_control
= sctx
->ps_db_shader_control
;
1491 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1492 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1493 db_shader_control
&= C_02880C_Z_ORDER
;
1494 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1497 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1498 if (!rs
->multisample_enable
)
1499 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1501 if (sctx
->screen
->info
.has_rbplus
&&
1502 !sctx
->screen
->info
.rbplus_allowed
)
1503 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1505 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1506 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1508 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1509 sctx
->context_roll
= true;
1513 * format translation
1515 static uint32_t si_translate_colorformat(enum pipe_format format
)
1517 const struct util_format_description
*desc
= util_format_description(format
);
1519 return V_028C70_COLOR_INVALID
;
1521 #define HAS_SIZE(x,y,z,w) \
1522 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1523 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1525 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1526 return V_028C70_COLOR_10_11_11
;
1528 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1529 return V_028C70_COLOR_INVALID
;
1531 /* hw cannot support mixed formats (except depth/stencil, since
1532 * stencil is not written to). */
1533 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1534 return V_028C70_COLOR_INVALID
;
1536 switch (desc
->nr_channels
) {
1538 switch (desc
->channel
[0].size
) {
1540 return V_028C70_COLOR_8
;
1542 return V_028C70_COLOR_16
;
1544 return V_028C70_COLOR_32
;
1548 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1549 switch (desc
->channel
[0].size
) {
1551 return V_028C70_COLOR_8_8
;
1553 return V_028C70_COLOR_16_16
;
1555 return V_028C70_COLOR_32_32
;
1557 } else if (HAS_SIZE(8,24,0,0)) {
1558 return V_028C70_COLOR_24_8
;
1559 } else if (HAS_SIZE(24,8,0,0)) {
1560 return V_028C70_COLOR_8_24
;
1564 if (HAS_SIZE(5,6,5,0)) {
1565 return V_028C70_COLOR_5_6_5
;
1566 } else if (HAS_SIZE(32,8,24,0)) {
1567 return V_028C70_COLOR_X24_8_32_FLOAT
;
1571 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1572 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1573 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1574 switch (desc
->channel
[0].size
) {
1576 return V_028C70_COLOR_4_4_4_4
;
1578 return V_028C70_COLOR_8_8_8_8
;
1580 return V_028C70_COLOR_16_16_16_16
;
1582 return V_028C70_COLOR_32_32_32_32
;
1584 } else if (HAS_SIZE(5,5,5,1)) {
1585 return V_028C70_COLOR_1_5_5_5
;
1586 } else if (HAS_SIZE(1,5,5,5)) {
1587 return V_028C70_COLOR_5_5_5_1
;
1588 } else if (HAS_SIZE(10,10,10,2)) {
1589 return V_028C70_COLOR_2_10_10_10
;
1593 return V_028C70_COLOR_INVALID
;
1596 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1598 if (SI_BIG_ENDIAN
) {
1599 switch(colorformat
) {
1600 /* 8-bit buffers. */
1601 case V_028C70_COLOR_8
:
1602 return V_028C70_ENDIAN_NONE
;
1604 /* 16-bit buffers. */
1605 case V_028C70_COLOR_5_6_5
:
1606 case V_028C70_COLOR_1_5_5_5
:
1607 case V_028C70_COLOR_4_4_4_4
:
1608 case V_028C70_COLOR_16
:
1609 case V_028C70_COLOR_8_8
:
1610 return V_028C70_ENDIAN_8IN16
;
1612 /* 32-bit buffers. */
1613 case V_028C70_COLOR_8_8_8_8
:
1614 case V_028C70_COLOR_2_10_10_10
:
1615 case V_028C70_COLOR_8_24
:
1616 case V_028C70_COLOR_24_8
:
1617 case V_028C70_COLOR_16_16
:
1618 return V_028C70_ENDIAN_8IN32
;
1620 /* 64-bit buffers. */
1621 case V_028C70_COLOR_16_16_16_16
:
1622 return V_028C70_ENDIAN_8IN16
;
1624 case V_028C70_COLOR_32_32
:
1625 return V_028C70_ENDIAN_8IN32
;
1627 /* 128-bit buffers. */
1628 case V_028C70_COLOR_32_32_32_32
:
1629 return V_028C70_ENDIAN_8IN32
;
1631 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1634 return V_028C70_ENDIAN_NONE
;
1638 static uint32_t si_translate_dbformat(enum pipe_format format
)
1641 case PIPE_FORMAT_Z16_UNORM
:
1642 return V_028040_Z_16
;
1643 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1644 case PIPE_FORMAT_X8Z24_UNORM
:
1645 case PIPE_FORMAT_Z24X8_UNORM
:
1646 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1647 return V_028040_Z_24
; /* deprecated on AMD GCN */
1648 case PIPE_FORMAT_Z32_FLOAT
:
1649 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1650 return V_028040_Z_32_FLOAT
;
1652 return V_028040_Z_INVALID
;
1657 * Texture translation
1660 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1661 enum pipe_format format
,
1662 const struct util_format_description
*desc
,
1665 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1666 bool uniform
= true;
1669 assert(sscreen
->info
.chip_class
<= GFX9
);
1671 /* Colorspace (return non-RGB formats directly). */
1672 switch (desc
->colorspace
) {
1673 /* Depth stencil formats */
1674 case UTIL_FORMAT_COLORSPACE_ZS
:
1676 case PIPE_FORMAT_Z16_UNORM
:
1677 return V_008F14_IMG_DATA_FORMAT_16
;
1678 case PIPE_FORMAT_X24S8_UINT
:
1679 case PIPE_FORMAT_S8X24_UINT
:
1681 * Implemented as an 8_8_8_8 data format to fix texture
1682 * gathers in stencil sampling. This affects at least
1683 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1685 if (sscreen
->info
.chip_class
<= GFX8
)
1686 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1688 if (format
== PIPE_FORMAT_X24S8_UINT
)
1689 return V_008F14_IMG_DATA_FORMAT_8_24
;
1691 return V_008F14_IMG_DATA_FORMAT_24_8
;
1692 case PIPE_FORMAT_Z24X8_UNORM
:
1693 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1694 return V_008F14_IMG_DATA_FORMAT_8_24
;
1695 case PIPE_FORMAT_X8Z24_UNORM
:
1696 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1697 return V_008F14_IMG_DATA_FORMAT_24_8
;
1698 case PIPE_FORMAT_S8_UINT
:
1699 return V_008F14_IMG_DATA_FORMAT_8
;
1700 case PIPE_FORMAT_Z32_FLOAT
:
1701 return V_008F14_IMG_DATA_FORMAT_32
;
1702 case PIPE_FORMAT_X32_S8X24_UINT
:
1703 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1704 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1709 case UTIL_FORMAT_COLORSPACE_YUV
:
1710 goto out_unknown
; /* TODO */
1712 case UTIL_FORMAT_COLORSPACE_SRGB
:
1713 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1721 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1722 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1726 case PIPE_FORMAT_RGTC1_SNORM
:
1727 case PIPE_FORMAT_LATC1_SNORM
:
1728 case PIPE_FORMAT_RGTC1_UNORM
:
1729 case PIPE_FORMAT_LATC1_UNORM
:
1730 return V_008F14_IMG_DATA_FORMAT_BC4
;
1731 case PIPE_FORMAT_RGTC2_SNORM
:
1732 case PIPE_FORMAT_LATC2_SNORM
:
1733 case PIPE_FORMAT_RGTC2_UNORM
:
1734 case PIPE_FORMAT_LATC2_UNORM
:
1735 return V_008F14_IMG_DATA_FORMAT_BC5
;
1741 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1742 (sscreen
->info
.family
== CHIP_STONEY
||
1743 sscreen
->info
.family
== CHIP_VEGA10
||
1744 sscreen
->info
.family
== CHIP_RAVEN
)) {
1746 case PIPE_FORMAT_ETC1_RGB8
:
1747 case PIPE_FORMAT_ETC2_RGB8
:
1748 case PIPE_FORMAT_ETC2_SRGB8
:
1749 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1750 case PIPE_FORMAT_ETC2_RGB8A1
:
1751 case PIPE_FORMAT_ETC2_SRGB8A1
:
1752 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1753 case PIPE_FORMAT_ETC2_RGBA8
:
1754 case PIPE_FORMAT_ETC2_SRGBA8
:
1755 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1756 case PIPE_FORMAT_ETC2_R11_UNORM
:
1757 case PIPE_FORMAT_ETC2_R11_SNORM
:
1758 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1759 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1760 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1761 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1767 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1768 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1772 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1773 case PIPE_FORMAT_BPTC_SRGBA
:
1774 return V_008F14_IMG_DATA_FORMAT_BC7
;
1775 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1776 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1777 return V_008F14_IMG_DATA_FORMAT_BC6
;
1783 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1785 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1786 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1787 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1788 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1789 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1790 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1796 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1797 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1801 case PIPE_FORMAT_DXT1_RGB
:
1802 case PIPE_FORMAT_DXT1_RGBA
:
1803 case PIPE_FORMAT_DXT1_SRGB
:
1804 case PIPE_FORMAT_DXT1_SRGBA
:
1805 return V_008F14_IMG_DATA_FORMAT_BC1
;
1806 case PIPE_FORMAT_DXT3_RGBA
:
1807 case PIPE_FORMAT_DXT3_SRGBA
:
1808 return V_008F14_IMG_DATA_FORMAT_BC2
;
1809 case PIPE_FORMAT_DXT5_RGBA
:
1810 case PIPE_FORMAT_DXT5_SRGBA
:
1811 return V_008F14_IMG_DATA_FORMAT_BC3
;
1817 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1818 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1819 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1820 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1823 /* R8G8Bx_SNORM - TODO CxV8U8 */
1825 /* hw cannot support mixed formats (except depth/stencil, since only
1827 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1830 /* See whether the components are of the same size. */
1831 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1832 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1835 /* Non-uniform formats. */
1837 switch(desc
->nr_channels
) {
1839 if (desc
->channel
[0].size
== 5 &&
1840 desc
->channel
[1].size
== 6 &&
1841 desc
->channel
[2].size
== 5) {
1842 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1846 if (desc
->channel
[0].size
== 5 &&
1847 desc
->channel
[1].size
== 5 &&
1848 desc
->channel
[2].size
== 5 &&
1849 desc
->channel
[3].size
== 1) {
1850 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1852 if (desc
->channel
[0].size
== 1 &&
1853 desc
->channel
[1].size
== 5 &&
1854 desc
->channel
[2].size
== 5 &&
1855 desc
->channel
[3].size
== 5) {
1856 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1858 if (desc
->channel
[0].size
== 10 &&
1859 desc
->channel
[1].size
== 10 &&
1860 desc
->channel
[2].size
== 10 &&
1861 desc
->channel
[3].size
== 2) {
1862 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1869 if (first_non_void
< 0 || first_non_void
> 3)
1872 /* uniform formats */
1873 switch (desc
->channel
[first_non_void
].size
) {
1875 switch (desc
->nr_channels
) {
1876 #if 0 /* Not supported for render targets */
1878 return V_008F14_IMG_DATA_FORMAT_4_4
;
1881 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1885 switch (desc
->nr_channels
) {
1887 return V_008F14_IMG_DATA_FORMAT_8
;
1889 return V_008F14_IMG_DATA_FORMAT_8_8
;
1891 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1895 switch (desc
->nr_channels
) {
1897 return V_008F14_IMG_DATA_FORMAT_16
;
1899 return V_008F14_IMG_DATA_FORMAT_16_16
;
1901 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1905 switch (desc
->nr_channels
) {
1907 return V_008F14_IMG_DATA_FORMAT_32
;
1909 return V_008F14_IMG_DATA_FORMAT_32_32
;
1910 #if 0 /* Not supported for render targets */
1912 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1915 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1923 static unsigned si_tex_wrap(unsigned wrap
)
1927 case PIPE_TEX_WRAP_REPEAT
:
1928 return V_008F30_SQ_TEX_WRAP
;
1929 case PIPE_TEX_WRAP_CLAMP
:
1930 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1931 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1932 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1933 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1934 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1935 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1936 return V_008F30_SQ_TEX_MIRROR
;
1937 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1938 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1939 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1940 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1941 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1942 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1946 static unsigned si_tex_mipfilter(unsigned filter
)
1949 case PIPE_TEX_MIPFILTER_NEAREST
:
1950 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1951 case PIPE_TEX_MIPFILTER_LINEAR
:
1952 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1954 case PIPE_TEX_MIPFILTER_NONE
:
1955 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1959 static unsigned si_tex_compare(unsigned compare
)
1963 case PIPE_FUNC_NEVER
:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1965 case PIPE_FUNC_LESS
:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1967 case PIPE_FUNC_EQUAL
:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1969 case PIPE_FUNC_LEQUAL
:
1970 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1971 case PIPE_FUNC_GREATER
:
1972 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1973 case PIPE_FUNC_NOTEQUAL
:
1974 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1975 case PIPE_FUNC_GEQUAL
:
1976 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1977 case PIPE_FUNC_ALWAYS
:
1978 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1982 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1983 unsigned view_target
, unsigned nr_samples
)
1985 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1987 if (view_target
== PIPE_TEXTURE_CUBE
||
1988 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1989 res_target
= view_target
;
1990 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1991 else if (res_target
== PIPE_TEXTURE_CUBE
||
1992 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1993 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1995 /* GFX9 allocates 1D textures as 2D. */
1996 if ((res_target
== PIPE_TEXTURE_1D
||
1997 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1998 sscreen
->info
.chip_class
== GFX9
&&
1999 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
2000 if (res_target
== PIPE_TEXTURE_1D
)
2001 res_target
= PIPE_TEXTURE_2D
;
2003 res_target
= PIPE_TEXTURE_2D_ARRAY
;
2006 switch (res_target
) {
2008 case PIPE_TEXTURE_1D
:
2009 return V_008F1C_SQ_RSRC_IMG_1D
;
2010 case PIPE_TEXTURE_1D_ARRAY
:
2011 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
2012 case PIPE_TEXTURE_2D
:
2013 case PIPE_TEXTURE_RECT
:
2014 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
2015 V_008F1C_SQ_RSRC_IMG_2D
;
2016 case PIPE_TEXTURE_2D_ARRAY
:
2017 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
2018 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2019 case PIPE_TEXTURE_3D
:
2020 return V_008F1C_SQ_RSRC_IMG_3D
;
2021 case PIPE_TEXTURE_CUBE
:
2022 case PIPE_TEXTURE_CUBE_ARRAY
:
2023 return V_008F1C_SQ_RSRC_IMG_CUBE
;
2028 * Format support testing
2031 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
2033 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2035 if (sscreen
->info
.chip_class
>= GFX10
) {
2036 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2037 if (!fmt
->img_format
|| fmt
->buffers_only
)
2042 const struct util_format_description
*desc
= util_format_description(format
);
2046 return si_translate_texformat(screen
, format
, desc
,
2047 util_format_get_first_non_void_channel(format
)) != ~0U;
2050 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
2051 const struct util_format_description
*desc
,
2056 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2058 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2059 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
2061 assert(first_non_void
>= 0);
2063 if (desc
->nr_channels
== 4 &&
2064 desc
->channel
[0].size
== 10 &&
2065 desc
->channel
[1].size
== 10 &&
2066 desc
->channel
[2].size
== 10 &&
2067 desc
->channel
[3].size
== 2)
2068 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
2070 /* See whether the components are of the same size. */
2071 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2072 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2073 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2076 switch (desc
->channel
[first_non_void
].size
) {
2078 switch (desc
->nr_channels
) {
2080 case 3: /* 3 loads */
2081 return V_008F0C_BUF_DATA_FORMAT_8
;
2083 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2085 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2089 switch (desc
->nr_channels
) {
2091 case 3: /* 3 loads */
2092 return V_008F0C_BUF_DATA_FORMAT_16
;
2094 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2096 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2100 switch (desc
->nr_channels
) {
2102 return V_008F0C_BUF_DATA_FORMAT_32
;
2104 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2106 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2108 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2112 /* Legacy double formats. */
2113 switch (desc
->nr_channels
) {
2114 case 1: /* 1 load */
2115 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2116 case 2: /* 1 load */
2117 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2118 case 3: /* 3 loads */
2119 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2120 case 4: /* 2 loads */
2121 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2126 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2129 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2130 const struct util_format_description
*desc
,
2133 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2135 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2136 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2138 assert(first_non_void
>= 0);
2140 switch (desc
->channel
[first_non_void
].type
) {
2141 case UTIL_FORMAT_TYPE_SIGNED
:
2142 case UTIL_FORMAT_TYPE_FIXED
:
2143 if (desc
->channel
[first_non_void
].size
>= 32 ||
2144 desc
->channel
[first_non_void
].pure_integer
)
2145 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2146 else if (desc
->channel
[first_non_void
].normalized
)
2147 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2149 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2151 case UTIL_FORMAT_TYPE_UNSIGNED
:
2152 if (desc
->channel
[first_non_void
].size
>= 32 ||
2153 desc
->channel
[first_non_void
].pure_integer
)
2154 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2155 else if (desc
->channel
[first_non_void
].normalized
)
2156 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2158 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2160 case UTIL_FORMAT_TYPE_FLOAT
:
2162 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2166 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2167 enum pipe_format format
,
2170 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2171 const struct util_format_description
*desc
;
2173 unsigned data_format
;
2175 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2176 PIPE_BIND_SAMPLER_VIEW
|
2177 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2179 desc
= util_format_description(format
);
2183 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2184 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2185 * for read-only access (with caveats surrounding bounds checks), but
2186 * obviously fails for write access which we have to implement for
2187 * shader images. Luckily, OpenGL doesn't expect this to be supported
2188 * anyway, and so the only impact is on PBO uploads / downloads, which
2189 * shouldn't be expected to be fast for GL_RGB anyway.
2191 if (desc
->block
.bits
== 3 * 8 ||
2192 desc
->block
.bits
== 3 * 16) {
2193 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2194 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2200 if (sscreen
->info
.chip_class
>= GFX10
) {
2201 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2202 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2207 first_non_void
= util_format_get_first_non_void_channel(format
);
2208 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2209 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2215 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2217 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2218 si_translate_colorswap(format
, false) != ~0U;
2221 static bool si_is_zs_format_supported(enum pipe_format format
)
2223 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2226 static bool si_is_format_supported(struct pipe_screen
*screen
,
2227 enum pipe_format format
,
2228 enum pipe_texture_target target
,
2229 unsigned sample_count
,
2230 unsigned storage_sample_count
,
2233 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2234 unsigned retval
= 0;
2236 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2237 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2241 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2244 if (sample_count
> 1) {
2245 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2248 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2251 /* Only power-of-two sample counts are supported. */
2252 if (!util_is_power_of_two_or_zero(sample_count
) ||
2253 !util_is_power_of_two_or_zero(storage_sample_count
))
2256 /* MSAA support without framebuffer attachments. */
2257 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2260 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2261 util_format_is_depth_or_stencil(format
)) {
2262 /* Color without EQAA or depth/stencil. */
2263 if (sample_count
> 8 ||
2264 sample_count
!= storage_sample_count
)
2267 /* Color with EQAA. */
2268 if (sample_count
> 16 ||
2269 storage_sample_count
> 8)
2274 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2275 PIPE_BIND_SHADER_IMAGE
)) {
2276 if (target
== PIPE_BUFFER
) {
2277 retval
|= si_is_vertex_format_supported(
2278 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2279 PIPE_BIND_SHADER_IMAGE
));
2281 if (si_is_sampler_format_supported(screen
, format
))
2282 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2283 PIPE_BIND_SHADER_IMAGE
);
2287 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2288 PIPE_BIND_DISPLAY_TARGET
|
2291 PIPE_BIND_BLENDABLE
)) &&
2292 si_is_colorbuffer_format_supported(format
)) {
2294 (PIPE_BIND_RENDER_TARGET
|
2295 PIPE_BIND_DISPLAY_TARGET
|
2298 if (!util_format_is_pure_integer(format
) &&
2299 !util_format_is_depth_or_stencil(format
))
2300 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2303 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2304 si_is_zs_format_supported(format
)) {
2305 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2308 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2309 retval
|= si_is_vertex_format_supported(screen
, format
,
2310 PIPE_BIND_VERTEX_BUFFER
);
2313 if ((usage
& PIPE_BIND_LINEAR
) &&
2314 !util_format_is_compressed(format
) &&
2315 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2316 retval
|= PIPE_BIND_LINEAR
;
2318 return retval
== usage
;
2322 * framebuffer handling
2325 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2326 unsigned format
, unsigned swap
,
2327 unsigned ntype
, bool is_depth
)
2329 /* Alpha is needed for alpha-to-coverage.
2330 * Blending may be with or without alpha.
2332 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2333 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2334 unsigned blend
= 0; /* supports blending, but may not export alpha */
2335 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2337 /* Choose the SPI color formats. These are required values for RB+.
2338 * Other chips have multiple choices, though they are not necessarily better.
2341 case V_028C70_COLOR_5_6_5
:
2342 case V_028C70_COLOR_1_5_5_5
:
2343 case V_028C70_COLOR_5_5_5_1
:
2344 case V_028C70_COLOR_4_4_4_4
:
2345 case V_028C70_COLOR_10_11_11
:
2346 case V_028C70_COLOR_11_11_10
:
2347 case V_028C70_COLOR_8
:
2348 case V_028C70_COLOR_8_8
:
2349 case V_028C70_COLOR_8_8_8_8
:
2350 case V_028C70_COLOR_10_10_10_2
:
2351 case V_028C70_COLOR_2_10_10_10
:
2352 if (ntype
== V_028C70_NUMBER_UINT
)
2353 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2354 else if (ntype
== V_028C70_NUMBER_SINT
)
2355 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2357 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2360 case V_028C70_COLOR_16
:
2361 case V_028C70_COLOR_16_16
:
2362 case V_028C70_COLOR_16_16_16_16
:
2363 if (ntype
== V_028C70_NUMBER_UNORM
||
2364 ntype
== V_028C70_NUMBER_SNORM
) {
2365 /* UNORM16 and SNORM16 don't support blending */
2366 if (ntype
== V_028C70_NUMBER_UNORM
)
2367 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2369 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2371 /* Use 32 bits per channel for blending. */
2372 if (format
== V_028C70_COLOR_16
) {
2373 if (swap
== V_028C70_SWAP_STD
) { /* R */
2374 blend
= V_028714_SPI_SHADER_32_R
;
2375 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2376 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2377 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2380 } else if (format
== V_028C70_COLOR_16_16
) {
2381 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2382 blend
= V_028714_SPI_SHADER_32_GR
;
2383 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2384 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2385 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2388 } else /* 16_16_16_16 */
2389 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2390 } else if (ntype
== V_028C70_NUMBER_UINT
)
2391 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2392 else if (ntype
== V_028C70_NUMBER_SINT
)
2393 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2394 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2395 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2400 case V_028C70_COLOR_32
:
2401 if (swap
== V_028C70_SWAP_STD
) { /* R */
2402 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2403 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2404 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2405 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2410 case V_028C70_COLOR_32_32
:
2411 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2412 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2413 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2414 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2415 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2420 case V_028C70_COLOR_32_32_32_32
:
2421 case V_028C70_COLOR_8_24
:
2422 case V_028C70_COLOR_24_8
:
2423 case V_028C70_COLOR_X24_8_32_FLOAT
:
2424 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2432 /* The DB->CB copy needs 32_ABGR. */
2434 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2436 surf
->spi_shader_col_format
= normal
;
2437 surf
->spi_shader_col_format_alpha
= alpha
;
2438 surf
->spi_shader_col_format_blend
= blend
;
2439 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2442 static void si_initialize_color_surface(struct si_context
*sctx
,
2443 struct si_surface
*surf
)
2445 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2446 unsigned color_info
, color_attrib
;
2447 unsigned format
, swap
, ntype
, endian
;
2448 const struct util_format_description
*desc
;
2450 unsigned blend_clamp
= 0, blend_bypass
= 0;
2452 desc
= util_format_description(surf
->base
.format
);
2453 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2454 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2458 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2459 ntype
= V_028C70_NUMBER_FLOAT
;
2461 ntype
= V_028C70_NUMBER_UNORM
;
2462 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2463 ntype
= V_028C70_NUMBER_SRGB
;
2464 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2465 if (desc
->channel
[firstchan
].pure_integer
) {
2466 ntype
= V_028C70_NUMBER_SINT
;
2468 assert(desc
->channel
[firstchan
].normalized
);
2469 ntype
= V_028C70_NUMBER_SNORM
;
2471 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2472 if (desc
->channel
[firstchan
].pure_integer
) {
2473 ntype
= V_028C70_NUMBER_UINT
;
2475 assert(desc
->channel
[firstchan
].normalized
);
2476 ntype
= V_028C70_NUMBER_UNORM
;
2481 format
= si_translate_colorformat(surf
->base
.format
);
2482 if (format
== V_028C70_COLOR_INVALID
) {
2483 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2485 assert(format
!= V_028C70_COLOR_INVALID
);
2486 swap
= si_translate_colorswap(surf
->base
.format
, false);
2487 endian
= si_colorformat_endian_swap(format
);
2489 /* blend clamp should be set for all NORM/SRGB types */
2490 if (ntype
== V_028C70_NUMBER_UNORM
||
2491 ntype
== V_028C70_NUMBER_SNORM
||
2492 ntype
== V_028C70_NUMBER_SRGB
)
2495 /* set blend bypass according to docs if SINT/UINT or
2496 8/24 COLOR variants */
2497 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2498 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2499 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2504 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2505 if (format
== V_028C70_COLOR_8
||
2506 format
== V_028C70_COLOR_8_8
||
2507 format
== V_028C70_COLOR_8_8_8_8
)
2508 surf
->color_is_int8
= true;
2509 else if (format
== V_028C70_COLOR_10_10_10_2
||
2510 format
== V_028C70_COLOR_2_10_10_10
)
2511 surf
->color_is_int10
= true;
2514 color_info
= S_028C70_FORMAT(format
) |
2515 S_028C70_COMP_SWAP(swap
) |
2516 S_028C70_BLEND_CLAMP(blend_clamp
) |
2517 S_028C70_BLEND_BYPASS(blend_bypass
) |
2518 S_028C70_SIMPLE_FLOAT(1) |
2519 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2520 ntype
!= V_028C70_NUMBER_SNORM
&&
2521 ntype
!= V_028C70_NUMBER_SRGB
&&
2522 format
!= V_028C70_COLOR_8_24
&&
2523 format
!= V_028C70_COLOR_24_8
) |
2524 S_028C70_NUMBER_TYPE(ntype
) |
2525 S_028C70_ENDIAN(endian
);
2527 /* Intensity is implemented as Red, so treat it that way. */
2528 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2529 util_format_is_intensity(surf
->base
.format
));
2531 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2532 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2533 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2535 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2536 S_028C74_NUM_FRAGMENTS(log_fragments
);
2538 if (tex
->surface
.fmask_offset
) {
2539 color_info
|= S_028C70_COMPRESSION(1);
2540 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2542 if (sctx
->chip_class
== GFX6
) {
2543 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2544 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2549 if (sctx
->chip_class
>= GFX10
) {
2550 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2552 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2553 64 for APU because all of our APUs to date use DIMMs which have
2554 a request granularity size of 64B while all other chips have a
2556 if (!sctx
->screen
->info
.has_dedicated_vram
)
2557 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2559 surf
->cb_dcc_control
=
2560 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2561 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2562 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2563 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2564 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2565 } else if (sctx
->chip_class
>= GFX8
) {
2566 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2567 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2569 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2570 64 for APU because all of our APUs to date use DIMMs which have
2571 a request granularity size of 64B while all other chips have a
2573 if (!sctx
->screen
->info
.has_dedicated_vram
)
2574 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2576 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2577 if (tex
->surface
.bpe
== 1)
2578 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2579 else if (tex
->surface
.bpe
== 2)
2580 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2583 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2584 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2585 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2588 /* This must be set for fast clear to work without FMASK. */
2589 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2590 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2591 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2594 /* GFX10 field has the same base shift as the GFX6 field */
2595 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2596 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2597 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2599 if (sctx
->chip_class
>= GFX10
) {
2600 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2602 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2603 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2604 S_028EE0_RESOURCE_LEVEL(1);
2605 } else if (sctx
->chip_class
== GFX9
) {
2606 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2607 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2608 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2611 if (sctx
->chip_class
>= GFX9
) {
2612 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2613 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2614 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2617 surf
->cb_color_view
= color_view
;
2618 surf
->cb_color_info
= color_info
;
2619 surf
->cb_color_attrib
= color_attrib
;
2621 /* Determine pixel shader export format */
2622 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2624 surf
->color_initialized
= true;
2627 static void si_init_depth_surface(struct si_context
*sctx
,
2628 struct si_surface
*surf
)
2630 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2631 unsigned level
= surf
->base
.u
.tex
.level
;
2632 unsigned format
, stencil_format
;
2633 uint32_t z_info
, s_info
;
2635 format
= si_translate_dbformat(tex
->db_render_format
);
2636 stencil_format
= tex
->surface
.has_stencil
?
2637 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2639 assert(format
!= V_028040_Z_INVALID
);
2640 if (format
== V_028040_Z_INVALID
)
2641 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2643 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2644 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2645 surf
->db_htile_data_base
= 0;
2646 surf
->db_htile_surface
= 0;
2648 if (sctx
->chip_class
>= GFX10
) {
2649 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2650 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2653 if (sctx
->chip_class
>= GFX9
) {
2654 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2655 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2656 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2657 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2658 z_info
= S_028038_FORMAT(format
) |
2659 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2660 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2661 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2662 s_info
= S_02803C_FORMAT(stencil_format
) |
2663 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2665 if (sctx
->chip_class
== GFX9
) {
2666 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2667 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2669 surf
->db_depth_view
|= S_028008_MIPID(level
);
2670 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2671 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2673 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2674 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2675 S_028038_ALLOW_EXPCLEAR(1);
2677 if (tex
->tc_compatible_htile
) {
2678 unsigned max_zplanes
= 4;
2680 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2681 tex
->buffer
.b
.b
.nr_samples
> 1)
2684 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2686 if (sctx
->chip_class
>= GFX10
) {
2687 z_info
|= S_028040_ITERATE_FLUSH(1);
2688 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2690 z_info
|= S_028038_ITERATE_FLUSH(1);
2691 s_info
|= S_02803C_ITERATE_FLUSH(1);
2695 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2696 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2697 * See that for explanation.
2699 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2701 /* Use all HTILE for depth if there's no stencil. */
2702 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2705 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2706 tex
->surface
.htile_offset
) >> 8;
2707 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2708 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2709 if (sctx
->chip_class
== GFX9
) {
2710 surf
->db_htile_surface
|=
2711 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2716 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2718 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2720 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2721 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2722 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2723 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2725 z_info
= S_028040_FORMAT(format
) |
2726 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2727 s_info
= S_028044_FORMAT(stencil_format
);
2728 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2730 if (sctx
->chip_class
>= GFX7
) {
2731 struct radeon_info
*info
= &sctx
->screen
->info
;
2732 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2733 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2734 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2735 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2736 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2737 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2739 surf
->db_depth_info
|=
2740 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2741 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2742 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2743 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2744 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2745 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2746 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2747 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2749 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2750 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2751 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2752 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2755 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2756 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2757 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2758 levelinfo
->nblk_y
) / 64 - 1);
2760 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2761 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2762 S_028040_ALLOW_EXPCLEAR(1);
2764 if (tex
->surface
.has_stencil
) {
2765 /* Workaround: For a not yet understood reason, the
2766 * combination of MSAA, fast stencil clear and stencil
2767 * decompress messes with subsequent stencil buffer
2768 * uses. Problem was reproduced on Verde, Bonaire,
2769 * Tonga, and Carrizo.
2771 * Disabling EXPCLEAR works around the problem.
2773 * Check piglit's arb_texture_multisample-stencil-clear
2774 * test if you want to try changing this.
2776 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2777 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2778 } else if (!tex
->tc_compatible_htile
) {
2779 /* Use all of the htile_buffer for depth if there's no stencil.
2780 * This must not be set when TC-compatible HTILE is enabled
2783 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2786 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2787 tex
->surface
.htile_offset
) >> 8;
2788 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2790 if (tex
->tc_compatible_htile
) {
2791 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2793 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2794 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2795 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2796 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2797 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2799 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2804 surf
->db_z_info
= z_info
;
2805 surf
->db_stencil_info
= s_info
;
2807 surf
->depth_initialized
= true;
2810 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2812 if (sctx
->decompression_enabled
)
2815 if (sctx
->framebuffer
.state
.zsbuf
) {
2816 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2817 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2819 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2821 if (tex
->surface
.has_stencil
)
2822 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2825 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2826 while (compressed_cb_mask
) {
2827 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2828 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2829 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2831 if (tex
->surface
.fmask_offset
)
2832 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2833 if (tex
->dcc_gather_statistics
)
2834 tex
->separate_dcc_dirty
= true;
2838 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2840 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2841 struct si_surface
*surf
= NULL
;
2842 struct si_texture
*tex
;
2844 if (!state
->cbufs
[i
])
2846 surf
= (struct si_surface
*)state
->cbufs
[i
];
2847 tex
= (struct si_texture
*)surf
->base
.texture
;
2849 p_atomic_dec(&tex
->framebuffers_bound
);
2853 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2854 const struct pipe_framebuffer_state
*state
)
2856 struct si_context
*sctx
= (struct si_context
*)ctx
;
2857 struct si_surface
*surf
= NULL
;
2858 struct si_texture
*tex
;
2859 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2860 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2861 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2862 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2863 bool old_has_stencil
=
2865 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2866 bool unbound
= false;
2869 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2870 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2871 * We could implement the full workaround here, but it's a useless case.
2873 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2874 unreachable("the framebuffer shouldn't have zero area");
2878 si_update_fb_dirtiness_after_rendering(sctx
);
2880 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2881 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2884 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2885 if (tex
->dcc_gather_statistics
)
2886 vi_separate_dcc_stop_query(sctx
, tex
);
2889 /* Disable DCC if the formats are incompatible. */
2890 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2891 if (!state
->cbufs
[i
])
2894 surf
= (struct si_surface
*)state
->cbufs
[i
];
2895 tex
= (struct si_texture
*)surf
->base
.texture
;
2897 if (!surf
->dcc_incompatible
)
2900 /* Since the DCC decompression calls back into set_framebuffer-
2901 * _state, we need to unbind the framebuffer, so that
2902 * vi_separate_dcc_stop_query isn't called twice with the same
2906 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2910 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2911 if (!si_texture_disable_dcc(sctx
, tex
))
2912 si_decompress_dcc(sctx
, tex
);
2914 surf
->dcc_incompatible
= false;
2917 /* Only flush TC when changing the framebuffer state, because
2918 * the only client not using TC that can change textures is
2921 * Wait for compute shaders because of possible transitions:
2922 * - FB write -> shader read
2923 * - shader write -> FB read
2925 * DB caches are flushed on demand (using si_decompress_textures).
2927 * When MSAA is enabled, CB and TC caches are flushed on demand
2928 * (after FMASK decompression). Shader write -> FB read transitions
2929 * cannot happen for MSAA textures, because MSAA shader images are
2932 * Only flush and wait for CB if there is actually a bound color buffer.
2934 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2935 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2936 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2937 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2940 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2942 /* u_blitter doesn't invoke depth decompression when it does multiple
2943 * blits in a row, but the only case when it matters for DB is when
2944 * doing generate_mipmap. So here we flush DB manually between
2945 * individual generate_mipmap blits.
2946 * Note that lower mipmap levels aren't compressed.
2948 if (sctx
->generate_mipmap_for_depth
) {
2949 si_make_DB_shader_coherent(sctx
, 1, false,
2950 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2951 } else if (sctx
->chip_class
== GFX9
) {
2952 /* It appears that DB metadata "leaks" in a sequence of:
2954 * - DCC decompress for shader image writes (with DB disabled)
2955 * - render with DEPTH_BEFORE_SHADER=1
2956 * Flushing DB metadata works around the problem.
2958 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2961 /* Take the maximum of the old and new count. If the new count is lower,
2962 * dirtying is needed to disable the unbound colorbuffers.
2964 sctx
->framebuffer
.dirty_cbufs
|=
2965 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2966 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2968 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2969 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2971 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2972 sctx
->framebuffer
.spi_shader_col_format
= 0;
2973 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2974 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2975 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2976 sctx
->framebuffer
.color_is_int8
= 0;
2977 sctx
->framebuffer
.color_is_int10
= 0;
2979 sctx
->framebuffer
.compressed_cb_mask
= 0;
2980 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2981 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2982 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2983 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2984 sctx
->framebuffer
.any_dst_linear
= false;
2985 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2986 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2987 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2988 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2990 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2991 if (!state
->cbufs
[i
])
2994 surf
= (struct si_surface
*)state
->cbufs
[i
];
2995 tex
= (struct si_texture
*)surf
->base
.texture
;
2997 if (!surf
->color_initialized
) {
2998 si_initialize_color_surface(sctx
, surf
);
3001 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
3002 sctx
->framebuffer
.spi_shader_col_format
|=
3003 surf
->spi_shader_col_format
<< (i
* 4);
3004 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
3005 surf
->spi_shader_col_format_alpha
<< (i
* 4);
3006 sctx
->framebuffer
.spi_shader_col_format_blend
|=
3007 surf
->spi_shader_col_format_blend
<< (i
* 4);
3008 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
3009 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
3011 if (surf
->color_is_int8
)
3012 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
3013 if (surf
->color_is_int10
)
3014 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
3016 if (tex
->surface
.fmask_offset
)
3017 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3019 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
3021 /* Don't update nr_color_samples for non-AA buffers.
3022 * (e.g. destination of MSAA resolve)
3024 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
3025 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
3026 sctx
->framebuffer
.nr_color_samples
=
3027 MIN2(sctx
->framebuffer
.nr_color_samples
,
3028 tex
->buffer
.b
.b
.nr_storage_samples
);
3029 sctx
->framebuffer
.nr_color_samples
=
3030 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
3033 if (tex
->surface
.is_linear
)
3034 sctx
->framebuffer
.any_dst_linear
= true;
3036 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
3037 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
3039 if (sctx
->chip_class
>= GFX9
&&
3040 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
3041 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
3044 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3046 p_atomic_inc(&tex
->framebuffers_bound
);
3048 if (tex
->dcc_gather_statistics
) {
3049 /* Dirty tracking must be enabled for DCC usage analysis. */
3050 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3051 vi_separate_dcc_start_query(sctx
, tex
);
3054 /* Update the minimum but don't keep 0. */
3055 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3056 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3057 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
3060 /* For optimal DCC performance. */
3061 if (sctx
->chip_class
>= GFX10
)
3062 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
3064 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
3066 struct si_texture
*zstex
= NULL
;
3069 surf
= (struct si_surface
*)state
->zsbuf
;
3070 zstex
= (struct si_texture
*)surf
->base
.texture
;
3072 if (!surf
->depth_initialized
) {
3073 si_init_depth_surface(sctx
, surf
);
3076 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
,
3078 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
3080 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3082 /* Update the minimum but don't keep 0. */
3083 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3084 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3085 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
3088 si_update_ps_colorbuf0_slot(sctx
);
3089 si_update_poly_offset_state(sctx
);
3090 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3091 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
3093 if (sctx
->screen
->dpbb_allowed
)
3094 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3096 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
3097 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3099 if (sctx
->screen
->has_out_of_order_rast
&&
3100 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
3101 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
3102 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
3103 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3105 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
3106 struct pipe_constant_buffer constbuf
= {0};
3108 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3109 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3111 constbuf
.buffer
= sctx
->sample_pos_buffer
;
3113 /* Set sample locations as fragment shader constants. */
3114 switch (sctx
->framebuffer
.nr_samples
) {
3116 constbuf
.buffer_offset
= 0;
3119 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
3120 (ubyte
*)sctx
->sample_positions
.x1
;
3123 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
3124 (ubyte
*)sctx
->sample_positions
.x1
;
3127 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
3128 (ubyte
*)sctx
->sample_positions
.x1
;
3131 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3132 (ubyte
*)sctx
->sample_positions
.x1
;
3135 PRINT_ERR("Requested an invalid number of samples %i.\n",
3136 sctx
->framebuffer
.nr_samples
);
3139 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3140 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3142 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3145 sctx
->do_update_shaders
= true;
3147 if (!sctx
->decompression_enabled
) {
3148 /* Prevent textures decompression when the framebuffer state
3149 * changes come from the decompression passes themselves.
3151 sctx
->need_check_render_feedback
= true;
3155 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3157 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3158 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3159 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3160 struct si_texture
*tex
= NULL
;
3161 struct si_surface
*cb
= NULL
;
3162 unsigned cb_color_info
= 0;
3165 for (i
= 0; i
< nr_cbufs
; i
++) {
3166 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3167 unsigned cb_color_attrib
;
3169 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3172 cb
= (struct si_surface
*)state
->cbufs
[i
];
3174 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3175 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3179 tex
= (struct si_texture
*)cb
->base
.texture
;
3180 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3181 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3182 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3183 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3184 RADEON_PRIO_COLOR_BUFFER
);
3186 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3187 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3188 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3189 RADEON_PRIO_SEPARATE_META
);
3192 if (tex
->dcc_separate_buffer
)
3193 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3194 tex
->dcc_separate_buffer
,
3195 RADEON_USAGE_READWRITE
,
3196 RADEON_PRIO_SEPARATE_META
);
3198 /* Compute mutable surface parameters. */
3199 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3201 cb_color_cmask
= tex
->cmask_base_address_reg
;
3203 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3204 cb_color_attrib
= cb
->cb_color_attrib
;
3206 if (cb
->base
.u
.tex
.level
> 0)
3207 cb_color_info
&= C_028C70_FAST_CLEAR
;
3209 if (tex
->surface
.fmask_offset
) {
3210 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
) >> 8;
3211 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3215 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3216 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3217 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3218 state
->cbufs
[1] == &cb
->base
&&
3219 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3221 if (!is_msaa_resolve_dst
)
3222 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3224 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3225 tex
->surface
.dcc_offset
) >> 8;
3227 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3228 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3229 cb_dcc_base
|= dcc_tile_swizzle
;
3232 if (sctx
->chip_class
>= GFX10
) {
3233 unsigned cb_color_attrib3
;
3235 /* Set mutable surface parameters. */
3236 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3237 cb_color_base
|= tex
->surface
.tile_swizzle
;
3238 if (!tex
->surface
.fmask_offset
)
3239 cb_color_fmask
= cb_color_base
;
3240 if (cb
->base
.u
.tex
.level
> 0)
3241 cb_color_cmask
= cb_color_base
;
3243 cb_color_attrib3
= cb
->cb_color_attrib3
|
3244 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3245 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3246 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3247 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3249 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3250 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3251 radeon_emit(cs
, 0); /* hole */
3252 radeon_emit(cs
, 0); /* hole */
3253 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3254 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3255 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3256 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3257 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3258 radeon_emit(cs
, 0); /* hole */
3259 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3260 radeon_emit(cs
, 0); /* hole */
3261 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3262 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3263 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3265 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4,
3266 cb_color_base
>> 32);
3267 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3268 cb_color_cmask
>> 32);
3269 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3270 cb_color_fmask
>> 32);
3271 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4,
3273 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4,
3274 cb
->cb_color_attrib2
);
3275 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4,
3277 } else if (sctx
->chip_class
== GFX9
) {
3278 struct gfx9_surf_meta_flags meta
;
3280 if (tex
->surface
.dcc_offset
)
3281 meta
= tex
->surface
.u
.gfx9
.dcc
;
3283 meta
= tex
->surface
.u
.gfx9
.cmask
;
3285 /* Set mutable surface parameters. */
3286 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3287 cb_color_base
|= tex
->surface
.tile_swizzle
;
3288 if (!tex
->surface
.fmask_offset
)
3289 cb_color_fmask
= cb_color_base
;
3290 if (cb
->base
.u
.tex
.level
> 0)
3291 cb_color_cmask
= cb_color_base
;
3292 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3293 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3294 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3295 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3297 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3298 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3299 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3300 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3301 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3302 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3303 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3304 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3305 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3306 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3307 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3308 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3309 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3310 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3311 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3312 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3314 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3315 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3317 /* Compute mutable surface parameters (GFX6-GFX8). */
3318 const struct legacy_surf_level
*level_info
=
3319 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3320 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3321 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3323 cb_color_base
+= level_info
->offset
>> 8;
3324 /* Only macrotiled modes can set tile swizzle. */
3325 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3326 cb_color_base
|= tex
->surface
.tile_swizzle
;
3328 if (!tex
->surface
.fmask_offset
)
3329 cb_color_fmask
= cb_color_base
;
3330 if (cb
->base
.u
.tex
.level
> 0)
3331 cb_color_cmask
= cb_color_base
;
3333 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3335 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3336 slice_tile_max
= level_info
->nblk_x
*
3337 level_info
->nblk_y
/ 64 - 1;
3338 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3340 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3341 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3342 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3344 if (tex
->surface
.fmask_offset
) {
3345 if (sctx
->chip_class
>= GFX7
)
3346 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3347 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3348 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3350 /* This must be set for fast clear to work without FMASK. */
3351 if (sctx
->chip_class
>= GFX7
)
3352 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3353 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3354 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3357 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3358 sctx
->chip_class
>= GFX8
? 14 : 13);
3359 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3360 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3361 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3362 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3363 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3364 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3365 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3366 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3367 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3368 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3369 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3370 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3371 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3373 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3374 radeon_emit(cs
, cb_dcc_base
);
3378 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3379 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3382 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3383 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3384 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3386 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3387 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3388 zb
->base
.texture
->nr_samples
> 1 ?
3389 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3390 RADEON_PRIO_DEPTH_BUFFER
);
3392 if (sctx
->chip_class
>= GFX10
) {
3393 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3394 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3396 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3397 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3398 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3399 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3400 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3401 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3402 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3403 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3404 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3406 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3407 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3408 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3409 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3410 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3411 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3412 } else if (sctx
->chip_class
== GFX9
) {
3413 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3414 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3415 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3416 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3418 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3419 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3420 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3421 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3422 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3423 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3424 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3425 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3426 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3427 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3428 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3429 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3431 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3432 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3433 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3435 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3437 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3438 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3439 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3440 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3441 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3442 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3443 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3444 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3445 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3446 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3447 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3450 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3451 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3452 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3454 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3455 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3456 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3457 if (sctx
->chip_class
== GFX9
)
3458 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3460 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3462 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3463 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3466 /* Framebuffer dimensions. */
3467 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3468 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3469 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3471 if (sctx
->screen
->dfsm_allowed
) {
3472 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3473 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3476 sctx
->framebuffer
.dirty_cbufs
= 0;
3477 sctx
->framebuffer
.dirty_zsbuf
= false;
3480 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3482 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3483 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3484 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3485 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3487 /* Smoothing (only possible with nr_samples == 1) uses the same
3488 * sample locations as the MSAA it simulates.
3490 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3491 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3493 /* On Polaris, the small primitive filter uses the sample locations
3494 * even when MSAA is off, so we need to make sure they're set to 0.
3496 * GFX10 uses sample locations unconditionally, so they always need
3499 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
||
3500 sctx
->chip_class
>= GFX10
) &&
3501 nr_samples
!= sctx
->sample_locs_num_samples
) {
3502 sctx
->sample_locs_num_samples
= nr_samples
;
3503 si_emit_sample_locations(cs
, nr_samples
);
3506 if (sctx
->family
>= CHIP_POLARIS10
) {
3507 unsigned small_prim_filter_cntl
=
3508 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3510 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3512 /* The alternative of setting sample locations to 0 would
3513 * require a DB flush to avoid Z errors, see
3514 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3516 if (has_msaa_sample_loc_bug
&&
3517 sctx
->framebuffer
.nr_samples
> 1 &&
3518 !rs
->multisample_enable
)
3519 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3521 radeon_opt_set_context_reg(sctx
,
3522 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3523 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3524 small_prim_filter_cntl
);
3527 /* The exclusion bits can be set to improve rasterization efficiency
3528 * if no sample lies on the pixel boundary (-8 sample offset).
3530 bool exclusion
= sctx
->chip_class
>= GFX7
&&
3531 (!rs
->multisample_enable
|| nr_samples
!= 16);
3532 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3533 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3534 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3535 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3538 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3540 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3541 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3543 if (!sctx
->screen
->has_out_of_order_rast
)
3546 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3548 colormask
&= blend
->cb_target_enabled_4bit
;
3550 /* Conservative: No logic op. */
3551 if (colormask
&& blend
->logicop_enable
)
3554 struct si_dsa_order_invariance dsa_order_invariant
= {
3555 .zs
= true, .pass_set
= true, .pass_last
= false
3558 if (sctx
->framebuffer
.state
.zsbuf
) {
3559 struct si_texture
*zstex
=
3560 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3561 bool has_stencil
= zstex
->surface
.has_stencil
;
3562 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3563 if (!dsa_order_invariant
.zs
)
3566 /* The set of PS invocations is always order invariant,
3567 * except when early Z/S tests are requested. */
3568 if (sctx
->ps_shader
.cso
&&
3569 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3570 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3571 !dsa_order_invariant
.pass_set
)
3574 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3575 !dsa_order_invariant
.pass_set
)
3582 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3585 /* Only commutative blending. */
3586 if (blendmask
& ~blend
->commutative_4bit
)
3589 if (!dsa_order_invariant
.pass_set
)
3593 if (colormask
& ~blendmask
) {
3594 if (!dsa_order_invariant
.pass_last
)
3601 static void si_emit_msaa_config(struct si_context
*sctx
)
3603 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3604 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3605 /* 33% faster rendering to linear color buffers */
3606 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3607 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3608 unsigned sc_mode_cntl_1
=
3609 S_028A4C_WALK_SIZE(dst_is_linear
) |
3610 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3611 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3612 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3613 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3615 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3616 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3617 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3618 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3619 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3620 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3621 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3622 S_028804_INCOHERENT_EQAA_READS(1) |
3623 S_028804_INTERPOLATE_COMP_Z(1) |
3624 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3625 unsigned coverage_samples
, color_samples
, z_samples
;
3626 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3628 /* S: Coverage samples (up to 16x):
3629 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3630 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3632 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3633 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3634 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3635 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3636 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3639 * F: Color samples (up to 8x, must be <= coverage samples):
3640 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3641 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3643 * Can be anything between coverage and color samples:
3644 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3645 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3646 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3647 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3648 * # All are currently set the same as coverage samples.
3650 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3651 * flag for undefined color samples. A shader-based resolve must handle unknowns
3652 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3653 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3654 * useful. The CB resolve always drops unknowns.
3656 * Sensible AA configurations:
3657 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3658 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3659 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3660 * EQAA 8s 8z 8f = 8x MSAA
3661 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3662 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3663 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3664 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3665 * EQAA 4s 4z 4f = 4x MSAA
3666 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3667 * EQAA 2s 2z 2f = 2x MSAA
3669 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3670 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3671 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3673 if (sctx
->framebuffer
.state
.zsbuf
) {
3674 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3675 z_samples
= MAX2(1, z_samples
);
3677 z_samples
= coverage_samples
;
3679 } else if (sctx
->smoothing_enabled
) {
3680 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3682 coverage_samples
= color_samples
= z_samples
= 1;
3685 /* Required by OpenGL line rasterization.
3687 * TODO: We should also enable perpendicular endcaps for AA lines,
3688 * but that requires implementing line stippling in the pixel
3689 * shader. SC can only do line stippling with axis-aligned
3692 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3693 unsigned sc_aa_config
= 0;
3695 if (coverage_samples
> 1) {
3696 /* distance from the pixel center, indexed by log2(nr_samples) */
3697 static unsigned max_dist
[] = {
3704 unsigned log_samples
= util_logbase2(coverage_samples
);
3705 unsigned log_z_samples
= util_logbase2(z_samples
);
3706 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3707 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3709 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3710 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3711 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3712 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3714 if (sctx
->framebuffer
.nr_samples
> 1) {
3715 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3716 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3717 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3718 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3719 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3720 } else if (sctx
->smoothing_enabled
) {
3721 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3725 unsigned initial_cdw
= cs
->current
.cdw
;
3727 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3728 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3729 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3731 /* R_028804_DB_EQAA */
3732 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3734 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3735 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3736 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3738 if (initial_cdw
!= cs
->current
.cdw
) {
3739 sctx
->context_roll
= true;
3741 /* GFX9: Flush DFSM when the AA mode changes. */
3742 if (sctx
->screen
->dfsm_allowed
) {
3743 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3744 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3749 void si_update_ps_iter_samples(struct si_context
*sctx
)
3751 if (sctx
->framebuffer
.nr_samples
> 1)
3752 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3753 if (sctx
->screen
->dpbb_allowed
)
3754 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3757 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3759 struct si_context
*sctx
= (struct si_context
*)ctx
;
3761 /* The hardware can only do sample shading with 2^n samples. */
3762 min_samples
= util_next_power_of_two(min_samples
);
3764 if (sctx
->ps_iter_samples
== min_samples
)
3767 sctx
->ps_iter_samples
= min_samples
;
3768 sctx
->do_update_shaders
= true;
3770 si_update_ps_iter_samples(sctx
);
3778 * Build the sampler view descriptor for a buffer texture.
3779 * @param state 256-bit descriptor; only the high 128 bits are filled in
3782 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3783 enum pipe_format format
,
3784 unsigned offset
, unsigned size
,
3787 const struct util_format_description
*desc
;
3789 unsigned num_records
;
3791 desc
= util_format_description(format
);
3792 stride
= desc
->block
.bits
/ 8;
3794 num_records
= size
/ stride
;
3795 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3797 /* The NUM_RECORDS field has a different meaning depending on the chip,
3798 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3801 * - If STRIDE == 0, it's in byte units.
3802 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3805 * - For SMEM and STRIDE == 0, it's in byte units.
3806 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3807 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3808 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3809 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3810 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3811 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3812 * That way the same descriptor can be used by both SMEM and VMEM.
3815 * - For SMEM and STRIDE == 0, it's in byte units.
3816 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3817 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3818 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3820 if (screen
->info
.chip_class
== GFX8
)
3821 num_records
*= stride
;
3824 state
[5] = S_008F04_STRIDE(stride
);
3825 state
[6] = num_records
;
3826 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3827 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3828 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3829 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3831 if (screen
->info
.chip_class
>= GFX10
) {
3832 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3834 /* OOB_SELECT chooses the out-of-bounds check:
3835 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3836 * - 1: index >= NUM_RECORDS
3837 * - 2: NUM_RECORDS == 0
3838 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3839 * else: swizzle_address >= NUM_RECORDS
3841 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3842 S_008F0C_OOB_SELECT(0) |
3843 S_008F0C_RESOURCE_LEVEL(1);
3846 unsigned num_format
, data_format
;
3848 first_non_void
= util_format_get_first_non_void_channel(format
);
3849 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3850 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3852 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) |
3853 S_008F0C_DATA_FORMAT(data_format
);
3857 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3859 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3861 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3862 /* For the pre-defined border color values (white, opaque
3863 * black, transparent black), the only thing that matters is
3864 * that the alpha channel winds up in the correct place
3865 * (because the RGB channels are all the same) so either of
3866 * these enumerations will work.
3868 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3869 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3871 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3872 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3873 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3874 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3876 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3877 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3878 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3879 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3880 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3887 * Build the sampler view descriptor for a texture.
3890 gfx10_make_texture_descriptor(struct si_screen
*screen
,
3891 struct si_texture
*tex
,
3893 enum pipe_texture_target target
,
3894 enum pipe_format pipe_format
,
3895 const unsigned char state_swizzle
[4],
3896 unsigned first_level
, unsigned last_level
,
3897 unsigned first_layer
, unsigned last_layer
,
3898 unsigned width
, unsigned height
, unsigned depth
,
3900 uint32_t *fmask_state
)
3902 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3903 const struct util_format_description
*desc
;
3904 unsigned img_format
;
3905 unsigned char swizzle
[4];
3909 desc
= util_format_description(pipe_format
);
3910 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3912 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3913 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3914 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3915 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3916 bool is_stencil
= false;
3918 switch (pipe_format
) {
3919 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3920 case PIPE_FORMAT_X32_S8X24_UINT
:
3921 case PIPE_FORMAT_X8Z24_UNORM
:
3922 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3925 case PIPE_FORMAT_X24S8_UINT
:
3927 * X24S8 is implemented as an 8_8_8_8 data format, to
3928 * fix texture gathers. This affects at least
3929 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3931 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3935 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3936 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3939 if (tex
->upgraded_depth
&& !is_stencil
) {
3940 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3941 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3944 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3948 (res
->target
== PIPE_TEXTURE_CUBE
||
3949 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3950 /* For the purpose of shader images, treat cube maps as 2D
3953 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3955 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3958 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3960 depth
= res
->array_size
;
3961 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3962 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3963 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3964 depth
= res
->array_size
;
3965 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3966 depth
= res
->array_size
/ 6;
3969 state
[1] = S_00A004_FORMAT(img_format
) |
3970 S_00A004_WIDTH_LO(width
- 1);
3971 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
3972 S_00A008_HEIGHT(height
- 1) |
3973 S_00A008_RESOURCE_LEVEL(1);
3974 state
[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3975 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3976 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3977 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3978 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ?
3980 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ?
3981 util_logbase2(res
->nr_samples
) :
3983 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) |
3984 S_00A00C_TYPE(type
);
3985 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3986 * to know the total number of layers.
3988 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
)
3989 ? depth
- 1 : last_layer
) |
3990 S_00A010_BASE_ARRAY(first_layer
);
3991 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3992 S_00A014_MAX_MIP(res
->nr_samples
> 1 ?
3993 util_logbase2(res
->nr_samples
) :
3994 tex
->buffer
.b
.b
.last_level
) |
3995 S_00A014_PERF_MOD(4);
3999 if (tex
->surface
.dcc_offset
) {
4000 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
4001 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
4002 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4005 /* Initialize the sampler view for FMASK. */
4006 if (tex
->surface
.fmask_offset
) {
4009 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4011 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4012 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4014 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
4017 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
4020 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
4023 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
4026 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
4029 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
4032 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
4035 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
4038 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
4041 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
4044 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
4047 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
4050 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
4053 unreachable("invalid nr_samples");
4056 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4057 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
4058 S_00A004_FORMAT(format
) |
4059 S_00A004_WIDTH_LO(width
- 1);
4060 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
4061 S_00A008_HEIGHT(height
- 1) |
4062 S_00A008_RESOURCE_LEVEL(1);
4063 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4064 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4065 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4066 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4067 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4068 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4069 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
4070 S_00A010_BASE_ARRAY(first_layer
);
4072 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
4078 * Build the sampler view descriptor for a texture (SI-GFX9).
4081 si_make_texture_descriptor(struct si_screen
*screen
,
4082 struct si_texture
*tex
,
4084 enum pipe_texture_target target
,
4085 enum pipe_format pipe_format
,
4086 const unsigned char state_swizzle
[4],
4087 unsigned first_level
, unsigned last_level
,
4088 unsigned first_layer
, unsigned last_layer
,
4089 unsigned width
, unsigned height
, unsigned depth
,
4091 uint32_t *fmask_state
)
4093 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
4094 const struct util_format_description
*desc
;
4095 unsigned char swizzle
[4];
4097 unsigned num_format
, data_format
, type
, num_samples
;
4100 desc
= util_format_description(pipe_format
);
4102 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
4103 MAX2(1, res
->nr_samples
) :
4104 MAX2(1, res
->nr_storage_samples
);
4106 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
4107 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
4108 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
4109 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
4111 switch (pipe_format
) {
4112 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4113 case PIPE_FORMAT_X32_S8X24_UINT
:
4114 case PIPE_FORMAT_X8Z24_UNORM
:
4115 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4117 case PIPE_FORMAT_X24S8_UINT
:
4119 * X24S8 is implemented as an 8_8_8_8 data format, to
4120 * fix texture gathers. This affects at least
4121 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4123 if (screen
->info
.chip_class
<= GFX8
)
4124 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
4126 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4129 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
4132 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
4135 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
4137 switch (pipe_format
) {
4138 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4139 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4142 if (first_non_void
< 0) {
4143 if (util_format_is_compressed(pipe_format
)) {
4144 switch (pipe_format
) {
4145 case PIPE_FORMAT_DXT1_SRGB
:
4146 case PIPE_FORMAT_DXT1_SRGBA
:
4147 case PIPE_FORMAT_DXT3_SRGBA
:
4148 case PIPE_FORMAT_DXT5_SRGBA
:
4149 case PIPE_FORMAT_BPTC_SRGBA
:
4150 case PIPE_FORMAT_ETC2_SRGB8
:
4151 case PIPE_FORMAT_ETC2_SRGB8A1
:
4152 case PIPE_FORMAT_ETC2_SRGBA8
:
4153 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4155 case PIPE_FORMAT_RGTC1_SNORM
:
4156 case PIPE_FORMAT_LATC1_SNORM
:
4157 case PIPE_FORMAT_RGTC2_SNORM
:
4158 case PIPE_FORMAT_LATC2_SNORM
:
4159 case PIPE_FORMAT_ETC2_R11_SNORM
:
4160 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4161 /* implies float, so use SNORM/UNORM to determine
4162 whether data is signed or not */
4163 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4164 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4167 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4170 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4171 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4173 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4175 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4176 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4178 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4180 switch (desc
->channel
[first_non_void
].type
) {
4181 case UTIL_FORMAT_TYPE_FLOAT
:
4182 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4184 case UTIL_FORMAT_TYPE_SIGNED
:
4185 if (desc
->channel
[first_non_void
].normalized
)
4186 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4187 else if (desc
->channel
[first_non_void
].pure_integer
)
4188 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4190 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4192 case UTIL_FORMAT_TYPE_UNSIGNED
:
4193 if (desc
->channel
[first_non_void
].normalized
)
4194 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4195 else if (desc
->channel
[first_non_void
].pure_integer
)
4196 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4198 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4203 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4204 if (data_format
== ~0) {
4208 /* S8 with Z32 HTILE needs a special format. */
4209 if (screen
->info
.chip_class
== GFX9
&&
4210 pipe_format
== PIPE_FORMAT_S8_UINT
&&
4211 tex
->tc_compatible_htile
)
4212 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4215 (res
->target
== PIPE_TEXTURE_CUBE
||
4216 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4217 (screen
->info
.chip_class
<= GFX8
&&
4218 res
->target
== PIPE_TEXTURE_3D
))) {
4219 /* For the purpose of shader images, treat cube maps and 3D
4220 * textures as 2D arrays. For 3D textures, the address
4221 * calculations for mipmaps are different, so we rely on the
4222 * caller to effectively disable mipmaps.
4224 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4226 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4228 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4231 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4233 depth
= res
->array_size
;
4234 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
4235 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4236 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4237 depth
= res
->array_size
;
4238 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4239 depth
= res
->array_size
/ 6;
4242 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
4243 S_008F14_NUM_FORMAT(num_format
));
4244 state
[2] = (S_008F18_WIDTH(width
- 1) |
4245 S_008F18_HEIGHT(height
- 1) |
4246 S_008F18_PERF_MOD(4));
4247 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4248 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4249 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4250 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4251 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4252 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
4253 util_logbase2(num_samples
) :
4255 S_008F1C_TYPE(type
));
4257 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4261 if (screen
->info
.chip_class
== GFX9
) {
4262 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4264 /* Depth is the the last accessible layer on Gfx9.
4265 * The hw doesn't need to know the total number of layers.
4267 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4268 state
[4] |= S_008F20_DEPTH(depth
- 1);
4270 state
[4] |= S_008F20_DEPTH(last_layer
);
4272 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4273 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
4274 util_logbase2(num_samples
) :
4275 tex
->buffer
.b
.b
.last_level
);
4277 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4278 state
[4] |= S_008F20_DEPTH(depth
- 1);
4279 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4282 if (tex
->surface
.dcc_offset
) {
4283 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4285 /* The last dword is unused by hw. The shader uses it to clear
4286 * bits in the first dword of sampler state.
4288 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4289 if (first_level
== last_level
)
4290 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4292 state
[7] = 0xffffffff;
4296 /* Initialize the sampler view for FMASK. */
4297 if (tex
->surface
.fmask_offset
) {
4298 uint32_t data_format
, num_format
;
4300 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4302 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4303 if (screen
->info
.chip_class
== GFX9
) {
4304 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4305 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4307 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4310 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4313 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4316 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4319 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4322 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4325 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4328 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4331 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4334 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4337 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4340 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4343 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4346 unreachable("invalid nr_samples");
4349 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4351 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4354 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4357 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4360 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4363 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4366 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4369 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4372 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4375 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4378 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4381 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4384 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4387 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4390 unreachable("invalid nr_samples");
4392 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4396 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4397 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
4398 S_008F14_DATA_FORMAT(data_format
) |
4399 S_008F14_NUM_FORMAT(num_format
);
4400 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
4401 S_008F18_HEIGHT(height
- 1);
4402 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4403 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4404 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4405 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4406 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4408 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4412 if (screen
->info
.chip_class
== GFX9
) {
4413 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4414 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4415 S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4416 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4417 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4419 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4420 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4421 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4422 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4428 * Create a sampler view.
4430 * @param ctx context
4431 * @param texture texture
4432 * @param state sampler view template
4433 * @param width0 width0 override (for compressed textures as int)
4434 * @param height0 height0 override (for compressed textures as int)
4435 * @param force_level set the base address to the level (for compressed textures)
4437 struct pipe_sampler_view
*
4438 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4439 struct pipe_resource
*texture
,
4440 const struct pipe_sampler_view
*state
,
4441 unsigned width0
, unsigned height0
,
4442 unsigned force_level
)
4444 struct si_context
*sctx
= (struct si_context
*)ctx
;
4445 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4446 struct si_texture
*tex
= (struct si_texture
*)texture
;
4447 unsigned base_level
, first_level
, last_level
;
4448 unsigned char state_swizzle
[4];
4449 unsigned height
, depth
, width
;
4450 unsigned last_layer
= state
->u
.tex
.last_layer
;
4451 enum pipe_format pipe_format
;
4452 const struct legacy_surf_level
*surflevel
;
4457 /* initialize base object */
4458 view
->base
= *state
;
4459 view
->base
.texture
= NULL
;
4460 view
->base
.reference
.count
= 1;
4461 view
->base
.context
= ctx
;
4464 pipe_resource_reference(&view
->base
.texture
, texture
);
4466 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4467 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4468 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4469 state
->format
== PIPE_FORMAT_S8_UINT
)
4470 view
->is_stencil_sampler
= true;
4472 /* Buffer resource. */
4473 if (texture
->target
== PIPE_BUFFER
) {
4474 si_make_buffer_descriptor(sctx
->screen
,
4475 si_resource(texture
),
4477 state
->u
.buf
.offset
,
4483 state_swizzle
[0] = state
->swizzle_r
;
4484 state_swizzle
[1] = state
->swizzle_g
;
4485 state_swizzle
[2] = state
->swizzle_b
;
4486 state_swizzle
[3] = state
->swizzle_a
;
4489 first_level
= state
->u
.tex
.first_level
;
4490 last_level
= state
->u
.tex
.last_level
;
4493 depth
= texture
->depth0
;
4495 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4496 assert(force_level
== first_level
&&
4497 force_level
== last_level
);
4498 base_level
= force_level
;
4501 width
= u_minify(width
, force_level
);
4502 height
= u_minify(height
, force_level
);
4503 depth
= u_minify(depth
, force_level
);
4506 /* This is not needed if state trackers set last_layer correctly. */
4507 if (state
->target
== PIPE_TEXTURE_1D
||
4508 state
->target
== PIPE_TEXTURE_2D
||
4509 state
->target
== PIPE_TEXTURE_RECT
||
4510 state
->target
== PIPE_TEXTURE_CUBE
)
4511 last_layer
= state
->u
.tex
.first_layer
;
4513 /* Texturing with separate depth and stencil. */
4514 pipe_format
= state
->format
;
4516 /* Depth/stencil texturing sometimes needs separate texture. */
4517 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4518 if (!tex
->flushed_depth_texture
&&
4519 !si_init_flushed_depth_texture(ctx
, texture
)) {
4520 pipe_resource_reference(&view
->base
.texture
, NULL
);
4525 assert(tex
->flushed_depth_texture
);
4527 /* Override format for the case where the flushed texture
4528 * contains only Z or only S.
4530 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4531 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4533 tex
= tex
->flushed_depth_texture
;
4536 surflevel
= tex
->surface
.u
.legacy
.level
;
4538 if (tex
->db_compatible
) {
4539 if (!view
->is_stencil_sampler
)
4540 pipe_format
= tex
->db_render_format
;
4542 switch (pipe_format
) {
4543 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4544 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4546 case PIPE_FORMAT_X8Z24_UNORM
:
4547 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4548 /* Z24 is always stored like this for DB
4551 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4553 case PIPE_FORMAT_X24S8_UINT
:
4554 case PIPE_FORMAT_S8X24_UINT
:
4555 case PIPE_FORMAT_X32_S8X24_UINT
:
4556 pipe_format
= PIPE_FORMAT_S8_UINT
;
4557 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4563 view
->dcc_incompatible
=
4564 vi_dcc_formats_are_incompatible(texture
,
4565 state
->u
.tex
.first_level
,
4568 sctx
->screen
->make_texture_descriptor(sctx
->screen
, tex
, true,
4569 state
->target
, pipe_format
, state_swizzle
,
4570 first_level
, last_level
,
4571 state
->u
.tex
.first_layer
, last_layer
,
4572 width
, height
, depth
,
4573 view
->state
, view
->fmask_state
);
4575 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4576 view
->is_integer
= false;
4578 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4579 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4582 /* Whether the number format is {U,S}{SCALED,INT} */
4584 (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4585 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4586 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4590 view
->base_level_info
= &surflevel
[base_level
];
4591 view
->base_level
= base_level
;
4592 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4596 static struct pipe_sampler_view
*
4597 si_create_sampler_view(struct pipe_context
*ctx
,
4598 struct pipe_resource
*texture
,
4599 const struct pipe_sampler_view
*state
)
4601 return si_create_sampler_view_custom(ctx
, texture
, state
,
4602 texture
? texture
->width0
: 0,
4603 texture
? texture
->height0
: 0, 0);
4606 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4607 struct pipe_sampler_view
*state
)
4609 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4611 pipe_resource_reference(&state
->texture
, NULL
);
4615 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4617 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4618 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4620 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4621 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4624 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4625 const struct pipe_sampler_state
*state
,
4626 const union pipe_color_union
*color
,
4629 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4630 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4632 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4633 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4634 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4635 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4637 #define simple_border_types(elt) \
4639 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4640 color->elt[2] == 0 && color->elt[3] == 0) \
4641 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4642 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4643 color->elt[2] == 0 && color->elt[3] == 1) \
4644 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4645 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4646 color->elt[2] == 1 && color->elt[3] == 1) \
4647 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4651 simple_border_types(ui
);
4653 simple_border_types(f
);
4655 #undef simple_border_types
4659 /* Check if the border has been uploaded already. */
4660 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4661 if (memcmp(&sctx
->border_color_table
[i
], color
,
4662 sizeof(*color
)) == 0)
4665 if (i
>= SI_MAX_BORDER_COLORS
) {
4666 /* Getting 4096 unique border colors is very unlikely. */
4667 fprintf(stderr
, "radeonsi: The border color table is full. "
4668 "Any new border colors will be just black. "
4669 "Please file a bug.\n");
4670 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4673 if (i
== sctx
->border_color_count
) {
4674 /* Upload a new border color. */
4675 memcpy(&sctx
->border_color_table
[i
], color
,
4677 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4678 color
, sizeof(*color
));
4679 sctx
->border_color_count
++;
4682 return S_008F3C_BORDER_COLOR_PTR(i
) |
4683 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4686 static inline int S_FIXED(float value
, unsigned frac_bits
)
4688 return value
* (1 << frac_bits
);
4691 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4693 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4694 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4695 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4697 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4698 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4701 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4714 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4715 const struct pipe_sampler_state
*state
)
4717 struct si_context
*sctx
= (struct si_context
*)ctx
;
4718 struct si_screen
*sscreen
= sctx
->screen
;
4719 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4720 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4721 : state
->max_anisotropy
;
4722 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4723 union pipe_color_union clamped_border_color
;
4730 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4732 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4733 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4734 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4735 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4736 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4737 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4738 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4739 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4740 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4741 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4742 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4743 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4744 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4745 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4746 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4747 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4748 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4749 S_008F38_MIP_POINT_PRECLAMP(0));
4750 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4752 if (sscreen
->info
.chip_class
>= GFX10
) {
4753 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4755 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4756 S_008F38_FILTER_PREC_FIX(1) |
4757 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4760 /* Create sampler resource for integer textures. */
4761 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4762 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4764 /* Create sampler resource for upgraded depth textures. */
4765 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4767 for (unsigned i
= 0; i
< 4; ++i
) {
4768 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4769 * when the border color is 1.0. */
4770 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4773 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4774 if (sscreen
->info
.chip_class
<= GFX9
)
4775 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4777 rstate
->upgraded_depth_val
[3] =
4778 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4784 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4786 struct si_context
*sctx
= (struct si_context
*)ctx
;
4788 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4791 sctx
->sample_mask
= sample_mask
;
4792 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4795 static void si_emit_sample_mask(struct si_context
*sctx
)
4797 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4798 unsigned mask
= sctx
->sample_mask
;
4800 /* Needed for line and polygon smoothing as well as for the Polaris
4801 * small primitive filter. We expect the state tracker to take care of
4804 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4805 (mask
& 1 && sctx
->blitter
->running
));
4807 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4808 radeon_emit(cs
, mask
| (mask
<< 16));
4809 radeon_emit(cs
, mask
| (mask
<< 16));
4812 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4815 struct si_sampler_state
*s
= state
;
4817 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4824 * Vertex elements & buffers
4827 struct si_fast_udiv_info32
4828 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4830 struct util_fast_udiv_info info
=
4831 util_compute_fast_udiv_info(D
, num_bits
, 32);
4833 struct si_fast_udiv_info32 result
= {
4842 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4844 const struct pipe_vertex_element
*elements
)
4846 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4847 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4848 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4849 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4850 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4851 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4852 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4853 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4854 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4857 assert(count
<= SI_MAX_ATTRIBS
);
4862 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4864 for (i
= 0; i
< count
; ++i
) {
4865 const struct util_format_description
*desc
;
4866 const struct util_format_channel_description
*channel
;
4868 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4870 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4875 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4876 if (instance_divisor
) {
4877 v
->uses_instance_divisors
= true;
4879 if (instance_divisor
== 1) {
4880 v
->instance_divisor_is_one
|= 1u << i
;
4882 v
->instance_divisor_is_fetched
|= 1u << i
;
4883 divisor_factors
[i
] =
4884 si_compute_fast_udiv_info32(instance_divisor
, 32);
4888 if (!used
[vbo_index
]) {
4889 v
->first_vb_use_mask
|= 1 << i
;
4890 used
[vbo_index
] = true;
4893 desc
= util_format_description(elements
[i
].src_format
);
4894 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4895 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4897 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4898 v
->src_offset
[i
] = elements
[i
].src_offset
;
4899 v
->vertex_buffer_index
[i
] = vbo_index
;
4901 bool always_fix
= false;
4902 union si_vs_fix_fetch fix_fetch
;
4903 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4906 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4909 switch (channel
->type
) {
4910 case UTIL_FORMAT_TYPE_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4911 case UTIL_FORMAT_TYPE_FIXED
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
; break;
4912 case UTIL_FORMAT_TYPE_SIGNED
: {
4913 if (channel
->pure_integer
)
4914 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4915 else if (channel
->normalized
)
4916 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4918 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4921 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4922 if (channel
->pure_integer
)
4923 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4924 else if (channel
->normalized
)
4925 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4927 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4930 default: unreachable("bad format type");
4933 switch (elements
[i
].src_format
) {
4934 case PIPE_FORMAT_R11G11B10_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4935 default: unreachable("bad other format");
4939 if (desc
->channel
[0].size
== 10) {
4940 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4941 log_hw_load_size
= 2;
4943 /* The hardware always treats the 2-bit alpha channel as
4944 * unsigned, so a shader workaround is needed. The affected
4945 * chips are GFX8 and older except Stoney (GFX8.1).
4947 always_fix
= sscreen
->info
.chip_class
<= GFX8
&&
4948 sscreen
->info
.family
!= CHIP_STONEY
&&
4949 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4950 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4951 fix_fetch
.u
.log_size
= 3; /* special encoding */
4952 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4953 log_hw_load_size
= 2;
4955 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4956 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4959 * - doubles (multiple loads + truncate to float)
4960 * - 32-bit requiring a conversion
4963 (fix_fetch
.u
.log_size
== 3) ||
4964 (fix_fetch
.u
.log_size
== 2 &&
4965 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4966 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4967 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4969 /* Also fixup 8_8_8 and 16_16_16. */
4970 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4972 log_hw_load_size
= fix_fetch
.u
.log_size
;
4976 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4977 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4978 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4979 fix_fetch
.u
.reverse
= 1;
4982 /* Force the workaround for unaligned access here already if the
4983 * offset relative to the vertex buffer base is unaligned.
4985 * There is a theoretical case in which this is too conservative:
4986 * if the vertex buffer's offset is also unaligned in just the
4987 * right way, we end up with an aligned address after all.
4988 * However, this case should be extremely rare in practice (it
4989 * won't happen in well-behaved applications), and taking it
4990 * into account would complicate the fast path (where everything
4991 * is nicely aligned).
4993 bool check_alignment
=
4994 log_hw_load_size
>= 1 &&
4995 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
== GFX10
);
4996 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4998 if (check_alignment
&&
4999 (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
5002 if (always_fix
|| check_alignment
|| opencode
)
5003 v
->fix_fetch
[i
] = fix_fetch
.bits
;
5006 v
->fix_fetch_opencode
|= 1 << i
;
5007 if (opencode
|| always_fix
)
5008 v
->fix_fetch_always
|= 1 << i
;
5010 if (check_alignment
&& !opencode
) {
5011 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
5013 v
->fix_fetch_unaligned
|= 1 << i
;
5014 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
5015 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
5018 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
5019 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
5020 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
5021 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
5023 if (sscreen
->info
.chip_class
>= GFX10
) {
5024 const struct gfx10_format
*fmt
=
5025 &gfx10_format_table
[elements
[i
].src_format
];
5026 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
5027 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) |
5028 S_008F0C_RESOURCE_LEVEL(1);
5030 unsigned data_format
, num_format
;
5031 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
5032 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
5033 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) |
5034 S_008F0C_DATA_FORMAT(data_format
);
5038 if (v
->instance_divisor_is_fetched
) {
5039 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
5041 v
->instance_divisor_factor_buffer
=
5042 (struct si_resource
*)
5043 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
5044 num_divisors
* sizeof(divisor_factors
[0]));
5045 if (!v
->instance_divisor_factor_buffer
) {
5049 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
5050 NULL
, PIPE_TRANSFER_WRITE
);
5051 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
5056 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
5058 struct si_context
*sctx
= (struct si_context
*)ctx
;
5059 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
5060 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5062 sctx
->vertex_elements
= v
;
5063 sctx
->vertex_buffers_dirty
= true;
5067 old
->count
!= v
->count
||
5068 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
5069 /* we don't check which divisors changed */
5070 v
->uses_instance_divisors
||
5071 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) & sctx
->vertex_buffer_unaligned
||
5072 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
5073 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
5074 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
5075 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5076 * functions of fix_fetch and the src_offset alignment.
5077 * If they change and fix_fetch doesn't, it must be due to different
5078 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5079 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
5080 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
5081 sctx
->do_update_shaders
= true;
5083 if (v
&& v
->instance_divisor_is_fetched
) {
5084 struct pipe_constant_buffer cb
;
5086 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
5087 cb
.user_buffer
= NULL
;
5088 cb
.buffer_offset
= 0;
5089 cb
.buffer_size
= 0xffffffff;
5090 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
5094 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
5096 struct si_context
*sctx
= (struct si_context
*)ctx
;
5097 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5099 if (sctx
->vertex_elements
== state
)
5100 sctx
->vertex_elements
= NULL
;
5101 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
5105 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
5106 unsigned start_slot
, unsigned count
,
5107 const struct pipe_vertex_buffer
*buffers
)
5109 struct si_context
*sctx
= (struct si_context
*)ctx
;
5110 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
5111 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
5112 uint32_t unaligned
= orig_unaligned
;
5115 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
5118 for (i
= 0; i
< count
; i
++) {
5119 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
5120 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
5121 struct pipe_resource
*buf
= src
->buffer
.resource
;
5123 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
5124 dsti
->buffer_offset
= src
->buffer_offset
;
5125 dsti
->stride
= src
->stride
;
5126 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
5127 unaligned
|= 1 << (start_slot
+ i
);
5129 unaligned
&= ~(1 << (start_slot
+ i
));
5131 si_context_add_resource_size(sctx
, buf
);
5133 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
5136 for (i
= 0; i
< count
; i
++) {
5137 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
5139 unaligned
&= ~u_bit_consecutive(start_slot
, count
);
5141 sctx
->vertex_buffers_dirty
= true;
5142 sctx
->vertex_buffer_unaligned
= unaligned
;
5144 /* Check whether alignment may have changed in a way that requires
5145 * shader changes. This check is conservative: a vertex buffer can only
5146 * trigger a shader change if the misalignment amount changes (e.g.
5147 * from byte-aligned to short-aligned), but we only keep track of
5148 * whether buffers are at least dword-aligned, since that should always
5149 * be the case in well-behaved applications anyway.
5151 if (sctx
->vertex_elements
&&
5152 (sctx
->vertex_elements
->vb_alignment_check_mask
&
5153 (unaligned
| orig_unaligned
) & u_bit_consecutive(start_slot
, count
)))
5154 sctx
->do_update_shaders
= true;
5161 static void si_set_tess_state(struct pipe_context
*ctx
,
5162 const float default_outer_level
[4],
5163 const float default_inner_level
[2])
5165 struct si_context
*sctx
= (struct si_context
*)ctx
;
5166 struct pipe_constant_buffer cb
;
5169 memcpy(array
, default_outer_level
, sizeof(float) * 4);
5170 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
5173 cb
.user_buffer
= NULL
;
5174 cb
.buffer_size
= sizeof(array
);
5176 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
5177 (void*)array
, sizeof(array
),
5180 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
5181 pipe_resource_reference(&cb
.buffer
, NULL
);
5184 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5186 struct si_context
*sctx
= (struct si_context
*)ctx
;
5188 si_update_fb_dirtiness_after_rendering(sctx
);
5190 /* Multisample surfaces are flushed in si_decompress_textures. */
5191 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5192 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5193 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5194 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5198 /* This only ensures coherency for shader image/buffer stores. */
5199 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5201 struct si_context
*sctx
= (struct si_context
*)ctx
;
5203 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5206 /* Subsequent commands must wait for all shader invocations to
5208 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
5209 SI_CONTEXT_CS_PARTIAL_FLUSH
;
5211 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5212 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
|
5213 SI_CONTEXT_INV_VCACHE
;
5215 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
5216 PIPE_BARRIER_SHADER_BUFFER
|
5217 PIPE_BARRIER_TEXTURE
|
5218 PIPE_BARRIER_IMAGE
|
5219 PIPE_BARRIER_STREAMOUT_BUFFER
|
5220 PIPE_BARRIER_GLOBAL_BUFFER
)) {
5221 /* As far as I can tell, L1 contents are written back to L2
5222 * automatically at end of shader, but the contents of other
5223 * L1 caches might still be stale. */
5224 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5227 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5228 /* Indices are read through TC L2 since GFX8.
5231 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5232 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5235 /* MSAA color, any depth and any stencil are flushed in
5236 * si_decompress_textures when needed.
5238 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
5239 sctx
->framebuffer
.uncompressed_cb_mask
) {
5240 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5242 if (sctx
->chip_class
<= GFX8
)
5243 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5246 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5247 if (sctx
->screen
->info
.chip_class
<= GFX8
&&
5248 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5249 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5252 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5254 struct pipe_blend_state blend
;
5256 memset(&blend
, 0, sizeof(blend
));
5257 blend
.independent_blend_enable
= true;
5258 blend
.rt
[0].colormask
= 0xf;
5259 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5262 static void si_init_config(struct si_context
*sctx
);
5264 void si_init_state_compute_functions(struct si_context
*sctx
)
5266 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5267 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5268 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5269 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5270 sctx
->b
.memory_barrier
= si_memory_barrier
;
5273 void si_init_state_functions(struct si_context
*sctx
)
5275 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5276 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5277 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5278 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5279 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5280 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5281 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5282 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5283 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5284 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5285 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5287 sctx
->b
.create_blend_state
= si_create_blend_state
;
5288 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5289 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5290 sctx
->b
.set_blend_color
= si_set_blend_color
;
5292 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5293 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5294 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5296 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5297 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5298 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5300 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5301 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5302 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5303 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5304 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5306 sctx
->b
.set_clip_state
= si_set_clip_state
;
5307 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5309 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5311 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5313 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5314 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5315 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5316 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5318 sctx
->b
.texture_barrier
= si_texture_barrier
;
5319 sctx
->b
.set_min_samples
= si_set_min_samples
;
5320 sctx
->b
.set_tess_state
= si_set_tess_state
;
5322 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5324 si_init_config(sctx
);
5327 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5329 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5331 if (sscreen
->info
.chip_class
>= GFX10
) {
5332 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5334 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5338 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
5339 struct si_pm4_state
*pm4
, unsigned value
)
5341 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
:
5342 R_00802C_GRBM_GFX_INDEX
;
5343 si_pm4_set_reg(pm4
, reg
, value
);
5346 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
5347 struct si_pm4_state
*pm4
, unsigned se
)
5349 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5350 si_set_grbm_gfx_index(sctx
, pm4
,
5351 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5352 S_030800_SE_INDEX(se
)) |
5353 S_030800_SH_BROADCAST_WRITES(1) |
5354 S_030800_INSTANCE_BROADCAST_WRITES(1));
5358 si_write_harvested_raster_configs(struct si_context
*sctx
,
5359 struct si_pm4_state
*pm4
,
5360 unsigned raster_config
,
5361 unsigned raster_config_1
)
5363 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5364 unsigned raster_config_se
[4];
5367 ac_get_harvested_configs(&sctx
->screen
->info
,
5372 for (se
= 0; se
< num_se
; se
++) {
5373 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5374 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5376 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5378 if (sctx
->chip_class
>= GFX7
) {
5379 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5383 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5385 struct si_screen
*sscreen
= sctx
->screen
;
5386 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5387 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5388 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5389 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5391 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5392 /* Always use the default config when all backends are enabled
5393 * (or when we failed to determine the enabled backends).
5395 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
5397 if (sctx
->chip_class
>= GFX7
)
5398 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
5401 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5405 static void si_init_config(struct si_context
*sctx
)
5407 struct si_screen
*sscreen
= sctx
->screen
;
5408 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5409 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5410 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5415 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5416 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5417 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5418 si_pm4_cmd_end(pm4
, false);
5420 if (has_clear_state
) {
5421 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5422 si_pm4_cmd_add(pm4
, 0);
5423 si_pm4_cmd_end(pm4
, false);
5426 if (sctx
->chip_class
<= GFX8
)
5427 si_set_raster_config(sctx
, pm4
);
5429 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5430 if (!has_clear_state
)
5431 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5433 /* FIXME calculate these values somehow ??? */
5434 if (sctx
->chip_class
<= GFX8
) {
5435 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5436 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5439 if (!has_clear_state
) {
5440 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5441 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5442 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5445 if (sscreen
->info
.chip_class
<= GFX9
)
5446 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5447 if (!has_clear_state
)
5448 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5449 if (sctx
->chip_class
< GFX7
)
5450 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
5451 S_008A14_CLIP_VTX_REORDER_ENA(1));
5453 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5454 * I don't know why. Deduced by trial and error.
5456 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5457 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5458 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5459 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5460 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5461 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5462 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5463 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5464 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5467 if (!has_clear_state
) {
5468 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5469 S_028230_ER_TRI(0xA) |
5470 S_028230_ER_POINT(0xA) |
5471 S_028230_ER_RECT(0xA) |
5472 /* Required by DX10_DIAMOND_TEST_ENA: */
5473 S_028230_ER_LINE_LR(0x1A) |
5474 S_028230_ER_LINE_RL(0x26) |
5475 S_028230_ER_LINE_TB(0xA) |
5476 S_028230_ER_LINE_BT(0xA));
5477 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5478 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5479 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5480 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5481 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5484 if (sctx
->chip_class
>= GFX10
) {
5485 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5486 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5487 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5488 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5489 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5490 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5491 } else if (sctx
->chip_class
== GFX9
) {
5492 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5493 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5494 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5496 /* These registers, when written, also overwrite the CLEAR_STATE
5497 * context, so we can't rely on CLEAR_STATE setting them.
5498 * It would be an issue if there was another UMD changing them.
5500 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5501 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5502 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5505 if (sctx
->chip_class
>= GFX7
) {
5506 if (sctx
->chip_class
>= GFX10
) {
5507 /* Logical CUs 16 - 31 */
5508 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
5509 S_00B404_CU_EN(0xffff));
5510 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
5511 S_00B104_CU_EN(0xffff));
5512 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
5513 S_00B004_CU_EN(0xffff));
5516 if (sctx
->chip_class
>= GFX9
) {
5517 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5518 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5520 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5521 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5522 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5523 S_00B41C_WAVE_LIMIT(0x3F));
5524 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5525 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5527 /* If this is 0, Bonaire can hang even if GS isn't being used.
5528 * Other chips are unaffected. These are suboptimal values,
5529 * but we don't use on-chip GS.
5531 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5532 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5533 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5536 /* Compute LATE_ALLOC_VS.LIMIT. */
5537 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5538 unsigned late_alloc_limit
; /* The limit is per SH. */
5540 if (sctx
->family
== CHIP_KABINI
) {
5541 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5542 } else if (num_cu_per_sh
<= 4) {
5543 /* Too few available compute units per SH. Disallowing
5544 * VS to run on one CU could hurt us more than late VS
5545 * allocation would help.
5547 * 2 is the highest safe number that allows us to keep
5550 late_alloc_limit
= 2;
5552 /* This is a good initial value, allowing 1 late_alloc
5553 * wave per SIMD on num_cu - 2.
5555 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5558 unsigned late_alloc_limit_gs
= late_alloc_limit
;
5559 unsigned cu_mask_vs
= 0xffff;
5560 unsigned cu_mask_gs
= 0xffff;
5562 if (late_alloc_limit
> 2) {
5563 if (sctx
->chip_class
>= GFX10
) {
5564 /* CU2 & CU3 disabled because of the dual CU design */
5565 cu_mask_vs
= 0xfff3;
5566 cu_mask_gs
= 0xfff3; /* NGG only */
5568 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5572 /* Don't use late alloc for NGG on Navi14 due to a hw bug.
5573 * If NGG is never used, enable all CUs.
5575 if (!sscreen
->use_ngg
|| sctx
->family
== CHIP_NAVI14
) {
5576 late_alloc_limit_gs
= 0;
5577 cu_mask_gs
= 0xffff;
5580 /* VS can't execute on one CU if the limit is > 2. */
5581 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5582 S_00B118_CU_EN(cu_mask_vs
) |
5583 S_00B118_WAVE_LIMIT(0x3F));
5584 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5585 S_00B11C_LIMIT(late_alloc_limit
));
5587 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5588 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5590 if (sctx
->chip_class
>= GFX10
) {
5591 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
5592 S_00B204_CU_EN(0xffff) |
5593 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit_gs
));
5596 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5597 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5600 if (sctx
->chip_class
>= GFX10
) {
5601 /* Break up a pixel wave if it contains deallocs for more than
5602 * half the parameter cache.
5604 * To avoid a deadlock where pixel waves aren't launched
5605 * because they're waiting for more pixels while the frontend
5606 * is stuck waiting for PC space, the maximum allowed value is
5607 * the size of the PC minus the largest possible allocation for
5608 * a single primitive shader subgroup.
5610 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
,
5611 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5612 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5614 if (!has_clear_state
) {
5615 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5616 sscreen
->info
.pa_sc_tile_steering_override
);
5619 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5620 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5621 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5622 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5623 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5624 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5625 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5626 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD
));
5628 si_pm4_set_reg(pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5629 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5630 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5631 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5632 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5633 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5634 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5635 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5636 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5637 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5639 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5640 S_00B0C0_SOFT_GROUPING_EN(1) |
5641 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5642 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5644 if (sctx
->family
== CHIP_NAVI10
||
5645 sctx
->family
== CHIP_NAVI12
||
5646 sctx
->family
== CHIP_NAVI14
) {
5647 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
5648 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
5649 si_pm4_cmd_add(pm4
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
5650 si_pm4_cmd_end(pm4
, false);
5652 /* TODO: For culling, replace 128 with 256. */
5653 si_pm4_set_reg(pm4
, R_030980_GE_PC_ALLOC
,
5654 S_030980_OVERSUB_EN(1) |
5655 S_030980_NUM_PC_LINES(128 * sscreen
->info
.max_se
- 1));
5658 if (sctx
->chip_class
>= GFX8
) {
5659 unsigned vgt_tess_distribution
;
5661 vgt_tess_distribution
=
5662 S_028B50_ACCUM_ISOLINE(32) |
5663 S_028B50_ACCUM_TRI(11) |
5664 S_028B50_ACCUM_QUAD(11) |
5665 S_028B50_DONUT_SPLIT(16);
5667 /* Testing with Unigine Heaven extreme tesselation yielded best results
5668 * with TRAP_SPLIT = 3.
5670 if (sctx
->family
== CHIP_FIJI
||
5671 sctx
->family
>= CHIP_POLARIS10
)
5672 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5674 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5675 } else if (!has_clear_state
) {
5676 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5677 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5680 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5681 if (sctx
->chip_class
>= GFX7
) {
5682 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5683 S_028084_ADDRESS(border_color_va
>> 40));
5685 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5686 RADEON_PRIO_BORDER_COLORS
);
5688 if (sctx
->chip_class
>= GFX9
) {
5689 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5690 S_028C48_MAX_ALLOC_COUNT(sscreen
->info
.pbb_max_alloc_count
- 1) |
5691 S_028C48_MAX_PRIM_PER_BATCH(1023));
5692 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5693 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5694 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5697 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5698 sctx
->init_config
= pm4
;