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radeonsi: add new SDMA texture copy code
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 if (!state->rt[j].colormask)
464 continue;
465
466 /* cb_render_state will disable unused ones */
467 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
468
469 if (!state->rt[j].blend_enable) {
470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
471 continue;
472 }
473
474 /* Blending optimizations for Stoney.
475 * These transformations don't change the behavior.
476 *
477 * First, get rid of DST in the blend factors:
478 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
479 */
480 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
481 PIPE_BLENDFACTOR_DST_COLOR,
482 PIPE_BLENDFACTOR_SRC_COLOR);
483 si_blend_remove_dst(&eqA, &srcA, &dstA,
484 PIPE_BLENDFACTOR_DST_COLOR,
485 PIPE_BLENDFACTOR_SRC_COLOR);
486 si_blend_remove_dst(&eqA, &srcA, &dstA,
487 PIPE_BLENDFACTOR_DST_ALPHA,
488 PIPE_BLENDFACTOR_SRC_ALPHA);
489
490 /* Look up the ideal settings from tables. */
491 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
492 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
493 srcA_opt = si_translate_blend_opt_factor(srcA, true);
494 dstA_opt = si_translate_blend_opt_factor(dstA, true);
495
496 /* Handle interdependencies. */
497 if (si_blend_factor_uses_dst(srcRGB))
498 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
499 if (si_blend_factor_uses_dst(srcA))
500 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
501
502 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
503 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
504 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
505 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
507
508 /* Set the final value. */
509 sx_mrt_blend_opt[i] =
510 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
511 S_028760_COLOR_DST_OPT(dstRGB_opt) |
512 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
513 S_028760_ALPHA_SRC_OPT(srcA_opt) |
514 S_028760_ALPHA_DST_OPT(dstA_opt) |
515 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
516
517 /* Set blend state. */
518 blend_cntl |= S_028780_ENABLE(1);
519 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
520 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
521 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
522
523 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
524 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
525 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
526 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
527 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
528 }
529 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
530
531 blend->blend_enable_4bit |= 0xfu << (i * 4);
532
533 /* This is only important for formats without alpha. */
534 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
535 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
536 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
537 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
538 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
539 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
540 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
541 }
542
543 if (blend->cb_target_mask) {
544 color_control |= S_028808_MODE(mode);
545 } else {
546 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
547 }
548
549 if (sctx->b.family == CHIP_STONEY) {
550 for (int i = 0; i < 8; i++)
551 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
552 sx_mrt_blend_opt[i]);
553
554 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
555 if (blend->dual_src_blend || state->logicop_enable ||
556 mode == V_028808_CB_RESOLVE)
557 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
558 }
559
560 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
561 return blend;
562 }
563
564 static void *si_create_blend_state(struct pipe_context *ctx,
565 const struct pipe_blend_state *state)
566 {
567 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
568 }
569
570 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
571 {
572 struct si_context *sctx = (struct si_context *)ctx;
573 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
574 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
575 }
576
577 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
578 {
579 struct si_context *sctx = (struct si_context *)ctx;
580 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
581 }
582
583 static void si_set_blend_color(struct pipe_context *ctx,
584 const struct pipe_blend_color *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587
588 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
589 return;
590
591 sctx->blend_color.state = *state;
592 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
593 }
594
595 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
596 {
597 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
598
599 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
600 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
601 }
602
603 /*
604 * Clipping
605 */
606
607 static void si_set_clip_state(struct pipe_context *ctx,
608 const struct pipe_clip_state *state)
609 {
610 struct si_context *sctx = (struct si_context *)ctx;
611 struct pipe_constant_buffer cb;
612
613 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
614 return;
615
616 sctx->clip_state.state = *state;
617 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
618
619 cb.buffer = NULL;
620 cb.user_buffer = state->ucp;
621 cb.buffer_offset = 0;
622 cb.buffer_size = 4*4*8;
623 si_set_constant_buffer(sctx, &sctx->rw_buffers,
624 SI_VS_CONST_CLIP_PLANES, &cb);
625 pipe_resource_reference(&cb.buffer, NULL);
626 }
627
628 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
629 {
630 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
631
632 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
633 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
634 }
635
636 #define SIX_BITS 0x3F
637
638 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
639 {
640 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
641 struct tgsi_shader_info *info = si_get_vs_info(sctx);
642 unsigned window_space =
643 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
644 unsigned clipdist_mask =
645 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
646
647 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
648 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
649 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
650 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
651 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
652 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
653 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
654 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
655 info->writes_edgeflag ||
656 info->writes_layer ||
657 info->writes_viewport_index) |
658 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
659 (sctx->queued.named.rasterizer->clip_plane_enable &
660 clipdist_mask));
661 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
662 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
663 (clipdist_mask ? 0 :
664 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
665 S_028810_CLIP_DISABLE(window_space));
666
667 /* reuse needs to be set off if we write oViewport */
668 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
669 S_028AB4_REUSE_OFF(info->writes_viewport_index));
670 }
671
672 /*
673 * inferred state between framebuffer and rasterizer
674 */
675 static void si_update_poly_offset_state(struct si_context *sctx)
676 {
677 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
678
679 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
680 return;
681
682 switch (sctx->framebuffer.state.zsbuf->texture->format) {
683 case PIPE_FORMAT_Z16_UNORM:
684 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
685 break;
686 default: /* 24-bit */
687 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
688 break;
689 case PIPE_FORMAT_Z32_FLOAT:
690 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
691 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
692 break;
693 }
694 }
695
696 /*
697 * Rasterizer
698 */
699
700 static uint32_t si_translate_fill(uint32_t func)
701 {
702 switch(func) {
703 case PIPE_POLYGON_MODE_FILL:
704 return V_028814_X_DRAW_TRIANGLES;
705 case PIPE_POLYGON_MODE_LINE:
706 return V_028814_X_DRAW_LINES;
707 case PIPE_POLYGON_MODE_POINT:
708 return V_028814_X_DRAW_POINTS;
709 default:
710 assert(0);
711 return V_028814_X_DRAW_POINTS;
712 }
713 }
714
715 static void *si_create_rs_state(struct pipe_context *ctx,
716 const struct pipe_rasterizer_state *state)
717 {
718 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
719 struct si_pm4_state *pm4 = &rs->pm4;
720 unsigned tmp, i;
721 float psize_min, psize_max;
722
723 if (!rs) {
724 return NULL;
725 }
726
727 rs->scissor_enable = state->scissor;
728 rs->two_side = state->light_twoside;
729 rs->multisample_enable = state->multisample;
730 rs->force_persample_interp = state->force_persample_interp;
731 rs->clip_plane_enable = state->clip_plane_enable;
732 rs->line_stipple_enable = state->line_stipple_enable;
733 rs->poly_stipple_enable = state->poly_stipple_enable;
734 rs->line_smooth = state->line_smooth;
735 rs->poly_smooth = state->poly_smooth;
736 rs->uses_poly_offset = state->offset_point || state->offset_line ||
737 state->offset_tri;
738 rs->clamp_fragment_color = state->clamp_fragment_color;
739 rs->flatshade = state->flatshade;
740 rs->sprite_coord_enable = state->sprite_coord_enable;
741 rs->rasterizer_discard = state->rasterizer_discard;
742 rs->pa_sc_line_stipple = state->line_stipple_enable ?
743 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
744 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
745 rs->pa_cl_clip_cntl =
746 S_028810_PS_UCP_MODE(3) |
747 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
748 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
749 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
750 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
751 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
752
753 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
754 S_0286D4_FLAT_SHADE_ENA(1) |
755 S_0286D4_PNT_SPRITE_ENA(1) |
756 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
757 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
758 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
759 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
760 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
761
762 /* point size 12.4 fixed point */
763 tmp = (unsigned)(state->point_size * 8.0);
764 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
765
766 if (state->point_size_per_vertex) {
767 psize_min = util_get_min_point_size(state);
768 psize_max = 8192;
769 } else {
770 /* Force the point size to be as if the vertex output was disabled. */
771 psize_min = state->point_size;
772 psize_max = state->point_size;
773 }
774 /* Divide by two, because 0.5 = 1 pixel. */
775 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
776 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
777 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
778
779 tmp = (unsigned)state->line_width * 8;
780 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
781 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
782 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
783 S_028A48_MSAA_ENABLE(state->multisample ||
784 state->poly_smooth ||
785 state->line_smooth) |
786 S_028A48_VPORT_SCISSOR_ENABLE(1));
787
788 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
789 S_028BE4_PIX_CENTER(state->half_pixel_center) |
790 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
791
792 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
793 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
794 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
795 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
796 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
797 S_028814_FACE(!state->front_ccw) |
798 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
799 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
800 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
801 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
802 state->fill_back != PIPE_POLYGON_MODE_FILL) |
803 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
804 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
805 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
806 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
807
808 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
809 for (i = 0; i < 3; i++) {
810 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
811 float offset_units = state->offset_units;
812 float offset_scale = state->offset_scale * 16.0f;
813
814 switch (i) {
815 case 0: /* 16-bit zbuffer */
816 offset_units *= 4.0f;
817 break;
818 case 1: /* 24-bit zbuffer */
819 offset_units *= 2.0f;
820 break;
821 case 2: /* 32-bit zbuffer */
822 offset_units *= 1.0f;
823 break;
824 }
825
826 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
827 fui(offset_scale));
828 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
829 fui(offset_units));
830 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
831 fui(offset_scale));
832 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
833 fui(offset_units));
834 }
835
836 return rs;
837 }
838
839 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
840 {
841 struct si_context *sctx = (struct si_context *)ctx;
842 struct si_state_rasterizer *old_rs =
843 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
844 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
845
846 if (!state)
847 return;
848
849 if (sctx->framebuffer.nr_samples > 1 &&
850 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
851 si_mark_atom_dirty(sctx, &sctx->db_render_state);
852
853 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
854
855 si_pm4_bind_state(sctx, rasterizer, rs);
856 si_update_poly_offset_state(sctx);
857
858 si_mark_atom_dirty(sctx, &sctx->clip_regs);
859 }
860
861 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
862 {
863 struct si_context *sctx = (struct si_context *)ctx;
864
865 if (sctx->queued.named.rasterizer == state)
866 si_pm4_bind_state(sctx, poly_offset, NULL);
867 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
868 }
869
870 /*
871 * infeered state between dsa and stencil ref
872 */
873 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
874 {
875 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
876 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
877 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
878
879 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
880 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
881 S_028430_STENCILMASK(dsa->valuemask[0]) |
882 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
883 S_028430_STENCILOPVAL(1));
884 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
885 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
886 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
887 S_028434_STENCILOPVAL_BF(1));
888 }
889
890 static void si_set_stencil_ref(struct pipe_context *ctx,
891 const struct pipe_stencil_ref *state)
892 {
893 struct si_context *sctx = (struct si_context *)ctx;
894
895 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
896 return;
897
898 sctx->stencil_ref.state = *state;
899 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
900 }
901
902
903 /*
904 * DSA
905 */
906
907 static uint32_t si_translate_stencil_op(int s_op)
908 {
909 switch (s_op) {
910 case PIPE_STENCIL_OP_KEEP:
911 return V_02842C_STENCIL_KEEP;
912 case PIPE_STENCIL_OP_ZERO:
913 return V_02842C_STENCIL_ZERO;
914 case PIPE_STENCIL_OP_REPLACE:
915 return V_02842C_STENCIL_REPLACE_TEST;
916 case PIPE_STENCIL_OP_INCR:
917 return V_02842C_STENCIL_ADD_CLAMP;
918 case PIPE_STENCIL_OP_DECR:
919 return V_02842C_STENCIL_SUB_CLAMP;
920 case PIPE_STENCIL_OP_INCR_WRAP:
921 return V_02842C_STENCIL_ADD_WRAP;
922 case PIPE_STENCIL_OP_DECR_WRAP:
923 return V_02842C_STENCIL_SUB_WRAP;
924 case PIPE_STENCIL_OP_INVERT:
925 return V_02842C_STENCIL_INVERT;
926 default:
927 R600_ERR("Unknown stencil op %d", s_op);
928 assert(0);
929 break;
930 }
931 return 0;
932 }
933
934 static void *si_create_dsa_state(struct pipe_context *ctx,
935 const struct pipe_depth_stencil_alpha_state *state)
936 {
937 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
938 struct si_pm4_state *pm4 = &dsa->pm4;
939 unsigned db_depth_control;
940 uint32_t db_stencil_control = 0;
941
942 if (!dsa) {
943 return NULL;
944 }
945
946 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
947 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
948 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
949 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
950
951 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
952 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
953 S_028800_ZFUNC(state->depth.func) |
954 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
955
956 /* stencil */
957 if (state->stencil[0].enabled) {
958 db_depth_control |= S_028800_STENCIL_ENABLE(1);
959 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
960 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
961 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
962 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
963
964 if (state->stencil[1].enabled) {
965 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
966 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
967 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
968 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
969 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
970 }
971 }
972
973 /* alpha */
974 if (state->alpha.enabled) {
975 dsa->alpha_func = state->alpha.func;
976
977 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
978 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
979 } else {
980 dsa->alpha_func = PIPE_FUNC_ALWAYS;
981 }
982
983 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
984 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
985 if (state->depth.bounds_test) {
986 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
987 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
988 }
989
990 return dsa;
991 }
992
993 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
994 {
995 struct si_context *sctx = (struct si_context *)ctx;
996 struct si_state_dsa *dsa = state;
997
998 if (!state)
999 return;
1000
1001 si_pm4_bind_state(sctx, dsa, dsa);
1002
1003 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1004 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1005 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1006 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1007 }
1008 }
1009
1010 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1011 {
1012 struct si_context *sctx = (struct si_context *)ctx;
1013 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1014 }
1015
1016 static void *si_create_db_flush_dsa(struct si_context *sctx)
1017 {
1018 struct pipe_depth_stencil_alpha_state dsa = {};
1019
1020 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1021 }
1022
1023 /* DB RENDER STATE */
1024
1025 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1026 {
1027 struct si_context *sctx = (struct si_context*)ctx;
1028
1029 /* Pipeline stat & streamout queries. */
1030 if (enable) {
1031 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1032 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1033 } else {
1034 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1035 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1036 }
1037
1038 /* Occlusion queries. */
1039 if (sctx->occlusion_queries_disabled != !enable) {
1040 sctx->occlusion_queries_disabled = !enable;
1041 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1042 }
1043 }
1044
1045 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1046 {
1047 struct si_context *sctx = (struct si_context*)ctx;
1048
1049 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1050 }
1051
1052 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1053 {
1054 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1055 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1056 unsigned db_shader_control;
1057
1058 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1059
1060 /* DB_RENDER_CONTROL */
1061 if (sctx->dbcb_depth_copy_enabled ||
1062 sctx->dbcb_stencil_copy_enabled) {
1063 radeon_emit(cs,
1064 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1065 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1066 S_028000_COPY_CENTROID(1) |
1067 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1068 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1069 radeon_emit(cs,
1070 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1071 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1072 } else {
1073 radeon_emit(cs,
1074 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1075 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1076 }
1077
1078 /* DB_COUNT_CONTROL (occlusion queries) */
1079 if (sctx->b.num_occlusion_queries > 0 &&
1080 !sctx->occlusion_queries_disabled) {
1081 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1082
1083 if (sctx->b.chip_class >= CIK) {
1084 radeon_emit(cs,
1085 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1086 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1087 S_028004_ZPASS_ENABLE(1) |
1088 S_028004_SLICE_EVEN_ENABLE(1) |
1089 S_028004_SLICE_ODD_ENABLE(1));
1090 } else {
1091 radeon_emit(cs,
1092 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1093 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1094 }
1095 } else {
1096 /* Disable occlusion queries. */
1097 if (sctx->b.chip_class >= CIK) {
1098 radeon_emit(cs, 0);
1099 } else {
1100 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1101 }
1102 }
1103
1104 /* DB_RENDER_OVERRIDE2 */
1105 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1106 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1107 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1108 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1109
1110 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1111 sctx->ps_db_shader_control;
1112
1113 /* Bug workaround for smoothing (overrasterization) on SI. */
1114 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1115 db_shader_control &= C_02880C_Z_ORDER;
1116 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1117 }
1118
1119 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1120 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1121 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1122
1123 if (sctx->b.family == CHIP_STONEY &&
1124 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1125 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1126
1127 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1128 db_shader_control);
1129 }
1130
1131 /*
1132 * format translation
1133 */
1134 static uint32_t si_translate_colorformat(enum pipe_format format)
1135 {
1136 const struct util_format_description *desc = util_format_description(format);
1137
1138 #define HAS_SIZE(x,y,z,w) \
1139 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1140 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1141
1142 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1143 return V_028C70_COLOR_10_11_11;
1144
1145 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1146 return V_028C70_COLOR_INVALID;
1147
1148 switch (desc->nr_channels) {
1149 case 1:
1150 switch (desc->channel[0].size) {
1151 case 8:
1152 return V_028C70_COLOR_8;
1153 case 16:
1154 return V_028C70_COLOR_16;
1155 case 32:
1156 return V_028C70_COLOR_32;
1157 }
1158 break;
1159 case 2:
1160 if (desc->channel[0].size == desc->channel[1].size) {
1161 switch (desc->channel[0].size) {
1162 case 8:
1163 return V_028C70_COLOR_8_8;
1164 case 16:
1165 return V_028C70_COLOR_16_16;
1166 case 32:
1167 return V_028C70_COLOR_32_32;
1168 }
1169 } else if (HAS_SIZE(8,24,0,0)) {
1170 return V_028C70_COLOR_24_8;
1171 } else if (HAS_SIZE(24,8,0,0)) {
1172 return V_028C70_COLOR_8_24;
1173 }
1174 break;
1175 case 3:
1176 if (HAS_SIZE(5,6,5,0)) {
1177 return V_028C70_COLOR_5_6_5;
1178 } else if (HAS_SIZE(32,8,24,0)) {
1179 return V_028C70_COLOR_X24_8_32_FLOAT;
1180 }
1181 break;
1182 case 4:
1183 if (desc->channel[0].size == desc->channel[1].size &&
1184 desc->channel[0].size == desc->channel[2].size &&
1185 desc->channel[0].size == desc->channel[3].size) {
1186 switch (desc->channel[0].size) {
1187 case 4:
1188 return V_028C70_COLOR_4_4_4_4;
1189 case 8:
1190 return V_028C70_COLOR_8_8_8_8;
1191 case 16:
1192 return V_028C70_COLOR_16_16_16_16;
1193 case 32:
1194 return V_028C70_COLOR_32_32_32_32;
1195 }
1196 } else if (HAS_SIZE(5,5,5,1)) {
1197 return V_028C70_COLOR_1_5_5_5;
1198 } else if (HAS_SIZE(10,10,10,2)) {
1199 return V_028C70_COLOR_2_10_10_10;
1200 }
1201 break;
1202 }
1203 return V_028C70_COLOR_INVALID;
1204 }
1205
1206 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1207 {
1208 if (SI_BIG_ENDIAN) {
1209 switch(colorformat) {
1210 /* 8-bit buffers. */
1211 case V_028C70_COLOR_8:
1212 return V_028C70_ENDIAN_NONE;
1213
1214 /* 16-bit buffers. */
1215 case V_028C70_COLOR_5_6_5:
1216 case V_028C70_COLOR_1_5_5_5:
1217 case V_028C70_COLOR_4_4_4_4:
1218 case V_028C70_COLOR_16:
1219 case V_028C70_COLOR_8_8:
1220 return V_028C70_ENDIAN_8IN16;
1221
1222 /* 32-bit buffers. */
1223 case V_028C70_COLOR_8_8_8_8:
1224 case V_028C70_COLOR_2_10_10_10:
1225 case V_028C70_COLOR_8_24:
1226 case V_028C70_COLOR_24_8:
1227 case V_028C70_COLOR_16_16:
1228 return V_028C70_ENDIAN_8IN32;
1229
1230 /* 64-bit buffers. */
1231 case V_028C70_COLOR_16_16_16_16:
1232 return V_028C70_ENDIAN_8IN16;
1233
1234 case V_028C70_COLOR_32_32:
1235 return V_028C70_ENDIAN_8IN32;
1236
1237 /* 128-bit buffers. */
1238 case V_028C70_COLOR_32_32_32_32:
1239 return V_028C70_ENDIAN_8IN32;
1240 default:
1241 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1242 }
1243 } else {
1244 return V_028C70_ENDIAN_NONE;
1245 }
1246 }
1247
1248 static uint32_t si_translate_dbformat(enum pipe_format format)
1249 {
1250 switch (format) {
1251 case PIPE_FORMAT_Z16_UNORM:
1252 return V_028040_Z_16;
1253 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1254 case PIPE_FORMAT_X8Z24_UNORM:
1255 case PIPE_FORMAT_Z24X8_UNORM:
1256 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1257 return V_028040_Z_24; /* deprecated on SI */
1258 case PIPE_FORMAT_Z32_FLOAT:
1259 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1260 return V_028040_Z_32_FLOAT;
1261 default:
1262 return V_028040_Z_INVALID;
1263 }
1264 }
1265
1266 /*
1267 * Texture translation
1268 */
1269
1270 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1271 enum pipe_format format,
1272 const struct util_format_description *desc,
1273 int first_non_void)
1274 {
1275 struct si_screen *sscreen = (struct si_screen*)screen;
1276 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1277 sscreen->b.info.drm_minor >= 31) ||
1278 sscreen->b.info.drm_major == 3;
1279 boolean uniform = TRUE;
1280 int i;
1281
1282 /* Colorspace (return non-RGB formats directly). */
1283 switch (desc->colorspace) {
1284 /* Depth stencil formats */
1285 case UTIL_FORMAT_COLORSPACE_ZS:
1286 switch (format) {
1287 case PIPE_FORMAT_Z16_UNORM:
1288 return V_008F14_IMG_DATA_FORMAT_16;
1289 case PIPE_FORMAT_X24S8_UINT:
1290 case PIPE_FORMAT_Z24X8_UNORM:
1291 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1292 return V_008F14_IMG_DATA_FORMAT_8_24;
1293 case PIPE_FORMAT_X8Z24_UNORM:
1294 case PIPE_FORMAT_S8X24_UINT:
1295 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1296 return V_008F14_IMG_DATA_FORMAT_24_8;
1297 case PIPE_FORMAT_S8_UINT:
1298 return V_008F14_IMG_DATA_FORMAT_8;
1299 case PIPE_FORMAT_Z32_FLOAT:
1300 return V_008F14_IMG_DATA_FORMAT_32;
1301 case PIPE_FORMAT_X32_S8X24_UINT:
1302 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1303 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1304 default:
1305 goto out_unknown;
1306 }
1307
1308 case UTIL_FORMAT_COLORSPACE_YUV:
1309 goto out_unknown; /* TODO */
1310
1311 case UTIL_FORMAT_COLORSPACE_SRGB:
1312 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1313 goto out_unknown;
1314 break;
1315
1316 default:
1317 break;
1318 }
1319
1320 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1321 if (!enable_compressed_formats)
1322 goto out_unknown;
1323
1324 switch (format) {
1325 case PIPE_FORMAT_RGTC1_SNORM:
1326 case PIPE_FORMAT_LATC1_SNORM:
1327 case PIPE_FORMAT_RGTC1_UNORM:
1328 case PIPE_FORMAT_LATC1_UNORM:
1329 return V_008F14_IMG_DATA_FORMAT_BC4;
1330 case PIPE_FORMAT_RGTC2_SNORM:
1331 case PIPE_FORMAT_LATC2_SNORM:
1332 case PIPE_FORMAT_RGTC2_UNORM:
1333 case PIPE_FORMAT_LATC2_UNORM:
1334 return V_008F14_IMG_DATA_FORMAT_BC5;
1335 default:
1336 goto out_unknown;
1337 }
1338 }
1339
1340 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1341 sscreen->b.family == CHIP_STONEY) {
1342 switch (format) {
1343 case PIPE_FORMAT_ETC1_RGB8:
1344 case PIPE_FORMAT_ETC2_RGB8:
1345 case PIPE_FORMAT_ETC2_SRGB8:
1346 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1347 case PIPE_FORMAT_ETC2_RGB8A1:
1348 case PIPE_FORMAT_ETC2_SRGB8A1:
1349 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1350 case PIPE_FORMAT_ETC2_RGBA8:
1351 case PIPE_FORMAT_ETC2_SRGBA8:
1352 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1353 case PIPE_FORMAT_ETC2_R11_UNORM:
1354 case PIPE_FORMAT_ETC2_R11_SNORM:
1355 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1356 case PIPE_FORMAT_ETC2_RG11_UNORM:
1357 case PIPE_FORMAT_ETC2_RG11_SNORM:
1358 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1359 default:
1360 goto out_unknown;
1361 }
1362 }
1363
1364 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1365 if (!enable_compressed_formats)
1366 goto out_unknown;
1367
1368 switch (format) {
1369 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1370 case PIPE_FORMAT_BPTC_SRGBA:
1371 return V_008F14_IMG_DATA_FORMAT_BC7;
1372 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1373 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1374 return V_008F14_IMG_DATA_FORMAT_BC6;
1375 default:
1376 goto out_unknown;
1377 }
1378 }
1379
1380 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1381 switch (format) {
1382 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1383 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1384 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1385 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1386 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1387 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1388 default:
1389 goto out_unknown;
1390 }
1391 }
1392
1393 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1394 if (!enable_compressed_formats)
1395 goto out_unknown;
1396
1397 if (!util_format_s3tc_enabled) {
1398 goto out_unknown;
1399 }
1400
1401 switch (format) {
1402 case PIPE_FORMAT_DXT1_RGB:
1403 case PIPE_FORMAT_DXT1_RGBA:
1404 case PIPE_FORMAT_DXT1_SRGB:
1405 case PIPE_FORMAT_DXT1_SRGBA:
1406 return V_008F14_IMG_DATA_FORMAT_BC1;
1407 case PIPE_FORMAT_DXT3_RGBA:
1408 case PIPE_FORMAT_DXT3_SRGBA:
1409 return V_008F14_IMG_DATA_FORMAT_BC2;
1410 case PIPE_FORMAT_DXT5_RGBA:
1411 case PIPE_FORMAT_DXT5_SRGBA:
1412 return V_008F14_IMG_DATA_FORMAT_BC3;
1413 default:
1414 goto out_unknown;
1415 }
1416 }
1417
1418 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1419 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1420 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1421 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1422 }
1423
1424 /* R8G8Bx_SNORM - TODO CxV8U8 */
1425
1426 /* See whether the components are of the same size. */
1427 for (i = 1; i < desc->nr_channels; i++) {
1428 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1429 }
1430
1431 /* Non-uniform formats. */
1432 if (!uniform) {
1433 switch(desc->nr_channels) {
1434 case 3:
1435 if (desc->channel[0].size == 5 &&
1436 desc->channel[1].size == 6 &&
1437 desc->channel[2].size == 5) {
1438 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1439 }
1440 goto out_unknown;
1441 case 4:
1442 if (desc->channel[0].size == 5 &&
1443 desc->channel[1].size == 5 &&
1444 desc->channel[2].size == 5 &&
1445 desc->channel[3].size == 1) {
1446 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1447 }
1448 if (desc->channel[0].size == 10 &&
1449 desc->channel[1].size == 10 &&
1450 desc->channel[2].size == 10 &&
1451 desc->channel[3].size == 2) {
1452 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1453 }
1454 goto out_unknown;
1455 }
1456 goto out_unknown;
1457 }
1458
1459 if (first_non_void < 0 || first_non_void > 3)
1460 goto out_unknown;
1461
1462 /* uniform formats */
1463 switch (desc->channel[first_non_void].size) {
1464 case 4:
1465 switch (desc->nr_channels) {
1466 #if 0 /* Not supported for render targets */
1467 case 2:
1468 return V_008F14_IMG_DATA_FORMAT_4_4;
1469 #endif
1470 case 4:
1471 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1472 }
1473 break;
1474 case 8:
1475 switch (desc->nr_channels) {
1476 case 1:
1477 return V_008F14_IMG_DATA_FORMAT_8;
1478 case 2:
1479 return V_008F14_IMG_DATA_FORMAT_8_8;
1480 case 4:
1481 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1482 }
1483 break;
1484 case 16:
1485 switch (desc->nr_channels) {
1486 case 1:
1487 return V_008F14_IMG_DATA_FORMAT_16;
1488 case 2:
1489 return V_008F14_IMG_DATA_FORMAT_16_16;
1490 case 4:
1491 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1492 }
1493 break;
1494 case 32:
1495 switch (desc->nr_channels) {
1496 case 1:
1497 return V_008F14_IMG_DATA_FORMAT_32;
1498 case 2:
1499 return V_008F14_IMG_DATA_FORMAT_32_32;
1500 #if 0 /* Not supported for render targets */
1501 case 3:
1502 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1503 #endif
1504 case 4:
1505 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1506 }
1507 }
1508
1509 out_unknown:
1510 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1511 return ~0;
1512 }
1513
1514 static unsigned si_tex_wrap(unsigned wrap)
1515 {
1516 switch (wrap) {
1517 default:
1518 case PIPE_TEX_WRAP_REPEAT:
1519 return V_008F30_SQ_TEX_WRAP;
1520 case PIPE_TEX_WRAP_CLAMP:
1521 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1522 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1523 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1524 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1525 return V_008F30_SQ_TEX_CLAMP_BORDER;
1526 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1527 return V_008F30_SQ_TEX_MIRROR;
1528 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1529 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1530 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1531 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1532 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1533 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1534 }
1535 }
1536
1537 static unsigned si_tex_mipfilter(unsigned filter)
1538 {
1539 switch (filter) {
1540 case PIPE_TEX_MIPFILTER_NEAREST:
1541 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1542 case PIPE_TEX_MIPFILTER_LINEAR:
1543 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1544 default:
1545 case PIPE_TEX_MIPFILTER_NONE:
1546 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1547 }
1548 }
1549
1550 static unsigned si_tex_compare(unsigned compare)
1551 {
1552 switch (compare) {
1553 default:
1554 case PIPE_FUNC_NEVER:
1555 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1556 case PIPE_FUNC_LESS:
1557 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1558 case PIPE_FUNC_EQUAL:
1559 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1560 case PIPE_FUNC_LEQUAL:
1561 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1562 case PIPE_FUNC_GREATER:
1563 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1564 case PIPE_FUNC_NOTEQUAL:
1565 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1566 case PIPE_FUNC_GEQUAL:
1567 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1568 case PIPE_FUNC_ALWAYS:
1569 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1570 }
1571 }
1572
1573 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1574 unsigned nr_samples)
1575 {
1576 if (view_target == PIPE_TEXTURE_CUBE ||
1577 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1578 res_target = view_target;
1579
1580 switch (res_target) {
1581 default:
1582 case PIPE_TEXTURE_1D:
1583 return V_008F1C_SQ_RSRC_IMG_1D;
1584 case PIPE_TEXTURE_1D_ARRAY:
1585 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1586 case PIPE_TEXTURE_2D:
1587 case PIPE_TEXTURE_RECT:
1588 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1589 V_008F1C_SQ_RSRC_IMG_2D;
1590 case PIPE_TEXTURE_2D_ARRAY:
1591 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1592 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1593 case PIPE_TEXTURE_3D:
1594 return V_008F1C_SQ_RSRC_IMG_3D;
1595 case PIPE_TEXTURE_CUBE:
1596 case PIPE_TEXTURE_CUBE_ARRAY:
1597 return V_008F1C_SQ_RSRC_IMG_CUBE;
1598 }
1599 }
1600
1601 /*
1602 * Format support testing
1603 */
1604
1605 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1606 {
1607 return si_translate_texformat(screen, format, util_format_description(format),
1608 util_format_get_first_non_void_channel(format)) != ~0U;
1609 }
1610
1611 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1612 const struct util_format_description *desc,
1613 int first_non_void)
1614 {
1615 unsigned type;
1616 int i;
1617
1618 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1619 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1620
1621 assert(first_non_void >= 0);
1622 type = desc->channel[first_non_void].type;
1623
1624 if (type == UTIL_FORMAT_TYPE_FIXED)
1625 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1626
1627 if (desc->nr_channels == 4 &&
1628 desc->channel[0].size == 10 &&
1629 desc->channel[1].size == 10 &&
1630 desc->channel[2].size == 10 &&
1631 desc->channel[3].size == 2)
1632 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1633
1634 /* See whether the components are of the same size. */
1635 for (i = 0; i < desc->nr_channels; i++) {
1636 if (desc->channel[first_non_void].size != desc->channel[i].size)
1637 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1638 }
1639
1640 switch (desc->channel[first_non_void].size) {
1641 case 8:
1642 switch (desc->nr_channels) {
1643 case 1:
1644 return V_008F0C_BUF_DATA_FORMAT_8;
1645 case 2:
1646 return V_008F0C_BUF_DATA_FORMAT_8_8;
1647 case 3:
1648 case 4:
1649 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1650 }
1651 break;
1652 case 16:
1653 switch (desc->nr_channels) {
1654 case 1:
1655 return V_008F0C_BUF_DATA_FORMAT_16;
1656 case 2:
1657 return V_008F0C_BUF_DATA_FORMAT_16_16;
1658 case 3:
1659 case 4:
1660 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1661 }
1662 break;
1663 case 32:
1664 /* From the Southern Islands ISA documentation about MTBUF:
1665 * 'Memory reads of data in memory that is 32 or 64 bits do not
1666 * undergo any format conversion.'
1667 */
1668 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1669 !desc->channel[first_non_void].pure_integer)
1670 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1671
1672 switch (desc->nr_channels) {
1673 case 1:
1674 return V_008F0C_BUF_DATA_FORMAT_32;
1675 case 2:
1676 return V_008F0C_BUF_DATA_FORMAT_32_32;
1677 case 3:
1678 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1679 case 4:
1680 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1681 }
1682 break;
1683 }
1684
1685 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1686 }
1687
1688 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1689 const struct util_format_description *desc,
1690 int first_non_void)
1691 {
1692 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1693 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1694
1695 assert(first_non_void >= 0);
1696
1697 switch (desc->channel[first_non_void].type) {
1698 case UTIL_FORMAT_TYPE_SIGNED:
1699 if (desc->channel[first_non_void].normalized)
1700 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1701 else if (desc->channel[first_non_void].pure_integer)
1702 return V_008F0C_BUF_NUM_FORMAT_SINT;
1703 else
1704 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1705 break;
1706 case UTIL_FORMAT_TYPE_UNSIGNED:
1707 if (desc->channel[first_non_void].normalized)
1708 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1709 else if (desc->channel[first_non_void].pure_integer)
1710 return V_008F0C_BUF_NUM_FORMAT_UINT;
1711 else
1712 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1713 break;
1714 case UTIL_FORMAT_TYPE_FLOAT:
1715 default:
1716 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1717 }
1718 }
1719
1720 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1721 {
1722 const struct util_format_description *desc;
1723 int first_non_void;
1724 unsigned data_format;
1725
1726 desc = util_format_description(format);
1727 first_non_void = util_format_get_first_non_void_channel(format);
1728 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1729 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1730 }
1731
1732 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1733 {
1734 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1735 r600_translate_colorswap(format, FALSE) != ~0U;
1736 }
1737
1738 static bool si_is_zs_format_supported(enum pipe_format format)
1739 {
1740 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1741 }
1742
1743 boolean si_is_format_supported(struct pipe_screen *screen,
1744 enum pipe_format format,
1745 enum pipe_texture_target target,
1746 unsigned sample_count,
1747 unsigned usage)
1748 {
1749 unsigned retval = 0;
1750
1751 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1752 R600_ERR("r600: unsupported texture type %d\n", target);
1753 return FALSE;
1754 }
1755
1756 if (!util_format_is_supported(format, usage))
1757 return FALSE;
1758
1759 if (sample_count > 1) {
1760 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1761 return FALSE;
1762
1763 switch (sample_count) {
1764 case 2:
1765 case 4:
1766 case 8:
1767 break;
1768 case 16:
1769 if (format == PIPE_FORMAT_NONE)
1770 return TRUE;
1771 else
1772 return FALSE;
1773 default:
1774 return FALSE;
1775 }
1776 }
1777
1778 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1779 if (target == PIPE_BUFFER) {
1780 if (si_is_vertex_format_supported(screen, format))
1781 retval |= PIPE_BIND_SAMPLER_VIEW;
1782 } else {
1783 if (si_is_sampler_format_supported(screen, format))
1784 retval |= PIPE_BIND_SAMPLER_VIEW;
1785 }
1786 }
1787
1788 if ((usage & (PIPE_BIND_RENDER_TARGET |
1789 PIPE_BIND_DISPLAY_TARGET |
1790 PIPE_BIND_SCANOUT |
1791 PIPE_BIND_SHARED |
1792 PIPE_BIND_BLENDABLE)) &&
1793 si_is_colorbuffer_format_supported(format)) {
1794 retval |= usage &
1795 (PIPE_BIND_RENDER_TARGET |
1796 PIPE_BIND_DISPLAY_TARGET |
1797 PIPE_BIND_SCANOUT |
1798 PIPE_BIND_SHARED);
1799 if (!util_format_is_pure_integer(format) &&
1800 !util_format_is_depth_or_stencil(format))
1801 retval |= usage & PIPE_BIND_BLENDABLE;
1802 }
1803
1804 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1805 si_is_zs_format_supported(format)) {
1806 retval |= PIPE_BIND_DEPTH_STENCIL;
1807 }
1808
1809 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1810 si_is_vertex_format_supported(screen, format)) {
1811 retval |= PIPE_BIND_VERTEX_BUFFER;
1812 }
1813
1814 if (usage & PIPE_BIND_TRANSFER_READ)
1815 retval |= PIPE_BIND_TRANSFER_READ;
1816 if (usage & PIPE_BIND_TRANSFER_WRITE)
1817 retval |= PIPE_BIND_TRANSFER_WRITE;
1818
1819 if ((usage & PIPE_BIND_LINEAR) &&
1820 !util_format_is_compressed(format) &&
1821 !(usage & PIPE_BIND_DEPTH_STENCIL))
1822 retval |= PIPE_BIND_LINEAR;
1823
1824 return retval == usage;
1825 }
1826
1827 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level,
1828 bool stencil)
1829 {
1830 unsigned tile_mode_index = 0;
1831
1832 if (stencil) {
1833 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1834 } else {
1835 tile_mode_index = rtex->surface.tiling_index[level];
1836 }
1837 return tile_mode_index;
1838 }
1839
1840 /*
1841 * framebuffer handling
1842 */
1843
1844 static void si_choose_spi_color_formats(struct r600_surface *surf,
1845 unsigned format, unsigned swap,
1846 unsigned ntype, bool is_depth)
1847 {
1848 /* Alpha is needed for alpha-to-coverage.
1849 * Blending may be with or without alpha.
1850 */
1851 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1852 unsigned alpha = 0; /* exports alpha, but may not support blending */
1853 unsigned blend = 0; /* supports blending, but may not export alpha */
1854 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1855
1856 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1857 * Other chips have multiple choices, though they are not necessarily better.
1858 */
1859 switch (format) {
1860 case V_028C70_COLOR_5_6_5:
1861 case V_028C70_COLOR_1_5_5_5:
1862 case V_028C70_COLOR_5_5_5_1:
1863 case V_028C70_COLOR_4_4_4_4:
1864 case V_028C70_COLOR_10_11_11:
1865 case V_028C70_COLOR_11_11_10:
1866 case V_028C70_COLOR_8:
1867 case V_028C70_COLOR_8_8:
1868 case V_028C70_COLOR_8_8_8_8:
1869 case V_028C70_COLOR_10_10_10_2:
1870 case V_028C70_COLOR_2_10_10_10:
1871 if (ntype == V_028C70_NUMBER_UINT)
1872 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1873 else if (ntype == V_028C70_NUMBER_SINT)
1874 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1875 else
1876 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1877 break;
1878
1879 case V_028C70_COLOR_16:
1880 case V_028C70_COLOR_16_16:
1881 case V_028C70_COLOR_16_16_16_16:
1882 if (ntype == V_028C70_NUMBER_UNORM ||
1883 ntype == V_028C70_NUMBER_SNORM) {
1884 /* UNORM16 and SNORM16 don't support blending */
1885 if (ntype == V_028C70_NUMBER_UNORM)
1886 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1887 else
1888 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1889
1890 /* Use 32 bits per channel for blending. */
1891 if (format == V_028C70_COLOR_16) {
1892 if (swap == V_028C70_SWAP_STD) { /* R */
1893 blend = V_028714_SPI_SHADER_32_R;
1894 blend_alpha = V_028714_SPI_SHADER_32_AR;
1895 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1896 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1897 else
1898 assert(0);
1899 } else if (format == V_028C70_COLOR_16_16) {
1900 if (swap == V_028C70_SWAP_STD) { /* RG */
1901 blend = V_028714_SPI_SHADER_32_GR;
1902 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1903 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1904 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1905 else
1906 assert(0);
1907 } else /* 16_16_16_16 */
1908 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1909 } else if (ntype == V_028C70_NUMBER_UINT)
1910 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1911 else if (ntype == V_028C70_NUMBER_SINT)
1912 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1913 else if (ntype == V_028C70_NUMBER_FLOAT)
1914 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1915 else
1916 assert(0);
1917 break;
1918
1919 case V_028C70_COLOR_32:
1920 if (swap == V_028C70_SWAP_STD) { /* R */
1921 blend = normal = V_028714_SPI_SHADER_32_R;
1922 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1923 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1924 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1925 else
1926 assert(0);
1927 break;
1928
1929 case V_028C70_COLOR_32_32:
1930 if (swap == V_028C70_SWAP_STD) { /* RG */
1931 blend = normal = V_028714_SPI_SHADER_32_GR;
1932 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1933 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1934 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1935 else
1936 assert(0);
1937 break;
1938
1939 case V_028C70_COLOR_32_32_32_32:
1940 case V_028C70_COLOR_8_24:
1941 case V_028C70_COLOR_24_8:
1942 case V_028C70_COLOR_X24_8_32_FLOAT:
1943 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1944 break;
1945
1946 default:
1947 assert(0);
1948 return;
1949 }
1950
1951 /* The DB->CB copy needs 32_ABGR. */
1952 if (is_depth)
1953 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1954
1955 surf->spi_shader_col_format = normal;
1956 surf->spi_shader_col_format_alpha = alpha;
1957 surf->spi_shader_col_format_blend = blend;
1958 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1959 }
1960
1961 static void si_initialize_color_surface(struct si_context *sctx,
1962 struct r600_surface *surf)
1963 {
1964 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1965 unsigned level = surf->base.u.tex.level;
1966 uint64_t offset = rtex->surface.level[level].offset;
1967 unsigned pitch, slice;
1968 unsigned color_info, color_attrib, color_pitch, color_view;
1969 unsigned tile_mode_index;
1970 unsigned format, swap, ntype, endian;
1971 const struct util_format_description *desc;
1972 int i;
1973 unsigned blend_clamp = 0, blend_bypass = 0;
1974
1975 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1976 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1977
1978 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1979 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1980 if (slice) {
1981 slice = slice - 1;
1982 }
1983
1984 tile_mode_index = si_tile_mode_index(rtex, level, false);
1985
1986 desc = util_format_description(surf->base.format);
1987 for (i = 0; i < 4; i++) {
1988 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1989 break;
1990 }
1991 }
1992 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1993 ntype = V_028C70_NUMBER_FLOAT;
1994 } else {
1995 ntype = V_028C70_NUMBER_UNORM;
1996 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1997 ntype = V_028C70_NUMBER_SRGB;
1998 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1999 if (desc->channel[i].pure_integer) {
2000 ntype = V_028C70_NUMBER_SINT;
2001 } else {
2002 assert(desc->channel[i].normalized);
2003 ntype = V_028C70_NUMBER_SNORM;
2004 }
2005 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2006 if (desc->channel[i].pure_integer) {
2007 ntype = V_028C70_NUMBER_UINT;
2008 } else {
2009 assert(desc->channel[i].normalized);
2010 ntype = V_028C70_NUMBER_UNORM;
2011 }
2012 }
2013 }
2014
2015 format = si_translate_colorformat(surf->base.format);
2016 if (format == V_028C70_COLOR_INVALID) {
2017 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2018 }
2019 assert(format != V_028C70_COLOR_INVALID);
2020 swap = r600_translate_colorswap(surf->base.format, FALSE);
2021 endian = si_colorformat_endian_swap(format);
2022
2023 /* blend clamp should be set for all NORM/SRGB types */
2024 if (ntype == V_028C70_NUMBER_UNORM ||
2025 ntype == V_028C70_NUMBER_SNORM ||
2026 ntype == V_028C70_NUMBER_SRGB)
2027 blend_clamp = 1;
2028
2029 /* set blend bypass according to docs if SINT/UINT or
2030 8/24 COLOR variants */
2031 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2032 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2033 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2034 blend_clamp = 0;
2035 blend_bypass = 1;
2036 }
2037
2038 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2039 (format == V_028C70_COLOR_8 ||
2040 format == V_028C70_COLOR_8_8 ||
2041 format == V_028C70_COLOR_8_8_8_8))
2042 surf->color_is_int8 = true;
2043
2044 color_info = S_028C70_FORMAT(format) |
2045 S_028C70_COMP_SWAP(swap) |
2046 S_028C70_BLEND_CLAMP(blend_clamp) |
2047 S_028C70_BLEND_BYPASS(blend_bypass) |
2048 S_028C70_NUMBER_TYPE(ntype) |
2049 S_028C70_ENDIAN(endian);
2050
2051 color_pitch = S_028C64_TILE_MAX(pitch);
2052
2053 /* Intensity is implemented as Red, so treat it that way. */
2054 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2055 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2056 util_format_is_intensity(surf->base.format));
2057
2058 if (rtex->resource.b.b.nr_samples > 1) {
2059 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2060
2061 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2062 S_028C74_NUM_FRAGMENTS(log_samples);
2063
2064 if (rtex->fmask.size) {
2065 color_info |= S_028C70_COMPRESSION(1);
2066 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2067
2068 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2069
2070 if (sctx->b.chip_class == SI) {
2071 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2072 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2073 }
2074 if (sctx->b.chip_class >= CIK) {
2075 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2076 }
2077 }
2078 }
2079
2080 offset += rtex->resource.gpu_address;
2081
2082 surf->cb_color_base = offset >> 8;
2083 surf->cb_color_pitch = color_pitch;
2084 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2085 surf->cb_color_view = color_view;
2086 surf->cb_color_info = color_info;
2087 surf->cb_color_attrib = color_attrib;
2088
2089 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2090 unsigned max_uncompressed_block_size = 2;
2091
2092 if (rtex->surface.nsamples > 1) {
2093 if (rtex->surface.bpe == 1)
2094 max_uncompressed_block_size = 0;
2095 else if (rtex->surface.bpe == 2)
2096 max_uncompressed_block_size = 1;
2097 }
2098
2099 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2100 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2101 surf->cb_dcc_base = (rtex->resource.gpu_address +
2102 rtex->dcc_offset +
2103 rtex->surface.level[level].dcc_offset) >> 8;
2104 }
2105
2106 if (rtex->fmask.size) {
2107 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2108 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2109 } else {
2110 /* This must be set for fast clear to work without FMASK. */
2111 surf->cb_color_fmask = surf->cb_color_base;
2112 surf->cb_color_fmask_slice = surf->cb_color_slice;
2113 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2114
2115 if (sctx->b.chip_class == SI) {
2116 unsigned bankh = util_logbase2(rtex->surface.bankh);
2117 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2118 }
2119
2120 if (sctx->b.chip_class >= CIK) {
2121 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2122 }
2123 }
2124
2125 /* Determine pixel shader export format */
2126 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2127
2128 surf->color_initialized = true;
2129 }
2130
2131 static void si_init_depth_surface(struct si_context *sctx,
2132 struct r600_surface *surf)
2133 {
2134 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2135 unsigned level = surf->base.u.tex.level;
2136 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2137 unsigned format;
2138 uint32_t z_info, s_info, db_depth_info;
2139 uint64_t z_offs, s_offs;
2140 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2141
2142 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2143 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2144 case PIPE_FORMAT_X8Z24_UNORM:
2145 case PIPE_FORMAT_Z24X8_UNORM:
2146 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2147 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2148 break;
2149 case PIPE_FORMAT_Z32_FLOAT:
2150 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2151 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2152 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2153 break;
2154 case PIPE_FORMAT_Z16_UNORM:
2155 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2156 break;
2157 default:
2158 assert(0);
2159 }
2160
2161 format = si_translate_dbformat(rtex->resource.b.b.format);
2162
2163 if (format == V_028040_Z_INVALID) {
2164 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2165 }
2166 assert(format != V_028040_Z_INVALID);
2167
2168 s_offs = z_offs = rtex->resource.gpu_address;
2169 z_offs += rtex->surface.level[level].offset;
2170 s_offs += rtex->surface.stencil_level[level].offset;
2171
2172 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2173
2174 z_info = S_028040_FORMAT(format);
2175 if (rtex->resource.b.b.nr_samples > 1) {
2176 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2177 }
2178
2179 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2180 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2181 else
2182 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2183
2184 if (sctx->b.chip_class >= CIK) {
2185 struct radeon_info *info = &sctx->screen->b.info;
2186 unsigned index = rtex->surface.tiling_index[level];
2187 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2188 unsigned macro_index = rtex->surface.macro_tile_index;
2189 unsigned tile_mode = info->si_tile_mode_array[index];
2190 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2191 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2192
2193 db_depth_info |=
2194 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2195 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2196 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2197 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2198 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2199 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2200 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2201 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2202 } else {
2203 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2204 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2205 tile_mode_index = si_tile_mode_index(rtex, level, true);
2206 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2207 }
2208
2209 /* HiZ aka depth buffer htile */
2210 /* use htile only for first level */
2211 if (rtex->htile_buffer && !level) {
2212 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2213 S_028040_ALLOW_EXPCLEAR(1);
2214
2215 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2216 /* Workaround: For a not yet understood reason, the
2217 * combination of MSAA, fast stencil clear and stencil
2218 * decompress messes with subsequent stencil buffer
2219 * uses. Problem was reproduced on Verde, Bonaire,
2220 * Tonga, and Carrizo.
2221 *
2222 * Disabling EXPCLEAR works around the problem.
2223 *
2224 * Check piglit's arb_texture_multisample-stencil-clear
2225 * test if you want to try changing this.
2226 */
2227 if (rtex->resource.b.b.nr_samples <= 1)
2228 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2229 } else
2230 /* Use all of the htile_buffer for depth if there's no stencil. */
2231 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2232
2233 uint64_t va = rtex->htile_buffer->gpu_address;
2234 db_htile_data_base = va >> 8;
2235 db_htile_surface = S_028ABC_FULL_CACHE(1);
2236 } else {
2237 db_htile_data_base = 0;
2238 db_htile_surface = 0;
2239 }
2240
2241 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2242
2243 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2244 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2245 surf->db_htile_data_base = db_htile_data_base;
2246 surf->db_depth_info = db_depth_info;
2247 surf->db_z_info = z_info;
2248 surf->db_stencil_info = s_info;
2249 surf->db_depth_base = z_offs >> 8;
2250 surf->db_stencil_base = s_offs >> 8;
2251 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2252 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2253 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2254 levelinfo->nblk_y) / 64 - 1);
2255 surf->db_htile_surface = db_htile_surface;
2256 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2257
2258 surf->depth_initialized = true;
2259 }
2260
2261 static void si_set_framebuffer_state(struct pipe_context *ctx,
2262 const struct pipe_framebuffer_state *state)
2263 {
2264 struct si_context *sctx = (struct si_context *)ctx;
2265 struct pipe_constant_buffer constbuf = {0};
2266 struct r600_surface *surf = NULL;
2267 struct r600_texture *rtex;
2268 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2269 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2270 int i;
2271
2272 /* Only flush TC when changing the framebuffer state, because
2273 * the only client not using TC that can change textures is
2274 * the framebuffer.
2275 *
2276 * Flush all CB and DB caches here because all buffers can be used
2277 * for write by both TC (with shader image stores) and CB/DB.
2278 */
2279 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2280 SI_CONTEXT_INV_GLOBAL_L2 |
2281 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2282 SI_CONTEXT_CS_PARTIAL_FLUSH;
2283
2284 /* Take the maximum of the old and new count. If the new count is lower,
2285 * dirtying is needed to disable the unbound colorbuffers.
2286 */
2287 sctx->framebuffer.dirty_cbufs |=
2288 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2289 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2290
2291 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2292
2293 sctx->framebuffer.spi_shader_col_format = 0;
2294 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2295 sctx->framebuffer.spi_shader_col_format_blend = 0;
2296 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2297 sctx->framebuffer.color_is_int8 = 0;
2298
2299 sctx->framebuffer.compressed_cb_mask = 0;
2300 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2301 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2302 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2303 util_format_is_pure_integer(state->cbufs[0]->format);
2304
2305 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2306 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2307
2308 for (i = 0; i < state->nr_cbufs; i++) {
2309 if (!state->cbufs[i])
2310 continue;
2311
2312 surf = (struct r600_surface*)state->cbufs[i];
2313 rtex = (struct r600_texture*)surf->base.texture;
2314
2315 if (!surf->color_initialized) {
2316 si_initialize_color_surface(sctx, surf);
2317 }
2318
2319 sctx->framebuffer.spi_shader_col_format |=
2320 surf->spi_shader_col_format << (i * 4);
2321 sctx->framebuffer.spi_shader_col_format_alpha |=
2322 surf->spi_shader_col_format_alpha << (i * 4);
2323 sctx->framebuffer.spi_shader_col_format_blend |=
2324 surf->spi_shader_col_format_blend << (i * 4);
2325 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2326 surf->spi_shader_col_format_blend_alpha << (i * 4);
2327
2328 if (surf->color_is_int8)
2329 sctx->framebuffer.color_is_int8 |= 1 << i;
2330
2331 if (rtex->fmask.size && rtex->cmask.size) {
2332 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2333 }
2334 r600_context_add_resource_size(ctx, surf->base.texture);
2335 }
2336 /* Set the second SPI format for possible dual-src blending. */
2337 if (i == 1 && surf) {
2338 sctx->framebuffer.spi_shader_col_format |=
2339 surf->spi_shader_col_format << (i * 4);
2340 sctx->framebuffer.spi_shader_col_format_alpha |=
2341 surf->spi_shader_col_format_alpha << (i * 4);
2342 sctx->framebuffer.spi_shader_col_format_blend |=
2343 surf->spi_shader_col_format_blend << (i * 4);
2344 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2345 surf->spi_shader_col_format_blend_alpha << (i * 4);
2346 }
2347
2348 if (state->zsbuf) {
2349 surf = (struct r600_surface*)state->zsbuf;
2350
2351 if (!surf->depth_initialized) {
2352 si_init_depth_surface(sctx, surf);
2353 }
2354 r600_context_add_resource_size(ctx, surf->base.texture);
2355 }
2356
2357 si_update_poly_offset_state(sctx);
2358 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2359 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2360
2361 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2362 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2363 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2364
2365 /* Set sample locations as fragment shader constants. */
2366 switch (sctx->framebuffer.nr_samples) {
2367 case 1:
2368 constbuf.user_buffer = sctx->b.sample_locations_1x;
2369 break;
2370 case 2:
2371 constbuf.user_buffer = sctx->b.sample_locations_2x;
2372 break;
2373 case 4:
2374 constbuf.user_buffer = sctx->b.sample_locations_4x;
2375 break;
2376 case 8:
2377 constbuf.user_buffer = sctx->b.sample_locations_8x;
2378 break;
2379 case 16:
2380 constbuf.user_buffer = sctx->b.sample_locations_16x;
2381 break;
2382 default:
2383 R600_ERR("Requested an invalid number of samples %i.\n",
2384 sctx->framebuffer.nr_samples);
2385 assert(0);
2386 }
2387 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2388 si_set_constant_buffer(sctx, &sctx->rw_buffers,
2389 SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2390
2391 /* Smoothing (only possible with nr_samples == 1) uses the same
2392 * sample locations as the MSAA it simulates.
2393 *
2394 * Therefore, don't update the sample locations when
2395 * transitioning from no AA to smoothing-equivalent AA, and
2396 * vice versa.
2397 */
2398 if ((sctx->framebuffer.nr_samples != 1 ||
2399 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2400 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2401 old_nr_samples != 1))
2402 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2403 }
2404 }
2405
2406 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2407 {
2408 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2409 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2410 unsigned i, nr_cbufs = state->nr_cbufs;
2411 struct r600_texture *tex = NULL;
2412 struct r600_surface *cb = NULL;
2413
2414 /* Colorbuffers. */
2415 for (i = 0; i < nr_cbufs; i++) {
2416 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2417 continue;
2418
2419 cb = (struct r600_surface*)state->cbufs[i];
2420 if (!cb) {
2421 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2422 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2423 continue;
2424 }
2425
2426 tex = (struct r600_texture *)cb->base.texture;
2427 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2428 &tex->resource, RADEON_USAGE_READWRITE,
2429 tex->surface.nsamples > 1 ?
2430 RADEON_PRIO_COLOR_BUFFER_MSAA :
2431 RADEON_PRIO_COLOR_BUFFER);
2432
2433 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2434 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2435 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2436 RADEON_PRIO_CMASK);
2437 }
2438
2439 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2440 sctx->b.chip_class >= VI ? 14 : 13);
2441 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2442 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2443 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2444 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2445 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2446 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2447 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2448 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2449 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2450 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2451 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2452 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2453 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2454
2455 if (sctx->b.chip_class >= VI)
2456 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2457 }
2458 /* set CB_COLOR1_INFO for possible dual-src blending */
2459 if (i == 1 && state->cbufs[0] &&
2460 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2461 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2462 cb->cb_color_info | tex->cb_color_info);
2463 i++;
2464 }
2465 for (; i < 8 ; i++)
2466 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2467 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2468
2469 /* ZS buffer. */
2470 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2471 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2472 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2473
2474 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2475 &rtex->resource, RADEON_USAGE_READWRITE,
2476 zb->base.texture->nr_samples > 1 ?
2477 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2478 RADEON_PRIO_DEPTH_BUFFER);
2479
2480 if (zb->db_htile_data_base) {
2481 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2482 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2483 RADEON_PRIO_HTILE);
2484 }
2485
2486 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2487 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2488
2489 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2490 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2491 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2492 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2493 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2494 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2495 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2496 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2497 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2498 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2499 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2500
2501 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2502 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2503 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2504
2505 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2506 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2507 zb->pa_su_poly_offset_db_fmt_cntl);
2508 } else if (sctx->framebuffer.dirty_zsbuf) {
2509 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2510 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2511 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2512 }
2513
2514 /* Framebuffer dimensions. */
2515 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2516 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2517 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2518
2519 sctx->framebuffer.dirty_cbufs = 0;
2520 sctx->framebuffer.dirty_zsbuf = false;
2521 }
2522
2523 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2524 struct r600_atom *atom)
2525 {
2526 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2527 unsigned nr_samples = sctx->framebuffer.nr_samples;
2528
2529 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2530 SI_NUM_SMOOTH_AA_SAMPLES);
2531 }
2532
2533 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2534 {
2535 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2536
2537 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2538 sctx->ps_iter_samples,
2539 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2540 }
2541
2542
2543 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2544 {
2545 struct si_context *sctx = (struct si_context *)ctx;
2546
2547 if (sctx->ps_iter_samples == min_samples)
2548 return;
2549
2550 sctx->ps_iter_samples = min_samples;
2551
2552 if (sctx->framebuffer.nr_samples > 1)
2553 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2554 }
2555
2556 /*
2557 * Samplers
2558 */
2559
2560 /**
2561 * Build the sampler view descriptor for a buffer texture.
2562 * @param state 256-bit descriptor; only the high 128 bits are filled in
2563 */
2564 void
2565 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2566 enum pipe_format format,
2567 unsigned first_element, unsigned last_element,
2568 uint32_t *state)
2569 {
2570 const struct util_format_description *desc;
2571 int first_non_void;
2572 uint64_t va;
2573 unsigned stride;
2574 unsigned num_records;
2575 unsigned num_format, data_format;
2576
2577 desc = util_format_description(format);
2578 first_non_void = util_format_get_first_non_void_channel(format);
2579 stride = desc->block.bits / 8;
2580 va = buf->gpu_address + first_element * stride;
2581 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2582 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2583
2584 num_records = last_element + 1 - first_element;
2585 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2586
2587 if (screen->b.chip_class >= VI)
2588 num_records *= stride;
2589
2590 state[4] = va;
2591 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2592 S_008F04_STRIDE(stride);
2593 state[6] = num_records;
2594 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2595 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2596 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2597 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2598 S_008F0C_NUM_FORMAT(num_format) |
2599 S_008F0C_DATA_FORMAT(data_format);
2600 }
2601
2602 /**
2603 * Build the sampler view descriptor for a texture.
2604 */
2605 void
2606 si_make_texture_descriptor(struct si_screen *screen,
2607 struct r600_texture *tex,
2608 bool sampler,
2609 enum pipe_texture_target target,
2610 enum pipe_format pipe_format,
2611 const unsigned char state_swizzle[4],
2612 unsigned base_level, unsigned first_level, unsigned last_level,
2613 unsigned first_layer, unsigned last_layer,
2614 unsigned width, unsigned height, unsigned depth,
2615 uint32_t *state,
2616 uint32_t *fmask_state)
2617 {
2618 struct pipe_resource *res = &tex->resource.b.b;
2619 const struct radeon_surf_level *surflevel = tex->surface.level;
2620 const struct util_format_description *desc;
2621 unsigned char swizzle[4];
2622 int first_non_void;
2623 unsigned num_format, data_format, type;
2624 uint32_t pitch;
2625 uint64_t va;
2626
2627 /* Texturing with separate depth and stencil. */
2628 if (tex->is_depth && !tex->is_flushing_texture) {
2629 switch (pipe_format) {
2630 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2631 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2632 break;
2633 case PIPE_FORMAT_X8Z24_UNORM:
2634 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2635 /* Z24 is always stored like this. */
2636 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2637 break;
2638 case PIPE_FORMAT_X24S8_UINT:
2639 case PIPE_FORMAT_S8X24_UINT:
2640 case PIPE_FORMAT_X32_S8X24_UINT:
2641 pipe_format = PIPE_FORMAT_S8_UINT;
2642 surflevel = tex->surface.stencil_level;
2643 break;
2644 default:;
2645 }
2646 }
2647
2648 desc = util_format_description(pipe_format);
2649
2650 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2651 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2652 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2653
2654 switch (pipe_format) {
2655 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2656 case PIPE_FORMAT_X24S8_UINT:
2657 case PIPE_FORMAT_X32_S8X24_UINT:
2658 case PIPE_FORMAT_X8Z24_UNORM:
2659 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2660 break;
2661 default:
2662 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2663 }
2664 } else {
2665 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2666 }
2667
2668 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2669
2670 switch (pipe_format) {
2671 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2672 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2673 break;
2674 default:
2675 if (first_non_void < 0) {
2676 if (util_format_is_compressed(pipe_format)) {
2677 switch (pipe_format) {
2678 case PIPE_FORMAT_DXT1_SRGB:
2679 case PIPE_FORMAT_DXT1_SRGBA:
2680 case PIPE_FORMAT_DXT3_SRGBA:
2681 case PIPE_FORMAT_DXT5_SRGBA:
2682 case PIPE_FORMAT_BPTC_SRGBA:
2683 case PIPE_FORMAT_ETC2_SRGB8:
2684 case PIPE_FORMAT_ETC2_SRGB8A1:
2685 case PIPE_FORMAT_ETC2_SRGBA8:
2686 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2687 break;
2688 case PIPE_FORMAT_RGTC1_SNORM:
2689 case PIPE_FORMAT_LATC1_SNORM:
2690 case PIPE_FORMAT_RGTC2_SNORM:
2691 case PIPE_FORMAT_LATC2_SNORM:
2692 case PIPE_FORMAT_ETC2_R11_SNORM:
2693 case PIPE_FORMAT_ETC2_RG11_SNORM:
2694 /* implies float, so use SNORM/UNORM to determine
2695 whether data is signed or not */
2696 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2697 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2698 break;
2699 default:
2700 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2701 break;
2702 }
2703 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2704 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2705 } else {
2706 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2707 }
2708 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2709 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2710 } else {
2711 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2712
2713 switch (desc->channel[first_non_void].type) {
2714 case UTIL_FORMAT_TYPE_FLOAT:
2715 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2716 break;
2717 case UTIL_FORMAT_TYPE_SIGNED:
2718 if (desc->channel[first_non_void].normalized)
2719 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2720 else if (desc->channel[first_non_void].pure_integer)
2721 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2722 else
2723 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2724 break;
2725 case UTIL_FORMAT_TYPE_UNSIGNED:
2726 if (desc->channel[first_non_void].normalized)
2727 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2728 else if (desc->channel[first_non_void].pure_integer)
2729 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2730 else
2731 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2732 }
2733 }
2734 }
2735
2736 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2737 if (data_format == ~0) {
2738 data_format = 0;
2739 }
2740
2741 if (!sampler &&
2742 (res->target == PIPE_TEXTURE_CUBE ||
2743 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2744 res->target == PIPE_TEXTURE_3D)) {
2745 /* For the purpose of shader images, treat cube maps and 3D
2746 * textures as 2D arrays. For 3D textures, the address
2747 * calculations for mipmaps are different, so we rely on the
2748 * caller to effectively disable mipmaps.
2749 */
2750 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2751
2752 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2753 } else {
2754 type = si_tex_dim(res->target, target, res->nr_samples);
2755 }
2756
2757 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2758 height = 1;
2759 depth = res->array_size;
2760 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2761 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2762 if (sampler || res->target != PIPE_TEXTURE_3D)
2763 depth = res->array_size;
2764 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2765 depth = res->array_size / 6;
2766
2767 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2768 va = tex->resource.gpu_address + surflevel[base_level].offset;
2769
2770 state[0] = va >> 8;
2771 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2772 S_008F14_DATA_FORMAT(data_format) |
2773 S_008F14_NUM_FORMAT(num_format));
2774 state[2] = (S_008F18_WIDTH(width - 1) |
2775 S_008F18_HEIGHT(height - 1));
2776 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2777 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2778 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2779 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2780 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2781 0 : first_level) |
2782 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2783 util_logbase2(res->nr_samples) :
2784 last_level) |
2785 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
2786 S_008F1C_POW2_PAD(res->last_level > 0) |
2787 S_008F1C_TYPE(type));
2788 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2789 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2790 S_008F24_LAST_ARRAY(last_layer));
2791
2792 if (tex->dcc_offset) {
2793 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2794
2795 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2796 state[7] = (tex->resource.gpu_address +
2797 tex->dcc_offset +
2798 surflevel[base_level].dcc_offset) >> 8;
2799 } else {
2800 state[6] = 0;
2801 state[7] = 0;
2802
2803 /* The last dword is unused by hw. The shader uses it to clear
2804 * bits in the first dword of sampler state.
2805 */
2806 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2807 if (first_level == last_level)
2808 state[7] = C_008F30_MAX_ANISO_RATIO;
2809 else
2810 state[7] = 0xffffffff;
2811 }
2812 }
2813
2814 /* Initialize the sampler view for FMASK. */
2815 if (tex->fmask.size) {
2816 uint32_t fmask_format;
2817
2818 va = tex->resource.gpu_address + tex->fmask.offset;
2819
2820 switch (res->nr_samples) {
2821 case 2:
2822 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2823 break;
2824 case 4:
2825 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2826 break;
2827 case 8:
2828 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2829 break;
2830 default:
2831 assert(0);
2832 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2833 }
2834
2835 fmask_state[0] = va >> 8;
2836 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2837 S_008F14_DATA_FORMAT(fmask_format) |
2838 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2839 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2840 S_008F18_HEIGHT(height - 1);
2841 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2842 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2843 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2844 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2845 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2846 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2847 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2848 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2849 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2850 S_008F24_LAST_ARRAY(last_layer);
2851 fmask_state[6] = 0;
2852 fmask_state[7] = 0;
2853 }
2854 }
2855
2856 /**
2857 * Create a sampler view.
2858 *
2859 * @param ctx context
2860 * @param texture texture
2861 * @param state sampler view template
2862 * @param width0 width0 override (for compressed textures as int)
2863 * @param height0 height0 override (for compressed textures as int)
2864 * @param force_level set the base address to the level (for compressed textures)
2865 */
2866 struct pipe_sampler_view *
2867 si_create_sampler_view_custom(struct pipe_context *ctx,
2868 struct pipe_resource *texture,
2869 const struct pipe_sampler_view *state,
2870 unsigned width0, unsigned height0,
2871 unsigned force_level)
2872 {
2873 struct si_context *sctx = (struct si_context*)ctx;
2874 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2875 struct r600_texture *tmp = (struct r600_texture*)texture;
2876 unsigned base_level, first_level, last_level;
2877 unsigned char state_swizzle[4];
2878 unsigned height, depth, width;
2879 unsigned last_layer = state->u.tex.last_layer;
2880
2881 if (!view)
2882 return NULL;
2883
2884 /* initialize base object */
2885 view->base = *state;
2886 view->base.texture = NULL;
2887 view->base.reference.count = 1;
2888 view->base.context = ctx;
2889
2890 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2891 if (!texture) {
2892 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2893 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2894 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2895 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2896 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2897 return &view->base;
2898 }
2899
2900 pipe_resource_reference(&view->base.texture, texture);
2901
2902 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2903 state->format == PIPE_FORMAT_S8X24_UINT ||
2904 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2905 state->format == PIPE_FORMAT_S8_UINT)
2906 view->is_stencil_sampler = true;
2907
2908 /* Buffer resource. */
2909 if (texture->target == PIPE_BUFFER) {
2910 si_make_buffer_descriptor(sctx->screen,
2911 (struct r600_resource *)texture,
2912 state->format,
2913 state->u.buf.first_element,
2914 state->u.buf.last_element,
2915 view->state);
2916
2917 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2918 return &view->base;
2919 }
2920
2921 state_swizzle[0] = state->swizzle_r;
2922 state_swizzle[1] = state->swizzle_g;
2923 state_swizzle[2] = state->swizzle_b;
2924 state_swizzle[3] = state->swizzle_a;
2925
2926 base_level = 0;
2927 first_level = state->u.tex.first_level;
2928 last_level = state->u.tex.last_level;
2929 width = width0;
2930 height = height0;
2931 depth = texture->depth0;
2932
2933 if (force_level) {
2934 assert(force_level == first_level &&
2935 force_level == last_level);
2936 base_level = force_level;
2937 first_level = 0;
2938 last_level = 0;
2939 width = u_minify(width, force_level);
2940 height = u_minify(height, force_level);
2941 depth = u_minify(depth, force_level);
2942 }
2943
2944 /* This is not needed if state trackers set last_layer correctly. */
2945 if (state->target == PIPE_TEXTURE_1D ||
2946 state->target == PIPE_TEXTURE_2D ||
2947 state->target == PIPE_TEXTURE_RECT ||
2948 state->target == PIPE_TEXTURE_CUBE)
2949 last_layer = state->u.tex.first_layer;
2950
2951 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
2952 state->format, state_swizzle,
2953 base_level, first_level, last_level,
2954 state->u.tex.first_layer, last_layer,
2955 width, height, depth,
2956 view->state, view->fmask_state);
2957
2958 return &view->base;
2959 }
2960
2961 static struct pipe_sampler_view *
2962 si_create_sampler_view(struct pipe_context *ctx,
2963 struct pipe_resource *texture,
2964 const struct pipe_sampler_view *state)
2965 {
2966 return si_create_sampler_view_custom(ctx, texture, state,
2967 texture ? texture->width0 : 0,
2968 texture ? texture->height0 : 0, 0);
2969 }
2970
2971 static void si_sampler_view_destroy(struct pipe_context *ctx,
2972 struct pipe_sampler_view *state)
2973 {
2974 struct si_sampler_view *view = (struct si_sampler_view *)state;
2975
2976 if (state->texture && state->texture->target == PIPE_BUFFER)
2977 LIST_DELINIT(&view->list);
2978
2979 pipe_resource_reference(&state->texture, NULL);
2980 FREE(view);
2981 }
2982
2983 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2984 {
2985 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2986 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2987 (linear_filter &&
2988 (wrap == PIPE_TEX_WRAP_CLAMP ||
2989 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2990 }
2991
2992 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2993 {
2994 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2995 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2996
2997 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2998 state->border_color.ui[2] || state->border_color.ui[3]) &&
2999 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3000 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3001 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3002 }
3003
3004 static void *si_create_sampler_state(struct pipe_context *ctx,
3005 const struct pipe_sampler_state *state)
3006 {
3007 struct si_context *sctx = (struct si_context *)ctx;
3008 struct r600_common_screen *rscreen = sctx->b.screen;
3009 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3010 unsigned border_color_type, border_color_index = 0;
3011 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3012 : state->max_anisotropy;
3013 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3014
3015 if (!rstate) {
3016 return NULL;
3017 }
3018
3019 if (!sampler_state_needs_border_color(state))
3020 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3021 else if (state->border_color.f[0] == 0 &&
3022 state->border_color.f[1] == 0 &&
3023 state->border_color.f[2] == 0 &&
3024 state->border_color.f[3] == 0)
3025 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3026 else if (state->border_color.f[0] == 0 &&
3027 state->border_color.f[1] == 0 &&
3028 state->border_color.f[2] == 0 &&
3029 state->border_color.f[3] == 1)
3030 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3031 else if (state->border_color.f[0] == 1 &&
3032 state->border_color.f[1] == 1 &&
3033 state->border_color.f[2] == 1 &&
3034 state->border_color.f[3] == 1)
3035 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3036 else {
3037 int i;
3038
3039 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3040
3041 /* Check if the border has been uploaded already. */
3042 for (i = 0; i < sctx->border_color_count; i++)
3043 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3044 sizeof(state->border_color)) == 0)
3045 break;
3046
3047 if (i >= SI_MAX_BORDER_COLORS) {
3048 /* Getting 4096 unique border colors is very unlikely. */
3049 fprintf(stderr, "radeonsi: The border color table is full. "
3050 "Any new border colors will be just black. "
3051 "Please file a bug.\n");
3052 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3053 } else {
3054 if (i == sctx->border_color_count) {
3055 /* Upload a new border color. */
3056 memcpy(&sctx->border_color_table[i], &state->border_color,
3057 sizeof(state->border_color));
3058 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3059 &state->border_color,
3060 sizeof(state->border_color));
3061 sctx->border_color_count++;
3062 }
3063
3064 border_color_index = i;
3065 }
3066 }
3067
3068 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3069 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3070 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3071 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3072 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3073 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3074 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3075 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3076 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3077 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3078 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3079 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3080 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3081 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3082 S_008F38_MIP_POINT_PRECLAMP(1) |
3083 S_008F38_DISABLE_LSB_CEIL(1) |
3084 S_008F38_FILTER_PREC_FIX(1) |
3085 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3086 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3087 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3088 return rstate;
3089 }
3090
3091 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3092 {
3093 struct si_context *sctx = (struct si_context *)ctx;
3094
3095 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3096 return;
3097
3098 sctx->sample_mask.sample_mask = sample_mask;
3099 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3100 }
3101
3102 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3103 {
3104 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3105 unsigned mask = sctx->sample_mask.sample_mask;
3106
3107 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3108 radeon_emit(cs, mask | (mask << 16));
3109 radeon_emit(cs, mask | (mask << 16));
3110 }
3111
3112 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3113 {
3114 free(state);
3115 }
3116
3117 /*
3118 * Vertex elements & buffers
3119 */
3120
3121 static void *si_create_vertex_elements(struct pipe_context *ctx,
3122 unsigned count,
3123 const struct pipe_vertex_element *elements)
3124 {
3125 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3126 int i;
3127
3128 assert(count <= SI_MAX_ATTRIBS);
3129 if (!v)
3130 return NULL;
3131
3132 v->count = count;
3133 for (i = 0; i < count; ++i) {
3134 const struct util_format_description *desc;
3135 unsigned data_format, num_format;
3136 int first_non_void;
3137
3138 desc = util_format_description(elements[i].src_format);
3139 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3140 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3141 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3142
3143 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3144 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3145 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3146 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3147 S_008F0C_NUM_FORMAT(num_format) |
3148 S_008F0C_DATA_FORMAT(data_format);
3149 v->format_size[i] = desc->block.bits / 8;
3150 }
3151 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3152
3153 return v;
3154 }
3155
3156 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3157 {
3158 struct si_context *sctx = (struct si_context *)ctx;
3159 struct si_vertex_element *v = (struct si_vertex_element*)state;
3160
3161 sctx->vertex_elements = v;
3162 sctx->vertex_buffers_dirty = true;
3163 }
3164
3165 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3166 {
3167 struct si_context *sctx = (struct si_context *)ctx;
3168
3169 if (sctx->vertex_elements == state)
3170 sctx->vertex_elements = NULL;
3171 FREE(state);
3172 }
3173
3174 static void si_set_vertex_buffers(struct pipe_context *ctx,
3175 unsigned start_slot, unsigned count,
3176 const struct pipe_vertex_buffer *buffers)
3177 {
3178 struct si_context *sctx = (struct si_context *)ctx;
3179 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3180 int i;
3181
3182 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3183
3184 if (buffers) {
3185 for (i = 0; i < count; i++) {
3186 const struct pipe_vertex_buffer *src = buffers + i;
3187 struct pipe_vertex_buffer *dsti = dst + i;
3188
3189 pipe_resource_reference(&dsti->buffer, src->buffer);
3190 dsti->buffer_offset = src->buffer_offset;
3191 dsti->stride = src->stride;
3192 r600_context_add_resource_size(ctx, src->buffer);
3193 }
3194 } else {
3195 for (i = 0; i < count; i++) {
3196 pipe_resource_reference(&dst[i].buffer, NULL);
3197 }
3198 }
3199 sctx->vertex_buffers_dirty = true;
3200 }
3201
3202 static void si_set_index_buffer(struct pipe_context *ctx,
3203 const struct pipe_index_buffer *ib)
3204 {
3205 struct si_context *sctx = (struct si_context *)ctx;
3206
3207 if (ib) {
3208 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3209 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3210 r600_context_add_resource_size(ctx, ib->buffer);
3211 } else {
3212 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3213 }
3214 }
3215
3216 /*
3217 * Misc
3218 */
3219
3220 static void si_set_tess_state(struct pipe_context *ctx,
3221 const float default_outer_level[4],
3222 const float default_inner_level[2])
3223 {
3224 struct si_context *sctx = (struct si_context *)ctx;
3225 struct pipe_constant_buffer cb;
3226 float array[8];
3227
3228 memcpy(array, default_outer_level, sizeof(float) * 4);
3229 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3230
3231 cb.buffer = NULL;
3232 cb.user_buffer = NULL;
3233 cb.buffer_size = sizeof(array);
3234
3235 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3236 (void*)array, sizeof(array),
3237 &cb.buffer_offset);
3238
3239 si_set_constant_buffer(sctx, &sctx->rw_buffers,
3240 SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3241 pipe_resource_reference(&cb.buffer, NULL);
3242 }
3243
3244 static void si_texture_barrier(struct pipe_context *ctx)
3245 {
3246 struct si_context *sctx = (struct si_context *)ctx;
3247
3248 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3249 SI_CONTEXT_INV_GLOBAL_L2 |
3250 SI_CONTEXT_FLUSH_AND_INV_CB |
3251 SI_CONTEXT_CS_PARTIAL_FLUSH;
3252 }
3253
3254 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3255 {
3256 struct si_context *sctx = (struct si_context *)ctx;
3257
3258 /* Subsequent commands must wait for all shader invocations to
3259 * complete. */
3260 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3261 SI_CONTEXT_CS_PARTIAL_FLUSH;
3262
3263 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3264 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3265 SI_CONTEXT_INV_VMEM_L1;
3266
3267 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3268 PIPE_BARRIER_SHADER_BUFFER |
3269 PIPE_BARRIER_TEXTURE |
3270 PIPE_BARRIER_IMAGE |
3271 PIPE_BARRIER_STREAMOUT_BUFFER |
3272 PIPE_BARRIER_GLOBAL_BUFFER)) {
3273 /* As far as I can tell, L1 contents are written back to L2
3274 * automatically at end of shader, but the contents of other
3275 * L1 caches might still be stale. */
3276 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3277 }
3278
3279 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3280 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3281
3282 /* Indices are read through TC L2 since VI. */
3283 if (sctx->screen->b.chip_class <= CIK)
3284 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3285 }
3286
3287 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3288 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3289
3290 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3291 PIPE_BARRIER_FRAMEBUFFER |
3292 PIPE_BARRIER_INDIRECT_BUFFER)) {
3293 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3294 *
3295 * We need to make sure that TC L1 & L2 are written back to
3296 * memory, because neither CPU accesses nor CB fetches consider
3297 * TC, but there's no need to invalidate any TC cache lines. */
3298 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3299 }
3300 }
3301
3302 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3303 {
3304 struct pipe_blend_state blend;
3305
3306 memset(&blend, 0, sizeof(blend));
3307 blend.independent_blend_enable = true;
3308 blend.rt[0].colormask = 0xf;
3309 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3310 }
3311
3312 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3313 bool include_draw_vbo)
3314 {
3315 si_need_cs_space((struct si_context*)ctx);
3316 }
3317
3318 static void si_init_config(struct si_context *sctx);
3319
3320 void si_init_state_functions(struct si_context *sctx)
3321 {
3322 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3323 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3324 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3325 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3326 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3327
3328 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3329 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3330 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3331 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3332 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3333 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3334 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3335 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3336 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3337 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3338 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3339
3340 sctx->b.b.create_blend_state = si_create_blend_state;
3341 sctx->b.b.bind_blend_state = si_bind_blend_state;
3342 sctx->b.b.delete_blend_state = si_delete_blend_state;
3343 sctx->b.b.set_blend_color = si_set_blend_color;
3344
3345 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3346 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3347 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3348
3349 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3350 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3351 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3352
3353 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3354 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3355 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3356 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3357 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3358
3359 sctx->b.b.set_clip_state = si_set_clip_state;
3360 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3361
3362 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3363 sctx->b.b.get_sample_position = cayman_get_sample_position;
3364
3365 sctx->b.b.create_sampler_state = si_create_sampler_state;
3366 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3367
3368 sctx->b.b.create_sampler_view = si_create_sampler_view;
3369 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3370
3371 sctx->b.b.set_sample_mask = si_set_sample_mask;
3372
3373 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3374 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3375 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3376 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3377 sctx->b.b.set_index_buffer = si_set_index_buffer;
3378
3379 sctx->b.b.texture_barrier = si_texture_barrier;
3380 sctx->b.b.memory_barrier = si_memory_barrier;
3381 sctx->b.b.set_min_samples = si_set_min_samples;
3382 sctx->b.b.set_tess_state = si_set_tess_state;
3383
3384 sctx->b.b.set_active_query_state = si_set_active_query_state;
3385 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3386 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3387
3388 sctx->b.b.draw_vbo = si_draw_vbo;
3389
3390 si_init_config(sctx);
3391 }
3392
3393 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3394 struct r600_texture *rtex,
3395 struct radeon_bo_metadata *md)
3396 {
3397 struct si_screen *sscreen = (struct si_screen*)rscreen;
3398 struct pipe_resource *res = &rtex->resource.b.b;
3399 static const unsigned char swizzle[] = {
3400 PIPE_SWIZZLE_X,
3401 PIPE_SWIZZLE_Y,
3402 PIPE_SWIZZLE_Z,
3403 PIPE_SWIZZLE_W
3404 };
3405 uint32_t desc[8], i;
3406 bool is_array = util_resource_is_array_texture(res);
3407
3408 /* DRM 2.x.x doesn't support this. */
3409 if (rscreen->info.drm_major != 3)
3410 return;
3411
3412 assert(rtex->fmask.size == 0);
3413
3414 /* Metadata image format format version 1:
3415 * [0] = 1 (metadata format identifier)
3416 * [1] = (VENDOR_ID << 16) | PCI_ID
3417 * [2:9] = image descriptor for the whole resource
3418 * [2] is always 0, because the base address is cleared
3419 * [9] is the DCC offset bits [39:8] from the beginning of
3420 * the buffer
3421 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3422 */
3423
3424 md->metadata[0] = 1; /* metadata image format version 1 */
3425
3426 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3427 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3428
3429 si_make_texture_descriptor(sscreen, rtex, true,
3430 res->target, res->format,
3431 swizzle, 0, 0, res->last_level, 0,
3432 is_array ? res->array_size - 1 : 0,
3433 res->width0, res->height0, res->depth0,
3434 desc, NULL);
3435
3436 /* Clear the base address and set the relative DCC offset. */
3437 desc[0] = 0;
3438 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3439 desc[7] = rtex->dcc_offset >> 8;
3440
3441 /* Dwords [2:9] contain the image descriptor. */
3442 memcpy(&md->metadata[2], desc, sizeof(desc));
3443
3444 /* Dwords [10:..] contain the mipmap level offsets. */
3445 for (i = 0; i <= res->last_level; i++)
3446 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3447
3448 md->size_metadata = (11 + res->last_level) * 4;
3449 }
3450
3451 void si_init_screen_state_functions(struct si_screen *sscreen)
3452 {
3453 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3454 }
3455
3456 static void
3457 si_write_harvested_raster_configs(struct si_context *sctx,
3458 struct si_pm4_state *pm4,
3459 unsigned raster_config,
3460 unsigned raster_config_1)
3461 {
3462 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3463 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3464 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3465 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3466 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3467 unsigned rb_per_se = num_rb / num_se;
3468 unsigned se_mask[4];
3469 unsigned se;
3470
3471 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3472 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3473 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3474 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3475
3476 assert(num_se == 1 || num_se == 2 || num_se == 4);
3477 assert(sh_per_se == 1 || sh_per_se == 2);
3478 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3479
3480 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3481 * fields are for, so I'm leaving them as their default
3482 * values. */
3483
3484 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3485 (!se_mask[2] && !se_mask[3]))) {
3486 raster_config_1 &= C_028354_SE_PAIR_MAP;
3487
3488 if (!se_mask[0] && !se_mask[1]) {
3489 raster_config_1 |=
3490 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3491 } else {
3492 raster_config_1 |=
3493 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3494 }
3495 }
3496
3497 for (se = 0; se < num_se; se++) {
3498 unsigned raster_config_se = raster_config;
3499 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3500 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3501 int idx = (se / 2) * 2;
3502
3503 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3504 raster_config_se &= C_028350_SE_MAP;
3505
3506 if (!se_mask[idx]) {
3507 raster_config_se |=
3508 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3509 } else {
3510 raster_config_se |=
3511 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3512 }
3513 }
3514
3515 pkr0_mask &= rb_mask;
3516 pkr1_mask &= rb_mask;
3517 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3518 raster_config_se &= C_028350_PKR_MAP;
3519
3520 if (!pkr0_mask) {
3521 raster_config_se |=
3522 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3523 } else {
3524 raster_config_se |=
3525 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3526 }
3527 }
3528
3529 if (rb_per_se >= 2) {
3530 unsigned rb0_mask = 1 << (se * rb_per_se);
3531 unsigned rb1_mask = rb0_mask << 1;
3532
3533 rb0_mask &= rb_mask;
3534 rb1_mask &= rb_mask;
3535 if (!rb0_mask || !rb1_mask) {
3536 raster_config_se &= C_028350_RB_MAP_PKR0;
3537
3538 if (!rb0_mask) {
3539 raster_config_se |=
3540 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3541 } else {
3542 raster_config_se |=
3543 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3544 }
3545 }
3546
3547 if (rb_per_se > 2) {
3548 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3549 rb1_mask = rb0_mask << 1;
3550 rb0_mask &= rb_mask;
3551 rb1_mask &= rb_mask;
3552 if (!rb0_mask || !rb1_mask) {
3553 raster_config_se &= C_028350_RB_MAP_PKR1;
3554
3555 if (!rb0_mask) {
3556 raster_config_se |=
3557 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3558 } else {
3559 raster_config_se |=
3560 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3561 }
3562 }
3563 }
3564 }
3565
3566 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3567 if (sctx->b.chip_class < CIK)
3568 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3569 SE_INDEX(se) | SH_BROADCAST_WRITES |
3570 INSTANCE_BROADCAST_WRITES);
3571 else
3572 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3573 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3574 S_030800_INSTANCE_BROADCAST_WRITES(1));
3575 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3576 if (sctx->b.chip_class >= CIK)
3577 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3578 }
3579
3580 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3581 if (sctx->b.chip_class < CIK)
3582 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3583 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3584 INSTANCE_BROADCAST_WRITES);
3585 else
3586 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3587 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3588 S_030800_INSTANCE_BROADCAST_WRITES(1));
3589 }
3590
3591 static void si_init_config(struct si_context *sctx)
3592 {
3593 struct si_screen *sscreen = sctx->screen;
3594 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3595 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3596 unsigned raster_config, raster_config_1;
3597 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3598 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3599 int i;
3600
3601 if (!pm4)
3602 return;
3603
3604 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3605 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3606 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3607 si_pm4_cmd_end(pm4, false);
3608
3609 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3610 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3611
3612 /* FIXME calculate these values somehow ??? */
3613 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3614 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3615 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3616
3617 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3618 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3619
3620 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3621 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3622 if (sctx->b.chip_class < CIK)
3623 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3624 S_008A14_CLIP_VTX_REORDER_ENA(1));
3625
3626 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3627 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3628
3629 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3630
3631 for (i = 0; i < 16; i++) {
3632 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3633 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3634 }
3635
3636 switch (sctx->screen->b.family) {
3637 case CHIP_TAHITI:
3638 case CHIP_PITCAIRN:
3639 raster_config = 0x2a00126a;
3640 raster_config_1 = 0x00000000;
3641 break;
3642 case CHIP_VERDE:
3643 raster_config = 0x0000124a;
3644 raster_config_1 = 0x00000000;
3645 break;
3646 case CHIP_OLAND:
3647 raster_config = 0x00000082;
3648 raster_config_1 = 0x00000000;
3649 break;
3650 case CHIP_HAINAN:
3651 raster_config = 0x00000000;
3652 raster_config_1 = 0x00000000;
3653 break;
3654 case CHIP_BONAIRE:
3655 raster_config = 0x16000012;
3656 raster_config_1 = 0x00000000;
3657 break;
3658 case CHIP_HAWAII:
3659 raster_config = 0x3a00161a;
3660 raster_config_1 = 0x0000002e;
3661 break;
3662 case CHIP_FIJI:
3663 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3664 /* old kernels with old tiling config */
3665 raster_config = 0x16000012;
3666 raster_config_1 = 0x0000002a;
3667 } else {
3668 raster_config = 0x3a00161a;
3669 raster_config_1 = 0x0000002e;
3670 }
3671 break;
3672 case CHIP_POLARIS10:
3673 raster_config = 0x16000012;
3674 raster_config_1 = 0x0000002a;
3675 break;
3676 case CHIP_POLARIS11:
3677 raster_config = 0x16000012;
3678 raster_config_1 = 0x00000000;
3679 break;
3680 case CHIP_TONGA:
3681 raster_config = 0x16000012;
3682 raster_config_1 = 0x0000002a;
3683 break;
3684 case CHIP_ICELAND:
3685 raster_config = 0x00000002;
3686 raster_config_1 = 0x00000000;
3687 break;
3688 case CHIP_CARRIZO:
3689 raster_config = 0x00000002;
3690 raster_config_1 = 0x00000000;
3691 break;
3692 case CHIP_KAVERI:
3693 /* KV should be 0x00000002, but that causes problems with radeon */
3694 raster_config = 0x00000000; /* 0x00000002 */
3695 raster_config_1 = 0x00000000;
3696 break;
3697 case CHIP_KABINI:
3698 case CHIP_MULLINS:
3699 case CHIP_STONEY:
3700 raster_config = 0x00000000;
3701 raster_config_1 = 0x00000000;
3702 break;
3703 default:
3704 fprintf(stderr,
3705 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3706 raster_config = 0x00000000;
3707 raster_config_1 = 0x00000000;
3708 break;
3709 }
3710
3711 /* Always use the default config when all backends are enabled
3712 * (or when we failed to determine the enabled backends).
3713 */
3714 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3715 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3716 raster_config);
3717 if (sctx->b.chip_class >= CIK)
3718 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3719 raster_config_1);
3720 } else {
3721 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3722 }
3723
3724 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3725 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3726 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3727 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3728 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3729 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3730 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3731
3732 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3733 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3734 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3735 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3736 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3737 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3738 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3739 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3740 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3741 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3742 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3743
3744 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3745 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3746 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3747
3748 if (sctx->b.chip_class >= CIK) {
3749 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3750 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3751 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3752
3753 if (sscreen->b.info.num_good_compute_units /
3754 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3755 /* Too few available compute units per SH. Disallowing
3756 * VS to run on CU0 could hurt us more than late VS
3757 * allocation would help.
3758 *
3759 * LATE_ALLOC_VS = 2 is the highest safe number.
3760 */
3761 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3762 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3763 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3764 } else {
3765 /* Set LATE_ALLOC_VS == 31. It should be less than
3766 * the number of scratch waves. Limitations:
3767 * - VS can't execute on CU0.
3768 * - If HS writes outputs to LDS, LS can't execute on CU0.
3769 */
3770 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3771 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3772 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3773 }
3774
3775 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3776 }
3777
3778 if (sctx->b.chip_class >= VI) {
3779 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3780 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3781 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3782 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3783 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3784 }
3785
3786 if (sctx->b.family == CHIP_STONEY)
3787 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3788
3789 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3790 if (sctx->b.chip_class >= CIK)
3791 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3792 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3793 RADEON_PRIO_BORDER_COLORS);
3794
3795 si_pm4_upload_indirect_buffer(sctx, pm4);
3796 sctx->init_config = pm4;
3797 }