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92f8d90a97c3e2e908428718808f29158b463a9c
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_pstipple.h"
38 #include "util/u_resource.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array + 1;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 uint32_t cb_target_mask, i;
100
101 /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
102 if (blend)
103 cb_target_mask = blend->cb_target_mask;
104 else
105 cb_target_mask = 0xffffffff;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* STONEY-specific register settings. */
121 if (sctx->b.family == CHIP_STONEY) {
122 unsigned spi_shader_col_format =
123 sctx->ps_shader.cso ?
124 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
125 unsigned sx_ps_downconvert = 0;
126 unsigned sx_blend_opt_epsilon = 0;
127 unsigned sx_blend_opt_control = 0;
128
129 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
130 struct r600_surface *surf =
131 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
132 unsigned format, swap, spi_format, colormask;
133 bool has_alpha, has_rgb;
134
135 if (!surf)
136 continue;
137
138 format = G_028C70_FORMAT(surf->cb_color_info);
139 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
140 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
141 colormask = (cb_target_mask >> (i * 4)) & 0xf;
142
143 /* Set if RGB and A are present. */
144 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
145
146 if (format == V_028C70_COLOR_8 ||
147 format == V_028C70_COLOR_16 ||
148 format == V_028C70_COLOR_32)
149 has_rgb = !has_alpha;
150 else
151 has_rgb = true;
152
153 /* Check the colormask and export format. */
154 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
155 has_rgb = false;
156 if (!(colormask & PIPE_MASK_A))
157 has_alpha = false;
158
159 if (spi_format == V_028714_SPI_SHADER_ZERO) {
160 has_rgb = false;
161 has_alpha = false;
162 }
163
164 /* Disable value checking for disabled channels. */
165 if (!has_rgb)
166 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
167 if (!has_alpha)
168 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
169
170 /* Enable down-conversion for 32bpp and smaller formats. */
171 switch (format) {
172 case V_028C70_COLOR_8:
173 case V_028C70_COLOR_8_8:
174 case V_028C70_COLOR_8_8_8_8:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
178 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
180 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
181 }
182 break;
183
184 case V_028C70_COLOR_5_6_5:
185 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_1_5_5_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_4_4_4_4:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_32:
206 if (swap == V_0280A0_SWAP_STD &&
207 spi_format == V_028714_SPI_SHADER_32_R)
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
209 else if (swap == V_0280A0_SWAP_ALT_REV &&
210 spi_format == V_028714_SPI_SHADER_32_AR)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
212 break;
213
214 case V_028C70_COLOR_16:
215 case V_028C70_COLOR_16_16:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
221 if (swap == V_0280A0_SWAP_STD ||
222 swap == V_0280A0_SWAP_STD_REV)
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
224 else
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
226 }
227 break;
228
229 case V_028C70_COLOR_10_11_11:
230 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
232 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_2_10_10_10:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
240 }
241 break;
242 }
243 }
244
245 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
246 sx_ps_downconvert = 0;
247 sx_blend_opt_epsilon = 0;
248 sx_blend_opt_control = 0;
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 }
256 }
257
258 /*
259 * Blender functions
260 */
261
262 static uint32_t si_translate_blend_function(int blend_func)
263 {
264 switch (blend_func) {
265 case PIPE_BLEND_ADD:
266 return V_028780_COMB_DST_PLUS_SRC;
267 case PIPE_BLEND_SUBTRACT:
268 return V_028780_COMB_SRC_MINUS_DST;
269 case PIPE_BLEND_REVERSE_SUBTRACT:
270 return V_028780_COMB_DST_MINUS_SRC;
271 case PIPE_BLEND_MIN:
272 return V_028780_COMB_MIN_DST_SRC;
273 case PIPE_BLEND_MAX:
274 return V_028780_COMB_MAX_DST_SRC;
275 default:
276 R600_ERR("Unknown blend function %d\n", blend_func);
277 assert(0);
278 break;
279 }
280 return 0;
281 }
282
283 static uint32_t si_translate_blend_factor(int blend_fact)
284 {
285 switch (blend_fact) {
286 case PIPE_BLENDFACTOR_ONE:
287 return V_028780_BLEND_ONE;
288 case PIPE_BLENDFACTOR_SRC_COLOR:
289 return V_028780_BLEND_SRC_COLOR;
290 case PIPE_BLENDFACTOR_SRC_ALPHA:
291 return V_028780_BLEND_SRC_ALPHA;
292 case PIPE_BLENDFACTOR_DST_ALPHA:
293 return V_028780_BLEND_DST_ALPHA;
294 case PIPE_BLENDFACTOR_DST_COLOR:
295 return V_028780_BLEND_DST_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
297 return V_028780_BLEND_SRC_ALPHA_SATURATE;
298 case PIPE_BLENDFACTOR_CONST_COLOR:
299 return V_028780_BLEND_CONSTANT_COLOR;
300 case PIPE_BLENDFACTOR_CONST_ALPHA:
301 return V_028780_BLEND_CONSTANT_ALPHA;
302 case PIPE_BLENDFACTOR_ZERO:
303 return V_028780_BLEND_ZERO;
304 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
305 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
306 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
309 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
310 case PIPE_BLENDFACTOR_INV_DST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
314 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
316 case PIPE_BLENDFACTOR_SRC1_COLOR:
317 return V_028780_BLEND_SRC1_COLOR;
318 case PIPE_BLENDFACTOR_SRC1_ALPHA:
319 return V_028780_BLEND_SRC1_ALPHA;
320 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
321 return V_028780_BLEND_INV_SRC1_COLOR;
322 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
323 return V_028780_BLEND_INV_SRC1_ALPHA;
324 default:
325 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
326 assert(0);
327 break;
328 }
329 return 0;
330 }
331
332 static uint32_t si_translate_blend_opt_function(int blend_func)
333 {
334 switch (blend_func) {
335 case PIPE_BLEND_ADD:
336 return V_028760_OPT_COMB_ADD;
337 case PIPE_BLEND_SUBTRACT:
338 return V_028760_OPT_COMB_SUBTRACT;
339 case PIPE_BLEND_REVERSE_SUBTRACT:
340 return V_028760_OPT_COMB_REVSUBTRACT;
341 case PIPE_BLEND_MIN:
342 return V_028760_OPT_COMB_MIN;
343 case PIPE_BLEND_MAX:
344 return V_028760_OPT_COMB_MAX;
345 default:
346 return V_028760_OPT_COMB_BLEND_DISABLED;
347 }
348 }
349
350 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
351 {
352 switch (blend_fact) {
353 case PIPE_BLENDFACTOR_ZERO:
354 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
355 case PIPE_BLENDFACTOR_ONE:
356 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
357 case PIPE_BLENDFACTOR_SRC_COLOR:
358 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
359 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
360 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
361 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
362 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
363 case PIPE_BLENDFACTOR_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
365 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
366 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
367 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
369 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
370 default:
371 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
372 }
373 }
374
375 /**
376 * Get rid of DST in the blend factors by commuting the operands:
377 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
378 */
379 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
380 unsigned *dst_factor, unsigned expected_dst,
381 unsigned replacement_src)
382 {
383 if (*src_factor == expected_dst &&
384 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
385 *src_factor = PIPE_BLENDFACTOR_ZERO;
386 *dst_factor = replacement_src;
387
388 /* Commuting the operands requires reversing subtractions. */
389 if (*func == PIPE_BLEND_SUBTRACT)
390 *func = PIPE_BLEND_REVERSE_SUBTRACT;
391 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
392 *func = PIPE_BLEND_SUBTRACT;
393 }
394 }
395
396 static bool si_blend_factor_uses_dst(unsigned factor)
397 {
398 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
399 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
401 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
402 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
403 }
404
405 static void *si_create_blend_state_mode(struct pipe_context *ctx,
406 const struct pipe_blend_state *state,
407 unsigned mode)
408 {
409 struct si_context *sctx = (struct si_context*)ctx;
410 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
411 struct si_pm4_state *pm4 = &blend->pm4;
412 uint32_t sx_mrt_blend_opt[8] = {0};
413 uint32_t color_control = 0;
414
415 if (!blend)
416 return NULL;
417
418 blend->alpha_to_coverage = state->alpha_to_coverage;
419 blend->alpha_to_one = state->alpha_to_one;
420 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
421
422 if (state->logicop_enable) {
423 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
424 } else {
425 color_control |= S_028808_ROP3(0xcc);
426 }
427
428 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
429 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
430 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
433 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
434
435 if (state->alpha_to_coverage)
436 blend->need_src_alpha_4bit |= 0xf;
437
438 blend->cb_target_mask = 0;
439 for (int i = 0; i < 8; i++) {
440 /* state->rt entries > 0 only written if independent blending */
441 const int j = state->independent_blend_enable ? i : 0;
442
443 unsigned eqRGB = state->rt[j].rgb_func;
444 unsigned srcRGB = state->rt[j].rgb_src_factor;
445 unsigned dstRGB = state->rt[j].rgb_dst_factor;
446 unsigned eqA = state->rt[j].alpha_func;
447 unsigned srcA = state->rt[j].alpha_src_factor;
448 unsigned dstA = state->rt[j].alpha_dst_factor;
449
450 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
451 unsigned blend_cntl = 0;
452
453 sx_mrt_blend_opt[i] =
454 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
455 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
456
457 /* Only set dual source blending for MRT0 to avoid a hang. */
458 if (i >= 1 && blend->dual_src_blend)
459 continue;
460
461 /* Only addition and subtraction equations are supported with
462 * dual source blending.
463 */
464 if (blend->dual_src_blend &&
465 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
466 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
467 assert(!"Unsupported equation for dual source blending");
468 continue;
469 }
470
471 if (!state->rt[j].colormask)
472 continue;
473
474 /* cb_render_state will disable unused ones */
475 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
476
477 if (!state->rt[j].blend_enable) {
478 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
479 continue;
480 }
481
482 /* Blending optimizations for Stoney.
483 * These transformations don't change the behavior.
484 *
485 * First, get rid of DST in the blend factors:
486 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
487 */
488 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
489 PIPE_BLENDFACTOR_DST_COLOR,
490 PIPE_BLENDFACTOR_SRC_COLOR);
491 si_blend_remove_dst(&eqA, &srcA, &dstA,
492 PIPE_BLENDFACTOR_DST_COLOR,
493 PIPE_BLENDFACTOR_SRC_COLOR);
494 si_blend_remove_dst(&eqA, &srcA, &dstA,
495 PIPE_BLENDFACTOR_DST_ALPHA,
496 PIPE_BLENDFACTOR_SRC_ALPHA);
497
498 /* Look up the ideal settings from tables. */
499 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
500 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
501 srcA_opt = si_translate_blend_opt_factor(srcA, true);
502 dstA_opt = si_translate_blend_opt_factor(dstA, true);
503
504 /* Handle interdependencies. */
505 if (si_blend_factor_uses_dst(srcRGB))
506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
507 if (si_blend_factor_uses_dst(srcA))
508 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
509
510 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
511 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
512 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
513 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
514 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
515
516 /* Set the final value. */
517 sx_mrt_blend_opt[i] =
518 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
519 S_028760_COLOR_DST_OPT(dstRGB_opt) |
520 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
521 S_028760_ALPHA_SRC_OPT(srcA_opt) |
522 S_028760_ALPHA_DST_OPT(dstA_opt) |
523 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
524
525 /* Set blend state. */
526 blend_cntl |= S_028780_ENABLE(1);
527 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
528 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
529 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
530
531 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
532 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
533 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
534 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
535 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
536 }
537 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
538
539 blend->blend_enable_4bit |= 0xfu << (i * 4);
540
541 /* This is only important for formats without alpha. */
542 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
543 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
544 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
545 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
546 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
547 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
548 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
549 }
550
551 if (blend->cb_target_mask) {
552 color_control |= S_028808_MODE(mode);
553 } else {
554 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
555 }
556
557 if (sctx->b.family == CHIP_STONEY) {
558 for (int i = 0; i < 8; i++)
559 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
560 sx_mrt_blend_opt[i]);
561
562 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
563 if (blend->dual_src_blend || state->logicop_enable ||
564 mode == V_028808_CB_RESOLVE)
565 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
566 }
567
568 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
569 return blend;
570 }
571
572 static void *si_create_blend_state(struct pipe_context *ctx,
573 const struct pipe_blend_state *state)
574 {
575 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
576 }
577
578 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
579 {
580 struct si_context *sctx = (struct si_context *)ctx;
581 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
582 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
583 sctx->do_update_shaders = true;
584 }
585
586 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
587 {
588 struct si_context *sctx = (struct si_context *)ctx;
589 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
590 }
591
592 static void si_set_blend_color(struct pipe_context *ctx,
593 const struct pipe_blend_color *state)
594 {
595 struct si_context *sctx = (struct si_context *)ctx;
596
597 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
598 return;
599
600 sctx->blend_color.state = *state;
601 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
602 }
603
604 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
605 {
606 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
607
608 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
609 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
610 }
611
612 /*
613 * Clipping
614 */
615
616 static void si_set_clip_state(struct pipe_context *ctx,
617 const struct pipe_clip_state *state)
618 {
619 struct si_context *sctx = (struct si_context *)ctx;
620 struct pipe_constant_buffer cb;
621
622 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
623 return;
624
625 sctx->clip_state.state = *state;
626 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
627
628 cb.buffer = NULL;
629 cb.user_buffer = state->ucp;
630 cb.buffer_offset = 0;
631 cb.buffer_size = 4*4*8;
632 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
633 pipe_resource_reference(&cb.buffer, NULL);
634 }
635
636 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
637 {
638 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
639
640 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
641 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
642 }
643
644 #define SIX_BITS 0x3F
645
646 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
647 {
648 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
649 struct tgsi_shader_info *info = si_get_vs_info(sctx);
650 unsigned window_space =
651 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
652 unsigned clipdist_mask =
653 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
654 unsigned total_mask = clipdist_mask | (info->culldist_writemask << info->num_written_clipdistance);
655
656 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
657 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
658 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
659 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
660 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
661 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
662 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
663 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
664 info->writes_edgeflag ||
665 info->writes_layer ||
666 info->writes_viewport_index) |
667 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
668 (sctx->queued.named.rasterizer->clip_plane_enable &
669 clipdist_mask) | (info->culldist_writemask << 8));
670 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
671 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
672 (clipdist_mask ? 0 :
673 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
674 S_028810_CLIP_DISABLE(window_space));
675
676 /* reuse needs to be set off if we write oViewport */
677 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
678 S_028AB4_REUSE_OFF(info->writes_viewport_index));
679 }
680
681 /*
682 * inferred state between framebuffer and rasterizer
683 */
684 static void si_update_poly_offset_state(struct si_context *sctx)
685 {
686 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
687
688 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
689 return;
690
691 switch (sctx->framebuffer.state.zsbuf->texture->format) {
692 case PIPE_FORMAT_Z16_UNORM:
693 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
694 break;
695 default: /* 24-bit */
696 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
697 break;
698 case PIPE_FORMAT_Z32_FLOAT:
699 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
700 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
701 break;
702 }
703 }
704
705 /*
706 * Rasterizer
707 */
708
709 static uint32_t si_translate_fill(uint32_t func)
710 {
711 switch(func) {
712 case PIPE_POLYGON_MODE_FILL:
713 return V_028814_X_DRAW_TRIANGLES;
714 case PIPE_POLYGON_MODE_LINE:
715 return V_028814_X_DRAW_LINES;
716 case PIPE_POLYGON_MODE_POINT:
717 return V_028814_X_DRAW_POINTS;
718 default:
719 assert(0);
720 return V_028814_X_DRAW_POINTS;
721 }
722 }
723
724 static void *si_create_rs_state(struct pipe_context *ctx,
725 const struct pipe_rasterizer_state *state)
726 {
727 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
728 struct si_pm4_state *pm4 = &rs->pm4;
729 unsigned tmp, i;
730 float psize_min, psize_max;
731
732 if (!rs) {
733 return NULL;
734 }
735
736 rs->scissor_enable = state->scissor;
737 rs->clip_halfz = state->clip_halfz;
738 rs->two_side = state->light_twoside;
739 rs->multisample_enable = state->multisample;
740 rs->force_persample_interp = state->force_persample_interp;
741 rs->clip_plane_enable = state->clip_plane_enable;
742 rs->line_stipple_enable = state->line_stipple_enable;
743 rs->poly_stipple_enable = state->poly_stipple_enable;
744 rs->line_smooth = state->line_smooth;
745 rs->poly_smooth = state->poly_smooth;
746 rs->uses_poly_offset = state->offset_point || state->offset_line ||
747 state->offset_tri;
748 rs->clamp_fragment_color = state->clamp_fragment_color;
749 rs->flatshade = state->flatshade;
750 rs->sprite_coord_enable = state->sprite_coord_enable;
751 rs->rasterizer_discard = state->rasterizer_discard;
752 rs->pa_sc_line_stipple = state->line_stipple_enable ?
753 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
754 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
755 rs->pa_cl_clip_cntl =
756 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
757 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
758 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
759 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
760 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
761
762 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
763 S_0286D4_FLAT_SHADE_ENA(1) |
764 S_0286D4_PNT_SPRITE_ENA(1) |
765 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
766 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
767 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
768 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
769 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
770
771 /* point size 12.4 fixed point */
772 tmp = (unsigned)(state->point_size * 8.0);
773 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
774
775 if (state->point_size_per_vertex) {
776 psize_min = util_get_min_point_size(state);
777 psize_max = 8192;
778 } else {
779 /* Force the point size to be as if the vertex output was disabled. */
780 psize_min = state->point_size;
781 psize_max = state->point_size;
782 }
783 /* Divide by two, because 0.5 = 1 pixel. */
784 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
785 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
786 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
787
788 tmp = (unsigned)state->line_width * 8;
789 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
790 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
791 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
792 S_028A48_MSAA_ENABLE(state->multisample ||
793 state->poly_smooth ||
794 state->line_smooth) |
795 S_028A48_VPORT_SCISSOR_ENABLE(1));
796
797 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
798 S_028BE4_PIX_CENTER(state->half_pixel_center) |
799 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
800
801 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
802 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
803 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
804 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
805 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
806 S_028814_FACE(!state->front_ccw) |
807 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
808 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
809 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
810 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
811 state->fill_back != PIPE_POLYGON_MODE_FILL) |
812 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
813 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
814 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
815 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
816
817 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
818 for (i = 0; i < 3; i++) {
819 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
820 float offset_units = state->offset_units;
821 float offset_scale = state->offset_scale * 16.0f;
822 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
823
824 if (!state->offset_units_unscaled) {
825 switch (i) {
826 case 0: /* 16-bit zbuffer */
827 offset_units *= 4.0f;
828 pa_su_poly_offset_db_fmt_cntl =
829 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
830 break;
831 case 1: /* 24-bit zbuffer */
832 offset_units *= 2.0f;
833 pa_su_poly_offset_db_fmt_cntl =
834 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
835 break;
836 case 2: /* 32-bit zbuffer */
837 offset_units *= 1.0f;
838 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
839 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
840 break;
841 }
842 }
843
844 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
845 fui(offset_scale));
846 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
847 fui(offset_units));
848 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
849 fui(offset_scale));
850 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
851 fui(offset_units));
852 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
853 pa_su_poly_offset_db_fmt_cntl);
854 }
855
856 return rs;
857 }
858
859 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
860 {
861 struct si_context *sctx = (struct si_context *)ctx;
862 struct si_state_rasterizer *old_rs =
863 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
864 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
865
866 if (!state)
867 return;
868
869 if (sctx->framebuffer.nr_samples > 1 &&
870 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
871 si_mark_atom_dirty(sctx, &sctx->db_render_state);
872
873 if (sctx->b.family >= CHIP_POLARIS10)
874 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
875 }
876
877 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
878
879 si_pm4_bind_state(sctx, rasterizer, rs);
880 si_update_poly_offset_state(sctx);
881
882 si_mark_atom_dirty(sctx, &sctx->clip_regs);
883 sctx->do_update_shaders = true;
884 }
885
886 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
887 {
888 struct si_context *sctx = (struct si_context *)ctx;
889
890 if (sctx->queued.named.rasterizer == state)
891 si_pm4_bind_state(sctx, poly_offset, NULL);
892 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
893 }
894
895 /*
896 * infeered state between dsa and stencil ref
897 */
898 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
899 {
900 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
901 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
902 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
903
904 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
905 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
906 S_028430_STENCILMASK(dsa->valuemask[0]) |
907 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
908 S_028430_STENCILOPVAL(1));
909 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
910 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
911 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
912 S_028434_STENCILOPVAL_BF(1));
913 }
914
915 static void si_set_stencil_ref(struct pipe_context *ctx,
916 const struct pipe_stencil_ref *state)
917 {
918 struct si_context *sctx = (struct si_context *)ctx;
919
920 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
921 return;
922
923 sctx->stencil_ref.state = *state;
924 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
925 }
926
927
928 /*
929 * DSA
930 */
931
932 static uint32_t si_translate_stencil_op(int s_op)
933 {
934 switch (s_op) {
935 case PIPE_STENCIL_OP_KEEP:
936 return V_02842C_STENCIL_KEEP;
937 case PIPE_STENCIL_OP_ZERO:
938 return V_02842C_STENCIL_ZERO;
939 case PIPE_STENCIL_OP_REPLACE:
940 return V_02842C_STENCIL_REPLACE_TEST;
941 case PIPE_STENCIL_OP_INCR:
942 return V_02842C_STENCIL_ADD_CLAMP;
943 case PIPE_STENCIL_OP_DECR:
944 return V_02842C_STENCIL_SUB_CLAMP;
945 case PIPE_STENCIL_OP_INCR_WRAP:
946 return V_02842C_STENCIL_ADD_WRAP;
947 case PIPE_STENCIL_OP_DECR_WRAP:
948 return V_02842C_STENCIL_SUB_WRAP;
949 case PIPE_STENCIL_OP_INVERT:
950 return V_02842C_STENCIL_INVERT;
951 default:
952 R600_ERR("Unknown stencil op %d", s_op);
953 assert(0);
954 break;
955 }
956 return 0;
957 }
958
959 static void *si_create_dsa_state(struct pipe_context *ctx,
960 const struct pipe_depth_stencil_alpha_state *state)
961 {
962 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
963 struct si_pm4_state *pm4 = &dsa->pm4;
964 unsigned db_depth_control;
965 uint32_t db_stencil_control = 0;
966
967 if (!dsa) {
968 return NULL;
969 }
970
971 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
972 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
973 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
974 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
975
976 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
977 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
978 S_028800_ZFUNC(state->depth.func) |
979 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
980
981 /* stencil */
982 if (state->stencil[0].enabled) {
983 db_depth_control |= S_028800_STENCIL_ENABLE(1);
984 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
985 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
986 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
987 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
988
989 if (state->stencil[1].enabled) {
990 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
991 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
992 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
993 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
994 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
995 }
996 }
997
998 /* alpha */
999 if (state->alpha.enabled) {
1000 dsa->alpha_func = state->alpha.func;
1001
1002 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1003 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1004 } else {
1005 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1006 }
1007
1008 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1009 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1010 if (state->depth.bounds_test) {
1011 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1012 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1013 }
1014
1015 return dsa;
1016 }
1017
1018 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1019 {
1020 struct si_context *sctx = (struct si_context *)ctx;
1021 struct si_state_dsa *dsa = state;
1022
1023 if (!state)
1024 return;
1025
1026 si_pm4_bind_state(sctx, dsa, dsa);
1027
1028 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1029 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1030 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1031 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1032 }
1033 sctx->do_update_shaders = true;
1034 }
1035
1036 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1037 {
1038 struct si_context *sctx = (struct si_context *)ctx;
1039 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1040 }
1041
1042 static void *si_create_db_flush_dsa(struct si_context *sctx)
1043 {
1044 struct pipe_depth_stencil_alpha_state dsa = {};
1045
1046 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1047 }
1048
1049 /* DB RENDER STATE */
1050
1051 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1052 {
1053 struct si_context *sctx = (struct si_context*)ctx;
1054
1055 /* Pipeline stat & streamout queries. */
1056 if (enable) {
1057 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1058 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1059 } else {
1060 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1061 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1062 }
1063
1064 /* Occlusion queries. */
1065 if (sctx->occlusion_queries_disabled != !enable) {
1066 sctx->occlusion_queries_disabled = !enable;
1067 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1068 }
1069 }
1070
1071 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1072 {
1073 struct si_context *sctx = (struct si_context*)ctx;
1074
1075 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1076 }
1077
1078 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1079 {
1080 struct si_context *sctx = (struct si_context*)ctx;
1081
1082 st->saved_compute = sctx->cs_shader_state.program;
1083
1084 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1085 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1086 }
1087
1088 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1089 {
1090 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1091 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1092 unsigned db_shader_control;
1093
1094 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1095
1096 /* DB_RENDER_CONTROL */
1097 if (sctx->dbcb_depth_copy_enabled ||
1098 sctx->dbcb_stencil_copy_enabled) {
1099 radeon_emit(cs,
1100 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1101 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1102 S_028000_COPY_CENTROID(1) |
1103 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1104 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1105 radeon_emit(cs,
1106 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1107 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1108 } else {
1109 radeon_emit(cs,
1110 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1111 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1112 }
1113
1114 /* DB_COUNT_CONTROL (occlusion queries) */
1115 if (sctx->b.num_occlusion_queries > 0 &&
1116 !sctx->occlusion_queries_disabled) {
1117 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1118
1119 if (sctx->b.chip_class >= CIK) {
1120 radeon_emit(cs,
1121 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1122 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1123 S_028004_ZPASS_ENABLE(1) |
1124 S_028004_SLICE_EVEN_ENABLE(1) |
1125 S_028004_SLICE_ODD_ENABLE(1));
1126 } else {
1127 radeon_emit(cs,
1128 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1129 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1130 }
1131 } else {
1132 /* Disable occlusion queries. */
1133 if (sctx->b.chip_class >= CIK) {
1134 radeon_emit(cs, 0);
1135 } else {
1136 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1137 }
1138 }
1139
1140 /* DB_RENDER_OVERRIDE2 */
1141 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1142 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1143 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1144 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1145
1146 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1147 sctx->ps_db_shader_control;
1148
1149 /* Bug workaround for smoothing (overrasterization) on SI. */
1150 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1151 db_shader_control &= C_02880C_Z_ORDER;
1152 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1153 }
1154
1155 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1156 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1157 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1158
1159 if (sctx->b.family == CHIP_STONEY &&
1160 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1161 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1162
1163 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1164 db_shader_control);
1165 }
1166
1167 /*
1168 * format translation
1169 */
1170 static uint32_t si_translate_colorformat(enum pipe_format format)
1171 {
1172 const struct util_format_description *desc = util_format_description(format);
1173
1174 #define HAS_SIZE(x,y,z,w) \
1175 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1176 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1177
1178 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1179 return V_028C70_COLOR_10_11_11;
1180
1181 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1182 return V_028C70_COLOR_INVALID;
1183
1184 /* hw cannot support mixed formats (except depth/stencil, since
1185 * stencil is not written to). */
1186 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1187 return V_028C70_COLOR_INVALID;
1188
1189 switch (desc->nr_channels) {
1190 case 1:
1191 switch (desc->channel[0].size) {
1192 case 8:
1193 return V_028C70_COLOR_8;
1194 case 16:
1195 return V_028C70_COLOR_16;
1196 case 32:
1197 return V_028C70_COLOR_32;
1198 }
1199 break;
1200 case 2:
1201 if (desc->channel[0].size == desc->channel[1].size) {
1202 switch (desc->channel[0].size) {
1203 case 8:
1204 return V_028C70_COLOR_8_8;
1205 case 16:
1206 return V_028C70_COLOR_16_16;
1207 case 32:
1208 return V_028C70_COLOR_32_32;
1209 }
1210 } else if (HAS_SIZE(8,24,0,0)) {
1211 return V_028C70_COLOR_24_8;
1212 } else if (HAS_SIZE(24,8,0,0)) {
1213 return V_028C70_COLOR_8_24;
1214 }
1215 break;
1216 case 3:
1217 if (HAS_SIZE(5,6,5,0)) {
1218 return V_028C70_COLOR_5_6_5;
1219 } else if (HAS_SIZE(32,8,24,0)) {
1220 return V_028C70_COLOR_X24_8_32_FLOAT;
1221 }
1222 break;
1223 case 4:
1224 if (desc->channel[0].size == desc->channel[1].size &&
1225 desc->channel[0].size == desc->channel[2].size &&
1226 desc->channel[0].size == desc->channel[3].size) {
1227 switch (desc->channel[0].size) {
1228 case 4:
1229 return V_028C70_COLOR_4_4_4_4;
1230 case 8:
1231 return V_028C70_COLOR_8_8_8_8;
1232 case 16:
1233 return V_028C70_COLOR_16_16_16_16;
1234 case 32:
1235 return V_028C70_COLOR_32_32_32_32;
1236 }
1237 } else if (HAS_SIZE(5,5,5,1)) {
1238 return V_028C70_COLOR_1_5_5_5;
1239 } else if (HAS_SIZE(10,10,10,2)) {
1240 return V_028C70_COLOR_2_10_10_10;
1241 }
1242 break;
1243 }
1244 return V_028C70_COLOR_INVALID;
1245 }
1246
1247 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1248 {
1249 if (SI_BIG_ENDIAN) {
1250 switch(colorformat) {
1251 /* 8-bit buffers. */
1252 case V_028C70_COLOR_8:
1253 return V_028C70_ENDIAN_NONE;
1254
1255 /* 16-bit buffers. */
1256 case V_028C70_COLOR_5_6_5:
1257 case V_028C70_COLOR_1_5_5_5:
1258 case V_028C70_COLOR_4_4_4_4:
1259 case V_028C70_COLOR_16:
1260 case V_028C70_COLOR_8_8:
1261 return V_028C70_ENDIAN_8IN16;
1262
1263 /* 32-bit buffers. */
1264 case V_028C70_COLOR_8_8_8_8:
1265 case V_028C70_COLOR_2_10_10_10:
1266 case V_028C70_COLOR_8_24:
1267 case V_028C70_COLOR_24_8:
1268 case V_028C70_COLOR_16_16:
1269 return V_028C70_ENDIAN_8IN32;
1270
1271 /* 64-bit buffers. */
1272 case V_028C70_COLOR_16_16_16_16:
1273 return V_028C70_ENDIAN_8IN16;
1274
1275 case V_028C70_COLOR_32_32:
1276 return V_028C70_ENDIAN_8IN32;
1277
1278 /* 128-bit buffers. */
1279 case V_028C70_COLOR_32_32_32_32:
1280 return V_028C70_ENDIAN_8IN32;
1281 default:
1282 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1283 }
1284 } else {
1285 return V_028C70_ENDIAN_NONE;
1286 }
1287 }
1288
1289 static uint32_t si_translate_dbformat(enum pipe_format format)
1290 {
1291 switch (format) {
1292 case PIPE_FORMAT_Z16_UNORM:
1293 return V_028040_Z_16;
1294 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1295 case PIPE_FORMAT_X8Z24_UNORM:
1296 case PIPE_FORMAT_Z24X8_UNORM:
1297 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1298 return V_028040_Z_24; /* deprecated on SI */
1299 case PIPE_FORMAT_Z32_FLOAT:
1300 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1301 return V_028040_Z_32_FLOAT;
1302 default:
1303 return V_028040_Z_INVALID;
1304 }
1305 }
1306
1307 /*
1308 * Texture translation
1309 */
1310
1311 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1312 enum pipe_format format,
1313 const struct util_format_description *desc,
1314 int first_non_void)
1315 {
1316 struct si_screen *sscreen = (struct si_screen*)screen;
1317 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1318 sscreen->b.info.drm_minor >= 31) ||
1319 sscreen->b.info.drm_major == 3;
1320 bool uniform = true;
1321 int i;
1322
1323 /* Colorspace (return non-RGB formats directly). */
1324 switch (desc->colorspace) {
1325 /* Depth stencil formats */
1326 case UTIL_FORMAT_COLORSPACE_ZS:
1327 switch (format) {
1328 case PIPE_FORMAT_Z16_UNORM:
1329 return V_008F14_IMG_DATA_FORMAT_16;
1330 case PIPE_FORMAT_X24S8_UINT:
1331 case PIPE_FORMAT_Z24X8_UNORM:
1332 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1333 return V_008F14_IMG_DATA_FORMAT_8_24;
1334 case PIPE_FORMAT_X8Z24_UNORM:
1335 case PIPE_FORMAT_S8X24_UINT:
1336 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1337 return V_008F14_IMG_DATA_FORMAT_24_8;
1338 case PIPE_FORMAT_S8_UINT:
1339 return V_008F14_IMG_DATA_FORMAT_8;
1340 case PIPE_FORMAT_Z32_FLOAT:
1341 return V_008F14_IMG_DATA_FORMAT_32;
1342 case PIPE_FORMAT_X32_S8X24_UINT:
1343 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1344 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1345 default:
1346 goto out_unknown;
1347 }
1348
1349 case UTIL_FORMAT_COLORSPACE_YUV:
1350 goto out_unknown; /* TODO */
1351
1352 case UTIL_FORMAT_COLORSPACE_SRGB:
1353 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1354 goto out_unknown;
1355 break;
1356
1357 default:
1358 break;
1359 }
1360
1361 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1362 if (!enable_compressed_formats)
1363 goto out_unknown;
1364
1365 switch (format) {
1366 case PIPE_FORMAT_RGTC1_SNORM:
1367 case PIPE_FORMAT_LATC1_SNORM:
1368 case PIPE_FORMAT_RGTC1_UNORM:
1369 case PIPE_FORMAT_LATC1_UNORM:
1370 return V_008F14_IMG_DATA_FORMAT_BC4;
1371 case PIPE_FORMAT_RGTC2_SNORM:
1372 case PIPE_FORMAT_LATC2_SNORM:
1373 case PIPE_FORMAT_RGTC2_UNORM:
1374 case PIPE_FORMAT_LATC2_UNORM:
1375 return V_008F14_IMG_DATA_FORMAT_BC5;
1376 default:
1377 goto out_unknown;
1378 }
1379 }
1380
1381 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1382 sscreen->b.family == CHIP_STONEY) {
1383 switch (format) {
1384 case PIPE_FORMAT_ETC1_RGB8:
1385 case PIPE_FORMAT_ETC2_RGB8:
1386 case PIPE_FORMAT_ETC2_SRGB8:
1387 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1388 case PIPE_FORMAT_ETC2_RGB8A1:
1389 case PIPE_FORMAT_ETC2_SRGB8A1:
1390 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1391 case PIPE_FORMAT_ETC2_RGBA8:
1392 case PIPE_FORMAT_ETC2_SRGBA8:
1393 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1394 case PIPE_FORMAT_ETC2_R11_UNORM:
1395 case PIPE_FORMAT_ETC2_R11_SNORM:
1396 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1397 case PIPE_FORMAT_ETC2_RG11_UNORM:
1398 case PIPE_FORMAT_ETC2_RG11_SNORM:
1399 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1400 default:
1401 goto out_unknown;
1402 }
1403 }
1404
1405 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1406 if (!enable_compressed_formats)
1407 goto out_unknown;
1408
1409 switch (format) {
1410 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1411 case PIPE_FORMAT_BPTC_SRGBA:
1412 return V_008F14_IMG_DATA_FORMAT_BC7;
1413 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1414 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1415 return V_008F14_IMG_DATA_FORMAT_BC6;
1416 default:
1417 goto out_unknown;
1418 }
1419 }
1420
1421 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1422 switch (format) {
1423 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1424 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1425 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1426 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1427 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1428 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1429 default:
1430 goto out_unknown;
1431 }
1432 }
1433
1434 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1435 if (!enable_compressed_formats)
1436 goto out_unknown;
1437
1438 if (!util_format_s3tc_enabled) {
1439 goto out_unknown;
1440 }
1441
1442 switch (format) {
1443 case PIPE_FORMAT_DXT1_RGB:
1444 case PIPE_FORMAT_DXT1_RGBA:
1445 case PIPE_FORMAT_DXT1_SRGB:
1446 case PIPE_FORMAT_DXT1_SRGBA:
1447 return V_008F14_IMG_DATA_FORMAT_BC1;
1448 case PIPE_FORMAT_DXT3_RGBA:
1449 case PIPE_FORMAT_DXT3_SRGBA:
1450 return V_008F14_IMG_DATA_FORMAT_BC2;
1451 case PIPE_FORMAT_DXT5_RGBA:
1452 case PIPE_FORMAT_DXT5_SRGBA:
1453 return V_008F14_IMG_DATA_FORMAT_BC3;
1454 default:
1455 goto out_unknown;
1456 }
1457 }
1458
1459 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1460 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1461 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1462 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1463 }
1464
1465 /* R8G8Bx_SNORM - TODO CxV8U8 */
1466
1467 /* hw cannot support mixed formats (except depth/stencil, since only
1468 * depth is read).*/
1469 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1470 goto out_unknown;
1471
1472 /* See whether the components are of the same size. */
1473 for (i = 1; i < desc->nr_channels; i++) {
1474 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1475 }
1476
1477 /* Non-uniform formats. */
1478 if (!uniform) {
1479 switch(desc->nr_channels) {
1480 case 3:
1481 if (desc->channel[0].size == 5 &&
1482 desc->channel[1].size == 6 &&
1483 desc->channel[2].size == 5) {
1484 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1485 }
1486 goto out_unknown;
1487 case 4:
1488 if (desc->channel[0].size == 5 &&
1489 desc->channel[1].size == 5 &&
1490 desc->channel[2].size == 5 &&
1491 desc->channel[3].size == 1) {
1492 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1493 }
1494 if (desc->channel[0].size == 10 &&
1495 desc->channel[1].size == 10 &&
1496 desc->channel[2].size == 10 &&
1497 desc->channel[3].size == 2) {
1498 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1499 }
1500 goto out_unknown;
1501 }
1502 goto out_unknown;
1503 }
1504
1505 if (first_non_void < 0 || first_non_void > 3)
1506 goto out_unknown;
1507
1508 /* uniform formats */
1509 switch (desc->channel[first_non_void].size) {
1510 case 4:
1511 switch (desc->nr_channels) {
1512 #if 0 /* Not supported for render targets */
1513 case 2:
1514 return V_008F14_IMG_DATA_FORMAT_4_4;
1515 #endif
1516 case 4:
1517 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1518 }
1519 break;
1520 case 8:
1521 switch (desc->nr_channels) {
1522 case 1:
1523 return V_008F14_IMG_DATA_FORMAT_8;
1524 case 2:
1525 return V_008F14_IMG_DATA_FORMAT_8_8;
1526 case 4:
1527 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1528 }
1529 break;
1530 case 16:
1531 switch (desc->nr_channels) {
1532 case 1:
1533 return V_008F14_IMG_DATA_FORMAT_16;
1534 case 2:
1535 return V_008F14_IMG_DATA_FORMAT_16_16;
1536 case 4:
1537 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1538 }
1539 break;
1540 case 32:
1541 switch (desc->nr_channels) {
1542 case 1:
1543 return V_008F14_IMG_DATA_FORMAT_32;
1544 case 2:
1545 return V_008F14_IMG_DATA_FORMAT_32_32;
1546 #if 0 /* Not supported for render targets */
1547 case 3:
1548 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1549 #endif
1550 case 4:
1551 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1552 }
1553 }
1554
1555 out_unknown:
1556 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1557 return ~0;
1558 }
1559
1560 static unsigned si_tex_wrap(unsigned wrap)
1561 {
1562 switch (wrap) {
1563 default:
1564 case PIPE_TEX_WRAP_REPEAT:
1565 return V_008F30_SQ_TEX_WRAP;
1566 case PIPE_TEX_WRAP_CLAMP:
1567 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1568 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1569 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1570 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1571 return V_008F30_SQ_TEX_CLAMP_BORDER;
1572 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1573 return V_008F30_SQ_TEX_MIRROR;
1574 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1575 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1576 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1577 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1578 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1579 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1580 }
1581 }
1582
1583 static unsigned si_tex_mipfilter(unsigned filter)
1584 {
1585 switch (filter) {
1586 case PIPE_TEX_MIPFILTER_NEAREST:
1587 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1588 case PIPE_TEX_MIPFILTER_LINEAR:
1589 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1590 default:
1591 case PIPE_TEX_MIPFILTER_NONE:
1592 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1593 }
1594 }
1595
1596 static unsigned si_tex_compare(unsigned compare)
1597 {
1598 switch (compare) {
1599 default:
1600 case PIPE_FUNC_NEVER:
1601 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1602 case PIPE_FUNC_LESS:
1603 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1604 case PIPE_FUNC_EQUAL:
1605 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1606 case PIPE_FUNC_LEQUAL:
1607 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1608 case PIPE_FUNC_GREATER:
1609 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1610 case PIPE_FUNC_NOTEQUAL:
1611 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1612 case PIPE_FUNC_GEQUAL:
1613 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1614 case PIPE_FUNC_ALWAYS:
1615 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1616 }
1617 }
1618
1619 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1620 unsigned nr_samples)
1621 {
1622 if (view_target == PIPE_TEXTURE_CUBE ||
1623 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1624 res_target = view_target;
1625 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1626 else if (res_target == PIPE_TEXTURE_CUBE ||
1627 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1628 res_target = PIPE_TEXTURE_2D_ARRAY;
1629
1630 switch (res_target) {
1631 default:
1632 case PIPE_TEXTURE_1D:
1633 return V_008F1C_SQ_RSRC_IMG_1D;
1634 case PIPE_TEXTURE_1D_ARRAY:
1635 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1636 case PIPE_TEXTURE_2D:
1637 case PIPE_TEXTURE_RECT:
1638 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1639 V_008F1C_SQ_RSRC_IMG_2D;
1640 case PIPE_TEXTURE_2D_ARRAY:
1641 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1642 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1643 case PIPE_TEXTURE_3D:
1644 return V_008F1C_SQ_RSRC_IMG_3D;
1645 case PIPE_TEXTURE_CUBE:
1646 case PIPE_TEXTURE_CUBE_ARRAY:
1647 return V_008F1C_SQ_RSRC_IMG_CUBE;
1648 }
1649 }
1650
1651 /*
1652 * Format support testing
1653 */
1654
1655 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1656 {
1657 return si_translate_texformat(screen, format, util_format_description(format),
1658 util_format_get_first_non_void_channel(format)) != ~0U;
1659 }
1660
1661 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1662 const struct util_format_description *desc,
1663 int first_non_void)
1664 {
1665 unsigned type;
1666 int i;
1667
1668 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1669 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1670
1671 assert(first_non_void >= 0);
1672 type = desc->channel[first_non_void].type;
1673
1674 if (type == UTIL_FORMAT_TYPE_FIXED)
1675 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1676
1677 if (desc->nr_channels == 4 &&
1678 desc->channel[0].size == 10 &&
1679 desc->channel[1].size == 10 &&
1680 desc->channel[2].size == 10 &&
1681 desc->channel[3].size == 2)
1682 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1683
1684 /* See whether the components are of the same size. */
1685 for (i = 0; i < desc->nr_channels; i++) {
1686 if (desc->channel[first_non_void].size != desc->channel[i].size)
1687 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1688 }
1689
1690 switch (desc->channel[first_non_void].size) {
1691 case 8:
1692 switch (desc->nr_channels) {
1693 case 1:
1694 return V_008F0C_BUF_DATA_FORMAT_8;
1695 case 2:
1696 return V_008F0C_BUF_DATA_FORMAT_8_8;
1697 case 3:
1698 case 4:
1699 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1700 }
1701 break;
1702 case 16:
1703 switch (desc->nr_channels) {
1704 case 1:
1705 return V_008F0C_BUF_DATA_FORMAT_16;
1706 case 2:
1707 return V_008F0C_BUF_DATA_FORMAT_16_16;
1708 case 3:
1709 case 4:
1710 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1711 }
1712 break;
1713 case 32:
1714 /* From the Southern Islands ISA documentation about MTBUF:
1715 * 'Memory reads of data in memory that is 32 or 64 bits do not
1716 * undergo any format conversion.'
1717 */
1718 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1719 !desc->channel[first_non_void].pure_integer)
1720 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1721
1722 switch (desc->nr_channels) {
1723 case 1:
1724 return V_008F0C_BUF_DATA_FORMAT_32;
1725 case 2:
1726 return V_008F0C_BUF_DATA_FORMAT_32_32;
1727 case 3:
1728 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1729 case 4:
1730 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1731 }
1732 break;
1733 }
1734
1735 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1736 }
1737
1738 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1739 const struct util_format_description *desc,
1740 int first_non_void)
1741 {
1742 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1743 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1744
1745 assert(first_non_void >= 0);
1746
1747 switch (desc->channel[first_non_void].type) {
1748 case UTIL_FORMAT_TYPE_SIGNED:
1749 if (desc->channel[first_non_void].normalized)
1750 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1751 else if (desc->channel[first_non_void].pure_integer)
1752 return V_008F0C_BUF_NUM_FORMAT_SINT;
1753 else
1754 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1755 break;
1756 case UTIL_FORMAT_TYPE_UNSIGNED:
1757 if (desc->channel[first_non_void].normalized)
1758 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1759 else if (desc->channel[first_non_void].pure_integer)
1760 return V_008F0C_BUF_NUM_FORMAT_UINT;
1761 else
1762 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1763 break;
1764 case UTIL_FORMAT_TYPE_FLOAT:
1765 default:
1766 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1767 }
1768 }
1769
1770 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1771 {
1772 const struct util_format_description *desc;
1773 int first_non_void;
1774 unsigned data_format;
1775
1776 desc = util_format_description(format);
1777 first_non_void = util_format_get_first_non_void_channel(format);
1778 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1779 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1780 }
1781
1782 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1783 {
1784 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1785 r600_translate_colorswap(format, false) != ~0U;
1786 }
1787
1788 static bool si_is_zs_format_supported(enum pipe_format format)
1789 {
1790 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1791 }
1792
1793 static boolean si_is_format_supported(struct pipe_screen *screen,
1794 enum pipe_format format,
1795 enum pipe_texture_target target,
1796 unsigned sample_count,
1797 unsigned usage)
1798 {
1799 unsigned retval = 0;
1800
1801 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1802 R600_ERR("r600: unsupported texture type %d\n", target);
1803 return false;
1804 }
1805
1806 if (!util_format_is_supported(format, usage))
1807 return false;
1808
1809 if (sample_count > 1) {
1810 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1811 return false;
1812
1813 if (usage & PIPE_BIND_SHADER_IMAGE)
1814 return false;
1815
1816 switch (sample_count) {
1817 case 2:
1818 case 4:
1819 case 8:
1820 break;
1821 case 16:
1822 if (format == PIPE_FORMAT_NONE)
1823 return true;
1824 else
1825 return false;
1826 default:
1827 return false;
1828 }
1829 }
1830
1831 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1832 PIPE_BIND_SHADER_IMAGE)) {
1833 if (target == PIPE_BUFFER) {
1834 if (si_is_vertex_format_supported(screen, format))
1835 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1836 PIPE_BIND_SHADER_IMAGE);
1837 } else {
1838 if (si_is_sampler_format_supported(screen, format))
1839 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1840 PIPE_BIND_SHADER_IMAGE);
1841 }
1842 }
1843
1844 if ((usage & (PIPE_BIND_RENDER_TARGET |
1845 PIPE_BIND_DISPLAY_TARGET |
1846 PIPE_BIND_SCANOUT |
1847 PIPE_BIND_SHARED |
1848 PIPE_BIND_BLENDABLE)) &&
1849 si_is_colorbuffer_format_supported(format)) {
1850 retval |= usage &
1851 (PIPE_BIND_RENDER_TARGET |
1852 PIPE_BIND_DISPLAY_TARGET |
1853 PIPE_BIND_SCANOUT |
1854 PIPE_BIND_SHARED);
1855 if (!util_format_is_pure_integer(format) &&
1856 !util_format_is_depth_or_stencil(format))
1857 retval |= usage & PIPE_BIND_BLENDABLE;
1858 }
1859
1860 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1861 si_is_zs_format_supported(format)) {
1862 retval |= PIPE_BIND_DEPTH_STENCIL;
1863 }
1864
1865 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1866 si_is_vertex_format_supported(screen, format)) {
1867 retval |= PIPE_BIND_VERTEX_BUFFER;
1868 }
1869
1870 if ((usage & PIPE_BIND_LINEAR) &&
1871 !util_format_is_compressed(format) &&
1872 !(usage & PIPE_BIND_DEPTH_STENCIL))
1873 retval |= PIPE_BIND_LINEAR;
1874
1875 return retval == usage;
1876 }
1877
1878 /*
1879 * framebuffer handling
1880 */
1881
1882 static void si_choose_spi_color_formats(struct r600_surface *surf,
1883 unsigned format, unsigned swap,
1884 unsigned ntype, bool is_depth)
1885 {
1886 /* Alpha is needed for alpha-to-coverage.
1887 * Blending may be with or without alpha.
1888 */
1889 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1890 unsigned alpha = 0; /* exports alpha, but may not support blending */
1891 unsigned blend = 0; /* supports blending, but may not export alpha */
1892 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1893
1894 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1895 * Other chips have multiple choices, though they are not necessarily better.
1896 */
1897 switch (format) {
1898 case V_028C70_COLOR_5_6_5:
1899 case V_028C70_COLOR_1_5_5_5:
1900 case V_028C70_COLOR_5_5_5_1:
1901 case V_028C70_COLOR_4_4_4_4:
1902 case V_028C70_COLOR_10_11_11:
1903 case V_028C70_COLOR_11_11_10:
1904 case V_028C70_COLOR_8:
1905 case V_028C70_COLOR_8_8:
1906 case V_028C70_COLOR_8_8_8_8:
1907 case V_028C70_COLOR_10_10_10_2:
1908 case V_028C70_COLOR_2_10_10_10:
1909 if (ntype == V_028C70_NUMBER_UINT)
1910 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1911 else if (ntype == V_028C70_NUMBER_SINT)
1912 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1913 else
1914 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1915 break;
1916
1917 case V_028C70_COLOR_16:
1918 case V_028C70_COLOR_16_16:
1919 case V_028C70_COLOR_16_16_16_16:
1920 if (ntype == V_028C70_NUMBER_UNORM ||
1921 ntype == V_028C70_NUMBER_SNORM) {
1922 /* UNORM16 and SNORM16 don't support blending */
1923 if (ntype == V_028C70_NUMBER_UNORM)
1924 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1925 else
1926 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1927
1928 /* Use 32 bits per channel for blending. */
1929 if (format == V_028C70_COLOR_16) {
1930 if (swap == V_028C70_SWAP_STD) { /* R */
1931 blend = V_028714_SPI_SHADER_32_R;
1932 blend_alpha = V_028714_SPI_SHADER_32_AR;
1933 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1934 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1935 else
1936 assert(0);
1937 } else if (format == V_028C70_COLOR_16_16) {
1938 if (swap == V_028C70_SWAP_STD) { /* RG */
1939 blend = V_028714_SPI_SHADER_32_GR;
1940 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1941 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1942 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1943 else
1944 assert(0);
1945 } else /* 16_16_16_16 */
1946 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1947 } else if (ntype == V_028C70_NUMBER_UINT)
1948 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1949 else if (ntype == V_028C70_NUMBER_SINT)
1950 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1951 else if (ntype == V_028C70_NUMBER_FLOAT)
1952 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1953 else
1954 assert(0);
1955 break;
1956
1957 case V_028C70_COLOR_32:
1958 if (swap == V_028C70_SWAP_STD) { /* R */
1959 blend = normal = V_028714_SPI_SHADER_32_R;
1960 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1961 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1962 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1963 else
1964 assert(0);
1965 break;
1966
1967 case V_028C70_COLOR_32_32:
1968 if (swap == V_028C70_SWAP_STD) { /* RG */
1969 blend = normal = V_028714_SPI_SHADER_32_GR;
1970 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1971 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1972 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1973 else
1974 assert(0);
1975 break;
1976
1977 case V_028C70_COLOR_32_32_32_32:
1978 case V_028C70_COLOR_8_24:
1979 case V_028C70_COLOR_24_8:
1980 case V_028C70_COLOR_X24_8_32_FLOAT:
1981 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1982 break;
1983
1984 default:
1985 assert(0);
1986 return;
1987 }
1988
1989 /* The DB->CB copy needs 32_ABGR. */
1990 if (is_depth)
1991 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1992
1993 surf->spi_shader_col_format = normal;
1994 surf->spi_shader_col_format_alpha = alpha;
1995 surf->spi_shader_col_format_blend = blend;
1996 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1997 }
1998
1999 static void si_initialize_color_surface(struct si_context *sctx,
2000 struct r600_surface *surf)
2001 {
2002 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2003 unsigned color_info, color_attrib, color_view;
2004 unsigned format, swap, ntype, endian;
2005 const struct util_format_description *desc;
2006 int i;
2007 unsigned blend_clamp = 0, blend_bypass = 0;
2008
2009 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2010 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2011
2012 desc = util_format_description(surf->base.format);
2013 for (i = 0; i < 4; i++) {
2014 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2015 break;
2016 }
2017 }
2018 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2019 ntype = V_028C70_NUMBER_FLOAT;
2020 } else {
2021 ntype = V_028C70_NUMBER_UNORM;
2022 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2023 ntype = V_028C70_NUMBER_SRGB;
2024 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2025 if (desc->channel[i].pure_integer) {
2026 ntype = V_028C70_NUMBER_SINT;
2027 } else {
2028 assert(desc->channel[i].normalized);
2029 ntype = V_028C70_NUMBER_SNORM;
2030 }
2031 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2032 if (desc->channel[i].pure_integer) {
2033 ntype = V_028C70_NUMBER_UINT;
2034 } else {
2035 assert(desc->channel[i].normalized);
2036 ntype = V_028C70_NUMBER_UNORM;
2037 }
2038 }
2039 }
2040
2041 format = si_translate_colorformat(surf->base.format);
2042 if (format == V_028C70_COLOR_INVALID) {
2043 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2044 }
2045 assert(format != V_028C70_COLOR_INVALID);
2046 swap = r600_translate_colorswap(surf->base.format, false);
2047 endian = si_colorformat_endian_swap(format);
2048
2049 /* blend clamp should be set for all NORM/SRGB types */
2050 if (ntype == V_028C70_NUMBER_UNORM ||
2051 ntype == V_028C70_NUMBER_SNORM ||
2052 ntype == V_028C70_NUMBER_SRGB)
2053 blend_clamp = 1;
2054
2055 /* set blend bypass according to docs if SINT/UINT or
2056 8/24 COLOR variants */
2057 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2058 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2059 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2060 blend_clamp = 0;
2061 blend_bypass = 1;
2062 }
2063
2064 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2065 (format == V_028C70_COLOR_8 ||
2066 format == V_028C70_COLOR_8_8 ||
2067 format == V_028C70_COLOR_8_8_8_8))
2068 surf->color_is_int8 = true;
2069
2070 color_info = S_028C70_FORMAT(format) |
2071 S_028C70_COMP_SWAP(swap) |
2072 S_028C70_BLEND_CLAMP(blend_clamp) |
2073 S_028C70_BLEND_BYPASS(blend_bypass) |
2074 S_028C70_SIMPLE_FLOAT(1) |
2075 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2076 ntype != V_028C70_NUMBER_SNORM &&
2077 ntype != V_028C70_NUMBER_SRGB &&
2078 format != V_028C70_COLOR_8_24 &&
2079 format != V_028C70_COLOR_24_8) |
2080 S_028C70_NUMBER_TYPE(ntype) |
2081 S_028C70_ENDIAN(endian);
2082
2083 /* Intensity is implemented as Red, so treat it that way. */
2084 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2085 util_format_is_intensity(surf->base.format));
2086
2087 if (rtex->resource.b.b.nr_samples > 1) {
2088 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2089
2090 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2091 S_028C74_NUM_FRAGMENTS(log_samples);
2092
2093 if (rtex->fmask.size) {
2094 color_info |= S_028C70_COMPRESSION(1);
2095 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2096
2097 if (sctx->b.chip_class == SI) {
2098 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2099 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2100 }
2101 }
2102 }
2103
2104 surf->cb_color_view = color_view;
2105 surf->cb_color_info = color_info;
2106 surf->cb_color_attrib = color_attrib;
2107
2108 if (sctx->b.chip_class >= VI) {
2109 unsigned max_uncompressed_block_size = 2;
2110
2111 if (rtex->surface.nsamples > 1) {
2112 if (rtex->surface.bpe == 1)
2113 max_uncompressed_block_size = 0;
2114 else if (rtex->surface.bpe == 2)
2115 max_uncompressed_block_size = 1;
2116 }
2117
2118 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2119 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2120 }
2121
2122 /* This must be set for fast clear to work without FMASK. */
2123 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2124 unsigned bankh = util_logbase2(rtex->surface.bankh);
2125 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2126 }
2127
2128 /* Determine pixel shader export format */
2129 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2130
2131 surf->color_initialized = true;
2132 }
2133
2134 static void si_init_depth_surface(struct si_context *sctx,
2135 struct r600_surface *surf)
2136 {
2137 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2138 unsigned level = surf->base.u.tex.level;
2139 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2140 unsigned format;
2141 uint32_t z_info, s_info, db_depth_info;
2142 uint64_t z_offs, s_offs;
2143 uint32_t db_htile_data_base, db_htile_surface;
2144
2145 format = si_translate_dbformat(rtex->resource.b.b.format);
2146
2147 if (format == V_028040_Z_INVALID) {
2148 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2149 }
2150 assert(format != V_028040_Z_INVALID);
2151
2152 s_offs = z_offs = rtex->resource.gpu_address;
2153 z_offs += rtex->surface.level[level].offset;
2154 s_offs += rtex->surface.stencil_level[level].offset;
2155
2156 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2157
2158 z_info = S_028040_FORMAT(format);
2159 if (rtex->resource.b.b.nr_samples > 1) {
2160 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2161 }
2162
2163 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2164 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2165 else
2166 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2167
2168 if (sctx->b.chip_class >= CIK) {
2169 struct radeon_info *info = &sctx->screen->b.info;
2170 unsigned index = rtex->surface.tiling_index[level];
2171 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2172 unsigned macro_index = rtex->surface.macro_tile_index;
2173 unsigned tile_mode = info->si_tile_mode_array[index];
2174 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2175 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2176
2177 db_depth_info |=
2178 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2179 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2180 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2181 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2182 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2183 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2184 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2185 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2186 } else {
2187 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2188 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2189 tile_mode_index = si_tile_mode_index(rtex, level, true);
2190 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2191 }
2192
2193 /* HiZ aka depth buffer htile */
2194 /* use htile only for first level */
2195 if (rtex->htile_buffer && !level) {
2196 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2197 S_028040_ALLOW_EXPCLEAR(1);
2198
2199 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2200 /* Workaround: For a not yet understood reason, the
2201 * combination of MSAA, fast stencil clear and stencil
2202 * decompress messes with subsequent stencil buffer
2203 * uses. Problem was reproduced on Verde, Bonaire,
2204 * Tonga, and Carrizo.
2205 *
2206 * Disabling EXPCLEAR works around the problem.
2207 *
2208 * Check piglit's arb_texture_multisample-stencil-clear
2209 * test if you want to try changing this.
2210 */
2211 if (rtex->resource.b.b.nr_samples <= 1)
2212 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2213 } else
2214 /* Use all of the htile_buffer for depth if there's no stencil. */
2215 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2216
2217 uint64_t va = rtex->htile_buffer->gpu_address;
2218 db_htile_data_base = va >> 8;
2219 db_htile_surface = S_028ABC_FULL_CACHE(1);
2220 } else {
2221 db_htile_data_base = 0;
2222 db_htile_surface = 0;
2223 }
2224
2225 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2226
2227 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2228 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2229 surf->db_htile_data_base = db_htile_data_base;
2230 surf->db_depth_info = db_depth_info;
2231 surf->db_z_info = z_info;
2232 surf->db_stencil_info = s_info;
2233 surf->db_depth_base = z_offs >> 8;
2234 surf->db_stencil_base = s_offs >> 8;
2235 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2236 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2237 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2238 levelinfo->nblk_y) / 64 - 1);
2239 surf->db_htile_surface = db_htile_surface;
2240
2241 surf->depth_initialized = true;
2242 }
2243
2244 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2245 {
2246 for (int i = 0; i < state->nr_cbufs; ++i) {
2247 struct r600_surface *surf = NULL;
2248 struct r600_texture *rtex;
2249
2250 if (!state->cbufs[i])
2251 continue;
2252 surf = (struct r600_surface*)state->cbufs[i];
2253 rtex = (struct r600_texture*)surf->base.texture;
2254
2255 p_atomic_dec(&rtex->framebuffers_bound);
2256 }
2257 }
2258
2259 static void si_set_framebuffer_state(struct pipe_context *ctx,
2260 const struct pipe_framebuffer_state *state)
2261 {
2262 struct si_context *sctx = (struct si_context *)ctx;
2263 struct pipe_constant_buffer constbuf = {0};
2264 struct r600_surface *surf = NULL;
2265 struct r600_texture *rtex;
2266 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2267 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2268 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2269 int i;
2270
2271 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2272 if (!sctx->framebuffer.state.cbufs[i])
2273 continue;
2274
2275 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2276 if (rtex->dcc_gather_statistics)
2277 vi_separate_dcc_stop_query(ctx, rtex);
2278 }
2279
2280 /* Only flush TC when changing the framebuffer state, because
2281 * the only client not using TC that can change textures is
2282 * the framebuffer.
2283 *
2284 * Flush all CB and DB caches here because all buffers can be used
2285 * for write by both TC (with shader image stores) and CB/DB.
2286 */
2287 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2288 SI_CONTEXT_INV_GLOBAL_L2 |
2289 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2290 SI_CONTEXT_CS_PARTIAL_FLUSH;
2291
2292 /* Take the maximum of the old and new count. If the new count is lower,
2293 * dirtying is needed to disable the unbound colorbuffers.
2294 */
2295 sctx->framebuffer.dirty_cbufs |=
2296 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2297 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2298
2299 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2300 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2301
2302 sctx->framebuffer.spi_shader_col_format = 0;
2303 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2304 sctx->framebuffer.spi_shader_col_format_blend = 0;
2305 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2306 sctx->framebuffer.color_is_int8 = 0;
2307
2308 sctx->framebuffer.compressed_cb_mask = 0;
2309 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2310 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2311 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2312 util_format_is_pure_integer(state->cbufs[0]->format);
2313 sctx->framebuffer.any_dst_linear = false;
2314
2315 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2316 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2317
2318 for (i = 0; i < state->nr_cbufs; i++) {
2319 if (!state->cbufs[i])
2320 continue;
2321
2322 surf = (struct r600_surface*)state->cbufs[i];
2323 rtex = (struct r600_texture*)surf->base.texture;
2324
2325 if (!surf->color_initialized) {
2326 si_initialize_color_surface(sctx, surf);
2327 }
2328
2329 sctx->framebuffer.spi_shader_col_format |=
2330 surf->spi_shader_col_format << (i * 4);
2331 sctx->framebuffer.spi_shader_col_format_alpha |=
2332 surf->spi_shader_col_format_alpha << (i * 4);
2333 sctx->framebuffer.spi_shader_col_format_blend |=
2334 surf->spi_shader_col_format_blend << (i * 4);
2335 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2336 surf->spi_shader_col_format_blend_alpha << (i * 4);
2337
2338 if (surf->color_is_int8)
2339 sctx->framebuffer.color_is_int8 |= 1 << i;
2340
2341 if (rtex->fmask.size && rtex->cmask.size) {
2342 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2343 }
2344
2345 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2346 sctx->framebuffer.any_dst_linear = true;
2347
2348 r600_context_add_resource_size(ctx, surf->base.texture);
2349
2350 p_atomic_inc(&rtex->framebuffers_bound);
2351
2352 if (rtex->dcc_gather_statistics) {
2353 /* Dirty tracking must be enabled for DCC usage analysis. */
2354 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2355 vi_separate_dcc_start_query(ctx, rtex);
2356 }
2357 }
2358
2359 if (state->zsbuf) {
2360 surf = (struct r600_surface*)state->zsbuf;
2361
2362 if (!surf->depth_initialized) {
2363 si_init_depth_surface(sctx, surf);
2364 }
2365 r600_context_add_resource_size(ctx, surf->base.texture);
2366 }
2367
2368 si_update_poly_offset_state(sctx);
2369 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2370 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2371
2372 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2373 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2374
2375 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2376 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2377 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2378
2379 /* Set sample locations as fragment shader constants. */
2380 switch (sctx->framebuffer.nr_samples) {
2381 case 1:
2382 constbuf.user_buffer = sctx->b.sample_locations_1x;
2383 break;
2384 case 2:
2385 constbuf.user_buffer = sctx->b.sample_locations_2x;
2386 break;
2387 case 4:
2388 constbuf.user_buffer = sctx->b.sample_locations_4x;
2389 break;
2390 case 8:
2391 constbuf.user_buffer = sctx->b.sample_locations_8x;
2392 break;
2393 case 16:
2394 constbuf.user_buffer = sctx->b.sample_locations_16x;
2395 break;
2396 default:
2397 R600_ERR("Requested an invalid number of samples %i.\n",
2398 sctx->framebuffer.nr_samples);
2399 assert(0);
2400 }
2401 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2402 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2403
2404 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2405 }
2406
2407 sctx->need_check_render_feedback = true;
2408 sctx->do_update_shaders = true;
2409 }
2410
2411 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2412 {
2413 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2414 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2415 unsigned i, nr_cbufs = state->nr_cbufs;
2416 struct r600_texture *tex = NULL;
2417 struct r600_surface *cb = NULL;
2418 unsigned cb_color_info = 0;
2419
2420 /* Colorbuffers. */
2421 for (i = 0; i < nr_cbufs; i++) {
2422 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2423 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2424 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2425
2426 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2427 continue;
2428
2429 cb = (struct r600_surface*)state->cbufs[i];
2430 if (!cb) {
2431 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2432 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2433 continue;
2434 }
2435
2436 tex = (struct r600_texture *)cb->base.texture;
2437 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2438 &tex->resource, RADEON_USAGE_READWRITE,
2439 tex->surface.nsamples > 1 ?
2440 RADEON_PRIO_COLOR_BUFFER_MSAA :
2441 RADEON_PRIO_COLOR_BUFFER);
2442
2443 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2444 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2445 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2446 RADEON_PRIO_CMASK);
2447 }
2448
2449 if (tex->dcc_separate_buffer)
2450 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2451 tex->dcc_separate_buffer,
2452 RADEON_USAGE_READWRITE,
2453 RADEON_PRIO_DCC);
2454
2455 /* Compute mutable surface parameters. */
2456 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2457 slice_tile_max = cb->level_info->nblk_x *
2458 cb->level_info->nblk_y / 64 - 1;
2459 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2460
2461 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2462 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2463 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2464 cb_color_attrib = cb->cb_color_attrib |
2465 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2466
2467 if (tex->fmask.size) {
2468 if (sctx->b.chip_class >= CIK)
2469 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2470 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2471 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2472 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2473 } else {
2474 /* This must be set for fast clear to work without FMASK. */
2475 if (sctx->b.chip_class >= CIK)
2476 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2477 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2478 cb_color_fmask = cb_color_base;
2479 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2480 }
2481
2482 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2483
2484 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2485 bool is_msaa_resolve_dst = state->cbufs[0] &&
2486 state->cbufs[0]->texture->nr_samples > 1 &&
2487 state->cbufs[1] == &cb->base &&
2488 state->cbufs[1]->texture->nr_samples <= 1;
2489
2490 if (!is_msaa_resolve_dst)
2491 cb_color_info |= S_028C70_DCC_ENABLE(1);
2492 }
2493
2494 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2495 sctx->b.chip_class >= VI ? 14 : 13);
2496 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2497 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2498 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2499 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2500 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2501 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2502 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2503 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2504 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2505 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2506 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2507 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2508 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2509
2510 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2511 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2512 tex->dcc_offset +
2513 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2514 }
2515 for (; i < 8 ; i++)
2516 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2517 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2518
2519 /* ZS buffer. */
2520 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2521 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2522 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2523
2524 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2525 &rtex->resource, RADEON_USAGE_READWRITE,
2526 zb->base.texture->nr_samples > 1 ?
2527 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2528 RADEON_PRIO_DEPTH_BUFFER);
2529
2530 if (zb->db_htile_data_base) {
2531 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2532 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2533 RADEON_PRIO_HTILE);
2534 }
2535
2536 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2537 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2538
2539 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2540 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2541 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2542 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2543 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2544 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2545 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2546 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2547 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2548 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2549 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2550
2551 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2552 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2553 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2554
2555 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2556 } else if (sctx->framebuffer.dirty_zsbuf) {
2557 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2558 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2559 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2560 }
2561
2562 /* Framebuffer dimensions. */
2563 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2564 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2565 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2566
2567 sctx->framebuffer.dirty_cbufs = 0;
2568 sctx->framebuffer.dirty_zsbuf = false;
2569 }
2570
2571 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2572 struct r600_atom *atom)
2573 {
2574 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2575 unsigned nr_samples = sctx->framebuffer.nr_samples;
2576
2577 /* Smoothing (only possible with nr_samples == 1) uses the same
2578 * sample locations as the MSAA it simulates.
2579 */
2580 if (nr_samples <= 1 && sctx->smoothing_enabled)
2581 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2582
2583 /* On Polaris, the small primitive filter uses the sample locations
2584 * even when MSAA is off, so we need to make sure they're set to 0.
2585 */
2586 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2587 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2588 sctx->msaa_sample_locs.nr_samples = nr_samples;
2589 cayman_emit_msaa_sample_locs(cs, nr_samples);
2590 }
2591
2592 if (sctx->b.family >= CHIP_POLARIS10) {
2593 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2594 unsigned small_prim_filter_cntl =
2595 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2596 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2597
2598 /* The alternative of setting sample locations to 0 would
2599 * require a DB flush to avoid Z errors, see
2600 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2601 */
2602 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2603 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2604
2605 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2606 small_prim_filter_cntl);
2607 }
2608 }
2609
2610 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2611 {
2612 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2613 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2614 /* 33% faster rendering to linear color buffers */
2615 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2616 unsigned sc_mode_cntl_1 =
2617 S_028A4C_WALK_SIZE(dst_is_linear) |
2618 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2619 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2620 /* always 1: */
2621 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2622 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2623 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2624 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2625 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2626 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2627
2628 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2629 sctx->ps_iter_samples,
2630 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2631 sc_mode_cntl_1);
2632 }
2633
2634 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2635 {
2636 struct si_context *sctx = (struct si_context *)ctx;
2637
2638 if (sctx->ps_iter_samples == min_samples)
2639 return;
2640
2641 sctx->ps_iter_samples = min_samples;
2642 sctx->do_update_shaders = true;
2643
2644 if (sctx->framebuffer.nr_samples > 1)
2645 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2646 }
2647
2648 /*
2649 * Samplers
2650 */
2651
2652 /**
2653 * Build the sampler view descriptor for a buffer texture.
2654 * @param state 256-bit descriptor; only the high 128 bits are filled in
2655 */
2656 void
2657 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2658 enum pipe_format format,
2659 unsigned offset, unsigned size,
2660 uint32_t *state)
2661 {
2662 const struct util_format_description *desc;
2663 int first_non_void;
2664 uint64_t va;
2665 unsigned stride;
2666 unsigned num_records;
2667 unsigned num_format, data_format;
2668
2669 desc = util_format_description(format);
2670 first_non_void = util_format_get_first_non_void_channel(format);
2671 stride = desc->block.bits / 8;
2672 va = buf->gpu_address + offset;
2673 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2674 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2675
2676 num_records = size / stride;
2677 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2678
2679 if (screen->b.chip_class >= VI)
2680 num_records *= stride;
2681
2682 state[4] = va;
2683 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2684 S_008F04_STRIDE(stride);
2685 state[6] = num_records;
2686 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2687 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2688 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2689 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2690 S_008F0C_NUM_FORMAT(num_format) |
2691 S_008F0C_DATA_FORMAT(data_format);
2692 }
2693
2694 /**
2695 * Build the sampler view descriptor for a texture.
2696 */
2697 void
2698 si_make_texture_descriptor(struct si_screen *screen,
2699 struct r600_texture *tex,
2700 bool sampler,
2701 enum pipe_texture_target target,
2702 enum pipe_format pipe_format,
2703 const unsigned char state_swizzle[4],
2704 unsigned first_level, unsigned last_level,
2705 unsigned first_layer, unsigned last_layer,
2706 unsigned width, unsigned height, unsigned depth,
2707 uint32_t *state,
2708 uint32_t *fmask_state)
2709 {
2710 struct pipe_resource *res = &tex->resource.b.b;
2711 const struct util_format_description *desc;
2712 unsigned char swizzle[4];
2713 int first_non_void;
2714 unsigned num_format, data_format, type;
2715 uint64_t va;
2716
2717 desc = util_format_description(pipe_format);
2718
2719 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2720 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2721 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2722
2723 switch (pipe_format) {
2724 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2725 case PIPE_FORMAT_X24S8_UINT:
2726 case PIPE_FORMAT_X32_S8X24_UINT:
2727 case PIPE_FORMAT_X8Z24_UNORM:
2728 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2729 break;
2730 default:
2731 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2732 }
2733 } else {
2734 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2735 }
2736
2737 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2738
2739 switch (pipe_format) {
2740 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2741 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2742 break;
2743 default:
2744 if (first_non_void < 0) {
2745 if (util_format_is_compressed(pipe_format)) {
2746 switch (pipe_format) {
2747 case PIPE_FORMAT_DXT1_SRGB:
2748 case PIPE_FORMAT_DXT1_SRGBA:
2749 case PIPE_FORMAT_DXT3_SRGBA:
2750 case PIPE_FORMAT_DXT5_SRGBA:
2751 case PIPE_FORMAT_BPTC_SRGBA:
2752 case PIPE_FORMAT_ETC2_SRGB8:
2753 case PIPE_FORMAT_ETC2_SRGB8A1:
2754 case PIPE_FORMAT_ETC2_SRGBA8:
2755 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2756 break;
2757 case PIPE_FORMAT_RGTC1_SNORM:
2758 case PIPE_FORMAT_LATC1_SNORM:
2759 case PIPE_FORMAT_RGTC2_SNORM:
2760 case PIPE_FORMAT_LATC2_SNORM:
2761 case PIPE_FORMAT_ETC2_R11_SNORM:
2762 case PIPE_FORMAT_ETC2_RG11_SNORM:
2763 /* implies float, so use SNORM/UNORM to determine
2764 whether data is signed or not */
2765 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2766 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2767 break;
2768 default:
2769 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2770 break;
2771 }
2772 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2773 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2774 } else {
2775 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2776 }
2777 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2778 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2779 } else {
2780 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2781
2782 switch (desc->channel[first_non_void].type) {
2783 case UTIL_FORMAT_TYPE_FLOAT:
2784 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2785 break;
2786 case UTIL_FORMAT_TYPE_SIGNED:
2787 if (desc->channel[first_non_void].normalized)
2788 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2789 else if (desc->channel[first_non_void].pure_integer)
2790 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2791 else
2792 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2793 break;
2794 case UTIL_FORMAT_TYPE_UNSIGNED:
2795 if (desc->channel[first_non_void].normalized)
2796 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2797 else if (desc->channel[first_non_void].pure_integer)
2798 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2799 else
2800 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2801 }
2802 }
2803 }
2804
2805 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2806 if (data_format == ~0) {
2807 data_format = 0;
2808 }
2809
2810 if (!sampler &&
2811 (res->target == PIPE_TEXTURE_CUBE ||
2812 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2813 res->target == PIPE_TEXTURE_3D)) {
2814 /* For the purpose of shader images, treat cube maps and 3D
2815 * textures as 2D arrays. For 3D textures, the address
2816 * calculations for mipmaps are different, so we rely on the
2817 * caller to effectively disable mipmaps.
2818 */
2819 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2820
2821 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2822 } else {
2823 type = si_tex_dim(res->target, target, res->nr_samples);
2824 }
2825
2826 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2827 height = 1;
2828 depth = res->array_size;
2829 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2830 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2831 if (sampler || res->target != PIPE_TEXTURE_3D)
2832 depth = res->array_size;
2833 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2834 depth = res->array_size / 6;
2835
2836 state[0] = 0;
2837 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2838 S_008F14_NUM_FORMAT(num_format));
2839 state[2] = (S_008F18_WIDTH(width - 1) |
2840 S_008F18_HEIGHT(height - 1) |
2841 S_008F18_PERF_MOD(4));
2842 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2843 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2844 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2845 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2846 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2847 0 : first_level) |
2848 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2849 util_logbase2(res->nr_samples) :
2850 last_level) |
2851 S_008F1C_POW2_PAD(res->last_level > 0) |
2852 S_008F1C_TYPE(type));
2853 state[4] = S_008F20_DEPTH(depth - 1);
2854 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2855 S_008F24_LAST_ARRAY(last_layer));
2856 state[6] = 0;
2857 state[7] = 0;
2858
2859 if (tex->dcc_offset) {
2860 unsigned swap = r600_translate_colorswap(pipe_format, false);
2861
2862 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2863 } else {
2864 /* The last dword is unused by hw. The shader uses it to clear
2865 * bits in the first dword of sampler state.
2866 */
2867 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2868 if (first_level == last_level)
2869 state[7] = C_008F30_MAX_ANISO_RATIO;
2870 else
2871 state[7] = 0xffffffff;
2872 }
2873 }
2874
2875 /* Initialize the sampler view for FMASK. */
2876 if (tex->fmask.size) {
2877 uint32_t fmask_format;
2878
2879 va = tex->resource.gpu_address + tex->fmask.offset;
2880
2881 switch (res->nr_samples) {
2882 case 2:
2883 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2884 break;
2885 case 4:
2886 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2887 break;
2888 case 8:
2889 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2890 break;
2891 default:
2892 assert(0);
2893 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2894 }
2895
2896 fmask_state[0] = va >> 8;
2897 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2898 S_008F14_DATA_FORMAT(fmask_format) |
2899 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2900 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2901 S_008F18_HEIGHT(height - 1);
2902 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2903 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2904 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2905 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2906 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2907 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2908 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2909 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2910 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2911 S_008F24_LAST_ARRAY(last_layer);
2912 fmask_state[6] = 0;
2913 fmask_state[7] = 0;
2914 }
2915 }
2916
2917 /**
2918 * Create a sampler view.
2919 *
2920 * @param ctx context
2921 * @param texture texture
2922 * @param state sampler view template
2923 * @param width0 width0 override (for compressed textures as int)
2924 * @param height0 height0 override (for compressed textures as int)
2925 * @param force_level set the base address to the level (for compressed textures)
2926 */
2927 struct pipe_sampler_view *
2928 si_create_sampler_view_custom(struct pipe_context *ctx,
2929 struct pipe_resource *texture,
2930 const struct pipe_sampler_view *state,
2931 unsigned width0, unsigned height0,
2932 unsigned force_level)
2933 {
2934 struct si_context *sctx = (struct si_context*)ctx;
2935 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2936 struct r600_texture *tmp = (struct r600_texture*)texture;
2937 unsigned base_level, first_level, last_level;
2938 unsigned char state_swizzle[4];
2939 unsigned height, depth, width;
2940 unsigned last_layer = state->u.tex.last_layer;
2941 enum pipe_format pipe_format;
2942 const struct radeon_surf_level *surflevel;
2943
2944 if (!view)
2945 return NULL;
2946
2947 /* initialize base object */
2948 view->base = *state;
2949 view->base.texture = NULL;
2950 view->base.reference.count = 1;
2951 view->base.context = ctx;
2952
2953 assert(texture);
2954 pipe_resource_reference(&view->base.texture, texture);
2955
2956 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2957 state->format == PIPE_FORMAT_S8X24_UINT ||
2958 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2959 state->format == PIPE_FORMAT_S8_UINT)
2960 view->is_stencil_sampler = true;
2961
2962 /* Buffer resource. */
2963 if (texture->target == PIPE_BUFFER) {
2964 si_make_buffer_descriptor(sctx->screen,
2965 (struct r600_resource *)texture,
2966 state->format,
2967 state->u.buf.offset,
2968 state->u.buf.size,
2969 view->state);
2970
2971 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2972 return &view->base;
2973 }
2974
2975 state_swizzle[0] = state->swizzle_r;
2976 state_swizzle[1] = state->swizzle_g;
2977 state_swizzle[2] = state->swizzle_b;
2978 state_swizzle[3] = state->swizzle_a;
2979
2980 base_level = 0;
2981 first_level = state->u.tex.first_level;
2982 last_level = state->u.tex.last_level;
2983 width = width0;
2984 height = height0;
2985 depth = texture->depth0;
2986
2987 if (force_level) {
2988 assert(force_level == first_level &&
2989 force_level == last_level);
2990 base_level = force_level;
2991 first_level = 0;
2992 last_level = 0;
2993 width = u_minify(width, force_level);
2994 height = u_minify(height, force_level);
2995 depth = u_minify(depth, force_level);
2996 }
2997
2998 /* This is not needed if state trackers set last_layer correctly. */
2999 if (state->target == PIPE_TEXTURE_1D ||
3000 state->target == PIPE_TEXTURE_2D ||
3001 state->target == PIPE_TEXTURE_RECT ||
3002 state->target == PIPE_TEXTURE_CUBE)
3003 last_layer = state->u.tex.first_layer;
3004
3005 /* Texturing with separate depth and stencil. */
3006 pipe_format = state->format;
3007
3008 /* Depth/stencil texturing sometimes needs separate texture. */
3009 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3010 if (!tmp->flushed_depth_texture &&
3011 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3012 pipe_resource_reference(&view->base.texture, NULL);
3013 FREE(view);
3014 return NULL;
3015 }
3016
3017 assert(tmp->flushed_depth_texture);
3018
3019 /* Override format for the case where the flushed texture
3020 * contains only Z or only S.
3021 */
3022 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3023 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3024
3025 tmp = tmp->flushed_depth_texture;
3026 }
3027
3028 surflevel = tmp->surface.level;
3029
3030 if (tmp->db_compatible) {
3031 switch (pipe_format) {
3032 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3033 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3034 break;
3035 case PIPE_FORMAT_X8Z24_UNORM:
3036 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3037 /* Z24 is always stored like this for DB
3038 * compatibility.
3039 */
3040 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3041 break;
3042 case PIPE_FORMAT_X24S8_UINT:
3043 case PIPE_FORMAT_S8X24_UINT:
3044 case PIPE_FORMAT_X32_S8X24_UINT:
3045 pipe_format = PIPE_FORMAT_S8_UINT;
3046 surflevel = tmp->surface.stencil_level;
3047 break;
3048 default:;
3049 }
3050 }
3051
3052 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3053 state->u.tex.first_level,
3054 state->format);
3055
3056 si_make_texture_descriptor(sctx->screen, tmp, true,
3057 state->target, pipe_format, state_swizzle,
3058 first_level, last_level,
3059 state->u.tex.first_layer, last_layer,
3060 width, height, depth,
3061 view->state, view->fmask_state);
3062
3063 view->base_level_info = &surflevel[base_level];
3064 view->base_level = base_level;
3065 view->block_width = util_format_get_blockwidth(pipe_format);
3066 return &view->base;
3067 }
3068
3069 static struct pipe_sampler_view *
3070 si_create_sampler_view(struct pipe_context *ctx,
3071 struct pipe_resource *texture,
3072 const struct pipe_sampler_view *state)
3073 {
3074 return si_create_sampler_view_custom(ctx, texture, state,
3075 texture ? texture->width0 : 0,
3076 texture ? texture->height0 : 0, 0);
3077 }
3078
3079 static void si_sampler_view_destroy(struct pipe_context *ctx,
3080 struct pipe_sampler_view *state)
3081 {
3082 struct si_sampler_view *view = (struct si_sampler_view *)state;
3083
3084 if (state->texture && state->texture->target == PIPE_BUFFER)
3085 LIST_DELINIT(&view->list);
3086
3087 pipe_resource_reference(&state->texture, NULL);
3088 FREE(view);
3089 }
3090
3091 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3092 {
3093 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3094 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3095 (linear_filter &&
3096 (wrap == PIPE_TEX_WRAP_CLAMP ||
3097 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3098 }
3099
3100 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3101 {
3102 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3103 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3104
3105 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3106 state->border_color.ui[2] || state->border_color.ui[3]) &&
3107 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3108 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3109 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3110 }
3111
3112 static void *si_create_sampler_state(struct pipe_context *ctx,
3113 const struct pipe_sampler_state *state)
3114 {
3115 struct si_context *sctx = (struct si_context *)ctx;
3116 struct r600_common_screen *rscreen = sctx->b.screen;
3117 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3118 unsigned border_color_type, border_color_index = 0;
3119 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3120 : state->max_anisotropy;
3121 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3122
3123 if (!rstate) {
3124 return NULL;
3125 }
3126
3127 if (!sampler_state_needs_border_color(state))
3128 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3129 else if (state->border_color.f[0] == 0 &&
3130 state->border_color.f[1] == 0 &&
3131 state->border_color.f[2] == 0 &&
3132 state->border_color.f[3] == 0)
3133 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3134 else if (state->border_color.f[0] == 0 &&
3135 state->border_color.f[1] == 0 &&
3136 state->border_color.f[2] == 0 &&
3137 state->border_color.f[3] == 1)
3138 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3139 else if (state->border_color.f[0] == 1 &&
3140 state->border_color.f[1] == 1 &&
3141 state->border_color.f[2] == 1 &&
3142 state->border_color.f[3] == 1)
3143 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3144 else {
3145 int i;
3146
3147 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3148
3149 /* Check if the border has been uploaded already. */
3150 for (i = 0; i < sctx->border_color_count; i++)
3151 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3152 sizeof(state->border_color)) == 0)
3153 break;
3154
3155 if (i >= SI_MAX_BORDER_COLORS) {
3156 /* Getting 4096 unique border colors is very unlikely. */
3157 fprintf(stderr, "radeonsi: The border color table is full. "
3158 "Any new border colors will be just black. "
3159 "Please file a bug.\n");
3160 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3161 } else {
3162 if (i == sctx->border_color_count) {
3163 /* Upload a new border color. */
3164 memcpy(&sctx->border_color_table[i], &state->border_color,
3165 sizeof(state->border_color));
3166 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3167 &state->border_color,
3168 sizeof(state->border_color));
3169 sctx->border_color_count++;
3170 }
3171
3172 border_color_index = i;
3173 }
3174 }
3175
3176 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3177 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3178 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3179 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3180 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3181 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3182 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3183 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3184 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3185 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3186 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3187 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3188 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3189 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3190 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3191 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3192 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3193 S_008F38_MIP_POINT_PRECLAMP(1) |
3194 S_008F38_DISABLE_LSB_CEIL(1) |
3195 S_008F38_FILTER_PREC_FIX(1) |
3196 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3197 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3198 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3199 return rstate;
3200 }
3201
3202 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3203 {
3204 struct si_context *sctx = (struct si_context *)ctx;
3205
3206 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3207 return;
3208
3209 sctx->sample_mask.sample_mask = sample_mask;
3210 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3211 }
3212
3213 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3214 {
3215 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3216 unsigned mask = sctx->sample_mask.sample_mask;
3217
3218 /* Needed for line and polygon smoothing as well as for the Polaris
3219 * small primitive filter. We expect the state tracker to take care of
3220 * this for us.
3221 */
3222 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3223 (mask & 1 && sctx->blitter->running));
3224
3225 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3226 radeon_emit(cs, mask | (mask << 16));
3227 radeon_emit(cs, mask | (mask << 16));
3228 }
3229
3230 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3231 {
3232 free(state);
3233 }
3234
3235 /*
3236 * Vertex elements & buffers
3237 */
3238
3239 static void *si_create_vertex_elements(struct pipe_context *ctx,
3240 unsigned count,
3241 const struct pipe_vertex_element *elements)
3242 {
3243 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3244 int i;
3245
3246 assert(count <= SI_MAX_ATTRIBS);
3247 if (!v)
3248 return NULL;
3249
3250 v->count = count;
3251 for (i = 0; i < count; ++i) {
3252 const struct util_format_description *desc;
3253 unsigned data_format, num_format;
3254 int first_non_void;
3255
3256 desc = util_format_description(elements[i].src_format);
3257 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3258 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3259 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3260
3261 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3262 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3263 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3264 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3265 S_008F0C_NUM_FORMAT(num_format) |
3266 S_008F0C_DATA_FORMAT(data_format);
3267 v->format_size[i] = desc->block.bits / 8;
3268 }
3269 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3270
3271 return v;
3272 }
3273
3274 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3275 {
3276 struct si_context *sctx = (struct si_context *)ctx;
3277 struct si_vertex_element *v = (struct si_vertex_element*)state;
3278
3279 sctx->vertex_elements = v;
3280 sctx->vertex_buffers_dirty = true;
3281 sctx->do_update_shaders = true;
3282 }
3283
3284 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3285 {
3286 struct si_context *sctx = (struct si_context *)ctx;
3287
3288 if (sctx->vertex_elements == state)
3289 sctx->vertex_elements = NULL;
3290 FREE(state);
3291 }
3292
3293 static void si_set_vertex_buffers(struct pipe_context *ctx,
3294 unsigned start_slot, unsigned count,
3295 const struct pipe_vertex_buffer *buffers)
3296 {
3297 struct si_context *sctx = (struct si_context *)ctx;
3298 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3299 int i;
3300
3301 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3302
3303 if (buffers) {
3304 for (i = 0; i < count; i++) {
3305 const struct pipe_vertex_buffer *src = buffers + i;
3306 struct pipe_vertex_buffer *dsti = dst + i;
3307 struct pipe_resource *buf = src->buffer;
3308
3309 pipe_resource_reference(&dsti->buffer, buf);
3310 dsti->buffer_offset = src->buffer_offset;
3311 dsti->stride = src->stride;
3312 r600_context_add_resource_size(ctx, buf);
3313 if (buf)
3314 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3315 }
3316 } else {
3317 for (i = 0; i < count; i++) {
3318 pipe_resource_reference(&dst[i].buffer, NULL);
3319 }
3320 }
3321 sctx->vertex_buffers_dirty = true;
3322 }
3323
3324 static void si_set_index_buffer(struct pipe_context *ctx,
3325 const struct pipe_index_buffer *ib)
3326 {
3327 struct si_context *sctx = (struct si_context *)ctx;
3328
3329 if (ib) {
3330 struct pipe_resource *buf = ib->buffer;
3331
3332 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3333 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3334 r600_context_add_resource_size(ctx, buf);
3335 if (buf)
3336 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3337 } else {
3338 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3339 }
3340 }
3341
3342 /*
3343 * Misc
3344 */
3345
3346 static void si_set_tess_state(struct pipe_context *ctx,
3347 const float default_outer_level[4],
3348 const float default_inner_level[2])
3349 {
3350 struct si_context *sctx = (struct si_context *)ctx;
3351 struct pipe_constant_buffer cb;
3352 float array[8];
3353
3354 memcpy(array, default_outer_level, sizeof(float) * 4);
3355 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3356
3357 cb.buffer = NULL;
3358 cb.user_buffer = NULL;
3359 cb.buffer_size = sizeof(array);
3360
3361 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3362 (void*)array, sizeof(array),
3363 &cb.buffer_offset);
3364
3365 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3366 pipe_resource_reference(&cb.buffer, NULL);
3367 }
3368
3369 static void si_texture_barrier(struct pipe_context *ctx)
3370 {
3371 struct si_context *sctx = (struct si_context *)ctx;
3372
3373 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3374 SI_CONTEXT_INV_GLOBAL_L2 |
3375 SI_CONTEXT_FLUSH_AND_INV_CB |
3376 SI_CONTEXT_CS_PARTIAL_FLUSH;
3377 }
3378
3379 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3380 {
3381 struct si_context *sctx = (struct si_context *)ctx;
3382
3383 /* Subsequent commands must wait for all shader invocations to
3384 * complete. */
3385 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3386 SI_CONTEXT_CS_PARTIAL_FLUSH;
3387
3388 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3389 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3390 SI_CONTEXT_INV_VMEM_L1;
3391
3392 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3393 PIPE_BARRIER_SHADER_BUFFER |
3394 PIPE_BARRIER_TEXTURE |
3395 PIPE_BARRIER_IMAGE |
3396 PIPE_BARRIER_STREAMOUT_BUFFER |
3397 PIPE_BARRIER_GLOBAL_BUFFER)) {
3398 /* As far as I can tell, L1 contents are written back to L2
3399 * automatically at end of shader, but the contents of other
3400 * L1 caches might still be stale. */
3401 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3402 }
3403
3404 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3405 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3406
3407 /* Indices are read through TC L2 since VI. */
3408 if (sctx->screen->b.chip_class <= CIK)
3409 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3410 }
3411
3412 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3413 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3414
3415 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3416 PIPE_BARRIER_INDIRECT_BUFFER)) {
3417 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3418 *
3419 * We need to make sure that TC L1 & L2 are written back to
3420 * memory, because CB fetches don't consider TC, but there's
3421 * no need to invalidate any TC cache lines. */
3422 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3423 }
3424 }
3425
3426 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3427 {
3428 struct pipe_blend_state blend;
3429
3430 memset(&blend, 0, sizeof(blend));
3431 blend.independent_blend_enable = true;
3432 blend.rt[0].colormask = 0xf;
3433 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3434 }
3435
3436 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3437 bool include_draw_vbo)
3438 {
3439 si_need_cs_space((struct si_context*)ctx);
3440 }
3441
3442 static void si_init_config(struct si_context *sctx);
3443
3444 void si_init_state_functions(struct si_context *sctx)
3445 {
3446 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3447 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3448 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3449 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3450 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3451
3452 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3453 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3454 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3455 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3456 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3457 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3458 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3459 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3460 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3461 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3462
3463 sctx->b.b.create_blend_state = si_create_blend_state;
3464 sctx->b.b.bind_blend_state = si_bind_blend_state;
3465 sctx->b.b.delete_blend_state = si_delete_blend_state;
3466 sctx->b.b.set_blend_color = si_set_blend_color;
3467
3468 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3469 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3470 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3471
3472 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3473 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3474 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3475
3476 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3477 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3478 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3479 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3480 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3481
3482 sctx->b.b.set_clip_state = si_set_clip_state;
3483 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3484
3485 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3486 sctx->b.b.get_sample_position = cayman_get_sample_position;
3487
3488 sctx->b.b.create_sampler_state = si_create_sampler_state;
3489 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3490
3491 sctx->b.b.create_sampler_view = si_create_sampler_view;
3492 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3493
3494 sctx->b.b.set_sample_mask = si_set_sample_mask;
3495
3496 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3497 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3498 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3499 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3500 sctx->b.b.set_index_buffer = si_set_index_buffer;
3501
3502 sctx->b.b.texture_barrier = si_texture_barrier;
3503 sctx->b.b.memory_barrier = si_memory_barrier;
3504 sctx->b.b.set_min_samples = si_set_min_samples;
3505 sctx->b.b.set_tess_state = si_set_tess_state;
3506
3507 sctx->b.b.set_active_query_state = si_set_active_query_state;
3508 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3509 sctx->b.save_qbo_state = si_save_qbo_state;
3510 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3511
3512 sctx->b.b.draw_vbo = si_draw_vbo;
3513
3514 si_init_config(sctx);
3515 }
3516
3517 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3518 {
3519 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3520 }
3521
3522 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3523 struct r600_texture *rtex,
3524 struct radeon_bo_metadata *md)
3525 {
3526 struct si_screen *sscreen = (struct si_screen*)rscreen;
3527 struct pipe_resource *res = &rtex->resource.b.b;
3528 static const unsigned char swizzle[] = {
3529 PIPE_SWIZZLE_X,
3530 PIPE_SWIZZLE_Y,
3531 PIPE_SWIZZLE_Z,
3532 PIPE_SWIZZLE_W
3533 };
3534 uint32_t desc[8], i;
3535 bool is_array = util_resource_is_array_texture(res);
3536
3537 /* DRM 2.x.x doesn't support this. */
3538 if (rscreen->info.drm_major != 3)
3539 return;
3540
3541 assert(rtex->dcc_separate_buffer == NULL);
3542 assert(rtex->fmask.size == 0);
3543
3544 /* Metadata image format format version 1:
3545 * [0] = 1 (metadata format identifier)
3546 * [1] = (VENDOR_ID << 16) | PCI_ID
3547 * [2:9] = image descriptor for the whole resource
3548 * [2] is always 0, because the base address is cleared
3549 * [9] is the DCC offset bits [39:8] from the beginning of
3550 * the buffer
3551 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3552 */
3553
3554 md->metadata[0] = 1; /* metadata image format version 1 */
3555
3556 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3557 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3558
3559 si_make_texture_descriptor(sscreen, rtex, true,
3560 res->target, res->format,
3561 swizzle, 0, res->last_level, 0,
3562 is_array ? res->array_size - 1 : 0,
3563 res->width0, res->height0, res->depth0,
3564 desc, NULL);
3565
3566 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3567 rtex->surface.blk_w, false, desc);
3568
3569 /* Clear the base address and set the relative DCC offset. */
3570 desc[0] = 0;
3571 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3572 desc[7] = rtex->dcc_offset >> 8;
3573
3574 /* Dwords [2:9] contain the image descriptor. */
3575 memcpy(&md->metadata[2], desc, sizeof(desc));
3576
3577 /* Dwords [10:..] contain the mipmap level offsets. */
3578 for (i = 0; i <= res->last_level; i++)
3579 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3580
3581 md->size_metadata = (11 + res->last_level) * 4;
3582 }
3583
3584 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3585 struct r600_texture *rtex,
3586 struct radeon_bo_metadata *md)
3587 {
3588 uint32_t *desc = &md->metadata[2];
3589
3590 if (rscreen->chip_class < VI)
3591 return;
3592
3593 /* Return if DCC is enabled. The texture should be set up with it
3594 * already.
3595 */
3596 if (md->size_metadata >= 11 * 4 &&
3597 md->metadata[0] != 0 &&
3598 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3599 G_008F28_COMPRESSION_EN(desc[6])) {
3600 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3601 return;
3602 }
3603
3604 /* Disable DCC. These are always set by texture_from_handle and must
3605 * be cleared here.
3606 */
3607 rtex->dcc_offset = 0;
3608 }
3609
3610 void si_init_screen_state_functions(struct si_screen *sscreen)
3611 {
3612 sscreen->b.b.is_format_supported = si_is_format_supported;
3613 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3614 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3615 }
3616
3617 static void
3618 si_write_harvested_raster_configs(struct si_context *sctx,
3619 struct si_pm4_state *pm4,
3620 unsigned raster_config,
3621 unsigned raster_config_1)
3622 {
3623 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3624 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3625 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3626 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3627 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3628 unsigned rb_per_se = num_rb / num_se;
3629 unsigned se_mask[4];
3630 unsigned se;
3631
3632 se_mask[0] = ((1 << rb_per_se) - 1);
3633 se_mask[1] = (se_mask[0] << rb_per_se);
3634 se_mask[2] = (se_mask[1] << rb_per_se);
3635 se_mask[3] = (se_mask[2] << rb_per_se);
3636
3637 se_mask[0] &= rb_mask;
3638 se_mask[1] &= rb_mask;
3639 se_mask[2] &= rb_mask;
3640 se_mask[3] &= rb_mask;
3641
3642 assert(num_se == 1 || num_se == 2 || num_se == 4);
3643 assert(sh_per_se == 1 || sh_per_se == 2);
3644 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3645
3646 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3647 * fields are for, so I'm leaving them as their default
3648 * values. */
3649
3650 for (se = 0; se < num_se; se++) {
3651 unsigned raster_config_se = raster_config;
3652 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3653 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3654 int idx = (se / 2) * 2;
3655
3656 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3657 raster_config_se &= C_028350_SE_MAP;
3658
3659 if (!se_mask[idx]) {
3660 raster_config_se |=
3661 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3662 } else {
3663 raster_config_se |=
3664 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3665 }
3666 }
3667
3668 pkr0_mask &= rb_mask;
3669 pkr1_mask &= rb_mask;
3670 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3671 raster_config_se &= C_028350_PKR_MAP;
3672
3673 if (!pkr0_mask) {
3674 raster_config_se |=
3675 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3676 } else {
3677 raster_config_se |=
3678 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3679 }
3680 }
3681
3682 if (rb_per_se >= 2) {
3683 unsigned rb0_mask = 1 << (se * rb_per_se);
3684 unsigned rb1_mask = rb0_mask << 1;
3685
3686 rb0_mask &= rb_mask;
3687 rb1_mask &= rb_mask;
3688 if (!rb0_mask || !rb1_mask) {
3689 raster_config_se &= C_028350_RB_MAP_PKR0;
3690
3691 if (!rb0_mask) {
3692 raster_config_se |=
3693 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3694 } else {
3695 raster_config_se |=
3696 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3697 }
3698 }
3699
3700 if (rb_per_se > 2) {
3701 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3702 rb1_mask = rb0_mask << 1;
3703 rb0_mask &= rb_mask;
3704 rb1_mask &= rb_mask;
3705 if (!rb0_mask || !rb1_mask) {
3706 raster_config_se &= C_028350_RB_MAP_PKR1;
3707
3708 if (!rb0_mask) {
3709 raster_config_se |=
3710 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3711 } else {
3712 raster_config_se |=
3713 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3714 }
3715 }
3716 }
3717 }
3718
3719 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3720 if (sctx->b.chip_class < CIK)
3721 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3722 SE_INDEX(se) | SH_BROADCAST_WRITES |
3723 INSTANCE_BROADCAST_WRITES);
3724 else
3725 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3726 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3727 S_030800_INSTANCE_BROADCAST_WRITES(1));
3728 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3729 }
3730
3731 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3732 if (sctx->b.chip_class < CIK)
3733 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3734 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3735 INSTANCE_BROADCAST_WRITES);
3736 else {
3737 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3738 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3739 S_030800_INSTANCE_BROADCAST_WRITES(1));
3740
3741 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3742 (!se_mask[2] && !se_mask[3]))) {
3743 raster_config_1 &= C_028354_SE_PAIR_MAP;
3744
3745 if (!se_mask[0] && !se_mask[1]) {
3746 raster_config_1 |=
3747 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3748 } else {
3749 raster_config_1 |=
3750 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3751 }
3752 }
3753
3754 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3755 }
3756 }
3757
3758 static void si_init_config(struct si_context *sctx)
3759 {
3760 struct si_screen *sscreen = sctx->screen;
3761 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3762 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3763 unsigned raster_config, raster_config_1;
3764 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3765 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3766
3767 if (!pm4)
3768 return;
3769
3770 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3771 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3772 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3773 si_pm4_cmd_end(pm4, false);
3774
3775 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3776 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3777
3778 /* FIXME calculate these values somehow ??? */
3779 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3780 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3781 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3782
3783 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3784 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3785
3786 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3787 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3788 if (sctx->b.chip_class < CIK)
3789 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3790 S_008A14_CLIP_VTX_REORDER_ENA(1));
3791
3792 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3793 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3794
3795 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3796
3797 switch (sctx->screen->b.family) {
3798 case CHIP_TAHITI:
3799 case CHIP_PITCAIRN:
3800 raster_config = 0x2a00126a;
3801 raster_config_1 = 0x00000000;
3802 break;
3803 case CHIP_VERDE:
3804 raster_config = 0x0000124a;
3805 raster_config_1 = 0x00000000;
3806 break;
3807 case CHIP_OLAND:
3808 raster_config = 0x00000082;
3809 raster_config_1 = 0x00000000;
3810 break;
3811 case CHIP_HAINAN:
3812 raster_config = 0x00000000;
3813 raster_config_1 = 0x00000000;
3814 break;
3815 case CHIP_BONAIRE:
3816 raster_config = 0x16000012;
3817 raster_config_1 = 0x00000000;
3818 break;
3819 case CHIP_HAWAII:
3820 raster_config = 0x3a00161a;
3821 raster_config_1 = 0x0000002e;
3822 break;
3823 case CHIP_FIJI:
3824 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3825 /* old kernels with old tiling config */
3826 raster_config = 0x16000012;
3827 raster_config_1 = 0x0000002a;
3828 } else {
3829 raster_config = 0x3a00161a;
3830 raster_config_1 = 0x0000002e;
3831 }
3832 break;
3833 case CHIP_POLARIS10:
3834 raster_config = 0x16000012;
3835 raster_config_1 = 0x0000002a;
3836 break;
3837 case CHIP_POLARIS11:
3838 raster_config = 0x16000012;
3839 raster_config_1 = 0x00000000;
3840 break;
3841 case CHIP_TONGA:
3842 raster_config = 0x16000012;
3843 raster_config_1 = 0x0000002a;
3844 break;
3845 case CHIP_ICELAND:
3846 if (num_rb == 1)
3847 raster_config = 0x00000000;
3848 else
3849 raster_config = 0x00000002;
3850 raster_config_1 = 0x00000000;
3851 break;
3852 case CHIP_CARRIZO:
3853 raster_config = 0x00000002;
3854 raster_config_1 = 0x00000000;
3855 break;
3856 case CHIP_KAVERI:
3857 /* KV should be 0x00000002, but that causes problems with radeon */
3858 raster_config = 0x00000000; /* 0x00000002 */
3859 raster_config_1 = 0x00000000;
3860 break;
3861 case CHIP_KABINI:
3862 case CHIP_MULLINS:
3863 case CHIP_STONEY:
3864 raster_config = 0x00000000;
3865 raster_config_1 = 0x00000000;
3866 break;
3867 default:
3868 fprintf(stderr,
3869 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3870 raster_config = 0x00000000;
3871 raster_config_1 = 0x00000000;
3872 break;
3873 }
3874
3875 /* Always use the default config when all backends are enabled
3876 * (or when we failed to determine the enabled backends).
3877 */
3878 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3879 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3880 raster_config);
3881 if (sctx->b.chip_class >= CIK)
3882 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3883 raster_config_1);
3884 } else {
3885 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3886 }
3887
3888 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3889 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3890 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3891 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3892 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3893 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3894 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3895
3896 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3897 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3898 S_028230_ER_TRI(0xA) |
3899 S_028230_ER_POINT(0xA) |
3900 S_028230_ER_RECT(0xA) |
3901 /* Required by DX10_DIAMOND_TEST_ENA: */
3902 S_028230_ER_LINE_LR(0x1A) |
3903 S_028230_ER_LINE_RL(0x26) |
3904 S_028230_ER_LINE_TB(0xA) |
3905 S_028230_ER_LINE_BT(0xA));
3906 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3907 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3908 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3909 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3910 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3911 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3912 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3913 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3914 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3915
3916 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3917 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3918 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3919
3920 if (sctx->b.chip_class >= CIK) {
3921 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3922 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3923 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3924 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3925
3926 if (sscreen->b.info.num_good_compute_units /
3927 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3928 /* Too few available compute units per SH. Disallowing
3929 * VS to run on CU0 could hurt us more than late VS
3930 * allocation would help.
3931 *
3932 * LATE_ALLOC_VS = 2 is the highest safe number.
3933 */
3934 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3935 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3936 } else {
3937 /* Set LATE_ALLOC_VS == 31. It should be less than
3938 * the number of scratch waves. Limitations:
3939 * - VS can't execute on CU0.
3940 * - If HS writes outputs to LDS, LS can't execute on CU0.
3941 */
3942 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3943 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3944 }
3945
3946 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3947 }
3948
3949 if (sctx->b.chip_class >= VI) {
3950 unsigned vgt_tess_distribution;
3951
3952 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3953 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3954 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3955 if (sctx->b.family < CHIP_POLARIS10)
3956 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3957 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3958
3959 vgt_tess_distribution =
3960 S_028B50_ACCUM_ISOLINE(32) |
3961 S_028B50_ACCUM_TRI(11) |
3962 S_028B50_ACCUM_QUAD(11) |
3963 S_028B50_DONUT_SPLIT(16);
3964
3965 /* Testing with Unigine Heaven extreme tesselation yielded best results
3966 * with TRAP_SPLIT = 3.
3967 */
3968 if (sctx->b.family == CHIP_FIJI ||
3969 sctx->b.family >= CHIP_POLARIS10)
3970 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3971
3972 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3973 } else {
3974 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3975 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3976 }
3977
3978 if (sctx->b.family == CHIP_STONEY)
3979 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3980
3981 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3982 if (sctx->b.chip_class >= CIK)
3983 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3984 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3985 RADEON_PRIO_BORDER_COLORS);
3986
3987 si_pm4_upload_indirect_buffer(sctx, pm4);
3988 sctx->init_config = pm4;
3989 }