2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
36 /* Initialize an external atom (owned by ../radeon). */
38 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
39 struct r600_atom
**list_elem
)
41 atom
->id
= list_elem
- sctx
->atoms
.array
;
45 /* Initialize an atom owned by radeonsi. */
46 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
47 struct r600_atom
**list_elem
,
48 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
50 atom
->emit
= emit_func
;
51 atom
->id
= list_elem
- sctx
->atoms
.array
;
55 static unsigned si_map_swizzle(unsigned swizzle
)
59 return V_008F0C_SQ_SEL_Y
;
61 return V_008F0C_SQ_SEL_Z
;
63 return V_008F0C_SQ_SEL_W
;
65 return V_008F0C_SQ_SEL_0
;
67 return V_008F0C_SQ_SEL_1
;
68 default: /* PIPE_SWIZZLE_X */
69 return V_008F0C_SQ_SEL_X
;
73 /* 12.4 fixed-point */
74 static unsigned si_pack_float_12p4(float x
)
77 x
>= 4096 ? 0xffff : x
* 16;
81 * Inferred framebuffer and blender state.
83 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
84 * if there is not enough PS outputs.
86 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
88 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
89 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
90 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
91 * but you never know. */
92 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
96 cb_target_mask
&= blend
->cb_target_mask
;
98 /* Avoid a hang that happens when dual source blending is enabled
99 * but there is not enough color outputs. This is undefined behavior,
100 * so disable color writes completely.
102 * Reproducible with Unigine Heaven 4.0 and drirc missing.
104 if (blend
&& blend
->dual_src_blend
&&
105 sctx
->ps_shader
.cso
&&
106 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
109 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
111 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
112 * I think we don't have to do anything between IBs.
114 if (sctx
->screen
->dfsm_allowed
&&
115 sctx
->last_cb_target_mask
!= cb_target_mask
) {
116 sctx
->last_cb_target_mask
= cb_target_mask
;
118 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
119 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
122 if (sctx
->chip_class
>= VI
) {
123 /* DCC MSAA workaround for blending.
124 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
125 * COMBINER_DISABLE, but that would be more complicated.
127 bool oc_disable
= (sctx
->chip_class
== VI
||
128 sctx
->chip_class
== GFX9
) &&
130 blend
->blend_enable_4bit
& cb_target_mask
&&
131 sctx
->framebuffer
.nr_samples
>= 2;
133 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
134 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
135 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
136 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
));
139 /* RB+ register settings. */
140 if (sctx
->screen
->rbplus_allowed
) {
141 unsigned spi_shader_col_format
=
142 sctx
->ps_shader
.cso
?
143 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
144 unsigned sx_ps_downconvert
= 0;
145 unsigned sx_blend_opt_epsilon
= 0;
146 unsigned sx_blend_opt_control
= 0;
148 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
149 struct r600_surface
*surf
=
150 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
151 unsigned format
, swap
, spi_format
, colormask
;
152 bool has_alpha
, has_rgb
;
157 format
= G_028C70_FORMAT(surf
->cb_color_info
);
158 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
159 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
160 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
162 /* Set if RGB and A are present. */
163 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
165 if (format
== V_028C70_COLOR_8
||
166 format
== V_028C70_COLOR_16
||
167 format
== V_028C70_COLOR_32
)
168 has_rgb
= !has_alpha
;
172 /* Check the colormask and export format. */
173 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
175 if (!(colormask
& PIPE_MASK_A
))
178 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
183 /* Disable value checking for disabled channels. */
185 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
187 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
189 /* Enable down-conversion for 32bpp and smaller formats. */
191 case V_028C70_COLOR_8
:
192 case V_028C70_COLOR_8_8
:
193 case V_028C70_COLOR_8_8_8_8
:
194 /* For 1 and 2-channel formats, use the superset thereof. */
195 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
196 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
197 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
198 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
199 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
203 case V_028C70_COLOR_5_6_5
:
204 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
205 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
206 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
210 case V_028C70_COLOR_1_5_5_5
:
211 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
212 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
213 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
217 case V_028C70_COLOR_4_4_4_4
:
218 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
219 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
220 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
224 case V_028C70_COLOR_32
:
225 if (swap
== V_028C70_SWAP_STD
&&
226 spi_format
== V_028714_SPI_SHADER_32_R
)
227 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
228 else if (swap
== V_028C70_SWAP_ALT_REV
&&
229 spi_format
== V_028714_SPI_SHADER_32_AR
)
230 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
233 case V_028C70_COLOR_16
:
234 case V_028C70_COLOR_16_16
:
235 /* For 1-channel formats, use the superset thereof. */
236 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
237 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
238 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
239 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
240 if (swap
== V_028C70_SWAP_STD
||
241 swap
== V_028C70_SWAP_STD_REV
)
242 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
244 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
248 case V_028C70_COLOR_10_11_11
:
249 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
250 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
251 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
255 case V_028C70_COLOR_2_10_10_10
:
256 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
257 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
258 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
264 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
265 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
266 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
267 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
268 } else if (sctx
->screen
->has_rbplus
) {
269 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
270 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
271 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
272 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
280 static uint32_t si_translate_blend_function(int blend_func
)
282 switch (blend_func
) {
284 return V_028780_COMB_DST_PLUS_SRC
;
285 case PIPE_BLEND_SUBTRACT
:
286 return V_028780_COMB_SRC_MINUS_DST
;
287 case PIPE_BLEND_REVERSE_SUBTRACT
:
288 return V_028780_COMB_DST_MINUS_SRC
;
290 return V_028780_COMB_MIN_DST_SRC
;
292 return V_028780_COMB_MAX_DST_SRC
;
294 PRINT_ERR("Unknown blend function %d\n", blend_func
);
301 static uint32_t si_translate_blend_factor(int blend_fact
)
303 switch (blend_fact
) {
304 case PIPE_BLENDFACTOR_ONE
:
305 return V_028780_BLEND_ONE
;
306 case PIPE_BLENDFACTOR_SRC_COLOR
:
307 return V_028780_BLEND_SRC_COLOR
;
308 case PIPE_BLENDFACTOR_SRC_ALPHA
:
309 return V_028780_BLEND_SRC_ALPHA
;
310 case PIPE_BLENDFACTOR_DST_ALPHA
:
311 return V_028780_BLEND_DST_ALPHA
;
312 case PIPE_BLENDFACTOR_DST_COLOR
:
313 return V_028780_BLEND_DST_COLOR
;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
316 case PIPE_BLENDFACTOR_CONST_COLOR
:
317 return V_028780_BLEND_CONSTANT_COLOR
;
318 case PIPE_BLENDFACTOR_CONST_ALPHA
:
319 return V_028780_BLEND_CONSTANT_ALPHA
;
320 case PIPE_BLENDFACTOR_ZERO
:
321 return V_028780_BLEND_ZERO
;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
334 case PIPE_BLENDFACTOR_SRC1_COLOR
:
335 return V_028780_BLEND_SRC1_COLOR
;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
337 return V_028780_BLEND_SRC1_ALPHA
;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
339 return V_028780_BLEND_INV_SRC1_COLOR
;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
341 return V_028780_BLEND_INV_SRC1_ALPHA
;
343 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
350 static uint32_t si_translate_blend_opt_function(int blend_func
)
352 switch (blend_func
) {
354 return V_028760_OPT_COMB_ADD
;
355 case PIPE_BLEND_SUBTRACT
:
356 return V_028760_OPT_COMB_SUBTRACT
;
357 case PIPE_BLEND_REVERSE_SUBTRACT
:
358 return V_028760_OPT_COMB_REVSUBTRACT
;
360 return V_028760_OPT_COMB_MIN
;
362 return V_028760_OPT_COMB_MAX
;
364 return V_028760_OPT_COMB_BLEND_DISABLED
;
368 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
370 switch (blend_fact
) {
371 case PIPE_BLENDFACTOR_ZERO
:
372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
373 case PIPE_BLENDFACTOR_ONE
:
374 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
375 case PIPE_BLENDFACTOR_SRC_COLOR
:
376 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
377 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
378 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
379 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
380 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
381 case PIPE_BLENDFACTOR_SRC_ALPHA
:
382 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
383 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
384 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
385 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
386 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
387 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
393 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
394 struct si_state_blend
*blend
,
395 enum pipe_blend_func func
,
396 enum pipe_blendfactor src
,
397 enum pipe_blendfactor dst
,
400 /* Src factor is allowed when it does not depend on Dst */
401 static const uint32_t src_allowed
=
402 (1u << PIPE_BLENDFACTOR_ONE
) |
403 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
404 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
405 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
406 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
407 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
408 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
409 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
410 (1u << PIPE_BLENDFACTOR_ZERO
) |
411 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
413 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
414 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
416 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
418 if (dst
== PIPE_BLENDFACTOR_ONE
&&
419 (src_allowed
& (1u << src
))) {
420 /* Addition is commutative, but floating point addition isn't
421 * associative: subtle changes can be introduced via different
424 * Out-of-order is also non-deterministic, which means that
425 * this breaks OpenGL invariance requirements. So only enable
426 * out-of-order additive blending if explicitly allowed by a
429 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
430 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
431 blend
->commutative_4bit
|= chanmask
;
436 * Get rid of DST in the blend factors by commuting the operands:
437 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
439 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
440 unsigned *dst_factor
, unsigned expected_dst
,
441 unsigned replacement_src
)
443 if (*src_factor
== expected_dst
&&
444 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
445 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
446 *dst_factor
= replacement_src
;
448 /* Commuting the operands requires reversing subtractions. */
449 if (*func
== PIPE_BLEND_SUBTRACT
)
450 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
451 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
452 *func
= PIPE_BLEND_SUBTRACT
;
456 static bool si_blend_factor_uses_dst(unsigned factor
)
458 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
459 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
460 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
461 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
462 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
465 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
466 const struct pipe_blend_state
*state
,
469 struct si_context
*sctx
= (struct si_context
*)ctx
;
470 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
471 struct si_pm4_state
*pm4
= &blend
->pm4
;
472 uint32_t sx_mrt_blend_opt
[8] = {0};
473 uint32_t color_control
= 0;
478 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
479 blend
->alpha_to_one
= state
->alpha_to_one
;
480 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
481 blend
->logicop_enable
= state
->logicop_enable
;
483 if (state
->logicop_enable
) {
484 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
486 color_control
|= S_028808_ROP3(0xcc);
489 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
490 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
491 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
492 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
493 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
496 if (state
->alpha_to_coverage
)
497 blend
->need_src_alpha_4bit
|= 0xf;
499 blend
->cb_target_mask
= 0;
500 blend
->cb_target_enabled_4bit
= 0;
502 for (int i
= 0; i
< 8; i
++) {
503 /* state->rt entries > 0 only written if independent blending */
504 const int j
= state
->independent_blend_enable
? i
: 0;
506 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
507 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
508 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
509 unsigned eqA
= state
->rt
[j
].alpha_func
;
510 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
511 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
513 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
514 unsigned blend_cntl
= 0;
516 sx_mrt_blend_opt
[i
] =
517 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
518 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
520 /* Only set dual source blending for MRT0 to avoid a hang. */
521 if (i
>= 1 && blend
->dual_src_blend
) {
522 /* Vulkan does this for dual source blending. */
524 blend_cntl
|= S_028780_ENABLE(1);
526 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
530 /* Only addition and subtraction equations are supported with
531 * dual source blending.
533 if (blend
->dual_src_blend
&&
534 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
535 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
536 assert(!"Unsupported equation for dual source blending");
537 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
541 /* cb_render_state will disable unused ones */
542 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
543 if (state
->rt
[j
].colormask
)
544 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
546 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
547 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
551 si_blend_check_commutativity(sctx
->screen
, blend
,
552 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
553 si_blend_check_commutativity(sctx
->screen
, blend
,
554 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
556 /* Blending optimizations for RB+.
557 * These transformations don't change the behavior.
559 * First, get rid of DST in the blend factors:
560 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
562 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
563 PIPE_BLENDFACTOR_DST_COLOR
,
564 PIPE_BLENDFACTOR_SRC_COLOR
);
565 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
566 PIPE_BLENDFACTOR_DST_COLOR
,
567 PIPE_BLENDFACTOR_SRC_COLOR
);
568 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
569 PIPE_BLENDFACTOR_DST_ALPHA
,
570 PIPE_BLENDFACTOR_SRC_ALPHA
);
572 /* Look up the ideal settings from tables. */
573 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
574 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
575 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
576 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
578 /* Handle interdependencies. */
579 if (si_blend_factor_uses_dst(srcRGB
))
580 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
581 if (si_blend_factor_uses_dst(srcA
))
582 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
584 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
585 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
586 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
587 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
588 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
590 /* Set the final value. */
591 sx_mrt_blend_opt
[i
] =
592 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
593 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
594 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
595 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
596 S_028760_ALPHA_DST_OPT(dstA_opt
) |
597 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
599 /* Set blend state. */
600 blend_cntl
|= S_028780_ENABLE(1);
601 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
602 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
603 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
605 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
606 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
607 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
608 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
609 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
611 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
613 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
615 /* This is only important for formats without alpha. */
616 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
617 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
618 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
619 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
620 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
621 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
622 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
625 if (blend
->cb_target_mask
) {
626 color_control
|= S_028808_MODE(mode
);
628 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
631 if (sctx
->screen
->has_rbplus
) {
632 /* Disable RB+ blend optimizations for dual source blending.
635 if (blend
->dual_src_blend
) {
636 for (int i
= 0; i
< 8; i
++) {
637 sx_mrt_blend_opt
[i
] =
638 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
639 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
643 for (int i
= 0; i
< 8; i
++)
644 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
645 sx_mrt_blend_opt
[i
]);
647 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
648 if (blend
->dual_src_blend
|| state
->logicop_enable
||
649 mode
== V_028808_CB_RESOLVE
)
650 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
653 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
657 static void *si_create_blend_state(struct pipe_context
*ctx
,
658 const struct pipe_blend_state
*state
)
660 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
663 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
665 struct si_context
*sctx
= (struct si_context
*)ctx
;
666 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
667 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
672 si_pm4_bind_state(sctx
, blend
, state
);
675 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
676 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
677 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
678 sctx
->framebuffer
.nr_samples
>= 2 &&
679 sctx
->screen
->dcc_msaa_allowed
))
680 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
683 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
684 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
685 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
686 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
687 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
688 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
689 sctx
->do_update_shaders
= true;
691 if (sctx
->screen
->dpbb_allowed
&&
693 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
694 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
695 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
696 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
698 if (sctx
->screen
->has_out_of_order_rast
&&
700 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
701 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
702 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
703 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
704 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
707 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
709 struct si_context
*sctx
= (struct si_context
*)ctx
;
710 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
713 static void si_set_blend_color(struct pipe_context
*ctx
,
714 const struct pipe_blend_color
*state
)
716 struct si_context
*sctx
= (struct si_context
*)ctx
;
717 static const struct pipe_blend_color zeros
;
719 sctx
->blend_color
.state
= *state
;
720 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
721 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
724 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
726 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
728 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
729 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
736 static void si_set_clip_state(struct pipe_context
*ctx
,
737 const struct pipe_clip_state
*state
)
739 struct si_context
*sctx
= (struct si_context
*)ctx
;
740 struct pipe_constant_buffer cb
;
741 static const struct pipe_clip_state zeros
;
743 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
746 sctx
->clip_state
.state
= *state
;
747 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
748 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
751 cb
.user_buffer
= state
->ucp
;
752 cb
.buffer_offset
= 0;
753 cb
.buffer_size
= 4*4*8;
754 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
755 pipe_resource_reference(&cb
.buffer
, NULL
);
758 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
760 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
762 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
763 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
766 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
768 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
769 struct si_shader
*vs
= si_get_vs_state(sctx
);
770 struct si_shader_selector
*vs_sel
= vs
->selector
;
771 struct tgsi_shader_info
*info
= &vs_sel
->info
;
772 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
773 unsigned window_space
=
774 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
775 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
776 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
777 unsigned culldist_mask
= vs_sel
->culldist_mask
;
780 if (vs
->key
.opt
.clip_disable
) {
781 assert(!info
->culldist_writemask
);
785 total_mask
= clipdist_mask
| culldist_mask
;
787 /* Clip distances on points have no effect, so need to be implemented
788 * as cull distances. This applies for the clipvertex case as well.
790 * Setting this for primitives other than points should have no adverse
793 clipdist_mask
&= rs
->clip_plane_enable
;
794 culldist_mask
|= clipdist_mask
;
796 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
797 vs_sel
->pa_cl_vs_out_cntl
|
798 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
799 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
800 clipdist_mask
| (culldist_mask
<< 8));
801 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
802 rs
->pa_cl_clip_cntl
|
804 S_028810_CLIP_DISABLE(window_space
));
808 * inferred state between framebuffer and rasterizer
810 static void si_update_poly_offset_state(struct si_context
*sctx
)
812 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
814 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
815 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
819 /* Use the user format, not db_render_format, so that the polygon
820 * offset behaves as expected by applications.
822 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
823 case PIPE_FORMAT_Z16_UNORM
:
824 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
826 default: /* 24-bit */
827 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
829 case PIPE_FORMAT_Z32_FLOAT
:
830 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
831 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
840 static uint32_t si_translate_fill(uint32_t func
)
843 case PIPE_POLYGON_MODE_FILL
:
844 return V_028814_X_DRAW_TRIANGLES
;
845 case PIPE_POLYGON_MODE_LINE
:
846 return V_028814_X_DRAW_LINES
;
847 case PIPE_POLYGON_MODE_POINT
:
848 return V_028814_X_DRAW_POINTS
;
851 return V_028814_X_DRAW_POINTS
;
855 static void *si_create_rs_state(struct pipe_context
*ctx
,
856 const struct pipe_rasterizer_state
*state
)
858 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
859 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
860 struct si_pm4_state
*pm4
= &rs
->pm4
;
862 float psize_min
, psize_max
;
868 rs
->scissor_enable
= state
->scissor
;
869 rs
->clip_halfz
= state
->clip_halfz
;
870 rs
->two_side
= state
->light_twoside
;
871 rs
->multisample_enable
= state
->multisample
;
872 rs
->force_persample_interp
= state
->force_persample_interp
;
873 rs
->clip_plane_enable
= state
->clip_plane_enable
;
874 rs
->line_stipple_enable
= state
->line_stipple_enable
;
875 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
876 rs
->line_smooth
= state
->line_smooth
;
877 rs
->line_width
= state
->line_width
;
878 rs
->poly_smooth
= state
->poly_smooth
;
879 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
881 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
882 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
883 rs
->flatshade
= state
->flatshade
;
884 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
885 rs
->rasterizer_discard
= state
->rasterizer_discard
;
886 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
887 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
888 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
889 rs
->pa_cl_clip_cntl
=
890 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
891 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
892 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
893 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
894 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
896 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
897 S_0286D4_FLAT_SHADE_ENA(1) |
898 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
899 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
902 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
903 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
905 /* point size 12.4 fixed point */
906 tmp
= (unsigned)(state
->point_size
* 8.0);
907 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
909 if (state
->point_size_per_vertex
) {
910 psize_min
= util_get_min_point_size(state
);
913 /* Force the point size to be as if the vertex output was disabled. */
914 psize_min
= state
->point_size
;
915 psize_max
= state
->point_size
;
917 rs
->max_point_size
= psize_max
;
919 /* Divide by two, because 0.5 = 1 pixel. */
920 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
921 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
922 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
924 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
925 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
926 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
927 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
928 S_028A48_MSAA_ENABLE(state
->multisample
||
929 state
->poly_smooth
||
930 state
->line_smooth
) |
931 S_028A48_VPORT_SCISSOR_ENABLE(1) |
932 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
934 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
935 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
936 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
938 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
939 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
940 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
941 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
942 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
943 S_028814_FACE(!state
->front_ccw
) |
944 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
945 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
946 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
947 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
948 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
949 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
950 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
952 if (!rs
->uses_poly_offset
)
955 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
956 if (!rs
->pm4_poly_offset
) {
961 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
962 for (i
= 0; i
< 3; i
++) {
963 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
964 float offset_units
= state
->offset_units
;
965 float offset_scale
= state
->offset_scale
* 16.0f
;
966 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
968 if (!state
->offset_units_unscaled
) {
970 case 0: /* 16-bit zbuffer */
971 offset_units
*= 4.0f
;
972 pa_su_poly_offset_db_fmt_cntl
=
973 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
975 case 1: /* 24-bit zbuffer */
976 offset_units
*= 2.0f
;
977 pa_su_poly_offset_db_fmt_cntl
=
978 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
980 case 2: /* 32-bit zbuffer */
981 offset_units
*= 1.0f
;
982 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
983 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
988 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
990 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
992 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
994 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
996 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
997 pa_su_poly_offset_db_fmt_cntl
);
1003 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1005 struct si_context
*sctx
= (struct si_context
*)ctx
;
1006 struct si_state_rasterizer
*old_rs
=
1007 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1008 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1013 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1014 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1016 /* Update the small primitive filter workaround if necessary. */
1017 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1018 sctx
->framebuffer
.nr_samples
> 1)
1019 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
1022 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1023 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1025 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1026 si_update_poly_offset_state(sctx
);
1029 (old_rs
->scissor_enable
!= rs
->scissor_enable
||
1030 old_rs
->line_width
!= rs
->line_width
||
1031 old_rs
->max_point_size
!= rs
->max_point_size
)) {
1032 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1033 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
1037 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1038 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1039 si_mark_atom_dirty(sctx
, &sctx
->viewports
.atom
);
1043 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1044 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1045 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1047 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1048 rs
->line_stipple_enable
;
1051 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1052 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1053 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1054 old_rs
->flatshade
!= rs
->flatshade
||
1055 old_rs
->two_side
!= rs
->two_side
||
1056 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1057 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1058 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1059 old_rs
->line_smooth
!= rs
->line_smooth
||
1060 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1061 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1062 sctx
->do_update_shaders
= true;
1065 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1067 struct si_context
*sctx
= (struct si_context
*)ctx
;
1068 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1070 if (sctx
->queued
.named
.rasterizer
== state
)
1071 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1073 FREE(rs
->pm4_poly_offset
);
1074 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1078 * infeered state between dsa and stencil ref
1080 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
1082 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
1083 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1084 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1086 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1087 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1088 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1089 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1090 S_028430_STENCILOPVAL(1));
1091 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1092 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1093 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1094 S_028434_STENCILOPVAL_BF(1));
1097 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1098 const struct pipe_stencil_ref
*state
)
1100 struct si_context
*sctx
= (struct si_context
*)ctx
;
1102 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1105 sctx
->stencil_ref
.state
= *state
;
1106 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1114 static uint32_t si_translate_stencil_op(int s_op
)
1117 case PIPE_STENCIL_OP_KEEP
:
1118 return V_02842C_STENCIL_KEEP
;
1119 case PIPE_STENCIL_OP_ZERO
:
1120 return V_02842C_STENCIL_ZERO
;
1121 case PIPE_STENCIL_OP_REPLACE
:
1122 return V_02842C_STENCIL_REPLACE_TEST
;
1123 case PIPE_STENCIL_OP_INCR
:
1124 return V_02842C_STENCIL_ADD_CLAMP
;
1125 case PIPE_STENCIL_OP_DECR
:
1126 return V_02842C_STENCIL_SUB_CLAMP
;
1127 case PIPE_STENCIL_OP_INCR_WRAP
:
1128 return V_02842C_STENCIL_ADD_WRAP
;
1129 case PIPE_STENCIL_OP_DECR_WRAP
:
1130 return V_02842C_STENCIL_SUB_WRAP
;
1131 case PIPE_STENCIL_OP_INVERT
:
1132 return V_02842C_STENCIL_INVERT
;
1134 PRINT_ERR("Unknown stencil op %d", s_op
);
1141 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1143 return s
->enabled
&& s
->writemask
&&
1144 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1145 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1146 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1149 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1151 /* REPLACE is normally order invariant, except when the stencil
1152 * reference value is written by the fragment shader. Tracking this
1153 * interaction does not seem worth the effort, so be conservative. */
1154 return op
!= PIPE_STENCIL_OP_INCR
&&
1155 op
!= PIPE_STENCIL_OP_DECR
&&
1156 op
!= PIPE_STENCIL_OP_REPLACE
;
1159 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1160 * invariant in the sense that the set of passing fragments as well as the
1161 * final stencil buffer result does not depend on the order of fragments. */
1162 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1164 return !state
->enabled
|| !state
->writemask
||
1165 /* The following assumes that Z writes are disabled. */
1166 (state
->func
== PIPE_FUNC_ALWAYS
&&
1167 si_order_invariant_stencil_op(state
->zpass_op
) &&
1168 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1169 (state
->func
== PIPE_FUNC_NEVER
&&
1170 si_order_invariant_stencil_op(state
->fail_op
));
1173 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1174 const struct pipe_depth_stencil_alpha_state
*state
)
1176 struct si_context
*sctx
= (struct si_context
*)ctx
;
1177 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1178 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1179 unsigned db_depth_control
;
1180 uint32_t db_stencil_control
= 0;
1186 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1187 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1188 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1189 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1191 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1192 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1193 S_028800_ZFUNC(state
->depth
.func
) |
1194 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1197 if (state
->stencil
[0].enabled
) {
1198 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1199 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1200 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1201 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1202 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1204 if (state
->stencil
[1].enabled
) {
1205 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1206 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1207 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1208 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1209 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1214 if (state
->alpha
.enabled
) {
1215 dsa
->alpha_func
= state
->alpha
.func
;
1217 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1218 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1220 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1223 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1224 if (state
->stencil
[0].enabled
)
1225 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1226 if (state
->depth
.bounds_test
) {
1227 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1228 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1231 dsa
->depth_enabled
= state
->depth
.enabled
;
1232 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1233 state
->depth
.writemask
;
1234 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1235 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1236 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1237 si_dsa_writes_stencil(&state
->stencil
[1]));
1238 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1239 dsa
->stencil_write_enabled
;
1241 bool zfunc_is_ordered
=
1242 state
->depth
.func
== PIPE_FUNC_NEVER
||
1243 state
->depth
.func
== PIPE_FUNC_LESS
||
1244 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1245 state
->depth
.func
== PIPE_FUNC_GREATER
||
1246 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1248 bool nozwrite_and_order_invariant_stencil
=
1249 !dsa
->db_can_write
||
1250 (!dsa
->depth_write_enabled
&&
1251 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1252 si_order_invariant_stencil_state(&state
->stencil
[1]));
1254 dsa
->order_invariance
[1].zs
=
1255 nozwrite_and_order_invariant_stencil
||
1256 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1257 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1259 dsa
->order_invariance
[1].pass_set
=
1260 nozwrite_and_order_invariant_stencil
||
1261 (!dsa
->stencil_write_enabled
&&
1262 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1263 state
->depth
.func
== PIPE_FUNC_NEVER
));
1264 dsa
->order_invariance
[0].pass_set
=
1265 !dsa
->depth_write_enabled
||
1266 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1267 state
->depth
.func
== PIPE_FUNC_NEVER
);
1269 dsa
->order_invariance
[1].pass_last
=
1270 sctx
->screen
->assume_no_z_fights
&&
1271 !dsa
->stencil_write_enabled
&&
1272 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1273 dsa
->order_invariance
[0].pass_last
=
1274 sctx
->screen
->assume_no_z_fights
&&
1275 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1280 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1282 struct si_context
*sctx
= (struct si_context
*)ctx
;
1283 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1284 struct si_state_dsa
*dsa
= state
;
1289 si_pm4_bind_state(sctx
, dsa
, dsa
);
1291 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1292 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1293 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1294 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1297 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1298 sctx
->do_update_shaders
= true;
1300 if (sctx
->screen
->dpbb_allowed
&&
1302 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1303 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1304 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1305 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
1307 if (sctx
->screen
->has_out_of_order_rast
&&
1309 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1310 sizeof(old_dsa
->order_invariance
))))
1311 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1314 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1316 struct si_context
*sctx
= (struct si_context
*)ctx
;
1317 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1320 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1322 struct pipe_depth_stencil_alpha_state dsa
= {};
1324 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1327 /* DB RENDER STATE */
1329 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1331 struct si_context
*sctx
= (struct si_context
*)ctx
;
1333 /* Pipeline stat & streamout queries. */
1335 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1336 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1338 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1339 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1342 /* Occlusion queries. */
1343 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1344 sctx
->occlusion_queries_disabled
= !enable
;
1345 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1349 void si_set_occlusion_query_state(struct si_context
*sctx
,
1350 bool old_perfect_enable
)
1352 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1354 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1356 if (perfect_enable
!= old_perfect_enable
)
1357 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1360 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1362 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1364 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1365 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1368 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1370 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
1371 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1372 unsigned db_shader_control
;
1374 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1376 /* DB_RENDER_CONTROL */
1377 if (sctx
->dbcb_depth_copy_enabled
||
1378 sctx
->dbcb_stencil_copy_enabled
) {
1380 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1381 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1382 S_028000_COPY_CENTROID(1) |
1383 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1384 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1386 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1387 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1390 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1391 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1394 /* DB_COUNT_CONTROL (occlusion queries) */
1395 if (sctx
->num_occlusion_queries
> 0 &&
1396 !sctx
->occlusion_queries_disabled
) {
1397 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1399 if (sctx
->chip_class
>= CIK
) {
1401 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1402 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1403 S_028004_ZPASS_ENABLE(1) |
1404 S_028004_SLICE_EVEN_ENABLE(1) |
1405 S_028004_SLICE_ODD_ENABLE(1));
1408 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1409 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1412 /* Disable occlusion queries. */
1413 if (sctx
->chip_class
>= CIK
) {
1416 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1420 /* DB_RENDER_OVERRIDE2 */
1421 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1422 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1423 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1424 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1426 db_shader_control
= sctx
->ps_db_shader_control
;
1428 /* Bug workaround for smoothing (overrasterization) on SI. */
1429 if (sctx
->chip_class
== SI
&& sctx
->smoothing_enabled
) {
1430 db_shader_control
&= C_02880C_Z_ORDER
;
1431 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1434 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1435 if (!rs
|| !rs
->multisample_enable
)
1436 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1438 if (sctx
->screen
->has_rbplus
&&
1439 !sctx
->screen
->rbplus_allowed
)
1440 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1442 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1447 * format translation
1449 static uint32_t si_translate_colorformat(enum pipe_format format
)
1451 const struct util_format_description
*desc
= util_format_description(format
);
1453 return V_028C70_COLOR_INVALID
;
1455 #define HAS_SIZE(x,y,z,w) \
1456 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1457 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1459 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1460 return V_028C70_COLOR_10_11_11
;
1462 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1463 return V_028C70_COLOR_INVALID
;
1465 /* hw cannot support mixed formats (except depth/stencil, since
1466 * stencil is not written to). */
1467 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1468 return V_028C70_COLOR_INVALID
;
1470 switch (desc
->nr_channels
) {
1472 switch (desc
->channel
[0].size
) {
1474 return V_028C70_COLOR_8
;
1476 return V_028C70_COLOR_16
;
1478 return V_028C70_COLOR_32
;
1482 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1483 switch (desc
->channel
[0].size
) {
1485 return V_028C70_COLOR_8_8
;
1487 return V_028C70_COLOR_16_16
;
1489 return V_028C70_COLOR_32_32
;
1491 } else if (HAS_SIZE(8,24,0,0)) {
1492 return V_028C70_COLOR_24_8
;
1493 } else if (HAS_SIZE(24,8,0,0)) {
1494 return V_028C70_COLOR_8_24
;
1498 if (HAS_SIZE(5,6,5,0)) {
1499 return V_028C70_COLOR_5_6_5
;
1500 } else if (HAS_SIZE(32,8,24,0)) {
1501 return V_028C70_COLOR_X24_8_32_FLOAT
;
1505 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1506 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1507 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1508 switch (desc
->channel
[0].size
) {
1510 return V_028C70_COLOR_4_4_4_4
;
1512 return V_028C70_COLOR_8_8_8_8
;
1514 return V_028C70_COLOR_16_16_16_16
;
1516 return V_028C70_COLOR_32_32_32_32
;
1518 } else if (HAS_SIZE(5,5,5,1)) {
1519 return V_028C70_COLOR_1_5_5_5
;
1520 } else if (HAS_SIZE(1,5,5,5)) {
1521 return V_028C70_COLOR_5_5_5_1
;
1522 } else if (HAS_SIZE(10,10,10,2)) {
1523 return V_028C70_COLOR_2_10_10_10
;
1527 return V_028C70_COLOR_INVALID
;
1530 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1532 if (SI_BIG_ENDIAN
) {
1533 switch(colorformat
) {
1534 /* 8-bit buffers. */
1535 case V_028C70_COLOR_8
:
1536 return V_028C70_ENDIAN_NONE
;
1538 /* 16-bit buffers. */
1539 case V_028C70_COLOR_5_6_5
:
1540 case V_028C70_COLOR_1_5_5_5
:
1541 case V_028C70_COLOR_4_4_4_4
:
1542 case V_028C70_COLOR_16
:
1543 case V_028C70_COLOR_8_8
:
1544 return V_028C70_ENDIAN_8IN16
;
1546 /* 32-bit buffers. */
1547 case V_028C70_COLOR_8_8_8_8
:
1548 case V_028C70_COLOR_2_10_10_10
:
1549 case V_028C70_COLOR_8_24
:
1550 case V_028C70_COLOR_24_8
:
1551 case V_028C70_COLOR_16_16
:
1552 return V_028C70_ENDIAN_8IN32
;
1554 /* 64-bit buffers. */
1555 case V_028C70_COLOR_16_16_16_16
:
1556 return V_028C70_ENDIAN_8IN16
;
1558 case V_028C70_COLOR_32_32
:
1559 return V_028C70_ENDIAN_8IN32
;
1561 /* 128-bit buffers. */
1562 case V_028C70_COLOR_32_32_32_32
:
1563 return V_028C70_ENDIAN_8IN32
;
1565 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1568 return V_028C70_ENDIAN_NONE
;
1572 static uint32_t si_translate_dbformat(enum pipe_format format
)
1575 case PIPE_FORMAT_Z16_UNORM
:
1576 return V_028040_Z_16
;
1577 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1578 case PIPE_FORMAT_X8Z24_UNORM
:
1579 case PIPE_FORMAT_Z24X8_UNORM
:
1580 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1581 return V_028040_Z_24
; /* deprecated on SI */
1582 case PIPE_FORMAT_Z32_FLOAT
:
1583 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1584 return V_028040_Z_32_FLOAT
;
1586 return V_028040_Z_INVALID
;
1591 * Texture translation
1594 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1595 enum pipe_format format
,
1596 const struct util_format_description
*desc
,
1599 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1600 bool enable_compressed_formats
= (sscreen
->info
.drm_major
== 2 &&
1601 sscreen
->info
.drm_minor
>= 31) ||
1602 sscreen
->info
.drm_major
== 3;
1603 bool uniform
= true;
1606 /* Colorspace (return non-RGB formats directly). */
1607 switch (desc
->colorspace
) {
1608 /* Depth stencil formats */
1609 case UTIL_FORMAT_COLORSPACE_ZS
:
1611 case PIPE_FORMAT_Z16_UNORM
:
1612 return V_008F14_IMG_DATA_FORMAT_16
;
1613 case PIPE_FORMAT_X24S8_UINT
:
1614 case PIPE_FORMAT_S8X24_UINT
:
1616 * Implemented as an 8_8_8_8 data format to fix texture
1617 * gathers in stencil sampling. This affects at least
1618 * GL45-CTS.texture_cube_map_array.sampling on VI.
1620 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1621 case PIPE_FORMAT_Z24X8_UNORM
:
1622 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1623 return V_008F14_IMG_DATA_FORMAT_8_24
;
1624 case PIPE_FORMAT_X8Z24_UNORM
:
1625 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1626 return V_008F14_IMG_DATA_FORMAT_24_8
;
1627 case PIPE_FORMAT_S8_UINT
:
1628 return V_008F14_IMG_DATA_FORMAT_8
;
1629 case PIPE_FORMAT_Z32_FLOAT
:
1630 return V_008F14_IMG_DATA_FORMAT_32
;
1631 case PIPE_FORMAT_X32_S8X24_UINT
:
1632 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1633 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1638 case UTIL_FORMAT_COLORSPACE_YUV
:
1639 goto out_unknown
; /* TODO */
1641 case UTIL_FORMAT_COLORSPACE_SRGB
:
1642 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1650 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1651 if (!enable_compressed_formats
)
1655 case PIPE_FORMAT_RGTC1_SNORM
:
1656 case PIPE_FORMAT_LATC1_SNORM
:
1657 case PIPE_FORMAT_RGTC1_UNORM
:
1658 case PIPE_FORMAT_LATC1_UNORM
:
1659 return V_008F14_IMG_DATA_FORMAT_BC4
;
1660 case PIPE_FORMAT_RGTC2_SNORM
:
1661 case PIPE_FORMAT_LATC2_SNORM
:
1662 case PIPE_FORMAT_RGTC2_UNORM
:
1663 case PIPE_FORMAT_LATC2_UNORM
:
1664 return V_008F14_IMG_DATA_FORMAT_BC5
;
1670 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1671 (sscreen
->info
.family
== CHIP_STONEY
||
1672 sscreen
->info
.family
== CHIP_VEGA10
||
1673 sscreen
->info
.family
== CHIP_RAVEN
)) {
1675 case PIPE_FORMAT_ETC1_RGB8
:
1676 case PIPE_FORMAT_ETC2_RGB8
:
1677 case PIPE_FORMAT_ETC2_SRGB8
:
1678 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1679 case PIPE_FORMAT_ETC2_RGB8A1
:
1680 case PIPE_FORMAT_ETC2_SRGB8A1
:
1681 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1682 case PIPE_FORMAT_ETC2_RGBA8
:
1683 case PIPE_FORMAT_ETC2_SRGBA8
:
1684 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1685 case PIPE_FORMAT_ETC2_R11_UNORM
:
1686 case PIPE_FORMAT_ETC2_R11_SNORM
:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1688 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1689 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1690 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1696 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1697 if (!enable_compressed_formats
)
1701 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1702 case PIPE_FORMAT_BPTC_SRGBA
:
1703 return V_008F14_IMG_DATA_FORMAT_BC7
;
1704 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1705 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1706 return V_008F14_IMG_DATA_FORMAT_BC6
;
1712 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1714 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1715 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1716 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1717 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1718 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1719 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1725 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1726 if (!enable_compressed_formats
)
1730 case PIPE_FORMAT_DXT1_RGB
:
1731 case PIPE_FORMAT_DXT1_RGBA
:
1732 case PIPE_FORMAT_DXT1_SRGB
:
1733 case PIPE_FORMAT_DXT1_SRGBA
:
1734 return V_008F14_IMG_DATA_FORMAT_BC1
;
1735 case PIPE_FORMAT_DXT3_RGBA
:
1736 case PIPE_FORMAT_DXT3_SRGBA
:
1737 return V_008F14_IMG_DATA_FORMAT_BC2
;
1738 case PIPE_FORMAT_DXT5_RGBA
:
1739 case PIPE_FORMAT_DXT5_SRGBA
:
1740 return V_008F14_IMG_DATA_FORMAT_BC3
;
1746 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1747 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1748 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1749 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1752 /* R8G8Bx_SNORM - TODO CxV8U8 */
1754 /* hw cannot support mixed formats (except depth/stencil, since only
1756 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1759 /* See whether the components are of the same size. */
1760 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1761 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1764 /* Non-uniform formats. */
1766 switch(desc
->nr_channels
) {
1768 if (desc
->channel
[0].size
== 5 &&
1769 desc
->channel
[1].size
== 6 &&
1770 desc
->channel
[2].size
== 5) {
1771 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1775 if (desc
->channel
[0].size
== 5 &&
1776 desc
->channel
[1].size
== 5 &&
1777 desc
->channel
[2].size
== 5 &&
1778 desc
->channel
[3].size
== 1) {
1779 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1781 if (desc
->channel
[0].size
== 1 &&
1782 desc
->channel
[1].size
== 5 &&
1783 desc
->channel
[2].size
== 5 &&
1784 desc
->channel
[3].size
== 5) {
1785 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1787 if (desc
->channel
[0].size
== 10 &&
1788 desc
->channel
[1].size
== 10 &&
1789 desc
->channel
[2].size
== 10 &&
1790 desc
->channel
[3].size
== 2) {
1791 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1798 if (first_non_void
< 0 || first_non_void
> 3)
1801 /* uniform formats */
1802 switch (desc
->channel
[first_non_void
].size
) {
1804 switch (desc
->nr_channels
) {
1805 #if 0 /* Not supported for render targets */
1807 return V_008F14_IMG_DATA_FORMAT_4_4
;
1810 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1814 switch (desc
->nr_channels
) {
1816 return V_008F14_IMG_DATA_FORMAT_8
;
1818 return V_008F14_IMG_DATA_FORMAT_8_8
;
1820 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1824 switch (desc
->nr_channels
) {
1826 return V_008F14_IMG_DATA_FORMAT_16
;
1828 return V_008F14_IMG_DATA_FORMAT_16_16
;
1830 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1834 switch (desc
->nr_channels
) {
1836 return V_008F14_IMG_DATA_FORMAT_32
;
1838 return V_008F14_IMG_DATA_FORMAT_32_32
;
1839 #if 0 /* Not supported for render targets */
1841 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1844 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1849 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1853 static unsigned si_tex_wrap(unsigned wrap
)
1857 case PIPE_TEX_WRAP_REPEAT
:
1858 return V_008F30_SQ_TEX_WRAP
;
1859 case PIPE_TEX_WRAP_CLAMP
:
1860 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1861 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1862 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1863 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1864 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1865 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1866 return V_008F30_SQ_TEX_MIRROR
;
1867 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1868 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1869 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1870 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1871 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1872 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1876 static unsigned si_tex_mipfilter(unsigned filter
)
1879 case PIPE_TEX_MIPFILTER_NEAREST
:
1880 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1881 case PIPE_TEX_MIPFILTER_LINEAR
:
1882 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1884 case PIPE_TEX_MIPFILTER_NONE
:
1885 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1889 static unsigned si_tex_compare(unsigned compare
)
1893 case PIPE_FUNC_NEVER
:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1895 case PIPE_FUNC_LESS
:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1897 case PIPE_FUNC_EQUAL
:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1899 case PIPE_FUNC_LEQUAL
:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1901 case PIPE_FUNC_GREATER
:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1903 case PIPE_FUNC_NOTEQUAL
:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1905 case PIPE_FUNC_GEQUAL
:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1907 case PIPE_FUNC_ALWAYS
:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1912 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1913 unsigned view_target
, unsigned nr_samples
)
1915 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1917 if (view_target
== PIPE_TEXTURE_CUBE
||
1918 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1919 res_target
= view_target
;
1920 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1921 else if (res_target
== PIPE_TEXTURE_CUBE
||
1922 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1923 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1925 /* GFX9 allocates 1D textures as 2D. */
1926 if ((res_target
== PIPE_TEXTURE_1D
||
1927 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1928 sscreen
->info
.chip_class
>= GFX9
&&
1929 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1930 if (res_target
== PIPE_TEXTURE_1D
)
1931 res_target
= PIPE_TEXTURE_2D
;
1933 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1936 switch (res_target
) {
1938 case PIPE_TEXTURE_1D
:
1939 return V_008F1C_SQ_RSRC_IMG_1D
;
1940 case PIPE_TEXTURE_1D_ARRAY
:
1941 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1942 case PIPE_TEXTURE_2D
:
1943 case PIPE_TEXTURE_RECT
:
1944 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1945 V_008F1C_SQ_RSRC_IMG_2D
;
1946 case PIPE_TEXTURE_2D_ARRAY
:
1947 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1948 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1949 case PIPE_TEXTURE_3D
:
1950 return V_008F1C_SQ_RSRC_IMG_3D
;
1951 case PIPE_TEXTURE_CUBE
:
1952 case PIPE_TEXTURE_CUBE_ARRAY
:
1953 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1958 * Format support testing
1961 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1963 const struct util_format_description
*desc
= util_format_description(format
);
1967 return si_translate_texformat(screen
, format
, desc
,
1968 util_format_get_first_non_void_channel(format
)) != ~0U;
1971 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1972 const struct util_format_description
*desc
,
1977 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1978 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1980 assert(first_non_void
>= 0);
1982 if (desc
->nr_channels
== 4 &&
1983 desc
->channel
[0].size
== 10 &&
1984 desc
->channel
[1].size
== 10 &&
1985 desc
->channel
[2].size
== 10 &&
1986 desc
->channel
[3].size
== 2)
1987 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1989 /* See whether the components are of the same size. */
1990 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1991 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1992 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1995 switch (desc
->channel
[first_non_void
].size
) {
1997 switch (desc
->nr_channels
) {
1999 case 3: /* 3 loads */
2000 return V_008F0C_BUF_DATA_FORMAT_8
;
2002 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2004 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2008 switch (desc
->nr_channels
) {
2010 case 3: /* 3 loads */
2011 return V_008F0C_BUF_DATA_FORMAT_16
;
2013 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2015 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2019 switch (desc
->nr_channels
) {
2021 return V_008F0C_BUF_DATA_FORMAT_32
;
2023 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2025 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2027 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2031 /* Legacy double formats. */
2032 switch (desc
->nr_channels
) {
2033 case 1: /* 1 load */
2034 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2035 case 2: /* 1 load */
2036 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2037 case 3: /* 3 loads */
2038 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2039 case 4: /* 2 loads */
2040 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2045 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2048 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2049 const struct util_format_description
*desc
,
2052 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2053 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2055 assert(first_non_void
>= 0);
2057 switch (desc
->channel
[first_non_void
].type
) {
2058 case UTIL_FORMAT_TYPE_SIGNED
:
2059 case UTIL_FORMAT_TYPE_FIXED
:
2060 if (desc
->channel
[first_non_void
].size
>= 32 ||
2061 desc
->channel
[first_non_void
].pure_integer
)
2062 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2063 else if (desc
->channel
[first_non_void
].normalized
)
2064 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2066 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2068 case UTIL_FORMAT_TYPE_UNSIGNED
:
2069 if (desc
->channel
[first_non_void
].size
>= 32 ||
2070 desc
->channel
[first_non_void
].pure_integer
)
2071 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2072 else if (desc
->channel
[first_non_void
].normalized
)
2073 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2075 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2077 case UTIL_FORMAT_TYPE_FLOAT
:
2079 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2083 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2084 enum pipe_format format
,
2087 const struct util_format_description
*desc
;
2089 unsigned data_format
;
2091 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2092 PIPE_BIND_SAMPLER_VIEW
|
2093 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2095 desc
= util_format_description(format
);
2099 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2100 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2101 * for read-only access (with caveats surrounding bounds checks), but
2102 * obviously fails for write access which we have to implement for
2103 * shader images. Luckily, OpenGL doesn't expect this to be supported
2104 * anyway, and so the only impact is on PBO uploads / downloads, which
2105 * shouldn't be expected to be fast for GL_RGB anyway.
2107 if (desc
->block
.bits
== 3 * 8 ||
2108 desc
->block
.bits
== 3 * 16) {
2109 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2110 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2116 first_non_void
= util_format_get_first_non_void_channel(format
);
2117 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2118 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2124 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2126 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2127 si_translate_colorswap(format
, false) != ~0U;
2130 static bool si_is_zs_format_supported(enum pipe_format format
)
2132 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2135 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2136 enum pipe_format format
,
2137 enum pipe_texture_target target
,
2138 unsigned sample_count
,
2141 unsigned retval
= 0;
2143 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2144 PRINT_ERR("r600: unsupported texture type %d\n", target
);
2148 if (!util_format_is_supported(format
, usage
))
2151 if (sample_count
> 1) {
2152 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2155 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2158 switch (sample_count
) {
2164 if (format
== PIPE_FORMAT_NONE
)
2173 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2174 PIPE_BIND_SHADER_IMAGE
)) {
2175 if (target
== PIPE_BUFFER
) {
2176 retval
|= si_is_vertex_format_supported(
2177 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2178 PIPE_BIND_SHADER_IMAGE
));
2180 if (si_is_sampler_format_supported(screen
, format
))
2181 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2182 PIPE_BIND_SHADER_IMAGE
);
2186 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2187 PIPE_BIND_DISPLAY_TARGET
|
2190 PIPE_BIND_BLENDABLE
)) &&
2191 si_is_colorbuffer_format_supported(format
)) {
2193 (PIPE_BIND_RENDER_TARGET
|
2194 PIPE_BIND_DISPLAY_TARGET
|
2197 if (!util_format_is_pure_integer(format
) &&
2198 !util_format_is_depth_or_stencil(format
))
2199 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2202 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2203 si_is_zs_format_supported(format
)) {
2204 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2207 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2208 retval
|= si_is_vertex_format_supported(screen
, format
,
2209 PIPE_BIND_VERTEX_BUFFER
);
2212 if ((usage
& PIPE_BIND_LINEAR
) &&
2213 !util_format_is_compressed(format
) &&
2214 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2215 retval
|= PIPE_BIND_LINEAR
;
2217 return retval
== usage
;
2221 * framebuffer handling
2224 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2225 unsigned format
, unsigned swap
,
2226 unsigned ntype
, bool is_depth
)
2228 /* Alpha is needed for alpha-to-coverage.
2229 * Blending may be with or without alpha.
2231 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2232 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2233 unsigned blend
= 0; /* supports blending, but may not export alpha */
2234 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2236 /* Choose the SPI color formats. These are required values for RB+.
2237 * Other chips have multiple choices, though they are not necessarily better.
2240 case V_028C70_COLOR_5_6_5
:
2241 case V_028C70_COLOR_1_5_5_5
:
2242 case V_028C70_COLOR_5_5_5_1
:
2243 case V_028C70_COLOR_4_4_4_4
:
2244 case V_028C70_COLOR_10_11_11
:
2245 case V_028C70_COLOR_11_11_10
:
2246 case V_028C70_COLOR_8
:
2247 case V_028C70_COLOR_8_8
:
2248 case V_028C70_COLOR_8_8_8_8
:
2249 case V_028C70_COLOR_10_10_10_2
:
2250 case V_028C70_COLOR_2_10_10_10
:
2251 if (ntype
== V_028C70_NUMBER_UINT
)
2252 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2253 else if (ntype
== V_028C70_NUMBER_SINT
)
2254 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2256 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2259 case V_028C70_COLOR_16
:
2260 case V_028C70_COLOR_16_16
:
2261 case V_028C70_COLOR_16_16_16_16
:
2262 if (ntype
== V_028C70_NUMBER_UNORM
||
2263 ntype
== V_028C70_NUMBER_SNORM
) {
2264 /* UNORM16 and SNORM16 don't support blending */
2265 if (ntype
== V_028C70_NUMBER_UNORM
)
2266 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2268 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2270 /* Use 32 bits per channel for blending. */
2271 if (format
== V_028C70_COLOR_16
) {
2272 if (swap
== V_028C70_SWAP_STD
) { /* R */
2273 blend
= V_028714_SPI_SHADER_32_R
;
2274 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2275 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2276 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2279 } else if (format
== V_028C70_COLOR_16_16
) {
2280 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2281 blend
= V_028714_SPI_SHADER_32_GR
;
2282 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2283 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2284 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2287 } else /* 16_16_16_16 */
2288 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2289 } else if (ntype
== V_028C70_NUMBER_UINT
)
2290 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2291 else if (ntype
== V_028C70_NUMBER_SINT
)
2292 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2293 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2294 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2299 case V_028C70_COLOR_32
:
2300 if (swap
== V_028C70_SWAP_STD
) { /* R */
2301 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2302 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2303 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2304 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2309 case V_028C70_COLOR_32_32
:
2310 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2311 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2312 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2313 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2314 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2319 case V_028C70_COLOR_32_32_32_32
:
2320 case V_028C70_COLOR_8_24
:
2321 case V_028C70_COLOR_24_8
:
2322 case V_028C70_COLOR_X24_8_32_FLOAT
:
2323 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2331 /* The DB->CB copy needs 32_ABGR. */
2333 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2335 surf
->spi_shader_col_format
= normal
;
2336 surf
->spi_shader_col_format_alpha
= alpha
;
2337 surf
->spi_shader_col_format_blend
= blend
;
2338 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2341 static void si_initialize_color_surface(struct si_context
*sctx
,
2342 struct r600_surface
*surf
)
2344 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2345 unsigned color_info
, color_attrib
;
2346 unsigned format
, swap
, ntype
, endian
;
2347 const struct util_format_description
*desc
;
2349 unsigned blend_clamp
= 0, blend_bypass
= 0;
2351 desc
= util_format_description(surf
->base
.format
);
2352 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2353 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2357 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2358 ntype
= V_028C70_NUMBER_FLOAT
;
2360 ntype
= V_028C70_NUMBER_UNORM
;
2361 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2362 ntype
= V_028C70_NUMBER_SRGB
;
2363 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2364 if (desc
->channel
[firstchan
].pure_integer
) {
2365 ntype
= V_028C70_NUMBER_SINT
;
2367 assert(desc
->channel
[firstchan
].normalized
);
2368 ntype
= V_028C70_NUMBER_SNORM
;
2370 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2371 if (desc
->channel
[firstchan
].pure_integer
) {
2372 ntype
= V_028C70_NUMBER_UINT
;
2374 assert(desc
->channel
[firstchan
].normalized
);
2375 ntype
= V_028C70_NUMBER_UNORM
;
2380 format
= si_translate_colorformat(surf
->base
.format
);
2381 if (format
== V_028C70_COLOR_INVALID
) {
2382 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2384 assert(format
!= V_028C70_COLOR_INVALID
);
2385 swap
= si_translate_colorswap(surf
->base
.format
, false);
2386 endian
= si_colorformat_endian_swap(format
);
2388 /* blend clamp should be set for all NORM/SRGB types */
2389 if (ntype
== V_028C70_NUMBER_UNORM
||
2390 ntype
== V_028C70_NUMBER_SNORM
||
2391 ntype
== V_028C70_NUMBER_SRGB
)
2394 /* set blend bypass according to docs if SINT/UINT or
2395 8/24 COLOR variants */
2396 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2397 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2398 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2403 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2404 if (format
== V_028C70_COLOR_8
||
2405 format
== V_028C70_COLOR_8_8
||
2406 format
== V_028C70_COLOR_8_8_8_8
)
2407 surf
->color_is_int8
= true;
2408 else if (format
== V_028C70_COLOR_10_10_10_2
||
2409 format
== V_028C70_COLOR_2_10_10_10
)
2410 surf
->color_is_int10
= true;
2413 color_info
= S_028C70_FORMAT(format
) |
2414 S_028C70_COMP_SWAP(swap
) |
2415 S_028C70_BLEND_CLAMP(blend_clamp
) |
2416 S_028C70_BLEND_BYPASS(blend_bypass
) |
2417 S_028C70_SIMPLE_FLOAT(1) |
2418 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2419 ntype
!= V_028C70_NUMBER_SNORM
&&
2420 ntype
!= V_028C70_NUMBER_SRGB
&&
2421 format
!= V_028C70_COLOR_8_24
&&
2422 format
!= V_028C70_COLOR_24_8
) |
2423 S_028C70_NUMBER_TYPE(ntype
) |
2424 S_028C70_ENDIAN(endian
);
2426 /* Intensity is implemented as Red, so treat it that way. */
2427 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2428 util_format_is_intensity(surf
->base
.format
));
2430 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2431 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2433 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2434 S_028C74_NUM_FRAGMENTS(log_samples
);
2436 if (rtex
->fmask
.size
) {
2437 color_info
|= S_028C70_COMPRESSION(1);
2438 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2440 if (sctx
->chip_class
== SI
) {
2441 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2442 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2447 if (sctx
->chip_class
>= VI
) {
2448 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2449 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2451 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2452 64 for APU because all of our APUs to date use DIMMs which have
2453 a request granularity size of 64B while all other chips have a
2455 if (!sctx
->screen
->info
.has_dedicated_vram
)
2456 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2458 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2459 if (rtex
->surface
.bpe
== 1)
2460 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2461 else if (rtex
->surface
.bpe
== 2)
2462 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2465 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2466 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2467 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2470 /* This must be set for fast clear to work without FMASK. */
2471 if (!rtex
->fmask
.size
&& sctx
->chip_class
== SI
) {
2472 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2473 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2476 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2477 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2479 if (sctx
->chip_class
>= GFX9
) {
2480 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2482 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2483 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2484 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2485 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2486 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2487 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2490 surf
->cb_color_view
= color_view
;
2491 surf
->cb_color_info
= color_info
;
2492 surf
->cb_color_attrib
= color_attrib
;
2494 /* Determine pixel shader export format */
2495 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2497 surf
->color_initialized
= true;
2500 static void si_init_depth_surface(struct si_context
*sctx
,
2501 struct r600_surface
*surf
)
2503 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2504 unsigned level
= surf
->base
.u
.tex
.level
;
2505 unsigned format
, stencil_format
;
2506 uint32_t z_info
, s_info
;
2508 format
= si_translate_dbformat(rtex
->db_render_format
);
2509 stencil_format
= rtex
->surface
.has_stencil
?
2510 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2512 assert(format
!= V_028040_Z_INVALID
);
2513 if (format
== V_028040_Z_INVALID
)
2514 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2516 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2517 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2518 surf
->db_htile_data_base
= 0;
2519 surf
->db_htile_surface
= 0;
2521 if (sctx
->chip_class
>= GFX9
) {
2522 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2523 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2524 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2525 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2526 z_info
= S_028038_FORMAT(format
) |
2527 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2528 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2529 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2530 s_info
= S_02803C_FORMAT(stencil_format
) |
2531 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2532 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2533 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2534 surf
->db_depth_view
|= S_028008_MIPID(level
);
2535 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2536 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2538 if (si_htile_enabled(rtex
, level
)) {
2539 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2540 S_028038_ALLOW_EXPCLEAR(1);
2542 if (rtex
->tc_compatible_htile
) {
2543 unsigned max_zplanes
= 4;
2545 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2546 rtex
->resource
.b
.b
.nr_samples
> 1)
2549 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2550 S_028038_ITERATE_FLUSH(1);
2551 s_info
|= S_02803C_ITERATE_FLUSH(1);
2554 if (rtex
->surface
.has_stencil
) {
2555 /* Stencil buffer workaround ported from the SI-CI-VI code.
2556 * See that for explanation.
2558 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2560 /* Use all HTILE for depth if there's no stencil. */
2561 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2564 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2565 rtex
->htile_offset
) >> 8;
2566 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2567 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2568 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2572 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2574 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2576 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2577 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2578 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2579 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2581 z_info
= S_028040_FORMAT(format
) |
2582 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2583 s_info
= S_028044_FORMAT(stencil_format
);
2584 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2586 if (sctx
->chip_class
>= CIK
) {
2587 struct radeon_info
*info
= &sctx
->screen
->info
;
2588 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2589 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2590 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2591 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2592 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2593 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2595 surf
->db_depth_info
|=
2596 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2597 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2598 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2599 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2600 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2601 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2602 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2603 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2605 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2606 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2607 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2608 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2611 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2612 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2613 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2614 levelinfo
->nblk_y
) / 64 - 1);
2616 if (si_htile_enabled(rtex
, level
)) {
2617 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2618 S_028040_ALLOW_EXPCLEAR(1);
2620 if (rtex
->surface
.has_stencil
) {
2621 /* Workaround: For a not yet understood reason, the
2622 * combination of MSAA, fast stencil clear and stencil
2623 * decompress messes with subsequent stencil buffer
2624 * uses. Problem was reproduced on Verde, Bonaire,
2625 * Tonga, and Carrizo.
2627 * Disabling EXPCLEAR works around the problem.
2629 * Check piglit's arb_texture_multisample-stencil-clear
2630 * test if you want to try changing this.
2632 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2633 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2634 } else if (!rtex
->tc_compatible_htile
) {
2635 /* Use all of the htile_buffer for depth if there's no stencil.
2636 * This must not be set when TC-compatible HTILE is enabled
2639 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2642 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2643 rtex
->htile_offset
) >> 8;
2644 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2646 if (rtex
->tc_compatible_htile
) {
2647 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2649 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2650 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2651 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2652 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2654 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2659 surf
->db_z_info
= z_info
;
2660 surf
->db_stencil_info
= s_info
;
2662 surf
->depth_initialized
= true;
2665 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2667 if (sctx
->decompression_enabled
)
2670 if (sctx
->framebuffer
.state
.zsbuf
) {
2671 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2672 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2674 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2676 if (rtex
->surface
.has_stencil
)
2677 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2680 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2681 while (compressed_cb_mask
) {
2682 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2683 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2684 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2686 if (rtex
->fmask
.size
)
2687 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2688 if (rtex
->dcc_gather_statistics
)
2689 rtex
->separate_dcc_dirty
= true;
2693 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2695 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2696 struct r600_surface
*surf
= NULL
;
2697 struct r600_texture
*rtex
;
2699 if (!state
->cbufs
[i
])
2701 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2702 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2704 p_atomic_dec(&rtex
->framebuffers_bound
);
2708 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2709 const struct pipe_framebuffer_state
*state
)
2711 struct si_context
*sctx
= (struct si_context
*)ctx
;
2712 struct pipe_constant_buffer constbuf
= {0};
2713 struct r600_surface
*surf
= NULL
;
2714 struct r600_texture
*rtex
;
2715 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2716 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2717 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2718 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2719 bool old_has_stencil
=
2721 ((struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2722 bool unbound
= false;
2725 si_update_fb_dirtiness_after_rendering(sctx
);
2727 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2728 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2731 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2732 if (rtex
->dcc_gather_statistics
)
2733 vi_separate_dcc_stop_query(sctx
, rtex
);
2736 /* Disable DCC if the formats are incompatible. */
2737 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2738 if (!state
->cbufs
[i
])
2741 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2742 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2744 if (!surf
->dcc_incompatible
)
2747 /* Since the DCC decompression calls back into set_framebuffer-
2748 * _state, we need to unbind the framebuffer, so that
2749 * vi_separate_dcc_stop_query isn't called twice with the same
2753 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2757 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2758 if (!si_texture_disable_dcc(sctx
, rtex
))
2759 si_decompress_dcc(sctx
, rtex
);
2761 surf
->dcc_incompatible
= false;
2764 /* Only flush TC when changing the framebuffer state, because
2765 * the only client not using TC that can change textures is
2768 * Wait for compute shaders because of possible transitions:
2769 * - FB write -> shader read
2770 * - shader write -> FB read
2772 * DB caches are flushed on demand (using si_decompress_textures).
2774 * When MSAA is enabled, CB and TC caches are flushed on demand
2775 * (after FMASK decompression). Shader write -> FB read transitions
2776 * cannot happen for MSAA textures, because MSAA shader images are
2779 * Only flush and wait for CB if there is actually a bound color buffer.
2781 if (sctx
->framebuffer
.uncompressed_cb_mask
)
2782 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2783 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2785 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2787 /* u_blitter doesn't invoke depth decompression when it does multiple
2788 * blits in a row, but the only case when it matters for DB is when
2789 * doing generate_mipmap. So here we flush DB manually between
2790 * individual generate_mipmap blits.
2791 * Note that lower mipmap levels aren't compressed.
2793 if (sctx
->generate_mipmap_for_depth
) {
2794 si_make_DB_shader_coherent(sctx
, 1, false,
2795 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2796 } else if (sctx
->chip_class
== GFX9
) {
2797 /* It appears that DB metadata "leaks" in a sequence of:
2799 * - DCC decompress for shader image writes (with DB disabled)
2800 * - render with DEPTH_BEFORE_SHADER=1
2801 * Flushing DB metadata works around the problem.
2803 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2806 /* Take the maximum of the old and new count. If the new count is lower,
2807 * dirtying is needed to disable the unbound colorbuffers.
2809 sctx
->framebuffer
.dirty_cbufs
|=
2810 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2811 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2813 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2814 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2816 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2817 sctx
->framebuffer
.spi_shader_col_format
= 0;
2818 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2819 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2820 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2821 sctx
->framebuffer
.color_is_int8
= 0;
2822 sctx
->framebuffer
.color_is_int10
= 0;
2824 sctx
->framebuffer
.compressed_cb_mask
= 0;
2825 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2826 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2827 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2828 sctx
->framebuffer
.any_dst_linear
= false;
2829 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2830 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2832 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2833 if (!state
->cbufs
[i
])
2836 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2837 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2839 if (!surf
->color_initialized
) {
2840 si_initialize_color_surface(sctx
, surf
);
2843 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2844 sctx
->framebuffer
.spi_shader_col_format
|=
2845 surf
->spi_shader_col_format
<< (i
* 4);
2846 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2847 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2848 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2849 surf
->spi_shader_col_format_blend
<< (i
* 4);
2850 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2851 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2853 if (surf
->color_is_int8
)
2854 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2855 if (surf
->color_is_int10
)
2856 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2858 if (rtex
->fmask
.size
)
2859 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2861 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2863 if (rtex
->surface
.is_linear
)
2864 sctx
->framebuffer
.any_dst_linear
= true;
2866 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2867 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2869 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2871 p_atomic_inc(&rtex
->framebuffers_bound
);
2873 if (rtex
->dcc_gather_statistics
) {
2874 /* Dirty tracking must be enabled for DCC usage analysis. */
2875 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2876 vi_separate_dcc_start_query(sctx
, rtex
);
2880 struct r600_texture
*zstex
= NULL
;
2883 surf
= (struct r600_surface
*)state
->zsbuf
;
2884 zstex
= (struct r600_texture
*)surf
->base
.texture
;
2886 if (!surf
->depth_initialized
) {
2887 si_init_depth_surface(sctx
, surf
);
2890 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2891 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2893 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2896 si_update_ps_colorbuf0_slot(sctx
);
2897 si_update_poly_offset_state(sctx
);
2898 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2899 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2901 if (sctx
->screen
->dpbb_allowed
)
2902 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
2904 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2905 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2907 if (sctx
->screen
->has_out_of_order_rast
&&
2908 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2909 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2910 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2911 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2913 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2914 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2915 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2917 /* Set sample locations as fragment shader constants. */
2918 switch (sctx
->framebuffer
.nr_samples
) {
2920 constbuf
.user_buffer
= sctx
->sample_locations_1x
;
2923 constbuf
.user_buffer
= sctx
->sample_locations_2x
;
2926 constbuf
.user_buffer
= sctx
->sample_locations_4x
;
2929 constbuf
.user_buffer
= sctx
->sample_locations_8x
;
2932 constbuf
.user_buffer
= sctx
->sample_locations_16x
;
2935 PRINT_ERR("Requested an invalid number of samples %i.\n",
2936 sctx
->framebuffer
.nr_samples
);
2939 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2940 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2942 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2945 sctx
->do_update_shaders
= true;
2947 if (!sctx
->decompression_enabled
) {
2948 /* Prevent textures decompression when the framebuffer state
2949 * changes come from the decompression passes themselves.
2951 sctx
->need_check_render_feedback
= true;
2955 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2957 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
2958 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2959 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2960 struct r600_texture
*tex
= NULL
;
2961 struct r600_surface
*cb
= NULL
;
2962 unsigned cb_color_info
= 0;
2965 for (i
= 0; i
< nr_cbufs
; i
++) {
2966 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2967 unsigned cb_color_attrib
;
2969 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2972 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2974 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2975 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2979 tex
= (struct r600_texture
*)cb
->base
.texture
;
2980 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
2981 &tex
->resource
, RADEON_USAGE_READWRITE
,
2982 tex
->resource
.b
.b
.nr_samples
> 1 ?
2983 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2984 RADEON_PRIO_COLOR_BUFFER
);
2986 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2987 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
2988 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2992 if (tex
->dcc_separate_buffer
)
2993 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
2994 tex
->dcc_separate_buffer
,
2995 RADEON_USAGE_READWRITE
,
2998 /* Compute mutable surface parameters. */
2999 cb_color_base
= tex
->resource
.gpu_address
>> 8;
3002 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3003 cb_color_attrib
= cb
->cb_color_attrib
;
3005 if (tex
->fmask
.size
) {
3006 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
3007 cb_color_fmask
|= tex
->fmask
.tile_swizzle
;
3011 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3012 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3013 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3014 state
->cbufs
[1] == &cb
->base
&&
3015 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3017 if (!is_msaa_resolve_dst
)
3018 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3020 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
3021 tex
->dcc_offset
) >> 8;
3022 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3025 if (sctx
->chip_class
>= GFX9
) {
3026 struct gfx9_surf_meta_flags meta
;
3028 if (tex
->dcc_offset
)
3029 meta
= tex
->surface
.u
.gfx9
.dcc
;
3031 meta
= tex
->surface
.u
.gfx9
.cmask
;
3033 /* Set mutable surface parameters. */
3034 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3035 cb_color_base
|= tex
->surface
.tile_swizzle
;
3036 if (!tex
->fmask
.size
)
3037 cb_color_fmask
= cb_color_base
;
3038 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3039 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3040 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3041 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3043 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3044 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3045 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3046 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3047 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3048 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3049 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3050 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3051 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3052 radeon_emit(cs
, S_028C80_BASE_256B(tex
->cmask
.base_address_reg
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3053 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3054 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3055 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3056 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3057 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3058 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3060 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3061 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3063 /* Compute mutable surface parameters (SI-CI-VI). */
3064 const struct legacy_surf_level
*level_info
=
3065 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3066 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3067 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3069 cb_color_base
+= level_info
->offset
>> 8;
3070 /* Only macrotiled modes can set tile swizzle. */
3071 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3072 cb_color_base
|= tex
->surface
.tile_swizzle
;
3074 if (!tex
->fmask
.size
)
3075 cb_color_fmask
= cb_color_base
;
3077 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3079 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3080 slice_tile_max
= level_info
->nblk_x
*
3081 level_info
->nblk_y
/ 64 - 1;
3082 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3084 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3085 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3086 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3088 if (tex
->fmask
.size
) {
3089 if (sctx
->chip_class
>= CIK
)
3090 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
3091 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
3092 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
3094 /* This must be set for fast clear to work without FMASK. */
3095 if (sctx
->chip_class
>= CIK
)
3096 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3097 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3098 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3101 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3102 sctx
->chip_class
>= VI
? 14 : 13);
3103 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3104 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3105 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3106 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3107 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3108 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3109 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3110 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3111 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3112 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3113 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3114 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3115 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3117 if (sctx
->chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3118 radeon_emit(cs
, cb_dcc_base
);
3122 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3123 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3126 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3127 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
3128 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
3130 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3131 &rtex
->resource
, RADEON_USAGE_READWRITE
,
3132 zb
->base
.texture
->nr_samples
> 1 ?
3133 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3134 RADEON_PRIO_DEPTH_BUFFER
);
3136 if (sctx
->chip_class
>= GFX9
) {
3137 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3138 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3139 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3140 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3142 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3143 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3144 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3145 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3146 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3147 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3148 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3149 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3150 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3151 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3152 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3153 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3155 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3156 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3157 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3159 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3161 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3162 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3163 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3164 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3165 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3166 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3167 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3168 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3169 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3170 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3171 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3174 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3175 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3176 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3178 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3179 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3180 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3181 if (sctx
->chip_class
>= GFX9
)
3182 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3184 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3186 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3187 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3190 /* Framebuffer dimensions. */
3191 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3192 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3193 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3195 if (sctx
->screen
->dfsm_allowed
) {
3196 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3197 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3200 sctx
->framebuffer
.dirty_cbufs
= 0;
3201 sctx
->framebuffer
.dirty_zsbuf
= false;
3204 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
3205 struct r600_atom
*atom
)
3207 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
3208 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3209 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3211 /* Smoothing (only possible with nr_samples == 1) uses the same
3212 * sample locations as the MSAA it simulates.
3214 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3215 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3217 /* On Polaris, the small primitive filter uses the sample locations
3218 * even when MSAA is off, so we need to make sure they're set to 0.
3220 if (has_msaa_sample_loc_bug
)
3221 nr_samples
= MAX2(nr_samples
, 1);
3223 if (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
) {
3224 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
3225 si_emit_sample_locations(cs
, nr_samples
);
3228 if (sctx
->family
>= CHIP_POLARIS10
) {
3229 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3230 unsigned small_prim_filter_cntl
=
3231 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3233 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3235 /* The alternative of setting sample locations to 0 would
3236 * require a DB flush to avoid Z errors, see
3237 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3239 if (has_msaa_sample_loc_bug
&&
3240 sctx
->framebuffer
.nr_samples
> 1 &&
3241 rs
&& !rs
->multisample_enable
)
3242 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3244 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3245 small_prim_filter_cntl
);
3249 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3251 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3252 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3254 if (!sctx
->screen
->has_out_of_order_rast
)
3257 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3260 colormask
&= blend
->cb_target_enabled_4bit
;
3265 /* Conservative: No logic op. */
3266 if (colormask
&& blend
->logicop_enable
)
3269 struct si_dsa_order_invariance dsa_order_invariant
= {
3270 .zs
= true, .pass_set
= true, .pass_last
= false
3273 if (sctx
->framebuffer
.state
.zsbuf
) {
3274 struct r600_texture
*zstex
=
3275 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3276 bool has_stencil
= zstex
->surface
.has_stencil
;
3277 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3278 if (!dsa_order_invariant
.zs
)
3281 /* The set of PS invocations is always order invariant,
3282 * except when early Z/S tests are requested. */
3283 if (sctx
->ps_shader
.cso
&&
3284 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3285 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3286 !dsa_order_invariant
.pass_set
)
3289 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3290 !dsa_order_invariant
.pass_set
)
3297 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3300 /* Only commutative blending. */
3301 if (blendmask
& ~blend
->commutative_4bit
)
3304 if (!dsa_order_invariant
.pass_set
)
3308 if (colormask
& ~blendmask
) {
3309 if (!dsa_order_invariant
.pass_last
)
3316 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
3318 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
3319 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3320 /* 33% faster rendering to linear color buffers */
3321 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3322 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3323 unsigned sc_mode_cntl_1
=
3324 S_028A4C_WALK_SIZE(dst_is_linear
) |
3325 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3326 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3327 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3328 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3330 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3331 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3332 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3333 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3334 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3335 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3337 int setup_samples
= sctx
->framebuffer
.nr_samples
> 1 ? sctx
->framebuffer
.nr_samples
:
3338 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0;
3340 /* Required by OpenGL line rasterization.
3342 * TODO: We should also enable perpendicular endcaps for AA lines,
3343 * but that requires implementing line stippling in the pixel
3344 * shader. SC can only do line stippling with axis-aligned
3347 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3349 if (setup_samples
> 1) {
3350 /* distance from the pixel center, indexed by log2(nr_samples) */
3351 static unsigned max_dist
[] = {
3358 unsigned log_samples
= util_logbase2(setup_samples
);
3359 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3360 unsigned log_ps_iter_samples
=
3361 util_logbase2(util_next_power_of_two(ps_iter_samples
));
3363 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3364 radeon_emit(cs
, sc_line_cntl
|
3365 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3366 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3367 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3368 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3370 if (sctx
->framebuffer
.nr_samples
> 1) {
3371 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3372 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
3373 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3374 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3375 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
3376 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3377 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3378 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3379 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1) |
3381 } else if (sctx
->smoothing_enabled
) {
3382 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3383 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3384 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3385 S_028804_OVERRASTERIZATION_AMOUNT(log_samples
));
3386 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3390 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3391 radeon_emit(cs
, sc_line_cntl
); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3392 radeon_emit(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3394 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3395 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3396 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3397 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3401 /* GFX9: Flush DFSM when the AA mode changes. */
3402 if (sctx
->screen
->dfsm_allowed
) {
3403 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3404 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3408 void si_update_ps_iter_samples(struct si_context
*sctx
)
3410 if (sctx
->framebuffer
.nr_samples
> 1)
3411 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3412 if (sctx
->screen
->dpbb_allowed
)
3413 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3416 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3418 struct si_context
*sctx
= (struct si_context
*)ctx
;
3420 if (sctx
->ps_iter_samples
== min_samples
)
3423 sctx
->ps_iter_samples
= min_samples
;
3424 sctx
->do_update_shaders
= true;
3426 si_update_ps_iter_samples(sctx
);
3434 * Build the sampler view descriptor for a buffer texture.
3435 * @param state 256-bit descriptor; only the high 128 bits are filled in
3438 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3439 enum pipe_format format
,
3440 unsigned offset
, unsigned size
,
3443 const struct util_format_description
*desc
;
3446 unsigned num_records
;
3447 unsigned num_format
, data_format
;
3449 desc
= util_format_description(format
);
3450 first_non_void
= util_format_get_first_non_void_channel(format
);
3451 stride
= desc
->block
.bits
/ 8;
3452 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3453 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3455 num_records
= size
/ stride
;
3456 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3458 /* The NUM_RECORDS field has a different meaning depending on the chip,
3459 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3462 * - If STRIDE == 0, it's in byte units.
3463 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3466 * - For SMEM and STRIDE == 0, it's in byte units.
3467 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3468 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3469 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3470 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3471 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3472 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3473 * That way the same descriptor can be used by both SMEM and VMEM.
3476 * - For SMEM and STRIDE == 0, it's in byte units.
3477 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3478 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3479 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3481 if (screen
->info
.chip_class
>= GFX9
)
3482 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3483 * from STRIDE to bytes. This works around it by setting
3484 * NUM_RECORDS to at least the size of one element, so that
3485 * the first element is readable when IDXEN == 0.
3487 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3488 * IDXEN is enforced?
3490 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3491 else if (screen
->info
.chip_class
== VI
)
3492 num_records
*= stride
;
3495 state
[5] = S_008F04_STRIDE(stride
);
3496 state
[6] = num_records
;
3497 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3498 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3499 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3500 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3501 S_008F0C_NUM_FORMAT(num_format
) |
3502 S_008F0C_DATA_FORMAT(data_format
);
3505 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3507 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3509 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3510 /* For the pre-defined border color values (white, opaque
3511 * black, transparent black), the only thing that matters is
3512 * that the alpha channel winds up in the correct place
3513 * (because the RGB channels are all the same) so either of
3514 * these enumerations will work.
3516 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3517 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3519 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3520 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3521 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3522 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3524 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3525 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3526 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3527 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3528 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3535 * Build the sampler view descriptor for a texture.
3538 si_make_texture_descriptor(struct si_screen
*screen
,
3539 struct r600_texture
*tex
,
3541 enum pipe_texture_target target
,
3542 enum pipe_format pipe_format
,
3543 const unsigned char state_swizzle
[4],
3544 unsigned first_level
, unsigned last_level
,
3545 unsigned first_layer
, unsigned last_layer
,
3546 unsigned width
, unsigned height
, unsigned depth
,
3548 uint32_t *fmask_state
)
3550 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
3551 const struct util_format_description
*desc
;
3552 unsigned char swizzle
[4];
3554 unsigned num_format
, data_format
, type
;
3557 desc
= util_format_description(pipe_format
);
3559 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3560 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3561 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3562 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3564 switch (pipe_format
) {
3565 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3566 case PIPE_FORMAT_X32_S8X24_UINT
:
3567 case PIPE_FORMAT_X8Z24_UNORM
:
3568 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3570 case PIPE_FORMAT_X24S8_UINT
:
3572 * X24S8 is implemented as an 8_8_8_8 data format, to
3573 * fix texture gathers. This affects at least
3574 * GL45-CTS.texture_cube_map_array.sampling on VI.
3576 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3579 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3582 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3585 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3587 switch (pipe_format
) {
3588 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3589 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3592 if (first_non_void
< 0) {
3593 if (util_format_is_compressed(pipe_format
)) {
3594 switch (pipe_format
) {
3595 case PIPE_FORMAT_DXT1_SRGB
:
3596 case PIPE_FORMAT_DXT1_SRGBA
:
3597 case PIPE_FORMAT_DXT3_SRGBA
:
3598 case PIPE_FORMAT_DXT5_SRGBA
:
3599 case PIPE_FORMAT_BPTC_SRGBA
:
3600 case PIPE_FORMAT_ETC2_SRGB8
:
3601 case PIPE_FORMAT_ETC2_SRGB8A1
:
3602 case PIPE_FORMAT_ETC2_SRGBA8
:
3603 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3605 case PIPE_FORMAT_RGTC1_SNORM
:
3606 case PIPE_FORMAT_LATC1_SNORM
:
3607 case PIPE_FORMAT_RGTC2_SNORM
:
3608 case PIPE_FORMAT_LATC2_SNORM
:
3609 case PIPE_FORMAT_ETC2_R11_SNORM
:
3610 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3611 /* implies float, so use SNORM/UNORM to determine
3612 whether data is signed or not */
3613 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3614 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3617 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3620 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3621 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3623 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3625 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3626 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3628 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3630 switch (desc
->channel
[first_non_void
].type
) {
3631 case UTIL_FORMAT_TYPE_FLOAT
:
3632 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3634 case UTIL_FORMAT_TYPE_SIGNED
:
3635 if (desc
->channel
[first_non_void
].normalized
)
3636 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3637 else if (desc
->channel
[first_non_void
].pure_integer
)
3638 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3640 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3642 case UTIL_FORMAT_TYPE_UNSIGNED
:
3643 if (desc
->channel
[first_non_void
].normalized
)
3644 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3645 else if (desc
->channel
[first_non_void
].pure_integer
)
3646 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3648 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3653 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3654 if (data_format
== ~0) {
3658 /* S8 with Z32 HTILE needs a special format. */
3659 if (screen
->info
.chip_class
>= GFX9
&&
3660 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3661 tex
->tc_compatible_htile
)
3662 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3665 (res
->target
== PIPE_TEXTURE_CUBE
||
3666 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3667 (screen
->info
.chip_class
<= VI
&&
3668 res
->target
== PIPE_TEXTURE_3D
))) {
3669 /* For the purpose of shader images, treat cube maps and 3D
3670 * textures as 2D arrays. For 3D textures, the address
3671 * calculations for mipmaps are different, so we rely on the
3672 * caller to effectively disable mipmaps.
3674 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3676 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3678 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3681 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3683 depth
= res
->array_size
;
3684 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3685 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3686 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3687 depth
= res
->array_size
;
3688 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3689 depth
= res
->array_size
/ 6;
3692 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3693 S_008F14_NUM_FORMAT_GFX6(num_format
));
3694 state
[2] = (S_008F18_WIDTH(width
- 1) |
3695 S_008F18_HEIGHT(height
- 1) |
3696 S_008F18_PERF_MOD(4));
3697 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3698 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3699 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3700 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3701 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3703 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3704 util_logbase2(res
->nr_samples
) :
3706 S_008F1C_TYPE(type
));
3708 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3712 if (screen
->info
.chip_class
>= GFX9
) {
3713 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3715 /* Depth is the the last accessible layer on Gfx9.
3716 * The hw doesn't need to know the total number of layers.
3718 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3719 state
[4] |= S_008F20_DEPTH(depth
- 1);
3721 state
[4] |= S_008F20_DEPTH(last_layer
);
3723 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3724 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3725 util_logbase2(res
->nr_samples
) :
3726 tex
->resource
.b
.b
.last_level
);
3728 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3729 state
[4] |= S_008F20_DEPTH(depth
- 1);
3730 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3733 if (tex
->dcc_offset
) {
3734 unsigned swap
= si_translate_colorswap(pipe_format
, false);
3736 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3738 /* The last dword is unused by hw. The shader uses it to clear
3739 * bits in the first dword of sampler state.
3741 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3742 if (first_level
== last_level
)
3743 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3745 state
[7] = 0xffffffff;
3749 /* Initialize the sampler view for FMASK. */
3750 if (tex
->fmask
.size
) {
3751 uint32_t data_format
, num_format
;
3753 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3755 if (screen
->info
.chip_class
>= GFX9
) {
3756 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3757 switch (res
->nr_samples
) {
3759 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3762 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3765 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3768 unreachable("invalid nr_samples");
3771 switch (res
->nr_samples
) {
3773 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3776 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3779 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3782 unreachable("invalid nr_samples");
3784 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3787 fmask_state
[0] = (va
>> 8) | tex
->fmask
.tile_swizzle
;
3788 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3789 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3790 S_008F14_NUM_FORMAT_GFX6(num_format
);
3791 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3792 S_008F18_HEIGHT(height
- 1);
3793 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3794 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3795 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3796 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3797 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3799 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3803 if (screen
->info
.chip_class
>= GFX9
) {
3804 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3805 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3806 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3807 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3808 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3810 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3811 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3812 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3813 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3819 * Create a sampler view.
3821 * @param ctx context
3822 * @param texture texture
3823 * @param state sampler view template
3824 * @param width0 width0 override (for compressed textures as int)
3825 * @param height0 height0 override (for compressed textures as int)
3826 * @param force_level set the base address to the level (for compressed textures)
3828 struct pipe_sampler_view
*
3829 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3830 struct pipe_resource
*texture
,
3831 const struct pipe_sampler_view
*state
,
3832 unsigned width0
, unsigned height0
,
3833 unsigned force_level
)
3835 struct si_context
*sctx
= (struct si_context
*)ctx
;
3836 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3837 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3838 unsigned base_level
, first_level
, last_level
;
3839 unsigned char state_swizzle
[4];
3840 unsigned height
, depth
, width
;
3841 unsigned last_layer
= state
->u
.tex
.last_layer
;
3842 enum pipe_format pipe_format
;
3843 const struct legacy_surf_level
*surflevel
;
3848 /* initialize base object */
3849 view
->base
= *state
;
3850 view
->base
.texture
= NULL
;
3851 view
->base
.reference
.count
= 1;
3852 view
->base
.context
= ctx
;
3855 pipe_resource_reference(&view
->base
.texture
, texture
);
3857 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3858 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3859 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3860 state
->format
== PIPE_FORMAT_S8_UINT
)
3861 view
->is_stencil_sampler
= true;
3863 /* Buffer resource. */
3864 if (texture
->target
== PIPE_BUFFER
) {
3865 si_make_buffer_descriptor(sctx
->screen
,
3866 (struct r600_resource
*)texture
,
3868 state
->u
.buf
.offset
,
3874 state_swizzle
[0] = state
->swizzle_r
;
3875 state_swizzle
[1] = state
->swizzle_g
;
3876 state_swizzle
[2] = state
->swizzle_b
;
3877 state_swizzle
[3] = state
->swizzle_a
;
3880 first_level
= state
->u
.tex
.first_level
;
3881 last_level
= state
->u
.tex
.last_level
;
3884 depth
= texture
->depth0
;
3886 if (sctx
->chip_class
<= VI
&& force_level
) {
3887 assert(force_level
== first_level
&&
3888 force_level
== last_level
);
3889 base_level
= force_level
;
3892 width
= u_minify(width
, force_level
);
3893 height
= u_minify(height
, force_level
);
3894 depth
= u_minify(depth
, force_level
);
3897 /* This is not needed if state trackers set last_layer correctly. */
3898 if (state
->target
== PIPE_TEXTURE_1D
||
3899 state
->target
== PIPE_TEXTURE_2D
||
3900 state
->target
== PIPE_TEXTURE_RECT
||
3901 state
->target
== PIPE_TEXTURE_CUBE
)
3902 last_layer
= state
->u
.tex
.first_layer
;
3904 /* Texturing with separate depth and stencil. */
3905 pipe_format
= state
->format
;
3907 /* Depth/stencil texturing sometimes needs separate texture. */
3908 if (tmp
->is_depth
&& !si_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3909 if (!tmp
->flushed_depth_texture
&&
3910 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3911 pipe_resource_reference(&view
->base
.texture
, NULL
);
3916 assert(tmp
->flushed_depth_texture
);
3918 /* Override format for the case where the flushed texture
3919 * contains only Z or only S.
3921 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3922 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3924 tmp
= tmp
->flushed_depth_texture
;
3927 surflevel
= tmp
->surface
.u
.legacy
.level
;
3929 if (tmp
->db_compatible
) {
3930 if (!view
->is_stencil_sampler
)
3931 pipe_format
= tmp
->db_render_format
;
3933 switch (pipe_format
) {
3934 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3935 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3937 case PIPE_FORMAT_X8Z24_UNORM
:
3938 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3939 /* Z24 is always stored like this for DB
3942 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3944 case PIPE_FORMAT_X24S8_UINT
:
3945 case PIPE_FORMAT_S8X24_UINT
:
3946 case PIPE_FORMAT_X32_S8X24_UINT
:
3947 pipe_format
= PIPE_FORMAT_S8_UINT
;
3948 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3954 view
->dcc_incompatible
=
3955 vi_dcc_formats_are_incompatible(texture
,
3956 state
->u
.tex
.first_level
,
3959 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3960 state
->target
, pipe_format
, state_swizzle
,
3961 first_level
, last_level
,
3962 state
->u
.tex
.first_layer
, last_layer
,
3963 width
, height
, depth
,
3964 view
->state
, view
->fmask_state
);
3966 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
3968 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
3969 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
3970 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
3971 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
3972 view
->base_level_info
= &surflevel
[base_level
];
3973 view
->base_level
= base_level
;
3974 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3978 static struct pipe_sampler_view
*
3979 si_create_sampler_view(struct pipe_context
*ctx
,
3980 struct pipe_resource
*texture
,
3981 const struct pipe_sampler_view
*state
)
3983 return si_create_sampler_view_custom(ctx
, texture
, state
,
3984 texture
? texture
->width0
: 0,
3985 texture
? texture
->height0
: 0, 0);
3988 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3989 struct pipe_sampler_view
*state
)
3991 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3993 pipe_resource_reference(&state
->texture
, NULL
);
3997 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3999 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4000 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4002 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4003 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4006 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4007 const struct pipe_sampler_state
*state
,
4008 const union pipe_color_union
*color
,
4011 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4012 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4014 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4015 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4016 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4017 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4019 #define simple_border_types(elt) \
4021 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4022 color->elt[2] == 0 && color->elt[3] == 0) \
4023 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4024 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4025 color->elt[2] == 0 && color->elt[3] == 1) \
4026 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4027 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4028 color->elt[2] == 1 && color->elt[3] == 1) \
4029 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4033 simple_border_types(ui
);
4035 simple_border_types(f
);
4037 #undef simple_border_types
4041 /* Check if the border has been uploaded already. */
4042 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4043 if (memcmp(&sctx
->border_color_table
[i
], color
,
4044 sizeof(*color
)) == 0)
4047 if (i
>= SI_MAX_BORDER_COLORS
) {
4048 /* Getting 4096 unique border colors is very unlikely. */
4049 fprintf(stderr
, "radeonsi: The border color table is full. "
4050 "Any new border colors will be just black. "
4051 "Please file a bug.\n");
4052 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4055 if (i
== sctx
->border_color_count
) {
4056 /* Upload a new border color. */
4057 memcpy(&sctx
->border_color_table
[i
], color
,
4059 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4060 color
, sizeof(*color
));
4061 sctx
->border_color_count
++;
4064 return S_008F3C_BORDER_COLOR_PTR(i
) |
4065 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4068 static inline int S_FIXED(float value
, unsigned frac_bits
)
4070 return value
* (1 << frac_bits
);
4073 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4075 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4076 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4077 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4079 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4080 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4083 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4096 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4097 const struct pipe_sampler_state
*state
)
4099 struct si_context
*sctx
= (struct si_context
*)ctx
;
4100 struct si_screen
*sscreen
= sctx
->screen
;
4101 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4102 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4103 : state
->max_anisotropy
;
4104 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4105 union pipe_color_union clamped_border_color
;
4112 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4114 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4115 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4116 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4117 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4118 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4119 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4120 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4121 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4122 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4123 S_008F30_COMPAT_MODE(sctx
->chip_class
>= VI
));
4124 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4125 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4126 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4127 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4128 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4129 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4130 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4131 S_008F38_MIP_POINT_PRECLAMP(0) |
4132 S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= VI
) |
4133 S_008F38_FILTER_PREC_FIX(1) |
4134 S_008F38_ANISO_OVERRIDE(sctx
->chip_class
>= VI
));
4135 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4137 /* Create sampler resource for integer textures. */
4138 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4139 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4141 /* Create sampler resource for upgraded depth textures. */
4142 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4144 for (unsigned i
= 0; i
< 4; ++i
) {
4145 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4146 * when the border color is 1.0. */
4147 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4150 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4151 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4153 rstate
->upgraded_depth_val
[3] =
4154 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4155 S_008F3C_UPGRADED_DEPTH(1);
4160 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4162 struct si_context
*sctx
= (struct si_context
*)ctx
;
4164 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
4167 sctx
->sample_mask
.sample_mask
= sample_mask
;
4168 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
4171 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
4173 struct radeon_winsys_cs
*cs
= sctx
->gfx_cs
;
4174 unsigned mask
= sctx
->sample_mask
.sample_mask
;
4176 /* Needed for line and polygon smoothing as well as for the Polaris
4177 * small primitive filter. We expect the state tracker to take care of
4180 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4181 (mask
& 1 && sctx
->blitter
->running
));
4183 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4184 radeon_emit(cs
, mask
| (mask
<< 16));
4185 radeon_emit(cs
, mask
| (mask
<< 16));
4188 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4191 struct si_sampler_state
*s
= state
;
4193 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4200 * Vertex elements & buffers
4203 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4205 const struct pipe_vertex_element
*elements
)
4207 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4208 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4209 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4212 assert(count
<= SI_MAX_ATTRIBS
);
4217 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4219 for (i
= 0; i
< count
; ++i
) {
4220 const struct util_format_description
*desc
;
4221 const struct util_format_channel_description
*channel
;
4222 unsigned data_format
, num_format
;
4224 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4225 unsigned char swizzle
[4];
4227 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4232 if (elements
[i
].instance_divisor
) {
4233 v
->uses_instance_divisors
= true;
4234 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4236 if (v
->instance_divisors
[i
] == 1)
4237 v
->instance_divisor_is_one
|= 1u << i
;
4239 v
->instance_divisor_is_fetched
|= 1u << i
;
4242 if (!used
[vbo_index
]) {
4243 v
->first_vb_use_mask
|= 1 << i
;
4244 used
[vbo_index
] = true;
4247 desc
= util_format_description(elements
[i
].src_format
);
4248 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4249 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4250 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4251 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4252 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4254 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4255 v
->src_offset
[i
] = elements
[i
].src_offset
;
4256 v
->vertex_buffer_index
[i
] = vbo_index
;
4258 /* The hardware always treats the 2-bit alpha channel as
4259 * unsigned, so a shader workaround is needed. The affected
4260 * chips are VI and older except Stoney (GFX8.1).
4262 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4263 sscreen
->info
.chip_class
<= VI
&&
4264 sscreen
->info
.family
!= CHIP_STONEY
) {
4265 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4266 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4267 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4268 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4269 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4270 /* This isn't actually used in OpenGL. */
4271 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4273 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4274 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4275 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4277 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4278 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4279 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4280 if (channel
->normalized
) {
4281 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4282 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4284 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4286 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4288 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4289 if (channel
->normalized
) {
4290 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4291 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4293 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4295 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4298 } else if (channel
&& channel
->size
== 64 &&
4299 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4300 switch (desc
->nr_channels
) {
4303 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4304 swizzle
[0] = PIPE_SWIZZLE_X
;
4305 swizzle
[1] = PIPE_SWIZZLE_Y
;
4306 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4307 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4310 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4311 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4312 swizzle
[1] = PIPE_SWIZZLE_Y
;
4313 swizzle
[2] = PIPE_SWIZZLE_0
;
4314 swizzle
[3] = PIPE_SWIZZLE_0
;
4317 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4318 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4319 swizzle
[1] = PIPE_SWIZZLE_Y
;
4320 swizzle
[2] = PIPE_SWIZZLE_Z
;
4321 swizzle
[3] = PIPE_SWIZZLE_W
;
4326 } else if (channel
&& desc
->nr_channels
== 3) {
4327 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4329 if (channel
->size
== 8) {
4330 if (channel
->pure_integer
)
4331 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4333 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4334 } else if (channel
->size
== 16) {
4335 if (channel
->pure_integer
)
4336 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4338 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4342 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4343 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4344 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4345 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4346 S_008F0C_NUM_FORMAT(num_format
) |
4347 S_008F0C_DATA_FORMAT(data_format
);
4352 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4354 struct si_context
*sctx
= (struct si_context
*)ctx
;
4355 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4356 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4358 sctx
->vertex_elements
= v
;
4359 sctx
->vertex_buffers_dirty
= true;
4363 old
->count
!= v
->count
||
4364 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4365 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4366 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4367 sctx
->do_update_shaders
= true;
4369 if (v
&& v
->instance_divisor_is_fetched
) {
4370 struct pipe_constant_buffer cb
;
4373 cb
.user_buffer
= v
->instance_divisors
;
4374 cb
.buffer_offset
= 0;
4375 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4376 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4380 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4382 struct si_context
*sctx
= (struct si_context
*)ctx
;
4384 if (sctx
->vertex_elements
== state
)
4385 sctx
->vertex_elements
= NULL
;
4389 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4390 unsigned start_slot
, unsigned count
,
4391 const struct pipe_vertex_buffer
*buffers
)
4393 struct si_context
*sctx
= (struct si_context
*)ctx
;
4394 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4397 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4400 for (i
= 0; i
< count
; i
++) {
4401 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4402 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4403 struct pipe_resource
*buf
= src
->buffer
.resource
;
4405 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4406 dsti
->buffer_offset
= src
->buffer_offset
;
4407 dsti
->stride
= src
->stride
;
4408 si_context_add_resource_size(sctx
, buf
);
4410 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4413 for (i
= 0; i
< count
; i
++) {
4414 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4417 sctx
->vertex_buffers_dirty
= true;
4424 static void si_set_tess_state(struct pipe_context
*ctx
,
4425 const float default_outer_level
[4],
4426 const float default_inner_level
[2])
4428 struct si_context
*sctx
= (struct si_context
*)ctx
;
4429 struct pipe_constant_buffer cb
;
4432 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4433 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4436 cb
.user_buffer
= NULL
;
4437 cb
.buffer_size
= sizeof(array
);
4439 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4440 (void*)array
, sizeof(array
),
4443 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4444 pipe_resource_reference(&cb
.buffer
, NULL
);
4447 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4449 struct si_context
*sctx
= (struct si_context
*)ctx
;
4451 si_update_fb_dirtiness_after_rendering(sctx
);
4453 /* Multisample surfaces are flushed in si_decompress_textures. */
4454 if (sctx
->framebuffer
.uncompressed_cb_mask
)
4455 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4456 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4459 /* This only ensures coherency for shader image/buffer stores. */
4460 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4462 struct si_context
*sctx
= (struct si_context
*)ctx
;
4464 /* Subsequent commands must wait for all shader invocations to
4466 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4467 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4469 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4470 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
|
4471 SI_CONTEXT_INV_VMEM_L1
;
4473 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4474 PIPE_BARRIER_SHADER_BUFFER
|
4475 PIPE_BARRIER_TEXTURE
|
4476 PIPE_BARRIER_IMAGE
|
4477 PIPE_BARRIER_STREAMOUT_BUFFER
|
4478 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4479 /* As far as I can tell, L1 contents are written back to L2
4480 * automatically at end of shader, but the contents of other
4481 * L1 caches might still be stale. */
4482 sctx
->flags
|= SI_CONTEXT_INV_VMEM_L1
;
4485 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4486 /* Indices are read through TC L2 since VI.
4489 if (sctx
->screen
->info
.chip_class
<= CIK
)
4490 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4493 /* MSAA color, any depth and any stencil are flushed in
4494 * si_decompress_textures when needed.
4496 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4497 sctx
->framebuffer
.uncompressed_cb_mask
) {
4498 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4500 if (sctx
->chip_class
<= VI
)
4501 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4504 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4505 if (sctx
->screen
->info
.chip_class
<= VI
&&
4506 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4507 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4510 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4512 struct pipe_blend_state blend
;
4514 memset(&blend
, 0, sizeof(blend
));
4515 blend
.independent_blend_enable
= true;
4516 blend
.rt
[0].colormask
= 0xf;
4517 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4520 static void si_init_config(struct si_context
*sctx
);
4522 void si_init_state_functions(struct si_context
*sctx
)
4524 si_init_external_atom(sctx
, &sctx
->render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
4525 si_init_external_atom(sctx
, &sctx
->streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
4526 si_init_external_atom(sctx
, &sctx
->streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
4527 si_init_external_atom(sctx
, &sctx
->scissors
.atom
, &sctx
->atoms
.s
.scissors
);
4528 si_init_external_atom(sctx
, &sctx
->viewports
.atom
, &sctx
->atoms
.s
.viewports
);
4530 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
4531 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
4532 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
4533 si_init_atom(sctx
, &sctx
->dpbb_state
, &sctx
->atoms
.s
.dpbb_state
, si_emit_dpbb_state
);
4534 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
4535 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
4536 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
4537 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
4538 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
4539 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
4540 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
4542 sctx
->b
.create_blend_state
= si_create_blend_state
;
4543 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4544 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4545 sctx
->b
.set_blend_color
= si_set_blend_color
;
4547 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4548 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4549 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4551 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4552 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4553 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4555 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4556 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4557 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4558 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4559 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4561 sctx
->b
.set_clip_state
= si_set_clip_state
;
4562 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
4564 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
4566 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4567 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4569 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4570 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4572 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
4574 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
4575 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4576 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4577 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
4579 sctx
->b
.texture_barrier
= si_texture_barrier
;
4580 sctx
->b
.memory_barrier
= si_memory_barrier
;
4581 sctx
->b
.set_min_samples
= si_set_min_samples
;
4582 sctx
->b
.set_tess_state
= si_set_tess_state
;
4584 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
4586 sctx
->b
.draw_vbo
= si_draw_vbo
;
4588 si_init_config(sctx
);
4591 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4593 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4596 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4597 struct si_pm4_state
*pm4
, unsigned value
)
4599 unsigned reg
= sctx
->chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4600 R_00802C_GRBM_GFX_INDEX
;
4601 si_pm4_set_reg(pm4
, reg
, value
);
4604 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4605 struct si_pm4_state
*pm4
, unsigned se
)
4607 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4608 si_set_grbm_gfx_index(sctx
, pm4
,
4609 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4610 S_030800_SE_INDEX(se
)) |
4611 S_030800_SH_BROADCAST_WRITES(1) |
4612 S_030800_INSTANCE_BROADCAST_WRITES(1));
4616 si_write_harvested_raster_configs(struct si_context
*sctx
,
4617 struct si_pm4_state
*pm4
,
4618 unsigned raster_config
,
4619 unsigned raster_config_1
)
4621 unsigned sh_per_se
= MAX2(sctx
->screen
->info
.max_sh_per_se
, 1);
4622 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4623 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4624 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4625 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4626 unsigned rb_per_se
= num_rb
/ num_se
;
4627 unsigned se_mask
[4];
4630 se_mask
[0] = ((1 << rb_per_se
) - 1);
4631 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4632 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4633 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4635 se_mask
[0] &= rb_mask
;
4636 se_mask
[1] &= rb_mask
;
4637 se_mask
[2] &= rb_mask
;
4638 se_mask
[3] &= rb_mask
;
4640 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4641 assert(sh_per_se
== 1 || sh_per_se
== 2);
4642 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4644 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4645 * fields are for, so I'm leaving them as their default
4648 for (se
= 0; se
< num_se
; se
++) {
4649 unsigned raster_config_se
= raster_config
;
4650 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4651 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4652 int idx
= (se
/ 2) * 2;
4654 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4655 raster_config_se
&= C_028350_SE_MAP
;
4657 if (!se_mask
[idx
]) {
4659 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4662 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4666 pkr0_mask
&= rb_mask
;
4667 pkr1_mask
&= rb_mask
;
4668 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4669 raster_config_se
&= C_028350_PKR_MAP
;
4673 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4676 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4680 if (rb_per_se
>= 2) {
4681 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4682 unsigned rb1_mask
= rb0_mask
<< 1;
4684 rb0_mask
&= rb_mask
;
4685 rb1_mask
&= rb_mask
;
4686 if (!rb0_mask
|| !rb1_mask
) {
4687 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4691 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4694 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4698 if (rb_per_se
> 2) {
4699 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4700 rb1_mask
= rb0_mask
<< 1;
4701 rb0_mask
&= rb_mask
;
4702 rb1_mask
&= rb_mask
;
4703 if (!rb0_mask
|| !rb1_mask
) {
4704 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4708 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4711 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4717 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4718 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4720 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4722 if (sctx
->chip_class
>= CIK
) {
4723 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4724 (!se_mask
[2] && !se_mask
[3]))) {
4725 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4727 if (!se_mask
[0] && !se_mask
[1]) {
4729 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4732 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4736 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4740 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4742 struct si_screen
*sscreen
= sctx
->screen
;
4743 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4744 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4745 unsigned raster_config
, raster_config_1
;
4747 switch (sctx
->family
) {
4750 raster_config
= 0x2a00126a;
4751 raster_config_1
= 0x00000000;
4754 raster_config
= 0x0000124a;
4755 raster_config_1
= 0x00000000;
4758 raster_config
= 0x00000082;
4759 raster_config_1
= 0x00000000;
4762 raster_config
= 0x00000000;
4763 raster_config_1
= 0x00000000;
4766 raster_config
= 0x16000012;
4767 raster_config_1
= 0x00000000;
4770 raster_config
= 0x3a00161a;
4771 raster_config_1
= 0x0000002e;
4774 if (sscreen
->info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4775 /* old kernels with old tiling config */
4776 raster_config
= 0x16000012;
4777 raster_config_1
= 0x0000002a;
4779 raster_config
= 0x3a00161a;
4780 raster_config_1
= 0x0000002e;
4783 case CHIP_POLARIS10
:
4784 raster_config
= 0x16000012;
4785 raster_config_1
= 0x0000002a;
4787 case CHIP_POLARIS11
:
4788 case CHIP_POLARIS12
:
4789 raster_config
= 0x16000012;
4790 raster_config_1
= 0x00000000;
4793 raster_config
= 0x16000012;
4794 raster_config_1
= 0x0000002a;
4798 raster_config
= 0x00000000;
4800 raster_config
= 0x00000002;
4801 raster_config_1
= 0x00000000;
4804 raster_config
= 0x00000002;
4805 raster_config_1
= 0x00000000;
4808 /* KV should be 0x00000002, but that causes problems with radeon */
4809 raster_config
= 0x00000000; /* 0x00000002 */
4810 raster_config_1
= 0x00000000;
4815 raster_config
= 0x00000000;
4816 raster_config_1
= 0x00000000;
4820 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4821 raster_config
= 0x00000000;
4822 raster_config_1
= 0x00000000;
4825 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4826 /* Always use the default config when all backends are enabled
4827 * (or when we failed to determine the enabled backends).
4829 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4831 if (sctx
->chip_class
>= CIK
)
4832 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4835 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4839 static void si_init_config(struct si_context
*sctx
)
4841 struct si_screen
*sscreen
= sctx
->screen
;
4842 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4843 bool has_clear_state
= sscreen
->has_clear_state
;
4844 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4846 /* Only SI can disable CLEAR_STATE for now. */
4847 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
);
4852 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4853 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4854 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4855 si_pm4_cmd_end(pm4
, false);
4857 if (has_clear_state
) {
4858 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4859 si_pm4_cmd_add(pm4
, 0);
4860 si_pm4_cmd_end(pm4
, false);
4863 if (sctx
->chip_class
<= VI
)
4864 si_set_raster_config(sctx
, pm4
);
4866 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4867 if (!has_clear_state
)
4868 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4870 /* FIXME calculate these values somehow ??? */
4871 if (sctx
->chip_class
<= VI
) {
4872 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4873 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4876 if (!has_clear_state
) {
4877 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4878 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4879 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4882 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4883 if (!has_clear_state
)
4884 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4885 if (sctx
->chip_class
< CIK
)
4886 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4887 S_008A14_CLIP_VTX_REORDER_ENA(1));
4889 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4890 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4892 if (!has_clear_state
)
4893 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4895 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4896 * I don't know why. Deduced by trial and error.
4898 if (sctx
->chip_class
<= CIK
) {
4899 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4900 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4901 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4902 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4903 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4904 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4905 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4906 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4909 if (!has_clear_state
) {
4910 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4911 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4912 S_028230_ER_TRI(0xA) |
4913 S_028230_ER_POINT(0xA) |
4914 S_028230_ER_RECT(0xA) |
4915 /* Required by DX10_DIAMOND_TEST_ENA: */
4916 S_028230_ER_LINE_LR(0x1A) |
4917 S_028230_ER_LINE_RL(0x26) |
4918 S_028230_ER_LINE_TB(0xA) |
4919 S_028230_ER_LINE_BT(0xA));
4920 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4921 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4922 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4923 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4924 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4925 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4926 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4929 if (sctx
->chip_class
>= GFX9
) {
4930 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4931 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4932 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4934 /* These registers, when written, also overwrite the CLEAR_STATE
4935 * context, so we can't rely on CLEAR_STATE setting them.
4936 * It would be an issue if there was another UMD changing them.
4938 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4939 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4940 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4943 if (sctx
->chip_class
>= CIK
) {
4944 if (sctx
->chip_class
>= GFX9
) {
4945 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4946 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4948 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4949 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4950 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4951 S_00B41C_WAVE_LIMIT(0x3F));
4952 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
4953 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4955 /* If this is 0, Bonaire can hang even if GS isn't being used.
4956 * Other chips are unaffected. These are suboptimal values,
4957 * but we don't use on-chip GS.
4959 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4960 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4961 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4963 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
4964 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4966 /* Compute LATE_ALLOC_VS.LIMIT. */
4967 unsigned num_cu_per_sh
= sscreen
->info
.num_good_compute_units
/
4968 (sscreen
->info
.max_se
*
4969 sscreen
->info
.max_sh_per_se
);
4970 unsigned late_alloc_limit
; /* The limit is per SH. */
4972 if (sctx
->family
== CHIP_KABINI
) {
4973 late_alloc_limit
= 0; /* Potential hang on Kabini. */
4974 } else if (num_cu_per_sh
<= 4) {
4975 /* Too few available compute units per SH. Disallowing
4976 * VS to run on one CU could hurt us more than late VS
4977 * allocation would help.
4979 * 2 is the highest safe number that allows us to keep
4982 late_alloc_limit
= 2;
4984 /* This is a good initial value, allowing 1 late_alloc
4985 * wave per SIMD on num_cu - 2.
4987 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
4989 /* The limit is 0-based, so 0 means 1. */
4990 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
4991 late_alloc_limit
-= 1;
4994 /* VS can't execute on one CU if the limit is > 2. */
4995 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
4996 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
4997 S_00B118_WAVE_LIMIT(0x3F));
4998 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
4999 S_00B11C_LIMIT(late_alloc_limit
));
5000 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5001 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5004 if (sctx
->chip_class
>= VI
) {
5005 unsigned vgt_tess_distribution
;
5007 vgt_tess_distribution
=
5008 S_028B50_ACCUM_ISOLINE(32) |
5009 S_028B50_ACCUM_TRI(11) |
5010 S_028B50_ACCUM_QUAD(11) |
5011 S_028B50_DONUT_SPLIT(16);
5013 /* Testing with Unigine Heaven extreme tesselation yielded best results
5014 * with TRAP_SPLIT = 3.
5016 if (sctx
->family
== CHIP_FIJI
||
5017 sctx
->family
>= CHIP_POLARIS10
)
5018 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5020 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5021 } else if (!has_clear_state
) {
5022 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5023 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5026 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5027 if (sctx
->chip_class
>= CIK
) {
5028 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5029 S_028084_ADDRESS(border_color_va
>> 40));
5031 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5032 RADEON_PRIO_BORDER_COLORS
);
5034 if (sctx
->chip_class
>= GFX9
) {
5035 unsigned num_se
= sscreen
->info
.max_se
;
5036 unsigned pc_lines
= 0;
5038 switch (sctx
->family
) {
5050 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5051 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5052 S_028C48_MAX_PRIM_PER_BATCH(1023));
5053 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5054 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5055 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5058 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5059 sctx
->init_config
= pm4
;