projects / mesa.git / blob
? search:


aba44dfc06e299b4ba553629ff15100d13419232
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "radeonsi_pipe.h"
35 #include "radeonsi_shader.h"
36 #include "si_state.h"
37 #include "sid.h"
38
39 /*
40 * inferred framebuffer and blender state
41 */
42 static void si_update_fb_blend_state(struct r600_context *rctx)
43 {
44 struct si_pm4_state *pm4;
45 struct si_state_blend *blend = rctx->queued.named.blend;
46 uint32_t mask;
47
48 if (blend == NULL)
49 return;
50
51 pm4 = CALLOC_STRUCT(si_pm4_state);
52 if (pm4 == NULL)
53 return;
54
55 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
56 mask &= blend->cb_target_mask;
57 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
58
59 si_pm4_set_state(rctx, fb_blend, pm4);
60 }
61
62 /*
63 * Blender functions
64 */
65
66 static uint32_t si_translate_blend_function(int blend_func)
67 {
68 switch (blend_func) {
69 case PIPE_BLEND_ADD:
70 return V_028780_COMB_DST_PLUS_SRC;
71 case PIPE_BLEND_SUBTRACT:
72 return V_028780_COMB_SRC_MINUS_DST;
73 case PIPE_BLEND_REVERSE_SUBTRACT:
74 return V_028780_COMB_DST_MINUS_SRC;
75 case PIPE_BLEND_MIN:
76 return V_028780_COMB_MIN_DST_SRC;
77 case PIPE_BLEND_MAX:
78 return V_028780_COMB_MAX_DST_SRC;
79 default:
80 R600_ERR("Unknown blend function %d\n", blend_func);
81 assert(0);
82 break;
83 }
84 return 0;
85 }
86
87 static uint32_t si_translate_blend_factor(int blend_fact)
88 {
89 switch (blend_fact) {
90 case PIPE_BLENDFACTOR_ONE:
91 return V_028780_BLEND_ONE;
92 case PIPE_BLENDFACTOR_SRC_COLOR:
93 return V_028780_BLEND_SRC_COLOR;
94 case PIPE_BLENDFACTOR_SRC_ALPHA:
95 return V_028780_BLEND_SRC_ALPHA;
96 case PIPE_BLENDFACTOR_DST_ALPHA:
97 return V_028780_BLEND_DST_ALPHA;
98 case PIPE_BLENDFACTOR_DST_COLOR:
99 return V_028780_BLEND_DST_COLOR;
100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
101 return V_028780_BLEND_SRC_ALPHA_SATURATE;
102 case PIPE_BLENDFACTOR_CONST_COLOR:
103 return V_028780_BLEND_CONSTANT_COLOR;
104 case PIPE_BLENDFACTOR_CONST_ALPHA:
105 return V_028780_BLEND_CONSTANT_ALPHA;
106 case PIPE_BLENDFACTOR_ZERO:
107 return V_028780_BLEND_ZERO;
108 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
112 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
114 case PIPE_BLENDFACTOR_INV_DST_COLOR:
115 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
116 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
120 case PIPE_BLENDFACTOR_SRC1_COLOR:
121 return V_028780_BLEND_SRC1_COLOR;
122 case PIPE_BLENDFACTOR_SRC1_ALPHA:
123 return V_028780_BLEND_SRC1_ALPHA;
124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
125 return V_028780_BLEND_INV_SRC1_COLOR;
126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
127 return V_028780_BLEND_INV_SRC1_ALPHA;
128 default:
129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
130 assert(0);
131 break;
132 }
133 return 0;
134 }
135
136 static void *si_create_blend_state(struct pipe_context *ctx,
137 const struct pipe_blend_state *state)
138 {
139 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
140 struct si_pm4_state *pm4 = &blend->pm4;
141
142 uint32_t color_control;
143
144 if (blend == NULL)
145 return NULL;
146
147 color_control = S_028808_MODE(V_028808_CB_NORMAL);
148 if (state->logicop_enable) {
149 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
150 } else {
151 color_control |= S_028808_ROP3(0xcc);
152 }
153 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
154
155 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
156 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
157
158 blend->cb_target_mask = 0;
159 for (int i = 0; i < 8; i++) {
160 /* state->rt entries > 0 only written if independent blending */
161 const int j = state->independent_blend_enable ? i : 0;
162
163 unsigned eqRGB = state->rt[j].rgb_func;
164 unsigned srcRGB = state->rt[j].rgb_src_factor;
165 unsigned dstRGB = state->rt[j].rgb_dst_factor;
166 unsigned eqA = state->rt[j].alpha_func;
167 unsigned srcA = state->rt[j].alpha_src_factor;
168 unsigned dstA = state->rt[j].alpha_dst_factor;
169
170 unsigned blend_cntl = 0;
171
172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
173 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
174
175 if (!state->rt[j].blend_enable) {
176 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
177 continue;
178 }
179
180 blend_cntl |= S_028780_ENABLE(1);
181 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
182 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
183 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
184
185 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
186 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
187 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
188 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
189 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
190 }
191 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
192 }
193
194 return blend;
195 }
196
197 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
201 si_update_fb_blend_state(rctx);
202 }
203
204 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
208 }
209
210 static void si_set_blend_color(struct pipe_context *ctx,
211 const struct pipe_blend_color *state)
212 {
213 struct r600_context *rctx = (struct r600_context *)ctx;
214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
215
216 if (pm4 == NULL)
217 return;
218
219 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
220 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
221 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
222 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
223
224 si_pm4_set_state(rctx, blend_color, pm4);
225 }
226
227 /*
228 * Clipping, scissors and viewport
229 */
230
231 static void si_set_clip_state(struct pipe_context *ctx,
232 const struct pipe_clip_state *state)
233 {
234 struct r600_context *rctx = (struct r600_context *)ctx;
235 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
236
237 if (pm4 == NULL)
238 return;
239
240 for (int i = 0; i < 6; i++) {
241 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
242 fui(state->ucp[i][0]));
243 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
244 fui(state->ucp[i][1]));
245 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
246 fui(state->ucp[i][2]));
247 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
248 fui(state->ucp[i][3]));
249 }
250
251 si_pm4_set_state(rctx, clip, pm4);
252 }
253
254 static void si_set_scissor_state(struct pipe_context *ctx,
255 const struct pipe_scissor_state *state)
256 {
257 struct r600_context *rctx = (struct r600_context *)ctx;
258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
259 uint32_t tl, br;
260
261 if (pm4 == NULL)
262 return;
263
264 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
265 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
266 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
267 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
268 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
269 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
270 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
271 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
272 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
273 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
274
275 si_pm4_set_state(rctx, scissor, pm4);
276 }
277
278 static void si_set_viewport_state(struct pipe_context *ctx,
279 const struct pipe_viewport_state *state)
280 {
281 struct r600_context *rctx = (struct r600_context *)ctx;
282 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
283 struct si_pm4_state *pm4 = &viewport->pm4;
284
285 if (viewport == NULL)
286 return;
287
288 viewport->viewport = *state;
289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
291 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
292 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
293 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
294 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
295 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
296 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
297 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
298
299 si_pm4_set_state(rctx, viewport, viewport);
300 }
301
302 /*
303 * inferred state between framebuffer and rasterizer
304 */
305 static void si_update_fb_rs_state(struct r600_context *rctx)
306 {
307 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
308 struct si_pm4_state *pm4;
309 unsigned offset_db_fmt_cntl = 0, depth;
310 float offset_units;
311
312 if (!rs || !rctx->framebuffer.zsbuf)
313 return;
314
315 offset_units = rctx->queued.named.rasterizer->offset_units;
316 switch (rctx->framebuffer.zsbuf->texture->format) {
317 case PIPE_FORMAT_Z24X8_UNORM:
318 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
319 depth = -24;
320 offset_units *= 2.0f;
321 break;
322 case PIPE_FORMAT_Z32_FLOAT:
323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
324 depth = -23;
325 offset_units *= 1.0f;
326 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
327 break;
328 case PIPE_FORMAT_Z16_UNORM:
329 depth = -16;
330 offset_units *= 4.0f;
331 break;
332 default:
333 return;
334 }
335
336 pm4 = CALLOC_STRUCT(si_pm4_state);
337 /* FIXME some of those reg can be computed with cso */
338 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
339 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
340 fui(rctx->queued.named.rasterizer->offset_scale));
341 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
342 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
343 fui(rctx->queued.named.rasterizer->offset_scale));
344 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
345 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
346
347 si_pm4_set_state(rctx, fb_rs, pm4);
348 }
349
350 /*
351 * Rasterizer
352 */
353
354 static uint32_t si_translate_fill(uint32_t func)
355 {
356 switch(func) {
357 case PIPE_POLYGON_MODE_FILL:
358 return V_028814_X_DRAW_TRIANGLES;
359 case PIPE_POLYGON_MODE_LINE:
360 return V_028814_X_DRAW_LINES;
361 case PIPE_POLYGON_MODE_POINT:
362 return V_028814_X_DRAW_POINTS;
363 default:
364 assert(0);
365 return V_028814_X_DRAW_POINTS;
366 }
367 }
368
369 static void *si_create_rs_state(struct pipe_context *ctx,
370 const struct pipe_rasterizer_state *state)
371 {
372 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
373 struct si_pm4_state *pm4 = &rs->pm4;
374 unsigned tmp;
375 unsigned prov_vtx = 1, polygon_dual_mode;
376 unsigned clip_rule;
377 float psize_min, psize_max;
378
379 if (rs == NULL) {
380 return NULL;
381 }
382
383 rs->two_side = state->light_twoside;
384
385 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
386 state->fill_back != PIPE_POLYGON_MODE_FILL);
387
388 if (state->flatshade_first)
389 prov_vtx = 0;
390
391 rs->flatshade = state->flatshade;
392 rs->sprite_coord_enable = state->sprite_coord_enable;
393 rs->pa_sc_line_stipple = state->line_stipple_enable ?
394 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
395 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
396 rs->pa_su_sc_mode_cntl =
397 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
398 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
399 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
400 S_028814_FACE(!state->front_ccw) |
401 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
402 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
403 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
404 S_028814_POLY_MODE(polygon_dual_mode) |
405 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
406 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
407 rs->pa_cl_clip_cntl =
408 S_028810_PS_UCP_MODE(3) |
409 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
410 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
411 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
412 rs->pa_cl_vs_out_cntl =
413 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
414 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
415
416 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
417
418 /* offset */
419 rs->offset_units = state->offset_units;
420 rs->offset_scale = state->offset_scale * 12.0f;
421
422 /* XXX: Flat shading hangs the GPU */
423 tmp = S_0286D4_FLAT_SHADE_ENA(0);
424 if (state->sprite_coord_enable) {
425 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
426 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
427 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
428 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
429 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
430 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
431 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
432 }
433 }
434 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
435
436 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
437 /* point size 12.4 fixed point */
438 tmp = (unsigned)(state->point_size * 8.0);
439 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
440
441 if (state->point_size_per_vertex) {
442 psize_min = util_get_min_point_size(state);
443 psize_max = 8192;
444 } else {
445 /* Force the point size to be as if the vertex output was disabled. */
446 psize_min = state->point_size;
447 psize_max = state->point_size;
448 }
449 /* Divide by two, because 0.5 = 1 pixel. */
450 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
451 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
452 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
453
454 tmp = (unsigned)state->line_width * 8;
455 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
456 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
457 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
458
459 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
460 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
461 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
462 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
463 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
464 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
465 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
466
467 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
468 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
469
470 return rs;
471 }
472
473 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
474 {
475 struct r600_context *rctx = (struct r600_context *)ctx;
476 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
477
478 if (state == NULL)
479 return;
480
481 // TODO
482 rctx->sprite_coord_enable = rs->sprite_coord_enable;
483 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
484 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
485 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
486 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
487
488 si_pm4_bind_state(rctx, rasterizer, rs);
489 si_update_fb_rs_state(rctx);
490 }
491
492 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
493 {
494 struct r600_context *rctx = (struct r600_context *)ctx;
495 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
496 }
497
498 /*
499 * infeered state between dsa and stencil ref
500 */
501 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
502 {
503 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
504 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
505 struct si_state_dsa *dsa = rctx->queued.named.dsa;
506
507 if (pm4 == NULL)
508 return;
509
510 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
511 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
512 S_028430_STENCILMASK(dsa->valuemask[0]) |
513 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
514 S_028430_STENCILOPVAL(1));
515 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
516 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
517 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
518 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
519 S_028434_STENCILOPVAL_BF(1));
520
521 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
522 }
523
524 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
525 const struct pipe_stencil_ref *state)
526 {
527 struct r600_context *rctx = (struct r600_context *)ctx;
528 rctx->stencil_ref = *state;
529 si_update_dsa_stencil_ref(rctx);
530 }
531
532
533 /*
534 * DSA
535 */
536
537 static uint32_t si_translate_stencil_op(int s_op)
538 {
539 switch (s_op) {
540 case PIPE_STENCIL_OP_KEEP:
541 return V_02842C_STENCIL_KEEP;
542 case PIPE_STENCIL_OP_ZERO:
543 return V_02842C_STENCIL_ZERO;
544 case PIPE_STENCIL_OP_REPLACE:
545 return V_02842C_STENCIL_REPLACE_TEST;
546 case PIPE_STENCIL_OP_INCR:
547 return V_02842C_STENCIL_ADD_CLAMP;
548 case PIPE_STENCIL_OP_DECR:
549 return V_02842C_STENCIL_SUB_CLAMP;
550 case PIPE_STENCIL_OP_INCR_WRAP:
551 return V_02842C_STENCIL_ADD_WRAP;
552 case PIPE_STENCIL_OP_DECR_WRAP:
553 return V_02842C_STENCIL_SUB_WRAP;
554 case PIPE_STENCIL_OP_INVERT:
555 return V_02842C_STENCIL_INVERT;
556 default:
557 R600_ERR("Unknown stencil op %d", s_op);
558 assert(0);
559 break;
560 }
561 return 0;
562 }
563
564 static void *si_create_dsa_state(struct pipe_context *ctx,
565 const struct pipe_depth_stencil_alpha_state *state)
566 {
567 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
568 struct si_pm4_state *pm4 = &dsa->pm4;
569 unsigned db_depth_control;
570 unsigned db_render_override, db_render_control;
571 uint32_t db_stencil_control = 0;
572
573 if (dsa == NULL) {
574 return NULL;
575 }
576
577 dsa->valuemask[0] = state->stencil[0].valuemask;
578 dsa->valuemask[1] = state->stencil[1].valuemask;
579 dsa->writemask[0] = state->stencil[0].writemask;
580 dsa->writemask[1] = state->stencil[1].writemask;
581
582 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
583 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
584 S_028800_ZFUNC(state->depth.func);
585
586 /* stencil */
587 if (state->stencil[0].enabled) {
588 db_depth_control |= S_028800_STENCIL_ENABLE(1);
589 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
590 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
591 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
592 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
593
594 if (state->stencil[1].enabled) {
595 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
596 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
597 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
598 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
599 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
600 }
601 }
602
603 /* alpha */
604 if (state->alpha.enabled) {
605 dsa->alpha_func = state->alpha.func;
606 dsa->alpha_ref = state->alpha.ref_value;
607 } else {
608 dsa->alpha_func = PIPE_FUNC_ALWAYS;
609 }
610
611 /* misc */
612 db_render_control = 0;
613 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
614 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
615 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
616 /* TODO db_render_override depends on query */
617 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
618 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
619 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
620 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
621 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
622 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
623 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
624 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
625 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
626 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
627 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
628 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
629 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
630 dsa->db_render_override = db_render_override;
631
632 return dsa;
633 }
634
635 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
636 {
637 struct r600_context *rctx = (struct r600_context *)ctx;
638 struct si_state_dsa *dsa = state;
639
640 if (state == NULL)
641 return;
642
643 si_pm4_bind_state(rctx, dsa, dsa);
644 si_update_dsa_stencil_ref(rctx);
645 }
646
647 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
648 {
649 struct r600_context *rctx = (struct r600_context *)ctx;
650 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
651 }
652
653 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
654 bool copy_stencil)
655 {
656 struct pipe_depth_stencil_alpha_state dsa;
657 struct si_state_dsa *state;
658
659 memset(&dsa, 0, sizeof(dsa));
660
661 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
662 if (copy_depth || copy_stencil) {
663 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
664 S_028000_DEPTH_COPY(copy_depth) |
665 S_028000_STENCIL_COPY(copy_stencil) |
666 S_028000_COPY_CENTROID(1));
667 } else {
668 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
669 S_028000_DEPTH_COMPRESS_DISABLE(1) |
670 S_028000_STENCIL_COMPRESS_DISABLE(1));
671 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
672 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
673 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
674 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
675 S_02800C_DISABLE_TILE_RATE_TILES(1));
676 }
677
678 return state;
679 }
680
681 /*
682 * format translation
683 */
684 static uint32_t si_translate_colorformat(enum pipe_format format)
685 {
686 switch (format) {
687 /* 8-bit buffers. */
688 case PIPE_FORMAT_A8_UNORM:
689 case PIPE_FORMAT_A8_SNORM:
690 case PIPE_FORMAT_A8_UINT:
691 case PIPE_FORMAT_A8_SINT:
692 case PIPE_FORMAT_I8_UNORM:
693 case PIPE_FORMAT_I8_SNORM:
694 case PIPE_FORMAT_I8_UINT:
695 case PIPE_FORMAT_I8_SINT:
696 case PIPE_FORMAT_L8_UNORM:
697 case PIPE_FORMAT_L8_SNORM:
698 case PIPE_FORMAT_L8_UINT:
699 case PIPE_FORMAT_L8_SINT:
700 case PIPE_FORMAT_L8_SRGB:
701 case PIPE_FORMAT_R8_UNORM:
702 case PIPE_FORMAT_R8_SNORM:
703 case PIPE_FORMAT_R8_UINT:
704 case PIPE_FORMAT_R8_SINT:
705 return V_028C70_COLOR_8;
706
707 /* 16-bit buffers. */
708 case PIPE_FORMAT_B5G6R5_UNORM:
709 return V_028C70_COLOR_5_6_5;
710
711 case PIPE_FORMAT_B5G5R5A1_UNORM:
712 case PIPE_FORMAT_B5G5R5X1_UNORM:
713 return V_028C70_COLOR_1_5_5_5;
714
715 case PIPE_FORMAT_B4G4R4A4_UNORM:
716 case PIPE_FORMAT_B4G4R4X4_UNORM:
717 return V_028C70_COLOR_4_4_4_4;
718
719 case PIPE_FORMAT_L8A8_UNORM:
720 case PIPE_FORMAT_L8A8_SNORM:
721 case PIPE_FORMAT_L8A8_UINT:
722 case PIPE_FORMAT_L8A8_SINT:
723 case PIPE_FORMAT_L8A8_SRGB:
724 case PIPE_FORMAT_R8G8_SNORM:
725 case PIPE_FORMAT_R8G8_UNORM:
726 case PIPE_FORMAT_R8G8_UINT:
727 case PIPE_FORMAT_R8G8_SINT:
728 return V_028C70_COLOR_8_8;
729
730 case PIPE_FORMAT_Z16_UNORM:
731 case PIPE_FORMAT_R16_UNORM:
732 case PIPE_FORMAT_R16_SNORM:
733 case PIPE_FORMAT_R16_UINT:
734 case PIPE_FORMAT_R16_SINT:
735 case PIPE_FORMAT_R16_FLOAT:
736 case PIPE_FORMAT_L16_UNORM:
737 case PIPE_FORMAT_L16_SNORM:
738 case PIPE_FORMAT_L16_FLOAT:
739 case PIPE_FORMAT_I16_UNORM:
740 case PIPE_FORMAT_I16_SNORM:
741 case PIPE_FORMAT_I16_FLOAT:
742 case PIPE_FORMAT_A16_UNORM:
743 case PIPE_FORMAT_A16_SNORM:
744 case PIPE_FORMAT_A16_FLOAT:
745 return V_028C70_COLOR_16;
746
747 /* 32-bit buffers. */
748 case PIPE_FORMAT_A8B8G8R8_SRGB:
749 case PIPE_FORMAT_A8B8G8R8_UNORM:
750 case PIPE_FORMAT_A8R8G8B8_UNORM:
751 case PIPE_FORMAT_B8G8R8A8_SRGB:
752 case PIPE_FORMAT_B8G8R8A8_UNORM:
753 case PIPE_FORMAT_B8G8R8X8_UNORM:
754 case PIPE_FORMAT_R8G8B8A8_SNORM:
755 case PIPE_FORMAT_R8G8B8A8_UNORM:
756 case PIPE_FORMAT_R8G8B8X8_UNORM:
757 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
758 case PIPE_FORMAT_X8B8G8R8_UNORM:
759 case PIPE_FORMAT_X8R8G8B8_UNORM:
760 case PIPE_FORMAT_R8G8B8_UNORM:
761 case PIPE_FORMAT_R8G8B8A8_SSCALED:
762 case PIPE_FORMAT_R8G8B8A8_USCALED:
763 case PIPE_FORMAT_R8G8B8A8_SINT:
764 case PIPE_FORMAT_R8G8B8A8_UINT:
765 return V_028C70_COLOR_8_8_8_8;
766
767 case PIPE_FORMAT_R10G10B10A2_UNORM:
768 case PIPE_FORMAT_R10G10B10X2_SNORM:
769 case PIPE_FORMAT_B10G10R10A2_UNORM:
770 case PIPE_FORMAT_B10G10R10A2_UINT:
771 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
772 return V_028C70_COLOR_2_10_10_10;
773
774 case PIPE_FORMAT_Z24X8_UNORM:
775 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
776 return V_028C70_COLOR_8_24;
777
778 case PIPE_FORMAT_X8Z24_UNORM:
779 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
780 return V_028C70_COLOR_24_8;
781
782 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
783 return V_028C70_COLOR_X24_8_32_FLOAT;
784
785 case PIPE_FORMAT_I32_FLOAT:
786 case PIPE_FORMAT_L32_FLOAT:
787 case PIPE_FORMAT_R32_FLOAT:
788 case PIPE_FORMAT_A32_FLOAT:
789 case PIPE_FORMAT_Z32_FLOAT:
790 return V_028C70_COLOR_32;
791
792 case PIPE_FORMAT_L16A16_UNORM:
793 case PIPE_FORMAT_L16A16_SNORM:
794 case PIPE_FORMAT_L16A16_FLOAT:
795 case PIPE_FORMAT_R16G16_SSCALED:
796 case PIPE_FORMAT_R16G16_UNORM:
797 case PIPE_FORMAT_R16G16_SNORM:
798 case PIPE_FORMAT_R16G16_UINT:
799 case PIPE_FORMAT_R16G16_SINT:
800 case PIPE_FORMAT_R16G16_FLOAT:
801 return V_028C70_COLOR_16_16;
802
803 case PIPE_FORMAT_R11G11B10_FLOAT:
804 return V_028C70_COLOR_10_11_11;
805
806 /* 64-bit buffers. */
807 case PIPE_FORMAT_R16G16B16_USCALED:
808 case PIPE_FORMAT_R16G16B16_SSCALED:
809 case PIPE_FORMAT_R16G16B16A16_UINT:
810 case PIPE_FORMAT_R16G16B16A16_SINT:
811 case PIPE_FORMAT_R16G16B16A16_USCALED:
812 case PIPE_FORMAT_R16G16B16A16_SSCALED:
813 case PIPE_FORMAT_R16G16B16A16_UNORM:
814 case PIPE_FORMAT_R16G16B16A16_SNORM:
815 case PIPE_FORMAT_R16G16B16_FLOAT:
816 case PIPE_FORMAT_R16G16B16A16_FLOAT:
817 return V_028C70_COLOR_16_16_16_16;
818
819 case PIPE_FORMAT_L32A32_FLOAT:
820 case PIPE_FORMAT_L32A32_UINT:
821 case PIPE_FORMAT_L32A32_SINT:
822 case PIPE_FORMAT_R32G32_FLOAT:
823 case PIPE_FORMAT_R32G32_USCALED:
824 case PIPE_FORMAT_R32G32_SSCALED:
825 case PIPE_FORMAT_R32G32_SINT:
826 case PIPE_FORMAT_R32G32_UINT:
827 return V_028C70_COLOR_32_32;
828
829 /* 128-bit buffers. */
830 case PIPE_FORMAT_R32G32B32A32_SNORM:
831 case PIPE_FORMAT_R32G32B32A32_UNORM:
832 case PIPE_FORMAT_R32G32B32A32_SSCALED:
833 case PIPE_FORMAT_R32G32B32A32_USCALED:
834 case PIPE_FORMAT_R32G32B32A32_SINT:
835 case PIPE_FORMAT_R32G32B32A32_UINT:
836 case PIPE_FORMAT_R32G32B32A32_FLOAT:
837 return V_028C70_COLOR_32_32_32_32;
838
839 /* YUV buffers. */
840 case PIPE_FORMAT_UYVY:
841 case PIPE_FORMAT_YUYV:
842 /* 96-bit buffers. */
843 case PIPE_FORMAT_R32G32B32_FLOAT:
844 /* 8-bit buffers. */
845 case PIPE_FORMAT_L4A4_UNORM:
846 case PIPE_FORMAT_R4A4_UNORM:
847 case PIPE_FORMAT_A4R4_UNORM:
848 default:
849 return V_028C70_COLOR_INVALID; /* Unsupported. */
850 }
851 }
852
853 static uint32_t si_translate_colorswap(enum pipe_format format)
854 {
855 switch (format) {
856 /* 8-bit buffers. */
857 case PIPE_FORMAT_L4A4_UNORM:
858 case PIPE_FORMAT_A4R4_UNORM:
859 return V_028C70_SWAP_ALT;
860
861 case PIPE_FORMAT_A8_UNORM:
862 case PIPE_FORMAT_A8_SNORM:
863 case PIPE_FORMAT_A8_UINT:
864 case PIPE_FORMAT_A8_SINT:
865 case PIPE_FORMAT_R4A4_UNORM:
866 return V_028C70_SWAP_ALT_REV;
867 case PIPE_FORMAT_I8_UNORM:
868 case PIPE_FORMAT_I8_SNORM:
869 case PIPE_FORMAT_L8_UNORM:
870 case PIPE_FORMAT_L8_SNORM:
871 case PIPE_FORMAT_I8_UINT:
872 case PIPE_FORMAT_I8_SINT:
873 case PIPE_FORMAT_L8_UINT:
874 case PIPE_FORMAT_L8_SINT:
875 case PIPE_FORMAT_L8_SRGB:
876 case PIPE_FORMAT_R8_UNORM:
877 case PIPE_FORMAT_R8_SNORM:
878 case PIPE_FORMAT_R8_UINT:
879 case PIPE_FORMAT_R8_SINT:
880 return V_028C70_SWAP_STD;
881
882 /* 16-bit buffers. */
883 case PIPE_FORMAT_B5G6R5_UNORM:
884 return V_028C70_SWAP_STD_REV;
885
886 case PIPE_FORMAT_B5G5R5A1_UNORM:
887 case PIPE_FORMAT_B5G5R5X1_UNORM:
888 return V_028C70_SWAP_ALT;
889
890 case PIPE_FORMAT_B4G4R4A4_UNORM:
891 case PIPE_FORMAT_B4G4R4X4_UNORM:
892 return V_028C70_SWAP_ALT;
893
894 case PIPE_FORMAT_Z16_UNORM:
895 return V_028C70_SWAP_STD;
896
897 case PIPE_FORMAT_L8A8_UNORM:
898 case PIPE_FORMAT_L8A8_SNORM:
899 case PIPE_FORMAT_L8A8_UINT:
900 case PIPE_FORMAT_L8A8_SINT:
901 case PIPE_FORMAT_L8A8_SRGB:
902 return V_028C70_SWAP_ALT;
903 case PIPE_FORMAT_R8G8_SNORM:
904 case PIPE_FORMAT_R8G8_UNORM:
905 case PIPE_FORMAT_R8G8_UINT:
906 case PIPE_FORMAT_R8G8_SINT:
907 return V_028C70_SWAP_STD;
908
909 case PIPE_FORMAT_I16_UNORM:
910 case PIPE_FORMAT_I16_SNORM:
911 case PIPE_FORMAT_I16_FLOAT:
912 case PIPE_FORMAT_L16_UNORM:
913 case PIPE_FORMAT_L16_SNORM:
914 case PIPE_FORMAT_L16_FLOAT:
915 case PIPE_FORMAT_R16_UNORM:
916 case PIPE_FORMAT_R16_SNORM:
917 case PIPE_FORMAT_R16_UINT:
918 case PIPE_FORMAT_R16_SINT:
919 case PIPE_FORMAT_R16_FLOAT:
920 return V_028C70_SWAP_STD;
921
922 case PIPE_FORMAT_A16_UNORM:
923 case PIPE_FORMAT_A16_SNORM:
924 case PIPE_FORMAT_A16_FLOAT:
925 return V_028C70_SWAP_ALT_REV;
926
927 /* 32-bit buffers. */
928 case PIPE_FORMAT_A8B8G8R8_SRGB:
929 return V_028C70_SWAP_STD_REV;
930 case PIPE_FORMAT_B8G8R8A8_SRGB:
931 return V_028C70_SWAP_ALT;
932
933 case PIPE_FORMAT_B8G8R8A8_UNORM:
934 case PIPE_FORMAT_B8G8R8X8_UNORM:
935 return V_028C70_SWAP_ALT;
936
937 case PIPE_FORMAT_A8R8G8B8_UNORM:
938 case PIPE_FORMAT_X8R8G8B8_UNORM:
939 return V_028C70_SWAP_ALT_REV;
940 case PIPE_FORMAT_R8G8B8A8_SNORM:
941 case PIPE_FORMAT_R8G8B8A8_UNORM:
942 case PIPE_FORMAT_R8G8B8A8_SSCALED:
943 case PIPE_FORMAT_R8G8B8A8_USCALED:
944 case PIPE_FORMAT_R8G8B8A8_SINT:
945 case PIPE_FORMAT_R8G8B8A8_UINT:
946 case PIPE_FORMAT_R8G8B8X8_UNORM:
947 return V_028C70_SWAP_STD;
948
949 case PIPE_FORMAT_A8B8G8R8_UNORM:
950 case PIPE_FORMAT_X8B8G8R8_UNORM:
951 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
952 return V_028C70_SWAP_STD_REV;
953
954 case PIPE_FORMAT_Z24X8_UNORM:
955 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
956 return V_028C70_SWAP_STD;
957
958 case PIPE_FORMAT_X8Z24_UNORM:
959 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
960 return V_028C70_SWAP_STD;
961
962 case PIPE_FORMAT_R10G10B10A2_UNORM:
963 case PIPE_FORMAT_R10G10B10X2_SNORM:
964 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
965 return V_028C70_SWAP_STD;
966
967 case PIPE_FORMAT_B10G10R10A2_UNORM:
968 case PIPE_FORMAT_B10G10R10A2_UINT:
969 return V_028C70_SWAP_ALT;
970
971 case PIPE_FORMAT_R11G11B10_FLOAT:
972 case PIPE_FORMAT_I32_FLOAT:
973 case PIPE_FORMAT_L32_FLOAT:
974 case PIPE_FORMAT_R32_FLOAT:
975 case PIPE_FORMAT_R32_UINT:
976 case PIPE_FORMAT_R32_SINT:
977 case PIPE_FORMAT_Z32_FLOAT:
978 case PIPE_FORMAT_R16G16_FLOAT:
979 case PIPE_FORMAT_R16G16_UNORM:
980 case PIPE_FORMAT_R16G16_SNORM:
981 case PIPE_FORMAT_R16G16_UINT:
982 case PIPE_FORMAT_R16G16_SINT:
983 return V_028C70_SWAP_STD;
984
985 case PIPE_FORMAT_L16A16_UNORM:
986 case PIPE_FORMAT_L16A16_SNORM:
987 case PIPE_FORMAT_L16A16_FLOAT:
988 return V_028C70_SWAP_ALT;
989
990 case PIPE_FORMAT_A32_FLOAT:
991 return V_028C70_SWAP_ALT_REV;
992
993 /* 64-bit buffers. */
994 case PIPE_FORMAT_R32G32_FLOAT:
995 case PIPE_FORMAT_R32G32_UINT:
996 case PIPE_FORMAT_R32G32_SINT:
997 case PIPE_FORMAT_R16G16B16A16_UNORM:
998 case PIPE_FORMAT_R16G16B16A16_SNORM:
999 case PIPE_FORMAT_R16G16B16A16_USCALED:
1000 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1001 case PIPE_FORMAT_R16G16B16A16_UINT:
1002 case PIPE_FORMAT_R16G16B16A16_SINT:
1003 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1004 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1005 return V_028C70_SWAP_STD;
1006
1007 case PIPE_FORMAT_L32A32_FLOAT:
1008 case PIPE_FORMAT_L32A32_UINT:
1009 case PIPE_FORMAT_L32A32_SINT:
1010 return V_028C70_SWAP_ALT;
1011
1012 /* 128-bit buffers. */
1013 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1014 case PIPE_FORMAT_R32G32B32A32_SNORM:
1015 case PIPE_FORMAT_R32G32B32A32_UNORM:
1016 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1017 case PIPE_FORMAT_R32G32B32A32_USCALED:
1018 case PIPE_FORMAT_R32G32B32A32_SINT:
1019 case PIPE_FORMAT_R32G32B32A32_UINT:
1020 return V_028C70_SWAP_STD;
1021 default:
1022 R600_ERR("unsupported colorswap format %d\n", format);
1023 return ~0U;
1024 }
1025 return ~0U;
1026 }
1027
1028 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1029 {
1030 if (R600_BIG_ENDIAN) {
1031 switch(colorformat) {
1032 /* 8-bit buffers. */
1033 case V_028C70_COLOR_8:
1034 return V_028C70_ENDIAN_NONE;
1035
1036 /* 16-bit buffers. */
1037 case V_028C70_COLOR_5_6_5:
1038 case V_028C70_COLOR_1_5_5_5:
1039 case V_028C70_COLOR_4_4_4_4:
1040 case V_028C70_COLOR_16:
1041 case V_028C70_COLOR_8_8:
1042 return V_028C70_ENDIAN_8IN16;
1043
1044 /* 32-bit buffers. */
1045 case V_028C70_COLOR_8_8_8_8:
1046 case V_028C70_COLOR_2_10_10_10:
1047 case V_028C70_COLOR_8_24:
1048 case V_028C70_COLOR_24_8:
1049 case V_028C70_COLOR_16_16:
1050 return V_028C70_ENDIAN_8IN32;
1051
1052 /* 64-bit buffers. */
1053 case V_028C70_COLOR_16_16_16_16:
1054 return V_028C70_ENDIAN_8IN16;
1055
1056 case V_028C70_COLOR_32_32:
1057 return V_028C70_ENDIAN_8IN32;
1058
1059 /* 128-bit buffers. */
1060 case V_028C70_COLOR_32_32_32_32:
1061 return V_028C70_ENDIAN_8IN32;
1062 default:
1063 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1064 }
1065 } else {
1066 return V_028C70_ENDIAN_NONE;
1067 }
1068 }
1069
1070 /* Returns the size in bits of the widest component of a CB format */
1071 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1072 {
1073 switch(colorformat) {
1074 case V_028C70_COLOR_4_4_4_4:
1075 return 4;
1076
1077 case V_028C70_COLOR_1_5_5_5:
1078 case V_028C70_COLOR_5_5_5_1:
1079 return 5;
1080
1081 case V_028C70_COLOR_5_6_5:
1082 return 6;
1083
1084 case V_028C70_COLOR_8:
1085 case V_028C70_COLOR_8_8:
1086 case V_028C70_COLOR_8_8_8_8:
1087 return 8;
1088
1089 case V_028C70_COLOR_10_10_10_2:
1090 case V_028C70_COLOR_2_10_10_10:
1091 return 10;
1092
1093 case V_028C70_COLOR_10_11_11:
1094 case V_028C70_COLOR_11_11_10:
1095 return 11;
1096
1097 case V_028C70_COLOR_16:
1098 case V_028C70_COLOR_16_16:
1099 case V_028C70_COLOR_16_16_16_16:
1100 return 16;
1101
1102 case V_028C70_COLOR_8_24:
1103 case V_028C70_COLOR_24_8:
1104 return 24;
1105
1106 case V_028C70_COLOR_32:
1107 case V_028C70_COLOR_32_32:
1108 case V_028C70_COLOR_32_32_32_32:
1109 case V_028C70_COLOR_X24_8_32_FLOAT:
1110 return 32;
1111 }
1112
1113 assert(!"Unknown maximum component size");
1114 return 0;
1115 }
1116
1117 static uint32_t si_translate_dbformat(enum pipe_format format)
1118 {
1119 switch (format) {
1120 case PIPE_FORMAT_Z16_UNORM:
1121 return V_028040_Z_16;
1122 case PIPE_FORMAT_Z24X8_UNORM:
1123 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1124 return V_028040_Z_24; /* XXX no longer supported on SI */
1125 case PIPE_FORMAT_Z32_FLOAT:
1126 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1127 return V_028040_Z_32_FLOAT;
1128 default:
1129 return V_028040_Z_INVALID;
1130 }
1131 }
1132
1133 /*
1134 * Texture translation
1135 */
1136
1137 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1138 enum pipe_format format,
1139 const struct util_format_description *desc,
1140 int first_non_void)
1141 {
1142 boolean uniform = TRUE;
1143 int i;
1144
1145 /* Colorspace (return non-RGB formats directly). */
1146 switch (desc->colorspace) {
1147 /* Depth stencil formats */
1148 case UTIL_FORMAT_COLORSPACE_ZS:
1149 switch (format) {
1150 case PIPE_FORMAT_Z16_UNORM:
1151 return V_008F14_IMG_DATA_FORMAT_16;
1152 case PIPE_FORMAT_X24S8_UINT:
1153 case PIPE_FORMAT_Z24X8_UNORM:
1154 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1155 return V_008F14_IMG_DATA_FORMAT_8_24;
1156 case PIPE_FORMAT_X8Z24_UNORM:
1157 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1158 return V_008F14_IMG_DATA_FORMAT_24_8;
1159 case PIPE_FORMAT_X32_S8X24_UINT:
1160 case PIPE_FORMAT_S8X24_UINT:
1161 case PIPE_FORMAT_S8_UINT:
1162 return V_008F14_IMG_DATA_FORMAT_8;
1163 case PIPE_FORMAT_Z32_FLOAT:
1164 return V_008F14_IMG_DATA_FORMAT_32;
1165 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1166 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1167 default:
1168 goto out_unknown;
1169 }
1170
1171 case UTIL_FORMAT_COLORSPACE_YUV:
1172 goto out_unknown; /* TODO */
1173
1174 case UTIL_FORMAT_COLORSPACE_SRGB:
1175 break;
1176
1177 default:
1178 break;
1179 }
1180
1181 /* TODO compressed formats */
1182
1183 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1184 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1185 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1186 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1187 }
1188
1189 /* R8G8Bx_SNORM - TODO CxV8U8 */
1190
1191 /* See whether the components are of the same size. */
1192 for (i = 1; i < desc->nr_channels; i++) {
1193 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1194 }
1195
1196 /* Non-uniform formats. */
1197 if (!uniform) {
1198 switch(desc->nr_channels) {
1199 case 3:
1200 if (desc->channel[0].size == 5 &&
1201 desc->channel[1].size == 6 &&
1202 desc->channel[2].size == 5) {
1203 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1204 }
1205 goto out_unknown;
1206 case 4:
1207 if (desc->channel[0].size == 5 &&
1208 desc->channel[1].size == 5 &&
1209 desc->channel[2].size == 5 &&
1210 desc->channel[3].size == 1) {
1211 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1212 }
1213 if (desc->channel[0].size == 10 &&
1214 desc->channel[1].size == 10 &&
1215 desc->channel[2].size == 10 &&
1216 desc->channel[3].size == 2) {
1217 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1218 }
1219 goto out_unknown;
1220 }
1221 goto out_unknown;
1222 }
1223
1224 if (first_non_void < 0 || first_non_void > 3)
1225 goto out_unknown;
1226
1227 /* uniform formats */
1228 switch (desc->channel[first_non_void].size) {
1229 case 4:
1230 switch (desc->nr_channels) {
1231 #if 0 /* Not supported for render targets */
1232 case 2:
1233 return V_008F14_IMG_DATA_FORMAT_4_4;
1234 #endif
1235 case 4:
1236 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1237 }
1238 break;
1239 case 8:
1240 switch (desc->nr_channels) {
1241 case 1:
1242 return V_008F14_IMG_DATA_FORMAT_8;
1243 case 2:
1244 return V_008F14_IMG_DATA_FORMAT_8_8;
1245 case 4:
1246 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1247 }
1248 break;
1249 case 16:
1250 switch (desc->nr_channels) {
1251 case 1:
1252 return V_008F14_IMG_DATA_FORMAT_16;
1253 case 2:
1254 return V_008F14_IMG_DATA_FORMAT_16_16;
1255 case 4:
1256 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1257 }
1258 break;
1259 case 32:
1260 switch (desc->nr_channels) {
1261 case 1:
1262 return V_008F14_IMG_DATA_FORMAT_32;
1263 case 2:
1264 return V_008F14_IMG_DATA_FORMAT_32_32;
1265 #if 0 /* Not supported for render targets */
1266 case 3:
1267 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1268 #endif
1269 case 4:
1270 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1271 }
1272 }
1273
1274 out_unknown:
1275 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1276 return ~0;
1277 }
1278
1279 static unsigned si_tex_wrap(unsigned wrap)
1280 {
1281 switch (wrap) {
1282 default:
1283 case PIPE_TEX_WRAP_REPEAT:
1284 return V_008F30_SQ_TEX_WRAP;
1285 case PIPE_TEX_WRAP_CLAMP:
1286 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1287 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1288 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1289 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1290 return V_008F30_SQ_TEX_CLAMP_BORDER;
1291 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1292 return V_008F30_SQ_TEX_MIRROR;
1293 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1294 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1295 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1296 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1297 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1298 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1299 }
1300 }
1301
1302 static unsigned si_tex_filter(unsigned filter)
1303 {
1304 switch (filter) {
1305 default:
1306 case PIPE_TEX_FILTER_NEAREST:
1307 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1308 case PIPE_TEX_FILTER_LINEAR:
1309 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1310 }
1311 }
1312
1313 static unsigned si_tex_mipfilter(unsigned filter)
1314 {
1315 switch (filter) {
1316 case PIPE_TEX_MIPFILTER_NEAREST:
1317 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1318 case PIPE_TEX_MIPFILTER_LINEAR:
1319 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1320 default:
1321 case PIPE_TEX_MIPFILTER_NONE:
1322 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1323 }
1324 }
1325
1326 static unsigned si_tex_compare(unsigned compare)
1327 {
1328 switch (compare) {
1329 default:
1330 case PIPE_FUNC_NEVER:
1331 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1332 case PIPE_FUNC_LESS:
1333 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1334 case PIPE_FUNC_EQUAL:
1335 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1336 case PIPE_FUNC_LEQUAL:
1337 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1338 case PIPE_FUNC_GREATER:
1339 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1340 case PIPE_FUNC_NOTEQUAL:
1341 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1342 case PIPE_FUNC_GEQUAL:
1343 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1344 case PIPE_FUNC_ALWAYS:
1345 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1346 }
1347 }
1348
1349 static unsigned si_tex_dim(unsigned dim)
1350 {
1351 switch (dim) {
1352 default:
1353 case PIPE_TEXTURE_1D:
1354 return V_008F1C_SQ_RSRC_IMG_1D;
1355 case PIPE_TEXTURE_1D_ARRAY:
1356 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1357 case PIPE_TEXTURE_2D:
1358 case PIPE_TEXTURE_RECT:
1359 return V_008F1C_SQ_RSRC_IMG_2D;
1360 case PIPE_TEXTURE_2D_ARRAY:
1361 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1362 case PIPE_TEXTURE_3D:
1363 return V_008F1C_SQ_RSRC_IMG_3D;
1364 case PIPE_TEXTURE_CUBE:
1365 return V_008F1C_SQ_RSRC_IMG_CUBE;
1366 }
1367 }
1368
1369 /*
1370 * Format support testing
1371 */
1372
1373 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1374 {
1375 return si_translate_texformat(screen, format, util_format_description(format),
1376 util_format_get_first_non_void_channel(format)) != ~0U;
1377 }
1378
1379 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1380 enum pipe_format format,
1381 const struct util_format_description *desc,
1382 int first_non_void)
1383 {
1384 unsigned type = desc->channel[first_non_void].type;
1385 int i;
1386
1387 if (type == UTIL_FORMAT_TYPE_FIXED)
1388 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1389
1390 /* See whether the components are of the same size. */
1391 for (i = 0; i < desc->nr_channels; i++) {
1392 if (desc->channel[first_non_void].size != desc->channel[i].size)
1393 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1394 }
1395
1396 switch (desc->channel[first_non_void].size) {
1397 case 8:
1398 switch (desc->nr_channels) {
1399 case 1:
1400 return V_008F0C_BUF_DATA_FORMAT_8;
1401 case 2:
1402 return V_008F0C_BUF_DATA_FORMAT_8_8;
1403 case 3:
1404 case 4:
1405 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1406 }
1407 break;
1408 case 16:
1409 switch (desc->nr_channels) {
1410 case 1:
1411 return V_008F0C_BUF_DATA_FORMAT_16;
1412 case 2:
1413 return V_008F0C_BUF_DATA_FORMAT_16_16;
1414 case 3:
1415 case 4:
1416 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1417 }
1418 break;
1419 case 32:
1420 if (type != UTIL_FORMAT_TYPE_FLOAT)
1421 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1422
1423 switch (desc->nr_channels) {
1424 case 1:
1425 return V_008F0C_BUF_DATA_FORMAT_32;
1426 case 2:
1427 return V_008F0C_BUF_DATA_FORMAT_32_32;
1428 case 3:
1429 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1430 case 4:
1431 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1432 }
1433 break;
1434 }
1435
1436 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1437 }
1438
1439 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1440 {
1441 const struct util_format_description *desc;
1442 int first_non_void;
1443 unsigned data_format;
1444
1445 desc = util_format_description(format);
1446 first_non_void = util_format_get_first_non_void_channel(format);
1447 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1448 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1449 }
1450
1451 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1452 {
1453 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1454 si_translate_colorswap(format) != ~0U;
1455 }
1456
1457 static bool si_is_zs_format_supported(enum pipe_format format)
1458 {
1459 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1460 }
1461
1462 boolean si_is_format_supported(struct pipe_screen *screen,
1463 enum pipe_format format,
1464 enum pipe_texture_target target,
1465 unsigned sample_count,
1466 unsigned usage)
1467 {
1468 unsigned retval = 0;
1469
1470 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1471 R600_ERR("r600: unsupported texture type %d\n", target);
1472 return FALSE;
1473 }
1474
1475 if (!util_format_is_supported(format, usage))
1476 return FALSE;
1477
1478 /* Multisample */
1479 if (sample_count > 1)
1480 return FALSE;
1481
1482 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1483 si_is_sampler_format_supported(screen, format)) {
1484 retval |= PIPE_BIND_SAMPLER_VIEW;
1485 }
1486
1487 if ((usage & (PIPE_BIND_RENDER_TARGET |
1488 PIPE_BIND_DISPLAY_TARGET |
1489 PIPE_BIND_SCANOUT |
1490 PIPE_BIND_SHARED)) &&
1491 si_is_colorbuffer_format_supported(format)) {
1492 retval |= usage &
1493 (PIPE_BIND_RENDER_TARGET |
1494 PIPE_BIND_DISPLAY_TARGET |
1495 PIPE_BIND_SCANOUT |
1496 PIPE_BIND_SHARED);
1497 }
1498
1499 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1500 si_is_zs_format_supported(format)) {
1501 retval |= PIPE_BIND_DEPTH_STENCIL;
1502 }
1503
1504 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1505 si_is_vertex_format_supported(screen, format)) {
1506 retval |= PIPE_BIND_VERTEX_BUFFER;
1507 }
1508
1509 if (usage & PIPE_BIND_TRANSFER_READ)
1510 retval |= PIPE_BIND_TRANSFER_READ;
1511 if (usage & PIPE_BIND_TRANSFER_WRITE)
1512 retval |= PIPE_BIND_TRANSFER_WRITE;
1513
1514 return retval == usage;
1515 }
1516
1517 static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level)
1518 {
1519 if (util_format_is_depth_or_stencil(rtex->real_format)) {
1520 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1521 return 4;
1522 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1523 switch (rtex->real_format) {
1524 case PIPE_FORMAT_Z16_UNORM:
1525 return 5;
1526 case PIPE_FORMAT_Z24X8_UNORM:
1527 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1528 case PIPE_FORMAT_Z32_FLOAT:
1529 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1530 return 6;
1531 default:
1532 return 7;
1533 }
1534 }
1535 }
1536
1537 switch (rtex->surface.level[level].mode) {
1538 default:
1539 assert(!"Invalid surface mode");
1540 /* Fall through */
1541 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1542 return 8;
1543 case RADEON_SURF_MODE_1D:
1544 if (rtex->surface.flags & RADEON_SURF_SCANOUT)
1545 return 9;
1546 else
1547 return 13;
1548 case RADEON_SURF_MODE_2D:
1549 if (rtex->surface.flags & RADEON_SURF_SCANOUT) {
1550 switch (util_format_get_blocksize(rtex->real_format)) {
1551 case 1:
1552 return 10;
1553 case 2:
1554 return 11;
1555 default:
1556 assert(!"Invalid block size");
1557 /* Fall through */
1558 case 4:
1559 return 12;
1560 }
1561 } else {
1562 switch (util_format_get_blocksize(rtex->real_format)) {
1563 case 1:
1564 return 14;
1565 case 2:
1566 return 15;
1567 case 4:
1568 return 16;
1569 case 8:
1570 return 17;
1571 default:
1572 return 13;
1573 }
1574 }
1575 }
1576 }
1577
1578 /*
1579 * framebuffer handling
1580 */
1581
1582 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1583 const struct pipe_framebuffer_state *state, int cb)
1584 {
1585 struct r600_resource_texture *rtex;
1586 struct r600_surface *surf;
1587 unsigned level = state->cbufs[cb]->u.tex.level;
1588 unsigned pitch, slice;
1589 unsigned color_info;
1590 unsigned tile_mode_index;
1591 unsigned format, swap, ntype, endian;
1592 uint64_t offset;
1593 const struct util_format_description *desc;
1594 int i;
1595 unsigned blend_clamp = 0, blend_bypass = 0;
1596 unsigned max_comp_size;
1597
1598 surf = (struct r600_surface *)state->cbufs[cb];
1599 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1600
1601 offset = rtex->surface.level[level].offset;
1602 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1603 offset += rtex->surface.level[level].slice_size *
1604 state->cbufs[cb]->u.tex.first_layer;
1605 }
1606 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1607 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1608 if (slice) {
1609 slice = slice - 1;
1610 }
1611
1612 tile_mode_index = si_tile_mode_index(rtex, level);
1613
1614 desc = util_format_description(surf->base.format);
1615 for (i = 0; i < 4; i++) {
1616 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1617 break;
1618 }
1619 }
1620 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1621 ntype = V_028C70_NUMBER_FLOAT;
1622 } else {
1623 ntype = V_028C70_NUMBER_UNORM;
1624 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1625 ntype = V_028C70_NUMBER_SRGB;
1626 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1627 if (desc->channel[i].normalized)
1628 ntype = V_028C70_NUMBER_SNORM;
1629 else if (desc->channel[i].pure_integer)
1630 ntype = V_028C70_NUMBER_SINT;
1631 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1632 if (desc->channel[i].normalized)
1633 ntype = V_028C70_NUMBER_UNORM;
1634 else if (desc->channel[i].pure_integer)
1635 ntype = V_028C70_NUMBER_UINT;
1636 }
1637 }
1638
1639 format = si_translate_colorformat(surf->base.format);
1640 if (format == V_028C70_COLOR_INVALID) {
1641 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1642 }
1643 assert(format != V_028C70_COLOR_INVALID);
1644 swap = si_translate_colorswap(surf->base.format);
1645 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1646 endian = V_028C70_ENDIAN_NONE;
1647 } else {
1648 endian = si_colorformat_endian_swap(format);
1649 }
1650
1651 /* blend clamp should be set for all NORM/SRGB types */
1652 if (ntype == V_028C70_NUMBER_UNORM ||
1653 ntype == V_028C70_NUMBER_SNORM ||
1654 ntype == V_028C70_NUMBER_SRGB)
1655 blend_clamp = 1;
1656
1657 /* set blend bypass according to docs if SINT/UINT or
1658 8/24 COLOR variants */
1659 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1660 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1661 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1662 blend_clamp = 0;
1663 blend_bypass = 1;
1664 }
1665
1666 color_info = S_028C70_FORMAT(format) |
1667 S_028C70_COMP_SWAP(swap) |
1668 S_028C70_BLEND_CLAMP(blend_clamp) |
1669 S_028C70_BLEND_BYPASS(blend_bypass) |
1670 S_028C70_NUMBER_TYPE(ntype) |
1671 S_028C70_ENDIAN(endian);
1672
1673 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1674 offset >>= 8;
1675
1676 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1677 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1678 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1679 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1680 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1681
1682 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1683 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1684 } else {
1685 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1686 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1687 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1688 }
1689 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1690 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
1691 S_028C74_TILE_MODE_INDEX(tile_mode_index));
1692
1693 /* Determine pixel shader export format */
1694 max_comp_size = si_colorformat_max_comp_size(format);
1695 if (ntype == V_028C70_NUMBER_SRGB ||
1696 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1697 max_comp_size <= 10) ||
1698 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1699 rctx->export_16bpc |= 1 << cb;
1700 }
1701 }
1702
1703 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1704 const struct pipe_framebuffer_state *state)
1705 {
1706 struct r600_resource_texture *rtex;
1707 struct r600_surface *surf;
1708 unsigned level, pitch, slice, format, tile_mode_index;
1709 uint32_t z_info, s_info;
1710 uint64_t z_offs, s_offs;
1711
1712 if (state->zsbuf == NULL) {
1713 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1714 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1715 return;
1716 }
1717
1718 surf = (struct r600_surface *)state->zsbuf;
1719 level = surf->base.u.tex.level;
1720 rtex = (struct r600_resource_texture*)surf->base.texture;
1721
1722 format = si_translate_dbformat(rtex->real_format);
1723
1724 if (format == V_028040_Z_INVALID) {
1725 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
1726 }
1727 assert(format != V_028040_Z_INVALID);
1728
1729 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1730 z_offs += rtex->surface.level[level].offset;
1731 s_offs += rtex->surface.stencil_level[level].offset;
1732
1733 z_offs >>= 8;
1734 s_offs >>= 8;
1735
1736 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1737 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1738 if (slice) {
1739 slice = slice - 1;
1740 }
1741
1742 z_info = S_028040_FORMAT(format);
1743 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1744 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1745 else
1746 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1747
1748 tile_mode_index = si_tile_mode_index(rtex, level);
1749 if (tile_mode_index < 4 || tile_mode_index > 7) {
1750 R600_ERR("Invalid DB tiling mode %d!\n",
1751 rtex->surface.level[level].mode);
1752 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1753 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1754 return;
1755 }
1756 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1757 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1758
1759 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1760 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1761 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1762
1763 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1));
1764 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1765 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1766
1767 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1768 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1769 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1770 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1771 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1772
1773 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1774 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1775 }
1776
1777 static void si_set_framebuffer_state(struct pipe_context *ctx,
1778 const struct pipe_framebuffer_state *state)
1779 {
1780 struct r600_context *rctx = (struct r600_context *)ctx;
1781 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1782 uint32_t shader_mask, tl, br;
1783 int tl_x, tl_y, br_x, br_y;
1784
1785 if (pm4 == NULL)
1786 return;
1787
1788 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1789
1790 if (state->zsbuf)
1791 si_pm4_inval_zsbuf_cache(pm4);
1792
1793 util_copy_framebuffer_state(&rctx->framebuffer, state);
1794
1795 /* build states */
1796 rctx->export_16bpc = 0;
1797 for (int i = 0; i < state->nr_cbufs; i++) {
1798 si_cb(rctx, pm4, state, i);
1799 }
1800 assert(!(rctx->export_16bpc & ~0xff));
1801 si_db(rctx, pm4, state);
1802
1803 shader_mask = 0;
1804 for (int i = 0; i < state->nr_cbufs; i++) {
1805 shader_mask |= 0xf << (i * 4);
1806 }
1807 tl_x = 0;
1808 tl_y = 0;
1809 br_x = state->width;
1810 br_y = state->height;
1811
1812 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1813 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1814
1815 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1816 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1817 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1818 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1819 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1820 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1821 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1822 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1823 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1824 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1825 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1826 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1827
1828 si_pm4_set_state(rctx, framebuffer, pm4);
1829 si_update_fb_rs_state(rctx);
1830 si_update_fb_blend_state(rctx);
1831 }
1832
1833 /*
1834 * shaders
1835 */
1836
1837 /* Compute the key for the hw shader variant */
1838 static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx,
1839 struct si_pipe_shader_selector *sel)
1840 {
1841 struct r600_context *rctx = (struct r600_context *)ctx;
1842 struct si_shader_key key;
1843 memset(&key, 0, sizeof(key));
1844
1845 if (sel->type == PIPE_SHADER_FRAGMENT) {
1846 if (sel->fs_write_all)
1847 key.nr_cbufs = rctx->framebuffer.nr_cbufs;
1848 key.export_16bpc = rctx->export_16bpc;
1849 if (rctx->queued.named.rasterizer) {
1850 key.color_two_side = rctx->queued.named.rasterizer->two_side;
1851 /*key.flatshade = rctx->queued.named.rasterizer->flatshade;*/
1852 }
1853 if (rctx->queued.named.dsa) {
1854 key.alpha_func = rctx->queued.named.dsa->alpha_func;
1855 key.alpha_ref = rctx->queued.named.dsa->alpha_ref;
1856 } else {
1857 key.alpha_func = PIPE_FUNC_ALWAYS;
1858 }
1859 }
1860
1861 return key;
1862 }
1863
1864 /* Select the hw shader variant depending on the current state.
1865 * (*dirty) is set to 1 if current variant was changed */
1866 int si_shader_select(struct pipe_context *ctx,
1867 struct si_pipe_shader_selector *sel,
1868 unsigned *dirty)
1869 {
1870 struct si_shader_key key;
1871 struct si_pipe_shader * shader = NULL;
1872 int r;
1873
1874 key = si_shader_selector_key(ctx, sel);
1875
1876 /* Check if we don't need to change anything.
1877 * This path is also used for most shaders that don't need multiple
1878 * variants, it will cost just a computation of the key and this
1879 * test. */
1880 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
1881 return 0;
1882 }
1883
1884 /* lookup if we have other variants in the list */
1885 if (sel->num_shaders > 1) {
1886 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1887
1888 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
1889 p = c;
1890 c = c->next_variant;
1891 }
1892
1893 if (c) {
1894 p->next_variant = c->next_variant;
1895 shader = c;
1896 }
1897 }
1898
1899 if (unlikely(!shader)) {
1900 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1901 shader->selector = sel;
1902
1903 r = si_pipe_shader_create(ctx, shader, key);
1904 if (unlikely(r)) {
1905 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1906 sel->type, r);
1907 sel->current = NULL;
1908 return r;
1909 }
1910
1911 /* We don't know the value of fs_write_all property until we built
1912 * at least one variant, so we may need to recompute the key (include
1913 * rctx->framebuffer.nr_cbufs) after building first variant. */
1914 if (sel->type == PIPE_SHADER_FRAGMENT &&
1915 sel->num_shaders == 0 &&
1916 shader->shader.fs_write_all) {
1917 sel->fs_write_all = 1;
1918 key = si_shader_selector_key(ctx, sel);
1919 }
1920
1921 shader->key = key;
1922 sel->num_shaders++;
1923 }
1924
1925 if (dirty)
1926 *dirty = 1;
1927
1928 shader->next_variant = sel->current;
1929 sel->current = shader;
1930
1931 return 0;
1932 }
1933
1934 static void *si_create_shader_state(struct pipe_context *ctx,
1935 const struct pipe_shader_state *state,
1936 unsigned pipe_shader_type)
1937 {
1938 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1939 int r;
1940
1941 sel->type = pipe_shader_type;
1942 sel->tokens = tgsi_dup_tokens(state->tokens);
1943 sel->so = state->stream_output;
1944
1945 r = si_shader_select(ctx, sel, NULL);
1946 if (r) {
1947 free(sel);
1948 return NULL;
1949 }
1950
1951 return sel;
1952 }
1953
1954 static void *si_create_fs_state(struct pipe_context *ctx,
1955 const struct pipe_shader_state *state)
1956 {
1957 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1958 }
1959
1960 static void *si_create_vs_state(struct pipe_context *ctx,
1961 const struct pipe_shader_state *state)
1962 {
1963 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1964 }
1965
1966 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1967 {
1968 struct r600_context *rctx = (struct r600_context *)ctx;
1969 struct si_pipe_shader_selector *sel = state;
1970
1971 if (rctx->vs_shader == sel)
1972 return;
1973
1974 rctx->vs_shader = sel;
1975
1976 if (sel && sel->current)
1977 si_pm4_bind_state(rctx, vs, sel->current->pm4);
1978 else
1979 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
1980 }
1981
1982 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1983 {
1984 struct r600_context *rctx = (struct r600_context *)ctx;
1985 struct si_pipe_shader_selector *sel = state;
1986
1987 if (rctx->ps_shader == sel)
1988 return;
1989
1990 rctx->ps_shader = sel;
1991
1992 if (sel && sel->current)
1993 si_pm4_bind_state(rctx, ps, sel->current->pm4);
1994 else
1995 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
1996 }
1997
1998 static void si_delete_shader_selector(struct pipe_context *ctx,
1999 struct si_pipe_shader_selector *sel)
2000 {
2001 struct r600_context *rctx = (struct r600_context *)ctx;
2002 struct si_pipe_shader *p = sel->current, *c;
2003
2004 while (p) {
2005 c = p->next_variant;
2006 si_pm4_delete_state(rctx, vs, p->pm4);
2007 si_pipe_shader_destroy(ctx, p);
2008 free(p);
2009 p = c;
2010 }
2011
2012 free(sel->tokens);
2013 free(sel);
2014 }
2015
2016 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2017 {
2018 struct r600_context *rctx = (struct r600_context *)ctx;
2019 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2020
2021 if (rctx->vs_shader == sel) {
2022 rctx->vs_shader = NULL;
2023 }
2024
2025 si_delete_shader_selector(ctx, sel);
2026 }
2027
2028 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2029 {
2030 struct r600_context *rctx = (struct r600_context *)ctx;
2031 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2032
2033 if (rctx->ps_shader == sel) {
2034 rctx->ps_shader = NULL;
2035 }
2036
2037 si_delete_shader_selector(ctx, sel);
2038 }
2039
2040 /*
2041 * Samplers
2042 */
2043
2044 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2045 struct pipe_resource *texture,
2046 const struct pipe_sampler_view *state)
2047 {
2048 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2049 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2050 const struct util_format_description *desc;
2051 unsigned format, num_format;
2052 uint32_t pitch = 0;
2053 unsigned char state_swizzle[4], swizzle[4];
2054 unsigned height, depth, width;
2055 enum pipe_format pipe_format = state->format;
2056 int first_non_void;
2057 uint64_t va;
2058
2059 if (view == NULL)
2060 return NULL;
2061
2062 /* initialize base object */
2063 view->base = *state;
2064 view->base.texture = NULL;
2065 pipe_reference(NULL, &texture->reference);
2066 view->base.texture = texture;
2067 view->base.reference.count = 1;
2068 view->base.context = ctx;
2069
2070 state_swizzle[0] = state->swizzle_r;
2071 state_swizzle[1] = state->swizzle_g;
2072 state_swizzle[2] = state->swizzle_b;
2073 state_swizzle[3] = state->swizzle_a;
2074
2075 /* Texturing with separate depth and stencil. */
2076 if (tmp->is_depth && !tmp->is_flushing_texture) {
2077 switch (pipe_format) {
2078 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2079 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2080 break;
2081 case PIPE_FORMAT_X24S8_UINT:
2082 case PIPE_FORMAT_S8X24_UINT:
2083 case PIPE_FORMAT_X32_S8X24_UINT:
2084 pipe_format = PIPE_FORMAT_S8_UINT;
2085 break;
2086 default:;
2087 }
2088 }
2089
2090 desc = util_format_description(pipe_format);
2091 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2092
2093 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2094 if (first_non_void < 0) {
2095 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2096 } else switch (desc->channel[first_non_void].type) {
2097 case UTIL_FORMAT_TYPE_FLOAT:
2098 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2099 break;
2100 case UTIL_FORMAT_TYPE_SIGNED:
2101 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2102 break;
2103 case UTIL_FORMAT_TYPE_UNSIGNED:
2104 default:
2105 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2106 }
2107
2108 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2109 if (format == ~0) {
2110 format = 0;
2111 }
2112
2113 view->resource = &tmp->resource;
2114
2115 /* not supported any more */
2116 //endian = si_colorformat_endian_swap(format);
2117
2118 width = tmp->surface.level[0].npix_x;
2119 height = tmp->surface.level[0].npix_y;
2120 depth = tmp->surface.level[0].npix_z;
2121 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(pipe_format);
2122
2123 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2124 height = 1;
2125 depth = texture->array_size;
2126 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2127 depth = texture->array_size;
2128 }
2129
2130 va = r600_resource_va(ctx->screen, texture);
2131 va += tmp->surface.level[0].offset;
2132 view->state[0] = va >> 8;
2133 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2134 S_008F14_DATA_FORMAT(format) |
2135 S_008F14_NUM_FORMAT(num_format));
2136 view->state[2] = (S_008F18_WIDTH(width - 1) |
2137 S_008F18_HEIGHT(height - 1));
2138 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2139 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2140 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2141 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2142 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2143 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2144 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0)) |
2145 S_008F1C_POW2_PAD(texture->last_level > 0) |
2146 S_008F1C_TYPE(si_tex_dim(texture->target)));
2147 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2148 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2149 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2150 view->state[6] = 0;
2151 view->state[7] = 0;
2152
2153 return &view->base;
2154 }
2155
2156 static void si_sampler_view_destroy(struct pipe_context *ctx,
2157 struct pipe_sampler_view *state)
2158 {
2159 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2160
2161 pipe_resource_reference(&state->texture, NULL);
2162 FREE(resource);
2163 }
2164
2165 static void *si_create_sampler_state(struct pipe_context *ctx,
2166 const struct pipe_sampler_state *state)
2167 {
2168 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2169 union util_color uc;
2170 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2171 unsigned border_color_type;
2172
2173 if (rstate == NULL) {
2174 return NULL;
2175 }
2176
2177 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2178 switch (uc.ui) {
2179 case 0x000000FF:
2180 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2181 break;
2182 case 0x00000000:
2183 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2184 break;
2185 case 0xFFFFFFFF:
2186 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2187 break;
2188 default: /* Use border color pointer */
2189 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2190 }
2191
2192 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2193 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2194 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2195 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2196 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2197 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2198 aniso_flag_offset << 16 | /* XXX */
2199 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2200 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2201 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2202 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2203 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2204 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2205 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2206 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2207
2208 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2209 memcpy(rstate->border_color, state->border_color.f,
2210 sizeof(rstate->border_color));
2211 }
2212
2213 return rstate;
2214 }
2215
2216 static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
2217 unsigned count,
2218 struct pipe_sampler_view **views,
2219 struct r600_textures_info *samplers,
2220 unsigned user_data_reg)
2221 {
2222 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2223 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2224 int i, j;
2225
2226 if (!count)
2227 goto out;
2228
2229 si_pm4_inval_texture_cache(pm4);
2230
2231 si_pm4_sh_data_begin(pm4);
2232 for (i = 0; i < count; i++) {
2233 pipe_sampler_view_reference(
2234 (struct pipe_sampler_view **)&samplers->views[i],
2235 views[i]);
2236
2237 if (views[i]) {
2238 struct r600_resource_texture *rtex =
2239 (struct r600_resource_texture*)views[i]->texture;
2240
2241 if (rtex->is_depth && !rtex->is_flushing_texture) {
2242 samplers->depth_texture_mask |= 1 << i;
2243 } else {
2244 samplers->depth_texture_mask &= ~(1 << i);
2245 }
2246
2247 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
2248 } else {
2249 samplers->depth_texture_mask &= ~(1 << i);
2250 }
2251
2252 for (j = 0; j < Elements(resource[i]->state); ++j) {
2253 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2254 }
2255 }
2256
2257 for (i = count; i < NUM_TEX_UNITS; i++) {
2258 if (samplers->views[i])
2259 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
2260 }
2261
2262 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
2263
2264 out:
2265 rctx->ps_samplers.n_views = count;
2266 return pm4;
2267 }
2268
2269 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2270 struct pipe_sampler_view **views)
2271 {
2272 struct r600_context *rctx = (struct r600_context *)ctx;
2273 struct si_pm4_state *pm4;
2274
2275 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
2276 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2277 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2278 }
2279
2280 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2281 struct pipe_sampler_view **views)
2282 {
2283 struct r600_context *rctx = (struct r600_context *)ctx;
2284 struct si_pm4_state *pm4;
2285
2286 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
2287 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2288 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2289 }
2290
2291 static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
2292 void **states,
2293 struct r600_textures_info *samplers,
2294 unsigned user_data_reg)
2295 {
2296 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2297 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2298 uint32_t *border_color_table = NULL;
2299 int i, j;
2300
2301 if (!count)
2302 goto out;
2303
2304 si_pm4_inval_texture_cache(pm4);
2305
2306 si_pm4_sh_data_begin(pm4);
2307 for (i = 0; i < count; i++) {
2308 if (rstates[i] &&
2309 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2310 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2311 if (!rctx->border_color_table ||
2312 ((rctx->border_color_offset + count - i) &
2313 C_008F3C_BORDER_COLOR_PTR)) {
2314 si_resource_reference(&rctx->border_color_table, NULL);
2315 rctx->border_color_offset = 0;
2316
2317 rctx->border_color_table =
2318 si_resource_create_custom(&rctx->screen->screen,
2319 PIPE_USAGE_STAGING,
2320 4096 * 4 * 4);
2321 }
2322
2323 if (!border_color_table) {
2324 border_color_table =
2325 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2326 rctx->cs,
2327 PIPE_TRANSFER_WRITE |
2328 PIPE_TRANSFER_UNSYNCHRONIZED);
2329 }
2330
2331 for (j = 0; j < 4; j++) {
2332 union fi border_color;
2333
2334 border_color.f = rstates[i]->border_color[j];
2335 border_color_table[4 * rctx->border_color_offset + j] =
2336 util_le32_to_cpu(border_color.i);
2337 }
2338
2339 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2340 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2341 }
2342
2343 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2344 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2345 }
2346 }
2347 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2348
2349 if (border_color_table) {
2350 uint64_t va_offset =
2351 r600_resource_va(&rctx->screen->screen,
2352 (void*)rctx->border_color_table);
2353
2354 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2355 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2356 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2357 }
2358
2359 memcpy(samplers->samplers, states, sizeof(void*) * count);
2360
2361 out:
2362 samplers->n_samplers = count;
2363 return pm4;
2364 }
2365
2366 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2367 {
2368 struct r600_context *rctx = (struct r600_context *)ctx;
2369 struct si_pm4_state *pm4;
2370
2371 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
2372 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2373 si_pm4_set_state(rctx, vs_sampler, pm4);
2374 }
2375
2376 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2377 {
2378 struct r600_context *rctx = (struct r600_context *)ctx;
2379 struct si_pm4_state *pm4;
2380
2381 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
2382 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2383 si_pm4_set_state(rctx, ps_sampler, pm4);
2384 }
2385
2386 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2387 {
2388 }
2389
2390 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2391 {
2392 free(state);
2393 }
2394
2395 /*
2396 * Constants
2397 */
2398 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2399 struct pipe_constant_buffer *cb)
2400 {
2401 struct r600_context *rctx = (struct r600_context *)ctx;
2402 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2403 struct si_pm4_state *pm4;
2404 uint64_t va_offset;
2405 uint32_t reg, offset;
2406
2407 /* Note that the state tracker can unbind constant buffers by
2408 * passing NULL here.
2409 */
2410 if (cb == NULL)
2411 return;
2412
2413 pm4 = CALLOC_STRUCT(si_pm4_state);
2414 si_pm4_inval_shader_cache(pm4);
2415
2416 if (cb->user_buffer)
2417 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2418 else
2419 offset = 0;
2420 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2421 va_offset += offset;
2422
2423 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2424
2425 switch (shader) {
2426 case PIPE_SHADER_VERTEX:
2427 reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
2428 si_pm4_set_reg(pm4, reg, va_offset);
2429 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2430 si_pm4_set_state(rctx, vs_const, pm4);
2431 break;
2432
2433 case PIPE_SHADER_FRAGMENT:
2434 reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
2435 si_pm4_set_reg(pm4, reg, va_offset);
2436 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2437 si_pm4_set_state(rctx, ps_const, pm4);
2438 break;
2439
2440 default:
2441 R600_ERR("unsupported %d\n", shader);
2442 }
2443
2444 if (cb->buffer != &rbuffer->b.b)
2445 si_resource_reference(&rbuffer, NULL);
2446 }
2447
2448 /*
2449 * Vertex elements & buffers
2450 */
2451
2452 static void *si_create_vertex_elements(struct pipe_context *ctx,
2453 unsigned count,
2454 const struct pipe_vertex_element *elements)
2455 {
2456 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2457 int i;
2458
2459 assert(count < PIPE_MAX_ATTRIBS);
2460 if (!v)
2461 return NULL;
2462
2463 v->count = count;
2464 for (i = 0; i < count; ++i) {
2465 const struct util_format_description *desc;
2466 unsigned data_format, num_format;
2467 int first_non_void;
2468
2469 desc = util_format_description(elements[i].src_format);
2470 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2471 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2472 desc, first_non_void);
2473
2474 switch (desc->channel[first_non_void].type) {
2475 case UTIL_FORMAT_TYPE_FIXED:
2476 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2477 break;
2478 case UTIL_FORMAT_TYPE_SIGNED:
2479 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2480 break;
2481 case UTIL_FORMAT_TYPE_UNSIGNED:
2482 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2483 break;
2484 case UTIL_FORMAT_TYPE_FLOAT:
2485 default:
2486 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2487 }
2488
2489 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2490 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2491 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2492 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2493 S_008F0C_NUM_FORMAT(num_format) |
2494 S_008F0C_DATA_FORMAT(data_format);
2495 }
2496 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2497
2498 return v;
2499 }
2500
2501 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2502 {
2503 struct r600_context *rctx = (struct r600_context *)ctx;
2504 struct si_vertex_element *v = (struct si_vertex_element*)state;
2505
2506 rctx->vertex_elements = v;
2507 }
2508
2509 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2510 {
2511 struct r600_context *rctx = (struct r600_context *)ctx;
2512
2513 if (rctx->vertex_elements == state)
2514 rctx->vertex_elements = NULL;
2515 FREE(state);
2516 }
2517
2518 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2519 const struct pipe_vertex_buffer *buffers)
2520 {
2521 struct r600_context *rctx = (struct r600_context *)ctx;
2522
2523 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2524 }
2525
2526 static void si_set_index_buffer(struct pipe_context *ctx,
2527 const struct pipe_index_buffer *ib)
2528 {
2529 struct r600_context *rctx = (struct r600_context *)ctx;
2530
2531 if (ib) {
2532 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2533 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2534 } else {
2535 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2536 }
2537 }
2538
2539 /*
2540 * Misc
2541 */
2542 static void si_set_polygon_stipple(struct pipe_context *ctx,
2543 const struct pipe_poly_stipple *state)
2544 {
2545 }
2546
2547 static void si_texture_barrier(struct pipe_context *ctx)
2548 {
2549 struct r600_context *rctx = (struct r600_context *)ctx;
2550 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2551
2552 si_pm4_inval_texture_cache(pm4);
2553 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2554 si_pm4_set_state(rctx, texture_barrier, pm4);
2555 }
2556
2557 void si_init_state_functions(struct r600_context *rctx)
2558 {
2559 rctx->context.create_blend_state = si_create_blend_state;
2560 rctx->context.bind_blend_state = si_bind_blend_state;
2561 rctx->context.delete_blend_state = si_delete_blend_state;
2562 rctx->context.set_blend_color = si_set_blend_color;
2563
2564 rctx->context.create_rasterizer_state = si_create_rs_state;
2565 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2566 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2567
2568 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2569 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2570 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2571 rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
2572 rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
2573 rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
2574 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
2575
2576 rctx->context.set_clip_state = si_set_clip_state;
2577 rctx->context.set_scissor_state = si_set_scissor_state;
2578 rctx->context.set_viewport_state = si_set_viewport_state;
2579 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2580
2581 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2582
2583 rctx->context.create_vs_state = si_create_vs_state;
2584 rctx->context.create_fs_state = si_create_fs_state;
2585 rctx->context.bind_vs_state = si_bind_vs_shader;
2586 rctx->context.bind_fs_state = si_bind_ps_shader;
2587 rctx->context.delete_vs_state = si_delete_vs_shader;
2588 rctx->context.delete_fs_state = si_delete_ps_shader;
2589
2590 rctx->context.create_sampler_state = si_create_sampler_state;
2591 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2592 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2593 rctx->context.delete_sampler_state = si_delete_sampler_state;
2594
2595 rctx->context.create_sampler_view = si_create_sampler_view;
2596 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2597 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2598 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2599
2600 rctx->context.set_sample_mask = si_set_sample_mask;
2601
2602 rctx->context.set_constant_buffer = si_set_constant_buffer;
2603
2604 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2605 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2606 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2607 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2608 rctx->context.set_index_buffer = si_set_index_buffer;
2609
2610 rctx->context.create_stream_output_target = si_create_so_target;
2611 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2612 rctx->context.set_stream_output_targets = si_set_so_targets;
2613
2614 rctx->context.texture_barrier = si_texture_barrier;
2615 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2616
2617 rctx->context.draw_vbo = si_draw_vbo;
2618 }
2619
2620 void si_init_config(struct r600_context *rctx)
2621 {
2622 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2623
2624 si_cmd_context_control(pm4);
2625
2626 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2627
2628 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2629 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2630 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2631 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2632 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2633 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2634 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2635 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2636 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2637 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2638 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2639 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2640 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2641 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2642 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2643 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2644 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2645 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2646 S_028AA8_SWITCH_ON_EOP(1) |
2647 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2648 S_028AA8_PRIMGROUP_SIZE(63));
2649 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2650 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2651 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2652 S_008A14_CLIP_VTX_REORDER_ENA(1));
2653
2654 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2655 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2656 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2657
2658 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2659
2660 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2661
2662 switch (rctx->screen->family) {
2663 case CHIP_TAHITI:
2664 case CHIP_PITCAIRN:
2665 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
2666 break;
2667 case CHIP_VERDE:
2668 default:
2669 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
2670 break;
2671 }
2672
2673 si_pm4_set_state(rctx, init, pm4);
2674 }