projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: use si_context instead of pipe_context in parameters pt2
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_pipe.h"
26 #include "sid.h"
27 #include "gfx9d.h"
28 #include "radeon/r600_cs.h"
29 #include "radeon/r600_query.h"
30
31 #include "util/u_dual_blend.h"
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_resource.h"
36 #include "util/u_upload_mgr.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = emit_func;
53 atom->id = list_elem - sctx->atoms.array;
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 /* 12.4 fixed-point */
76 static unsigned si_pack_float_12p4(float x)
77 {
78 return x <= 0 ? 0 :
79 x >= 4096 ? 0xffff : x * 16;
80 }
81
82 /*
83 * Inferred framebuffer and blender state.
84 *
85 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
86 * if there is not enough PS outputs.
87 */
88 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
89 {
90 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
91 struct si_state_blend *blend = sctx->queued.named.blend;
92 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
93 * but you never know. */
94 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
95 unsigned i;
96
97 if (blend)
98 cb_target_mask &= blend->cb_target_mask;
99
100 /* Avoid a hang that happens when dual source blending is enabled
101 * but there is not enough color outputs. This is undefined behavior,
102 * so disable color writes completely.
103 *
104 * Reproducible with Unigine Heaven 4.0 and drirc missing.
105 */
106 if (blend && blend->dual_src_blend &&
107 sctx->ps_shader.cso &&
108 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
109 cb_target_mask = 0;
110
111 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
112
113 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
114 * I think we don't have to do anything between IBs.
115 */
116 if (sctx->screen->dfsm_allowed &&
117 sctx->last_cb_target_mask != cb_target_mask) {
118 sctx->last_cb_target_mask = cb_target_mask;
119
120 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
121 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
122 }
123
124 if (sctx->b.chip_class >= VI) {
125 /* DCC MSAA workaround for blending.
126 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
127 * COMBINER_DISABLE, but that would be more complicated.
128 */
129 bool oc_disable = (sctx->b.chip_class == VI ||
130 sctx->b.chip_class == GFX9) &&
131 blend &&
132 blend->blend_enable_4bit & cb_target_mask &&
133 sctx->framebuffer.nr_samples >= 2;
134
135 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
136 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
137 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
138 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
139 }
140
141 /* RB+ register settings. */
142 if (sctx->screen->rbplus_allowed) {
143 unsigned spi_shader_col_format =
144 sctx->ps_shader.cso ?
145 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
146 unsigned sx_ps_downconvert = 0;
147 unsigned sx_blend_opt_epsilon = 0;
148 unsigned sx_blend_opt_control = 0;
149
150 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
151 struct r600_surface *surf =
152 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
153 unsigned format, swap, spi_format, colormask;
154 bool has_alpha, has_rgb;
155
156 if (!surf)
157 continue;
158
159 format = G_028C70_FORMAT(surf->cb_color_info);
160 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
161 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
162 colormask = (cb_target_mask >> (i * 4)) & 0xf;
163
164 /* Set if RGB and A are present. */
165 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
166
167 if (format == V_028C70_COLOR_8 ||
168 format == V_028C70_COLOR_16 ||
169 format == V_028C70_COLOR_32)
170 has_rgb = !has_alpha;
171 else
172 has_rgb = true;
173
174 /* Check the colormask and export format. */
175 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
176 has_rgb = false;
177 if (!(colormask & PIPE_MASK_A))
178 has_alpha = false;
179
180 if (spi_format == V_028714_SPI_SHADER_ZERO) {
181 has_rgb = false;
182 has_alpha = false;
183 }
184
185 /* Disable value checking for disabled channels. */
186 if (!has_rgb)
187 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
188 if (!has_alpha)
189 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
190
191 /* Enable down-conversion for 32bpp and smaller formats. */
192 switch (format) {
193 case V_028C70_COLOR_8:
194 case V_028C70_COLOR_8_8:
195 case V_028C70_COLOR_8_8_8_8:
196 /* For 1 and 2-channel formats, use the superset thereof. */
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
199 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_5_6_5:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_1_5_5_5:
213 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
215 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
216 }
217 break;
218
219 case V_028C70_COLOR_4_4_4_4:
220 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
222 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
223 }
224 break;
225
226 case V_028C70_COLOR_32:
227 if (swap == V_028C70_SWAP_STD &&
228 spi_format == V_028714_SPI_SHADER_32_R)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
230 else if (swap == V_028C70_SWAP_ALT_REV &&
231 spi_format == V_028714_SPI_SHADER_32_AR)
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
233 break;
234
235 case V_028C70_COLOR_16:
236 case V_028C70_COLOR_16_16:
237 /* For 1-channel formats, use the superset thereof. */
238 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
241 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
242 if (swap == V_028C70_SWAP_STD ||
243 swap == V_028C70_SWAP_STD_REV)
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
245 else
246 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
247 }
248 break;
249
250 case V_028C70_COLOR_10_11_11:
251 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
252 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
253 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
254 }
255 break;
256
257 case V_028C70_COLOR_2_10_10_10:
258 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
259 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
260 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
261 }
262 break;
263 }
264 }
265
266 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
267 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
268 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
269 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
270 } else if (sctx->screen->has_rbplus) {
271 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
272 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
273 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
274 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
275 }
276 }
277
278 /*
279 * Blender functions
280 */
281
282 static uint32_t si_translate_blend_function(int blend_func)
283 {
284 switch (blend_func) {
285 case PIPE_BLEND_ADD:
286 return V_028780_COMB_DST_PLUS_SRC;
287 case PIPE_BLEND_SUBTRACT:
288 return V_028780_COMB_SRC_MINUS_DST;
289 case PIPE_BLEND_REVERSE_SUBTRACT:
290 return V_028780_COMB_DST_MINUS_SRC;
291 case PIPE_BLEND_MIN:
292 return V_028780_COMB_MIN_DST_SRC;
293 case PIPE_BLEND_MAX:
294 return V_028780_COMB_MAX_DST_SRC;
295 default:
296 R600_ERR("Unknown blend function %d\n", blend_func);
297 assert(0);
298 break;
299 }
300 return 0;
301 }
302
303 static uint32_t si_translate_blend_factor(int blend_fact)
304 {
305 switch (blend_fact) {
306 case PIPE_BLENDFACTOR_ONE:
307 return V_028780_BLEND_ONE;
308 case PIPE_BLENDFACTOR_SRC_COLOR:
309 return V_028780_BLEND_SRC_COLOR;
310 case PIPE_BLENDFACTOR_SRC_ALPHA:
311 return V_028780_BLEND_SRC_ALPHA;
312 case PIPE_BLENDFACTOR_DST_ALPHA:
313 return V_028780_BLEND_DST_ALPHA;
314 case PIPE_BLENDFACTOR_DST_COLOR:
315 return V_028780_BLEND_DST_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
317 return V_028780_BLEND_SRC_ALPHA_SATURATE;
318 case PIPE_BLENDFACTOR_CONST_COLOR:
319 return V_028780_BLEND_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_CONST_ALPHA:
321 return V_028780_BLEND_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_ZERO:
323 return V_028780_BLEND_ZERO;
324 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
325 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
326 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
329 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
330 case PIPE_BLENDFACTOR_INV_DST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
334 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
336 case PIPE_BLENDFACTOR_SRC1_COLOR:
337 return V_028780_BLEND_SRC1_COLOR;
338 case PIPE_BLENDFACTOR_SRC1_ALPHA:
339 return V_028780_BLEND_SRC1_ALPHA;
340 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
341 return V_028780_BLEND_INV_SRC1_COLOR;
342 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
343 return V_028780_BLEND_INV_SRC1_ALPHA;
344 default:
345 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
346 assert(0);
347 break;
348 }
349 return 0;
350 }
351
352 static uint32_t si_translate_blend_opt_function(int blend_func)
353 {
354 switch (blend_func) {
355 case PIPE_BLEND_ADD:
356 return V_028760_OPT_COMB_ADD;
357 case PIPE_BLEND_SUBTRACT:
358 return V_028760_OPT_COMB_SUBTRACT;
359 case PIPE_BLEND_REVERSE_SUBTRACT:
360 return V_028760_OPT_COMB_REVSUBTRACT;
361 case PIPE_BLEND_MIN:
362 return V_028760_OPT_COMB_MIN;
363 case PIPE_BLEND_MAX:
364 return V_028760_OPT_COMB_MAX;
365 default:
366 return V_028760_OPT_COMB_BLEND_DISABLED;
367 }
368 }
369
370 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
371 {
372 switch (blend_fact) {
373 case PIPE_BLENDFACTOR_ZERO:
374 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
375 case PIPE_BLENDFACTOR_ONE:
376 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
377 case PIPE_BLENDFACTOR_SRC_COLOR:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
379 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
380 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
381 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
382 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
383 case PIPE_BLENDFACTOR_SRC_ALPHA:
384 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
385 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
386 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
387 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
388 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
389 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
390 default:
391 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
392 }
393 }
394
395 static void si_blend_check_commutativity(struct si_screen *sscreen,
396 struct si_state_blend *blend,
397 enum pipe_blend_func func,
398 enum pipe_blendfactor src,
399 enum pipe_blendfactor dst,
400 unsigned chanmask)
401 {
402 /* Src factor is allowed when it does not depend on Dst */
403 static const uint32_t src_allowed =
404 (1u << PIPE_BLENDFACTOR_ONE) |
405 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
406 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
407 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
408 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
409 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
410 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
411 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
412 (1u << PIPE_BLENDFACTOR_ZERO) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
414 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
415 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
416 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
419
420 if (dst == PIPE_BLENDFACTOR_ONE &&
421 (src_allowed & (1u << src))) {
422 /* Addition is commutative, but floating point addition isn't
423 * associative: subtle changes can be introduced via different
424 * rounding.
425 *
426 * Out-of-order is also non-deterministic, which means that
427 * this breaks OpenGL invariance requirements. So only enable
428 * out-of-order additive blending if explicitly allowed by a
429 * setting.
430 */
431 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
432 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
433 blend->commutative_4bit |= chanmask;
434 }
435 }
436
437 /**
438 * Get rid of DST in the blend factors by commuting the operands:
439 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
440 */
441 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
442 unsigned *dst_factor, unsigned expected_dst,
443 unsigned replacement_src)
444 {
445 if (*src_factor == expected_dst &&
446 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
447 *src_factor = PIPE_BLENDFACTOR_ZERO;
448 *dst_factor = replacement_src;
449
450 /* Commuting the operands requires reversing subtractions. */
451 if (*func == PIPE_BLEND_SUBTRACT)
452 *func = PIPE_BLEND_REVERSE_SUBTRACT;
453 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
454 *func = PIPE_BLEND_SUBTRACT;
455 }
456 }
457
458 static bool si_blend_factor_uses_dst(unsigned factor)
459 {
460 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
461 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
462 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
463 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
464 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
465 }
466
467 static void *si_create_blend_state_mode(struct pipe_context *ctx,
468 const struct pipe_blend_state *state,
469 unsigned mode)
470 {
471 struct si_context *sctx = (struct si_context*)ctx;
472 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
473 struct si_pm4_state *pm4 = &blend->pm4;
474 uint32_t sx_mrt_blend_opt[8] = {0};
475 uint32_t color_control = 0;
476
477 if (!blend)
478 return NULL;
479
480 blend->alpha_to_coverage = state->alpha_to_coverage;
481 blend->alpha_to_one = state->alpha_to_one;
482 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
483 blend->logicop_enable = state->logicop_enable;
484
485 if (state->logicop_enable) {
486 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
487 } else {
488 color_control |= S_028808_ROP3(0xcc);
489 }
490
491 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
492 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
493 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
495 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
496 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
497
498 if (state->alpha_to_coverage)
499 blend->need_src_alpha_4bit |= 0xf;
500
501 blend->cb_target_mask = 0;
502 blend->cb_target_enabled_4bit = 0;
503
504 for (int i = 0; i < 8; i++) {
505 /* state->rt entries > 0 only written if independent blending */
506 const int j = state->independent_blend_enable ? i : 0;
507
508 unsigned eqRGB = state->rt[j].rgb_func;
509 unsigned srcRGB = state->rt[j].rgb_src_factor;
510 unsigned dstRGB = state->rt[j].rgb_dst_factor;
511 unsigned eqA = state->rt[j].alpha_func;
512 unsigned srcA = state->rt[j].alpha_src_factor;
513 unsigned dstA = state->rt[j].alpha_dst_factor;
514
515 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
516 unsigned blend_cntl = 0;
517
518 sx_mrt_blend_opt[i] =
519 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
520 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
521
522 /* Only set dual source blending for MRT0 to avoid a hang. */
523 if (i >= 1 && blend->dual_src_blend) {
524 /* Vulkan does this for dual source blending. */
525 if (i == 1)
526 blend_cntl |= S_028780_ENABLE(1);
527
528 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
529 continue;
530 }
531
532 /* Only addition and subtraction equations are supported with
533 * dual source blending.
534 */
535 if (blend->dual_src_blend &&
536 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
537 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
538 assert(!"Unsupported equation for dual source blending");
539 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
540 continue;
541 }
542
543 /* cb_render_state will disable unused ones */
544 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
545 if (state->rt[j].colormask)
546 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
547
548 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
549 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
550 continue;
551 }
552
553 si_blend_check_commutativity(sctx->screen, blend,
554 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
555 si_blend_check_commutativity(sctx->screen, blend,
556 eqA, srcA, dstA, 0x8 << (4 * i));
557
558 /* Blending optimizations for RB+.
559 * These transformations don't change the behavior.
560 *
561 * First, get rid of DST in the blend factors:
562 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
563 */
564 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
565 PIPE_BLENDFACTOR_DST_COLOR,
566 PIPE_BLENDFACTOR_SRC_COLOR);
567 si_blend_remove_dst(&eqA, &srcA, &dstA,
568 PIPE_BLENDFACTOR_DST_COLOR,
569 PIPE_BLENDFACTOR_SRC_COLOR);
570 si_blend_remove_dst(&eqA, &srcA, &dstA,
571 PIPE_BLENDFACTOR_DST_ALPHA,
572 PIPE_BLENDFACTOR_SRC_ALPHA);
573
574 /* Look up the ideal settings from tables. */
575 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
576 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
577 srcA_opt = si_translate_blend_opt_factor(srcA, true);
578 dstA_opt = si_translate_blend_opt_factor(dstA, true);
579
580 /* Handle interdependencies. */
581 if (si_blend_factor_uses_dst(srcRGB))
582 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
583 if (si_blend_factor_uses_dst(srcA))
584 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
585
586 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
587 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
588 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
589 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
590 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
591
592 /* Set the final value. */
593 sx_mrt_blend_opt[i] =
594 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
595 S_028760_COLOR_DST_OPT(dstRGB_opt) |
596 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
597 S_028760_ALPHA_SRC_OPT(srcA_opt) |
598 S_028760_ALPHA_DST_OPT(dstA_opt) |
599 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
600
601 /* Set blend state. */
602 blend_cntl |= S_028780_ENABLE(1);
603 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
604 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
605 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
606
607 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
608 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
609 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
610 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
611 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
612 }
613 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
614
615 blend->blend_enable_4bit |= 0xfu << (i * 4);
616
617 /* This is only important for formats without alpha. */
618 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
619 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
620 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
621 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
622 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
623 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
624 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
625 }
626
627 if (blend->cb_target_mask) {
628 color_control |= S_028808_MODE(mode);
629 } else {
630 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
631 }
632
633 if (sctx->screen->has_rbplus) {
634 /* Disable RB+ blend optimizations for dual source blending.
635 * Vulkan does this.
636 */
637 if (blend->dual_src_blend) {
638 for (int i = 0; i < 8; i++) {
639 sx_mrt_blend_opt[i] =
640 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
641 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
642 }
643 }
644
645 for (int i = 0; i < 8; i++)
646 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
647 sx_mrt_blend_opt[i]);
648
649 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
650 if (blend->dual_src_blend || state->logicop_enable ||
651 mode == V_028808_CB_RESOLVE)
652 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
653 }
654
655 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
656 return blend;
657 }
658
659 static void *si_create_blend_state(struct pipe_context *ctx,
660 const struct pipe_blend_state *state)
661 {
662 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
663 }
664
665 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 struct si_state_blend *old_blend = sctx->queued.named.blend;
669 struct si_state_blend *blend = (struct si_state_blend *)state;
670
671 if (!state)
672 return;
673
674 si_pm4_bind_state(sctx, blend, state);
675
676 if (!old_blend ||
677 old_blend->cb_target_mask != blend->cb_target_mask ||
678 old_blend->dual_src_blend != blend->dual_src_blend ||
679 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
680 sctx->framebuffer.nr_samples >= 2 &&
681 sctx->screen->dcc_msaa_allowed))
682 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
683
684 if (!old_blend ||
685 old_blend->cb_target_mask != blend->cb_target_mask ||
686 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
687 old_blend->alpha_to_one != blend->alpha_to_one ||
688 old_blend->dual_src_blend != blend->dual_src_blend ||
689 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
690 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
691 sctx->do_update_shaders = true;
692
693 if (sctx->screen->dpbb_allowed &&
694 (!old_blend ||
695 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
696 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
697 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
698 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
699
700 if (sctx->screen->has_out_of_order_rast &&
701 (!old_blend ||
702 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
703 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
704 old_blend->commutative_4bit != blend->commutative_4bit ||
705 old_blend->logicop_enable != blend->logicop_enable)))
706 si_mark_atom_dirty(sctx, &sctx->msaa_config);
707 }
708
709 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
710 {
711 struct si_context *sctx = (struct si_context *)ctx;
712 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
713 }
714
715 static void si_set_blend_color(struct pipe_context *ctx,
716 const struct pipe_blend_color *state)
717 {
718 struct si_context *sctx = (struct si_context *)ctx;
719 static const struct pipe_blend_color zeros;
720
721 sctx->blend_color.state = *state;
722 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
723 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
724 }
725
726 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
727 {
728 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
729
730 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
731 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
732 }
733
734 /*
735 * Clipping
736 */
737
738 static void si_set_clip_state(struct pipe_context *ctx,
739 const struct pipe_clip_state *state)
740 {
741 struct si_context *sctx = (struct si_context *)ctx;
742 struct pipe_constant_buffer cb;
743 static const struct pipe_clip_state zeros;
744
745 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
746 return;
747
748 sctx->clip_state.state = *state;
749 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
750 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
751
752 cb.buffer = NULL;
753 cb.user_buffer = state->ucp;
754 cb.buffer_offset = 0;
755 cb.buffer_size = 4*4*8;
756 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
757 pipe_resource_reference(&cb.buffer, NULL);
758 }
759
760 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
761 {
762 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
763
764 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
765 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
766 }
767
768 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
769 {
770 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
771 struct si_shader *vs = si_get_vs_state(sctx);
772 struct si_shader_selector *vs_sel = vs->selector;
773 struct tgsi_shader_info *info = &vs_sel->info;
774 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
775 unsigned window_space =
776 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
777 unsigned clipdist_mask = vs_sel->clipdist_mask;
778 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
779 unsigned culldist_mask = vs_sel->culldist_mask;
780 unsigned total_mask;
781
782 if (vs->key.opt.clip_disable) {
783 assert(!info->culldist_writemask);
784 clipdist_mask = 0;
785 culldist_mask = 0;
786 }
787 total_mask = clipdist_mask | culldist_mask;
788
789 /* Clip distances on points have no effect, so need to be implemented
790 * as cull distances. This applies for the clipvertex case as well.
791 *
792 * Setting this for primitives other than points should have no adverse
793 * effects.
794 */
795 clipdist_mask &= rs->clip_plane_enable;
796 culldist_mask |= clipdist_mask;
797
798 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
799 vs_sel->pa_cl_vs_out_cntl |
800 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
801 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
802 clipdist_mask | (culldist_mask << 8));
803 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
804 rs->pa_cl_clip_cntl |
805 ucp_mask |
806 S_028810_CLIP_DISABLE(window_space));
807 }
808
809 /*
810 * inferred state between framebuffer and rasterizer
811 */
812 static void si_update_poly_offset_state(struct si_context *sctx)
813 {
814 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
815
816 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
817 si_pm4_bind_state(sctx, poly_offset, NULL);
818 return;
819 }
820
821 /* Use the user format, not db_render_format, so that the polygon
822 * offset behaves as expected by applications.
823 */
824 switch (sctx->framebuffer.state.zsbuf->texture->format) {
825 case PIPE_FORMAT_Z16_UNORM:
826 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
827 break;
828 default: /* 24-bit */
829 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
830 break;
831 case PIPE_FORMAT_Z32_FLOAT:
832 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
833 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
834 break;
835 }
836 }
837
838 /*
839 * Rasterizer
840 */
841
842 static uint32_t si_translate_fill(uint32_t func)
843 {
844 switch(func) {
845 case PIPE_POLYGON_MODE_FILL:
846 return V_028814_X_DRAW_TRIANGLES;
847 case PIPE_POLYGON_MODE_LINE:
848 return V_028814_X_DRAW_LINES;
849 case PIPE_POLYGON_MODE_POINT:
850 return V_028814_X_DRAW_POINTS;
851 default:
852 assert(0);
853 return V_028814_X_DRAW_POINTS;
854 }
855 }
856
857 static void *si_create_rs_state(struct pipe_context *ctx,
858 const struct pipe_rasterizer_state *state)
859 {
860 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
861 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
862 struct si_pm4_state *pm4 = &rs->pm4;
863 unsigned tmp, i;
864 float psize_min, psize_max;
865
866 if (!rs) {
867 return NULL;
868 }
869
870 rs->scissor_enable = state->scissor;
871 rs->clip_halfz = state->clip_halfz;
872 rs->two_side = state->light_twoside;
873 rs->multisample_enable = state->multisample;
874 rs->force_persample_interp = state->force_persample_interp;
875 rs->clip_plane_enable = state->clip_plane_enable;
876 rs->line_stipple_enable = state->line_stipple_enable;
877 rs->poly_stipple_enable = state->poly_stipple_enable;
878 rs->line_smooth = state->line_smooth;
879 rs->line_width = state->line_width;
880 rs->poly_smooth = state->poly_smooth;
881 rs->uses_poly_offset = state->offset_point || state->offset_line ||
882 state->offset_tri;
883 rs->clamp_fragment_color = state->clamp_fragment_color;
884 rs->clamp_vertex_color = state->clamp_vertex_color;
885 rs->flatshade = state->flatshade;
886 rs->sprite_coord_enable = state->sprite_coord_enable;
887 rs->rasterizer_discard = state->rasterizer_discard;
888 rs->pa_sc_line_stipple = state->line_stipple_enable ?
889 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
890 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
891 rs->pa_cl_clip_cntl =
892 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
893 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
894 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
895 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
896 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
897
898 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
899 S_0286D4_FLAT_SHADE_ENA(1) |
900 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
901 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
902 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
903 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
904 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
905 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
906
907 /* point size 12.4 fixed point */
908 tmp = (unsigned)(state->point_size * 8.0);
909 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
910
911 if (state->point_size_per_vertex) {
912 psize_min = util_get_min_point_size(state);
913 psize_max = 8192;
914 } else {
915 /* Force the point size to be as if the vertex output was disabled. */
916 psize_min = state->point_size;
917 psize_max = state->point_size;
918 }
919 rs->max_point_size = psize_max;
920
921 /* Divide by two, because 0.5 = 1 pixel. */
922 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
923 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
924 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
925
926 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
927 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
928 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
929 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
930 S_028A48_MSAA_ENABLE(state->multisample ||
931 state->poly_smooth ||
932 state->line_smooth) |
933 S_028A48_VPORT_SCISSOR_ENABLE(1) |
934 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
935
936 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
937 S_028BE4_PIX_CENTER(state->half_pixel_center) |
938 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
939
940 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
941 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
942 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
943 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
944 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
945 S_028814_FACE(!state->front_ccw) |
946 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
947 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
948 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
949 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
950 state->fill_back != PIPE_POLYGON_MODE_FILL) |
951 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
952 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
953
954 if (!rs->uses_poly_offset)
955 return rs;
956
957 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
958 if (!rs->pm4_poly_offset) {
959 FREE(rs);
960 return NULL;
961 }
962
963 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
964 for (i = 0; i < 3; i++) {
965 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
966 float offset_units = state->offset_units;
967 float offset_scale = state->offset_scale * 16.0f;
968 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
969
970 if (!state->offset_units_unscaled) {
971 switch (i) {
972 case 0: /* 16-bit zbuffer */
973 offset_units *= 4.0f;
974 pa_su_poly_offset_db_fmt_cntl =
975 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
976 break;
977 case 1: /* 24-bit zbuffer */
978 offset_units *= 2.0f;
979 pa_su_poly_offset_db_fmt_cntl =
980 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
981 break;
982 case 2: /* 32-bit zbuffer */
983 offset_units *= 1.0f;
984 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
985 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
986 break;
987 }
988 }
989
990 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
991 fui(offset_scale));
992 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
993 fui(offset_units));
994 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
995 fui(offset_scale));
996 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
997 fui(offset_units));
998 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
999 pa_su_poly_offset_db_fmt_cntl);
1000 }
1001
1002 return rs;
1003 }
1004
1005 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1006 {
1007 struct si_context *sctx = (struct si_context *)ctx;
1008 struct si_state_rasterizer *old_rs =
1009 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1010 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1011
1012 if (!state)
1013 return;
1014
1015 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1016 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1017
1018 /* Update the small primitive filter workaround if necessary. */
1019 if (sctx->screen->has_msaa_sample_loc_bug &&
1020 sctx->framebuffer.nr_samples > 1)
1021 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1022 }
1023
1024 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1025 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1026
1027 si_pm4_bind_state(sctx, rasterizer, rs);
1028 si_update_poly_offset_state(sctx);
1029
1030 if (!old_rs ||
1031 (old_rs->scissor_enable != rs->scissor_enable ||
1032 old_rs->line_width != rs->line_width ||
1033 old_rs->max_point_size != rs->max_point_size)) {
1034 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1035 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1036 }
1037
1038 if (!old_rs ||
1039 old_rs->clip_halfz != rs->clip_halfz) {
1040 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1041 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1042 }
1043
1044 if (!old_rs ||
1045 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1046 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1047 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1048
1049 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1050 rs->line_stipple_enable;
1051
1052 if (!old_rs ||
1053 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1054 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1055 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1056 old_rs->flatshade != rs->flatshade ||
1057 old_rs->two_side != rs->two_side ||
1058 old_rs->multisample_enable != rs->multisample_enable ||
1059 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1060 old_rs->poly_smooth != rs->poly_smooth ||
1061 old_rs->line_smooth != rs->line_smooth ||
1062 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1063 old_rs->force_persample_interp != rs->force_persample_interp)
1064 sctx->do_update_shaders = true;
1065 }
1066
1067 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1068 {
1069 struct si_context *sctx = (struct si_context *)ctx;
1070 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1071
1072 if (sctx->queued.named.rasterizer == state)
1073 si_pm4_bind_state(sctx, poly_offset, NULL);
1074
1075 FREE(rs->pm4_poly_offset);
1076 si_pm4_delete_state(sctx, rasterizer, rs);
1077 }
1078
1079 /*
1080 * infeered state between dsa and stencil ref
1081 */
1082 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1083 {
1084 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
1085 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1086 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1087
1088 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1089 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1090 S_028430_STENCILMASK(dsa->valuemask[0]) |
1091 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1092 S_028430_STENCILOPVAL(1));
1093 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1094 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1095 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1096 S_028434_STENCILOPVAL_BF(1));
1097 }
1098
1099 static void si_set_stencil_ref(struct pipe_context *ctx,
1100 const struct pipe_stencil_ref *state)
1101 {
1102 struct si_context *sctx = (struct si_context *)ctx;
1103
1104 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1105 return;
1106
1107 sctx->stencil_ref.state = *state;
1108 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1109 }
1110
1111
1112 /*
1113 * DSA
1114 */
1115
1116 static uint32_t si_translate_stencil_op(int s_op)
1117 {
1118 switch (s_op) {
1119 case PIPE_STENCIL_OP_KEEP:
1120 return V_02842C_STENCIL_KEEP;
1121 case PIPE_STENCIL_OP_ZERO:
1122 return V_02842C_STENCIL_ZERO;
1123 case PIPE_STENCIL_OP_REPLACE:
1124 return V_02842C_STENCIL_REPLACE_TEST;
1125 case PIPE_STENCIL_OP_INCR:
1126 return V_02842C_STENCIL_ADD_CLAMP;
1127 case PIPE_STENCIL_OP_DECR:
1128 return V_02842C_STENCIL_SUB_CLAMP;
1129 case PIPE_STENCIL_OP_INCR_WRAP:
1130 return V_02842C_STENCIL_ADD_WRAP;
1131 case PIPE_STENCIL_OP_DECR_WRAP:
1132 return V_02842C_STENCIL_SUB_WRAP;
1133 case PIPE_STENCIL_OP_INVERT:
1134 return V_02842C_STENCIL_INVERT;
1135 default:
1136 R600_ERR("Unknown stencil op %d", s_op);
1137 assert(0);
1138 break;
1139 }
1140 return 0;
1141 }
1142
1143 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1144 {
1145 return s->enabled && s->writemask &&
1146 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1147 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1148 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1149 }
1150
1151 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1152 {
1153 /* REPLACE is normally order invariant, except when the stencil
1154 * reference value is written by the fragment shader. Tracking this
1155 * interaction does not seem worth the effort, so be conservative. */
1156 return op != PIPE_STENCIL_OP_INCR &&
1157 op != PIPE_STENCIL_OP_DECR &&
1158 op != PIPE_STENCIL_OP_REPLACE;
1159 }
1160
1161 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1162 * invariant in the sense that the set of passing fragments as well as the
1163 * final stencil buffer result does not depend on the order of fragments. */
1164 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1165 {
1166 return !state->enabled || !state->writemask ||
1167 /* The following assumes that Z writes are disabled. */
1168 (state->func == PIPE_FUNC_ALWAYS &&
1169 si_order_invariant_stencil_op(state->zpass_op) &&
1170 si_order_invariant_stencil_op(state->zfail_op)) ||
1171 (state->func == PIPE_FUNC_NEVER &&
1172 si_order_invariant_stencil_op(state->fail_op));
1173 }
1174
1175 static void *si_create_dsa_state(struct pipe_context *ctx,
1176 const struct pipe_depth_stencil_alpha_state *state)
1177 {
1178 struct si_context *sctx = (struct si_context *)ctx;
1179 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1180 struct si_pm4_state *pm4 = &dsa->pm4;
1181 unsigned db_depth_control;
1182 uint32_t db_stencil_control = 0;
1183
1184 if (!dsa) {
1185 return NULL;
1186 }
1187
1188 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1189 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1190 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1191 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1192
1193 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1194 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1195 S_028800_ZFUNC(state->depth.func) |
1196 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1197
1198 /* stencil */
1199 if (state->stencil[0].enabled) {
1200 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1201 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1202 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1203 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1204 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1205
1206 if (state->stencil[1].enabled) {
1207 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1208 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1209 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1210 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1211 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1212 }
1213 }
1214
1215 /* alpha */
1216 if (state->alpha.enabled) {
1217 dsa->alpha_func = state->alpha.func;
1218
1219 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1220 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1221 } else {
1222 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1223 }
1224
1225 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1226 if (state->stencil[0].enabled)
1227 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1228 if (state->depth.bounds_test) {
1229 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1230 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1231 }
1232
1233 dsa->depth_enabled = state->depth.enabled;
1234 dsa->depth_write_enabled = state->depth.enabled &&
1235 state->depth.writemask;
1236 dsa->stencil_enabled = state->stencil[0].enabled;
1237 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1238 (si_dsa_writes_stencil(&state->stencil[0]) ||
1239 si_dsa_writes_stencil(&state->stencil[1]));
1240 dsa->db_can_write = dsa->depth_write_enabled ||
1241 dsa->stencil_write_enabled;
1242
1243 bool zfunc_is_ordered =
1244 state->depth.func == PIPE_FUNC_NEVER ||
1245 state->depth.func == PIPE_FUNC_LESS ||
1246 state->depth.func == PIPE_FUNC_LEQUAL ||
1247 state->depth.func == PIPE_FUNC_GREATER ||
1248 state->depth.func == PIPE_FUNC_GEQUAL;
1249
1250 bool nozwrite_and_order_invariant_stencil =
1251 !dsa->db_can_write ||
1252 (!dsa->depth_write_enabled &&
1253 si_order_invariant_stencil_state(&state->stencil[0]) &&
1254 si_order_invariant_stencil_state(&state->stencil[1]));
1255
1256 dsa->order_invariance[1].zs =
1257 nozwrite_and_order_invariant_stencil ||
1258 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1259 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1260
1261 dsa->order_invariance[1].pass_set =
1262 nozwrite_and_order_invariant_stencil ||
1263 (!dsa->stencil_write_enabled &&
1264 (state->depth.func == PIPE_FUNC_ALWAYS ||
1265 state->depth.func == PIPE_FUNC_NEVER));
1266 dsa->order_invariance[0].pass_set =
1267 !dsa->depth_write_enabled ||
1268 (state->depth.func == PIPE_FUNC_ALWAYS ||
1269 state->depth.func == PIPE_FUNC_NEVER);
1270
1271 dsa->order_invariance[1].pass_last =
1272 sctx->screen->assume_no_z_fights &&
1273 !dsa->stencil_write_enabled &&
1274 dsa->depth_write_enabled && zfunc_is_ordered;
1275 dsa->order_invariance[0].pass_last =
1276 sctx->screen->assume_no_z_fights &&
1277 dsa->depth_write_enabled && zfunc_is_ordered;
1278
1279 return dsa;
1280 }
1281
1282 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1283 {
1284 struct si_context *sctx = (struct si_context *)ctx;
1285 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1286 struct si_state_dsa *dsa = state;
1287
1288 if (!state)
1289 return;
1290
1291 si_pm4_bind_state(sctx, dsa, dsa);
1292
1293 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1294 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1295 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1296 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1297 }
1298
1299 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1300 sctx->do_update_shaders = true;
1301
1302 if (sctx->screen->dpbb_allowed &&
1303 (!old_dsa ||
1304 (old_dsa->depth_enabled != dsa->depth_enabled ||
1305 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1306 old_dsa->db_can_write != dsa->db_can_write)))
1307 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1308
1309 if (sctx->screen->has_out_of_order_rast &&
1310 (!old_dsa ||
1311 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1312 sizeof(old_dsa->order_invariance))))
1313 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1314 }
1315
1316 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1317 {
1318 struct si_context *sctx = (struct si_context *)ctx;
1319 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1320 }
1321
1322 static void *si_create_db_flush_dsa(struct si_context *sctx)
1323 {
1324 struct pipe_depth_stencil_alpha_state dsa = {};
1325
1326 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1327 }
1328
1329 /* DB RENDER STATE */
1330
1331 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1332 {
1333 struct si_context *sctx = (struct si_context*)ctx;
1334
1335 /* Pipeline stat & streamout queries. */
1336 if (enable) {
1337 sctx->b.flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1338 sctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
1339 } else {
1340 sctx->b.flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1341 sctx->b.flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1342 }
1343
1344 /* Occlusion queries. */
1345 if (sctx->occlusion_queries_disabled != !enable) {
1346 sctx->occlusion_queries_disabled = !enable;
1347 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1348 }
1349 }
1350
1351 void si_set_occlusion_query_state(struct si_context *sctx,
1352 bool old_perfect_enable)
1353 {
1354 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1355
1356 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
1357
1358 if (perfect_enable != old_perfect_enable)
1359 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1360 }
1361
1362 void si_save_qbo_state(struct si_context *sctx, struct r600_qbo_state *st)
1363 {
1364 st->saved_compute = sctx->cs_shader_state.program;
1365
1366 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1367 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1368 }
1369
1370 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1371 {
1372 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
1373 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1374 unsigned db_shader_control;
1375
1376 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1377
1378 /* DB_RENDER_CONTROL */
1379 if (sctx->dbcb_depth_copy_enabled ||
1380 sctx->dbcb_stencil_copy_enabled) {
1381 radeon_emit(cs,
1382 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1383 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1384 S_028000_COPY_CENTROID(1) |
1385 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1386 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1387 radeon_emit(cs,
1388 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1389 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1390 } else {
1391 radeon_emit(cs,
1392 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1393 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1394 }
1395
1396 /* DB_COUNT_CONTROL (occlusion queries) */
1397 if (sctx->b.num_occlusion_queries > 0 &&
1398 !sctx->occlusion_queries_disabled) {
1399 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1400
1401 if (sctx->b.chip_class >= CIK) {
1402 radeon_emit(cs,
1403 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1404 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1405 S_028004_ZPASS_ENABLE(1) |
1406 S_028004_SLICE_EVEN_ENABLE(1) |
1407 S_028004_SLICE_ODD_ENABLE(1));
1408 } else {
1409 radeon_emit(cs,
1410 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1411 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1412 }
1413 } else {
1414 /* Disable occlusion queries. */
1415 if (sctx->b.chip_class >= CIK) {
1416 radeon_emit(cs, 0);
1417 } else {
1418 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1419 }
1420 }
1421
1422 /* DB_RENDER_OVERRIDE2 */
1423 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1424 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1425 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1426 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1427
1428 db_shader_control = sctx->ps_db_shader_control;
1429
1430 /* Bug workaround for smoothing (overrasterization) on SI. */
1431 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1432 db_shader_control &= C_02880C_Z_ORDER;
1433 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1434 }
1435
1436 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1437 if (!rs || !rs->multisample_enable)
1438 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1439
1440 if (sctx->screen->has_rbplus &&
1441 !sctx->screen->rbplus_allowed)
1442 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1443
1444 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1445 db_shader_control);
1446 }
1447
1448 /*
1449 * format translation
1450 */
1451 static uint32_t si_translate_colorformat(enum pipe_format format)
1452 {
1453 const struct util_format_description *desc = util_format_description(format);
1454 if (!desc)
1455 return V_028C70_COLOR_INVALID;
1456
1457 #define HAS_SIZE(x,y,z,w) \
1458 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1459 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1460
1461 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1462 return V_028C70_COLOR_10_11_11;
1463
1464 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1465 return V_028C70_COLOR_INVALID;
1466
1467 /* hw cannot support mixed formats (except depth/stencil, since
1468 * stencil is not written to). */
1469 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1470 return V_028C70_COLOR_INVALID;
1471
1472 switch (desc->nr_channels) {
1473 case 1:
1474 switch (desc->channel[0].size) {
1475 case 8:
1476 return V_028C70_COLOR_8;
1477 case 16:
1478 return V_028C70_COLOR_16;
1479 case 32:
1480 return V_028C70_COLOR_32;
1481 }
1482 break;
1483 case 2:
1484 if (desc->channel[0].size == desc->channel[1].size) {
1485 switch (desc->channel[0].size) {
1486 case 8:
1487 return V_028C70_COLOR_8_8;
1488 case 16:
1489 return V_028C70_COLOR_16_16;
1490 case 32:
1491 return V_028C70_COLOR_32_32;
1492 }
1493 } else if (HAS_SIZE(8,24,0,0)) {
1494 return V_028C70_COLOR_24_8;
1495 } else if (HAS_SIZE(24,8,0,0)) {
1496 return V_028C70_COLOR_8_24;
1497 }
1498 break;
1499 case 3:
1500 if (HAS_SIZE(5,6,5,0)) {
1501 return V_028C70_COLOR_5_6_5;
1502 } else if (HAS_SIZE(32,8,24,0)) {
1503 return V_028C70_COLOR_X24_8_32_FLOAT;
1504 }
1505 break;
1506 case 4:
1507 if (desc->channel[0].size == desc->channel[1].size &&
1508 desc->channel[0].size == desc->channel[2].size &&
1509 desc->channel[0].size == desc->channel[3].size) {
1510 switch (desc->channel[0].size) {
1511 case 4:
1512 return V_028C70_COLOR_4_4_4_4;
1513 case 8:
1514 return V_028C70_COLOR_8_8_8_8;
1515 case 16:
1516 return V_028C70_COLOR_16_16_16_16;
1517 case 32:
1518 return V_028C70_COLOR_32_32_32_32;
1519 }
1520 } else if (HAS_SIZE(5,5,5,1)) {
1521 return V_028C70_COLOR_1_5_5_5;
1522 } else if (HAS_SIZE(1,5,5,5)) {
1523 return V_028C70_COLOR_5_5_5_1;
1524 } else if (HAS_SIZE(10,10,10,2)) {
1525 return V_028C70_COLOR_2_10_10_10;
1526 }
1527 break;
1528 }
1529 return V_028C70_COLOR_INVALID;
1530 }
1531
1532 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1533 {
1534 if (SI_BIG_ENDIAN) {
1535 switch(colorformat) {
1536 /* 8-bit buffers. */
1537 case V_028C70_COLOR_8:
1538 return V_028C70_ENDIAN_NONE;
1539
1540 /* 16-bit buffers. */
1541 case V_028C70_COLOR_5_6_5:
1542 case V_028C70_COLOR_1_5_5_5:
1543 case V_028C70_COLOR_4_4_4_4:
1544 case V_028C70_COLOR_16:
1545 case V_028C70_COLOR_8_8:
1546 return V_028C70_ENDIAN_8IN16;
1547
1548 /* 32-bit buffers. */
1549 case V_028C70_COLOR_8_8_8_8:
1550 case V_028C70_COLOR_2_10_10_10:
1551 case V_028C70_COLOR_8_24:
1552 case V_028C70_COLOR_24_8:
1553 case V_028C70_COLOR_16_16:
1554 return V_028C70_ENDIAN_8IN32;
1555
1556 /* 64-bit buffers. */
1557 case V_028C70_COLOR_16_16_16_16:
1558 return V_028C70_ENDIAN_8IN16;
1559
1560 case V_028C70_COLOR_32_32:
1561 return V_028C70_ENDIAN_8IN32;
1562
1563 /* 128-bit buffers. */
1564 case V_028C70_COLOR_32_32_32_32:
1565 return V_028C70_ENDIAN_8IN32;
1566 default:
1567 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1568 }
1569 } else {
1570 return V_028C70_ENDIAN_NONE;
1571 }
1572 }
1573
1574 static uint32_t si_translate_dbformat(enum pipe_format format)
1575 {
1576 switch (format) {
1577 case PIPE_FORMAT_Z16_UNORM:
1578 return V_028040_Z_16;
1579 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1580 case PIPE_FORMAT_X8Z24_UNORM:
1581 case PIPE_FORMAT_Z24X8_UNORM:
1582 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1583 return V_028040_Z_24; /* deprecated on SI */
1584 case PIPE_FORMAT_Z32_FLOAT:
1585 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1586 return V_028040_Z_32_FLOAT;
1587 default:
1588 return V_028040_Z_INVALID;
1589 }
1590 }
1591
1592 /*
1593 * Texture translation
1594 */
1595
1596 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1597 enum pipe_format format,
1598 const struct util_format_description *desc,
1599 int first_non_void)
1600 {
1601 struct si_screen *sscreen = (struct si_screen*)screen;
1602 bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
1603 sscreen->info.drm_minor >= 31) ||
1604 sscreen->info.drm_major == 3;
1605 bool uniform = true;
1606 int i;
1607
1608 /* Colorspace (return non-RGB formats directly). */
1609 switch (desc->colorspace) {
1610 /* Depth stencil formats */
1611 case UTIL_FORMAT_COLORSPACE_ZS:
1612 switch (format) {
1613 case PIPE_FORMAT_Z16_UNORM:
1614 return V_008F14_IMG_DATA_FORMAT_16;
1615 case PIPE_FORMAT_X24S8_UINT:
1616 case PIPE_FORMAT_S8X24_UINT:
1617 /*
1618 * Implemented as an 8_8_8_8 data format to fix texture
1619 * gathers in stencil sampling. This affects at least
1620 * GL45-CTS.texture_cube_map_array.sampling on VI.
1621 */
1622 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1623 case PIPE_FORMAT_Z24X8_UNORM:
1624 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1625 return V_008F14_IMG_DATA_FORMAT_8_24;
1626 case PIPE_FORMAT_X8Z24_UNORM:
1627 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1628 return V_008F14_IMG_DATA_FORMAT_24_8;
1629 case PIPE_FORMAT_S8_UINT:
1630 return V_008F14_IMG_DATA_FORMAT_8;
1631 case PIPE_FORMAT_Z32_FLOAT:
1632 return V_008F14_IMG_DATA_FORMAT_32;
1633 case PIPE_FORMAT_X32_S8X24_UINT:
1634 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1635 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1636 default:
1637 goto out_unknown;
1638 }
1639
1640 case UTIL_FORMAT_COLORSPACE_YUV:
1641 goto out_unknown; /* TODO */
1642
1643 case UTIL_FORMAT_COLORSPACE_SRGB:
1644 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1645 goto out_unknown;
1646 break;
1647
1648 default:
1649 break;
1650 }
1651
1652 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1653 if (!enable_compressed_formats)
1654 goto out_unknown;
1655
1656 switch (format) {
1657 case PIPE_FORMAT_RGTC1_SNORM:
1658 case PIPE_FORMAT_LATC1_SNORM:
1659 case PIPE_FORMAT_RGTC1_UNORM:
1660 case PIPE_FORMAT_LATC1_UNORM:
1661 return V_008F14_IMG_DATA_FORMAT_BC4;
1662 case PIPE_FORMAT_RGTC2_SNORM:
1663 case PIPE_FORMAT_LATC2_SNORM:
1664 case PIPE_FORMAT_RGTC2_UNORM:
1665 case PIPE_FORMAT_LATC2_UNORM:
1666 return V_008F14_IMG_DATA_FORMAT_BC5;
1667 default:
1668 goto out_unknown;
1669 }
1670 }
1671
1672 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1673 (sscreen->info.family == CHIP_STONEY ||
1674 sscreen->info.family == CHIP_VEGA10 ||
1675 sscreen->info.family == CHIP_RAVEN)) {
1676 switch (format) {
1677 case PIPE_FORMAT_ETC1_RGB8:
1678 case PIPE_FORMAT_ETC2_RGB8:
1679 case PIPE_FORMAT_ETC2_SRGB8:
1680 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1681 case PIPE_FORMAT_ETC2_RGB8A1:
1682 case PIPE_FORMAT_ETC2_SRGB8A1:
1683 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1684 case PIPE_FORMAT_ETC2_RGBA8:
1685 case PIPE_FORMAT_ETC2_SRGBA8:
1686 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1687 case PIPE_FORMAT_ETC2_R11_UNORM:
1688 case PIPE_FORMAT_ETC2_R11_SNORM:
1689 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1690 case PIPE_FORMAT_ETC2_RG11_UNORM:
1691 case PIPE_FORMAT_ETC2_RG11_SNORM:
1692 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1693 default:
1694 goto out_unknown;
1695 }
1696 }
1697
1698 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1699 if (!enable_compressed_formats)
1700 goto out_unknown;
1701
1702 switch (format) {
1703 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1704 case PIPE_FORMAT_BPTC_SRGBA:
1705 return V_008F14_IMG_DATA_FORMAT_BC7;
1706 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1707 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1708 return V_008F14_IMG_DATA_FORMAT_BC6;
1709 default:
1710 goto out_unknown;
1711 }
1712 }
1713
1714 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1715 switch (format) {
1716 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1717 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1718 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1719 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1720 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1721 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1722 default:
1723 goto out_unknown;
1724 }
1725 }
1726
1727 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1728 if (!enable_compressed_formats)
1729 goto out_unknown;
1730
1731 switch (format) {
1732 case PIPE_FORMAT_DXT1_RGB:
1733 case PIPE_FORMAT_DXT1_RGBA:
1734 case PIPE_FORMAT_DXT1_SRGB:
1735 case PIPE_FORMAT_DXT1_SRGBA:
1736 return V_008F14_IMG_DATA_FORMAT_BC1;
1737 case PIPE_FORMAT_DXT3_RGBA:
1738 case PIPE_FORMAT_DXT3_SRGBA:
1739 return V_008F14_IMG_DATA_FORMAT_BC2;
1740 case PIPE_FORMAT_DXT5_RGBA:
1741 case PIPE_FORMAT_DXT5_SRGBA:
1742 return V_008F14_IMG_DATA_FORMAT_BC3;
1743 default:
1744 goto out_unknown;
1745 }
1746 }
1747
1748 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1749 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1750 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1751 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1752 }
1753
1754 /* R8G8Bx_SNORM - TODO CxV8U8 */
1755
1756 /* hw cannot support mixed formats (except depth/stencil, since only
1757 * depth is read).*/
1758 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1759 goto out_unknown;
1760
1761 /* See whether the components are of the same size. */
1762 for (i = 1; i < desc->nr_channels; i++) {
1763 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1764 }
1765
1766 /* Non-uniform formats. */
1767 if (!uniform) {
1768 switch(desc->nr_channels) {
1769 case 3:
1770 if (desc->channel[0].size == 5 &&
1771 desc->channel[1].size == 6 &&
1772 desc->channel[2].size == 5) {
1773 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1774 }
1775 goto out_unknown;
1776 case 4:
1777 if (desc->channel[0].size == 5 &&
1778 desc->channel[1].size == 5 &&
1779 desc->channel[2].size == 5 &&
1780 desc->channel[3].size == 1) {
1781 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1782 }
1783 if (desc->channel[0].size == 1 &&
1784 desc->channel[1].size == 5 &&
1785 desc->channel[2].size == 5 &&
1786 desc->channel[3].size == 5) {
1787 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1788 }
1789 if (desc->channel[0].size == 10 &&
1790 desc->channel[1].size == 10 &&
1791 desc->channel[2].size == 10 &&
1792 desc->channel[3].size == 2) {
1793 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1794 }
1795 goto out_unknown;
1796 }
1797 goto out_unknown;
1798 }
1799
1800 if (first_non_void < 0 || first_non_void > 3)
1801 goto out_unknown;
1802
1803 /* uniform formats */
1804 switch (desc->channel[first_non_void].size) {
1805 case 4:
1806 switch (desc->nr_channels) {
1807 #if 0 /* Not supported for render targets */
1808 case 2:
1809 return V_008F14_IMG_DATA_FORMAT_4_4;
1810 #endif
1811 case 4:
1812 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1813 }
1814 break;
1815 case 8:
1816 switch (desc->nr_channels) {
1817 case 1:
1818 return V_008F14_IMG_DATA_FORMAT_8;
1819 case 2:
1820 return V_008F14_IMG_DATA_FORMAT_8_8;
1821 case 4:
1822 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1823 }
1824 break;
1825 case 16:
1826 switch (desc->nr_channels) {
1827 case 1:
1828 return V_008F14_IMG_DATA_FORMAT_16;
1829 case 2:
1830 return V_008F14_IMG_DATA_FORMAT_16_16;
1831 case 4:
1832 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1833 }
1834 break;
1835 case 32:
1836 switch (desc->nr_channels) {
1837 case 1:
1838 return V_008F14_IMG_DATA_FORMAT_32;
1839 case 2:
1840 return V_008F14_IMG_DATA_FORMAT_32_32;
1841 #if 0 /* Not supported for render targets */
1842 case 3:
1843 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1844 #endif
1845 case 4:
1846 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1847 }
1848 }
1849
1850 out_unknown:
1851 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1852 return ~0;
1853 }
1854
1855 static unsigned si_tex_wrap(unsigned wrap)
1856 {
1857 switch (wrap) {
1858 default:
1859 case PIPE_TEX_WRAP_REPEAT:
1860 return V_008F30_SQ_TEX_WRAP;
1861 case PIPE_TEX_WRAP_CLAMP:
1862 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1863 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1864 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1865 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1866 return V_008F30_SQ_TEX_CLAMP_BORDER;
1867 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1868 return V_008F30_SQ_TEX_MIRROR;
1869 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1870 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1871 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1872 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1873 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1874 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1875 }
1876 }
1877
1878 static unsigned si_tex_mipfilter(unsigned filter)
1879 {
1880 switch (filter) {
1881 case PIPE_TEX_MIPFILTER_NEAREST:
1882 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1883 case PIPE_TEX_MIPFILTER_LINEAR:
1884 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1885 default:
1886 case PIPE_TEX_MIPFILTER_NONE:
1887 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1888 }
1889 }
1890
1891 static unsigned si_tex_compare(unsigned compare)
1892 {
1893 switch (compare) {
1894 default:
1895 case PIPE_FUNC_NEVER:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1897 case PIPE_FUNC_LESS:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1899 case PIPE_FUNC_EQUAL:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1901 case PIPE_FUNC_LEQUAL:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1903 case PIPE_FUNC_GREATER:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1905 case PIPE_FUNC_NOTEQUAL:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1907 case PIPE_FUNC_GEQUAL:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1909 case PIPE_FUNC_ALWAYS:
1910 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1911 }
1912 }
1913
1914 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1915 unsigned view_target, unsigned nr_samples)
1916 {
1917 unsigned res_target = rtex->resource.b.b.target;
1918
1919 if (view_target == PIPE_TEXTURE_CUBE ||
1920 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1921 res_target = view_target;
1922 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1923 else if (res_target == PIPE_TEXTURE_CUBE ||
1924 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1925 res_target = PIPE_TEXTURE_2D_ARRAY;
1926
1927 /* GFX9 allocates 1D textures as 2D. */
1928 if ((res_target == PIPE_TEXTURE_1D ||
1929 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1930 sscreen->info.chip_class >= GFX9 &&
1931 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1932 if (res_target == PIPE_TEXTURE_1D)
1933 res_target = PIPE_TEXTURE_2D;
1934 else
1935 res_target = PIPE_TEXTURE_2D_ARRAY;
1936 }
1937
1938 switch (res_target) {
1939 default:
1940 case PIPE_TEXTURE_1D:
1941 return V_008F1C_SQ_RSRC_IMG_1D;
1942 case PIPE_TEXTURE_1D_ARRAY:
1943 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1944 case PIPE_TEXTURE_2D:
1945 case PIPE_TEXTURE_RECT:
1946 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1947 V_008F1C_SQ_RSRC_IMG_2D;
1948 case PIPE_TEXTURE_2D_ARRAY:
1949 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1950 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1951 case PIPE_TEXTURE_3D:
1952 return V_008F1C_SQ_RSRC_IMG_3D;
1953 case PIPE_TEXTURE_CUBE:
1954 case PIPE_TEXTURE_CUBE_ARRAY:
1955 return V_008F1C_SQ_RSRC_IMG_CUBE;
1956 }
1957 }
1958
1959 /*
1960 * Format support testing
1961 */
1962
1963 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1964 {
1965 const struct util_format_description *desc = util_format_description(format);
1966 if (!desc)
1967 return false;
1968
1969 return si_translate_texformat(screen, format, desc,
1970 util_format_get_first_non_void_channel(format)) != ~0U;
1971 }
1972
1973 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1974 const struct util_format_description *desc,
1975 int first_non_void)
1976 {
1977 int i;
1978
1979 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1980 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1981
1982 assert(first_non_void >= 0);
1983
1984 if (desc->nr_channels == 4 &&
1985 desc->channel[0].size == 10 &&
1986 desc->channel[1].size == 10 &&
1987 desc->channel[2].size == 10 &&
1988 desc->channel[3].size == 2)
1989 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1990
1991 /* See whether the components are of the same size. */
1992 for (i = 0; i < desc->nr_channels; i++) {
1993 if (desc->channel[first_non_void].size != desc->channel[i].size)
1994 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1995 }
1996
1997 switch (desc->channel[first_non_void].size) {
1998 case 8:
1999 switch (desc->nr_channels) {
2000 case 1:
2001 case 3: /* 3 loads */
2002 return V_008F0C_BUF_DATA_FORMAT_8;
2003 case 2:
2004 return V_008F0C_BUF_DATA_FORMAT_8_8;
2005 case 4:
2006 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2007 }
2008 break;
2009 case 16:
2010 switch (desc->nr_channels) {
2011 case 1:
2012 case 3: /* 3 loads */
2013 return V_008F0C_BUF_DATA_FORMAT_16;
2014 case 2:
2015 return V_008F0C_BUF_DATA_FORMAT_16_16;
2016 case 4:
2017 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2018 }
2019 break;
2020 case 32:
2021 switch (desc->nr_channels) {
2022 case 1:
2023 return V_008F0C_BUF_DATA_FORMAT_32;
2024 case 2:
2025 return V_008F0C_BUF_DATA_FORMAT_32_32;
2026 case 3:
2027 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2028 case 4:
2029 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2030 }
2031 break;
2032 case 64:
2033 /* Legacy double formats. */
2034 switch (desc->nr_channels) {
2035 case 1: /* 1 load */
2036 return V_008F0C_BUF_DATA_FORMAT_32_32;
2037 case 2: /* 1 load */
2038 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2039 case 3: /* 3 loads */
2040 return V_008F0C_BUF_DATA_FORMAT_32_32;
2041 case 4: /* 2 loads */
2042 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2043 }
2044 break;
2045 }
2046
2047 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2048 }
2049
2050 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2051 const struct util_format_description *desc,
2052 int first_non_void)
2053 {
2054 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2055 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2056
2057 assert(first_non_void >= 0);
2058
2059 switch (desc->channel[first_non_void].type) {
2060 case UTIL_FORMAT_TYPE_SIGNED:
2061 case UTIL_FORMAT_TYPE_FIXED:
2062 if (desc->channel[first_non_void].size >= 32 ||
2063 desc->channel[first_non_void].pure_integer)
2064 return V_008F0C_BUF_NUM_FORMAT_SINT;
2065 else if (desc->channel[first_non_void].normalized)
2066 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2067 else
2068 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2069 break;
2070 case UTIL_FORMAT_TYPE_UNSIGNED:
2071 if (desc->channel[first_non_void].size >= 32 ||
2072 desc->channel[first_non_void].pure_integer)
2073 return V_008F0C_BUF_NUM_FORMAT_UINT;
2074 else if (desc->channel[first_non_void].normalized)
2075 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2076 else
2077 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2078 break;
2079 case UTIL_FORMAT_TYPE_FLOAT:
2080 default:
2081 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2082 }
2083 }
2084
2085 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2086 enum pipe_format format,
2087 unsigned usage)
2088 {
2089 const struct util_format_description *desc;
2090 int first_non_void;
2091 unsigned data_format;
2092
2093 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2094 PIPE_BIND_SAMPLER_VIEW |
2095 PIPE_BIND_VERTEX_BUFFER)) == 0);
2096
2097 desc = util_format_description(format);
2098 if (!desc)
2099 return 0;
2100
2101 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2102 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2103 * for read-only access (with caveats surrounding bounds checks), but
2104 * obviously fails for write access which we have to implement for
2105 * shader images. Luckily, OpenGL doesn't expect this to be supported
2106 * anyway, and so the only impact is on PBO uploads / downloads, which
2107 * shouldn't be expected to be fast for GL_RGB anyway.
2108 */
2109 if (desc->block.bits == 3 * 8 ||
2110 desc->block.bits == 3 * 16) {
2111 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2112 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2113 if (!usage)
2114 return 0;
2115 }
2116 }
2117
2118 first_non_void = util_format_get_first_non_void_channel(format);
2119 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2120 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2121 return 0;
2122
2123 return usage;
2124 }
2125
2126 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2127 {
2128 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2129 si_translate_colorswap(format, false) != ~0U;
2130 }
2131
2132 static bool si_is_zs_format_supported(enum pipe_format format)
2133 {
2134 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2135 }
2136
2137 static boolean si_is_format_supported(struct pipe_screen *screen,
2138 enum pipe_format format,
2139 enum pipe_texture_target target,
2140 unsigned sample_count,
2141 unsigned usage)
2142 {
2143 unsigned retval = 0;
2144
2145 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2146 R600_ERR("r600: unsupported texture type %d\n", target);
2147 return false;
2148 }
2149
2150 if (!util_format_is_supported(format, usage))
2151 return false;
2152
2153 if (sample_count > 1) {
2154 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2155 return false;
2156
2157 if (usage & PIPE_BIND_SHADER_IMAGE)
2158 return false;
2159
2160 switch (sample_count) {
2161 case 2:
2162 case 4:
2163 case 8:
2164 break;
2165 case 16:
2166 if (format == PIPE_FORMAT_NONE)
2167 return true;
2168 else
2169 return false;
2170 default:
2171 return false;
2172 }
2173 }
2174
2175 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2176 PIPE_BIND_SHADER_IMAGE)) {
2177 if (target == PIPE_BUFFER) {
2178 retval |= si_is_vertex_format_supported(
2179 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2180 PIPE_BIND_SHADER_IMAGE));
2181 } else {
2182 if (si_is_sampler_format_supported(screen, format))
2183 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2184 PIPE_BIND_SHADER_IMAGE);
2185 }
2186 }
2187
2188 if ((usage & (PIPE_BIND_RENDER_TARGET |
2189 PIPE_BIND_DISPLAY_TARGET |
2190 PIPE_BIND_SCANOUT |
2191 PIPE_BIND_SHARED |
2192 PIPE_BIND_BLENDABLE)) &&
2193 si_is_colorbuffer_format_supported(format)) {
2194 retval |= usage &
2195 (PIPE_BIND_RENDER_TARGET |
2196 PIPE_BIND_DISPLAY_TARGET |
2197 PIPE_BIND_SCANOUT |
2198 PIPE_BIND_SHARED);
2199 if (!util_format_is_pure_integer(format) &&
2200 !util_format_is_depth_or_stencil(format))
2201 retval |= usage & PIPE_BIND_BLENDABLE;
2202 }
2203
2204 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2205 si_is_zs_format_supported(format)) {
2206 retval |= PIPE_BIND_DEPTH_STENCIL;
2207 }
2208
2209 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2210 retval |= si_is_vertex_format_supported(screen, format,
2211 PIPE_BIND_VERTEX_BUFFER);
2212 }
2213
2214 if ((usage & PIPE_BIND_LINEAR) &&
2215 !util_format_is_compressed(format) &&
2216 !(usage & PIPE_BIND_DEPTH_STENCIL))
2217 retval |= PIPE_BIND_LINEAR;
2218
2219 return retval == usage;
2220 }
2221
2222 /*
2223 * framebuffer handling
2224 */
2225
2226 static void si_choose_spi_color_formats(struct r600_surface *surf,
2227 unsigned format, unsigned swap,
2228 unsigned ntype, bool is_depth)
2229 {
2230 /* Alpha is needed for alpha-to-coverage.
2231 * Blending may be with or without alpha.
2232 */
2233 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2234 unsigned alpha = 0; /* exports alpha, but may not support blending */
2235 unsigned blend = 0; /* supports blending, but may not export alpha */
2236 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2237
2238 /* Choose the SPI color formats. These are required values for RB+.
2239 * Other chips have multiple choices, though they are not necessarily better.
2240 */
2241 switch (format) {
2242 case V_028C70_COLOR_5_6_5:
2243 case V_028C70_COLOR_1_5_5_5:
2244 case V_028C70_COLOR_5_5_5_1:
2245 case V_028C70_COLOR_4_4_4_4:
2246 case V_028C70_COLOR_10_11_11:
2247 case V_028C70_COLOR_11_11_10:
2248 case V_028C70_COLOR_8:
2249 case V_028C70_COLOR_8_8:
2250 case V_028C70_COLOR_8_8_8_8:
2251 case V_028C70_COLOR_10_10_10_2:
2252 case V_028C70_COLOR_2_10_10_10:
2253 if (ntype == V_028C70_NUMBER_UINT)
2254 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2255 else if (ntype == V_028C70_NUMBER_SINT)
2256 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2257 else
2258 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2259 break;
2260
2261 case V_028C70_COLOR_16:
2262 case V_028C70_COLOR_16_16:
2263 case V_028C70_COLOR_16_16_16_16:
2264 if (ntype == V_028C70_NUMBER_UNORM ||
2265 ntype == V_028C70_NUMBER_SNORM) {
2266 /* UNORM16 and SNORM16 don't support blending */
2267 if (ntype == V_028C70_NUMBER_UNORM)
2268 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2269 else
2270 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2271
2272 /* Use 32 bits per channel for blending. */
2273 if (format == V_028C70_COLOR_16) {
2274 if (swap == V_028C70_SWAP_STD) { /* R */
2275 blend = V_028714_SPI_SHADER_32_R;
2276 blend_alpha = V_028714_SPI_SHADER_32_AR;
2277 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2278 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2279 else
2280 assert(0);
2281 } else if (format == V_028C70_COLOR_16_16) {
2282 if (swap == V_028C70_SWAP_STD) { /* RG */
2283 blend = V_028714_SPI_SHADER_32_GR;
2284 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2285 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2286 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2287 else
2288 assert(0);
2289 } else /* 16_16_16_16 */
2290 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2291 } else if (ntype == V_028C70_NUMBER_UINT)
2292 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2293 else if (ntype == V_028C70_NUMBER_SINT)
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2295 else if (ntype == V_028C70_NUMBER_FLOAT)
2296 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2297 else
2298 assert(0);
2299 break;
2300
2301 case V_028C70_COLOR_32:
2302 if (swap == V_028C70_SWAP_STD) { /* R */
2303 blend = normal = V_028714_SPI_SHADER_32_R;
2304 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2305 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2306 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2307 else
2308 assert(0);
2309 break;
2310
2311 case V_028C70_COLOR_32_32:
2312 if (swap == V_028C70_SWAP_STD) { /* RG */
2313 blend = normal = V_028714_SPI_SHADER_32_GR;
2314 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2315 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2316 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2317 else
2318 assert(0);
2319 break;
2320
2321 case V_028C70_COLOR_32_32_32_32:
2322 case V_028C70_COLOR_8_24:
2323 case V_028C70_COLOR_24_8:
2324 case V_028C70_COLOR_X24_8_32_FLOAT:
2325 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2326 break;
2327
2328 default:
2329 assert(0);
2330 return;
2331 }
2332
2333 /* The DB->CB copy needs 32_ABGR. */
2334 if (is_depth)
2335 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2336
2337 surf->spi_shader_col_format = normal;
2338 surf->spi_shader_col_format_alpha = alpha;
2339 surf->spi_shader_col_format_blend = blend;
2340 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2341 }
2342
2343 static void si_initialize_color_surface(struct si_context *sctx,
2344 struct r600_surface *surf)
2345 {
2346 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2347 unsigned color_info, color_attrib;
2348 unsigned format, swap, ntype, endian;
2349 const struct util_format_description *desc;
2350 int firstchan;
2351 unsigned blend_clamp = 0, blend_bypass = 0;
2352
2353 desc = util_format_description(surf->base.format);
2354 for (firstchan = 0; firstchan < 4; firstchan++) {
2355 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2356 break;
2357 }
2358 }
2359 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2360 ntype = V_028C70_NUMBER_FLOAT;
2361 } else {
2362 ntype = V_028C70_NUMBER_UNORM;
2363 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2364 ntype = V_028C70_NUMBER_SRGB;
2365 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2366 if (desc->channel[firstchan].pure_integer) {
2367 ntype = V_028C70_NUMBER_SINT;
2368 } else {
2369 assert(desc->channel[firstchan].normalized);
2370 ntype = V_028C70_NUMBER_SNORM;
2371 }
2372 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2373 if (desc->channel[firstchan].pure_integer) {
2374 ntype = V_028C70_NUMBER_UINT;
2375 } else {
2376 assert(desc->channel[firstchan].normalized);
2377 ntype = V_028C70_NUMBER_UNORM;
2378 }
2379 }
2380 }
2381
2382 format = si_translate_colorformat(surf->base.format);
2383 if (format == V_028C70_COLOR_INVALID) {
2384 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2385 }
2386 assert(format != V_028C70_COLOR_INVALID);
2387 swap = si_translate_colorswap(surf->base.format, false);
2388 endian = si_colorformat_endian_swap(format);
2389
2390 /* blend clamp should be set for all NORM/SRGB types */
2391 if (ntype == V_028C70_NUMBER_UNORM ||
2392 ntype == V_028C70_NUMBER_SNORM ||
2393 ntype == V_028C70_NUMBER_SRGB)
2394 blend_clamp = 1;
2395
2396 /* set blend bypass according to docs if SINT/UINT or
2397 8/24 COLOR variants */
2398 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2399 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2400 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2401 blend_clamp = 0;
2402 blend_bypass = 1;
2403 }
2404
2405 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2406 if (format == V_028C70_COLOR_8 ||
2407 format == V_028C70_COLOR_8_8 ||
2408 format == V_028C70_COLOR_8_8_8_8)
2409 surf->color_is_int8 = true;
2410 else if (format == V_028C70_COLOR_10_10_10_2 ||
2411 format == V_028C70_COLOR_2_10_10_10)
2412 surf->color_is_int10 = true;
2413 }
2414
2415 color_info = S_028C70_FORMAT(format) |
2416 S_028C70_COMP_SWAP(swap) |
2417 S_028C70_BLEND_CLAMP(blend_clamp) |
2418 S_028C70_BLEND_BYPASS(blend_bypass) |
2419 S_028C70_SIMPLE_FLOAT(1) |
2420 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2421 ntype != V_028C70_NUMBER_SNORM &&
2422 ntype != V_028C70_NUMBER_SRGB &&
2423 format != V_028C70_COLOR_8_24 &&
2424 format != V_028C70_COLOR_24_8) |
2425 S_028C70_NUMBER_TYPE(ntype) |
2426 S_028C70_ENDIAN(endian);
2427
2428 /* Intensity is implemented as Red, so treat it that way. */
2429 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2430 util_format_is_intensity(surf->base.format));
2431
2432 if (rtex->resource.b.b.nr_samples > 1) {
2433 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2434
2435 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2436 S_028C74_NUM_FRAGMENTS(log_samples);
2437
2438 if (rtex->fmask.size) {
2439 color_info |= S_028C70_COMPRESSION(1);
2440 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2441
2442 if (sctx->b.chip_class == SI) {
2443 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2444 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2445 }
2446 }
2447 }
2448
2449 if (sctx->b.chip_class >= VI) {
2450 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2451 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2452
2453 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2454 64 for APU because all of our APUs to date use DIMMs which have
2455 a request granularity size of 64B while all other chips have a
2456 32B request size */
2457 if (!sctx->screen->info.has_dedicated_vram)
2458 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2459
2460 if (rtex->resource.b.b.nr_samples > 1) {
2461 if (rtex->surface.bpe == 1)
2462 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2463 else if (rtex->surface.bpe == 2)
2464 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2465 }
2466
2467 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2468 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2469 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2470 }
2471
2472 /* This must be set for fast clear to work without FMASK. */
2473 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2474 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2475 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2476 }
2477
2478 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2479 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2480
2481 if (sctx->b.chip_class >= GFX9) {
2482 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2483
2484 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2485 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2486 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2487 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2488 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2489 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2490 }
2491
2492 surf->cb_color_view = color_view;
2493 surf->cb_color_info = color_info;
2494 surf->cb_color_attrib = color_attrib;
2495
2496 /* Determine pixel shader export format */
2497 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2498
2499 surf->color_initialized = true;
2500 }
2501
2502 static void si_init_depth_surface(struct si_context *sctx,
2503 struct r600_surface *surf)
2504 {
2505 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2506 unsigned level = surf->base.u.tex.level;
2507 unsigned format, stencil_format;
2508 uint32_t z_info, s_info;
2509
2510 format = si_translate_dbformat(rtex->db_render_format);
2511 stencil_format = rtex->surface.has_stencil ?
2512 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2513
2514 assert(format != V_028040_Z_INVALID);
2515 if (format == V_028040_Z_INVALID)
2516 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2517
2518 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2519 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2520 surf->db_htile_data_base = 0;
2521 surf->db_htile_surface = 0;
2522
2523 if (sctx->b.chip_class >= GFX9) {
2524 assert(rtex->surface.u.gfx9.surf_offset == 0);
2525 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2526 surf->db_stencil_base = (rtex->resource.gpu_address +
2527 rtex->surface.u.gfx9.stencil_offset) >> 8;
2528 z_info = S_028038_FORMAT(format) |
2529 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2530 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2531 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2532 s_info = S_02803C_FORMAT(stencil_format) |
2533 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2534 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2535 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2536 surf->db_depth_view |= S_028008_MIPID(level);
2537 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2538 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2539
2540 if (si_htile_enabled(rtex, level)) {
2541 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2542 S_028038_ALLOW_EXPCLEAR(1);
2543
2544 if (rtex->tc_compatible_htile) {
2545 unsigned max_zplanes = 4;
2546
2547 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2548 rtex->resource.b.b.nr_samples > 1)
2549 max_zplanes = 2;
2550
2551 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2552 S_028038_ITERATE_FLUSH(1);
2553 s_info |= S_02803C_ITERATE_FLUSH(1);
2554 }
2555
2556 if (rtex->surface.has_stencil) {
2557 /* Stencil buffer workaround ported from the SI-CI-VI code.
2558 * See that for explanation.
2559 */
2560 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2561 } else {
2562 /* Use all HTILE for depth if there's no stencil. */
2563 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2564 }
2565
2566 surf->db_htile_data_base = (rtex->resource.gpu_address +
2567 rtex->htile_offset) >> 8;
2568 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2569 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2570 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2571 }
2572 } else {
2573 /* SI-CI-VI */
2574 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2575
2576 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2577
2578 surf->db_depth_base = (rtex->resource.gpu_address +
2579 rtex->surface.u.legacy.level[level].offset) >> 8;
2580 surf->db_stencil_base = (rtex->resource.gpu_address +
2581 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2582
2583 z_info = S_028040_FORMAT(format) |
2584 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2585 s_info = S_028044_FORMAT(stencil_format);
2586 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2587
2588 if (sctx->b.chip_class >= CIK) {
2589 struct radeon_info *info = &sctx->screen->info;
2590 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2591 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2592 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2593 unsigned tile_mode = info->si_tile_mode_array[index];
2594 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2595 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2596
2597 surf->db_depth_info |=
2598 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2599 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2600 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2601 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2602 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2603 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2604 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2605 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2606 } else {
2607 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2608 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2609 tile_mode_index = si_tile_mode_index(rtex, level, true);
2610 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2611 }
2612
2613 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2614 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2615 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2616 levelinfo->nblk_y) / 64 - 1);
2617
2618 if (si_htile_enabled(rtex, level)) {
2619 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2620 S_028040_ALLOW_EXPCLEAR(1);
2621
2622 if (rtex->surface.has_stencil) {
2623 /* Workaround: For a not yet understood reason, the
2624 * combination of MSAA, fast stencil clear and stencil
2625 * decompress messes with subsequent stencil buffer
2626 * uses. Problem was reproduced on Verde, Bonaire,
2627 * Tonga, and Carrizo.
2628 *
2629 * Disabling EXPCLEAR works around the problem.
2630 *
2631 * Check piglit's arb_texture_multisample-stencil-clear
2632 * test if you want to try changing this.
2633 */
2634 if (rtex->resource.b.b.nr_samples <= 1)
2635 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2636 } else if (!rtex->tc_compatible_htile) {
2637 /* Use all of the htile_buffer for depth if there's no stencil.
2638 * This must not be set when TC-compatible HTILE is enabled
2639 * due to a hw bug.
2640 */
2641 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2642 }
2643
2644 surf->db_htile_data_base = (rtex->resource.gpu_address +
2645 rtex->htile_offset) >> 8;
2646 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2647
2648 if (rtex->tc_compatible_htile) {
2649 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2650
2651 if (rtex->resource.b.b.nr_samples <= 1)
2652 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2653 else if (rtex->resource.b.b.nr_samples <= 4)
2654 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2655 else
2656 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2657 }
2658 }
2659 }
2660
2661 surf->db_z_info = z_info;
2662 surf->db_stencil_info = s_info;
2663
2664 surf->depth_initialized = true;
2665 }
2666
2667 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2668 {
2669 if (sctx->decompression_enabled)
2670 return;
2671
2672 if (sctx->framebuffer.state.zsbuf) {
2673 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2674 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2675
2676 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2677
2678 if (rtex->surface.has_stencil)
2679 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2680 }
2681
2682 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2683 while (compressed_cb_mask) {
2684 unsigned i = u_bit_scan(&compressed_cb_mask);
2685 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2686 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2687
2688 if (rtex->fmask.size)
2689 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2690 if (rtex->dcc_gather_statistics)
2691 rtex->separate_dcc_dirty = true;
2692 }
2693 }
2694
2695 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2696 {
2697 for (int i = 0; i < state->nr_cbufs; ++i) {
2698 struct r600_surface *surf = NULL;
2699 struct r600_texture *rtex;
2700
2701 if (!state->cbufs[i])
2702 continue;
2703 surf = (struct r600_surface*)state->cbufs[i];
2704 rtex = (struct r600_texture*)surf->base.texture;
2705
2706 p_atomic_dec(&rtex->framebuffers_bound);
2707 }
2708 }
2709
2710 static void si_set_framebuffer_state(struct pipe_context *ctx,
2711 const struct pipe_framebuffer_state *state)
2712 {
2713 struct si_context *sctx = (struct si_context *)ctx;
2714 struct pipe_constant_buffer constbuf = {0};
2715 struct r600_surface *surf = NULL;
2716 struct r600_texture *rtex;
2717 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2718 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2719 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2720 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2721 bool old_has_stencil =
2722 old_has_zsbuf &&
2723 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2724 bool unbound = false;
2725 int i;
2726
2727 si_update_fb_dirtiness_after_rendering(sctx);
2728
2729 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2730 if (!sctx->framebuffer.state.cbufs[i])
2731 continue;
2732
2733 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2734 if (rtex->dcc_gather_statistics)
2735 vi_separate_dcc_stop_query(sctx, rtex);
2736 }
2737
2738 /* Disable DCC if the formats are incompatible. */
2739 for (i = 0; i < state->nr_cbufs; i++) {
2740 if (!state->cbufs[i])
2741 continue;
2742
2743 surf = (struct r600_surface*)state->cbufs[i];
2744 rtex = (struct r600_texture*)surf->base.texture;
2745
2746 if (!surf->dcc_incompatible)
2747 continue;
2748
2749 /* Since the DCC decompression calls back into set_framebuffer-
2750 * _state, we need to unbind the framebuffer, so that
2751 * vi_separate_dcc_stop_query isn't called twice with the same
2752 * color buffer.
2753 */
2754 if (!unbound) {
2755 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2756 unbound = true;
2757 }
2758
2759 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2760 if (!si_texture_disable_dcc(sctx, rtex))
2761 si_decompress_dcc(ctx, rtex);
2762
2763 surf->dcc_incompatible = false;
2764 }
2765
2766 /* Only flush TC when changing the framebuffer state, because
2767 * the only client not using TC that can change textures is
2768 * the framebuffer.
2769 *
2770 * Wait for compute shaders because of possible transitions:
2771 * - FB write -> shader read
2772 * - shader write -> FB read
2773 *
2774 * DB caches are flushed on demand (using si_decompress_textures).
2775 *
2776 * When MSAA is enabled, CB and TC caches are flushed on demand
2777 * (after FMASK decompression). Shader write -> FB read transitions
2778 * cannot happen for MSAA textures, because MSAA shader images are
2779 * not supported.
2780 *
2781 * Only flush and wait for CB if there is actually a bound color buffer.
2782 */
2783 if (sctx->framebuffer.uncompressed_cb_mask)
2784 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2785 sctx->framebuffer.CB_has_shader_readable_metadata);
2786
2787 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2788
2789 /* u_blitter doesn't invoke depth decompression when it does multiple
2790 * blits in a row, but the only case when it matters for DB is when
2791 * doing generate_mipmap. So here we flush DB manually between
2792 * individual generate_mipmap blits.
2793 * Note that lower mipmap levels aren't compressed.
2794 */
2795 if (sctx->generate_mipmap_for_depth) {
2796 si_make_DB_shader_coherent(sctx, 1, false,
2797 sctx->framebuffer.DB_has_shader_readable_metadata);
2798 } else if (sctx->b.chip_class == GFX9) {
2799 /* It appears that DB metadata "leaks" in a sequence of:
2800 * - depth clear
2801 * - DCC decompress for shader image writes (with DB disabled)
2802 * - render with DEPTH_BEFORE_SHADER=1
2803 * Flushing DB metadata works around the problem.
2804 */
2805 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2806 }
2807
2808 /* Take the maximum of the old and new count. If the new count is lower,
2809 * dirtying is needed to disable the unbound colorbuffers.
2810 */
2811 sctx->framebuffer.dirty_cbufs |=
2812 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2813 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2814
2815 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2816 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2817
2818 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2819 sctx->framebuffer.spi_shader_col_format = 0;
2820 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2821 sctx->framebuffer.spi_shader_col_format_blend = 0;
2822 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2823 sctx->framebuffer.color_is_int8 = 0;
2824 sctx->framebuffer.color_is_int10 = 0;
2825
2826 sctx->framebuffer.compressed_cb_mask = 0;
2827 sctx->framebuffer.uncompressed_cb_mask = 0;
2828 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2829 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2830 sctx->framebuffer.any_dst_linear = false;
2831 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2832 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2833
2834 for (i = 0; i < state->nr_cbufs; i++) {
2835 if (!state->cbufs[i])
2836 continue;
2837
2838 surf = (struct r600_surface*)state->cbufs[i];
2839 rtex = (struct r600_texture*)surf->base.texture;
2840
2841 if (!surf->color_initialized) {
2842 si_initialize_color_surface(sctx, surf);
2843 }
2844
2845 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2846 sctx->framebuffer.spi_shader_col_format |=
2847 surf->spi_shader_col_format << (i * 4);
2848 sctx->framebuffer.spi_shader_col_format_alpha |=
2849 surf->spi_shader_col_format_alpha << (i * 4);
2850 sctx->framebuffer.spi_shader_col_format_blend |=
2851 surf->spi_shader_col_format_blend << (i * 4);
2852 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2853 surf->spi_shader_col_format_blend_alpha << (i * 4);
2854
2855 if (surf->color_is_int8)
2856 sctx->framebuffer.color_is_int8 |= 1 << i;
2857 if (surf->color_is_int10)
2858 sctx->framebuffer.color_is_int10 |= 1 << i;
2859
2860 if (rtex->fmask.size)
2861 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2862 else
2863 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2864
2865 if (rtex->surface.is_linear)
2866 sctx->framebuffer.any_dst_linear = true;
2867
2868 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2869 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2870
2871 si_context_add_resource_size(sctx, surf->base.texture);
2872
2873 p_atomic_inc(&rtex->framebuffers_bound);
2874
2875 if (rtex->dcc_gather_statistics) {
2876 /* Dirty tracking must be enabled for DCC usage analysis. */
2877 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2878 vi_separate_dcc_start_query(sctx, rtex);
2879 }
2880 }
2881
2882 struct r600_texture *zstex = NULL;
2883
2884 if (state->zsbuf) {
2885 surf = (struct r600_surface*)state->zsbuf;
2886 zstex = (struct r600_texture*)surf->base.texture;
2887
2888 if (!surf->depth_initialized) {
2889 si_init_depth_surface(sctx, surf);
2890 }
2891
2892 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2893 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2894
2895 si_context_add_resource_size(sctx, surf->base.texture);
2896 }
2897
2898 si_update_ps_colorbuf0_slot(sctx);
2899 si_update_poly_offset_state(sctx);
2900 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2901 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2902
2903 if (sctx->screen->dpbb_allowed)
2904 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2905
2906 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2907 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2908
2909 if (sctx->screen->has_out_of_order_rast &&
2910 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2911 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2912 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2913 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2914
2915 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2916 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2917 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2918
2919 /* Set sample locations as fragment shader constants. */
2920 switch (sctx->framebuffer.nr_samples) {
2921 case 1:
2922 constbuf.user_buffer = sctx->sample_locations_1x;
2923 break;
2924 case 2:
2925 constbuf.user_buffer = sctx->sample_locations_2x;
2926 break;
2927 case 4:
2928 constbuf.user_buffer = sctx->sample_locations_4x;
2929 break;
2930 case 8:
2931 constbuf.user_buffer = sctx->sample_locations_8x;
2932 break;
2933 case 16:
2934 constbuf.user_buffer = sctx->sample_locations_16x;
2935 break;
2936 default:
2937 R600_ERR("Requested an invalid number of samples %i.\n",
2938 sctx->framebuffer.nr_samples);
2939 assert(0);
2940 }
2941 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2942 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2943
2944 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2945 }
2946
2947 sctx->do_update_shaders = true;
2948
2949 if (!sctx->decompression_enabled) {
2950 /* Prevent textures decompression when the framebuffer state
2951 * changes come from the decompression passes themselves.
2952 */
2953 sctx->need_check_render_feedback = true;
2954 }
2955 }
2956
2957 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2958 {
2959 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
2960 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2961 unsigned i, nr_cbufs = state->nr_cbufs;
2962 struct r600_texture *tex = NULL;
2963 struct r600_surface *cb = NULL;
2964 unsigned cb_color_info = 0;
2965
2966 /* Colorbuffers. */
2967 for (i = 0; i < nr_cbufs; i++) {
2968 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2969 unsigned cb_color_attrib;
2970
2971 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2972 continue;
2973
2974 cb = (struct r600_surface*)state->cbufs[i];
2975 if (!cb) {
2976 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2977 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2978 continue;
2979 }
2980
2981 tex = (struct r600_texture *)cb->base.texture;
2982 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
2983 &tex->resource, RADEON_USAGE_READWRITE,
2984 tex->resource.b.b.nr_samples > 1 ?
2985 RADEON_PRIO_COLOR_BUFFER_MSAA :
2986 RADEON_PRIO_COLOR_BUFFER);
2987
2988 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2989 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
2990 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2991 RADEON_PRIO_CMASK);
2992 }
2993
2994 if (tex->dcc_separate_buffer)
2995 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
2996 tex->dcc_separate_buffer,
2997 RADEON_USAGE_READWRITE,
2998 RADEON_PRIO_DCC);
2999
3000 /* Compute mutable surface parameters. */
3001 cb_color_base = tex->resource.gpu_address >> 8;
3002 cb_color_fmask = 0;
3003 cb_dcc_base = 0;
3004 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3005 cb_color_attrib = cb->cb_color_attrib;
3006
3007 if (tex->fmask.size) {
3008 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
3009 cb_color_fmask |= tex->fmask.tile_swizzle;
3010 }
3011
3012 /* Set up DCC. */
3013 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3014 bool is_msaa_resolve_dst = state->cbufs[0] &&
3015 state->cbufs[0]->texture->nr_samples > 1 &&
3016 state->cbufs[1] == &cb->base &&
3017 state->cbufs[1]->texture->nr_samples <= 1;
3018
3019 if (!is_msaa_resolve_dst)
3020 cb_color_info |= S_028C70_DCC_ENABLE(1);
3021
3022 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3023 tex->dcc_offset) >> 8;
3024 cb_dcc_base |= tex->surface.tile_swizzle;
3025 }
3026
3027 if (sctx->b.chip_class >= GFX9) {
3028 struct gfx9_surf_meta_flags meta;
3029
3030 if (tex->dcc_offset)
3031 meta = tex->surface.u.gfx9.dcc;
3032 else
3033 meta = tex->surface.u.gfx9.cmask;
3034
3035 /* Set mutable surface parameters. */
3036 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3037 cb_color_base |= tex->surface.tile_swizzle;
3038 if (!tex->fmask.size)
3039 cb_color_fmask = cb_color_base;
3040 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3041 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3042 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3043 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3044
3045 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3046 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3047 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3048 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3049 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3050 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3051 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3052 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3053 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3054 radeon_emit(cs, S_028C80_BASE_256B(tex->cmask.base_address_reg >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3055 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3056 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3057 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3058 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3059 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3060 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3061
3062 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3063 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3064 } else {
3065 /* Compute mutable surface parameters (SI-CI-VI). */
3066 const struct legacy_surf_level *level_info =
3067 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3068 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3069 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3070
3071 cb_color_base += level_info->offset >> 8;
3072 /* Only macrotiled modes can set tile swizzle. */
3073 if (level_info->mode == RADEON_SURF_MODE_2D)
3074 cb_color_base |= tex->surface.tile_swizzle;
3075
3076 if (!tex->fmask.size)
3077 cb_color_fmask = cb_color_base;
3078 if (cb_dcc_base)
3079 cb_dcc_base += level_info->dcc_offset >> 8;
3080
3081 pitch_tile_max = level_info->nblk_x / 8 - 1;
3082 slice_tile_max = level_info->nblk_x *
3083 level_info->nblk_y / 64 - 1;
3084 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3085
3086 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3087 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3088 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3089
3090 if (tex->fmask.size) {
3091 if (sctx->b.chip_class >= CIK)
3092 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3093 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3094 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3095 } else {
3096 /* This must be set for fast clear to work without FMASK. */
3097 if (sctx->b.chip_class >= CIK)
3098 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3099 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3100 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3101 }
3102
3103 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3104 sctx->b.chip_class >= VI ? 14 : 13);
3105 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3106 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3107 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3108 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3109 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3110 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3111 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3112 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3113 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3114 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3115 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3116 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3117 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3118
3119 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3120 radeon_emit(cs, cb_dcc_base);
3121 }
3122 }
3123 for (; i < 8 ; i++)
3124 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3125 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3126
3127 /* ZS buffer. */
3128 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3129 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3130 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3131
3132 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
3133 &rtex->resource, RADEON_USAGE_READWRITE,
3134 zb->base.texture->nr_samples > 1 ?
3135 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3136 RADEON_PRIO_DEPTH_BUFFER);
3137
3138 if (sctx->b.chip_class >= GFX9) {
3139 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3140 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3141 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3142 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3143
3144 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3145 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3146 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3147 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3148 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3149 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3150 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3151 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3152 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3153 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3154 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3155 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3156
3157 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3158 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3159 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3160 } else {
3161 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3162
3163 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3164 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3165 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3166 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3167 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3168 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3169 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3170 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3171 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3172 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3173 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3174 }
3175
3176 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3177 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3178 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3179
3180 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3181 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3182 } else if (sctx->framebuffer.dirty_zsbuf) {
3183 if (sctx->b.chip_class >= GFX9)
3184 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3185 else
3186 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3187
3188 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3189 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3190 }
3191
3192 /* Framebuffer dimensions. */
3193 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3194 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3195 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3196
3197 if (sctx->screen->dfsm_allowed) {
3198 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3199 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3200 }
3201
3202 sctx->framebuffer.dirty_cbufs = 0;
3203 sctx->framebuffer.dirty_zsbuf = false;
3204 }
3205
3206 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3207 struct r600_atom *atom)
3208 {
3209 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
3210 unsigned nr_samples = sctx->framebuffer.nr_samples;
3211 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3212
3213 /* Smoothing (only possible with nr_samples == 1) uses the same
3214 * sample locations as the MSAA it simulates.
3215 */
3216 if (nr_samples <= 1 && sctx->smoothing_enabled)
3217 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3218
3219 /* On Polaris, the small primitive filter uses the sample locations
3220 * even when MSAA is off, so we need to make sure they're set to 0.
3221 */
3222 if (has_msaa_sample_loc_bug)
3223 nr_samples = MAX2(nr_samples, 1);
3224
3225 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3226 sctx->msaa_sample_locs.nr_samples = nr_samples;
3227 si_emit_sample_locations(cs, nr_samples);
3228 }
3229
3230 if (sctx->b.family >= CHIP_POLARIS10) {
3231 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3232 unsigned small_prim_filter_cntl =
3233 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3234 /* line bug */
3235 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3236
3237 /* The alternative of setting sample locations to 0 would
3238 * require a DB flush to avoid Z errors, see
3239 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3240 */
3241 if (has_msaa_sample_loc_bug &&
3242 sctx->framebuffer.nr_samples > 1 &&
3243 rs && !rs->multisample_enable)
3244 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3245
3246 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3247 small_prim_filter_cntl);
3248 }
3249 }
3250
3251 static bool si_out_of_order_rasterization(struct si_context *sctx)
3252 {
3253 struct si_state_blend *blend = sctx->queued.named.blend;
3254 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3255
3256 if (!sctx->screen->has_out_of_order_rast)
3257 return false;
3258
3259 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3260
3261 if (blend) {
3262 colormask &= blend->cb_target_enabled_4bit;
3263 } else {
3264 colormask = 0;
3265 }
3266
3267 /* Conservative: No logic op. */
3268 if (colormask && blend->logicop_enable)
3269 return false;
3270
3271 struct si_dsa_order_invariance dsa_order_invariant = {
3272 .zs = true, .pass_set = true, .pass_last = false
3273 };
3274
3275 if (sctx->framebuffer.state.zsbuf) {
3276 struct r600_texture *zstex =
3277 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3278 bool has_stencil = zstex->surface.has_stencil;
3279 dsa_order_invariant = dsa->order_invariance[has_stencil];
3280 if (!dsa_order_invariant.zs)
3281 return false;
3282
3283 /* The set of PS invocations is always order invariant,
3284 * except when early Z/S tests are requested. */
3285 if (sctx->ps_shader.cso &&
3286 sctx->ps_shader.cso->info.writes_memory &&
3287 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3288 !dsa_order_invariant.pass_set)
3289 return false;
3290
3291 if (sctx->b.num_perfect_occlusion_queries != 0 &&
3292 !dsa_order_invariant.pass_set)
3293 return false;
3294 }
3295
3296 if (!colormask)
3297 return true;
3298
3299 unsigned blendmask = colormask & blend->blend_enable_4bit;
3300
3301 if (blendmask) {
3302 /* Only commutative blending. */
3303 if (blendmask & ~blend->commutative_4bit)
3304 return false;
3305
3306 if (!dsa_order_invariant.pass_set)
3307 return false;
3308 }
3309
3310 if (colormask & ~blendmask) {
3311 if (!dsa_order_invariant.pass_last)
3312 return false;
3313 }
3314
3315 return true;
3316 }
3317
3318 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3319 {
3320 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
3321 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3322 /* 33% faster rendering to linear color buffers */
3323 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3324 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3325 unsigned sc_mode_cntl_1 =
3326 S_028A4C_WALK_SIZE(dst_is_linear) |
3327 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3328 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3329 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3330 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3331 /* always 1: */
3332 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3333 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3334 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3335 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3336 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3337 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3338
3339 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3340 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3341
3342 /* Required by OpenGL line rasterization.
3343 *
3344 * TODO: We should also enable perpendicular endcaps for AA lines,
3345 * but that requires implementing line stippling in the pixel
3346 * shader. SC can only do line stippling with axis-aligned
3347 * endcaps.
3348 */
3349 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3350
3351 if (setup_samples > 1) {
3352 /* distance from the pixel center, indexed by log2(nr_samples) */
3353 static unsigned max_dist[] = {
3354 0, /* unused */
3355 4, /* 2x MSAA */
3356 6, /* 4x MSAA */
3357 7, /* 8x MSAA */
3358 8, /* 16x MSAA */
3359 };
3360 unsigned log_samples = util_logbase2(setup_samples);
3361 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3362 unsigned log_ps_iter_samples =
3363 util_logbase2(util_next_power_of_two(ps_iter_samples));
3364
3365 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3366 radeon_emit(cs, sc_line_cntl |
3367 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3368 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3369 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3370 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3371
3372 if (sctx->framebuffer.nr_samples > 1) {
3373 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3374 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3375 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3376 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3377 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3378 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3379 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3380 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3381 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3382 sc_mode_cntl_1);
3383 } else if (sctx->smoothing_enabled) {
3384 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3385 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3386 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3387 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3388 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3389 sc_mode_cntl_1);
3390 }
3391 } else {
3392 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3393 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3394 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3395
3396 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3397 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3398 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3399 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3400 sc_mode_cntl_1);
3401 }
3402
3403 /* GFX9: Flush DFSM when the AA mode changes. */
3404 if (sctx->screen->dfsm_allowed) {
3405 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3406 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3407 }
3408 }
3409
3410 void si_update_ps_iter_samples(struct si_context *sctx)
3411 {
3412 if (sctx->framebuffer.nr_samples > 1)
3413 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3414 if (sctx->screen->dpbb_allowed)
3415 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3416 }
3417
3418 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3419 {
3420 struct si_context *sctx = (struct si_context *)ctx;
3421
3422 if (sctx->ps_iter_samples == min_samples)
3423 return;
3424
3425 sctx->ps_iter_samples = min_samples;
3426 sctx->do_update_shaders = true;
3427
3428 si_update_ps_iter_samples(sctx);
3429 }
3430
3431 /*
3432 * Samplers
3433 */
3434
3435 /**
3436 * Build the sampler view descriptor for a buffer texture.
3437 * @param state 256-bit descriptor; only the high 128 bits are filled in
3438 */
3439 void
3440 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3441 enum pipe_format format,
3442 unsigned offset, unsigned size,
3443 uint32_t *state)
3444 {
3445 const struct util_format_description *desc;
3446 int first_non_void;
3447 unsigned stride;
3448 unsigned num_records;
3449 unsigned num_format, data_format;
3450
3451 desc = util_format_description(format);
3452 first_non_void = util_format_get_first_non_void_channel(format);
3453 stride = desc->block.bits / 8;
3454 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3455 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3456
3457 num_records = size / stride;
3458 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3459
3460 /* The NUM_RECORDS field has a different meaning depending on the chip,
3461 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3462 *
3463 * SI-CIK:
3464 * - If STRIDE == 0, it's in byte units.
3465 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3466 *
3467 * VI:
3468 * - For SMEM and STRIDE == 0, it's in byte units.
3469 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3470 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3471 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3472 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3473 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3474 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3475 * That way the same descriptor can be used by both SMEM and VMEM.
3476 *
3477 * GFX9:
3478 * - For SMEM and STRIDE == 0, it's in byte units.
3479 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3480 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3481 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3482 */
3483 if (screen->info.chip_class >= GFX9)
3484 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3485 * from STRIDE to bytes. This works around it by setting
3486 * NUM_RECORDS to at least the size of one element, so that
3487 * the first element is readable when IDXEN == 0.
3488 *
3489 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3490 * IDXEN is enforced?
3491 */
3492 num_records = num_records ? MAX2(num_records, stride) : 0;
3493 else if (screen->info.chip_class == VI)
3494 num_records *= stride;
3495
3496 state[4] = 0;
3497 state[5] = S_008F04_STRIDE(stride);
3498 state[6] = num_records;
3499 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3500 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3501 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3502 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3503 S_008F0C_NUM_FORMAT(num_format) |
3504 S_008F0C_DATA_FORMAT(data_format);
3505 }
3506
3507 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3508 {
3509 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3510
3511 if (swizzle[3] == PIPE_SWIZZLE_X) {
3512 /* For the pre-defined border color values (white, opaque
3513 * black, transparent black), the only thing that matters is
3514 * that the alpha channel winds up in the correct place
3515 * (because the RGB channels are all the same) so either of
3516 * these enumerations will work.
3517 */
3518 if (swizzle[2] == PIPE_SWIZZLE_Y)
3519 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3520 else
3521 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3522 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3523 if (swizzle[1] == PIPE_SWIZZLE_Y)
3524 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3525 else
3526 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3527 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3528 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3529 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3530 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3531 }
3532
3533 return bc_swizzle;
3534 }
3535
3536 /**
3537 * Build the sampler view descriptor for a texture.
3538 */
3539 void
3540 si_make_texture_descriptor(struct si_screen *screen,
3541 struct r600_texture *tex,
3542 bool sampler,
3543 enum pipe_texture_target target,
3544 enum pipe_format pipe_format,
3545 const unsigned char state_swizzle[4],
3546 unsigned first_level, unsigned last_level,
3547 unsigned first_layer, unsigned last_layer,
3548 unsigned width, unsigned height, unsigned depth,
3549 uint32_t *state,
3550 uint32_t *fmask_state)
3551 {
3552 struct pipe_resource *res = &tex->resource.b.b;
3553 const struct util_format_description *desc;
3554 unsigned char swizzle[4];
3555 int first_non_void;
3556 unsigned num_format, data_format, type;
3557 uint64_t va;
3558
3559 desc = util_format_description(pipe_format);
3560
3561 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3562 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3563 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3564 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3565
3566 switch (pipe_format) {
3567 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3568 case PIPE_FORMAT_X32_S8X24_UINT:
3569 case PIPE_FORMAT_X8Z24_UNORM:
3570 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3571 break;
3572 case PIPE_FORMAT_X24S8_UINT:
3573 /*
3574 * X24S8 is implemented as an 8_8_8_8 data format, to
3575 * fix texture gathers. This affects at least
3576 * GL45-CTS.texture_cube_map_array.sampling on VI.
3577 */
3578 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3579 break;
3580 default:
3581 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3582 }
3583 } else {
3584 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3585 }
3586
3587 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3588
3589 switch (pipe_format) {
3590 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3591 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3592 break;
3593 default:
3594 if (first_non_void < 0) {
3595 if (util_format_is_compressed(pipe_format)) {
3596 switch (pipe_format) {
3597 case PIPE_FORMAT_DXT1_SRGB:
3598 case PIPE_FORMAT_DXT1_SRGBA:
3599 case PIPE_FORMAT_DXT3_SRGBA:
3600 case PIPE_FORMAT_DXT5_SRGBA:
3601 case PIPE_FORMAT_BPTC_SRGBA:
3602 case PIPE_FORMAT_ETC2_SRGB8:
3603 case PIPE_FORMAT_ETC2_SRGB8A1:
3604 case PIPE_FORMAT_ETC2_SRGBA8:
3605 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3606 break;
3607 case PIPE_FORMAT_RGTC1_SNORM:
3608 case PIPE_FORMAT_LATC1_SNORM:
3609 case PIPE_FORMAT_RGTC2_SNORM:
3610 case PIPE_FORMAT_LATC2_SNORM:
3611 case PIPE_FORMAT_ETC2_R11_SNORM:
3612 case PIPE_FORMAT_ETC2_RG11_SNORM:
3613 /* implies float, so use SNORM/UNORM to determine
3614 whether data is signed or not */
3615 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3616 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3617 break;
3618 default:
3619 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3620 break;
3621 }
3622 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3623 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3624 } else {
3625 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3626 }
3627 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3628 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3629 } else {
3630 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3631
3632 switch (desc->channel[first_non_void].type) {
3633 case UTIL_FORMAT_TYPE_FLOAT:
3634 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3635 break;
3636 case UTIL_FORMAT_TYPE_SIGNED:
3637 if (desc->channel[first_non_void].normalized)
3638 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3639 else if (desc->channel[first_non_void].pure_integer)
3640 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3641 else
3642 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3643 break;
3644 case UTIL_FORMAT_TYPE_UNSIGNED:
3645 if (desc->channel[first_non_void].normalized)
3646 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3647 else if (desc->channel[first_non_void].pure_integer)
3648 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3649 else
3650 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3651 }
3652 }
3653 }
3654
3655 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3656 if (data_format == ~0) {
3657 data_format = 0;
3658 }
3659
3660 /* S8 with Z32 HTILE needs a special format. */
3661 if (screen->info.chip_class >= GFX9 &&
3662 pipe_format == PIPE_FORMAT_S8_UINT &&
3663 tex->tc_compatible_htile)
3664 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3665
3666 if (!sampler &&
3667 (res->target == PIPE_TEXTURE_CUBE ||
3668 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3669 (screen->info.chip_class <= VI &&
3670 res->target == PIPE_TEXTURE_3D))) {
3671 /* For the purpose of shader images, treat cube maps and 3D
3672 * textures as 2D arrays. For 3D textures, the address
3673 * calculations for mipmaps are different, so we rely on the
3674 * caller to effectively disable mipmaps.
3675 */
3676 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3677
3678 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3679 } else {
3680 type = si_tex_dim(screen, tex, target, res->nr_samples);
3681 }
3682
3683 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3684 height = 1;
3685 depth = res->array_size;
3686 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3687 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3688 if (sampler || res->target != PIPE_TEXTURE_3D)
3689 depth = res->array_size;
3690 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3691 depth = res->array_size / 6;
3692
3693 state[0] = 0;
3694 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3695 S_008F14_NUM_FORMAT_GFX6(num_format));
3696 state[2] = (S_008F18_WIDTH(width - 1) |
3697 S_008F18_HEIGHT(height - 1) |
3698 S_008F18_PERF_MOD(4));
3699 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3700 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3701 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3702 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3703 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3704 0 : first_level) |
3705 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3706 util_logbase2(res->nr_samples) :
3707 last_level) |
3708 S_008F1C_TYPE(type));
3709 state[4] = 0;
3710 state[5] = S_008F24_BASE_ARRAY(first_layer);
3711 state[6] = 0;
3712 state[7] = 0;
3713
3714 if (screen->info.chip_class >= GFX9) {
3715 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3716
3717 /* Depth is the the last accessible layer on Gfx9.
3718 * The hw doesn't need to know the total number of layers.
3719 */
3720 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3721 state[4] |= S_008F20_DEPTH(depth - 1);
3722 else
3723 state[4] |= S_008F20_DEPTH(last_layer);
3724
3725 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3726 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3727 util_logbase2(res->nr_samples) :
3728 tex->resource.b.b.last_level);
3729 } else {
3730 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3731 state[4] |= S_008F20_DEPTH(depth - 1);
3732 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3733 }
3734
3735 if (tex->dcc_offset) {
3736 unsigned swap = si_translate_colorswap(pipe_format, false);
3737
3738 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3739 } else {
3740 /* The last dword is unused by hw. The shader uses it to clear
3741 * bits in the first dword of sampler state.
3742 */
3743 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3744 if (first_level == last_level)
3745 state[7] = C_008F30_MAX_ANISO_RATIO;
3746 else
3747 state[7] = 0xffffffff;
3748 }
3749 }
3750
3751 /* Initialize the sampler view for FMASK. */
3752 if (tex->fmask.size) {
3753 uint32_t data_format, num_format;
3754
3755 va = tex->resource.gpu_address + tex->fmask.offset;
3756
3757 if (screen->info.chip_class >= GFX9) {
3758 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3759 switch (res->nr_samples) {
3760 case 2:
3761 num_format = V_008F14_IMG_FMASK_8_2_2;
3762 break;
3763 case 4:
3764 num_format = V_008F14_IMG_FMASK_8_4_4;
3765 break;
3766 case 8:
3767 num_format = V_008F14_IMG_FMASK_32_8_8;
3768 break;
3769 default:
3770 unreachable("invalid nr_samples");
3771 }
3772 } else {
3773 switch (res->nr_samples) {
3774 case 2:
3775 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3776 break;
3777 case 4:
3778 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3779 break;
3780 case 8:
3781 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3782 break;
3783 default:
3784 unreachable("invalid nr_samples");
3785 }
3786 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3787 }
3788
3789 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3790 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3791 S_008F14_DATA_FORMAT_GFX6(data_format) |
3792 S_008F14_NUM_FORMAT_GFX6(num_format);
3793 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3794 S_008F18_HEIGHT(height - 1);
3795 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3796 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3797 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3798 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3799 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3800 fmask_state[4] = 0;
3801 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3802 fmask_state[6] = 0;
3803 fmask_state[7] = 0;
3804
3805 if (screen->info.chip_class >= GFX9) {
3806 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3807 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3808 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3809 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3810 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3811 } else {
3812 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3813 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3814 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3815 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3816 }
3817 }
3818 }
3819
3820 /**
3821 * Create a sampler view.
3822 *
3823 * @param ctx context
3824 * @param texture texture
3825 * @param state sampler view template
3826 * @param width0 width0 override (for compressed textures as int)
3827 * @param height0 height0 override (for compressed textures as int)
3828 * @param force_level set the base address to the level (for compressed textures)
3829 */
3830 struct pipe_sampler_view *
3831 si_create_sampler_view_custom(struct pipe_context *ctx,
3832 struct pipe_resource *texture,
3833 const struct pipe_sampler_view *state,
3834 unsigned width0, unsigned height0,
3835 unsigned force_level)
3836 {
3837 struct si_context *sctx = (struct si_context*)ctx;
3838 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3839 struct r600_texture *tmp = (struct r600_texture*)texture;
3840 unsigned base_level, first_level, last_level;
3841 unsigned char state_swizzle[4];
3842 unsigned height, depth, width;
3843 unsigned last_layer = state->u.tex.last_layer;
3844 enum pipe_format pipe_format;
3845 const struct legacy_surf_level *surflevel;
3846
3847 if (!view)
3848 return NULL;
3849
3850 /* initialize base object */
3851 view->base = *state;
3852 view->base.texture = NULL;
3853 view->base.reference.count = 1;
3854 view->base.context = ctx;
3855
3856 assert(texture);
3857 pipe_resource_reference(&view->base.texture, texture);
3858
3859 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3860 state->format == PIPE_FORMAT_S8X24_UINT ||
3861 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3862 state->format == PIPE_FORMAT_S8_UINT)
3863 view->is_stencil_sampler = true;
3864
3865 /* Buffer resource. */
3866 if (texture->target == PIPE_BUFFER) {
3867 si_make_buffer_descriptor(sctx->screen,
3868 (struct r600_resource *)texture,
3869 state->format,
3870 state->u.buf.offset,
3871 state->u.buf.size,
3872 view->state);
3873 return &view->base;
3874 }
3875
3876 state_swizzle[0] = state->swizzle_r;
3877 state_swizzle[1] = state->swizzle_g;
3878 state_swizzle[2] = state->swizzle_b;
3879 state_swizzle[3] = state->swizzle_a;
3880
3881 base_level = 0;
3882 first_level = state->u.tex.first_level;
3883 last_level = state->u.tex.last_level;
3884 width = width0;
3885 height = height0;
3886 depth = texture->depth0;
3887
3888 if (sctx->b.chip_class <= VI && force_level) {
3889 assert(force_level == first_level &&
3890 force_level == last_level);
3891 base_level = force_level;
3892 first_level = 0;
3893 last_level = 0;
3894 width = u_minify(width, force_level);
3895 height = u_minify(height, force_level);
3896 depth = u_minify(depth, force_level);
3897 }
3898
3899 /* This is not needed if state trackers set last_layer correctly. */
3900 if (state->target == PIPE_TEXTURE_1D ||
3901 state->target == PIPE_TEXTURE_2D ||
3902 state->target == PIPE_TEXTURE_RECT ||
3903 state->target == PIPE_TEXTURE_CUBE)
3904 last_layer = state->u.tex.first_layer;
3905
3906 /* Texturing with separate depth and stencil. */
3907 pipe_format = state->format;
3908
3909 /* Depth/stencil texturing sometimes needs separate texture. */
3910 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
3911 if (!tmp->flushed_depth_texture &&
3912 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3913 pipe_resource_reference(&view->base.texture, NULL);
3914 FREE(view);
3915 return NULL;
3916 }
3917
3918 assert(tmp->flushed_depth_texture);
3919
3920 /* Override format for the case where the flushed texture
3921 * contains only Z or only S.
3922 */
3923 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3924 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3925
3926 tmp = tmp->flushed_depth_texture;
3927 }
3928
3929 surflevel = tmp->surface.u.legacy.level;
3930
3931 if (tmp->db_compatible) {
3932 if (!view->is_stencil_sampler)
3933 pipe_format = tmp->db_render_format;
3934
3935 switch (pipe_format) {
3936 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3937 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3938 break;
3939 case PIPE_FORMAT_X8Z24_UNORM:
3940 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3941 /* Z24 is always stored like this for DB
3942 * compatibility.
3943 */
3944 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3945 break;
3946 case PIPE_FORMAT_X24S8_UINT:
3947 case PIPE_FORMAT_S8X24_UINT:
3948 case PIPE_FORMAT_X32_S8X24_UINT:
3949 pipe_format = PIPE_FORMAT_S8_UINT;
3950 surflevel = tmp->surface.u.legacy.stencil_level;
3951 break;
3952 default:;
3953 }
3954 }
3955
3956 view->dcc_incompatible =
3957 vi_dcc_formats_are_incompatible(texture,
3958 state->u.tex.first_level,
3959 state->format);
3960
3961 si_make_texture_descriptor(sctx->screen, tmp, true,
3962 state->target, pipe_format, state_swizzle,
3963 first_level, last_level,
3964 state->u.tex.first_layer, last_layer,
3965 width, height, depth,
3966 view->state, view->fmask_state);
3967
3968 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3969 view->is_integer =
3970 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3971 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3972 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3973 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3974 view->base_level_info = &surflevel[base_level];
3975 view->base_level = base_level;
3976 view->block_width = util_format_get_blockwidth(pipe_format);
3977 return &view->base;
3978 }
3979
3980 static struct pipe_sampler_view *
3981 si_create_sampler_view(struct pipe_context *ctx,
3982 struct pipe_resource *texture,
3983 const struct pipe_sampler_view *state)
3984 {
3985 return si_create_sampler_view_custom(ctx, texture, state,
3986 texture ? texture->width0 : 0,
3987 texture ? texture->height0 : 0, 0);
3988 }
3989
3990 static void si_sampler_view_destroy(struct pipe_context *ctx,
3991 struct pipe_sampler_view *state)
3992 {
3993 struct si_sampler_view *view = (struct si_sampler_view *)state;
3994
3995 pipe_resource_reference(&state->texture, NULL);
3996 FREE(view);
3997 }
3998
3999 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4000 {
4001 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4002 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4003 (linear_filter &&
4004 (wrap == PIPE_TEX_WRAP_CLAMP ||
4005 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4006 }
4007
4008 static uint32_t si_translate_border_color(struct si_context *sctx,
4009 const struct pipe_sampler_state *state,
4010 const union pipe_color_union *color,
4011 bool is_integer)
4012 {
4013 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4014 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4015
4016 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4017 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4018 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4019 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4020
4021 #define simple_border_types(elt) \
4022 do { \
4023 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4024 color->elt[2] == 0 && color->elt[3] == 0) \
4025 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4026 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4027 color->elt[2] == 0 && color->elt[3] == 1) \
4028 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4029 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4030 color->elt[2] == 1 && color->elt[3] == 1) \
4031 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4032 } while (false)
4033
4034 if (is_integer)
4035 simple_border_types(ui);
4036 else
4037 simple_border_types(f);
4038
4039 #undef simple_border_types
4040
4041 int i;
4042
4043 /* Check if the border has been uploaded already. */
4044 for (i = 0; i < sctx->border_color_count; i++)
4045 if (memcmp(&sctx->border_color_table[i], color,
4046 sizeof(*color)) == 0)
4047 break;
4048
4049 if (i >= SI_MAX_BORDER_COLORS) {
4050 /* Getting 4096 unique border colors is very unlikely. */
4051 fprintf(stderr, "radeonsi: The border color table is full. "
4052 "Any new border colors will be just black. "
4053 "Please file a bug.\n");
4054 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4055 }
4056
4057 if (i == sctx->border_color_count) {
4058 /* Upload a new border color. */
4059 memcpy(&sctx->border_color_table[i], color,
4060 sizeof(*color));
4061 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4062 color, sizeof(*color));
4063 sctx->border_color_count++;
4064 }
4065
4066 return S_008F3C_BORDER_COLOR_PTR(i) |
4067 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4068 }
4069
4070 static inline int S_FIXED(float value, unsigned frac_bits)
4071 {
4072 return value * (1 << frac_bits);
4073 }
4074
4075 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4076 {
4077 if (filter == PIPE_TEX_FILTER_LINEAR)
4078 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4079 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4080 else
4081 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4082 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4083 }
4084
4085 static inline unsigned si_tex_aniso_filter(unsigned filter)
4086 {
4087 if (filter < 2)
4088 return 0;
4089 if (filter < 4)
4090 return 1;
4091 if (filter < 8)
4092 return 2;
4093 if (filter < 16)
4094 return 3;
4095 return 4;
4096 }
4097
4098 static void *si_create_sampler_state(struct pipe_context *ctx,
4099 const struct pipe_sampler_state *state)
4100 {
4101 struct si_context *sctx = (struct si_context *)ctx;
4102 struct si_screen *sscreen = sctx->screen;
4103 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4104 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4105 : state->max_anisotropy;
4106 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4107 union pipe_color_union clamped_border_color;
4108
4109 if (!rstate) {
4110 return NULL;
4111 }
4112
4113 #ifdef DEBUG
4114 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4115 #endif
4116 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4117 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4118 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4119 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4120 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4121 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4122 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4123 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4124 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4125 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
4126 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4127 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4128 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4129 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4130 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4131 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4132 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4133 S_008F38_MIP_POINT_PRECLAMP(0) |
4134 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
4135 S_008F38_FILTER_PREC_FIX(1) |
4136 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
4137 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4138
4139 /* Create sampler resource for integer textures. */
4140 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4141 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4142
4143 /* Create sampler resource for upgraded depth textures. */
4144 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4145
4146 for (unsigned i = 0; i < 4; ++i) {
4147 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4148 * when the border color is 1.0. */
4149 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4150 }
4151
4152 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4153 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4154 else
4155 rstate->upgraded_depth_val[3] =
4156 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4157 S_008F3C_UPGRADED_DEPTH(1);
4158
4159 return rstate;
4160 }
4161
4162 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4163 {
4164 struct si_context *sctx = (struct si_context *)ctx;
4165
4166 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4167 return;
4168
4169 sctx->sample_mask.sample_mask = sample_mask;
4170 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4171 }
4172
4173 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4174 {
4175 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
4176 unsigned mask = sctx->sample_mask.sample_mask;
4177
4178 /* Needed for line and polygon smoothing as well as for the Polaris
4179 * small primitive filter. We expect the state tracker to take care of
4180 * this for us.
4181 */
4182 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4183 (mask & 1 && sctx->blitter->running));
4184
4185 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4186 radeon_emit(cs, mask | (mask << 16));
4187 radeon_emit(cs, mask | (mask << 16));
4188 }
4189
4190 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4191 {
4192 #ifdef DEBUG
4193 struct si_sampler_state *s = state;
4194
4195 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4196 s->magic = 0;
4197 #endif
4198 free(state);
4199 }
4200
4201 /*
4202 * Vertex elements & buffers
4203 */
4204
4205 static void *si_create_vertex_elements(struct pipe_context *ctx,
4206 unsigned count,
4207 const struct pipe_vertex_element *elements)
4208 {
4209 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4210 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4211 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4212 int i;
4213
4214 assert(count <= SI_MAX_ATTRIBS);
4215 if (!v)
4216 return NULL;
4217
4218 v->count = count;
4219 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4220
4221 for (i = 0; i < count; ++i) {
4222 const struct util_format_description *desc;
4223 const struct util_format_channel_description *channel;
4224 unsigned data_format, num_format;
4225 int first_non_void;
4226 unsigned vbo_index = elements[i].vertex_buffer_index;
4227 unsigned char swizzle[4];
4228
4229 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4230 FREE(v);
4231 return NULL;
4232 }
4233
4234 if (elements[i].instance_divisor) {
4235 v->uses_instance_divisors = true;
4236 v->instance_divisors[i] = elements[i].instance_divisor;
4237
4238 if (v->instance_divisors[i] == 1)
4239 v->instance_divisor_is_one |= 1u << i;
4240 else
4241 v->instance_divisor_is_fetched |= 1u << i;
4242 }
4243
4244 if (!used[vbo_index]) {
4245 v->first_vb_use_mask |= 1 << i;
4246 used[vbo_index] = true;
4247 }
4248
4249 desc = util_format_description(elements[i].src_format);
4250 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4251 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4252 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4253 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4254 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4255
4256 v->format_size[i] = desc->block.bits / 8;
4257 v->src_offset[i] = elements[i].src_offset;
4258 v->vertex_buffer_index[i] = vbo_index;
4259
4260 /* The hardware always treats the 2-bit alpha channel as
4261 * unsigned, so a shader workaround is needed. The affected
4262 * chips are VI and older except Stoney (GFX8.1).
4263 */
4264 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4265 sscreen->info.chip_class <= VI &&
4266 sscreen->info.family != CHIP_STONEY) {
4267 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4268 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4269 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4270 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4271 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4272 /* This isn't actually used in OpenGL. */
4273 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4274 }
4275 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4276 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4277 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4278 else
4279 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4280 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4281 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4282 if (channel->normalized) {
4283 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4284 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4285 else
4286 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4287 } else {
4288 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4289 }
4290 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4291 if (channel->normalized) {
4292 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4293 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4294 else
4295 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4296 } else {
4297 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4298 }
4299 }
4300 } else if (channel && channel->size == 64 &&
4301 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4302 switch (desc->nr_channels) {
4303 case 1:
4304 case 2:
4305 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4306 swizzle[0] = PIPE_SWIZZLE_X;
4307 swizzle[1] = PIPE_SWIZZLE_Y;
4308 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4309 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4310 break;
4311 case 3:
4312 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4313 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4314 swizzle[1] = PIPE_SWIZZLE_Y;
4315 swizzle[2] = PIPE_SWIZZLE_0;
4316 swizzle[3] = PIPE_SWIZZLE_0;
4317 break;
4318 case 4:
4319 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4320 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4321 swizzle[1] = PIPE_SWIZZLE_Y;
4322 swizzle[2] = PIPE_SWIZZLE_Z;
4323 swizzle[3] = PIPE_SWIZZLE_W;
4324 break;
4325 default:
4326 assert(0);
4327 }
4328 } else if (channel && desc->nr_channels == 3) {
4329 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4330
4331 if (channel->size == 8) {
4332 if (channel->pure_integer)
4333 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4334 else
4335 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4336 } else if (channel->size == 16) {
4337 if (channel->pure_integer)
4338 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4339 else
4340 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4341 }
4342 }
4343
4344 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4345 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4346 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4347 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4348 S_008F0C_NUM_FORMAT(num_format) |
4349 S_008F0C_DATA_FORMAT(data_format);
4350 }
4351 return v;
4352 }
4353
4354 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4355 {
4356 struct si_context *sctx = (struct si_context *)ctx;
4357 struct si_vertex_elements *old = sctx->vertex_elements;
4358 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4359
4360 sctx->vertex_elements = v;
4361 sctx->vertex_buffers_dirty = true;
4362
4363 if (v &&
4364 (!old ||
4365 old->count != v->count ||
4366 old->uses_instance_divisors != v->uses_instance_divisors ||
4367 v->uses_instance_divisors || /* we don't check which divisors changed */
4368 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4369 sctx->do_update_shaders = true;
4370
4371 if (v && v->instance_divisor_is_fetched) {
4372 struct pipe_constant_buffer cb;
4373
4374 cb.buffer = NULL;
4375 cb.user_buffer = v->instance_divisors;
4376 cb.buffer_offset = 0;
4377 cb.buffer_size = sizeof(uint32_t) * v->count;
4378 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4379 }
4380 }
4381
4382 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4383 {
4384 struct si_context *sctx = (struct si_context *)ctx;
4385
4386 if (sctx->vertex_elements == state)
4387 sctx->vertex_elements = NULL;
4388 FREE(state);
4389 }
4390
4391 static void si_set_vertex_buffers(struct pipe_context *ctx,
4392 unsigned start_slot, unsigned count,
4393 const struct pipe_vertex_buffer *buffers)
4394 {
4395 struct si_context *sctx = (struct si_context *)ctx;
4396 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4397 int i;
4398
4399 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4400
4401 if (buffers) {
4402 for (i = 0; i < count; i++) {
4403 const struct pipe_vertex_buffer *src = buffers + i;
4404 struct pipe_vertex_buffer *dsti = dst + i;
4405 struct pipe_resource *buf = src->buffer.resource;
4406
4407 pipe_resource_reference(&dsti->buffer.resource, buf);
4408 dsti->buffer_offset = src->buffer_offset;
4409 dsti->stride = src->stride;
4410 si_context_add_resource_size(sctx, buf);
4411 if (buf)
4412 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4413 }
4414 } else {
4415 for (i = 0; i < count; i++) {
4416 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4417 }
4418 }
4419 sctx->vertex_buffers_dirty = true;
4420 }
4421
4422 /*
4423 * Misc
4424 */
4425
4426 static void si_set_tess_state(struct pipe_context *ctx,
4427 const float default_outer_level[4],
4428 const float default_inner_level[2])
4429 {
4430 struct si_context *sctx = (struct si_context *)ctx;
4431 struct pipe_constant_buffer cb;
4432 float array[8];
4433
4434 memcpy(array, default_outer_level, sizeof(float) * 4);
4435 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4436
4437 cb.buffer = NULL;
4438 cb.user_buffer = NULL;
4439 cb.buffer_size = sizeof(array);
4440
4441 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4442 (void*)array, sizeof(array),
4443 &cb.buffer_offset);
4444
4445 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4446 pipe_resource_reference(&cb.buffer, NULL);
4447 }
4448
4449 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4450 {
4451 struct si_context *sctx = (struct si_context *)ctx;
4452
4453 si_update_fb_dirtiness_after_rendering(sctx);
4454
4455 /* Multisample surfaces are flushed in si_decompress_textures. */
4456 if (sctx->framebuffer.uncompressed_cb_mask)
4457 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4458 sctx->framebuffer.CB_has_shader_readable_metadata);
4459 }
4460
4461 /* This only ensures coherency for shader image/buffer stores. */
4462 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4463 {
4464 struct si_context *sctx = (struct si_context *)ctx;
4465
4466 /* Subsequent commands must wait for all shader invocations to
4467 * complete. */
4468 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4469 SI_CONTEXT_CS_PARTIAL_FLUSH;
4470
4471 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4472 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4473 SI_CONTEXT_INV_VMEM_L1;
4474
4475 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4476 PIPE_BARRIER_SHADER_BUFFER |
4477 PIPE_BARRIER_TEXTURE |
4478 PIPE_BARRIER_IMAGE |
4479 PIPE_BARRIER_STREAMOUT_BUFFER |
4480 PIPE_BARRIER_GLOBAL_BUFFER)) {
4481 /* As far as I can tell, L1 contents are written back to L2
4482 * automatically at end of shader, but the contents of other
4483 * L1 caches might still be stale. */
4484 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4485 }
4486
4487 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4488 /* Indices are read through TC L2 since VI.
4489 * L1 isn't used.
4490 */
4491 if (sctx->screen->info.chip_class <= CIK)
4492 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4493 }
4494
4495 /* MSAA color, any depth and any stencil are flushed in
4496 * si_decompress_textures when needed.
4497 */
4498 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4499 sctx->framebuffer.uncompressed_cb_mask) {
4500 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4501
4502 if (sctx->b.chip_class <= VI)
4503 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4504 }
4505
4506 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4507 if (sctx->screen->info.chip_class <= VI &&
4508 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4509 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4510 }
4511
4512 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4513 {
4514 struct pipe_blend_state blend;
4515
4516 memset(&blend, 0, sizeof(blend));
4517 blend.independent_blend_enable = true;
4518 blend.rt[0].colormask = 0xf;
4519 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4520 }
4521
4522 static void si_init_config(struct si_context *sctx);
4523
4524 void si_init_state_functions(struct si_context *sctx)
4525 {
4526 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4527 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4528 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4529 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4530 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4531
4532 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4533 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4534 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4535 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4536 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4537 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4538 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4539 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4540 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4541 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4542 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4543
4544 sctx->b.b.create_blend_state = si_create_blend_state;
4545 sctx->b.b.bind_blend_state = si_bind_blend_state;
4546 sctx->b.b.delete_blend_state = si_delete_blend_state;
4547 sctx->b.b.set_blend_color = si_set_blend_color;
4548
4549 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4550 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4551 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4552
4553 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4554 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4555 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4556
4557 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4558 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4559 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4560 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4561 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4562
4563 sctx->b.b.set_clip_state = si_set_clip_state;
4564 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4565
4566 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4567
4568 sctx->b.b.create_sampler_state = si_create_sampler_state;
4569 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4570
4571 sctx->b.b.create_sampler_view = si_create_sampler_view;
4572 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4573
4574 sctx->b.b.set_sample_mask = si_set_sample_mask;
4575
4576 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4577 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4578 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4579 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4580
4581 sctx->b.b.texture_barrier = si_texture_barrier;
4582 sctx->b.b.memory_barrier = si_memory_barrier;
4583 sctx->b.b.set_min_samples = si_set_min_samples;
4584 sctx->b.b.set_tess_state = si_set_tess_state;
4585
4586 sctx->b.b.set_active_query_state = si_set_active_query_state;
4587
4588 sctx->b.b.draw_vbo = si_draw_vbo;
4589
4590 si_init_config(sctx);
4591 }
4592
4593 void si_init_screen_state_functions(struct si_screen *sscreen)
4594 {
4595 sscreen->b.is_format_supported = si_is_format_supported;
4596 }
4597
4598 static void si_set_grbm_gfx_index(struct si_context *sctx,
4599 struct si_pm4_state *pm4, unsigned value)
4600 {
4601 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4602 R_00802C_GRBM_GFX_INDEX;
4603 si_pm4_set_reg(pm4, reg, value);
4604 }
4605
4606 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4607 struct si_pm4_state *pm4, unsigned se)
4608 {
4609 assert(se == ~0 || se < sctx->screen->info.max_se);
4610 si_set_grbm_gfx_index(sctx, pm4,
4611 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4612 S_030800_SE_INDEX(se)) |
4613 S_030800_SH_BROADCAST_WRITES(1) |
4614 S_030800_INSTANCE_BROADCAST_WRITES(1));
4615 }
4616
4617 static void
4618 si_write_harvested_raster_configs(struct si_context *sctx,
4619 struct si_pm4_state *pm4,
4620 unsigned raster_config,
4621 unsigned raster_config_1)
4622 {
4623 unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1);
4624 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4625 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4626 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4627 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4628 unsigned rb_per_se = num_rb / num_se;
4629 unsigned se_mask[4];
4630 unsigned se;
4631
4632 se_mask[0] = ((1 << rb_per_se) - 1);
4633 se_mask[1] = (se_mask[0] << rb_per_se);
4634 se_mask[2] = (se_mask[1] << rb_per_se);
4635 se_mask[3] = (se_mask[2] << rb_per_se);
4636
4637 se_mask[0] &= rb_mask;
4638 se_mask[1] &= rb_mask;
4639 se_mask[2] &= rb_mask;
4640 se_mask[3] &= rb_mask;
4641
4642 assert(num_se == 1 || num_se == 2 || num_se == 4);
4643 assert(sh_per_se == 1 || sh_per_se == 2);
4644 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4645
4646 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4647 * fields are for, so I'm leaving them as their default
4648 * values. */
4649
4650 for (se = 0; se < num_se; se++) {
4651 unsigned raster_config_se = raster_config;
4652 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4653 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4654 int idx = (se / 2) * 2;
4655
4656 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4657 raster_config_se &= C_028350_SE_MAP;
4658
4659 if (!se_mask[idx]) {
4660 raster_config_se |=
4661 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4662 } else {
4663 raster_config_se |=
4664 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4665 }
4666 }
4667
4668 pkr0_mask &= rb_mask;
4669 pkr1_mask &= rb_mask;
4670 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4671 raster_config_se &= C_028350_PKR_MAP;
4672
4673 if (!pkr0_mask) {
4674 raster_config_se |=
4675 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4676 } else {
4677 raster_config_se |=
4678 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4679 }
4680 }
4681
4682 if (rb_per_se >= 2) {
4683 unsigned rb0_mask = 1 << (se * rb_per_se);
4684 unsigned rb1_mask = rb0_mask << 1;
4685
4686 rb0_mask &= rb_mask;
4687 rb1_mask &= rb_mask;
4688 if (!rb0_mask || !rb1_mask) {
4689 raster_config_se &= C_028350_RB_MAP_PKR0;
4690
4691 if (!rb0_mask) {
4692 raster_config_se |=
4693 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4694 } else {
4695 raster_config_se |=
4696 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4697 }
4698 }
4699
4700 if (rb_per_se > 2) {
4701 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4702 rb1_mask = rb0_mask << 1;
4703 rb0_mask &= rb_mask;
4704 rb1_mask &= rb_mask;
4705 if (!rb0_mask || !rb1_mask) {
4706 raster_config_se &= C_028350_RB_MAP_PKR1;
4707
4708 if (!rb0_mask) {
4709 raster_config_se |=
4710 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4711 } else {
4712 raster_config_se |=
4713 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4714 }
4715 }
4716 }
4717 }
4718
4719 si_set_grbm_gfx_index_se(sctx, pm4, se);
4720 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4721 }
4722 si_set_grbm_gfx_index(sctx, pm4, ~0);
4723
4724 if (sctx->b.chip_class >= CIK) {
4725 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4726 (!se_mask[2] && !se_mask[3]))) {
4727 raster_config_1 &= C_028354_SE_PAIR_MAP;
4728
4729 if (!se_mask[0] && !se_mask[1]) {
4730 raster_config_1 |=
4731 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4732 } else {
4733 raster_config_1 |=
4734 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4735 }
4736 }
4737
4738 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4739 }
4740 }
4741
4742 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4743 {
4744 struct si_screen *sscreen = sctx->screen;
4745 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4746 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4747 unsigned raster_config, raster_config_1;
4748
4749 switch (sctx->b.family) {
4750 case CHIP_TAHITI:
4751 case CHIP_PITCAIRN:
4752 raster_config = 0x2a00126a;
4753 raster_config_1 = 0x00000000;
4754 break;
4755 case CHIP_VERDE:
4756 raster_config = 0x0000124a;
4757 raster_config_1 = 0x00000000;
4758 break;
4759 case CHIP_OLAND:
4760 raster_config = 0x00000082;
4761 raster_config_1 = 0x00000000;
4762 break;
4763 case CHIP_HAINAN:
4764 raster_config = 0x00000000;
4765 raster_config_1 = 0x00000000;
4766 break;
4767 case CHIP_BONAIRE:
4768 raster_config = 0x16000012;
4769 raster_config_1 = 0x00000000;
4770 break;
4771 case CHIP_HAWAII:
4772 raster_config = 0x3a00161a;
4773 raster_config_1 = 0x0000002e;
4774 break;
4775 case CHIP_FIJI:
4776 if (sscreen->info.cik_macrotile_mode_array[0] == 0x000000e8) {
4777 /* old kernels with old tiling config */
4778 raster_config = 0x16000012;
4779 raster_config_1 = 0x0000002a;
4780 } else {
4781 raster_config = 0x3a00161a;
4782 raster_config_1 = 0x0000002e;
4783 }
4784 break;
4785 case CHIP_POLARIS10:
4786 raster_config = 0x16000012;
4787 raster_config_1 = 0x0000002a;
4788 break;
4789 case CHIP_POLARIS11:
4790 case CHIP_POLARIS12:
4791 raster_config = 0x16000012;
4792 raster_config_1 = 0x00000000;
4793 break;
4794 case CHIP_TONGA:
4795 raster_config = 0x16000012;
4796 raster_config_1 = 0x0000002a;
4797 break;
4798 case CHIP_ICELAND:
4799 if (num_rb == 1)
4800 raster_config = 0x00000000;
4801 else
4802 raster_config = 0x00000002;
4803 raster_config_1 = 0x00000000;
4804 break;
4805 case CHIP_CARRIZO:
4806 raster_config = 0x00000002;
4807 raster_config_1 = 0x00000000;
4808 break;
4809 case CHIP_KAVERI:
4810 /* KV should be 0x00000002, but that causes problems with radeon */
4811 raster_config = 0x00000000; /* 0x00000002 */
4812 raster_config_1 = 0x00000000;
4813 break;
4814 case CHIP_KABINI:
4815 case CHIP_MULLINS:
4816 case CHIP_STONEY:
4817 raster_config = 0x00000000;
4818 raster_config_1 = 0x00000000;
4819 break;
4820 default:
4821 fprintf(stderr,
4822 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4823 raster_config = 0x00000000;
4824 raster_config_1 = 0x00000000;
4825 }
4826
4827 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4828 /* Always use the default config when all backends are enabled
4829 * (or when we failed to determine the enabled backends).
4830 */
4831 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4832 raster_config);
4833 if (sctx->b.chip_class >= CIK)
4834 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4835 raster_config_1);
4836 } else {
4837 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4838 }
4839 }
4840
4841 static void si_init_config(struct si_context *sctx)
4842 {
4843 struct si_screen *sscreen = sctx->screen;
4844 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4845 bool has_clear_state = sscreen->has_clear_state;
4846 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4847
4848 /* Only SI can disable CLEAR_STATE for now. */
4849 assert(has_clear_state || sscreen->info.chip_class == SI);
4850
4851 if (!pm4)
4852 return;
4853
4854 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4855 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4856 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4857 si_pm4_cmd_end(pm4, false);
4858
4859 if (has_clear_state) {
4860 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4861 si_pm4_cmd_add(pm4, 0);
4862 si_pm4_cmd_end(pm4, false);
4863 }
4864
4865 if (sctx->b.chip_class <= VI)
4866 si_set_raster_config(sctx, pm4);
4867
4868 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4869 if (!has_clear_state)
4870 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4871
4872 /* FIXME calculate these values somehow ??? */
4873 if (sctx->b.chip_class <= VI) {
4874 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4875 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4876 }
4877
4878 if (!has_clear_state) {
4879 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4880 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4881 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4882 }
4883
4884 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4885 if (!has_clear_state)
4886 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4887 if (sctx->b.chip_class < CIK)
4888 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4889 S_008A14_CLIP_VTX_REORDER_ENA(1));
4890
4891 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4892 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4893
4894 if (!has_clear_state)
4895 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4896
4897 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4898 * I don't know why. Deduced by trial and error.
4899 */
4900 if (sctx->b.chip_class <= CIK) {
4901 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4902 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4903 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4904 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4905 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4906 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4907 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4908 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4909 }
4910
4911 if (!has_clear_state) {
4912 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4913 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4914 S_028230_ER_TRI(0xA) |
4915 S_028230_ER_POINT(0xA) |
4916 S_028230_ER_RECT(0xA) |
4917 /* Required by DX10_DIAMOND_TEST_ENA: */
4918 S_028230_ER_LINE_LR(0x1A) |
4919 S_028230_ER_LINE_RL(0x26) |
4920 S_028230_ER_LINE_TB(0xA) |
4921 S_028230_ER_LINE_BT(0xA));
4922 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4923 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4924 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4925 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4926 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4927 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4928 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4929 }
4930
4931 if (sctx->b.chip_class >= GFX9) {
4932 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4933 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4934 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4935 } else {
4936 /* These registers, when written, also overwrite the CLEAR_STATE
4937 * context, so we can't rely on CLEAR_STATE setting them.
4938 * It would be an issue if there was another UMD changing them.
4939 */
4940 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4941 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4942 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4943 }
4944
4945 if (sctx->b.chip_class >= CIK) {
4946 if (sctx->b.chip_class >= GFX9) {
4947 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4948 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4949 } else {
4950 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4951 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4952 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4953 S_00B41C_WAVE_LIMIT(0x3F));
4954 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4955 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4956
4957 /* If this is 0, Bonaire can hang even if GS isn't being used.
4958 * Other chips are unaffected. These are suboptimal values,
4959 * but we don't use on-chip GS.
4960 */
4961 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4962 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4963 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4964 }
4965 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4966 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4967
4968 /* Compute LATE_ALLOC_VS.LIMIT. */
4969 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4970 (sscreen->info.max_se *
4971 sscreen->info.max_sh_per_se);
4972 unsigned late_alloc_limit; /* The limit is per SH. */
4973
4974 if (sctx->b.family == CHIP_KABINI) {
4975 late_alloc_limit = 0; /* Potential hang on Kabini. */
4976 } else if (num_cu_per_sh <= 4) {
4977 /* Too few available compute units per SH. Disallowing
4978 * VS to run on one CU could hurt us more than late VS
4979 * allocation would help.
4980 *
4981 * 2 is the highest safe number that allows us to keep
4982 * all CUs enabled.
4983 */
4984 late_alloc_limit = 2;
4985 } else {
4986 /* This is a good initial value, allowing 1 late_alloc
4987 * wave per SIMD on num_cu - 2.
4988 */
4989 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4990
4991 /* The limit is 0-based, so 0 means 1. */
4992 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4993 late_alloc_limit -= 1;
4994 }
4995
4996 /* VS can't execute on one CU if the limit is > 2. */
4997 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4998 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4999 S_00B118_WAVE_LIMIT(0x3F));
5000 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5001 S_00B11C_LIMIT(late_alloc_limit));
5002 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5003 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5004 }
5005
5006 if (sctx->b.chip_class >= VI) {
5007 unsigned vgt_tess_distribution;
5008
5009 vgt_tess_distribution =
5010 S_028B50_ACCUM_ISOLINE(32) |
5011 S_028B50_ACCUM_TRI(11) |
5012 S_028B50_ACCUM_QUAD(11) |
5013 S_028B50_DONUT_SPLIT(16);
5014
5015 /* Testing with Unigine Heaven extreme tesselation yielded best results
5016 * with TRAP_SPLIT = 3.
5017 */
5018 if (sctx->b.family == CHIP_FIJI ||
5019 sctx->b.family >= CHIP_POLARIS10)
5020 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5021
5022 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5023 } else if (!has_clear_state) {
5024 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5025 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5026 }
5027
5028 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5029 if (sctx->b.chip_class >= CIK) {
5030 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5031 S_028084_ADDRESS(border_color_va >> 40));
5032 }
5033 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5034 RADEON_PRIO_BORDER_COLORS);
5035
5036 if (sctx->b.chip_class >= GFX9) {
5037 unsigned num_se = sscreen->info.max_se;
5038 unsigned pc_lines = 0;
5039
5040 switch (sctx->b.family) {
5041 case CHIP_VEGA10:
5042 case CHIP_VEGA12:
5043 pc_lines = 4096;
5044 break;
5045 case CHIP_RAVEN:
5046 pc_lines = 1024;
5047 break;
5048 default:
5049 assert(0);
5050 }
5051
5052 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5053 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5054 S_028C48_MAX_PRIM_PER_BATCH(1023));
5055 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5056 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5057 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5058 }
5059
5060 si_pm4_upload_indirect_buffer(sctx, pm4);
5061 sctx->init_config = pm4;
5062 }