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radeonsi: use TC write-back instead of full cache invalidation
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
76 {
77 return value * (1 << frac_bits);
78 }
79
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x)
82 {
83 return x <= 0 ? 0 :
84 x >= 4096 ? 0xffff : x * 16;
85 }
86
87 /*
88 * Inferred framebuffer and blender state.
89 *
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
92 */
93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_state_blend *blend = sctx->queued.named.blend;
97 uint32_t cb_target_mask, i;
98
99 /* CB_COLORn_INFO.FORMAT=INVALID disables empty colorbuffer slots. */
100 if (blend)
101 cb_target_mask = blend->cb_target_mask;
102 else
103 cb_target_mask = 0xffffffff;
104
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
108 *
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
110 */
111 if (blend && blend->dual_src_blend &&
112 sctx->ps_shader.cso &&
113 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
114 cb_target_mask = 0;
115
116 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
117
118 /* STONEY-specific register settings. */
119 if (sctx->b.family == CHIP_STONEY) {
120 unsigned spi_shader_col_format =
121 sctx->ps_shader.cso ?
122 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
123 unsigned sx_ps_downconvert = 0;
124 unsigned sx_blend_opt_epsilon = 0;
125 unsigned sx_blend_opt_control = 0;
126
127 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
128 struct r600_surface *surf =
129 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf)
134 continue;
135
136 format = G_028C70_FORMAT(surf->cb_color_info);
137 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
138 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
139 colormask = (cb_target_mask >> (i * 4)) & 0xf;
140
141 /* Set if RGB and A are present. */
142 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
143
144 if (format == V_028C70_COLOR_8 ||
145 format == V_028C70_COLOR_16 ||
146 format == V_028C70_COLOR_32)
147 has_rgb = !has_alpha;
148 else
149 has_rgb = true;
150
151 /* Check the colormask and export format. */
152 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
153 has_rgb = false;
154 if (!(colormask & PIPE_MASK_A))
155 has_alpha = false;
156
157 if (spi_format == V_028714_SPI_SHADER_ZERO) {
158 has_rgb = false;
159 has_alpha = false;
160 }
161
162 /* Disable value checking for disabled channels. */
163 if (!has_rgb)
164 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
165 if (!has_alpha)
166 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
167
168 /* Enable down-conversion for 32bpp and smaller formats. */
169 switch (format) {
170 case V_028C70_COLOR_8:
171 case V_028C70_COLOR_8_8:
172 case V_028C70_COLOR_8_8_8_8:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
175 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_5_6_5:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_1_5_5_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_4_4_4_4:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_32:
204 if (swap == V_0280A0_SWAP_STD &&
205 spi_format == V_028714_SPI_SHADER_32_R)
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
207 else if (swap == V_0280A0_SWAP_ALT_REV &&
208 spi_format == V_028714_SPI_SHADER_32_AR)
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
210 break;
211
212 case V_028C70_COLOR_16:
213 case V_028C70_COLOR_16_16:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
216 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
219 if (swap == V_0280A0_SWAP_STD ||
220 swap == V_0280A0_SWAP_STD_REV)
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
222 else
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
224 }
225 break;
226
227 case V_028C70_COLOR_10_11_11:
228 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
230 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_2_10_10_10:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
238 }
239 break;
240 }
241 }
242
243 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
244 sx_ps_downconvert = 0;
245 sx_blend_opt_epsilon = 0;
246 sx_blend_opt_control = 0;
247 }
248
249 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 R600_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
383 *src_factor = PIPE_BLENDFACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == PIPE_BLEND_SUBTRACT)
388 *func = PIPE_BLEND_REVERSE_SUBTRACT;
389 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
390 *func = PIPE_BLEND_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
397 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
398 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
399 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
401 }
402
403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
404 const struct pipe_blend_state *state,
405 unsigned mode)
406 {
407 struct si_context *sctx = (struct si_context*)ctx;
408 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
409 struct si_pm4_state *pm4 = &blend->pm4;
410 uint32_t sx_mrt_blend_opt[8] = {0};
411 uint32_t color_control = 0;
412
413 if (!blend)
414 return NULL;
415
416 blend->alpha_to_coverage = state->alpha_to_coverage;
417 blend->alpha_to_one = state->alpha_to_one;
418 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
419
420 if (state->logicop_enable) {
421 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
422 } else {
423 color_control |= S_028808_ROP3(0xcc);
424 }
425
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
432
433 if (state->alpha_to_coverage)
434 blend->need_src_alpha_4bit |= 0xf;
435
436 blend->cb_target_mask = 0;
437 for (int i = 0; i < 8; i++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j = state->independent_blend_enable ? i : 0;
440
441 unsigned eqRGB = state->rt[j].rgb_func;
442 unsigned srcRGB = state->rt[j].rgb_src_factor;
443 unsigned dstRGB = state->rt[j].rgb_dst_factor;
444 unsigned eqA = state->rt[j].alpha_func;
445 unsigned srcA = state->rt[j].alpha_src_factor;
446 unsigned dstA = state->rt[j].alpha_dst_factor;
447
448 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
449 unsigned blend_cntl = 0;
450
451 sx_mrt_blend_opt[i] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
454
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i >= 1 && blend->dual_src_blend)
457 continue;
458
459 /* Only addition and subtraction equations are supported with
460 * dual source blending.
461 */
462 if (blend->dual_src_blend &&
463 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
464 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
465 assert(!"Unsupported equation for dual source blending");
466 continue;
467 }
468
469 if (!state->rt[j].colormask)
470 continue;
471
472 /* cb_render_state will disable unused ones */
473 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
474
475 if (!state->rt[j].blend_enable) {
476 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
477 continue;
478 }
479
480 /* Blending optimizations for Stoney.
481 * These transformations don't change the behavior.
482 *
483 * First, get rid of DST in the blend factors:
484 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
485 */
486 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
487 PIPE_BLENDFACTOR_DST_COLOR,
488 PIPE_BLENDFACTOR_SRC_COLOR);
489 si_blend_remove_dst(&eqA, &srcA, &dstA,
490 PIPE_BLENDFACTOR_DST_COLOR,
491 PIPE_BLENDFACTOR_SRC_COLOR);
492 si_blend_remove_dst(&eqA, &srcA, &dstA,
493 PIPE_BLENDFACTOR_DST_ALPHA,
494 PIPE_BLENDFACTOR_SRC_ALPHA);
495
496 /* Look up the ideal settings from tables. */
497 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
498 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
499 srcA_opt = si_translate_blend_opt_factor(srcA, true);
500 dstA_opt = si_translate_blend_opt_factor(dstA, true);
501
502 /* Handle interdependencies. */
503 if (si_blend_factor_uses_dst(srcRGB))
504 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
505 if (si_blend_factor_uses_dst(srcA))
506 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
507
508 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
509 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
510 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
511 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
512 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
513
514 /* Set the final value. */
515 sx_mrt_blend_opt[i] =
516 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
517 S_028760_COLOR_DST_OPT(dstRGB_opt) |
518 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
519 S_028760_ALPHA_SRC_OPT(srcA_opt) |
520 S_028760_ALPHA_DST_OPT(dstA_opt) |
521 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
522
523 /* Set blend state. */
524 blend_cntl |= S_028780_ENABLE(1);
525 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
526 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
527 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
528
529 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
530 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
531 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
532 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
533 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
534 }
535 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536
537 blend->blend_enable_4bit |= 0xfu << (i * 4);
538
539 /* This is only important for formats without alpha. */
540 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
541 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
542 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
543 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
544 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
545 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
546 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
547 }
548
549 if (blend->cb_target_mask) {
550 color_control |= S_028808_MODE(mode);
551 } else {
552 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
553 }
554
555 if (sctx->b.family == CHIP_STONEY) {
556 for (int i = 0; i < 8; i++)
557 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
558 sx_mrt_blend_opt[i]);
559
560 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
561 if (blend->dual_src_blend || state->logicop_enable ||
562 mode == V_028808_CB_RESOLVE)
563 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
564 }
565
566 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
567 return blend;
568 }
569
570 static void *si_create_blend_state(struct pipe_context *ctx,
571 const struct pipe_blend_state *state)
572 {
573 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
574 }
575
576 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
577 {
578 struct si_context *sctx = (struct si_context *)ctx;
579 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
580 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
581 sctx->do_update_shaders = true;
582 }
583
584 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
588 }
589
590 static void si_set_blend_color(struct pipe_context *ctx,
591 const struct pipe_blend_color *state)
592 {
593 struct si_context *sctx = (struct si_context *)ctx;
594
595 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
596 return;
597
598 sctx->blend_color.state = *state;
599 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
600 }
601
602 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
603 {
604 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
605
606 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
607 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
608 }
609
610 /*
611 * Clipping
612 */
613
614 static void si_set_clip_state(struct pipe_context *ctx,
615 const struct pipe_clip_state *state)
616 {
617 struct si_context *sctx = (struct si_context *)ctx;
618 struct pipe_constant_buffer cb;
619
620 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
621 return;
622
623 sctx->clip_state.state = *state;
624 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
625
626 cb.buffer = NULL;
627 cb.user_buffer = state->ucp;
628 cb.buffer_offset = 0;
629 cb.buffer_size = 4*4*8;
630 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
631 pipe_resource_reference(&cb.buffer, NULL);
632 }
633
634 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
635 {
636 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
637
638 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
639 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
640 }
641
642 #define SIX_BITS 0x3F
643
644 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
645 {
646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
647 struct tgsi_shader_info *info = si_get_vs_info(sctx);
648 unsigned window_space =
649 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
650 unsigned clipdist_mask =
651 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
652 unsigned total_mask = clipdist_mask | (info->culldist_writemask << info->num_written_clipdistance);
653
654 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
655 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
656 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
657 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
658 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
659 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
660 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
661 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
662 info->writes_edgeflag ||
663 info->writes_layer ||
664 info->writes_viewport_index) |
665 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
666 (sctx->queued.named.rasterizer->clip_plane_enable &
667 clipdist_mask) | (info->culldist_writemask << 8));
668 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
669 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
670 (clipdist_mask ? 0 :
671 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
672 S_028810_CLIP_DISABLE(window_space));
673
674 /* reuse needs to be set off if we write oViewport */
675 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
676 S_028AB4_REUSE_OFF(info->writes_viewport_index));
677 }
678
679 /*
680 * inferred state between framebuffer and rasterizer
681 */
682 static void si_update_poly_offset_state(struct si_context *sctx)
683 {
684 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
685
686 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
687 return;
688
689 switch (sctx->framebuffer.state.zsbuf->texture->format) {
690 case PIPE_FORMAT_Z16_UNORM:
691 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
692 break;
693 default: /* 24-bit */
694 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
695 break;
696 case PIPE_FORMAT_Z32_FLOAT:
697 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
698 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
699 break;
700 }
701 }
702
703 /*
704 * Rasterizer
705 */
706
707 static uint32_t si_translate_fill(uint32_t func)
708 {
709 switch(func) {
710 case PIPE_POLYGON_MODE_FILL:
711 return V_028814_X_DRAW_TRIANGLES;
712 case PIPE_POLYGON_MODE_LINE:
713 return V_028814_X_DRAW_LINES;
714 case PIPE_POLYGON_MODE_POINT:
715 return V_028814_X_DRAW_POINTS;
716 default:
717 assert(0);
718 return V_028814_X_DRAW_POINTS;
719 }
720 }
721
722 static void *si_create_rs_state(struct pipe_context *ctx,
723 const struct pipe_rasterizer_state *state)
724 {
725 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
726 struct si_pm4_state *pm4 = &rs->pm4;
727 unsigned tmp, i;
728 float psize_min, psize_max;
729
730 if (!rs) {
731 return NULL;
732 }
733
734 rs->scissor_enable = state->scissor;
735 rs->clip_halfz = state->clip_halfz;
736 rs->two_side = state->light_twoside;
737 rs->multisample_enable = state->multisample;
738 rs->force_persample_interp = state->force_persample_interp;
739 rs->clip_plane_enable = state->clip_plane_enable;
740 rs->line_stipple_enable = state->line_stipple_enable;
741 rs->poly_stipple_enable = state->poly_stipple_enable;
742 rs->line_smooth = state->line_smooth;
743 rs->poly_smooth = state->poly_smooth;
744 rs->uses_poly_offset = state->offset_point || state->offset_line ||
745 state->offset_tri;
746 rs->clamp_fragment_color = state->clamp_fragment_color;
747 rs->flatshade = state->flatshade;
748 rs->sprite_coord_enable = state->sprite_coord_enable;
749 rs->rasterizer_discard = state->rasterizer_discard;
750 rs->pa_sc_line_stipple = state->line_stipple_enable ?
751 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
752 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
753 rs->pa_cl_clip_cntl =
754 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
755 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
756 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
757 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
758 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
759
760 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
761 S_0286D4_FLAT_SHADE_ENA(1) |
762 S_0286D4_PNT_SPRITE_ENA(1) |
763 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
764 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
765 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
766 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
767 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
768
769 /* point size 12.4 fixed point */
770 tmp = (unsigned)(state->point_size * 8.0);
771 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
772
773 if (state->point_size_per_vertex) {
774 psize_min = util_get_min_point_size(state);
775 psize_max = 8192;
776 } else {
777 /* Force the point size to be as if the vertex output was disabled. */
778 psize_min = state->point_size;
779 psize_max = state->point_size;
780 }
781 /* Divide by two, because 0.5 = 1 pixel. */
782 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
783 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
784 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
785
786 tmp = (unsigned)state->line_width * 8;
787 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
788 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
789 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
790 S_028A48_MSAA_ENABLE(state->multisample ||
791 state->poly_smooth ||
792 state->line_smooth) |
793 S_028A48_VPORT_SCISSOR_ENABLE(1));
794
795 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
796 S_028BE4_PIX_CENTER(state->half_pixel_center) |
797 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
798
799 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
800 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
801 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
802 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
803 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
804 S_028814_FACE(!state->front_ccw) |
805 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
806 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
807 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
808 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
809 state->fill_back != PIPE_POLYGON_MODE_FILL) |
810 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
811 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
812 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
813 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
814
815 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
816 for (i = 0; i < 3; i++) {
817 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
818 float offset_units = state->offset_units;
819 float offset_scale = state->offset_scale * 16.0f;
820 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
821
822 if (!state->offset_units_unscaled) {
823 switch (i) {
824 case 0: /* 16-bit zbuffer */
825 offset_units *= 4.0f;
826 pa_su_poly_offset_db_fmt_cntl =
827 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
828 break;
829 case 1: /* 24-bit zbuffer */
830 offset_units *= 2.0f;
831 pa_su_poly_offset_db_fmt_cntl =
832 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
833 break;
834 case 2: /* 32-bit zbuffer */
835 offset_units *= 1.0f;
836 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
837 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
838 break;
839 }
840 }
841
842 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
843 fui(offset_scale));
844 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
845 fui(offset_units));
846 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
847 fui(offset_scale));
848 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
849 fui(offset_units));
850 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
851 pa_su_poly_offset_db_fmt_cntl);
852 }
853
854 return rs;
855 }
856
857 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
858 {
859 struct si_context *sctx = (struct si_context *)ctx;
860 struct si_state_rasterizer *old_rs =
861 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
862 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
863
864 if (!state)
865 return;
866
867 if (sctx->framebuffer.nr_samples > 1 &&
868 (!old_rs || old_rs->multisample_enable != rs->multisample_enable)) {
869 si_mark_atom_dirty(sctx, &sctx->db_render_state);
870
871 if (sctx->b.family >= CHIP_POLARIS10)
872 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
873 }
874
875 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
876
877 si_pm4_bind_state(sctx, rasterizer, rs);
878 si_update_poly_offset_state(sctx);
879
880 si_mark_atom_dirty(sctx, &sctx->clip_regs);
881 sctx->do_update_shaders = true;
882 }
883
884 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
885 {
886 struct si_context *sctx = (struct si_context *)ctx;
887
888 if (sctx->queued.named.rasterizer == state)
889 si_pm4_bind_state(sctx, poly_offset, NULL);
890 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
891 }
892
893 /*
894 * infeered state between dsa and stencil ref
895 */
896 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
897 {
898 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
899 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
900 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
901
902 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
903 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
904 S_028430_STENCILMASK(dsa->valuemask[0]) |
905 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
906 S_028430_STENCILOPVAL(1));
907 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
908 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
909 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
910 S_028434_STENCILOPVAL_BF(1));
911 }
912
913 static void si_set_stencil_ref(struct pipe_context *ctx,
914 const struct pipe_stencil_ref *state)
915 {
916 struct si_context *sctx = (struct si_context *)ctx;
917
918 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
919 return;
920
921 sctx->stencil_ref.state = *state;
922 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
923 }
924
925
926 /*
927 * DSA
928 */
929
930 static uint32_t si_translate_stencil_op(int s_op)
931 {
932 switch (s_op) {
933 case PIPE_STENCIL_OP_KEEP:
934 return V_02842C_STENCIL_KEEP;
935 case PIPE_STENCIL_OP_ZERO:
936 return V_02842C_STENCIL_ZERO;
937 case PIPE_STENCIL_OP_REPLACE:
938 return V_02842C_STENCIL_REPLACE_TEST;
939 case PIPE_STENCIL_OP_INCR:
940 return V_02842C_STENCIL_ADD_CLAMP;
941 case PIPE_STENCIL_OP_DECR:
942 return V_02842C_STENCIL_SUB_CLAMP;
943 case PIPE_STENCIL_OP_INCR_WRAP:
944 return V_02842C_STENCIL_ADD_WRAP;
945 case PIPE_STENCIL_OP_DECR_WRAP:
946 return V_02842C_STENCIL_SUB_WRAP;
947 case PIPE_STENCIL_OP_INVERT:
948 return V_02842C_STENCIL_INVERT;
949 default:
950 R600_ERR("Unknown stencil op %d", s_op);
951 assert(0);
952 break;
953 }
954 return 0;
955 }
956
957 static void *si_create_dsa_state(struct pipe_context *ctx,
958 const struct pipe_depth_stencil_alpha_state *state)
959 {
960 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
961 struct si_pm4_state *pm4 = &dsa->pm4;
962 unsigned db_depth_control;
963 uint32_t db_stencil_control = 0;
964
965 if (!dsa) {
966 return NULL;
967 }
968
969 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
970 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
971 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
972 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
973
974 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
975 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
976 S_028800_ZFUNC(state->depth.func) |
977 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
978
979 /* stencil */
980 if (state->stencil[0].enabled) {
981 db_depth_control |= S_028800_STENCIL_ENABLE(1);
982 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
983 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
984 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
985 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
986
987 if (state->stencil[1].enabled) {
988 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
989 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
990 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
991 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
992 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
993 }
994 }
995
996 /* alpha */
997 if (state->alpha.enabled) {
998 dsa->alpha_func = state->alpha.func;
999
1000 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1001 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1002 } else {
1003 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1004 }
1005
1006 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1007 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1008 if (state->depth.bounds_test) {
1009 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1010 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1011 }
1012
1013 return dsa;
1014 }
1015
1016 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1017 {
1018 struct si_context *sctx = (struct si_context *)ctx;
1019 struct si_state_dsa *dsa = state;
1020
1021 if (!state)
1022 return;
1023
1024 si_pm4_bind_state(sctx, dsa, dsa);
1025
1026 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1027 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1028 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1029 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1030 }
1031 sctx->do_update_shaders = true;
1032 }
1033
1034 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1035 {
1036 struct si_context *sctx = (struct si_context *)ctx;
1037 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1038 }
1039
1040 static void *si_create_db_flush_dsa(struct si_context *sctx)
1041 {
1042 struct pipe_depth_stencil_alpha_state dsa = {};
1043
1044 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1045 }
1046
1047 /* DB RENDER STATE */
1048
1049 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1050 {
1051 struct si_context *sctx = (struct si_context*)ctx;
1052
1053 /* Pipeline stat & streamout queries. */
1054 if (enable) {
1055 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1056 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1057 } else {
1058 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1059 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1060 }
1061
1062 /* Occlusion queries. */
1063 if (sctx->occlusion_queries_disabled != !enable) {
1064 sctx->occlusion_queries_disabled = !enable;
1065 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1066 }
1067 }
1068
1069 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1070 {
1071 struct si_context *sctx = (struct si_context*)ctx;
1072
1073 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1074 }
1075
1076 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1077 {
1078 struct si_context *sctx = (struct si_context*)ctx;
1079
1080 st->saved_compute = sctx->cs_shader_state.program;
1081
1082 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1083 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1084 }
1085
1086 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1087 {
1088 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1089 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1090 unsigned db_shader_control;
1091
1092 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1093
1094 /* DB_RENDER_CONTROL */
1095 if (sctx->dbcb_depth_copy_enabled ||
1096 sctx->dbcb_stencil_copy_enabled) {
1097 radeon_emit(cs,
1098 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1099 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1100 S_028000_COPY_CENTROID(1) |
1101 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1102 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1103 radeon_emit(cs,
1104 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1105 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1106 } else {
1107 radeon_emit(cs,
1108 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1109 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1110 }
1111
1112 /* DB_COUNT_CONTROL (occlusion queries) */
1113 if (sctx->b.num_occlusion_queries > 0 &&
1114 !sctx->occlusion_queries_disabled) {
1115 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1116
1117 if (sctx->b.chip_class >= CIK) {
1118 radeon_emit(cs,
1119 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1120 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1121 S_028004_ZPASS_ENABLE(1) |
1122 S_028004_SLICE_EVEN_ENABLE(1) |
1123 S_028004_SLICE_ODD_ENABLE(1));
1124 } else {
1125 radeon_emit(cs,
1126 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1127 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1128 }
1129 } else {
1130 /* Disable occlusion queries. */
1131 if (sctx->b.chip_class >= CIK) {
1132 radeon_emit(cs, 0);
1133 } else {
1134 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1135 }
1136 }
1137
1138 /* DB_RENDER_OVERRIDE2 */
1139 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1140 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1141 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1142 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1143
1144 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1145 sctx->ps_db_shader_control;
1146
1147 /* Bug workaround for smoothing (overrasterization) on SI. */
1148 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1149 db_shader_control &= C_02880C_Z_ORDER;
1150 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1151 }
1152
1153 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1154 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1155 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1156
1157 if (sctx->b.family == CHIP_STONEY &&
1158 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1159 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1160
1161 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1162 db_shader_control);
1163 }
1164
1165 /*
1166 * format translation
1167 */
1168 static uint32_t si_translate_colorformat(enum pipe_format format)
1169 {
1170 const struct util_format_description *desc = util_format_description(format);
1171
1172 #define HAS_SIZE(x,y,z,w) \
1173 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1174 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1175
1176 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1177 return V_028C70_COLOR_10_11_11;
1178
1179 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1180 return V_028C70_COLOR_INVALID;
1181
1182 /* hw cannot support mixed formats (except depth/stencil, since
1183 * stencil is not written to). */
1184 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1185 return V_028C70_COLOR_INVALID;
1186
1187 switch (desc->nr_channels) {
1188 case 1:
1189 switch (desc->channel[0].size) {
1190 case 8:
1191 return V_028C70_COLOR_8;
1192 case 16:
1193 return V_028C70_COLOR_16;
1194 case 32:
1195 return V_028C70_COLOR_32;
1196 }
1197 break;
1198 case 2:
1199 if (desc->channel[0].size == desc->channel[1].size) {
1200 switch (desc->channel[0].size) {
1201 case 8:
1202 return V_028C70_COLOR_8_8;
1203 case 16:
1204 return V_028C70_COLOR_16_16;
1205 case 32:
1206 return V_028C70_COLOR_32_32;
1207 }
1208 } else if (HAS_SIZE(8,24,0,0)) {
1209 return V_028C70_COLOR_24_8;
1210 } else if (HAS_SIZE(24,8,0,0)) {
1211 return V_028C70_COLOR_8_24;
1212 }
1213 break;
1214 case 3:
1215 if (HAS_SIZE(5,6,5,0)) {
1216 return V_028C70_COLOR_5_6_5;
1217 } else if (HAS_SIZE(32,8,24,0)) {
1218 return V_028C70_COLOR_X24_8_32_FLOAT;
1219 }
1220 break;
1221 case 4:
1222 if (desc->channel[0].size == desc->channel[1].size &&
1223 desc->channel[0].size == desc->channel[2].size &&
1224 desc->channel[0].size == desc->channel[3].size) {
1225 switch (desc->channel[0].size) {
1226 case 4:
1227 return V_028C70_COLOR_4_4_4_4;
1228 case 8:
1229 return V_028C70_COLOR_8_8_8_8;
1230 case 16:
1231 return V_028C70_COLOR_16_16_16_16;
1232 case 32:
1233 return V_028C70_COLOR_32_32_32_32;
1234 }
1235 } else if (HAS_SIZE(5,5,5,1)) {
1236 return V_028C70_COLOR_1_5_5_5;
1237 } else if (HAS_SIZE(10,10,10,2)) {
1238 return V_028C70_COLOR_2_10_10_10;
1239 }
1240 break;
1241 }
1242 return V_028C70_COLOR_INVALID;
1243 }
1244
1245 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1246 {
1247 if (SI_BIG_ENDIAN) {
1248 switch(colorformat) {
1249 /* 8-bit buffers. */
1250 case V_028C70_COLOR_8:
1251 return V_028C70_ENDIAN_NONE;
1252
1253 /* 16-bit buffers. */
1254 case V_028C70_COLOR_5_6_5:
1255 case V_028C70_COLOR_1_5_5_5:
1256 case V_028C70_COLOR_4_4_4_4:
1257 case V_028C70_COLOR_16:
1258 case V_028C70_COLOR_8_8:
1259 return V_028C70_ENDIAN_8IN16;
1260
1261 /* 32-bit buffers. */
1262 case V_028C70_COLOR_8_8_8_8:
1263 case V_028C70_COLOR_2_10_10_10:
1264 case V_028C70_COLOR_8_24:
1265 case V_028C70_COLOR_24_8:
1266 case V_028C70_COLOR_16_16:
1267 return V_028C70_ENDIAN_8IN32;
1268
1269 /* 64-bit buffers. */
1270 case V_028C70_COLOR_16_16_16_16:
1271 return V_028C70_ENDIAN_8IN16;
1272
1273 case V_028C70_COLOR_32_32:
1274 return V_028C70_ENDIAN_8IN32;
1275
1276 /* 128-bit buffers. */
1277 case V_028C70_COLOR_32_32_32_32:
1278 return V_028C70_ENDIAN_8IN32;
1279 default:
1280 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1281 }
1282 } else {
1283 return V_028C70_ENDIAN_NONE;
1284 }
1285 }
1286
1287 static uint32_t si_translate_dbformat(enum pipe_format format)
1288 {
1289 switch (format) {
1290 case PIPE_FORMAT_Z16_UNORM:
1291 return V_028040_Z_16;
1292 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1293 case PIPE_FORMAT_X8Z24_UNORM:
1294 case PIPE_FORMAT_Z24X8_UNORM:
1295 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1296 return V_028040_Z_24; /* deprecated on SI */
1297 case PIPE_FORMAT_Z32_FLOAT:
1298 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1299 return V_028040_Z_32_FLOAT;
1300 default:
1301 return V_028040_Z_INVALID;
1302 }
1303 }
1304
1305 /*
1306 * Texture translation
1307 */
1308
1309 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1310 enum pipe_format format,
1311 const struct util_format_description *desc,
1312 int first_non_void)
1313 {
1314 struct si_screen *sscreen = (struct si_screen*)screen;
1315 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1316 sscreen->b.info.drm_minor >= 31) ||
1317 sscreen->b.info.drm_major == 3;
1318 bool uniform = true;
1319 int i;
1320
1321 /* Colorspace (return non-RGB formats directly). */
1322 switch (desc->colorspace) {
1323 /* Depth stencil formats */
1324 case UTIL_FORMAT_COLORSPACE_ZS:
1325 switch (format) {
1326 case PIPE_FORMAT_Z16_UNORM:
1327 return V_008F14_IMG_DATA_FORMAT_16;
1328 case PIPE_FORMAT_X24S8_UINT:
1329 case PIPE_FORMAT_Z24X8_UNORM:
1330 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1331 return V_008F14_IMG_DATA_FORMAT_8_24;
1332 case PIPE_FORMAT_X8Z24_UNORM:
1333 case PIPE_FORMAT_S8X24_UINT:
1334 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1335 return V_008F14_IMG_DATA_FORMAT_24_8;
1336 case PIPE_FORMAT_S8_UINT:
1337 return V_008F14_IMG_DATA_FORMAT_8;
1338 case PIPE_FORMAT_Z32_FLOAT:
1339 return V_008F14_IMG_DATA_FORMAT_32;
1340 case PIPE_FORMAT_X32_S8X24_UINT:
1341 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1342 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1343 default:
1344 goto out_unknown;
1345 }
1346
1347 case UTIL_FORMAT_COLORSPACE_YUV:
1348 goto out_unknown; /* TODO */
1349
1350 case UTIL_FORMAT_COLORSPACE_SRGB:
1351 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1352 goto out_unknown;
1353 break;
1354
1355 default:
1356 break;
1357 }
1358
1359 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1360 if (!enable_compressed_formats)
1361 goto out_unknown;
1362
1363 switch (format) {
1364 case PIPE_FORMAT_RGTC1_SNORM:
1365 case PIPE_FORMAT_LATC1_SNORM:
1366 case PIPE_FORMAT_RGTC1_UNORM:
1367 case PIPE_FORMAT_LATC1_UNORM:
1368 return V_008F14_IMG_DATA_FORMAT_BC4;
1369 case PIPE_FORMAT_RGTC2_SNORM:
1370 case PIPE_FORMAT_LATC2_SNORM:
1371 case PIPE_FORMAT_RGTC2_UNORM:
1372 case PIPE_FORMAT_LATC2_UNORM:
1373 return V_008F14_IMG_DATA_FORMAT_BC5;
1374 default:
1375 goto out_unknown;
1376 }
1377 }
1378
1379 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1380 sscreen->b.family == CHIP_STONEY) {
1381 switch (format) {
1382 case PIPE_FORMAT_ETC1_RGB8:
1383 case PIPE_FORMAT_ETC2_RGB8:
1384 case PIPE_FORMAT_ETC2_SRGB8:
1385 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1386 case PIPE_FORMAT_ETC2_RGB8A1:
1387 case PIPE_FORMAT_ETC2_SRGB8A1:
1388 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1389 case PIPE_FORMAT_ETC2_RGBA8:
1390 case PIPE_FORMAT_ETC2_SRGBA8:
1391 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1392 case PIPE_FORMAT_ETC2_R11_UNORM:
1393 case PIPE_FORMAT_ETC2_R11_SNORM:
1394 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1395 case PIPE_FORMAT_ETC2_RG11_UNORM:
1396 case PIPE_FORMAT_ETC2_RG11_SNORM:
1397 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1398 default:
1399 goto out_unknown;
1400 }
1401 }
1402
1403 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1404 if (!enable_compressed_formats)
1405 goto out_unknown;
1406
1407 switch (format) {
1408 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1409 case PIPE_FORMAT_BPTC_SRGBA:
1410 return V_008F14_IMG_DATA_FORMAT_BC7;
1411 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1412 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1413 return V_008F14_IMG_DATA_FORMAT_BC6;
1414 default:
1415 goto out_unknown;
1416 }
1417 }
1418
1419 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1420 switch (format) {
1421 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1422 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1423 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1424 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1425 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1426 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1427 default:
1428 goto out_unknown;
1429 }
1430 }
1431
1432 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1433 if (!enable_compressed_formats)
1434 goto out_unknown;
1435
1436 if (!util_format_s3tc_enabled) {
1437 goto out_unknown;
1438 }
1439
1440 switch (format) {
1441 case PIPE_FORMAT_DXT1_RGB:
1442 case PIPE_FORMAT_DXT1_RGBA:
1443 case PIPE_FORMAT_DXT1_SRGB:
1444 case PIPE_FORMAT_DXT1_SRGBA:
1445 return V_008F14_IMG_DATA_FORMAT_BC1;
1446 case PIPE_FORMAT_DXT3_RGBA:
1447 case PIPE_FORMAT_DXT3_SRGBA:
1448 return V_008F14_IMG_DATA_FORMAT_BC2;
1449 case PIPE_FORMAT_DXT5_RGBA:
1450 case PIPE_FORMAT_DXT5_SRGBA:
1451 return V_008F14_IMG_DATA_FORMAT_BC3;
1452 default:
1453 goto out_unknown;
1454 }
1455 }
1456
1457 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1458 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1459 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1460 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1461 }
1462
1463 /* R8G8Bx_SNORM - TODO CxV8U8 */
1464
1465 /* hw cannot support mixed formats (except depth/stencil, since only
1466 * depth is read).*/
1467 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1468 goto out_unknown;
1469
1470 /* See whether the components are of the same size. */
1471 for (i = 1; i < desc->nr_channels; i++) {
1472 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1473 }
1474
1475 /* Non-uniform formats. */
1476 if (!uniform) {
1477 switch(desc->nr_channels) {
1478 case 3:
1479 if (desc->channel[0].size == 5 &&
1480 desc->channel[1].size == 6 &&
1481 desc->channel[2].size == 5) {
1482 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1483 }
1484 goto out_unknown;
1485 case 4:
1486 if (desc->channel[0].size == 5 &&
1487 desc->channel[1].size == 5 &&
1488 desc->channel[2].size == 5 &&
1489 desc->channel[3].size == 1) {
1490 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1491 }
1492 if (desc->channel[0].size == 10 &&
1493 desc->channel[1].size == 10 &&
1494 desc->channel[2].size == 10 &&
1495 desc->channel[3].size == 2) {
1496 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1497 }
1498 goto out_unknown;
1499 }
1500 goto out_unknown;
1501 }
1502
1503 if (first_non_void < 0 || first_non_void > 3)
1504 goto out_unknown;
1505
1506 /* uniform formats */
1507 switch (desc->channel[first_non_void].size) {
1508 case 4:
1509 switch (desc->nr_channels) {
1510 #if 0 /* Not supported for render targets */
1511 case 2:
1512 return V_008F14_IMG_DATA_FORMAT_4_4;
1513 #endif
1514 case 4:
1515 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1516 }
1517 break;
1518 case 8:
1519 switch (desc->nr_channels) {
1520 case 1:
1521 return V_008F14_IMG_DATA_FORMAT_8;
1522 case 2:
1523 return V_008F14_IMG_DATA_FORMAT_8_8;
1524 case 4:
1525 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1526 }
1527 break;
1528 case 16:
1529 switch (desc->nr_channels) {
1530 case 1:
1531 return V_008F14_IMG_DATA_FORMAT_16;
1532 case 2:
1533 return V_008F14_IMG_DATA_FORMAT_16_16;
1534 case 4:
1535 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1536 }
1537 break;
1538 case 32:
1539 switch (desc->nr_channels) {
1540 case 1:
1541 return V_008F14_IMG_DATA_FORMAT_32;
1542 case 2:
1543 return V_008F14_IMG_DATA_FORMAT_32_32;
1544 #if 0 /* Not supported for render targets */
1545 case 3:
1546 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1547 #endif
1548 case 4:
1549 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1550 }
1551 }
1552
1553 out_unknown:
1554 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1555 return ~0;
1556 }
1557
1558 static unsigned si_tex_wrap(unsigned wrap)
1559 {
1560 switch (wrap) {
1561 default:
1562 case PIPE_TEX_WRAP_REPEAT:
1563 return V_008F30_SQ_TEX_WRAP;
1564 case PIPE_TEX_WRAP_CLAMP:
1565 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1566 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1567 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1568 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1569 return V_008F30_SQ_TEX_CLAMP_BORDER;
1570 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1571 return V_008F30_SQ_TEX_MIRROR;
1572 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1573 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1574 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1575 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1576 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1577 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1578 }
1579 }
1580
1581 static unsigned si_tex_mipfilter(unsigned filter)
1582 {
1583 switch (filter) {
1584 case PIPE_TEX_MIPFILTER_NEAREST:
1585 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1586 case PIPE_TEX_MIPFILTER_LINEAR:
1587 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1588 default:
1589 case PIPE_TEX_MIPFILTER_NONE:
1590 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1591 }
1592 }
1593
1594 static unsigned si_tex_compare(unsigned compare)
1595 {
1596 switch (compare) {
1597 default:
1598 case PIPE_FUNC_NEVER:
1599 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1600 case PIPE_FUNC_LESS:
1601 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1602 case PIPE_FUNC_EQUAL:
1603 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1604 case PIPE_FUNC_LEQUAL:
1605 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1606 case PIPE_FUNC_GREATER:
1607 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1608 case PIPE_FUNC_NOTEQUAL:
1609 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1610 case PIPE_FUNC_GEQUAL:
1611 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1612 case PIPE_FUNC_ALWAYS:
1613 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1614 }
1615 }
1616
1617 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1618 unsigned nr_samples)
1619 {
1620 if (view_target == PIPE_TEXTURE_CUBE ||
1621 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1622 res_target = view_target;
1623 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1624 else if (res_target == PIPE_TEXTURE_CUBE ||
1625 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1626 res_target = PIPE_TEXTURE_2D_ARRAY;
1627
1628 switch (res_target) {
1629 default:
1630 case PIPE_TEXTURE_1D:
1631 return V_008F1C_SQ_RSRC_IMG_1D;
1632 case PIPE_TEXTURE_1D_ARRAY:
1633 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1634 case PIPE_TEXTURE_2D:
1635 case PIPE_TEXTURE_RECT:
1636 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1637 V_008F1C_SQ_RSRC_IMG_2D;
1638 case PIPE_TEXTURE_2D_ARRAY:
1639 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1640 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1641 case PIPE_TEXTURE_3D:
1642 return V_008F1C_SQ_RSRC_IMG_3D;
1643 case PIPE_TEXTURE_CUBE:
1644 case PIPE_TEXTURE_CUBE_ARRAY:
1645 return V_008F1C_SQ_RSRC_IMG_CUBE;
1646 }
1647 }
1648
1649 /*
1650 * Format support testing
1651 */
1652
1653 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1654 {
1655 return si_translate_texformat(screen, format, util_format_description(format),
1656 util_format_get_first_non_void_channel(format)) != ~0U;
1657 }
1658
1659 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1660 const struct util_format_description *desc,
1661 int first_non_void)
1662 {
1663 unsigned type;
1664 int i;
1665
1666 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1667 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1668
1669 assert(first_non_void >= 0);
1670 type = desc->channel[first_non_void].type;
1671
1672 if (type == UTIL_FORMAT_TYPE_FIXED)
1673 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1674
1675 if (desc->nr_channels == 4 &&
1676 desc->channel[0].size == 10 &&
1677 desc->channel[1].size == 10 &&
1678 desc->channel[2].size == 10 &&
1679 desc->channel[3].size == 2)
1680 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1681
1682 /* See whether the components are of the same size. */
1683 for (i = 0; i < desc->nr_channels; i++) {
1684 if (desc->channel[first_non_void].size != desc->channel[i].size)
1685 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1686 }
1687
1688 switch (desc->channel[first_non_void].size) {
1689 case 8:
1690 switch (desc->nr_channels) {
1691 case 1:
1692 return V_008F0C_BUF_DATA_FORMAT_8;
1693 case 2:
1694 return V_008F0C_BUF_DATA_FORMAT_8_8;
1695 case 3:
1696 case 4:
1697 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1698 }
1699 break;
1700 case 16:
1701 switch (desc->nr_channels) {
1702 case 1:
1703 return V_008F0C_BUF_DATA_FORMAT_16;
1704 case 2:
1705 return V_008F0C_BUF_DATA_FORMAT_16_16;
1706 case 3:
1707 case 4:
1708 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1709 }
1710 break;
1711 case 32:
1712 /* From the Southern Islands ISA documentation about MTBUF:
1713 * 'Memory reads of data in memory that is 32 or 64 bits do not
1714 * undergo any format conversion.'
1715 */
1716 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1717 !desc->channel[first_non_void].pure_integer)
1718 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1719
1720 switch (desc->nr_channels) {
1721 case 1:
1722 return V_008F0C_BUF_DATA_FORMAT_32;
1723 case 2:
1724 return V_008F0C_BUF_DATA_FORMAT_32_32;
1725 case 3:
1726 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1727 case 4:
1728 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1729 }
1730 break;
1731 }
1732
1733 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1734 }
1735
1736 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1737 const struct util_format_description *desc,
1738 int first_non_void)
1739 {
1740 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1741 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1742
1743 assert(first_non_void >= 0);
1744
1745 switch (desc->channel[first_non_void].type) {
1746 case UTIL_FORMAT_TYPE_SIGNED:
1747 if (desc->channel[first_non_void].normalized)
1748 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1749 else if (desc->channel[first_non_void].pure_integer)
1750 return V_008F0C_BUF_NUM_FORMAT_SINT;
1751 else
1752 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1753 break;
1754 case UTIL_FORMAT_TYPE_UNSIGNED:
1755 if (desc->channel[first_non_void].normalized)
1756 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1757 else if (desc->channel[first_non_void].pure_integer)
1758 return V_008F0C_BUF_NUM_FORMAT_UINT;
1759 else
1760 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1761 break;
1762 case UTIL_FORMAT_TYPE_FLOAT:
1763 default:
1764 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1765 }
1766 }
1767
1768 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1769 {
1770 const struct util_format_description *desc;
1771 int first_non_void;
1772 unsigned data_format;
1773
1774 desc = util_format_description(format);
1775 first_non_void = util_format_get_first_non_void_channel(format);
1776 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1777 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1778 }
1779
1780 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1781 {
1782 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1783 r600_translate_colorswap(format, false) != ~0U;
1784 }
1785
1786 static bool si_is_zs_format_supported(enum pipe_format format)
1787 {
1788 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1789 }
1790
1791 static boolean si_is_format_supported(struct pipe_screen *screen,
1792 enum pipe_format format,
1793 enum pipe_texture_target target,
1794 unsigned sample_count,
1795 unsigned usage)
1796 {
1797 unsigned retval = 0;
1798
1799 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1800 R600_ERR("r600: unsupported texture type %d\n", target);
1801 return false;
1802 }
1803
1804 if (!util_format_is_supported(format, usage))
1805 return false;
1806
1807 if (sample_count > 1) {
1808 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1809 return false;
1810
1811 if (usage & PIPE_BIND_SHADER_IMAGE)
1812 return false;
1813
1814 switch (sample_count) {
1815 case 2:
1816 case 4:
1817 case 8:
1818 break;
1819 case 16:
1820 if (format == PIPE_FORMAT_NONE)
1821 return true;
1822 else
1823 return false;
1824 default:
1825 return false;
1826 }
1827 }
1828
1829 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1830 PIPE_BIND_SHADER_IMAGE)) {
1831 if (target == PIPE_BUFFER) {
1832 if (si_is_vertex_format_supported(screen, format))
1833 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1834 PIPE_BIND_SHADER_IMAGE);
1835 } else {
1836 if (si_is_sampler_format_supported(screen, format))
1837 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1838 PIPE_BIND_SHADER_IMAGE);
1839 }
1840 }
1841
1842 if ((usage & (PIPE_BIND_RENDER_TARGET |
1843 PIPE_BIND_DISPLAY_TARGET |
1844 PIPE_BIND_SCANOUT |
1845 PIPE_BIND_SHARED |
1846 PIPE_BIND_BLENDABLE)) &&
1847 si_is_colorbuffer_format_supported(format)) {
1848 retval |= usage &
1849 (PIPE_BIND_RENDER_TARGET |
1850 PIPE_BIND_DISPLAY_TARGET |
1851 PIPE_BIND_SCANOUT |
1852 PIPE_BIND_SHARED);
1853 if (!util_format_is_pure_integer(format) &&
1854 !util_format_is_depth_or_stencil(format))
1855 retval |= usage & PIPE_BIND_BLENDABLE;
1856 }
1857
1858 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1859 si_is_zs_format_supported(format)) {
1860 retval |= PIPE_BIND_DEPTH_STENCIL;
1861 }
1862
1863 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1864 si_is_vertex_format_supported(screen, format)) {
1865 retval |= PIPE_BIND_VERTEX_BUFFER;
1866 }
1867
1868 if ((usage & PIPE_BIND_LINEAR) &&
1869 !util_format_is_compressed(format) &&
1870 !(usage & PIPE_BIND_DEPTH_STENCIL))
1871 retval |= PIPE_BIND_LINEAR;
1872
1873 return retval == usage;
1874 }
1875
1876 /*
1877 * framebuffer handling
1878 */
1879
1880 static void si_choose_spi_color_formats(struct r600_surface *surf,
1881 unsigned format, unsigned swap,
1882 unsigned ntype, bool is_depth)
1883 {
1884 /* Alpha is needed for alpha-to-coverage.
1885 * Blending may be with or without alpha.
1886 */
1887 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1888 unsigned alpha = 0; /* exports alpha, but may not support blending */
1889 unsigned blend = 0; /* supports blending, but may not export alpha */
1890 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1891
1892 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1893 * Other chips have multiple choices, though they are not necessarily better.
1894 */
1895 switch (format) {
1896 case V_028C70_COLOR_5_6_5:
1897 case V_028C70_COLOR_1_5_5_5:
1898 case V_028C70_COLOR_5_5_5_1:
1899 case V_028C70_COLOR_4_4_4_4:
1900 case V_028C70_COLOR_10_11_11:
1901 case V_028C70_COLOR_11_11_10:
1902 case V_028C70_COLOR_8:
1903 case V_028C70_COLOR_8_8:
1904 case V_028C70_COLOR_8_8_8_8:
1905 case V_028C70_COLOR_10_10_10_2:
1906 case V_028C70_COLOR_2_10_10_10:
1907 if (ntype == V_028C70_NUMBER_UINT)
1908 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1909 else if (ntype == V_028C70_NUMBER_SINT)
1910 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1911 else
1912 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1913 break;
1914
1915 case V_028C70_COLOR_16:
1916 case V_028C70_COLOR_16_16:
1917 case V_028C70_COLOR_16_16_16_16:
1918 if (ntype == V_028C70_NUMBER_UNORM ||
1919 ntype == V_028C70_NUMBER_SNORM) {
1920 /* UNORM16 and SNORM16 don't support blending */
1921 if (ntype == V_028C70_NUMBER_UNORM)
1922 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1923 else
1924 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1925
1926 /* Use 32 bits per channel for blending. */
1927 if (format == V_028C70_COLOR_16) {
1928 if (swap == V_028C70_SWAP_STD) { /* R */
1929 blend = V_028714_SPI_SHADER_32_R;
1930 blend_alpha = V_028714_SPI_SHADER_32_AR;
1931 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1932 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1933 else
1934 assert(0);
1935 } else if (format == V_028C70_COLOR_16_16) {
1936 if (swap == V_028C70_SWAP_STD) { /* RG */
1937 blend = V_028714_SPI_SHADER_32_GR;
1938 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1939 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1940 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1941 else
1942 assert(0);
1943 } else /* 16_16_16_16 */
1944 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1945 } else if (ntype == V_028C70_NUMBER_UINT)
1946 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1947 else if (ntype == V_028C70_NUMBER_SINT)
1948 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1949 else if (ntype == V_028C70_NUMBER_FLOAT)
1950 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1951 else
1952 assert(0);
1953 break;
1954
1955 case V_028C70_COLOR_32:
1956 if (swap == V_028C70_SWAP_STD) { /* R */
1957 blend = normal = V_028714_SPI_SHADER_32_R;
1958 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1959 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1960 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1961 else
1962 assert(0);
1963 break;
1964
1965 case V_028C70_COLOR_32_32:
1966 if (swap == V_028C70_SWAP_STD) { /* RG */
1967 blend = normal = V_028714_SPI_SHADER_32_GR;
1968 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1969 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1970 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1971 else
1972 assert(0);
1973 break;
1974
1975 case V_028C70_COLOR_32_32_32_32:
1976 case V_028C70_COLOR_8_24:
1977 case V_028C70_COLOR_24_8:
1978 case V_028C70_COLOR_X24_8_32_FLOAT:
1979 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1980 break;
1981
1982 default:
1983 assert(0);
1984 return;
1985 }
1986
1987 /* The DB->CB copy needs 32_ABGR. */
1988 if (is_depth)
1989 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1990
1991 surf->spi_shader_col_format = normal;
1992 surf->spi_shader_col_format_alpha = alpha;
1993 surf->spi_shader_col_format_blend = blend;
1994 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1995 }
1996
1997 static void si_initialize_color_surface(struct si_context *sctx,
1998 struct r600_surface *surf)
1999 {
2000 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2001 unsigned color_info, color_attrib, color_view;
2002 unsigned format, swap, ntype, endian;
2003 const struct util_format_description *desc;
2004 int i;
2005 unsigned blend_clamp = 0, blend_bypass = 0;
2006
2007 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2008 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2009
2010 desc = util_format_description(surf->base.format);
2011 for (i = 0; i < 4; i++) {
2012 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2013 break;
2014 }
2015 }
2016 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2017 ntype = V_028C70_NUMBER_FLOAT;
2018 } else {
2019 ntype = V_028C70_NUMBER_UNORM;
2020 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2021 ntype = V_028C70_NUMBER_SRGB;
2022 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2023 if (desc->channel[i].pure_integer) {
2024 ntype = V_028C70_NUMBER_SINT;
2025 } else {
2026 assert(desc->channel[i].normalized);
2027 ntype = V_028C70_NUMBER_SNORM;
2028 }
2029 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2030 if (desc->channel[i].pure_integer) {
2031 ntype = V_028C70_NUMBER_UINT;
2032 } else {
2033 assert(desc->channel[i].normalized);
2034 ntype = V_028C70_NUMBER_UNORM;
2035 }
2036 }
2037 }
2038
2039 format = si_translate_colorformat(surf->base.format);
2040 if (format == V_028C70_COLOR_INVALID) {
2041 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2042 }
2043 assert(format != V_028C70_COLOR_INVALID);
2044 swap = r600_translate_colorswap(surf->base.format, false);
2045 endian = si_colorformat_endian_swap(format);
2046
2047 /* blend clamp should be set for all NORM/SRGB types */
2048 if (ntype == V_028C70_NUMBER_UNORM ||
2049 ntype == V_028C70_NUMBER_SNORM ||
2050 ntype == V_028C70_NUMBER_SRGB)
2051 blend_clamp = 1;
2052
2053 /* set blend bypass according to docs if SINT/UINT or
2054 8/24 COLOR variants */
2055 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2056 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2057 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2058 blend_clamp = 0;
2059 blend_bypass = 1;
2060 }
2061
2062 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2063 (format == V_028C70_COLOR_8 ||
2064 format == V_028C70_COLOR_8_8 ||
2065 format == V_028C70_COLOR_8_8_8_8))
2066 surf->color_is_int8 = true;
2067
2068 color_info = S_028C70_FORMAT(format) |
2069 S_028C70_COMP_SWAP(swap) |
2070 S_028C70_BLEND_CLAMP(blend_clamp) |
2071 S_028C70_BLEND_BYPASS(blend_bypass) |
2072 S_028C70_SIMPLE_FLOAT(1) |
2073 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2074 ntype != V_028C70_NUMBER_SNORM &&
2075 ntype != V_028C70_NUMBER_SRGB &&
2076 format != V_028C70_COLOR_8_24 &&
2077 format != V_028C70_COLOR_24_8) |
2078 S_028C70_NUMBER_TYPE(ntype) |
2079 S_028C70_ENDIAN(endian);
2080
2081 /* Intensity is implemented as Red, so treat it that way. */
2082 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2083 util_format_is_intensity(surf->base.format));
2084
2085 if (rtex->resource.b.b.nr_samples > 1) {
2086 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2087
2088 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2089 S_028C74_NUM_FRAGMENTS(log_samples);
2090
2091 if (rtex->fmask.size) {
2092 color_info |= S_028C70_COMPRESSION(1);
2093 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2094
2095 if (sctx->b.chip_class == SI) {
2096 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2097 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2098 }
2099 }
2100 }
2101
2102 surf->cb_color_view = color_view;
2103 surf->cb_color_info = color_info;
2104 surf->cb_color_attrib = color_attrib;
2105
2106 if (sctx->b.chip_class >= VI) {
2107 unsigned max_uncompressed_block_size = 2;
2108
2109 if (rtex->surface.nsamples > 1) {
2110 if (rtex->surface.bpe == 1)
2111 max_uncompressed_block_size = 0;
2112 else if (rtex->surface.bpe == 2)
2113 max_uncompressed_block_size = 1;
2114 }
2115
2116 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2117 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2118 }
2119
2120 /* This must be set for fast clear to work without FMASK. */
2121 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2122 unsigned bankh = util_logbase2(rtex->surface.bankh);
2123 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2124 }
2125
2126 /* Determine pixel shader export format */
2127 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2128
2129 surf->color_initialized = true;
2130 }
2131
2132 static void si_init_depth_surface(struct si_context *sctx,
2133 struct r600_surface *surf)
2134 {
2135 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2136 unsigned level = surf->base.u.tex.level;
2137 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2138 unsigned format;
2139 uint32_t z_info, s_info, db_depth_info;
2140 uint64_t z_offs, s_offs;
2141 uint32_t db_htile_data_base, db_htile_surface;
2142
2143 format = si_translate_dbformat(rtex->resource.b.b.format);
2144
2145 if (format == V_028040_Z_INVALID) {
2146 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2147 }
2148 assert(format != V_028040_Z_INVALID);
2149
2150 s_offs = z_offs = rtex->resource.gpu_address;
2151 z_offs += rtex->surface.level[level].offset;
2152 s_offs += rtex->surface.stencil_level[level].offset;
2153
2154 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2155
2156 z_info = S_028040_FORMAT(format);
2157 if (rtex->resource.b.b.nr_samples > 1) {
2158 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2159 }
2160
2161 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2162 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2163 else
2164 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2165
2166 if (sctx->b.chip_class >= CIK) {
2167 struct radeon_info *info = &sctx->screen->b.info;
2168 unsigned index = rtex->surface.tiling_index[level];
2169 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2170 unsigned macro_index = rtex->surface.macro_tile_index;
2171 unsigned tile_mode = info->si_tile_mode_array[index];
2172 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2173 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2174
2175 db_depth_info |=
2176 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2177 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2178 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2179 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2180 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2181 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2182 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2183 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2184 } else {
2185 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2186 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2187 tile_mode_index = si_tile_mode_index(rtex, level, true);
2188 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2189 }
2190
2191 /* HiZ aka depth buffer htile */
2192 /* use htile only for first level */
2193 if (rtex->htile_buffer && !level) {
2194 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2195 S_028040_ALLOW_EXPCLEAR(1);
2196
2197 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2198 /* Workaround: For a not yet understood reason, the
2199 * combination of MSAA, fast stencil clear and stencil
2200 * decompress messes with subsequent stencil buffer
2201 * uses. Problem was reproduced on Verde, Bonaire,
2202 * Tonga, and Carrizo.
2203 *
2204 * Disabling EXPCLEAR works around the problem.
2205 *
2206 * Check piglit's arb_texture_multisample-stencil-clear
2207 * test if you want to try changing this.
2208 */
2209 if (rtex->resource.b.b.nr_samples <= 1)
2210 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2211 } else
2212 /* Use all of the htile_buffer for depth if there's no stencil. */
2213 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2214
2215 uint64_t va = rtex->htile_buffer->gpu_address;
2216 db_htile_data_base = va >> 8;
2217 db_htile_surface = S_028ABC_FULL_CACHE(1);
2218 } else {
2219 db_htile_data_base = 0;
2220 db_htile_surface = 0;
2221 }
2222
2223 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2224
2225 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2226 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2227 surf->db_htile_data_base = db_htile_data_base;
2228 surf->db_depth_info = db_depth_info;
2229 surf->db_z_info = z_info;
2230 surf->db_stencil_info = s_info;
2231 surf->db_depth_base = z_offs >> 8;
2232 surf->db_stencil_base = s_offs >> 8;
2233 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2234 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2235 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2236 levelinfo->nblk_y) / 64 - 1);
2237 surf->db_htile_surface = db_htile_surface;
2238
2239 surf->depth_initialized = true;
2240 }
2241
2242 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2243 {
2244 for (int i = 0; i < state->nr_cbufs; ++i) {
2245 struct r600_surface *surf = NULL;
2246 struct r600_texture *rtex;
2247
2248 if (!state->cbufs[i])
2249 continue;
2250 surf = (struct r600_surface*)state->cbufs[i];
2251 rtex = (struct r600_texture*)surf->base.texture;
2252
2253 p_atomic_dec(&rtex->framebuffers_bound);
2254 }
2255 }
2256
2257 static void si_set_framebuffer_state(struct pipe_context *ctx,
2258 const struct pipe_framebuffer_state *state)
2259 {
2260 struct si_context *sctx = (struct si_context *)ctx;
2261 struct pipe_constant_buffer constbuf = {0};
2262 struct r600_surface *surf = NULL;
2263 struct r600_texture *rtex;
2264 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2265 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2266 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2267 int i;
2268
2269 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2270 if (!sctx->framebuffer.state.cbufs[i])
2271 continue;
2272
2273 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2274 if (rtex->dcc_gather_statistics)
2275 vi_separate_dcc_stop_query(ctx, rtex);
2276 }
2277
2278 /* Only flush TC when changing the framebuffer state, because
2279 * the only client not using TC that can change textures is
2280 * the framebuffer.
2281 *
2282 * Flush all CB and DB caches here because all buffers can be used
2283 * for write by both TC (with shader image stores) and CB/DB.
2284 */
2285 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2286 SI_CONTEXT_INV_GLOBAL_L2 |
2287 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2288 SI_CONTEXT_CS_PARTIAL_FLUSH;
2289
2290 /* Take the maximum of the old and new count. If the new count is lower,
2291 * dirtying is needed to disable the unbound colorbuffers.
2292 */
2293 sctx->framebuffer.dirty_cbufs |=
2294 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2295 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2296
2297 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2298 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2299
2300 sctx->framebuffer.spi_shader_col_format = 0;
2301 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2302 sctx->framebuffer.spi_shader_col_format_blend = 0;
2303 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2304 sctx->framebuffer.color_is_int8 = 0;
2305
2306 sctx->framebuffer.compressed_cb_mask = 0;
2307 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2308 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2309 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2310 util_format_is_pure_integer(state->cbufs[0]->format);
2311 sctx->framebuffer.any_dst_linear = false;
2312
2313 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2314 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2315
2316 for (i = 0; i < state->nr_cbufs; i++) {
2317 if (!state->cbufs[i])
2318 continue;
2319
2320 surf = (struct r600_surface*)state->cbufs[i];
2321 rtex = (struct r600_texture*)surf->base.texture;
2322
2323 if (!surf->color_initialized) {
2324 si_initialize_color_surface(sctx, surf);
2325 }
2326
2327 sctx->framebuffer.spi_shader_col_format |=
2328 surf->spi_shader_col_format << (i * 4);
2329 sctx->framebuffer.spi_shader_col_format_alpha |=
2330 surf->spi_shader_col_format_alpha << (i * 4);
2331 sctx->framebuffer.spi_shader_col_format_blend |=
2332 surf->spi_shader_col_format_blend << (i * 4);
2333 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2334 surf->spi_shader_col_format_blend_alpha << (i * 4);
2335
2336 if (surf->color_is_int8)
2337 sctx->framebuffer.color_is_int8 |= 1 << i;
2338
2339 if (rtex->fmask.size && rtex->cmask.size) {
2340 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2341 }
2342
2343 if (surf->level_info->mode == RADEON_SURF_MODE_LINEAR_ALIGNED)
2344 sctx->framebuffer.any_dst_linear = true;
2345
2346 r600_context_add_resource_size(ctx, surf->base.texture);
2347
2348 p_atomic_inc(&rtex->framebuffers_bound);
2349
2350 if (rtex->dcc_gather_statistics) {
2351 /* Dirty tracking must be enabled for DCC usage analysis. */
2352 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2353 vi_separate_dcc_start_query(ctx, rtex);
2354 }
2355 }
2356
2357 if (state->zsbuf) {
2358 surf = (struct r600_surface*)state->zsbuf;
2359
2360 if (!surf->depth_initialized) {
2361 si_init_depth_surface(sctx, surf);
2362 }
2363 r600_context_add_resource_size(ctx, surf->base.texture);
2364 }
2365
2366 si_update_poly_offset_state(sctx);
2367 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2368 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2369
2370 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2371 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2372
2373 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2374 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2375 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2376
2377 /* Set sample locations as fragment shader constants. */
2378 switch (sctx->framebuffer.nr_samples) {
2379 case 1:
2380 constbuf.user_buffer = sctx->b.sample_locations_1x;
2381 break;
2382 case 2:
2383 constbuf.user_buffer = sctx->b.sample_locations_2x;
2384 break;
2385 case 4:
2386 constbuf.user_buffer = sctx->b.sample_locations_4x;
2387 break;
2388 case 8:
2389 constbuf.user_buffer = sctx->b.sample_locations_8x;
2390 break;
2391 case 16:
2392 constbuf.user_buffer = sctx->b.sample_locations_16x;
2393 break;
2394 default:
2395 R600_ERR("Requested an invalid number of samples %i.\n",
2396 sctx->framebuffer.nr_samples);
2397 assert(0);
2398 }
2399 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2400 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2401
2402 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2403 }
2404
2405 sctx->need_check_render_feedback = true;
2406 sctx->do_update_shaders = true;
2407 }
2408
2409 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2410 {
2411 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2412 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2413 unsigned i, nr_cbufs = state->nr_cbufs;
2414 struct r600_texture *tex = NULL;
2415 struct r600_surface *cb = NULL;
2416 unsigned cb_color_info = 0;
2417
2418 /* Colorbuffers. */
2419 for (i = 0; i < nr_cbufs; i++) {
2420 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2421 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2422 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2423
2424 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2425 continue;
2426
2427 cb = (struct r600_surface*)state->cbufs[i];
2428 if (!cb) {
2429 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2430 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2431 continue;
2432 }
2433
2434 tex = (struct r600_texture *)cb->base.texture;
2435 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2436 &tex->resource, RADEON_USAGE_READWRITE,
2437 tex->surface.nsamples > 1 ?
2438 RADEON_PRIO_COLOR_BUFFER_MSAA :
2439 RADEON_PRIO_COLOR_BUFFER);
2440
2441 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2442 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2443 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2444 RADEON_PRIO_CMASK);
2445 }
2446
2447 if (tex->dcc_separate_buffer)
2448 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2449 tex->dcc_separate_buffer,
2450 RADEON_USAGE_READWRITE,
2451 RADEON_PRIO_DCC);
2452
2453 /* Compute mutable surface parameters. */
2454 pitch_tile_max = cb->level_info->nblk_x / 8 - 1;
2455 slice_tile_max = cb->level_info->nblk_x *
2456 cb->level_info->nblk_y / 64 - 1;
2457 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2458
2459 cb_color_base = (tex->resource.gpu_address + cb->level_info->offset) >> 8;
2460 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2461 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2462 cb_color_attrib = cb->cb_color_attrib |
2463 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2464
2465 if (tex->fmask.size) {
2466 if (sctx->b.chip_class >= CIK)
2467 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2468 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2469 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2470 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2471 } else {
2472 /* This must be set for fast clear to work without FMASK. */
2473 if (sctx->b.chip_class >= CIK)
2474 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2475 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2476 cb_color_fmask = cb_color_base;
2477 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2478 }
2479
2480 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2481
2482 if (tex->dcc_offset && cb->level_info->dcc_enabled) {
2483 bool is_msaa_resolve_dst = state->cbufs[0] &&
2484 state->cbufs[0]->texture->nr_samples > 1 &&
2485 state->cbufs[1] == &cb->base &&
2486 state->cbufs[1]->texture->nr_samples <= 1;
2487
2488 if (!is_msaa_resolve_dst)
2489 cb_color_info |= S_028C70_DCC_ENABLE(1);
2490 }
2491
2492 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2493 sctx->b.chip_class >= VI ? 14 : 13);
2494 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2495 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2496 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2497 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2498 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2499 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2500 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2501 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2502 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2503 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2504 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2505 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2506 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2507
2508 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2509 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2510 tex->dcc_offset +
2511 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2512 }
2513 for (; i < 8 ; i++)
2514 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2515 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2516
2517 /* ZS buffer. */
2518 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2519 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2520 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2521
2522 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2523 &rtex->resource, RADEON_USAGE_READWRITE,
2524 zb->base.texture->nr_samples > 1 ?
2525 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2526 RADEON_PRIO_DEPTH_BUFFER);
2527
2528 if (zb->db_htile_data_base) {
2529 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2530 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2531 RADEON_PRIO_HTILE);
2532 }
2533
2534 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2535 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2536
2537 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2538 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2539 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2540 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2541 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2542 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2543 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2544 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2545 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2546 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2547 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2548
2549 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2550 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2551 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2552
2553 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2554 } else if (sctx->framebuffer.dirty_zsbuf) {
2555 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2556 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2557 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2558 }
2559
2560 /* Framebuffer dimensions. */
2561 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2562 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2563 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2564
2565 sctx->framebuffer.dirty_cbufs = 0;
2566 sctx->framebuffer.dirty_zsbuf = false;
2567 }
2568
2569 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2570 struct r600_atom *atom)
2571 {
2572 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2573 unsigned nr_samples = sctx->framebuffer.nr_samples;
2574
2575 /* Smoothing (only possible with nr_samples == 1) uses the same
2576 * sample locations as the MSAA it simulates.
2577 */
2578 if (nr_samples <= 1 && sctx->smoothing_enabled)
2579 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2580
2581 /* On Polaris, the small primitive filter uses the sample locations
2582 * even when MSAA is off, so we need to make sure they're set to 0.
2583 */
2584 if ((nr_samples > 1 || sctx->b.family >= CHIP_POLARIS10) &&
2585 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2586 sctx->msaa_sample_locs.nr_samples = nr_samples;
2587 cayman_emit_msaa_sample_locs(cs, nr_samples);
2588 }
2589
2590 if (sctx->b.family >= CHIP_POLARIS10) {
2591 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2592 unsigned small_prim_filter_cntl =
2593 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2594 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2595
2596 /* The alternative of setting sample locations to 0 would
2597 * require a DB flush to avoid Z errors, see
2598 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2599 */
2600 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2601 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2602
2603 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2604 small_prim_filter_cntl);
2605 }
2606 }
2607
2608 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2609 {
2610 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2611 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2612 /* 33% faster rendering to linear color buffers */
2613 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2614 unsigned sc_mode_cntl_1 =
2615 S_028A4C_WALK_SIZE(dst_is_linear) |
2616 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2617 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2618 /* always 1: */
2619 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2620 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2621 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2622 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2623 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2624 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2625
2626 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2627 sctx->ps_iter_samples,
2628 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2629 sc_mode_cntl_1);
2630 }
2631
2632 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2633 {
2634 struct si_context *sctx = (struct si_context *)ctx;
2635
2636 if (sctx->ps_iter_samples == min_samples)
2637 return;
2638
2639 sctx->ps_iter_samples = min_samples;
2640 sctx->do_update_shaders = true;
2641
2642 if (sctx->framebuffer.nr_samples > 1)
2643 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2644 }
2645
2646 /*
2647 * Samplers
2648 */
2649
2650 /**
2651 * Build the sampler view descriptor for a buffer texture.
2652 * @param state 256-bit descriptor; only the high 128 bits are filled in
2653 */
2654 void
2655 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2656 enum pipe_format format,
2657 unsigned offset, unsigned size,
2658 uint32_t *state)
2659 {
2660 const struct util_format_description *desc;
2661 int first_non_void;
2662 unsigned stride;
2663 unsigned num_records;
2664 unsigned num_format, data_format;
2665
2666 desc = util_format_description(format);
2667 first_non_void = util_format_get_first_non_void_channel(format);
2668 stride = desc->block.bits / 8;
2669 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2670 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2671
2672 num_records = size / stride;
2673 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2674
2675 if (screen->b.chip_class >= VI)
2676 num_records *= stride;
2677
2678 state[4] = 0;
2679 state[5] = S_008F04_STRIDE(stride);
2680 state[6] = num_records;
2681 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2682 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2683 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2684 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2685 S_008F0C_NUM_FORMAT(num_format) |
2686 S_008F0C_DATA_FORMAT(data_format);
2687 }
2688
2689 /**
2690 * Build the sampler view descriptor for a texture.
2691 */
2692 void
2693 si_make_texture_descriptor(struct si_screen *screen,
2694 struct r600_texture *tex,
2695 bool sampler,
2696 enum pipe_texture_target target,
2697 enum pipe_format pipe_format,
2698 const unsigned char state_swizzle[4],
2699 unsigned first_level, unsigned last_level,
2700 unsigned first_layer, unsigned last_layer,
2701 unsigned width, unsigned height, unsigned depth,
2702 uint32_t *state,
2703 uint32_t *fmask_state)
2704 {
2705 struct pipe_resource *res = &tex->resource.b.b;
2706 const struct util_format_description *desc;
2707 unsigned char swizzle[4];
2708 int first_non_void;
2709 unsigned num_format, data_format, type;
2710 uint64_t va;
2711
2712 desc = util_format_description(pipe_format);
2713
2714 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2715 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2716 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2717
2718 switch (pipe_format) {
2719 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2720 case PIPE_FORMAT_X24S8_UINT:
2721 case PIPE_FORMAT_X32_S8X24_UINT:
2722 case PIPE_FORMAT_X8Z24_UNORM:
2723 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2724 break;
2725 default:
2726 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2727 }
2728 } else {
2729 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2730 }
2731
2732 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2733
2734 switch (pipe_format) {
2735 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2736 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2737 break;
2738 default:
2739 if (first_non_void < 0) {
2740 if (util_format_is_compressed(pipe_format)) {
2741 switch (pipe_format) {
2742 case PIPE_FORMAT_DXT1_SRGB:
2743 case PIPE_FORMAT_DXT1_SRGBA:
2744 case PIPE_FORMAT_DXT3_SRGBA:
2745 case PIPE_FORMAT_DXT5_SRGBA:
2746 case PIPE_FORMAT_BPTC_SRGBA:
2747 case PIPE_FORMAT_ETC2_SRGB8:
2748 case PIPE_FORMAT_ETC2_SRGB8A1:
2749 case PIPE_FORMAT_ETC2_SRGBA8:
2750 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2751 break;
2752 case PIPE_FORMAT_RGTC1_SNORM:
2753 case PIPE_FORMAT_LATC1_SNORM:
2754 case PIPE_FORMAT_RGTC2_SNORM:
2755 case PIPE_FORMAT_LATC2_SNORM:
2756 case PIPE_FORMAT_ETC2_R11_SNORM:
2757 case PIPE_FORMAT_ETC2_RG11_SNORM:
2758 /* implies float, so use SNORM/UNORM to determine
2759 whether data is signed or not */
2760 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2761 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2762 break;
2763 default:
2764 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2765 break;
2766 }
2767 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2768 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2769 } else {
2770 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2771 }
2772 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2773 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2774 } else {
2775 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2776
2777 switch (desc->channel[first_non_void].type) {
2778 case UTIL_FORMAT_TYPE_FLOAT:
2779 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2780 break;
2781 case UTIL_FORMAT_TYPE_SIGNED:
2782 if (desc->channel[first_non_void].normalized)
2783 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2784 else if (desc->channel[first_non_void].pure_integer)
2785 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2786 else
2787 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2788 break;
2789 case UTIL_FORMAT_TYPE_UNSIGNED:
2790 if (desc->channel[first_non_void].normalized)
2791 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2792 else if (desc->channel[first_non_void].pure_integer)
2793 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2794 else
2795 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2796 }
2797 }
2798 }
2799
2800 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2801 if (data_format == ~0) {
2802 data_format = 0;
2803 }
2804
2805 if (!sampler &&
2806 (res->target == PIPE_TEXTURE_CUBE ||
2807 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2808 res->target == PIPE_TEXTURE_3D)) {
2809 /* For the purpose of shader images, treat cube maps and 3D
2810 * textures as 2D arrays. For 3D textures, the address
2811 * calculations for mipmaps are different, so we rely on the
2812 * caller to effectively disable mipmaps.
2813 */
2814 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2815
2816 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2817 } else {
2818 type = si_tex_dim(res->target, target, res->nr_samples);
2819 }
2820
2821 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2822 height = 1;
2823 depth = res->array_size;
2824 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2825 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2826 if (sampler || res->target != PIPE_TEXTURE_3D)
2827 depth = res->array_size;
2828 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2829 depth = res->array_size / 6;
2830
2831 state[0] = 0;
2832 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2833 S_008F14_NUM_FORMAT(num_format));
2834 state[2] = (S_008F18_WIDTH(width - 1) |
2835 S_008F18_HEIGHT(height - 1) |
2836 S_008F18_PERF_MOD(4));
2837 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2838 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2839 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2840 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2841 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2842 0 : first_level) |
2843 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2844 util_logbase2(res->nr_samples) :
2845 last_level) |
2846 S_008F1C_POW2_PAD(res->last_level > 0) |
2847 S_008F1C_TYPE(type));
2848 state[4] = S_008F20_DEPTH(depth - 1);
2849 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2850 S_008F24_LAST_ARRAY(last_layer));
2851 state[6] = 0;
2852 state[7] = 0;
2853
2854 if (tex->dcc_offset) {
2855 unsigned swap = r600_translate_colorswap(pipe_format, false);
2856
2857 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2858 } else {
2859 /* The last dword is unused by hw. The shader uses it to clear
2860 * bits in the first dword of sampler state.
2861 */
2862 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2863 if (first_level == last_level)
2864 state[7] = C_008F30_MAX_ANISO_RATIO;
2865 else
2866 state[7] = 0xffffffff;
2867 }
2868 }
2869
2870 /* Initialize the sampler view for FMASK. */
2871 if (tex->fmask.size) {
2872 uint32_t fmask_format;
2873
2874 va = tex->resource.gpu_address + tex->fmask.offset;
2875
2876 switch (res->nr_samples) {
2877 case 2:
2878 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2879 break;
2880 case 4:
2881 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2882 break;
2883 case 8:
2884 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2885 break;
2886 default:
2887 assert(0);
2888 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2889 }
2890
2891 fmask_state[0] = va >> 8;
2892 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2893 S_008F14_DATA_FORMAT(fmask_format) |
2894 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2895 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2896 S_008F18_HEIGHT(height - 1);
2897 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2898 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2899 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2900 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2901 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2902 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2903 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2904 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2905 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2906 S_008F24_LAST_ARRAY(last_layer);
2907 fmask_state[6] = 0;
2908 fmask_state[7] = 0;
2909 }
2910 }
2911
2912 /**
2913 * Create a sampler view.
2914 *
2915 * @param ctx context
2916 * @param texture texture
2917 * @param state sampler view template
2918 * @param width0 width0 override (for compressed textures as int)
2919 * @param height0 height0 override (for compressed textures as int)
2920 * @param force_level set the base address to the level (for compressed textures)
2921 */
2922 struct pipe_sampler_view *
2923 si_create_sampler_view_custom(struct pipe_context *ctx,
2924 struct pipe_resource *texture,
2925 const struct pipe_sampler_view *state,
2926 unsigned width0, unsigned height0,
2927 unsigned force_level)
2928 {
2929 struct si_context *sctx = (struct si_context*)ctx;
2930 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2931 struct r600_texture *tmp = (struct r600_texture*)texture;
2932 unsigned base_level, first_level, last_level;
2933 unsigned char state_swizzle[4];
2934 unsigned height, depth, width;
2935 unsigned last_layer = state->u.tex.last_layer;
2936 enum pipe_format pipe_format;
2937 const struct radeon_surf_level *surflevel;
2938
2939 if (!view)
2940 return NULL;
2941
2942 /* initialize base object */
2943 view->base = *state;
2944 view->base.texture = NULL;
2945 view->base.reference.count = 1;
2946 view->base.context = ctx;
2947
2948 assert(texture);
2949 pipe_resource_reference(&view->base.texture, texture);
2950
2951 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2952 state->format == PIPE_FORMAT_S8X24_UINT ||
2953 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2954 state->format == PIPE_FORMAT_S8_UINT)
2955 view->is_stencil_sampler = true;
2956
2957 /* Buffer resource. */
2958 if (texture->target == PIPE_BUFFER) {
2959 si_make_buffer_descriptor(sctx->screen,
2960 (struct r600_resource *)texture,
2961 state->format,
2962 state->u.buf.offset,
2963 state->u.buf.size,
2964 view->state);
2965 return &view->base;
2966 }
2967
2968 state_swizzle[0] = state->swizzle_r;
2969 state_swizzle[1] = state->swizzle_g;
2970 state_swizzle[2] = state->swizzle_b;
2971 state_swizzle[3] = state->swizzle_a;
2972
2973 base_level = 0;
2974 first_level = state->u.tex.first_level;
2975 last_level = state->u.tex.last_level;
2976 width = width0;
2977 height = height0;
2978 depth = texture->depth0;
2979
2980 if (force_level) {
2981 assert(force_level == first_level &&
2982 force_level == last_level);
2983 base_level = force_level;
2984 first_level = 0;
2985 last_level = 0;
2986 width = u_minify(width, force_level);
2987 height = u_minify(height, force_level);
2988 depth = u_minify(depth, force_level);
2989 }
2990
2991 /* This is not needed if state trackers set last_layer correctly. */
2992 if (state->target == PIPE_TEXTURE_1D ||
2993 state->target == PIPE_TEXTURE_2D ||
2994 state->target == PIPE_TEXTURE_RECT ||
2995 state->target == PIPE_TEXTURE_CUBE)
2996 last_layer = state->u.tex.first_layer;
2997
2998 /* Texturing with separate depth and stencil. */
2999 pipe_format = state->format;
3000
3001 /* Depth/stencil texturing sometimes needs separate texture. */
3002 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3003 if (!tmp->flushed_depth_texture &&
3004 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3005 pipe_resource_reference(&view->base.texture, NULL);
3006 FREE(view);
3007 return NULL;
3008 }
3009
3010 assert(tmp->flushed_depth_texture);
3011
3012 /* Override format for the case where the flushed texture
3013 * contains only Z or only S.
3014 */
3015 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3016 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3017
3018 tmp = tmp->flushed_depth_texture;
3019 }
3020
3021 surflevel = tmp->surface.level;
3022
3023 if (tmp->db_compatible) {
3024 switch (pipe_format) {
3025 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3026 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3027 break;
3028 case PIPE_FORMAT_X8Z24_UNORM:
3029 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3030 /* Z24 is always stored like this for DB
3031 * compatibility.
3032 */
3033 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3034 break;
3035 case PIPE_FORMAT_X24S8_UINT:
3036 case PIPE_FORMAT_S8X24_UINT:
3037 case PIPE_FORMAT_X32_S8X24_UINT:
3038 pipe_format = PIPE_FORMAT_S8_UINT;
3039 surflevel = tmp->surface.stencil_level;
3040 break;
3041 default:;
3042 }
3043 }
3044
3045 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3046 state->u.tex.first_level,
3047 state->format);
3048
3049 si_make_texture_descriptor(sctx->screen, tmp, true,
3050 state->target, pipe_format, state_swizzle,
3051 first_level, last_level,
3052 state->u.tex.first_layer, last_layer,
3053 width, height, depth,
3054 view->state, view->fmask_state);
3055
3056 view->base_level_info = &surflevel[base_level];
3057 view->base_level = base_level;
3058 view->block_width = util_format_get_blockwidth(pipe_format);
3059 return &view->base;
3060 }
3061
3062 static struct pipe_sampler_view *
3063 si_create_sampler_view(struct pipe_context *ctx,
3064 struct pipe_resource *texture,
3065 const struct pipe_sampler_view *state)
3066 {
3067 return si_create_sampler_view_custom(ctx, texture, state,
3068 texture ? texture->width0 : 0,
3069 texture ? texture->height0 : 0, 0);
3070 }
3071
3072 static void si_sampler_view_destroy(struct pipe_context *ctx,
3073 struct pipe_sampler_view *state)
3074 {
3075 struct si_sampler_view *view = (struct si_sampler_view *)state;
3076
3077 pipe_resource_reference(&state->texture, NULL);
3078 FREE(view);
3079 }
3080
3081 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3082 {
3083 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3084 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3085 (linear_filter &&
3086 (wrap == PIPE_TEX_WRAP_CLAMP ||
3087 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3088 }
3089
3090 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3091 {
3092 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3093 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3094
3095 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3096 state->border_color.ui[2] || state->border_color.ui[3]) &&
3097 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3098 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3099 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3100 }
3101
3102 static void *si_create_sampler_state(struct pipe_context *ctx,
3103 const struct pipe_sampler_state *state)
3104 {
3105 struct si_context *sctx = (struct si_context *)ctx;
3106 struct r600_common_screen *rscreen = sctx->b.screen;
3107 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3108 unsigned border_color_type, border_color_index = 0;
3109 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3110 : state->max_anisotropy;
3111 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3112
3113 if (!rstate) {
3114 return NULL;
3115 }
3116
3117 if (!sampler_state_needs_border_color(state))
3118 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3119 else if (state->border_color.f[0] == 0 &&
3120 state->border_color.f[1] == 0 &&
3121 state->border_color.f[2] == 0 &&
3122 state->border_color.f[3] == 0)
3123 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3124 else if (state->border_color.f[0] == 0 &&
3125 state->border_color.f[1] == 0 &&
3126 state->border_color.f[2] == 0 &&
3127 state->border_color.f[3] == 1)
3128 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3129 else if (state->border_color.f[0] == 1 &&
3130 state->border_color.f[1] == 1 &&
3131 state->border_color.f[2] == 1 &&
3132 state->border_color.f[3] == 1)
3133 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3134 else {
3135 int i;
3136
3137 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3138
3139 /* Check if the border has been uploaded already. */
3140 for (i = 0; i < sctx->border_color_count; i++)
3141 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3142 sizeof(state->border_color)) == 0)
3143 break;
3144
3145 if (i >= SI_MAX_BORDER_COLORS) {
3146 /* Getting 4096 unique border colors is very unlikely. */
3147 fprintf(stderr, "radeonsi: The border color table is full. "
3148 "Any new border colors will be just black. "
3149 "Please file a bug.\n");
3150 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3151 } else {
3152 if (i == sctx->border_color_count) {
3153 /* Upload a new border color. */
3154 memcpy(&sctx->border_color_table[i], &state->border_color,
3155 sizeof(state->border_color));
3156 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3157 &state->border_color,
3158 sizeof(state->border_color));
3159 sctx->border_color_count++;
3160 }
3161
3162 border_color_index = i;
3163 }
3164 }
3165
3166 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3167 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3168 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3169 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3170 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3171 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3172 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3173 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3174 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3175 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3176 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3177 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3178 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3179 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3180 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3181 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3182 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3183 S_008F38_MIP_POINT_PRECLAMP(1) |
3184 S_008F38_DISABLE_LSB_CEIL(1) |
3185 S_008F38_FILTER_PREC_FIX(1) |
3186 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3187 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3188 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3189 return rstate;
3190 }
3191
3192 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3193 {
3194 struct si_context *sctx = (struct si_context *)ctx;
3195
3196 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3197 return;
3198
3199 sctx->sample_mask.sample_mask = sample_mask;
3200 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3201 }
3202
3203 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3204 {
3205 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3206 unsigned mask = sctx->sample_mask.sample_mask;
3207
3208 /* Needed for line and polygon smoothing as well as for the Polaris
3209 * small primitive filter. We expect the state tracker to take care of
3210 * this for us.
3211 */
3212 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3213 (mask & 1 && sctx->blitter->running));
3214
3215 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3216 radeon_emit(cs, mask | (mask << 16));
3217 radeon_emit(cs, mask | (mask << 16));
3218 }
3219
3220 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3221 {
3222 free(state);
3223 }
3224
3225 /*
3226 * Vertex elements & buffers
3227 */
3228
3229 static void *si_create_vertex_elements(struct pipe_context *ctx,
3230 unsigned count,
3231 const struct pipe_vertex_element *elements)
3232 {
3233 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3234 int i;
3235
3236 assert(count <= SI_MAX_ATTRIBS);
3237 if (!v)
3238 return NULL;
3239
3240 v->count = count;
3241 for (i = 0; i < count; ++i) {
3242 const struct util_format_description *desc;
3243 unsigned data_format, num_format;
3244 int first_non_void;
3245
3246 desc = util_format_description(elements[i].src_format);
3247 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3248 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3249 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3250
3251 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3252 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3253 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3254 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3255 S_008F0C_NUM_FORMAT(num_format) |
3256 S_008F0C_DATA_FORMAT(data_format);
3257 v->format_size[i] = desc->block.bits / 8;
3258 }
3259 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3260
3261 return v;
3262 }
3263
3264 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3265 {
3266 struct si_context *sctx = (struct si_context *)ctx;
3267 struct si_vertex_element *v = (struct si_vertex_element*)state;
3268
3269 sctx->vertex_elements = v;
3270 sctx->vertex_buffers_dirty = true;
3271 sctx->do_update_shaders = true;
3272 }
3273
3274 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3275 {
3276 struct si_context *sctx = (struct si_context *)ctx;
3277
3278 if (sctx->vertex_elements == state)
3279 sctx->vertex_elements = NULL;
3280 FREE(state);
3281 }
3282
3283 static void si_set_vertex_buffers(struct pipe_context *ctx,
3284 unsigned start_slot, unsigned count,
3285 const struct pipe_vertex_buffer *buffers)
3286 {
3287 struct si_context *sctx = (struct si_context *)ctx;
3288 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3289 int i;
3290
3291 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3292
3293 if (buffers) {
3294 for (i = 0; i < count; i++) {
3295 const struct pipe_vertex_buffer *src = buffers + i;
3296 struct pipe_vertex_buffer *dsti = dst + i;
3297 struct pipe_resource *buf = src->buffer;
3298
3299 pipe_resource_reference(&dsti->buffer, buf);
3300 dsti->buffer_offset = src->buffer_offset;
3301 dsti->stride = src->stride;
3302 r600_context_add_resource_size(ctx, buf);
3303 if (buf)
3304 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3305 }
3306 } else {
3307 for (i = 0; i < count; i++) {
3308 pipe_resource_reference(&dst[i].buffer, NULL);
3309 }
3310 }
3311 sctx->vertex_buffers_dirty = true;
3312 }
3313
3314 static void si_set_index_buffer(struct pipe_context *ctx,
3315 const struct pipe_index_buffer *ib)
3316 {
3317 struct si_context *sctx = (struct si_context *)ctx;
3318
3319 if (ib) {
3320 struct pipe_resource *buf = ib->buffer;
3321
3322 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3323 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3324 r600_context_add_resource_size(ctx, buf);
3325 if (buf)
3326 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3327 } else {
3328 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3329 }
3330 }
3331
3332 /*
3333 * Misc
3334 */
3335
3336 static void si_set_tess_state(struct pipe_context *ctx,
3337 const float default_outer_level[4],
3338 const float default_inner_level[2])
3339 {
3340 struct si_context *sctx = (struct si_context *)ctx;
3341 struct pipe_constant_buffer cb;
3342 float array[8];
3343
3344 memcpy(array, default_outer_level, sizeof(float) * 4);
3345 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3346
3347 cb.buffer = NULL;
3348 cb.user_buffer = NULL;
3349 cb.buffer_size = sizeof(array);
3350
3351 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3352 (void*)array, sizeof(array),
3353 &cb.buffer_offset);
3354
3355 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3356 pipe_resource_reference(&cb.buffer, NULL);
3357 }
3358
3359 static void si_texture_barrier(struct pipe_context *ctx)
3360 {
3361 struct si_context *sctx = (struct si_context *)ctx;
3362
3363 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3364 SI_CONTEXT_INV_GLOBAL_L2 |
3365 SI_CONTEXT_FLUSH_AND_INV_CB |
3366 SI_CONTEXT_CS_PARTIAL_FLUSH;
3367 }
3368
3369 /* This only ensures coherency for shader image/buffer stores. */
3370 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3371 {
3372 struct si_context *sctx = (struct si_context *)ctx;
3373
3374 /* Subsequent commands must wait for all shader invocations to
3375 * complete. */
3376 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3377 SI_CONTEXT_CS_PARTIAL_FLUSH;
3378
3379 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3380 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3381 SI_CONTEXT_INV_VMEM_L1;
3382
3383 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3384 PIPE_BARRIER_SHADER_BUFFER |
3385 PIPE_BARRIER_TEXTURE |
3386 PIPE_BARRIER_IMAGE |
3387 PIPE_BARRIER_STREAMOUT_BUFFER |
3388 PIPE_BARRIER_GLOBAL_BUFFER)) {
3389 /* As far as I can tell, L1 contents are written back to L2
3390 * automatically at end of shader, but the contents of other
3391 * L1 caches might still be stale. */
3392 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3393 }
3394
3395 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3396 /* Indices are read through TC L2 since VI.
3397 * L1 isn't used.
3398 */
3399 if (sctx->screen->b.chip_class <= CIK)
3400 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3401 }
3402
3403 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3404 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3405
3406 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3407 PIPE_BARRIER_INDIRECT_BUFFER))
3408 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3409 }
3410
3411 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3412 {
3413 struct pipe_blend_state blend;
3414
3415 memset(&blend, 0, sizeof(blend));
3416 blend.independent_blend_enable = true;
3417 blend.rt[0].colormask = 0xf;
3418 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3419 }
3420
3421 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3422 bool include_draw_vbo)
3423 {
3424 si_need_cs_space((struct si_context*)ctx);
3425 }
3426
3427 static void si_init_config(struct si_context *sctx);
3428
3429 void si_init_state_functions(struct si_context *sctx)
3430 {
3431 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3432 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3433 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3434 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3435 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3436
3437 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3438 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3439 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3440 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3441 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3442 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3443 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3444 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3445 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3446 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3447
3448 sctx->b.b.create_blend_state = si_create_blend_state;
3449 sctx->b.b.bind_blend_state = si_bind_blend_state;
3450 sctx->b.b.delete_blend_state = si_delete_blend_state;
3451 sctx->b.b.set_blend_color = si_set_blend_color;
3452
3453 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3454 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3455 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3456
3457 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3458 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3459 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3460
3461 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3462 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3463 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3464 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3465 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3466
3467 sctx->b.b.set_clip_state = si_set_clip_state;
3468 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3469
3470 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3471 sctx->b.b.get_sample_position = cayman_get_sample_position;
3472
3473 sctx->b.b.create_sampler_state = si_create_sampler_state;
3474 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3475
3476 sctx->b.b.create_sampler_view = si_create_sampler_view;
3477 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3478
3479 sctx->b.b.set_sample_mask = si_set_sample_mask;
3480
3481 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3482 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3483 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3484 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3485 sctx->b.b.set_index_buffer = si_set_index_buffer;
3486
3487 sctx->b.b.texture_barrier = si_texture_barrier;
3488 sctx->b.b.memory_barrier = si_memory_barrier;
3489 sctx->b.b.set_min_samples = si_set_min_samples;
3490 sctx->b.b.set_tess_state = si_set_tess_state;
3491
3492 sctx->b.b.set_active_query_state = si_set_active_query_state;
3493 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3494 sctx->b.save_qbo_state = si_save_qbo_state;
3495 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3496
3497 sctx->b.b.draw_vbo = si_draw_vbo;
3498
3499 si_init_config(sctx);
3500 }
3501
3502 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3503 {
3504 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3505 }
3506
3507 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3508 struct r600_texture *rtex,
3509 struct radeon_bo_metadata *md)
3510 {
3511 struct si_screen *sscreen = (struct si_screen*)rscreen;
3512 struct pipe_resource *res = &rtex->resource.b.b;
3513 static const unsigned char swizzle[] = {
3514 PIPE_SWIZZLE_X,
3515 PIPE_SWIZZLE_Y,
3516 PIPE_SWIZZLE_Z,
3517 PIPE_SWIZZLE_W
3518 };
3519 uint32_t desc[8], i;
3520 bool is_array = util_resource_is_array_texture(res);
3521
3522 /* DRM 2.x.x doesn't support this. */
3523 if (rscreen->info.drm_major != 3)
3524 return;
3525
3526 assert(rtex->dcc_separate_buffer == NULL);
3527 assert(rtex->fmask.size == 0);
3528
3529 /* Metadata image format format version 1:
3530 * [0] = 1 (metadata format identifier)
3531 * [1] = (VENDOR_ID << 16) | PCI_ID
3532 * [2:9] = image descriptor for the whole resource
3533 * [2] is always 0, because the base address is cleared
3534 * [9] is the DCC offset bits [39:8] from the beginning of
3535 * the buffer
3536 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3537 */
3538
3539 md->metadata[0] = 1; /* metadata image format version 1 */
3540
3541 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3542 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3543
3544 si_make_texture_descriptor(sscreen, rtex, true,
3545 res->target, res->format,
3546 swizzle, 0, res->last_level, 0,
3547 is_array ? res->array_size - 1 : 0,
3548 res->width0, res->height0, res->depth0,
3549 desc, NULL);
3550
3551 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3552 rtex->surface.blk_w, false, desc);
3553
3554 /* Clear the base address and set the relative DCC offset. */
3555 desc[0] = 0;
3556 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3557 desc[7] = rtex->dcc_offset >> 8;
3558
3559 /* Dwords [2:9] contain the image descriptor. */
3560 memcpy(&md->metadata[2], desc, sizeof(desc));
3561
3562 /* Dwords [10:..] contain the mipmap level offsets. */
3563 for (i = 0; i <= res->last_level; i++)
3564 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3565
3566 md->size_metadata = (11 + res->last_level) * 4;
3567 }
3568
3569 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3570 struct r600_texture *rtex,
3571 struct radeon_bo_metadata *md)
3572 {
3573 uint32_t *desc = &md->metadata[2];
3574
3575 if (rscreen->chip_class < VI)
3576 return;
3577
3578 /* Return if DCC is enabled. The texture should be set up with it
3579 * already.
3580 */
3581 if (md->size_metadata >= 11 * 4 &&
3582 md->metadata[0] != 0 &&
3583 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3584 G_008F28_COMPRESSION_EN(desc[6])) {
3585 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3586 return;
3587 }
3588
3589 /* Disable DCC. These are always set by texture_from_handle and must
3590 * be cleared here.
3591 */
3592 rtex->dcc_offset = 0;
3593 }
3594
3595 void si_init_screen_state_functions(struct si_screen *sscreen)
3596 {
3597 sscreen->b.b.is_format_supported = si_is_format_supported;
3598 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3599 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3600 }
3601
3602 static void
3603 si_write_harvested_raster_configs(struct si_context *sctx,
3604 struct si_pm4_state *pm4,
3605 unsigned raster_config,
3606 unsigned raster_config_1)
3607 {
3608 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3609 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3610 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3611 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3612 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3613 unsigned rb_per_se = num_rb / num_se;
3614 unsigned se_mask[4];
3615 unsigned se;
3616
3617 se_mask[0] = ((1 << rb_per_se) - 1);
3618 se_mask[1] = (se_mask[0] << rb_per_se);
3619 se_mask[2] = (se_mask[1] << rb_per_se);
3620 se_mask[3] = (se_mask[2] << rb_per_se);
3621
3622 se_mask[0] &= rb_mask;
3623 se_mask[1] &= rb_mask;
3624 se_mask[2] &= rb_mask;
3625 se_mask[3] &= rb_mask;
3626
3627 assert(num_se == 1 || num_se == 2 || num_se == 4);
3628 assert(sh_per_se == 1 || sh_per_se == 2);
3629 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3630
3631 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3632 * fields are for, so I'm leaving them as their default
3633 * values. */
3634
3635 for (se = 0; se < num_se; se++) {
3636 unsigned raster_config_se = raster_config;
3637 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3638 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3639 int idx = (se / 2) * 2;
3640
3641 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3642 raster_config_se &= C_028350_SE_MAP;
3643
3644 if (!se_mask[idx]) {
3645 raster_config_se |=
3646 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3647 } else {
3648 raster_config_se |=
3649 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3650 }
3651 }
3652
3653 pkr0_mask &= rb_mask;
3654 pkr1_mask &= rb_mask;
3655 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3656 raster_config_se &= C_028350_PKR_MAP;
3657
3658 if (!pkr0_mask) {
3659 raster_config_se |=
3660 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3661 } else {
3662 raster_config_se |=
3663 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3664 }
3665 }
3666
3667 if (rb_per_se >= 2) {
3668 unsigned rb0_mask = 1 << (se * rb_per_se);
3669 unsigned rb1_mask = rb0_mask << 1;
3670
3671 rb0_mask &= rb_mask;
3672 rb1_mask &= rb_mask;
3673 if (!rb0_mask || !rb1_mask) {
3674 raster_config_se &= C_028350_RB_MAP_PKR0;
3675
3676 if (!rb0_mask) {
3677 raster_config_se |=
3678 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3679 } else {
3680 raster_config_se |=
3681 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3682 }
3683 }
3684
3685 if (rb_per_se > 2) {
3686 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3687 rb1_mask = rb0_mask << 1;
3688 rb0_mask &= rb_mask;
3689 rb1_mask &= rb_mask;
3690 if (!rb0_mask || !rb1_mask) {
3691 raster_config_se &= C_028350_RB_MAP_PKR1;
3692
3693 if (!rb0_mask) {
3694 raster_config_se |=
3695 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3696 } else {
3697 raster_config_se |=
3698 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3699 }
3700 }
3701 }
3702 }
3703
3704 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3705 if (sctx->b.chip_class < CIK)
3706 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3707 SE_INDEX(se) | SH_BROADCAST_WRITES |
3708 INSTANCE_BROADCAST_WRITES);
3709 else
3710 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3711 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3712 S_030800_INSTANCE_BROADCAST_WRITES(1));
3713 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3714 }
3715
3716 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3717 if (sctx->b.chip_class < CIK)
3718 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3719 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3720 INSTANCE_BROADCAST_WRITES);
3721 else {
3722 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3723 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3724 S_030800_INSTANCE_BROADCAST_WRITES(1));
3725
3726 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3727 (!se_mask[2] && !se_mask[3]))) {
3728 raster_config_1 &= C_028354_SE_PAIR_MAP;
3729
3730 if (!se_mask[0] && !se_mask[1]) {
3731 raster_config_1 |=
3732 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3733 } else {
3734 raster_config_1 |=
3735 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3736 }
3737 }
3738
3739 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3740 }
3741 }
3742
3743 static void si_init_config(struct si_context *sctx)
3744 {
3745 struct si_screen *sscreen = sctx->screen;
3746 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3747 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3748 unsigned raster_config, raster_config_1;
3749 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3750 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3751
3752 if (!pm4)
3753 return;
3754
3755 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3756 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3757 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3758 si_pm4_cmd_end(pm4, false);
3759
3760 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3761 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3762
3763 /* FIXME calculate these values somehow ??? */
3764 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3765 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3766 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3767
3768 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3769 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3770
3771 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3772 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3773 if (sctx->b.chip_class < CIK)
3774 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3775 S_008A14_CLIP_VTX_REORDER_ENA(1));
3776
3777 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3778 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3779
3780 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3781
3782 switch (sctx->screen->b.family) {
3783 case CHIP_TAHITI:
3784 case CHIP_PITCAIRN:
3785 raster_config = 0x2a00126a;
3786 raster_config_1 = 0x00000000;
3787 break;
3788 case CHIP_VERDE:
3789 raster_config = 0x0000124a;
3790 raster_config_1 = 0x00000000;
3791 break;
3792 case CHIP_OLAND:
3793 raster_config = 0x00000082;
3794 raster_config_1 = 0x00000000;
3795 break;
3796 case CHIP_HAINAN:
3797 raster_config = 0x00000000;
3798 raster_config_1 = 0x00000000;
3799 break;
3800 case CHIP_BONAIRE:
3801 raster_config = 0x16000012;
3802 raster_config_1 = 0x00000000;
3803 break;
3804 case CHIP_HAWAII:
3805 raster_config = 0x3a00161a;
3806 raster_config_1 = 0x0000002e;
3807 break;
3808 case CHIP_FIJI:
3809 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3810 /* old kernels with old tiling config */
3811 raster_config = 0x16000012;
3812 raster_config_1 = 0x0000002a;
3813 } else {
3814 raster_config = 0x3a00161a;
3815 raster_config_1 = 0x0000002e;
3816 }
3817 break;
3818 case CHIP_POLARIS10:
3819 raster_config = 0x16000012;
3820 raster_config_1 = 0x0000002a;
3821 break;
3822 case CHIP_POLARIS11:
3823 raster_config = 0x16000012;
3824 raster_config_1 = 0x00000000;
3825 break;
3826 case CHIP_TONGA:
3827 raster_config = 0x16000012;
3828 raster_config_1 = 0x0000002a;
3829 break;
3830 case CHIP_ICELAND:
3831 if (num_rb == 1)
3832 raster_config = 0x00000000;
3833 else
3834 raster_config = 0x00000002;
3835 raster_config_1 = 0x00000000;
3836 break;
3837 case CHIP_CARRIZO:
3838 raster_config = 0x00000002;
3839 raster_config_1 = 0x00000000;
3840 break;
3841 case CHIP_KAVERI:
3842 /* KV should be 0x00000002, but that causes problems with radeon */
3843 raster_config = 0x00000000; /* 0x00000002 */
3844 raster_config_1 = 0x00000000;
3845 break;
3846 case CHIP_KABINI:
3847 case CHIP_MULLINS:
3848 case CHIP_STONEY:
3849 raster_config = 0x00000000;
3850 raster_config_1 = 0x00000000;
3851 break;
3852 default:
3853 fprintf(stderr,
3854 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3855 raster_config = 0x00000000;
3856 raster_config_1 = 0x00000000;
3857 break;
3858 }
3859
3860 /* Always use the default config when all backends are enabled
3861 * (or when we failed to determine the enabled backends).
3862 */
3863 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3864 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3865 raster_config);
3866 if (sctx->b.chip_class >= CIK)
3867 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3868 raster_config_1);
3869 } else {
3870 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3871 }
3872
3873 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3874 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3875 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3876 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3877 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3878 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3879 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3880
3881 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3882 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
3883 S_028230_ER_TRI(0xA) |
3884 S_028230_ER_POINT(0xA) |
3885 S_028230_ER_RECT(0xA) |
3886 /* Required by DX10_DIAMOND_TEST_ENA: */
3887 S_028230_ER_LINE_LR(0x1A) |
3888 S_028230_ER_LINE_RL(0x26) |
3889 S_028230_ER_LINE_TB(0xA) |
3890 S_028230_ER_LINE_BT(0xA));
3891 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3892 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3893 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3894 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3895 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3896 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3897 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3898 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3899 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3900
3901 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3902 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3903 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3904
3905 if (sctx->b.chip_class >= CIK) {
3906 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3907 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3908 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3909 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3910
3911 if (sscreen->b.info.num_good_compute_units /
3912 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3913 /* Too few available compute units per SH. Disallowing
3914 * VS to run on CU0 could hurt us more than late VS
3915 * allocation would help.
3916 *
3917 * LATE_ALLOC_VS = 2 is the highest safe number.
3918 */
3919 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3920 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3921 } else {
3922 /* Set LATE_ALLOC_VS == 31. It should be less than
3923 * the number of scratch waves. Limitations:
3924 * - VS can't execute on CU0.
3925 * - If HS writes outputs to LDS, LS can't execute on CU0.
3926 */
3927 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3928 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3929 }
3930
3931 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3932 }
3933
3934 if (sctx->b.chip_class >= VI) {
3935 unsigned vgt_tess_distribution;
3936
3937 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3938 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3939 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3940 if (sctx->b.family < CHIP_POLARIS10)
3941 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3942 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3943
3944 vgt_tess_distribution =
3945 S_028B50_ACCUM_ISOLINE(32) |
3946 S_028B50_ACCUM_TRI(11) |
3947 S_028B50_ACCUM_QUAD(11) |
3948 S_028B50_DONUT_SPLIT(16);
3949
3950 /* Testing with Unigine Heaven extreme tesselation yielded best results
3951 * with TRAP_SPLIT = 3.
3952 */
3953 if (sctx->b.family == CHIP_FIJI ||
3954 sctx->b.family >= CHIP_POLARIS10)
3955 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
3956
3957 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
3958 } else {
3959 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
3960 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
3961 }
3962
3963 if (sctx->b.family == CHIP_STONEY)
3964 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3965
3966 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3967 if (sctx->b.chip_class >= CIK)
3968 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3969 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3970 RADEON_PRIO_BORDER_COLORS);
3971
3972 si_pm4_upload_indirect_buffer(sctx, pm4);
3973 sctx->init_config = pm4;
3974 }