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radeonsi: fix stencil op mapping
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_pack_color.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "radeonsi_pipe.h"
33 #include "si_state.h"
34 #include "sid.h"
35
36 /*
37 * inferred framebuffer and blender state
38 */
39 static void si_update_fb_blend_state(struct r600_context *rctx)
40 {
41 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
42 struct si_state_blend *blend = rctx->queued.named.blend;
43 uint32_t mask;
44
45 if (pm4 == NULL || blend == NULL)
46 return;
47
48 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
49 mask &= blend->cb_target_mask;
50 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
51
52 si_pm4_set_state(rctx, fb_blend, pm4);
53 }
54
55 /*
56 * Blender functions
57 */
58
59 static uint32_t si_translate_blend_function(int blend_func)
60 {
61 switch (blend_func) {
62 case PIPE_BLEND_ADD:
63 return V_028780_COMB_DST_PLUS_SRC;
64 case PIPE_BLEND_SUBTRACT:
65 return V_028780_COMB_SRC_MINUS_DST;
66 case PIPE_BLEND_REVERSE_SUBTRACT:
67 return V_028780_COMB_DST_MINUS_SRC;
68 case PIPE_BLEND_MIN:
69 return V_028780_COMB_MIN_DST_SRC;
70 case PIPE_BLEND_MAX:
71 return V_028780_COMB_MAX_DST_SRC;
72 default:
73 R600_ERR("Unknown blend function %d\n", blend_func);
74 assert(0);
75 break;
76 }
77 return 0;
78 }
79
80 static uint32_t si_translate_blend_factor(int blend_fact)
81 {
82 switch (blend_fact) {
83 case PIPE_BLENDFACTOR_ONE:
84 return V_028780_BLEND_ONE;
85 case PIPE_BLENDFACTOR_SRC_COLOR:
86 return V_028780_BLEND_SRC_COLOR;
87 case PIPE_BLENDFACTOR_SRC_ALPHA:
88 return V_028780_BLEND_SRC_ALPHA;
89 case PIPE_BLENDFACTOR_DST_ALPHA:
90 return V_028780_BLEND_DST_ALPHA;
91 case PIPE_BLENDFACTOR_DST_COLOR:
92 return V_028780_BLEND_DST_COLOR;
93 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
94 return V_028780_BLEND_SRC_ALPHA_SATURATE;
95 case PIPE_BLENDFACTOR_CONST_COLOR:
96 return V_028780_BLEND_CONSTANT_COLOR;
97 case PIPE_BLENDFACTOR_CONST_ALPHA:
98 return V_028780_BLEND_CONSTANT_ALPHA;
99 case PIPE_BLENDFACTOR_ZERO:
100 return V_028780_BLEND_ZERO;
101 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
102 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
103 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
104 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
105 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
106 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
107 case PIPE_BLENDFACTOR_INV_DST_COLOR:
108 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
109 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
110 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
111 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
112 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
113 case PIPE_BLENDFACTOR_SRC1_COLOR:
114 return V_028780_BLEND_SRC1_COLOR;
115 case PIPE_BLENDFACTOR_SRC1_ALPHA:
116 return V_028780_BLEND_SRC1_ALPHA;
117 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
118 return V_028780_BLEND_INV_SRC1_COLOR;
119 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
120 return V_028780_BLEND_INV_SRC1_ALPHA;
121 default:
122 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
123 assert(0);
124 break;
125 }
126 return 0;
127 }
128
129 static void *si_create_blend_state(struct pipe_context *ctx,
130 const struct pipe_blend_state *state)
131 {
132 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
133 struct si_pm4_state *pm4 = &blend->pm4;
134
135 uint32_t color_control;
136
137 if (blend == NULL)
138 return NULL;
139
140 color_control = S_028808_MODE(V_028808_CB_NORMAL);
141 if (state->logicop_enable) {
142 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
143 } else {
144 color_control |= S_028808_ROP3(0xcc);
145 }
146 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
147
148 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
149 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
150
151 blend->cb_target_mask = 0;
152 for (int i = 0; i < 8; i++) {
153 /* state->rt entries > 0 only written if independent blending */
154 const int j = state->independent_blend_enable ? i : 0;
155
156 unsigned eqRGB = state->rt[j].rgb_func;
157 unsigned srcRGB = state->rt[j].rgb_src_factor;
158 unsigned dstRGB = state->rt[j].rgb_dst_factor;
159 unsigned eqA = state->rt[j].alpha_func;
160 unsigned srcA = state->rt[j].alpha_src_factor;
161 unsigned dstA = state->rt[j].alpha_dst_factor;
162
163 unsigned blend_cntl = 0;
164
165 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
166 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
167
168 if (!state->rt[j].blend_enable) {
169 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
170 continue;
171 }
172
173 blend_cntl |= S_028780_ENABLE(1);
174 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
175 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
176 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
177
178 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
179 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
180 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
181 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
182 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
183 }
184 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
185 }
186
187 return blend;
188 }
189
190 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
191 {
192 struct r600_context *rctx = (struct r600_context *)ctx;
193 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
194 si_update_fb_blend_state(rctx);
195 }
196
197 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
201 }
202
203 static void si_set_blend_color(struct pipe_context *ctx,
204 const struct pipe_blend_color *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
208
209 if (pm4 == NULL)
210 return;
211
212 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
213 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
214 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
215 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
216
217 si_pm4_set_state(rctx, blend_color, pm4);
218 }
219
220 /*
221 * Clipping, scissors and viewport
222 */
223
224 static void si_set_clip_state(struct pipe_context *ctx,
225 const struct pipe_clip_state *state)
226 {
227 struct r600_context *rctx = (struct r600_context *)ctx;
228 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
229
230 if (pm4 == NULL)
231 return;
232
233 for (int i = 0; i < 6; i++) {
234 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
235 fui(state->ucp[i][0]));
236 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
237 fui(state->ucp[i][1]));
238 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
239 fui(state->ucp[i][2]));
240 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
241 fui(state->ucp[i][3]));
242 }
243
244 si_pm4_set_state(rctx, clip, pm4);
245 }
246
247 static void si_set_scissor_state(struct pipe_context *ctx,
248 const struct pipe_scissor_state *state)
249 {
250 struct r600_context *rctx = (struct r600_context *)ctx;
251 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
252 uint32_t tl, br;
253
254 if (pm4 == NULL)
255 return;
256
257 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
258 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
259 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
260 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
261 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
262 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
263 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
264 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
265 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
266 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
267
268 si_pm4_set_state(rctx, scissor, pm4);
269 }
270
271 static void si_set_viewport_state(struct pipe_context *ctx,
272 const struct pipe_viewport_state *state)
273 {
274 struct r600_context *rctx = (struct r600_context *)ctx;
275 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
276 struct si_pm4_state *pm4 = &viewport->pm4;
277
278 if (viewport == NULL)
279 return;
280
281 viewport->viewport = *state;
282 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
283 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
284 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
285 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
286 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
287 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
288 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
289 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
290 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
291 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
292
293 si_pm4_set_state(rctx, viewport, viewport);
294 }
295
296 /*
297 * inferred state between framebuffer and rasterizer
298 */
299 static void si_update_fb_rs_state(struct r600_context *rctx)
300 {
301 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
302 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
303 unsigned offset_db_fmt_cntl = 0, depth;
304 float offset_units;
305
306 if (!rs || !rctx->framebuffer.zsbuf) {
307 FREE(pm4);
308 return;
309 }
310
311 offset_units = rctx->queued.named.rasterizer->offset_units;
312 switch (rctx->framebuffer.zsbuf->texture->format) {
313 case PIPE_FORMAT_Z24X8_UNORM:
314 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
315 depth = -24;
316 offset_units *= 2.0f;
317 break;
318 case PIPE_FORMAT_Z32_FLOAT:
319 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
320 depth = -23;
321 offset_units *= 1.0f;
322 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
323 break;
324 case PIPE_FORMAT_Z16_UNORM:
325 depth = -16;
326 offset_units *= 4.0f;
327 break;
328 default:
329 return;
330 }
331
332 /* FIXME some of those reg can be computed with cso */
333 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
334 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
335 fui(rctx->queued.named.rasterizer->offset_scale));
336 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
337 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
338 fui(rctx->queued.named.rasterizer->offset_scale));
339 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
340 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
341
342 si_pm4_set_state(rctx, fb_rs, pm4);
343 }
344
345 /*
346 * Rasterizer
347 */
348
349 static uint32_t si_translate_fill(uint32_t func)
350 {
351 switch(func) {
352 case PIPE_POLYGON_MODE_FILL:
353 return V_028814_X_DRAW_TRIANGLES;
354 case PIPE_POLYGON_MODE_LINE:
355 return V_028814_X_DRAW_LINES;
356 case PIPE_POLYGON_MODE_POINT:
357 return V_028814_X_DRAW_POINTS;
358 default:
359 assert(0);
360 return V_028814_X_DRAW_POINTS;
361 }
362 }
363
364 static void *si_create_rs_state(struct pipe_context *ctx,
365 const struct pipe_rasterizer_state *state)
366 {
367 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
368 struct si_pm4_state *pm4 = &rs->pm4;
369 unsigned tmp;
370 unsigned prov_vtx = 1, polygon_dual_mode;
371 unsigned clip_rule;
372 float psize_min, psize_max;
373
374 if (rs == NULL) {
375 return NULL;
376 }
377
378 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
379 state->fill_back != PIPE_POLYGON_MODE_FILL);
380
381 if (state->flatshade_first)
382 prov_vtx = 0;
383
384 rs->flatshade = state->flatshade;
385 rs->sprite_coord_enable = state->sprite_coord_enable;
386 rs->pa_sc_line_stipple = state->line_stipple_enable ?
387 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
388 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
389 rs->pa_su_sc_mode_cntl =
390 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
391 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
392 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
393 S_028814_FACE(!state->front_ccw) |
394 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
395 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
396 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
397 S_028814_POLY_MODE(polygon_dual_mode) |
398 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
399 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
400 rs->pa_cl_clip_cntl =
401 S_028810_PS_UCP_MODE(3) |
402 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
403 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
404 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
405 rs->pa_cl_vs_out_cntl =
406 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
407 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
408
409 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
410
411 /* offset */
412 rs->offset_units = state->offset_units;
413 rs->offset_scale = state->offset_scale * 12.0f;
414
415 /* XXX: Flat shading hangs the GPU */
416 tmp = S_0286D4_FLAT_SHADE_ENA(0);
417 if (state->sprite_coord_enable) {
418 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
419 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
420 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
421 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
422 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
423 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
424 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
425 }
426 }
427 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
428
429 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
430 /* point size 12.4 fixed point */
431 tmp = (unsigned)(state->point_size * 8.0);
432 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
433
434 if (state->point_size_per_vertex) {
435 psize_min = util_get_min_point_size(state);
436 psize_max = 8192;
437 } else {
438 /* Force the point size to be as if the vertex output was disabled. */
439 psize_min = state->point_size;
440 psize_max = state->point_size;
441 }
442 /* Divide by two, because 0.5 = 1 pixel. */
443 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
444 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
445 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
446
447 tmp = (unsigned)state->line_width * 8;
448 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
449 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
450 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
451
452 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
453 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
454 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
455 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
456 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
457 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
458 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
459
460 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
461 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
462
463 return rs;
464 }
465
466 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
467 {
468 struct r600_context *rctx = (struct r600_context *)ctx;
469 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
470
471 if (state == NULL)
472 return;
473
474 // TODO
475 rctx->sprite_coord_enable = rs->sprite_coord_enable;
476 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
477 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
478 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
479 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
480
481 si_pm4_bind_state(rctx, rasterizer, rs);
482 si_update_fb_rs_state(rctx);
483 }
484
485 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
486 {
487 struct r600_context *rctx = (struct r600_context *)ctx;
488 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
489 }
490
491 /*
492 * infeered state between dsa and stencil ref
493 */
494 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
495 {
496 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
497 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
498 struct si_state_dsa *dsa = rctx->queued.named.dsa;
499
500 if (pm4 == NULL)
501 return;
502
503 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
504 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
505 S_028430_STENCILMASK(dsa->valuemask[0]) |
506 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
507 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
508 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
509 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
510 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
511
512 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
513 }
514
515 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
516 const struct pipe_stencil_ref *state)
517 {
518 struct r600_context *rctx = (struct r600_context *)ctx;
519 rctx->stencil_ref = *state;
520 si_update_dsa_stencil_ref(rctx);
521 }
522
523
524 /*
525 * DSA
526 */
527
528 static uint32_t si_translate_stencil_op(int s_op)
529 {
530 switch (s_op) {
531 case PIPE_STENCIL_OP_KEEP:
532 return V_02842C_STENCIL_KEEP;
533 case PIPE_STENCIL_OP_ZERO:
534 return V_02842C_STENCIL_ZERO;
535 case PIPE_STENCIL_OP_REPLACE:
536 return V_02842C_STENCIL_REPLACE_TEST;
537 case PIPE_STENCIL_OP_INCR:
538 return V_02842C_STENCIL_ADD_CLAMP;
539 case PIPE_STENCIL_OP_DECR:
540 return V_02842C_STENCIL_SUB_CLAMP;
541 case PIPE_STENCIL_OP_INCR_WRAP:
542 return V_02842C_STENCIL_ADD_WRAP;
543 case PIPE_STENCIL_OP_DECR_WRAP:
544 return V_02842C_STENCIL_SUB_WRAP;
545 case PIPE_STENCIL_OP_INVERT:
546 return V_02842C_STENCIL_INVERT;
547 default:
548 R600_ERR("Unknown stencil op %d", s_op);
549 assert(0);
550 break;
551 }
552 return 0;
553 }
554
555 static void *si_create_dsa_state(struct pipe_context *ctx,
556 const struct pipe_depth_stencil_alpha_state *state)
557 {
558 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
559 struct si_pm4_state *pm4 = &dsa->pm4;
560 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
561 unsigned db_render_override, db_render_control;
562 uint32_t db_stencil_control = 0;
563
564 if (dsa == NULL) {
565 return NULL;
566 }
567
568 dsa->valuemask[0] = state->stencil[0].valuemask;
569 dsa->valuemask[1] = state->stencil[1].valuemask;
570 dsa->writemask[0] = state->stencil[0].writemask;
571 dsa->writemask[1] = state->stencil[1].writemask;
572
573 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
574 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
575 S_028800_ZFUNC(state->depth.func);
576
577 /* stencil */
578 if (state->stencil[0].enabled) {
579 db_depth_control |= S_028800_STENCIL_ENABLE(1);
580 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
581 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
582 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
583 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
584
585 if (state->stencil[1].enabled) {
586 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
587 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
588 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
589 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
590 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
591 }
592 }
593
594 /* alpha */
595 //alpha_test_control = 0;
596 alpha_ref = 0;
597 if (state->alpha.enabled) {
598 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
599 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
600 alpha_ref = fui(state->alpha.ref_value);
601 }
602 dsa->alpha_ref = alpha_ref;
603
604 /* misc */
605 db_render_control = 0;
606 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
607 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
608 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
609 /* TODO db_render_override depends on query */
610 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
611 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
612 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
613 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
614 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
615 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
616 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
617 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
618 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
619 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
620 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
621 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
622 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
623 dsa->db_render_override = db_render_override;
624
625 return dsa;
626 }
627
628 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
629 {
630 struct r600_context *rctx = (struct r600_context *)ctx;
631 struct si_state_dsa *dsa = state;
632
633 if (state == NULL)
634 return;
635
636 si_pm4_bind_state(rctx, dsa, dsa);
637 si_update_dsa_stencil_ref(rctx);
638
639 // TODO
640 rctx->alpha_ref = dsa->alpha_ref;
641 rctx->alpha_ref_dirty = true;
642 }
643
644 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
645 {
646 struct r600_context *rctx = (struct r600_context *)ctx;
647 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
648 }
649
650 static void *si_create_db_flush_dsa(struct r600_context *rctx)
651 {
652 struct pipe_depth_stencil_alpha_state dsa;
653 struct si_state_dsa *state;
654
655 memset(&dsa, 0, sizeof(dsa));
656
657 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
658 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
659 S_028000_DEPTH_COPY(1) |
660 S_028000_STENCIL_COPY(1) |
661 S_028000_COPY_CENTROID(1));
662 return state;
663 }
664
665 /*
666 * format translation
667 */
668 static uint32_t si_translate_colorformat(enum pipe_format format)
669 {
670 switch (format) {
671 /* 8-bit buffers. */
672 case PIPE_FORMAT_A8_UNORM:
673 case PIPE_FORMAT_A8_UINT:
674 case PIPE_FORMAT_A8_SINT:
675 case PIPE_FORMAT_I8_UNORM:
676 case PIPE_FORMAT_I8_UINT:
677 case PIPE_FORMAT_I8_SINT:
678 case PIPE_FORMAT_L8_UNORM:
679 case PIPE_FORMAT_L8_UINT:
680 case PIPE_FORMAT_L8_SINT:
681 case PIPE_FORMAT_L8_SRGB:
682 case PIPE_FORMAT_R8_UNORM:
683 case PIPE_FORMAT_R8_SNORM:
684 case PIPE_FORMAT_R8_UINT:
685 case PIPE_FORMAT_R8_SINT:
686 return V_028C70_COLOR_8;
687
688 /* 16-bit buffers. */
689 case PIPE_FORMAT_B5G6R5_UNORM:
690 return V_028C70_COLOR_5_6_5;
691
692 case PIPE_FORMAT_B5G5R5A1_UNORM:
693 case PIPE_FORMAT_B5G5R5X1_UNORM:
694 return V_028C70_COLOR_1_5_5_5;
695
696 case PIPE_FORMAT_B4G4R4A4_UNORM:
697 case PIPE_FORMAT_B4G4R4X4_UNORM:
698 return V_028C70_COLOR_4_4_4_4;
699
700 case PIPE_FORMAT_L8A8_UNORM:
701 case PIPE_FORMAT_L8A8_UINT:
702 case PIPE_FORMAT_L8A8_SINT:
703 case PIPE_FORMAT_L8A8_SRGB:
704 case PIPE_FORMAT_R8G8_UNORM:
705 case PIPE_FORMAT_R8G8_UINT:
706 case PIPE_FORMAT_R8G8_SINT:
707 return V_028C70_COLOR_8_8;
708
709 case PIPE_FORMAT_Z16_UNORM:
710 case PIPE_FORMAT_R16_UNORM:
711 case PIPE_FORMAT_R16_UINT:
712 case PIPE_FORMAT_R16_SINT:
713 case PIPE_FORMAT_R16_FLOAT:
714 case PIPE_FORMAT_R16G16_FLOAT:
715 return V_028C70_COLOR_16;
716
717 /* 32-bit buffers. */
718 case PIPE_FORMAT_A8B8G8R8_SRGB:
719 case PIPE_FORMAT_A8B8G8R8_UNORM:
720 case PIPE_FORMAT_A8R8G8B8_UNORM:
721 case PIPE_FORMAT_B8G8R8A8_SRGB:
722 case PIPE_FORMAT_B8G8R8A8_UNORM:
723 case PIPE_FORMAT_B8G8R8X8_UNORM:
724 case PIPE_FORMAT_R8G8B8A8_SNORM:
725 case PIPE_FORMAT_R8G8B8A8_UNORM:
726 case PIPE_FORMAT_R8G8B8X8_UNORM:
727 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
728 case PIPE_FORMAT_X8B8G8R8_UNORM:
729 case PIPE_FORMAT_X8R8G8B8_UNORM:
730 case PIPE_FORMAT_R8G8B8_UNORM:
731 case PIPE_FORMAT_R8G8B8A8_SSCALED:
732 case PIPE_FORMAT_R8G8B8A8_USCALED:
733 case PIPE_FORMAT_R8G8B8A8_SINT:
734 case PIPE_FORMAT_R8G8B8A8_UINT:
735 return V_028C70_COLOR_8_8_8_8;
736
737 case PIPE_FORMAT_R10G10B10A2_UNORM:
738 case PIPE_FORMAT_R10G10B10X2_SNORM:
739 case PIPE_FORMAT_B10G10R10A2_UNORM:
740 case PIPE_FORMAT_B10G10R10A2_UINT:
741 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
742 return V_028C70_COLOR_2_10_10_10;
743
744 case PIPE_FORMAT_Z24X8_UNORM:
745 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
746 return V_028C70_COLOR_8_24;
747
748 case PIPE_FORMAT_X8Z24_UNORM:
749 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
750 return V_028C70_COLOR_24_8;
751
752 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
753 return V_028C70_COLOR_X24_8_32_FLOAT;
754
755 case PIPE_FORMAT_R32_FLOAT:
756 case PIPE_FORMAT_Z32_FLOAT:
757 return V_028C70_COLOR_32;
758
759 case PIPE_FORMAT_R16G16_SSCALED:
760 case PIPE_FORMAT_R16G16_UNORM:
761 case PIPE_FORMAT_R16G16_UINT:
762 case PIPE_FORMAT_R16G16_SINT:
763 return V_028C70_COLOR_16_16;
764
765 case PIPE_FORMAT_R11G11B10_FLOAT:
766 return V_028C70_COLOR_10_11_11;
767
768 /* 64-bit buffers. */
769 case PIPE_FORMAT_R16G16B16_USCALED:
770 case PIPE_FORMAT_R16G16B16_SSCALED:
771 case PIPE_FORMAT_R16G16B16A16_UINT:
772 case PIPE_FORMAT_R16G16B16A16_SINT:
773 case PIPE_FORMAT_R16G16B16A16_USCALED:
774 case PIPE_FORMAT_R16G16B16A16_SSCALED:
775 case PIPE_FORMAT_R16G16B16A16_UNORM:
776 case PIPE_FORMAT_R16G16B16A16_SNORM:
777 case PIPE_FORMAT_R16G16B16_FLOAT:
778 case PIPE_FORMAT_R16G16B16A16_FLOAT:
779 return V_028C70_COLOR_16_16_16_16;
780
781 case PIPE_FORMAT_R32G32_FLOAT:
782 case PIPE_FORMAT_R32G32_USCALED:
783 case PIPE_FORMAT_R32G32_SSCALED:
784 case PIPE_FORMAT_R32G32_SINT:
785 case PIPE_FORMAT_R32G32_UINT:
786 return V_028C70_COLOR_32_32;
787
788 /* 128-bit buffers. */
789 case PIPE_FORMAT_R32G32B32A32_SNORM:
790 case PIPE_FORMAT_R32G32B32A32_UNORM:
791 case PIPE_FORMAT_R32G32B32A32_SSCALED:
792 case PIPE_FORMAT_R32G32B32A32_USCALED:
793 case PIPE_FORMAT_R32G32B32A32_SINT:
794 case PIPE_FORMAT_R32G32B32A32_UINT:
795 case PIPE_FORMAT_R32G32B32A32_FLOAT:
796 return V_028C70_COLOR_32_32_32_32;
797
798 /* YUV buffers. */
799 case PIPE_FORMAT_UYVY:
800 case PIPE_FORMAT_YUYV:
801 /* 96-bit buffers. */
802 case PIPE_FORMAT_R32G32B32_FLOAT:
803 /* 8-bit buffers. */
804 case PIPE_FORMAT_L4A4_UNORM:
805 case PIPE_FORMAT_R4A4_UNORM:
806 case PIPE_FORMAT_A4R4_UNORM:
807 default:
808 return ~0U; /* Unsupported. */
809 }
810 }
811
812 static uint32_t si_translate_colorswap(enum pipe_format format)
813 {
814 switch (format) {
815 /* 8-bit buffers. */
816 case PIPE_FORMAT_L4A4_UNORM:
817 case PIPE_FORMAT_A4R4_UNORM:
818 return V_028C70_SWAP_ALT;
819
820 case PIPE_FORMAT_A8_UNORM:
821 case PIPE_FORMAT_A8_UINT:
822 case PIPE_FORMAT_A8_SINT:
823 case PIPE_FORMAT_R4A4_UNORM:
824 return V_028C70_SWAP_ALT_REV;
825 case PIPE_FORMAT_I8_UNORM:
826 case PIPE_FORMAT_L8_UNORM:
827 case PIPE_FORMAT_I8_UINT:
828 case PIPE_FORMAT_I8_SINT:
829 case PIPE_FORMAT_L8_UINT:
830 case PIPE_FORMAT_L8_SINT:
831 case PIPE_FORMAT_L8_SRGB:
832 case PIPE_FORMAT_R8_UNORM:
833 case PIPE_FORMAT_R8_SNORM:
834 case PIPE_FORMAT_R8_UINT:
835 case PIPE_FORMAT_R8_SINT:
836 return V_028C70_SWAP_STD;
837
838 /* 16-bit buffers. */
839 case PIPE_FORMAT_B5G6R5_UNORM:
840 return V_028C70_SWAP_STD_REV;
841
842 case PIPE_FORMAT_B5G5R5A1_UNORM:
843 case PIPE_FORMAT_B5G5R5X1_UNORM:
844 return V_028C70_SWAP_ALT;
845
846 case PIPE_FORMAT_B4G4R4A4_UNORM:
847 case PIPE_FORMAT_B4G4R4X4_UNORM:
848 return V_028C70_SWAP_ALT;
849
850 case PIPE_FORMAT_Z16_UNORM:
851 return V_028C70_SWAP_STD;
852
853 case PIPE_FORMAT_L8A8_UNORM:
854 case PIPE_FORMAT_L8A8_UINT:
855 case PIPE_FORMAT_L8A8_SINT:
856 case PIPE_FORMAT_L8A8_SRGB:
857 return V_028C70_SWAP_ALT;
858 case PIPE_FORMAT_R8G8_UNORM:
859 case PIPE_FORMAT_R8G8_UINT:
860 case PIPE_FORMAT_R8G8_SINT:
861 return V_028C70_SWAP_STD;
862
863 case PIPE_FORMAT_R16_UNORM:
864 case PIPE_FORMAT_R16_UINT:
865 case PIPE_FORMAT_R16_SINT:
866 case PIPE_FORMAT_R16_FLOAT:
867 return V_028C70_SWAP_STD;
868
869 /* 32-bit buffers. */
870 case PIPE_FORMAT_A8B8G8R8_SRGB:
871 return V_028C70_SWAP_STD_REV;
872 case PIPE_FORMAT_B8G8R8A8_SRGB:
873 return V_028C70_SWAP_ALT;
874
875 case PIPE_FORMAT_B8G8R8A8_UNORM:
876 case PIPE_FORMAT_B8G8R8X8_UNORM:
877 return V_028C70_SWAP_ALT;
878
879 case PIPE_FORMAT_A8R8G8B8_UNORM:
880 case PIPE_FORMAT_X8R8G8B8_UNORM:
881 return V_028C70_SWAP_ALT_REV;
882 case PIPE_FORMAT_R8G8B8A8_SNORM:
883 case PIPE_FORMAT_R8G8B8A8_UNORM:
884 case PIPE_FORMAT_R8G8B8A8_SSCALED:
885 case PIPE_FORMAT_R8G8B8A8_USCALED:
886 case PIPE_FORMAT_R8G8B8A8_SINT:
887 case PIPE_FORMAT_R8G8B8A8_UINT:
888 case PIPE_FORMAT_R8G8B8X8_UNORM:
889 return V_028C70_SWAP_STD;
890
891 case PIPE_FORMAT_A8B8G8R8_UNORM:
892 case PIPE_FORMAT_X8B8G8R8_UNORM:
893 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
894 return V_028C70_SWAP_STD_REV;
895
896 case PIPE_FORMAT_Z24X8_UNORM:
897 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
898 return V_028C70_SWAP_STD;
899
900 case PIPE_FORMAT_X8Z24_UNORM:
901 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
902 return V_028C70_SWAP_STD;
903
904 case PIPE_FORMAT_R10G10B10A2_UNORM:
905 case PIPE_FORMAT_R10G10B10X2_SNORM:
906 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
907 return V_028C70_SWAP_STD;
908
909 case PIPE_FORMAT_B10G10R10A2_UNORM:
910 case PIPE_FORMAT_B10G10R10A2_UINT:
911 return V_028C70_SWAP_ALT;
912
913 case PIPE_FORMAT_R11G11B10_FLOAT:
914 case PIPE_FORMAT_R32_FLOAT:
915 case PIPE_FORMAT_R32_UINT:
916 case PIPE_FORMAT_R32_SINT:
917 case PIPE_FORMAT_Z32_FLOAT:
918 case PIPE_FORMAT_R16G16_FLOAT:
919 case PIPE_FORMAT_R16G16_UNORM:
920 case PIPE_FORMAT_R16G16_UINT:
921 case PIPE_FORMAT_R16G16_SINT:
922 return V_028C70_SWAP_STD;
923
924 /* 64-bit buffers. */
925 case PIPE_FORMAT_R32G32_FLOAT:
926 case PIPE_FORMAT_R32G32_UINT:
927 case PIPE_FORMAT_R32G32_SINT:
928 case PIPE_FORMAT_R16G16B16A16_UNORM:
929 case PIPE_FORMAT_R16G16B16A16_SNORM:
930 case PIPE_FORMAT_R16G16B16A16_USCALED:
931 case PIPE_FORMAT_R16G16B16A16_SSCALED:
932 case PIPE_FORMAT_R16G16B16A16_UINT:
933 case PIPE_FORMAT_R16G16B16A16_SINT:
934 case PIPE_FORMAT_R16G16B16A16_FLOAT:
935 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
936
937 /* 128-bit buffers. */
938 case PIPE_FORMAT_R32G32B32A32_FLOAT:
939 case PIPE_FORMAT_R32G32B32A32_SNORM:
940 case PIPE_FORMAT_R32G32B32A32_UNORM:
941 case PIPE_FORMAT_R32G32B32A32_SSCALED:
942 case PIPE_FORMAT_R32G32B32A32_USCALED:
943 case PIPE_FORMAT_R32G32B32A32_SINT:
944 case PIPE_FORMAT_R32G32B32A32_UINT:
945 return V_028C70_SWAP_STD;
946 default:
947 R600_ERR("unsupported colorswap format %d\n", format);
948 return ~0U;
949 }
950 return ~0U;
951 }
952
953 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
954 {
955 if (R600_BIG_ENDIAN) {
956 switch(colorformat) {
957 /* 8-bit buffers. */
958 case V_028C70_COLOR_8:
959 return V_028C70_ENDIAN_NONE;
960
961 /* 16-bit buffers. */
962 case V_028C70_COLOR_5_6_5:
963 case V_028C70_COLOR_1_5_5_5:
964 case V_028C70_COLOR_4_4_4_4:
965 case V_028C70_COLOR_16:
966 case V_028C70_COLOR_8_8:
967 return V_028C70_ENDIAN_8IN16;
968
969 /* 32-bit buffers. */
970 case V_028C70_COLOR_8_8_8_8:
971 case V_028C70_COLOR_2_10_10_10:
972 case V_028C70_COLOR_8_24:
973 case V_028C70_COLOR_24_8:
974 case V_028C70_COLOR_16_16:
975 return V_028C70_ENDIAN_8IN32;
976
977 /* 64-bit buffers. */
978 case V_028C70_COLOR_16_16_16_16:
979 return V_028C70_ENDIAN_8IN16;
980
981 case V_028C70_COLOR_32_32:
982 return V_028C70_ENDIAN_8IN32;
983
984 /* 128-bit buffers. */
985 case V_028C70_COLOR_32_32_32_32:
986 return V_028C70_ENDIAN_8IN32;
987 default:
988 return V_028C70_ENDIAN_NONE; /* Unsupported. */
989 }
990 } else {
991 return V_028C70_ENDIAN_NONE;
992 }
993 }
994
995 static uint32_t si_translate_dbformat(enum pipe_format format)
996 {
997 switch (format) {
998 case PIPE_FORMAT_Z16_UNORM:
999 return V_028040_Z_16;
1000 case PIPE_FORMAT_Z24X8_UNORM:
1001 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1002 return V_028040_Z_24; /* XXX no longer supported on SI */
1003 case PIPE_FORMAT_Z32_FLOAT:
1004 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1005 return V_028040_Z_32_FLOAT;
1006 default:
1007 return ~0U;
1008 }
1009 }
1010
1011 /*
1012 * Texture translation
1013 */
1014
1015 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1016 enum pipe_format format,
1017 const struct util_format_description *desc,
1018 int first_non_void)
1019 {
1020 boolean uniform = TRUE;
1021 int i;
1022
1023 /* Colorspace (return non-RGB formats directly). */
1024 switch (desc->colorspace) {
1025 /* Depth stencil formats */
1026 case UTIL_FORMAT_COLORSPACE_ZS:
1027 switch (format) {
1028 case PIPE_FORMAT_Z16_UNORM:
1029 return V_008F14_IMG_DATA_FORMAT_16;
1030 case PIPE_FORMAT_X24S8_UINT:
1031 case PIPE_FORMAT_Z24X8_UNORM:
1032 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1033 return V_008F14_IMG_DATA_FORMAT_24_8;
1034 case PIPE_FORMAT_S8X24_UINT:
1035 case PIPE_FORMAT_X8Z24_UNORM:
1036 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1037 return V_008F14_IMG_DATA_FORMAT_8_24;
1038 case PIPE_FORMAT_S8_UINT:
1039 return V_008F14_IMG_DATA_FORMAT_8;
1040 case PIPE_FORMAT_Z32_FLOAT:
1041 return V_008F14_IMG_DATA_FORMAT_32;
1042 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1043 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1044 default:
1045 goto out_unknown;
1046 }
1047
1048 case UTIL_FORMAT_COLORSPACE_YUV:
1049 goto out_unknown; /* TODO */
1050
1051 case UTIL_FORMAT_COLORSPACE_SRGB:
1052 break;
1053
1054 default:
1055 break;
1056 }
1057
1058 /* TODO compressed formats */
1059
1060 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1061 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1062 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1063 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1064 }
1065
1066 /* R8G8Bx_SNORM - TODO CxV8U8 */
1067
1068 /* See whether the components are of the same size. */
1069 for (i = 1; i < desc->nr_channels; i++) {
1070 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1071 }
1072
1073 /* Non-uniform formats. */
1074 if (!uniform) {
1075 switch(desc->nr_channels) {
1076 case 3:
1077 if (desc->channel[0].size == 5 &&
1078 desc->channel[1].size == 6 &&
1079 desc->channel[2].size == 5) {
1080 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1081 }
1082 goto out_unknown;
1083 case 4:
1084 if (desc->channel[0].size == 5 &&
1085 desc->channel[1].size == 5 &&
1086 desc->channel[2].size == 5 &&
1087 desc->channel[3].size == 1) {
1088 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1089 }
1090 if (desc->channel[0].size == 10 &&
1091 desc->channel[1].size == 10 &&
1092 desc->channel[2].size == 10 &&
1093 desc->channel[3].size == 2) {
1094 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1095 }
1096 goto out_unknown;
1097 }
1098 goto out_unknown;
1099 }
1100
1101 if (first_non_void < 0 || first_non_void > 3)
1102 goto out_unknown;
1103
1104 /* uniform formats */
1105 switch (desc->channel[first_non_void].size) {
1106 case 4:
1107 switch (desc->nr_channels) {
1108 case 2:
1109 return V_008F14_IMG_DATA_FORMAT_4_4;
1110 case 4:
1111 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1112 }
1113 break;
1114 case 8:
1115 switch (desc->nr_channels) {
1116 case 1:
1117 return V_008F14_IMG_DATA_FORMAT_8;
1118 case 2:
1119 return V_008F14_IMG_DATA_FORMAT_8_8;
1120 case 4:
1121 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1122 }
1123 break;
1124 case 16:
1125 switch (desc->nr_channels) {
1126 case 1:
1127 return V_008F14_IMG_DATA_FORMAT_16;
1128 case 2:
1129 return V_008F14_IMG_DATA_FORMAT_16_16;
1130 case 4:
1131 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1132 }
1133 break;
1134 case 32:
1135 switch (desc->nr_channels) {
1136 case 1:
1137 return V_008F14_IMG_DATA_FORMAT_32;
1138 case 2:
1139 return V_008F14_IMG_DATA_FORMAT_32_32;
1140 case 3:
1141 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1142 case 4:
1143 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1144 }
1145 }
1146
1147 out_unknown:
1148 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1149 return ~0;
1150 }
1151
1152 static unsigned si_tex_wrap(unsigned wrap)
1153 {
1154 switch (wrap) {
1155 default:
1156 case PIPE_TEX_WRAP_REPEAT:
1157 return V_008F30_SQ_TEX_WRAP;
1158 case PIPE_TEX_WRAP_CLAMP:
1159 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1160 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1161 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1162 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1163 return V_008F30_SQ_TEX_CLAMP_BORDER;
1164 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1165 return V_008F30_SQ_TEX_MIRROR;
1166 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1167 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1168 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1169 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1170 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1171 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1172 }
1173 }
1174
1175 static unsigned si_tex_filter(unsigned filter)
1176 {
1177 switch (filter) {
1178 default:
1179 case PIPE_TEX_FILTER_NEAREST:
1180 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1181 case PIPE_TEX_FILTER_LINEAR:
1182 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1183 }
1184 }
1185
1186 static unsigned si_tex_mipfilter(unsigned filter)
1187 {
1188 switch (filter) {
1189 case PIPE_TEX_MIPFILTER_NEAREST:
1190 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1191 case PIPE_TEX_MIPFILTER_LINEAR:
1192 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1193 default:
1194 case PIPE_TEX_MIPFILTER_NONE:
1195 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1196 }
1197 }
1198
1199 static unsigned si_tex_compare(unsigned compare)
1200 {
1201 switch (compare) {
1202 default:
1203 case PIPE_FUNC_NEVER:
1204 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1205 case PIPE_FUNC_LESS:
1206 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1207 case PIPE_FUNC_EQUAL:
1208 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1209 case PIPE_FUNC_LEQUAL:
1210 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1211 case PIPE_FUNC_GREATER:
1212 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1213 case PIPE_FUNC_NOTEQUAL:
1214 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1215 case PIPE_FUNC_GEQUAL:
1216 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1217 case PIPE_FUNC_ALWAYS:
1218 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1219 }
1220 }
1221
1222 static unsigned si_tex_dim(unsigned dim)
1223 {
1224 switch (dim) {
1225 default:
1226 case PIPE_TEXTURE_1D:
1227 return V_008F1C_SQ_RSRC_IMG_1D;
1228 case PIPE_TEXTURE_1D_ARRAY:
1229 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1230 case PIPE_TEXTURE_2D:
1231 case PIPE_TEXTURE_RECT:
1232 return V_008F1C_SQ_RSRC_IMG_2D;
1233 case PIPE_TEXTURE_2D_ARRAY:
1234 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1235 case PIPE_TEXTURE_3D:
1236 return V_008F1C_SQ_RSRC_IMG_3D;
1237 case PIPE_TEXTURE_CUBE:
1238 return V_008F1C_SQ_RSRC_IMG_CUBE;
1239 }
1240 }
1241
1242 /*
1243 * Format support testing
1244 */
1245
1246 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1247 {
1248 return si_translate_texformat(screen, format, util_format_description(format),
1249 util_format_get_first_non_void_channel(format)) != ~0U;
1250 }
1251
1252 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1253 enum pipe_format format,
1254 const struct util_format_description *desc,
1255 int first_non_void)
1256 {
1257 uint32_t result;
1258
1259 if (desc->channel[first_non_void].type == UTIL_FORMAT_TYPE_FIXED)
1260 return ~0;
1261
1262 result = si_translate_texformat(screen, format, desc, first_non_void);
1263 if (result == V_008F0C_BUF_DATA_FORMAT_INVALID ||
1264 result > V_008F0C_BUF_DATA_FORMAT_32_32_32_32)
1265 result = ~0;
1266
1267 return result;
1268 }
1269
1270 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1271 {
1272 return si_translate_vertexformat(screen, format, util_format_description(format),
1273 util_format_get_first_non_void_channel(format)) != ~0U;
1274 }
1275
1276 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1277 {
1278 return si_translate_colorformat(format) != ~0U &&
1279 si_translate_colorswap(format) != ~0U;
1280 }
1281
1282 static bool si_is_zs_format_supported(enum pipe_format format)
1283 {
1284 return si_translate_dbformat(format) != ~0U;
1285 }
1286
1287 bool si_is_format_supported(struct pipe_screen *screen,
1288 enum pipe_format format,
1289 enum pipe_texture_target target,
1290 unsigned sample_count,
1291 unsigned usage)
1292 {
1293 unsigned retval = 0;
1294
1295 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1296 R600_ERR("r600: unsupported texture type %d\n", target);
1297 return FALSE;
1298 }
1299
1300 if (!util_format_is_supported(format, usage))
1301 return FALSE;
1302
1303 /* Multisample */
1304 if (sample_count > 1)
1305 return FALSE;
1306
1307 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1308 si_is_sampler_format_supported(screen, format)) {
1309 retval |= PIPE_BIND_SAMPLER_VIEW;
1310 }
1311
1312 if ((usage & (PIPE_BIND_RENDER_TARGET |
1313 PIPE_BIND_DISPLAY_TARGET |
1314 PIPE_BIND_SCANOUT |
1315 PIPE_BIND_SHARED)) &&
1316 si_is_colorbuffer_format_supported(format)) {
1317 retval |= usage &
1318 (PIPE_BIND_RENDER_TARGET |
1319 PIPE_BIND_DISPLAY_TARGET |
1320 PIPE_BIND_SCANOUT |
1321 PIPE_BIND_SHARED);
1322 }
1323
1324 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1325 si_is_zs_format_supported(format)) {
1326 retval |= PIPE_BIND_DEPTH_STENCIL;
1327 }
1328
1329 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1330 si_is_vertex_format_supported(screen, format)) {
1331 retval |= PIPE_BIND_VERTEX_BUFFER;
1332 }
1333
1334 if (usage & PIPE_BIND_TRANSFER_READ)
1335 retval |= PIPE_BIND_TRANSFER_READ;
1336 if (usage & PIPE_BIND_TRANSFER_WRITE)
1337 retval |= PIPE_BIND_TRANSFER_WRITE;
1338
1339 return retval == usage;
1340 }
1341
1342 /*
1343 * framebuffer handling
1344 */
1345
1346 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1347 const struct pipe_framebuffer_state *state, int cb)
1348 {
1349 struct r600_resource_texture *rtex;
1350 struct r600_surface *surf;
1351 unsigned level = state->cbufs[cb]->u.tex.level;
1352 unsigned pitch, slice;
1353 unsigned color_info, color_attrib;
1354 unsigned format, swap, ntype, endian;
1355 uint64_t offset;
1356 unsigned blocksize;
1357 const struct util_format_description *desc;
1358 int i;
1359 unsigned blend_clamp = 0, blend_bypass = 0;
1360
1361 surf = (struct r600_surface *)state->cbufs[cb];
1362 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1363 blocksize = util_format_get_blocksize(rtex->real_format);
1364
1365 if (rtex->depth)
1366 rctx->have_depth_fb = TRUE;
1367
1368 if (rtex->depth && !rtex->is_flushing_texture) {
1369 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1370 rtex = rtex->flushed_depth_texture;
1371 }
1372
1373 offset = rtex->surface.level[level].offset;
1374 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1375 offset += rtex->surface.level[level].slice_size *
1376 state->cbufs[cb]->u.tex.first_layer;
1377 }
1378 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1379 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1380 if (slice) {
1381 slice = slice - 1;
1382 }
1383
1384 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1385 switch (rtex->surface.level[level].mode) {
1386 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1387 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1388 break;
1389 case RADEON_SURF_MODE_1D:
1390 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1391 break;
1392 case RADEON_SURF_MODE_2D:
1393 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1394 switch (blocksize) {
1395 case 1:
1396 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1397 break;
1398 case 2:
1399 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1400 break;
1401 case 4:
1402 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1403 break;
1404 }
1405 break;
1406 } else switch (blocksize) {
1407 case 1:
1408 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1409 break;
1410 case 2:
1411 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1412 break;
1413 case 4:
1414 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1415 break;
1416 case 8:
1417 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1418 break;
1419 default:
1420 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1421 }
1422 break;
1423 }
1424
1425 desc = util_format_description(surf->base.format);
1426 for (i = 0; i < 4; i++) {
1427 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1428 break;
1429 }
1430 }
1431 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1432 ntype = V_028C70_NUMBER_FLOAT;
1433 } else {
1434 ntype = V_028C70_NUMBER_UNORM;
1435 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1436 ntype = V_028C70_NUMBER_SRGB;
1437 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1438 if (desc->channel[i].normalized)
1439 ntype = V_028C70_NUMBER_SNORM;
1440 else if (desc->channel[i].pure_integer)
1441 ntype = V_028C70_NUMBER_SINT;
1442 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1443 if (desc->channel[i].normalized)
1444 ntype = V_028C70_NUMBER_UNORM;
1445 else if (desc->channel[i].pure_integer)
1446 ntype = V_028C70_NUMBER_UINT;
1447 }
1448 }
1449
1450 format = si_translate_colorformat(surf->base.format);
1451 swap = si_translate_colorswap(surf->base.format);
1452 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1453 endian = V_028C70_ENDIAN_NONE;
1454 } else {
1455 endian = si_colorformat_endian_swap(format);
1456 }
1457
1458 /* blend clamp should be set for all NORM/SRGB types */
1459 if (ntype == V_028C70_NUMBER_UNORM ||
1460 ntype == V_028C70_NUMBER_SNORM ||
1461 ntype == V_028C70_NUMBER_SRGB)
1462 blend_clamp = 1;
1463
1464 /* set blend bypass according to docs if SINT/UINT or
1465 8/24 COLOR variants */
1466 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1467 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1468 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1469 blend_clamp = 0;
1470 blend_bypass = 1;
1471 }
1472
1473 color_info = S_028C70_FORMAT(format) |
1474 S_028C70_COMP_SWAP(swap) |
1475 S_028C70_BLEND_CLAMP(blend_clamp) |
1476 S_028C70_BLEND_BYPASS(blend_bypass) |
1477 S_028C70_NUMBER_TYPE(ntype) |
1478 S_028C70_ENDIAN(endian);
1479
1480 rctx->alpha_ref_dirty = true;
1481
1482 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1483 offset >>= 8;
1484
1485 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1486 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1487 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1488 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1489 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1490
1491 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1492 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1493 } else {
1494 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1495 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1496 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1497 }
1498 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1499 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1500 }
1501
1502 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1503 const struct pipe_framebuffer_state *state)
1504 {
1505 struct r600_resource_texture *rtex;
1506 struct r600_surface *surf;
1507 unsigned level, first_layer, pitch, slice, format;
1508 uint32_t db_z_info, stencil_info;
1509 uint64_t offset;
1510
1511 if (state->zsbuf == NULL) {
1512 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1513 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1514 return;
1515 }
1516
1517 surf = (struct r600_surface *)state->zsbuf;
1518 level = surf->base.u.tex.level;
1519 rtex = (struct r600_resource_texture*)surf->base.texture;
1520
1521 first_layer = surf->base.u.tex.first_layer;
1522 format = si_translate_dbformat(rtex->real_format);
1523
1524 offset = r600_resource_va(rctx->context.screen, surf->base.texture);
1525 offset += rtex->surface.level[level].offset;
1526 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1527 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1528 if (slice) {
1529 slice = slice - 1;
1530 }
1531 offset >>= 8;
1532
1533 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1534 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, offset);
1535 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, offset);
1536 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1537 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1538 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1539
1540 db_z_info = S_028040_FORMAT(format);
1541 stencil_info = S_028044_FORMAT(rtex->stencil != 0);
1542
1543 switch (format) {
1544 case V_028040_Z_16:
1545 db_z_info |= S_028040_TILE_MODE_INDEX(5);
1546 stencil_info |= S_028044_TILE_MODE_INDEX(5);
1547 break;
1548 case V_028040_Z_24:
1549 case V_028040_Z_32_FLOAT:
1550 db_z_info |= S_028040_TILE_MODE_INDEX(6);
1551 stencil_info |= S_028044_TILE_MODE_INDEX(6);
1552 break;
1553 default:
1554 db_z_info |= S_028040_TILE_MODE_INDEX(7);
1555 stencil_info |= S_028044_TILE_MODE_INDEX(7);
1556 }
1557
1558 if (rtex->stencil) {
1559 uint64_t stencil_offset =
1560 r600_texture_get_offset(rtex->stencil, level, first_layer);
1561
1562 stencil_offset += r600_resource_va(rctx->context.screen, (void*)rtex->stencil);
1563 stencil_offset >>= 8;
1564
1565 si_pm4_add_bo(pm4, &rtex->stencil->resource, RADEON_USAGE_READWRITE);
1566 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, stencil_offset);
1567 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, stencil_offset);
1568 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, stencil_info);
1569 } else {
1570 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1571 }
1572
1573 if (format != ~0U) {
1574 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1575 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, db_z_info);
1576 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1577 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1578
1579 } else {
1580 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1581 }
1582 }
1583
1584 static void si_set_framebuffer_state(struct pipe_context *ctx,
1585 const struct pipe_framebuffer_state *state)
1586 {
1587 struct r600_context *rctx = (struct r600_context *)ctx;
1588 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1589 uint32_t shader_mask, tl, br;
1590 int tl_x, tl_y, br_x, br_y;
1591
1592 if (pm4 == NULL)
1593 return;
1594
1595 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1596
1597 if (state->zsbuf)
1598 si_pm4_inval_zsbuf_cache(pm4);
1599
1600 util_copy_framebuffer_state(&rctx->framebuffer, state);
1601
1602 /* build states */
1603 rctx->have_depth_fb = 0;
1604 for (int i = 0; i < state->nr_cbufs; i++) {
1605 si_cb(rctx, pm4, state, i);
1606 }
1607 si_db(rctx, pm4, state);
1608
1609 shader_mask = 0;
1610 for (int i = 0; i < state->nr_cbufs; i++) {
1611 shader_mask |= 0xf << (i * 4);
1612 }
1613 tl_x = 0;
1614 tl_y = 0;
1615 br_x = state->width;
1616 br_y = state->height;
1617 #if 0 /* These shouldn't be necessary on SI, see PA_SC_ENHANCE register */
1618 /* EG hw workaround */
1619 if (br_x == 0)
1620 tl_x = 1;
1621 if (br_y == 0)
1622 tl_y = 1;
1623 /* cayman hw workaround */
1624 if (rctx->chip_class == CAYMAN) {
1625 if (br_x == 1 && br_y == 1)
1626 br_x = 2;
1627 }
1628 #endif
1629 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1630 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1631
1632 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1633 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1634 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1635 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1636 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1637 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1638 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1639 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1640 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1641 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1642 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1643 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1644
1645 si_pm4_set_state(rctx, framebuffer, pm4);
1646 si_update_fb_rs_state(rctx);
1647 si_update_fb_blend_state(rctx);
1648 }
1649
1650 /*
1651 * shaders
1652 */
1653
1654 static void *si_create_shader_state(struct pipe_context *ctx,
1655 const struct pipe_shader_state *state)
1656 {
1657 struct si_pipe_shader *shader = CALLOC_STRUCT(si_pipe_shader);
1658
1659 shader->tokens = tgsi_dup_tokens(state->tokens);
1660 shader->so = state->stream_output;
1661
1662 return shader;
1663 }
1664
1665 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1666 {
1667 struct r600_context *rctx = (struct r600_context *)ctx;
1668 struct si_pipe_shader *shader = state;
1669
1670 if (rctx->vs_shader == state)
1671 return;
1672
1673 rctx->shader_dirty = true;
1674 rctx->vs_shader = shader;
1675
1676 if (shader) {
1677 si_pm4_bind_state(rctx, vs, shader->pm4);
1678 }
1679 }
1680
1681 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1682 {
1683 struct r600_context *rctx = (struct r600_context *)ctx;
1684 struct si_pipe_shader *shader = state;
1685
1686 if (rctx->ps_shader == state)
1687 return;
1688
1689 rctx->shader_dirty = true;
1690 rctx->ps_shader = shader;
1691
1692 if (shader) {
1693 si_pm4_bind_state(rctx, ps, shader->pm4);
1694 }
1695 }
1696
1697 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
1698 {
1699 struct r600_context *rctx = (struct r600_context *)ctx;
1700 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1701
1702 if (rctx->vs_shader == shader) {
1703 rctx->vs_shader = NULL;
1704 }
1705
1706 si_pm4_delete_state(rctx, vs, shader->pm4);
1707 free(shader->tokens);
1708 si_pipe_shader_destroy(ctx, shader);
1709 free(shader);
1710 }
1711
1712 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
1713 {
1714 struct r600_context *rctx = (struct r600_context *)ctx;
1715 struct si_pipe_shader *shader = (struct si_pipe_shader *)state;
1716
1717 if (rctx->ps_shader == shader) {
1718 rctx->ps_shader = NULL;
1719 }
1720
1721 si_pm4_delete_state(rctx, ps, shader->pm4);
1722 free(shader->tokens);
1723 si_pipe_shader_destroy(ctx, shader);
1724 free(shader);
1725 }
1726
1727 /*
1728 * Samplers
1729 */
1730
1731 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
1732 struct pipe_resource *texture,
1733 const struct pipe_sampler_view *state)
1734 {
1735 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
1736 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1737 const struct util_format_description *desc = util_format_description(state->format);
1738 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
1739 unsigned format, num_format, /*endian,*/ tiling_index;
1740 uint32_t pitch = 0;
1741 unsigned char state_swizzle[4], swizzle[4];
1742 unsigned height, depth, width;
1743 int first_non_void;
1744 uint64_t va;
1745
1746 if (view == NULL)
1747 return NULL;
1748
1749 /* initialize base object */
1750 view->base = *state;
1751 view->base.texture = NULL;
1752 pipe_reference(NULL, &texture->reference);
1753 view->base.texture = texture;
1754 view->base.reference.count = 1;
1755 view->base.context = ctx;
1756
1757 state_swizzle[0] = state->swizzle_r;
1758 state_swizzle[1] = state->swizzle_g;
1759 state_swizzle[2] = state->swizzle_b;
1760 state_swizzle[3] = state->swizzle_a;
1761 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
1762
1763 first_non_void = util_format_get_first_non_void_channel(state->format);
1764 switch (desc->channel[first_non_void].type) {
1765 case UTIL_FORMAT_TYPE_FLOAT:
1766 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
1767 break;
1768 case UTIL_FORMAT_TYPE_SIGNED:
1769 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
1770 break;
1771 case UTIL_FORMAT_TYPE_UNSIGNED:
1772 default:
1773 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
1774 }
1775
1776 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
1777 if (format == ~0) {
1778 format = 0;
1779 }
1780
1781 if (tmp->depth && !tmp->is_flushing_texture) {
1782 r600_texture_depth_flush(ctx, texture, TRUE);
1783 tmp = tmp->flushed_depth_texture;
1784 }
1785
1786 /* not supported any more */
1787 //endian = si_colorformat_endian_swap(format);
1788
1789 height = texture->height0;
1790 depth = texture->depth0;
1791 width = texture->width0;
1792 pitch = align(tmp->pitch_in_blocks[0] *
1793 util_format_get_blockwidth(state->format), 8);
1794
1795 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1796 height = 1;
1797 depth = texture->array_size;
1798 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1799 depth = texture->array_size;
1800 }
1801
1802 tiling_index = 8;
1803 switch (tmp->surface.level[state->u.tex.first_level].mode) {
1804 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1805 tiling_index = 8;
1806 break;
1807 case RADEON_SURF_MODE_1D:
1808 tiling_index = 9;
1809 break;
1810 case RADEON_SURF_MODE_2D:
1811 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1812 switch (blocksize) {
1813 case 1:
1814 tiling_index = 10;
1815 break;
1816 case 2:
1817 tiling_index = 11;
1818 break;
1819 case 4:
1820 tiling_index = 12;
1821 break;
1822 }
1823 break;
1824 } else switch (blocksize) {
1825 case 1:
1826 tiling_index = 14;
1827 break;
1828 case 2:
1829 tiling_index = 15;
1830 break;
1831 case 4:
1832 tiling_index = 16;
1833 break;
1834 case 8:
1835 tiling_index = 17;
1836 break;
1837 default:
1838 tiling_index = 13;
1839 }
1840 break;
1841 }
1842
1843 va = r600_resource_va(ctx->screen, texture);
1844 if (state->u.tex.last_level) {
1845 view->state[0] = (va + tmp->offset[1]) >> 8;
1846 } else {
1847 view->state[0] = (va + tmp->offset[0]) >> 8;
1848 }
1849 view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
1850 S_008F14_DATA_FORMAT(format) |
1851 S_008F14_NUM_FORMAT(num_format));
1852 view->state[2] = (S_008F18_WIDTH(width - 1) |
1853 S_008F18_HEIGHT(height - 1));
1854 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
1855 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
1856 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
1857 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
1858 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
1859 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
1860 S_008F1C_TILING_INDEX(tiling_index) |
1861 S_008F1C_TYPE(si_tex_dim(texture->target)));
1862 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
1863 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
1864 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
1865 view->state[6] = 0;
1866 view->state[7] = 0;
1867
1868 return &view->base;
1869 }
1870
1871 static void si_sampler_view_destroy(struct pipe_context *ctx,
1872 struct pipe_sampler_view *state)
1873 {
1874 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
1875
1876 pipe_resource_reference(&state->texture, NULL);
1877 FREE(resource);
1878 }
1879
1880 static void *si_create_sampler_state(struct pipe_context *ctx,
1881 const struct pipe_sampler_state *state)
1882 {
1883 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
1884 union util_color uc;
1885 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
1886 unsigned border_color_type;
1887
1888 if (rstate == NULL) {
1889 return NULL;
1890 }
1891
1892 util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1893 switch (uc.ui) {
1894 case 0x000000FF:
1895 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1896 break;
1897 case 0x00000000:
1898 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1899 break;
1900 case 0xFFFFFFFF:
1901 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1902 break;
1903 default: /* Use border color pointer */
1904 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
1905 }
1906
1907 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
1908 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
1909 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
1910 (state->max_anisotropy & 0x7) << 9 | /* XXX */
1911 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
1912 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
1913 aniso_flag_offset << 16 | /* XXX */
1914 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
1915 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
1916 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
1917 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
1918 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
1919 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
1920 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
1921 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
1922
1923 #if 0
1924 if (border_color_type == 3) {
1925 si_pm4_set_reg(pm4, R_00A404_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]));
1926 si_pm4_set_reg(pm4, R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]));
1927 si_pm4_set_reg(pm4, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]));
1928 si_pm4_set_reg(pm4, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]));
1929 }
1930 #endif
1931 return rstate;
1932 }
1933
1934 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1935 struct pipe_sampler_view **views)
1936 {
1937 assert(count == 0);
1938 }
1939
1940 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1941 struct pipe_sampler_view **views)
1942 {
1943 struct r600_context *rctx = (struct r600_context *)ctx;
1944 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
1945 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1946 struct si_resource *bo;
1947 int i;
1948 int has_depth = 0;
1949 uint64_t va;
1950 char *ptr;
1951
1952 if (!count)
1953 goto out;
1954
1955 si_pm4_inval_texture_cache(pm4);
1956
1957 bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
1958 count * sizeof(resource[0]->state));
1959 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
1960
1961 for (i = 0; i < count; i++, ptr += sizeof(resource[0]->state)) {
1962 struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
1963
1964 pipe_sampler_view_reference(
1965 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1966 views[i]);
1967
1968 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
1969
1970 if (resource[i]) {
1971 if (tex->depth)
1972 has_depth = 1;
1973
1974 memcpy(ptr, resource[i]->state, sizeof(resource[0]->state));
1975 } else
1976 memset(ptr, 0, sizeof(resource[0]->state));
1977 }
1978
1979 rctx->ws->buffer_unmap(bo->cs_buf);
1980
1981 for (i = count; i < NUM_TEX_UNITS; i++) {
1982 if (rctx->ps_samplers.views[i])
1983 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1984 }
1985
1986 va = r600_resource_va(ctx->screen, (void *)bo);
1987 si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
1988 si_pm4_set_reg(pm4, R_00B040_SPI_SHADER_USER_DATA_PS_4, va);
1989 si_pm4_set_reg(pm4, R_00B044_SPI_SHADER_USER_DATA_PS_5, va >> 32);
1990
1991 out:
1992 si_pm4_set_state(rctx, ps_sampler_views, pm4);
1993 rctx->have_depth_texture = has_depth;
1994 rctx->ps_samplers.n_views = count;
1995 }
1996
1997 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1998 {
1999 assert(count == 0);
2000 }
2001
2002 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2003 {
2004 struct r600_context *rctx = (struct r600_context *)ctx;
2005 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2006 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2007 struct si_resource *bo;
2008 uint64_t va;
2009 char *ptr;
2010 int i;
2011
2012 if (!count)
2013 goto out;
2014
2015 si_pm4_inval_texture_cache(pm4);
2016
2017 bo = si_resource_create_custom(ctx->screen, PIPE_USAGE_IMMUTABLE,
2018 count * sizeof(rstates[0]->val));
2019 ptr = rctx->ws->buffer_map(bo->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
2020
2021 for (i = 0; i < count; i++, ptr += sizeof(rstates[0]->val)) {
2022 memcpy(ptr, rstates[i]->val, sizeof(rstates[0]->val));
2023 }
2024
2025 rctx->ws->buffer_unmap(bo->cs_buf);
2026
2027 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
2028
2029 va = r600_resource_va(ctx->screen, (void *)bo);
2030 si_pm4_add_bo(pm4, bo, RADEON_USAGE_READ);
2031 si_pm4_set_reg(pm4, R_00B038_SPI_SHADER_USER_DATA_PS_2, va);
2032 si_pm4_set_reg(pm4, R_00B03C_SPI_SHADER_USER_DATA_PS_3, va >> 32);
2033
2034 out:
2035 si_pm4_set_state(rctx, ps_sampler, pm4);
2036 rctx->ps_samplers.n_samplers = count;
2037 }
2038
2039 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2040 {
2041 }
2042
2043 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2044 {
2045 free(state);
2046 }
2047
2048 /*
2049 * Constants
2050 */
2051 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2052 struct pipe_constant_buffer *cb)
2053 {
2054 struct r600_context *rctx = (struct r600_context *)ctx;
2055 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2056 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2057 uint64_t va_offset;
2058 uint32_t offset;
2059
2060 /* Note that the state tracker can unbind constant buffers by
2061 * passing NULL here.
2062 */
2063 if (cb == NULL) {
2064 FREE(pm4);
2065 return;
2066 }
2067
2068 si_pm4_inval_shader_cache(pm4);
2069
2070 if (cb->user_buffer)
2071 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2072 else
2073 offset = 0;
2074 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2075 va_offset += offset;
2076
2077 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2078
2079 switch (shader) {
2080 case PIPE_SHADER_VERTEX:
2081 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, va_offset);
2082 si_pm4_set_reg(pm4, R_00B134_SPI_SHADER_USER_DATA_VS_1, va_offset >> 32);
2083 si_pm4_set_state(rctx, vs_const, pm4);
2084 break;
2085
2086 case PIPE_SHADER_FRAGMENT:
2087 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, va_offset);
2088 si_pm4_set_reg(pm4, R_00B034_SPI_SHADER_USER_DATA_PS_1, va_offset >> 32);
2089 si_pm4_set_state(rctx, ps_const, pm4);
2090 break;
2091
2092 default:
2093 R600_ERR("unsupported %d\n", shader);
2094 return;
2095 }
2096
2097 if (cb->buffer != &rbuffer->b.b)
2098 si_resource_reference(&rbuffer, NULL);
2099 }
2100
2101 /*
2102 * Vertex elements & buffers
2103 */
2104
2105 static void *si_create_vertex_elements(struct pipe_context *ctx,
2106 unsigned count,
2107 const struct pipe_vertex_element *elements)
2108 {
2109 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2110 int i;
2111
2112 assert(count < PIPE_MAX_ATTRIBS);
2113 if (!v)
2114 return NULL;
2115
2116 v->count = count;
2117 for (i = 0; i < count; ++i) {
2118 const struct util_format_description *desc;
2119 unsigned data_format, num_format;
2120 int first_non_void;
2121
2122 desc = util_format_description(elements[i].src_format);
2123 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2124 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2125 desc, first_non_void);
2126
2127 switch (desc->channel[first_non_void].type) {
2128 case UTIL_FORMAT_TYPE_FIXED:
2129 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2130 break;
2131 case UTIL_FORMAT_TYPE_SIGNED:
2132 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2133 break;
2134 case UTIL_FORMAT_TYPE_UNSIGNED:
2135 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2136 break;
2137 case UTIL_FORMAT_TYPE_FLOAT:
2138 default:
2139 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2140 }
2141
2142 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2143 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2144 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2145 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2146 S_008F0C_NUM_FORMAT(num_format) |
2147 S_008F0C_DATA_FORMAT(data_format);
2148 }
2149 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2150
2151 return v;
2152 }
2153
2154 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2155 {
2156 struct r600_context *rctx = (struct r600_context *)ctx;
2157 struct si_vertex_element *v = (struct si_vertex_element*)state;
2158
2159 rctx->vertex_elements = v;
2160 }
2161
2162 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2163 {
2164 struct r600_context *rctx = (struct r600_context *)ctx;
2165
2166 if (rctx->vertex_elements == state)
2167 rctx->vertex_elements = NULL;
2168 FREE(state);
2169 }
2170
2171 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
2172 const struct pipe_vertex_buffer *buffers)
2173 {
2174 struct r600_context *rctx = (struct r600_context *)ctx;
2175
2176 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
2177 }
2178
2179 static void si_set_index_buffer(struct pipe_context *ctx,
2180 const struct pipe_index_buffer *ib)
2181 {
2182 struct r600_context *rctx = (struct r600_context *)ctx;
2183
2184 if (ib) {
2185 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2186 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2187 } else {
2188 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2189 }
2190 }
2191
2192 /*
2193 * Stream out
2194 */
2195
2196 static struct pipe_stream_output_target *
2197 si_create_so_target(struct pipe_context *ctx,
2198 struct pipe_resource *buffer,
2199 unsigned buffer_offset,
2200 unsigned buffer_size)
2201 {
2202 struct r600_context *rctx = (struct r600_context *)ctx;
2203 struct r600_so_target *t;
2204 void *ptr;
2205
2206 t = CALLOC_STRUCT(r600_so_target);
2207 if (!t) {
2208 return NULL;
2209 }
2210
2211 t->b.reference.count = 1;
2212 t->b.context = ctx;
2213 pipe_resource_reference(&t->b.buffer, buffer);
2214 t->b.buffer_offset = buffer_offset;
2215 t->b.buffer_size = buffer_size;
2216
2217 t->filled_size = si_resource_create_custom(ctx->screen, PIPE_USAGE_STATIC, 4);
2218 ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
2219 memset(ptr, 0, t->filled_size->buf->size);
2220 rctx->ws->buffer_unmap(t->filled_size->cs_buf);
2221
2222 return &t->b;
2223 }
2224
2225 static void si_so_target_destroy(struct pipe_context *ctx,
2226 struct pipe_stream_output_target *target)
2227 {
2228 struct r600_so_target *t = (struct r600_so_target*)target;
2229 pipe_resource_reference(&t->b.buffer, NULL);
2230 si_resource_reference(&t->filled_size, NULL);
2231 FREE(t);
2232 }
2233
2234 static void si_set_so_targets(struct pipe_context *ctx,
2235 unsigned num_targets,
2236 struct pipe_stream_output_target **targets,
2237 unsigned append_bitmask)
2238 {
2239 struct r600_context *rctx = (struct r600_context *)ctx;
2240 unsigned i;
2241
2242 /* Stop streamout. */
2243 if (rctx->num_so_targets) {
2244 r600_context_streamout_end(rctx);
2245 }
2246
2247 /* Set the new targets. */
2248 for (i = 0; i < num_targets; i++) {
2249 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
2250 }
2251 for (; i < rctx->num_so_targets; i++) {
2252 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
2253 }
2254
2255 rctx->num_so_targets = num_targets;
2256 rctx->streamout_start = num_targets != 0;
2257 rctx->streamout_append_bitmask = append_bitmask;
2258 }
2259
2260 /*
2261 * Misc
2262 */
2263 static void si_set_polygon_stipple(struct pipe_context *ctx,
2264 const struct pipe_poly_stipple *state)
2265 {
2266 }
2267
2268 static void si_texture_barrier(struct pipe_context *ctx)
2269 {
2270 struct r600_context *rctx = (struct r600_context *)ctx;
2271 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2272
2273 si_pm4_inval_texture_cache(pm4);
2274 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2275 si_pm4_set_state(rctx, texture_barrier, pm4);
2276 }
2277
2278 void si_init_state_functions(struct r600_context *rctx)
2279 {
2280 rctx->context.create_blend_state = si_create_blend_state;
2281 rctx->context.bind_blend_state = si_bind_blend_state;
2282 rctx->context.delete_blend_state = si_delete_blend_state;
2283 rctx->context.set_blend_color = si_set_blend_color;
2284
2285 rctx->context.create_rasterizer_state = si_create_rs_state;
2286 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2287 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2288
2289 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2290 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2291 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2292 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
2293
2294 rctx->context.set_clip_state = si_set_clip_state;
2295 rctx->context.set_scissor_state = si_set_scissor_state;
2296 rctx->context.set_viewport_state = si_set_viewport_state;
2297 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2298
2299 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2300
2301 rctx->context.create_vs_state = si_create_shader_state;
2302 rctx->context.create_fs_state = si_create_shader_state;
2303 rctx->context.bind_vs_state = si_bind_vs_shader;
2304 rctx->context.bind_fs_state = si_bind_ps_shader;
2305 rctx->context.delete_vs_state = si_delete_vs_shader;
2306 rctx->context.delete_fs_state = si_delete_ps_shader;
2307
2308 rctx->context.create_sampler_state = si_create_sampler_state;
2309 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2310 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2311 rctx->context.delete_sampler_state = si_delete_sampler_state;
2312
2313 rctx->context.create_sampler_view = si_create_sampler_view;
2314 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2315 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2316 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2317
2318 rctx->context.set_sample_mask = si_set_sample_mask;
2319
2320 rctx->context.set_constant_buffer = si_set_constant_buffer;
2321
2322 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2323 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2324 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2325 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2326 rctx->context.set_index_buffer = si_set_index_buffer;
2327
2328 rctx->context.create_stream_output_target = si_create_so_target;
2329 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2330 rctx->context.set_stream_output_targets = si_set_so_targets;
2331
2332 rctx->context.texture_barrier = si_texture_barrier;
2333 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2334
2335 rctx->context.draw_vbo = si_draw_vbo;
2336 }
2337
2338 void si_init_config(struct r600_context *rctx)
2339 {
2340 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2341
2342 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2343
2344 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2345 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2346 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2347 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2348 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2349 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2350 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2351 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2352 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2353 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2354 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2355 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2356 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2357 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2358 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2359 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2360 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2361 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2362 S_028AA8_SWITCH_ON_EOP(1) |
2363 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2364 S_028AA8_PRIMGROUP_SIZE(63));
2365 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2366 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2367 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2368
2369 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2370 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2371 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2372
2373 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2374
2375 si_pm4_set_state(rctx, init, pm4);
2376 }