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radeonsi: set correct pipe config for Hawaii in DB
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "radeonsi_pipe.h"
38 #include "radeonsi_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(uint32_t nbanks)
44 {
45 switch (nbanks) {
46 case 2:
47 return V_02803C_ADDR_SURF_2_BANK;
48 case 4:
49 return V_02803C_ADDR_SURF_4_BANK;
50 case 8:
51 default:
52 return V_02803C_ADDR_SURF_8_BANK;
53 case 16:
54 return V_02803C_ADDR_SURF_16_BANK;
55 }
56 }
57
58
59 static unsigned cik_tile_split(unsigned tile_split)
60 {
61 switch (tile_split) {
62 case 64:
63 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
64 break;
65 case 128:
66 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
67 break;
68 case 256:
69 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
70 break;
71 case 512:
72 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
73 break;
74 default:
75 case 1024:
76 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
77 break;
78 case 2048:
79 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
80 break;
81 case 4096:
82 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
83 break;
84 }
85 return tile_split;
86 }
87
88 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
89 {
90 switch (macro_tile_aspect) {
91 default:
92 case 1:
93 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
94 break;
95 case 2:
96 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
97 break;
98 case 4:
99 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
100 break;
101 case 8:
102 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
103 break;
104 }
105 return macro_tile_aspect;
106 }
107
108 static unsigned cik_bank_wh(unsigned bankwh)
109 {
110 switch (bankwh) {
111 default:
112 case 1:
113 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
114 break;
115 case 2:
116 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
117 break;
118 case 4:
119 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
120 break;
121 case 8:
122 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
123 break;
124 }
125 return bankwh;
126 }
127
128 static unsigned cik_db_pipe_config(struct r600_screen *rscreen, unsigned tile_mode)
129 {
130 if (rscreen->b.info.si_tile_mode_array_valid) {
131 uint32_t gb_tile_mode = rscreen->b.info.si_tile_mode_array[tile_mode];
132
133 return G_009910_PIPE_CONFIG(gb_tile_mode);
134 }
135
136 /* This is probably broken for a lot of chips, but it's only used
137 * if the kernel cannot return the tile mode array for CIK. */
138 switch (rscreen->b.info.r600_num_tile_pipes) {
139 case 16:
140 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
141 case 8:
142 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
143 case 4:
144 default:
145 if (rscreen->b.info.r600_num_backends == 4)
146 return V_02803C_X_ADDR_SURF_P4_16X16;
147 else
148 return V_02803C_X_ADDR_SURF_P4_8X16;
149 case 2:
150 return V_02803C_ADDR_SURF_P2;
151 }
152 }
153
154 /*
155 * inferred framebuffer and blender state
156 */
157 static void si_update_fb_blend_state(struct r600_context *rctx)
158 {
159 struct si_pm4_state *pm4;
160 struct si_state_blend *blend = rctx->queued.named.blend;
161 uint32_t mask;
162
163 if (blend == NULL)
164 return;
165
166 pm4 = si_pm4_alloc_state(rctx);
167 if (pm4 == NULL)
168 return;
169
170 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
171 mask &= blend->cb_target_mask;
172 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
173
174 si_pm4_set_state(rctx, fb_blend, pm4);
175 }
176
177 /*
178 * Blender functions
179 */
180
181 static uint32_t si_translate_blend_function(int blend_func)
182 {
183 switch (blend_func) {
184 case PIPE_BLEND_ADD:
185 return V_028780_COMB_DST_PLUS_SRC;
186 case PIPE_BLEND_SUBTRACT:
187 return V_028780_COMB_SRC_MINUS_DST;
188 case PIPE_BLEND_REVERSE_SUBTRACT:
189 return V_028780_COMB_DST_MINUS_SRC;
190 case PIPE_BLEND_MIN:
191 return V_028780_COMB_MIN_DST_SRC;
192 case PIPE_BLEND_MAX:
193 return V_028780_COMB_MAX_DST_SRC;
194 default:
195 R600_ERR("Unknown blend function %d\n", blend_func);
196 assert(0);
197 break;
198 }
199 return 0;
200 }
201
202 static uint32_t si_translate_blend_factor(int blend_fact)
203 {
204 switch (blend_fact) {
205 case PIPE_BLENDFACTOR_ONE:
206 return V_028780_BLEND_ONE;
207 case PIPE_BLENDFACTOR_SRC_COLOR:
208 return V_028780_BLEND_SRC_COLOR;
209 case PIPE_BLENDFACTOR_SRC_ALPHA:
210 return V_028780_BLEND_SRC_ALPHA;
211 case PIPE_BLENDFACTOR_DST_ALPHA:
212 return V_028780_BLEND_DST_ALPHA;
213 case PIPE_BLENDFACTOR_DST_COLOR:
214 return V_028780_BLEND_DST_COLOR;
215 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
216 return V_028780_BLEND_SRC_ALPHA_SATURATE;
217 case PIPE_BLENDFACTOR_CONST_COLOR:
218 return V_028780_BLEND_CONSTANT_COLOR;
219 case PIPE_BLENDFACTOR_CONST_ALPHA:
220 return V_028780_BLEND_CONSTANT_ALPHA;
221 case PIPE_BLENDFACTOR_ZERO:
222 return V_028780_BLEND_ZERO;
223 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
224 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
225 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
226 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
227 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
228 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
229 case PIPE_BLENDFACTOR_INV_DST_COLOR:
230 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
231 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
232 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
233 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
234 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
235 case PIPE_BLENDFACTOR_SRC1_COLOR:
236 return V_028780_BLEND_SRC1_COLOR;
237 case PIPE_BLENDFACTOR_SRC1_ALPHA:
238 return V_028780_BLEND_SRC1_ALPHA;
239 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
240 return V_028780_BLEND_INV_SRC1_COLOR;
241 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
242 return V_028780_BLEND_INV_SRC1_ALPHA;
243 default:
244 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
245 assert(0);
246 break;
247 }
248 return 0;
249 }
250
251 static void *si_create_blend_state_mode(struct pipe_context *ctx,
252 const struct pipe_blend_state *state,
253 unsigned mode)
254 {
255 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
256 struct si_pm4_state *pm4 = &blend->pm4;
257
258 uint32_t color_control = 0;
259
260 if (blend == NULL)
261 return NULL;
262
263 blend->alpha_to_one = state->alpha_to_one;
264
265 if (state->logicop_enable) {
266 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
267 } else {
268 color_control |= S_028808_ROP3(0xcc);
269 }
270
271 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
272 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
273 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
275 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
276 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
277
278 blend->cb_target_mask = 0;
279 for (int i = 0; i < 8; i++) {
280 /* state->rt entries > 0 only written if independent blending */
281 const int j = state->independent_blend_enable ? i : 0;
282
283 unsigned eqRGB = state->rt[j].rgb_func;
284 unsigned srcRGB = state->rt[j].rgb_src_factor;
285 unsigned dstRGB = state->rt[j].rgb_dst_factor;
286 unsigned eqA = state->rt[j].alpha_func;
287 unsigned srcA = state->rt[j].alpha_src_factor;
288 unsigned dstA = state->rt[j].alpha_dst_factor;
289
290 unsigned blend_cntl = 0;
291
292 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
293 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
294
295 if (!state->rt[j].blend_enable) {
296 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
297 continue;
298 }
299
300 blend_cntl |= S_028780_ENABLE(1);
301 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
302 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
303 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
304
305 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
306 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
307 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
308 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
309 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
310 }
311 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
312 }
313
314 if (blend->cb_target_mask) {
315 color_control |= S_028808_MODE(mode);
316 } else {
317 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
318 }
319 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
320
321 return blend;
322 }
323
324 static void *si_create_blend_state(struct pipe_context *ctx,
325 const struct pipe_blend_state *state)
326 {
327 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
328 }
329
330 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
331 {
332 struct r600_context *rctx = (struct r600_context *)ctx;
333 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
334 si_update_fb_blend_state(rctx);
335 }
336
337 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
338 {
339 struct r600_context *rctx = (struct r600_context *)ctx;
340 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
341 }
342
343 static void si_set_blend_color(struct pipe_context *ctx,
344 const struct pipe_blend_color *state)
345 {
346 struct r600_context *rctx = (struct r600_context *)ctx;
347 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
348
349 if (pm4 == NULL)
350 return;
351
352 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
353 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
354 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
355 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
356
357 si_pm4_set_state(rctx, blend_color, pm4);
358 }
359
360 /*
361 * Clipping, scissors and viewport
362 */
363
364 static void si_set_clip_state(struct pipe_context *ctx,
365 const struct pipe_clip_state *state)
366 {
367 struct r600_context *rctx = (struct r600_context *)ctx;
368 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
369 struct pipe_constant_buffer cb;
370
371 if (pm4 == NULL)
372 return;
373
374 for (int i = 0; i < 6; i++) {
375 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
376 fui(state->ucp[i][0]));
377 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
378 fui(state->ucp[i][1]));
379 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
380 fui(state->ucp[i][2]));
381 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
382 fui(state->ucp[i][3]));
383 }
384
385 cb.buffer = NULL;
386 cb.user_buffer = state->ucp;
387 cb.buffer_offset = 0;
388 cb.buffer_size = 4*4*8;
389 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
390 pipe_resource_reference(&cb.buffer, NULL);
391
392 si_pm4_set_state(rctx, clip, pm4);
393 }
394
395 static void si_set_scissor_states(struct pipe_context *ctx,
396 unsigned start_slot,
397 unsigned num_scissors,
398 const struct pipe_scissor_state *state)
399 {
400 struct r600_context *rctx = (struct r600_context *)ctx;
401 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
402 uint32_t tl, br;
403
404 if (pm4 == NULL)
405 return;
406
407 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
408 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
409 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
410 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
411 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
412 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
413 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
414 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
415 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
416 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
417
418 si_pm4_set_state(rctx, scissor, pm4);
419 }
420
421 static void si_set_viewport_states(struct pipe_context *ctx,
422 unsigned start_slot,
423 unsigned num_viewports,
424 const struct pipe_viewport_state *state)
425 {
426 struct r600_context *rctx = (struct r600_context *)ctx;
427 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
428 struct si_pm4_state *pm4 = &viewport->pm4;
429
430 if (viewport == NULL)
431 return;
432
433 viewport->viewport = *state;
434 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
435 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
436 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
437 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
438 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
439 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
440
441 si_pm4_set_state(rctx, viewport, viewport);
442 }
443
444 /*
445 * inferred state between framebuffer and rasterizer
446 */
447 static void si_update_fb_rs_state(struct r600_context *rctx)
448 {
449 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
450 struct si_pm4_state *pm4;
451 unsigned offset_db_fmt_cntl = 0, depth;
452 float offset_units;
453
454 if (!rs || !rctx->framebuffer.zsbuf)
455 return;
456
457 offset_units = rctx->queued.named.rasterizer->offset_units;
458 switch (rctx->framebuffer.zsbuf->texture->format) {
459 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
460 case PIPE_FORMAT_X8Z24_UNORM:
461 case PIPE_FORMAT_Z24X8_UNORM:
462 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
463 depth = -24;
464 offset_units *= 2.0f;
465 break;
466 case PIPE_FORMAT_Z32_FLOAT:
467 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
468 depth = -23;
469 offset_units *= 1.0f;
470 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
471 break;
472 case PIPE_FORMAT_Z16_UNORM:
473 depth = -16;
474 offset_units *= 4.0f;
475 break;
476 default:
477 return;
478 }
479
480 pm4 = si_pm4_alloc_state(rctx);
481
482 if (pm4 == NULL)
483 return;
484
485 /* FIXME some of those reg can be computed with cso */
486 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
487 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
488 fui(rctx->queued.named.rasterizer->offset_scale));
489 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
490 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
491 fui(rctx->queued.named.rasterizer->offset_scale));
492 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
493 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
494
495 si_pm4_set_state(rctx, fb_rs, pm4);
496 }
497
498 /*
499 * Rasterizer
500 */
501
502 static uint32_t si_translate_fill(uint32_t func)
503 {
504 switch(func) {
505 case PIPE_POLYGON_MODE_FILL:
506 return V_028814_X_DRAW_TRIANGLES;
507 case PIPE_POLYGON_MODE_LINE:
508 return V_028814_X_DRAW_LINES;
509 case PIPE_POLYGON_MODE_POINT:
510 return V_028814_X_DRAW_POINTS;
511 default:
512 assert(0);
513 return V_028814_X_DRAW_POINTS;
514 }
515 }
516
517 static void *si_create_rs_state(struct pipe_context *ctx,
518 const struct pipe_rasterizer_state *state)
519 {
520 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
521 struct si_pm4_state *pm4 = &rs->pm4;
522 unsigned tmp;
523 unsigned prov_vtx = 1, polygon_dual_mode;
524 unsigned clip_rule;
525 float psize_min, psize_max;
526
527 if (rs == NULL) {
528 return NULL;
529 }
530
531 rs->two_side = state->light_twoside;
532 rs->multisample_enable = state->multisample;
533 rs->clip_plane_enable = state->clip_plane_enable;
534 rs->line_stipple_enable = state->line_stipple_enable;
535
536 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
537 state->fill_back != PIPE_POLYGON_MODE_FILL);
538
539 if (state->flatshade_first)
540 prov_vtx = 0;
541
542 rs->flatshade = state->flatshade;
543 rs->sprite_coord_enable = state->sprite_coord_enable;
544 rs->pa_sc_line_stipple = state->line_stipple_enable ?
545 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
546 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
547 rs->pa_su_sc_mode_cntl =
548 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
549 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
550 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
551 S_028814_FACE(!state->front_ccw) |
552 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
553 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
554 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
555 S_028814_POLY_MODE(polygon_dual_mode) |
556 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
557 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
558 rs->pa_cl_clip_cntl =
559 S_028810_PS_UCP_MODE(3) |
560 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
561 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
562 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
563 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
564
565 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
566
567 /* offset */
568 rs->offset_units = state->offset_units;
569 rs->offset_scale = state->offset_scale * 12.0f;
570
571 tmp = S_0286D4_FLAT_SHADE_ENA(1);
572 if (state->sprite_coord_enable) {
573 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
574 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
575 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
576 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
577 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
578 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
579 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
580 }
581 }
582 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
583
584 /* point size 12.4 fixed point */
585 tmp = (unsigned)(state->point_size * 8.0);
586 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
587
588 if (state->point_size_per_vertex) {
589 psize_min = util_get_min_point_size(state);
590 psize_max = 8192;
591 } else {
592 /* Force the point size to be as if the vertex output was disabled. */
593 psize_min = state->point_size;
594 psize_max = state->point_size;
595 }
596 /* Divide by two, because 0.5 = 1 pixel. */
597 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
598 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
599 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
600
601 tmp = (unsigned)state->line_width * 8;
602 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
603 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
604 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
605 S_028A48_MSAA_ENABLE(state->multisample));
606
607 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
608 S_028BE4_PIX_CENTER(state->half_pixel_center) |
609 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
610
611 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
612 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
613
614 return rs;
615 }
616
617 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
618 {
619 struct r600_context *rctx = (struct r600_context *)ctx;
620 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
621
622 if (state == NULL)
623 return;
624
625 // TODO
626 rctx->sprite_coord_enable = rs->sprite_coord_enable;
627 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
628 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
629
630 si_pm4_bind_state(rctx, rasterizer, rs);
631 si_update_fb_rs_state(rctx);
632 }
633
634 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
635 {
636 struct r600_context *rctx = (struct r600_context *)ctx;
637 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
638 }
639
640 /*
641 * infeered state between dsa and stencil ref
642 */
643 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
644 {
645 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
646 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
647 struct si_state_dsa *dsa = rctx->queued.named.dsa;
648
649 if (pm4 == NULL)
650 return;
651
652 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
653 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
654 S_028430_STENCILMASK(dsa->valuemask[0]) |
655 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
656 S_028430_STENCILOPVAL(1));
657 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
658 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
659 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
660 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
661 S_028434_STENCILOPVAL_BF(1));
662
663 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
664 }
665
666 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
667 const struct pipe_stencil_ref *state)
668 {
669 struct r600_context *rctx = (struct r600_context *)ctx;
670 rctx->stencil_ref = *state;
671 si_update_dsa_stencil_ref(rctx);
672 }
673
674
675 /*
676 * DSA
677 */
678
679 static uint32_t si_translate_stencil_op(int s_op)
680 {
681 switch (s_op) {
682 case PIPE_STENCIL_OP_KEEP:
683 return V_02842C_STENCIL_KEEP;
684 case PIPE_STENCIL_OP_ZERO:
685 return V_02842C_STENCIL_ZERO;
686 case PIPE_STENCIL_OP_REPLACE:
687 return V_02842C_STENCIL_REPLACE_TEST;
688 case PIPE_STENCIL_OP_INCR:
689 return V_02842C_STENCIL_ADD_CLAMP;
690 case PIPE_STENCIL_OP_DECR:
691 return V_02842C_STENCIL_SUB_CLAMP;
692 case PIPE_STENCIL_OP_INCR_WRAP:
693 return V_02842C_STENCIL_ADD_WRAP;
694 case PIPE_STENCIL_OP_DECR_WRAP:
695 return V_02842C_STENCIL_SUB_WRAP;
696 case PIPE_STENCIL_OP_INVERT:
697 return V_02842C_STENCIL_INVERT;
698 default:
699 R600_ERR("Unknown stencil op %d", s_op);
700 assert(0);
701 break;
702 }
703 return 0;
704 }
705
706 static void *si_create_dsa_state(struct pipe_context *ctx,
707 const struct pipe_depth_stencil_alpha_state *state)
708 {
709 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
710 struct si_pm4_state *pm4 = &dsa->pm4;
711 unsigned db_depth_control;
712 unsigned db_render_control;
713 uint32_t db_stencil_control = 0;
714
715 if (dsa == NULL) {
716 return NULL;
717 }
718
719 dsa->valuemask[0] = state->stencil[0].valuemask;
720 dsa->valuemask[1] = state->stencil[1].valuemask;
721 dsa->writemask[0] = state->stencil[0].writemask;
722 dsa->writemask[1] = state->stencil[1].writemask;
723
724 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
725 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
726 S_028800_ZFUNC(state->depth.func);
727
728 /* stencil */
729 if (state->stencil[0].enabled) {
730 db_depth_control |= S_028800_STENCIL_ENABLE(1);
731 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
732 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
733 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
734 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
735
736 if (state->stencil[1].enabled) {
737 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
738 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
739 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
740 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
741 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
742 }
743 }
744
745 /* alpha */
746 if (state->alpha.enabled) {
747 dsa->alpha_func = state->alpha.func;
748 dsa->alpha_ref = state->alpha.ref_value;
749
750 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
751 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
752 } else {
753 dsa->alpha_func = PIPE_FUNC_ALWAYS;
754 }
755
756 /* misc */
757 db_render_control = 0;
758 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
759 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
760 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
761
762 return dsa;
763 }
764
765 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
766 {
767 struct r600_context *rctx = (struct r600_context *)ctx;
768 struct si_state_dsa *dsa = state;
769
770 if (state == NULL)
771 return;
772
773 si_pm4_bind_state(rctx, dsa, dsa);
774 si_update_dsa_stencil_ref(rctx);
775 }
776
777 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
778 {
779 struct r600_context *rctx = (struct r600_context *)ctx;
780 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
781 }
782
783 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
784 bool copy_stencil, int sample)
785 {
786 struct pipe_depth_stencil_alpha_state dsa;
787 struct si_state_dsa *state;
788
789 memset(&dsa, 0, sizeof(dsa));
790
791 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
792 if (copy_depth || copy_stencil) {
793 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
794 S_028000_DEPTH_COPY(copy_depth) |
795 S_028000_STENCIL_COPY(copy_stencil) |
796 S_028000_COPY_CENTROID(1) |
797 S_028000_COPY_SAMPLE(sample));
798 } else {
799 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
800 S_028000_DEPTH_COMPRESS_DISABLE(1) |
801 S_028000_STENCIL_COMPRESS_DISABLE(1));
802 }
803
804 return state;
805 }
806
807 /*
808 * format translation
809 */
810 static uint32_t si_translate_colorformat(enum pipe_format format)
811 {
812 const struct util_format_description *desc = util_format_description(format);
813
814 #define HAS_SIZE(x,y,z,w) \
815 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
816 desc->channel[2].size == (z) && desc->channel[3].size == (w))
817
818 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
819 return V_028C70_COLOR_10_11_11;
820
821 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
822 return V_028C70_COLOR_INVALID;
823
824 switch (desc->nr_channels) {
825 case 1:
826 switch (desc->channel[0].size) {
827 case 8:
828 return V_028C70_COLOR_8;
829 case 16:
830 return V_028C70_COLOR_16;
831 case 32:
832 return V_028C70_COLOR_32;
833 }
834 break;
835 case 2:
836 if (desc->channel[0].size == desc->channel[1].size) {
837 switch (desc->channel[0].size) {
838 case 8:
839 return V_028C70_COLOR_8_8;
840 case 16:
841 return V_028C70_COLOR_16_16;
842 case 32:
843 return V_028C70_COLOR_32_32;
844 }
845 } else if (HAS_SIZE(8,24,0,0)) {
846 return V_028C70_COLOR_24_8;
847 } else if (HAS_SIZE(24,8,0,0)) {
848 return V_028C70_COLOR_8_24;
849 }
850 break;
851 case 3:
852 if (HAS_SIZE(5,6,5,0)) {
853 return V_028C70_COLOR_5_6_5;
854 } else if (HAS_SIZE(32,8,24,0)) {
855 return V_028C70_COLOR_X24_8_32_FLOAT;
856 }
857 break;
858 case 4:
859 if (desc->channel[0].size == desc->channel[1].size &&
860 desc->channel[0].size == desc->channel[2].size &&
861 desc->channel[0].size == desc->channel[3].size) {
862 switch (desc->channel[0].size) {
863 case 4:
864 return V_028C70_COLOR_4_4_4_4;
865 case 8:
866 return V_028C70_COLOR_8_8_8_8;
867 case 16:
868 return V_028C70_COLOR_16_16_16_16;
869 case 32:
870 return V_028C70_COLOR_32_32_32_32;
871 }
872 } else if (HAS_SIZE(5,5,5,1)) {
873 return V_028C70_COLOR_1_5_5_5;
874 } else if (HAS_SIZE(10,10,10,2)) {
875 return V_028C70_COLOR_2_10_10_10;
876 }
877 break;
878 }
879 return V_028C70_COLOR_INVALID;
880 }
881
882 static uint32_t si_translate_colorswap(enum pipe_format format)
883 {
884 const struct util_format_description *desc = util_format_description(format);
885
886 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
887
888 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
889 return V_028C70_SWAP_STD;
890
891 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
892 return ~0;
893
894 switch (desc->nr_channels) {
895 case 1:
896 if (HAS_SWIZZLE(0,X))
897 return V_028C70_SWAP_STD; /* X___ */
898 else if (HAS_SWIZZLE(3,X))
899 return V_028C70_SWAP_ALT_REV; /* ___X */
900 break;
901 case 2:
902 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
903 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
904 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
905 return V_028C70_SWAP_STD; /* XY__ */
906 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
907 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
908 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
909 return V_028C70_SWAP_STD_REV; /* YX__ */
910 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
911 return V_028C70_SWAP_ALT; /* X__Y */
912 break;
913 case 3:
914 if (HAS_SWIZZLE(0,X))
915 return V_028C70_SWAP_STD; /* XYZ */
916 else if (HAS_SWIZZLE(0,Z))
917 return V_028C70_SWAP_STD_REV; /* ZYX */
918 break;
919 case 4:
920 /* check the middle channels, the 1st and 4th channel can be NONE */
921 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
922 return V_028C70_SWAP_STD; /* XYZW */
923 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
924 return V_028C70_SWAP_STD_REV; /* WZYX */
925 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
926 return V_028C70_SWAP_ALT; /* ZYXW */
927 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
928 return V_028C70_SWAP_ALT_REV; /* WXYZ */
929 break;
930 }
931 return ~0U;
932 }
933
934 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
935 {
936 if (R600_BIG_ENDIAN) {
937 switch(colorformat) {
938 /* 8-bit buffers. */
939 case V_028C70_COLOR_8:
940 return V_028C70_ENDIAN_NONE;
941
942 /* 16-bit buffers. */
943 case V_028C70_COLOR_5_6_5:
944 case V_028C70_COLOR_1_5_5_5:
945 case V_028C70_COLOR_4_4_4_4:
946 case V_028C70_COLOR_16:
947 case V_028C70_COLOR_8_8:
948 return V_028C70_ENDIAN_8IN16;
949
950 /* 32-bit buffers. */
951 case V_028C70_COLOR_8_8_8_8:
952 case V_028C70_COLOR_2_10_10_10:
953 case V_028C70_COLOR_8_24:
954 case V_028C70_COLOR_24_8:
955 case V_028C70_COLOR_16_16:
956 return V_028C70_ENDIAN_8IN32;
957
958 /* 64-bit buffers. */
959 case V_028C70_COLOR_16_16_16_16:
960 return V_028C70_ENDIAN_8IN16;
961
962 case V_028C70_COLOR_32_32:
963 return V_028C70_ENDIAN_8IN32;
964
965 /* 128-bit buffers. */
966 case V_028C70_COLOR_32_32_32_32:
967 return V_028C70_ENDIAN_8IN32;
968 default:
969 return V_028C70_ENDIAN_NONE; /* Unsupported. */
970 }
971 } else {
972 return V_028C70_ENDIAN_NONE;
973 }
974 }
975
976 /* Returns the size in bits of the widest component of a CB format */
977 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
978 {
979 switch(colorformat) {
980 case V_028C70_COLOR_4_4_4_4:
981 return 4;
982
983 case V_028C70_COLOR_1_5_5_5:
984 case V_028C70_COLOR_5_5_5_1:
985 return 5;
986
987 case V_028C70_COLOR_5_6_5:
988 return 6;
989
990 case V_028C70_COLOR_8:
991 case V_028C70_COLOR_8_8:
992 case V_028C70_COLOR_8_8_8_8:
993 return 8;
994
995 case V_028C70_COLOR_10_10_10_2:
996 case V_028C70_COLOR_2_10_10_10:
997 return 10;
998
999 case V_028C70_COLOR_10_11_11:
1000 case V_028C70_COLOR_11_11_10:
1001 return 11;
1002
1003 case V_028C70_COLOR_16:
1004 case V_028C70_COLOR_16_16:
1005 case V_028C70_COLOR_16_16_16_16:
1006 return 16;
1007
1008 case V_028C70_COLOR_8_24:
1009 case V_028C70_COLOR_24_8:
1010 return 24;
1011
1012 case V_028C70_COLOR_32:
1013 case V_028C70_COLOR_32_32:
1014 case V_028C70_COLOR_32_32_32_32:
1015 case V_028C70_COLOR_X24_8_32_FLOAT:
1016 return 32;
1017 }
1018
1019 assert(!"Unknown maximum component size");
1020 return 0;
1021 }
1022
1023 static uint32_t si_translate_dbformat(enum pipe_format format)
1024 {
1025 switch (format) {
1026 case PIPE_FORMAT_Z16_UNORM:
1027 return V_028040_Z_16;
1028 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1029 case PIPE_FORMAT_X8Z24_UNORM:
1030 case PIPE_FORMAT_Z24X8_UNORM:
1031 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1032 return V_028040_Z_24; /* deprecated on SI */
1033 case PIPE_FORMAT_Z32_FLOAT:
1034 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1035 return V_028040_Z_32_FLOAT;
1036 default:
1037 return V_028040_Z_INVALID;
1038 }
1039 }
1040
1041 /*
1042 * Texture translation
1043 */
1044
1045 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1046 enum pipe_format format,
1047 const struct util_format_description *desc,
1048 int first_non_void)
1049 {
1050 struct r600_screen *rscreen = (struct r600_screen*)screen;
1051 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1052 boolean uniform = TRUE;
1053 int i;
1054
1055 /* Colorspace (return non-RGB formats directly). */
1056 switch (desc->colorspace) {
1057 /* Depth stencil formats */
1058 case UTIL_FORMAT_COLORSPACE_ZS:
1059 switch (format) {
1060 case PIPE_FORMAT_Z16_UNORM:
1061 return V_008F14_IMG_DATA_FORMAT_16;
1062 case PIPE_FORMAT_X24S8_UINT:
1063 case PIPE_FORMAT_Z24X8_UNORM:
1064 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1065 return V_008F14_IMG_DATA_FORMAT_8_24;
1066 case PIPE_FORMAT_X8Z24_UNORM:
1067 case PIPE_FORMAT_S8X24_UINT:
1068 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1069 return V_008F14_IMG_DATA_FORMAT_24_8;
1070 case PIPE_FORMAT_S8_UINT:
1071 return V_008F14_IMG_DATA_FORMAT_8;
1072 case PIPE_FORMAT_Z32_FLOAT:
1073 return V_008F14_IMG_DATA_FORMAT_32;
1074 case PIPE_FORMAT_X32_S8X24_UINT:
1075 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1076 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1077 default:
1078 goto out_unknown;
1079 }
1080
1081 case UTIL_FORMAT_COLORSPACE_YUV:
1082 goto out_unknown; /* TODO */
1083
1084 case UTIL_FORMAT_COLORSPACE_SRGB:
1085 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1086 goto out_unknown;
1087 break;
1088
1089 default:
1090 break;
1091 }
1092
1093 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1094 if (!enable_s3tc)
1095 goto out_unknown;
1096
1097 switch (format) {
1098 case PIPE_FORMAT_RGTC1_SNORM:
1099 case PIPE_FORMAT_LATC1_SNORM:
1100 case PIPE_FORMAT_RGTC1_UNORM:
1101 case PIPE_FORMAT_LATC1_UNORM:
1102 return V_008F14_IMG_DATA_FORMAT_BC4;
1103 case PIPE_FORMAT_RGTC2_SNORM:
1104 case PIPE_FORMAT_LATC2_SNORM:
1105 case PIPE_FORMAT_RGTC2_UNORM:
1106 case PIPE_FORMAT_LATC2_UNORM:
1107 return V_008F14_IMG_DATA_FORMAT_BC5;
1108 default:
1109 goto out_unknown;
1110 }
1111 }
1112
1113 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1114
1115 if (!enable_s3tc)
1116 goto out_unknown;
1117
1118 if (!util_format_s3tc_enabled) {
1119 goto out_unknown;
1120 }
1121
1122 switch (format) {
1123 case PIPE_FORMAT_DXT1_RGB:
1124 case PIPE_FORMAT_DXT1_RGBA:
1125 case PIPE_FORMAT_DXT1_SRGB:
1126 case PIPE_FORMAT_DXT1_SRGBA:
1127 return V_008F14_IMG_DATA_FORMAT_BC1;
1128 case PIPE_FORMAT_DXT3_RGBA:
1129 case PIPE_FORMAT_DXT3_SRGBA:
1130 return V_008F14_IMG_DATA_FORMAT_BC2;
1131 case PIPE_FORMAT_DXT5_RGBA:
1132 case PIPE_FORMAT_DXT5_SRGBA:
1133 return V_008F14_IMG_DATA_FORMAT_BC3;
1134 default:
1135 goto out_unknown;
1136 }
1137 }
1138
1139 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1140 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1141 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1142 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1143 }
1144
1145 /* R8G8Bx_SNORM - TODO CxV8U8 */
1146
1147 /* See whether the components are of the same size. */
1148 for (i = 1; i < desc->nr_channels; i++) {
1149 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1150 }
1151
1152 /* Non-uniform formats. */
1153 if (!uniform) {
1154 switch(desc->nr_channels) {
1155 case 3:
1156 if (desc->channel[0].size == 5 &&
1157 desc->channel[1].size == 6 &&
1158 desc->channel[2].size == 5) {
1159 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1160 }
1161 goto out_unknown;
1162 case 4:
1163 if (desc->channel[0].size == 5 &&
1164 desc->channel[1].size == 5 &&
1165 desc->channel[2].size == 5 &&
1166 desc->channel[3].size == 1) {
1167 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1168 }
1169 if (desc->channel[0].size == 10 &&
1170 desc->channel[1].size == 10 &&
1171 desc->channel[2].size == 10 &&
1172 desc->channel[3].size == 2) {
1173 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1174 }
1175 goto out_unknown;
1176 }
1177 goto out_unknown;
1178 }
1179
1180 if (first_non_void < 0 || first_non_void > 3)
1181 goto out_unknown;
1182
1183 /* uniform formats */
1184 switch (desc->channel[first_non_void].size) {
1185 case 4:
1186 switch (desc->nr_channels) {
1187 #if 0 /* Not supported for render targets */
1188 case 2:
1189 return V_008F14_IMG_DATA_FORMAT_4_4;
1190 #endif
1191 case 4:
1192 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1193 }
1194 break;
1195 case 8:
1196 switch (desc->nr_channels) {
1197 case 1:
1198 return V_008F14_IMG_DATA_FORMAT_8;
1199 case 2:
1200 return V_008F14_IMG_DATA_FORMAT_8_8;
1201 case 4:
1202 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1203 }
1204 break;
1205 case 16:
1206 switch (desc->nr_channels) {
1207 case 1:
1208 return V_008F14_IMG_DATA_FORMAT_16;
1209 case 2:
1210 return V_008F14_IMG_DATA_FORMAT_16_16;
1211 case 4:
1212 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1213 }
1214 break;
1215 case 32:
1216 switch (desc->nr_channels) {
1217 case 1:
1218 return V_008F14_IMG_DATA_FORMAT_32;
1219 case 2:
1220 return V_008F14_IMG_DATA_FORMAT_32_32;
1221 #if 0 /* Not supported for render targets */
1222 case 3:
1223 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1224 #endif
1225 case 4:
1226 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1227 }
1228 }
1229
1230 out_unknown:
1231 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1232 return ~0;
1233 }
1234
1235 static unsigned si_tex_wrap(unsigned wrap)
1236 {
1237 switch (wrap) {
1238 default:
1239 case PIPE_TEX_WRAP_REPEAT:
1240 return V_008F30_SQ_TEX_WRAP;
1241 case PIPE_TEX_WRAP_CLAMP:
1242 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1243 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1244 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1245 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1246 return V_008F30_SQ_TEX_CLAMP_BORDER;
1247 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1248 return V_008F30_SQ_TEX_MIRROR;
1249 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1250 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1251 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1252 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1253 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1254 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1255 }
1256 }
1257
1258 static unsigned si_tex_filter(unsigned filter)
1259 {
1260 switch (filter) {
1261 default:
1262 case PIPE_TEX_FILTER_NEAREST:
1263 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1264 case PIPE_TEX_FILTER_LINEAR:
1265 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1266 }
1267 }
1268
1269 static unsigned si_tex_mipfilter(unsigned filter)
1270 {
1271 switch (filter) {
1272 case PIPE_TEX_MIPFILTER_NEAREST:
1273 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1274 case PIPE_TEX_MIPFILTER_LINEAR:
1275 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1276 default:
1277 case PIPE_TEX_MIPFILTER_NONE:
1278 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1279 }
1280 }
1281
1282 static unsigned si_tex_compare(unsigned compare)
1283 {
1284 switch (compare) {
1285 default:
1286 case PIPE_FUNC_NEVER:
1287 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1288 case PIPE_FUNC_LESS:
1289 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1290 case PIPE_FUNC_EQUAL:
1291 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1292 case PIPE_FUNC_LEQUAL:
1293 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1294 case PIPE_FUNC_GREATER:
1295 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1296 case PIPE_FUNC_NOTEQUAL:
1297 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1298 case PIPE_FUNC_GEQUAL:
1299 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1300 case PIPE_FUNC_ALWAYS:
1301 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1302 }
1303 }
1304
1305 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1306 {
1307 switch (dim) {
1308 default:
1309 case PIPE_TEXTURE_1D:
1310 return V_008F1C_SQ_RSRC_IMG_1D;
1311 case PIPE_TEXTURE_1D_ARRAY:
1312 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1313 case PIPE_TEXTURE_2D:
1314 case PIPE_TEXTURE_RECT:
1315 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1316 V_008F1C_SQ_RSRC_IMG_2D;
1317 case PIPE_TEXTURE_2D_ARRAY:
1318 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1319 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1320 case PIPE_TEXTURE_3D:
1321 return V_008F1C_SQ_RSRC_IMG_3D;
1322 case PIPE_TEXTURE_CUBE:
1323 return V_008F1C_SQ_RSRC_IMG_CUBE;
1324 }
1325 }
1326
1327 /*
1328 * Format support testing
1329 */
1330
1331 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1332 {
1333 return si_translate_texformat(screen, format, util_format_description(format),
1334 util_format_get_first_non_void_channel(format)) != ~0U;
1335 }
1336
1337 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1338 const struct util_format_description *desc,
1339 int first_non_void)
1340 {
1341 unsigned type = desc->channel[first_non_void].type;
1342 int i;
1343
1344 if (type == UTIL_FORMAT_TYPE_FIXED)
1345 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1346
1347 if (desc->nr_channels == 4 &&
1348 desc->channel[0].size == 10 &&
1349 desc->channel[1].size == 10 &&
1350 desc->channel[2].size == 10 &&
1351 desc->channel[3].size == 2)
1352 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1353
1354 /* See whether the components are of the same size. */
1355 for (i = 0; i < desc->nr_channels; i++) {
1356 if (desc->channel[first_non_void].size != desc->channel[i].size)
1357 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1358 }
1359
1360 switch (desc->channel[first_non_void].size) {
1361 case 8:
1362 switch (desc->nr_channels) {
1363 case 1:
1364 return V_008F0C_BUF_DATA_FORMAT_8;
1365 case 2:
1366 return V_008F0C_BUF_DATA_FORMAT_8_8;
1367 case 3:
1368 case 4:
1369 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1370 }
1371 break;
1372 case 16:
1373 switch (desc->nr_channels) {
1374 case 1:
1375 return V_008F0C_BUF_DATA_FORMAT_16;
1376 case 2:
1377 return V_008F0C_BUF_DATA_FORMAT_16_16;
1378 case 3:
1379 case 4:
1380 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1381 }
1382 break;
1383 case 32:
1384 /* From the Southern Islands ISA documentation about MTBUF:
1385 * 'Memory reads of data in memory that is 32 or 64 bits do not
1386 * undergo any format conversion.'
1387 */
1388 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1389 !desc->channel[first_non_void].pure_integer)
1390 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1391
1392 switch (desc->nr_channels) {
1393 case 1:
1394 return V_008F0C_BUF_DATA_FORMAT_32;
1395 case 2:
1396 return V_008F0C_BUF_DATA_FORMAT_32_32;
1397 case 3:
1398 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1399 case 4:
1400 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1401 }
1402 break;
1403 }
1404
1405 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1406 }
1407
1408 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1409 const struct util_format_description *desc,
1410 int first_non_void)
1411 {
1412 switch (desc->channel[first_non_void].type) {
1413 case UTIL_FORMAT_TYPE_SIGNED:
1414 if (desc->channel[first_non_void].normalized)
1415 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1416 else if (desc->channel[first_non_void].pure_integer)
1417 return V_008F0C_BUF_NUM_FORMAT_SINT;
1418 else
1419 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1420 break;
1421 case UTIL_FORMAT_TYPE_UNSIGNED:
1422 if (desc->channel[first_non_void].normalized)
1423 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1424 else if (desc->channel[first_non_void].pure_integer)
1425 return V_008F0C_BUF_NUM_FORMAT_UINT;
1426 else
1427 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1428 break;
1429 case UTIL_FORMAT_TYPE_FLOAT:
1430 default:
1431 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1432 }
1433 }
1434
1435 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1436 {
1437 const struct util_format_description *desc;
1438 int first_non_void;
1439 unsigned data_format;
1440
1441 desc = util_format_description(format);
1442 first_non_void = util_format_get_first_non_void_channel(format);
1443 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1444 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1445 }
1446
1447 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1448 {
1449 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1450 si_translate_colorswap(format) != ~0U;
1451 }
1452
1453 static bool si_is_zs_format_supported(enum pipe_format format)
1454 {
1455 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1456 }
1457
1458 boolean si_is_format_supported(struct pipe_screen *screen,
1459 enum pipe_format format,
1460 enum pipe_texture_target target,
1461 unsigned sample_count,
1462 unsigned usage)
1463 {
1464 struct r600_screen *rscreen = (struct r600_screen *)screen;
1465 unsigned retval = 0;
1466
1467 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1468 R600_ERR("r600: unsupported texture type %d\n", target);
1469 return FALSE;
1470 }
1471
1472 if (!util_format_is_supported(format, usage))
1473 return FALSE;
1474
1475 if (sample_count > 1) {
1476 if (HAVE_LLVM < 0x0304)
1477 return FALSE;
1478
1479 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1480 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1481 return FALSE;
1482
1483 switch (sample_count) {
1484 case 2:
1485 case 4:
1486 case 8:
1487 break;
1488 default:
1489 return FALSE;
1490 }
1491 }
1492
1493 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1494 if (target == PIPE_BUFFER) {
1495 if (si_is_vertex_format_supported(screen, format))
1496 retval |= PIPE_BIND_SAMPLER_VIEW;
1497 } else {
1498 if (si_is_sampler_format_supported(screen, format))
1499 retval |= PIPE_BIND_SAMPLER_VIEW;
1500 }
1501 }
1502
1503 if ((usage & (PIPE_BIND_RENDER_TARGET |
1504 PIPE_BIND_DISPLAY_TARGET |
1505 PIPE_BIND_SCANOUT |
1506 PIPE_BIND_SHARED)) &&
1507 si_is_colorbuffer_format_supported(format)) {
1508 retval |= usage &
1509 (PIPE_BIND_RENDER_TARGET |
1510 PIPE_BIND_DISPLAY_TARGET |
1511 PIPE_BIND_SCANOUT |
1512 PIPE_BIND_SHARED);
1513 }
1514
1515 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1516 si_is_zs_format_supported(format)) {
1517 retval |= PIPE_BIND_DEPTH_STENCIL;
1518 }
1519
1520 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1521 si_is_vertex_format_supported(screen, format)) {
1522 retval |= PIPE_BIND_VERTEX_BUFFER;
1523 }
1524
1525 if (usage & PIPE_BIND_TRANSFER_READ)
1526 retval |= PIPE_BIND_TRANSFER_READ;
1527 if (usage & PIPE_BIND_TRANSFER_WRITE)
1528 retval |= PIPE_BIND_TRANSFER_WRITE;
1529
1530 return retval == usage;
1531 }
1532
1533 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1534 {
1535 unsigned tile_mode_index = 0;
1536
1537 if (stencil) {
1538 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1539 } else {
1540 tile_mode_index = rtex->surface.tiling_index[level];
1541 }
1542 return tile_mode_index;
1543 }
1544
1545 /*
1546 * framebuffer handling
1547 */
1548
1549 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1550 const struct pipe_framebuffer_state *state, int cb)
1551 {
1552 struct r600_texture *rtex;
1553 struct r600_surface *surf;
1554 unsigned level = state->cbufs[cb]->u.tex.level;
1555 unsigned pitch, slice;
1556 unsigned color_info, color_attrib, color_pitch, color_view;
1557 unsigned tile_mode_index;
1558 unsigned format, swap, ntype, endian;
1559 uint64_t offset;
1560 const struct util_format_description *desc;
1561 int i;
1562 unsigned blend_clamp = 0, blend_bypass = 0;
1563 unsigned max_comp_size;
1564
1565 surf = (struct r600_surface *)state->cbufs[cb];
1566 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1567
1568 offset = rtex->surface.level[level].offset;
1569
1570 /* Layered rendering doesn't work with LINEAR_GENERAL.
1571 * (LINEAR_ALIGNED and others work) */
1572 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1573 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1574 offset += rtex->surface.level[level].slice_size *
1575 state->cbufs[cb]->u.tex.first_layer;
1576 color_view = 0;
1577 } else {
1578 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1579 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1580 }
1581
1582 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1583 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1584 if (slice) {
1585 slice = slice - 1;
1586 }
1587
1588 tile_mode_index = si_tile_mode_index(rtex, level, false);
1589
1590 desc = util_format_description(surf->base.format);
1591 for (i = 0; i < 4; i++) {
1592 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1593 break;
1594 }
1595 }
1596 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1597 ntype = V_028C70_NUMBER_FLOAT;
1598 } else {
1599 ntype = V_028C70_NUMBER_UNORM;
1600 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1601 ntype = V_028C70_NUMBER_SRGB;
1602 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1603 if (desc->channel[i].pure_integer) {
1604 ntype = V_028C70_NUMBER_SINT;
1605 } else {
1606 assert(desc->channel[i].normalized);
1607 ntype = V_028C70_NUMBER_SNORM;
1608 }
1609 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1610 if (desc->channel[i].pure_integer) {
1611 ntype = V_028C70_NUMBER_UINT;
1612 } else {
1613 assert(desc->channel[i].normalized);
1614 ntype = V_028C70_NUMBER_UNORM;
1615 }
1616 }
1617 }
1618
1619 format = si_translate_colorformat(surf->base.format);
1620 if (format == V_028C70_COLOR_INVALID) {
1621 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1622 }
1623 assert(format != V_028C70_COLOR_INVALID);
1624 swap = si_translate_colorswap(surf->base.format);
1625 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1626 endian = V_028C70_ENDIAN_NONE;
1627 } else {
1628 endian = si_colorformat_endian_swap(format);
1629 }
1630
1631 /* blend clamp should be set for all NORM/SRGB types */
1632 if (ntype == V_028C70_NUMBER_UNORM ||
1633 ntype == V_028C70_NUMBER_SNORM ||
1634 ntype == V_028C70_NUMBER_SRGB)
1635 blend_clamp = 1;
1636
1637 /* set blend bypass according to docs if SINT/UINT or
1638 8/24 COLOR variants */
1639 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1640 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1641 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1642 blend_clamp = 0;
1643 blend_bypass = 1;
1644 }
1645
1646 color_info = S_028C70_FORMAT(format) |
1647 S_028C70_COMP_SWAP(swap) |
1648 S_028C70_BLEND_CLAMP(blend_clamp) |
1649 S_028C70_BLEND_BYPASS(blend_bypass) |
1650 S_028C70_NUMBER_TYPE(ntype) |
1651 S_028C70_ENDIAN(endian);
1652
1653 color_pitch = S_028C64_TILE_MAX(pitch);
1654
1655 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1656 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1657
1658 if (rtex->resource.b.b.nr_samples > 1) {
1659 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1660
1661 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1662 S_028C74_NUM_FRAGMENTS(log_samples);
1663
1664 if (rtex->fmask.size) {
1665 color_info |= S_028C70_COMPRESSION(1);
1666 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1667
1668 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1669
1670 if (rctx->b.chip_class == SI) {
1671 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1672 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1673 }
1674 if (rctx->b.chip_class >= CIK) {
1675 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1676 }
1677 }
1678 }
1679
1680 if (rtex->cmask.size) {
1681 color_info |= S_028C70_FAST_CLEAR(1);
1682 }
1683
1684 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1685 offset >>= 8;
1686
1687 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1688 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1689 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1690 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1691 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1692 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1693 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1694
1695 if (rtex->cmask.size) {
1696 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1697 offset + (rtex->cmask.offset >> 8));
1698 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1699 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1700 }
1701 if (rtex->fmask.size) {
1702 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1703 offset + (rtex->fmask.offset >> 8));
1704 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1705 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1706 }
1707
1708 /* set CB_COLOR1_INFO for possible dual-src blending */
1709 if (state->nr_cbufs == 1) {
1710 assert(cb == 0);
1711 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1712 }
1713
1714 /* Determine pixel shader export format */
1715 max_comp_size = si_colorformat_max_comp_size(format);
1716 if (ntype == V_028C70_NUMBER_SRGB ||
1717 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1718 max_comp_size <= 10) ||
1719 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1720 rctx->export_16bpc |= 1 << cb;
1721 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1722 if (state->nr_cbufs == 1)
1723 rctx->export_16bpc |= 1 << 1;
1724 }
1725 }
1726
1727 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1728 const struct pipe_framebuffer_state *state)
1729 {
1730 struct r600_screen *rscreen = rctx->screen;
1731 struct r600_texture *rtex;
1732 struct r600_surface *surf;
1733 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1734 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1735 uint32_t z_info, s_info, db_depth_info;
1736 uint64_t z_offs, s_offs;
1737 uint32_t db_htile_data_base, db_htile_surface;
1738
1739 if (state->zsbuf == NULL) {
1740 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1741 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1742 return;
1743 }
1744
1745 surf = (struct r600_surface *)state->zsbuf;
1746 level = surf->base.u.tex.level;
1747 rtex = (struct r600_texture*)surf->base.texture;
1748
1749 format = si_translate_dbformat(rtex->resource.b.b.format);
1750
1751 if (format == V_028040_Z_INVALID) {
1752 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1753 }
1754 assert(format != V_028040_Z_INVALID);
1755
1756 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1757 z_offs += rtex->surface.level[level].offset;
1758 s_offs += rtex->surface.stencil_level[level].offset;
1759
1760 z_offs >>= 8;
1761 s_offs >>= 8;
1762
1763 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1764 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1765 if (slice) {
1766 slice = slice - 1;
1767 }
1768
1769 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1770
1771 z_info = S_028040_FORMAT(format);
1772 if (rtex->resource.b.b.nr_samples > 1) {
1773 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1774 }
1775
1776 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1777 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1778 else
1779 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1780
1781 if (rctx->b.chip_class >= CIK) {
1782 switch (rtex->surface.level[level].mode) {
1783 case RADEON_SURF_MODE_2D:
1784 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1785 break;
1786 case RADEON_SURF_MODE_1D:
1787 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1788 case RADEON_SURF_MODE_LINEAR:
1789 default:
1790 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1791 break;
1792 }
1793 tile_split = rtex->surface.tile_split;
1794 stile_split = rtex->surface.stencil_tile_split;
1795 macro_aspect = rtex->surface.mtilea;
1796 bankw = rtex->surface.bankw;
1797 bankh = rtex->surface.bankh;
1798 tile_split = cik_tile_split(tile_split);
1799 stile_split = cik_tile_split(stile_split);
1800 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1801 bankw = cik_bank_wh(bankw);
1802 bankh = cik_bank_wh(bankh);
1803 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1804 tile_mode_index = si_tile_mode_index(rtex, level, false);
1805 pipe_config = cik_db_pipe_config(rscreen, tile_mode_index);
1806
1807 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1808 S_02803C_PIPE_CONFIG(pipe_config) |
1809 S_02803C_BANK_WIDTH(bankw) |
1810 S_02803C_BANK_HEIGHT(bankh) |
1811 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1812 S_02803C_NUM_BANKS(nbanks);
1813 z_info |= S_028040_TILE_SPLIT(tile_split);
1814 s_info |= S_028044_TILE_SPLIT(stile_split);
1815 } else {
1816 tile_mode_index = si_tile_mode_index(rtex, level, false);
1817 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1818 tile_mode_index = si_tile_mode_index(rtex, level, true);
1819 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1820 }
1821
1822 /* HiZ aka depth buffer htile */
1823 /* use htile only for first level */
1824 if (rtex->htile_buffer && !level) {
1825 const struct util_format_description *fmt_desc;
1826
1827 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1828
1829 /* This is optimal for the clear value of 1.0 and using
1830 * the LESS and LEQUAL test functions. Set this to 0
1831 * for the opposite case. This can only be changed when
1832 * clearing. */
1833 z_info |= S_028040_ZRANGE_PRECISION(1);
1834
1835 fmt_desc = util_format_description(rtex->resource.b.b.format);
1836 if (!util_format_has_stencil(fmt_desc)) {
1837 /* Use all of the htile_buffer for depth */
1838 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1839 }
1840
1841 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1842 db_htile_data_base = va >> 8;
1843 db_htile_surface = S_028ABC_FULL_CACHE(1);
1844
1845 si_pm4_add_bo(pm4, rtex->htile_buffer, RADEON_USAGE_READWRITE);
1846 } else {
1847 db_htile_data_base = 0;
1848 db_htile_surface = 0;
1849 }
1850
1851 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1852 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1853 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1854 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1855
1856 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1857 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1858 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1859
1860 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1861 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1862 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1863 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1864 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1865
1866 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1867 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1868
1869 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1870 }
1871
1872 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1873 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1874 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1875 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1876 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1877
1878 /* 2xMSAA
1879 * There are two locations (-4, 4), (4, -4). */
1880 static uint32_t sample_locs_2x[] = {
1881 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1882 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1883 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1884 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1885 };
1886 static unsigned max_dist_2x = 4;
1887 /* 4xMSAA
1888 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1889 static uint32_t sample_locs_4x[] = {
1890 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1891 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1892 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1893 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1894 };
1895 static unsigned max_dist_4x = 6;
1896 /* Cayman/SI 8xMSAA */
1897 static uint32_t cm_sample_locs_8x[] = {
1898 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1899 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1900 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1901 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1902 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1903 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1904 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1905 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1906 };
1907 static unsigned cm_max_dist_8x = 8;
1908 /* Cayman/SI 16xMSAA */
1909 static uint32_t cm_sample_locs_16x[] = {
1910 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1911 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1912 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1913 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1914 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1915 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1916 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1917 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1918 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1919 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1920 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1921 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1922 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1923 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1924 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1925 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1926 };
1927 static unsigned cm_max_dist_16x = 8;
1928
1929 static void si_get_sample_position(struct pipe_context *ctx,
1930 unsigned sample_count,
1931 unsigned sample_index,
1932 float *out_value)
1933 {
1934 int offset, index;
1935 struct {
1936 int idx:4;
1937 } val;
1938 switch (sample_count) {
1939 case 1:
1940 default:
1941 out_value[0] = out_value[1] = 0.5;
1942 break;
1943 case 2:
1944 offset = 4 * (sample_index * 2);
1945 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1946 out_value[0] = (float)(val.idx + 8) / 16.0f;
1947 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1948 out_value[1] = (float)(val.idx + 8) / 16.0f;
1949 break;
1950 case 4:
1951 offset = 4 * (sample_index * 2);
1952 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1953 out_value[0] = (float)(val.idx + 8) / 16.0f;
1954 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1955 out_value[1] = (float)(val.idx + 8) / 16.0f;
1956 break;
1957 case 8:
1958 offset = 4 * (sample_index % 4 * 2);
1959 index = (sample_index / 4) * 4;
1960 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1961 out_value[0] = (float)(val.idx + 8) / 16.0f;
1962 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
1963 out_value[1] = (float)(val.idx + 8) / 16.0f;
1964 break;
1965 case 16:
1966 offset = 4 * (sample_index % 4 * 2);
1967 index = (sample_index / 4) * 4;
1968 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
1969 out_value[0] = (float)(val.idx + 8) / 16.0f;
1970 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
1971 out_value[1] = (float)(val.idx + 8) / 16.0f;
1972 break;
1973 }
1974 }
1975
1976 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
1977 {
1978 unsigned max_dist = 0;
1979
1980 switch (nr_samples) {
1981 default:
1982 nr_samples = 0;
1983 break;
1984 case 2:
1985 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
1986 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
1987 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
1988 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
1989 max_dist = max_dist_2x;
1990 break;
1991 case 4:
1992 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
1993 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
1994 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
1995 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
1996 max_dist = max_dist_4x;
1997 break;
1998 case 8:
1999 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2000 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2001 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2002 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2003 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2004 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2005 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2006 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2007 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2008 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2009 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2010 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2011 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2012 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2013 max_dist = cm_max_dist_8x;
2014 break;
2015 case 16:
2016 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2017 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2018 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2019 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2020 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2021 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2022 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2023 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2024 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2025 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2026 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2027 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2028 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2029 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2030 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2031 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2032 max_dist = cm_max_dist_16x;
2033 break;
2034 }
2035
2036 if (nr_samples > 1) {
2037 unsigned log_samples = util_logbase2(nr_samples);
2038
2039 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2040 S_028BDC_LAST_PIXEL(1) |
2041 S_028BDC_EXPAND_LINE_WIDTH(1));
2042 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2043 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2044 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2045 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2046
2047 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2048 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2049 S_028804_PS_ITER_SAMPLES(log_samples) |
2050 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2051 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2052 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2053 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2054 } else {
2055 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2056 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2057
2058 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2059 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2060 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2061 }
2062 }
2063
2064 static void si_set_framebuffer_state(struct pipe_context *ctx,
2065 const struct pipe_framebuffer_state *state)
2066 {
2067 struct r600_context *rctx = (struct r600_context *)ctx;
2068 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2069 uint32_t tl, br;
2070 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2071
2072 if (pm4 == NULL)
2073 return;
2074
2075 if (rctx->framebuffer.nr_cbufs) {
2076 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2077 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2078 }
2079 if (rctx->framebuffer.zsbuf) {
2080 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
2081 R600_CONTEXT_FLUSH_AND_INV_DB_META;
2082 }
2083
2084 util_copy_framebuffer_state(&rctx->framebuffer, state);
2085
2086 /* build states */
2087 rctx->export_16bpc = 0;
2088 rctx->fb_compressed_cb_mask = 0;
2089 for (i = 0; i < state->nr_cbufs; i++) {
2090 struct r600_texture *rtex =
2091 (struct r600_texture*)state->cbufs[i]->texture;
2092
2093 si_cb(rctx, pm4, state, i);
2094
2095 if (rtex->fmask.size || rtex->cmask.size) {
2096 rctx->fb_compressed_cb_mask |= 1 << i;
2097 }
2098 }
2099 for (; i < 8; i++) {
2100 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2101 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2102 }
2103
2104 assert(!(rctx->export_16bpc & ~0xff));
2105 si_db(rctx, pm4, state);
2106
2107 tl_x = 0;
2108 tl_y = 0;
2109 br_x = state->width;
2110 br_y = state->height;
2111
2112 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2113 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2114
2115 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2116 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2117 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2118 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2119 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2120 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2121 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2122 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2123
2124 if (state->nr_cbufs)
2125 nr_samples = state->cbufs[0]->texture->nr_samples;
2126 else if (state->zsbuf)
2127 nr_samples = state->zsbuf->texture->nr_samples;
2128 else
2129 nr_samples = 0;
2130
2131 si_set_msaa_state(rctx, pm4, nr_samples);
2132 rctx->fb_log_samples = util_logbase2(nr_samples);
2133 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2134 util_format_is_pure_integer(state->cbufs[0]->format);
2135
2136 si_pm4_set_state(rctx, framebuffer, pm4);
2137 si_update_fb_rs_state(rctx);
2138 si_update_fb_blend_state(rctx);
2139 }
2140
2141 /*
2142 * shaders
2143 */
2144
2145 /* Compute the key for the hw shader variant */
2146 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2147 struct si_pipe_shader_selector *sel,
2148 union si_shader_key *key)
2149 {
2150 struct r600_context *rctx = (struct r600_context *)ctx;
2151 memset(key, 0, sizeof(*key));
2152
2153 if (sel->type == PIPE_SHADER_VERTEX) {
2154 unsigned i;
2155 if (!rctx->vertex_elements)
2156 return;
2157
2158 for (i = 0; i < rctx->vertex_elements->count; ++i)
2159 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2160
2161 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2162 key->vs.ucps_enabled |= 0x2;
2163 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2164 key->vs.ucps_enabled |= 0x1;
2165 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2166 if (sel->fs_write_all)
2167 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2168 key->ps.export_16bpc = rctx->export_16bpc;
2169
2170 if (rctx->queued.named.rasterizer) {
2171 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2172 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2173
2174 if (rctx->queued.named.blend) {
2175 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2176 rctx->queued.named.rasterizer->multisample_enable &&
2177 !rctx->fb_cb0_is_integer;
2178 }
2179 }
2180 if (rctx->queued.named.dsa) {
2181 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2182
2183 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2184 if (rctx->framebuffer.nr_cbufs &&
2185 rctx->framebuffer.cbufs[0] &&
2186 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2187 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2188 } else {
2189 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2190 }
2191 }
2192 }
2193
2194 /* Select the hw shader variant depending on the current state.
2195 * (*dirty) is set to 1 if current variant was changed */
2196 int si_shader_select(struct pipe_context *ctx,
2197 struct si_pipe_shader_selector *sel,
2198 unsigned *dirty)
2199 {
2200 union si_shader_key key;
2201 struct si_pipe_shader * shader = NULL;
2202 int r;
2203
2204 si_shader_selector_key(ctx, sel, &key);
2205
2206 /* Check if we don't need to change anything.
2207 * This path is also used for most shaders that don't need multiple
2208 * variants, it will cost just a computation of the key and this
2209 * test. */
2210 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2211 return 0;
2212 }
2213
2214 /* lookup if we have other variants in the list */
2215 if (sel->num_shaders > 1) {
2216 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2217
2218 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2219 p = c;
2220 c = c->next_variant;
2221 }
2222
2223 if (c) {
2224 p->next_variant = c->next_variant;
2225 shader = c;
2226 }
2227 }
2228
2229 if (unlikely(!shader)) {
2230 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2231 shader->selector = sel;
2232 shader->key = key;
2233
2234 r = si_pipe_shader_create(ctx, shader);
2235 if (unlikely(r)) {
2236 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2237 sel->type, r);
2238 sel->current = NULL;
2239 FREE(shader);
2240 return r;
2241 }
2242 sel->num_shaders++;
2243 }
2244
2245 if (dirty)
2246 *dirty = 1;
2247
2248 shader->next_variant = sel->current;
2249 sel->current = shader;
2250
2251 return 0;
2252 }
2253
2254 static void *si_create_shader_state(struct pipe_context *ctx,
2255 const struct pipe_shader_state *state,
2256 unsigned pipe_shader_type)
2257 {
2258 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2259 int r;
2260
2261 sel->type = pipe_shader_type;
2262 sel->tokens = tgsi_dup_tokens(state->tokens);
2263 sel->so = state->stream_output;
2264
2265 if (pipe_shader_type == PIPE_SHADER_FRAGMENT) {
2266 struct tgsi_shader_info info;
2267
2268 tgsi_scan_shader(state->tokens, &info);
2269 sel->fs_write_all = info.color0_writes_all_cbufs;
2270 }
2271
2272 r = si_shader_select(ctx, sel, NULL);
2273 if (r) {
2274 free(sel);
2275 return NULL;
2276 }
2277
2278 return sel;
2279 }
2280
2281 static void *si_create_fs_state(struct pipe_context *ctx,
2282 const struct pipe_shader_state *state)
2283 {
2284 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2285 }
2286
2287 static void *si_create_vs_state(struct pipe_context *ctx,
2288 const struct pipe_shader_state *state)
2289 {
2290 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2291 }
2292
2293 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2294 {
2295 struct r600_context *rctx = (struct r600_context *)ctx;
2296 struct si_pipe_shader_selector *sel = state;
2297
2298 if (rctx->vs_shader == sel)
2299 return;
2300
2301 if (!sel || !sel->current)
2302 return;
2303
2304 rctx->vs_shader = sel;
2305 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2306 rctx->b.streamout.stride_in_dw = sel->so.stride;
2307 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2308 }
2309
2310 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2311 {
2312 struct r600_context *rctx = (struct r600_context *)ctx;
2313 struct si_pipe_shader_selector *sel = state;
2314
2315 if (rctx->ps_shader == sel)
2316 return;
2317
2318 if (!sel || !sel->current)
2319 sel = rctx->dummy_pixel_shader;
2320
2321 rctx->ps_shader = sel;
2322 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2323 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2324 }
2325
2326 static void si_delete_shader_selector(struct pipe_context *ctx,
2327 struct si_pipe_shader_selector *sel)
2328 {
2329 struct r600_context *rctx = (struct r600_context *)ctx;
2330 struct si_pipe_shader *p = sel->current, *c;
2331
2332 while (p) {
2333 c = p->next_variant;
2334 si_pm4_delete_state(rctx, vs, p->pm4);
2335 si_pipe_shader_destroy(ctx, p);
2336 free(p);
2337 p = c;
2338 }
2339
2340 free(sel->tokens);
2341 free(sel);
2342 }
2343
2344 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2345 {
2346 struct r600_context *rctx = (struct r600_context *)ctx;
2347 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2348
2349 if (rctx->vs_shader == sel) {
2350 rctx->vs_shader = NULL;
2351 }
2352
2353 si_delete_shader_selector(ctx, sel);
2354 }
2355
2356 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2357 {
2358 struct r600_context *rctx = (struct r600_context *)ctx;
2359 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2360
2361 if (rctx->ps_shader == sel) {
2362 rctx->ps_shader = NULL;
2363 }
2364
2365 si_delete_shader_selector(ctx, sel);
2366 }
2367
2368 /*
2369 * Samplers
2370 */
2371
2372 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2373 struct pipe_resource *texture,
2374 const struct pipe_sampler_view *state)
2375 {
2376 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2377 struct r600_texture *tmp = (struct r600_texture*)texture;
2378 const struct util_format_description *desc;
2379 unsigned format, num_format;
2380 uint32_t pitch = 0;
2381 unsigned char state_swizzle[4], swizzle[4];
2382 unsigned height, depth, width;
2383 enum pipe_format pipe_format = state->format;
2384 struct radeon_surface_level *surflevel;
2385 int first_non_void;
2386 uint64_t va;
2387
2388 if (view == NULL)
2389 return NULL;
2390
2391 /* initialize base object */
2392 view->base = *state;
2393 view->base.texture = NULL;
2394 pipe_resource_reference(&view->base.texture, texture);
2395 view->base.reference.count = 1;
2396 view->base.context = ctx;
2397 view->resource = &tmp->resource;
2398
2399 /* Buffer resource. */
2400 if (texture->target == PIPE_BUFFER) {
2401 unsigned stride;
2402
2403 desc = util_format_description(state->format);
2404 first_non_void = util_format_get_first_non_void_channel(state->format);
2405 stride = desc->block.bits / 8;
2406 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2407 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2408 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2409
2410 view->state[0] = va;
2411 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2412 S_008F04_STRIDE(stride);
2413 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2414 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2415 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2416 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2417 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2418 S_008F0C_NUM_FORMAT(num_format) |
2419 S_008F0C_DATA_FORMAT(format);
2420 return &view->base;
2421 }
2422
2423 state_swizzle[0] = state->swizzle_r;
2424 state_swizzle[1] = state->swizzle_g;
2425 state_swizzle[2] = state->swizzle_b;
2426 state_swizzle[3] = state->swizzle_a;
2427
2428 surflevel = tmp->surface.level;
2429
2430 /* Texturing with separate depth and stencil. */
2431 if (tmp->is_depth && !tmp->is_flushing_texture) {
2432 switch (pipe_format) {
2433 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2434 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2435 break;
2436 case PIPE_FORMAT_X8Z24_UNORM:
2437 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2438 /* Z24 is always stored like this. */
2439 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2440 break;
2441 case PIPE_FORMAT_X24S8_UINT:
2442 case PIPE_FORMAT_S8X24_UINT:
2443 case PIPE_FORMAT_X32_S8X24_UINT:
2444 pipe_format = PIPE_FORMAT_S8_UINT;
2445 surflevel = tmp->surface.stencil_level;
2446 break;
2447 default:;
2448 }
2449 }
2450
2451 desc = util_format_description(pipe_format);
2452
2453 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2454 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2455 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2456
2457 switch (pipe_format) {
2458 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2459 case PIPE_FORMAT_X24S8_UINT:
2460 case PIPE_FORMAT_X32_S8X24_UINT:
2461 case PIPE_FORMAT_X8Z24_UNORM:
2462 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2463 break;
2464 default:
2465 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2466 }
2467 } else {
2468 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2469 }
2470
2471 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2472
2473 switch (pipe_format) {
2474 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2475 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2476 break;
2477 default:
2478 if (first_non_void < 0) {
2479 if (util_format_is_compressed(pipe_format)) {
2480 switch (pipe_format) {
2481 case PIPE_FORMAT_DXT1_SRGB:
2482 case PIPE_FORMAT_DXT1_SRGBA:
2483 case PIPE_FORMAT_DXT3_SRGBA:
2484 case PIPE_FORMAT_DXT5_SRGBA:
2485 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2486 break;
2487 case PIPE_FORMAT_RGTC1_SNORM:
2488 case PIPE_FORMAT_LATC1_SNORM:
2489 case PIPE_FORMAT_RGTC2_SNORM:
2490 case PIPE_FORMAT_LATC2_SNORM:
2491 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2492 break;
2493 default:
2494 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2495 break;
2496 }
2497 } else {
2498 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2499 }
2500 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2501 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2502 } else {
2503 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2504
2505 switch (desc->channel[first_non_void].type) {
2506 case UTIL_FORMAT_TYPE_FLOAT:
2507 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2508 break;
2509 case UTIL_FORMAT_TYPE_SIGNED:
2510 if (desc->channel[first_non_void].normalized)
2511 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2512 else if (desc->channel[first_non_void].pure_integer)
2513 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2514 else
2515 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2516 break;
2517 case UTIL_FORMAT_TYPE_UNSIGNED:
2518 if (desc->channel[first_non_void].normalized)
2519 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2520 else if (desc->channel[first_non_void].pure_integer)
2521 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2522 else
2523 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2524 }
2525 }
2526 }
2527
2528 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2529 if (format == ~0) {
2530 format = 0;
2531 }
2532
2533 /* not supported any more */
2534 //endian = si_colorformat_endian_swap(format);
2535
2536 width = surflevel[0].npix_x;
2537 height = surflevel[0].npix_y;
2538 depth = surflevel[0].npix_z;
2539 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2540
2541 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2542 height = 1;
2543 depth = texture->array_size;
2544 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2545 depth = texture->array_size;
2546 }
2547
2548 va = r600_resource_va(ctx->screen, texture);
2549 va += surflevel[0].offset;
2550 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2551 view->state[0] = va >> 8;
2552 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2553 S_008F14_DATA_FORMAT(format) |
2554 S_008F14_NUM_FORMAT(num_format));
2555 view->state[2] = (S_008F18_WIDTH(width - 1) |
2556 S_008F18_HEIGHT(height - 1));
2557 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2558 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2559 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2560 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2561 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2562 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2563 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2564 util_logbase2(texture->nr_samples) :
2565 state->u.tex.last_level - tmp->mipmap_shift) |
2566 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2567 S_008F1C_POW2_PAD(texture->last_level > 0) |
2568 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2569 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2570 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2571 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2572 view->state[6] = 0;
2573 view->state[7] = 0;
2574
2575 /* Initialize the sampler view for FMASK. */
2576 if (tmp->fmask.size) {
2577 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2578 uint32_t fmask_format;
2579
2580 switch (texture->nr_samples) {
2581 case 2:
2582 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2583 break;
2584 case 4:
2585 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2586 break;
2587 case 8:
2588 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2589 break;
2590 default:
2591 assert(0);
2592 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2593 }
2594
2595 view->fmask_state[0] = va >> 8;
2596 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2597 S_008F14_DATA_FORMAT(fmask_format) |
2598 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2599 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2600 S_008F18_HEIGHT(height - 1);
2601 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2602 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2603 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2604 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2605 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2606 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2607 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2608 S_008F20_PITCH(tmp->fmask.pitch - 1);
2609 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2610 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2611 view->fmask_state[6] = 0;
2612 view->fmask_state[7] = 0;
2613 }
2614
2615 return &view->base;
2616 }
2617
2618 static void si_sampler_view_destroy(struct pipe_context *ctx,
2619 struct pipe_sampler_view *state)
2620 {
2621 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2622
2623 pipe_resource_reference(&state->texture, NULL);
2624 FREE(resource);
2625 }
2626
2627 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2628 {
2629 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2630 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2631 (linear_filter &&
2632 (wrap == PIPE_TEX_WRAP_CLAMP ||
2633 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2634 }
2635
2636 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2637 {
2638 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2639 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2640
2641 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2642 state->border_color.ui[2] || state->border_color.ui[3]) &&
2643 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2644 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2645 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2646 }
2647
2648 static void *si_create_sampler_state(struct pipe_context *ctx,
2649 const struct pipe_sampler_state *state)
2650 {
2651 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2652 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2653 unsigned border_color_type;
2654
2655 if (rstate == NULL) {
2656 return NULL;
2657 }
2658
2659 if (sampler_state_needs_border_color(state))
2660 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2661 else
2662 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2663
2664 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2665 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2666 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2667 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2668 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2669 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2670 aniso_flag_offset << 16 | /* XXX */
2671 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2672 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2673 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2674 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2675 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2676 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2677 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2678 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2679
2680 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2681 memcpy(rstate->border_color, state->border_color.ui,
2682 sizeof(rstate->border_color));
2683 }
2684
2685 return rstate;
2686 }
2687
2688 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2689 * the si_set_sampler_view calls. LTO might help too. */
2690 static void si_set_sampler_views(struct pipe_context *ctx,
2691 unsigned shader, unsigned start,
2692 unsigned count,
2693 struct pipe_sampler_view **views)
2694 {
2695 struct r600_context *rctx = (struct r600_context *)ctx;
2696 struct r600_textures_info *samplers = &rctx->samplers[shader];
2697 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2698 int i;
2699
2700 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2701 return;
2702
2703 assert(start == 0);
2704
2705 for (i = 0; i < count; i++) {
2706 if (!views[i]) {
2707 samplers->depth_texture_mask &= ~(1 << i);
2708 samplers->compressed_colortex_mask &= ~(1 << i);
2709 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2710 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2711 NULL, NULL);
2712 continue;
2713 }
2714
2715 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2716
2717 if (views[i]->texture->target != PIPE_BUFFER) {
2718 struct r600_texture *rtex =
2719 (struct r600_texture*)views[i]->texture;
2720
2721 if (rtex->is_depth && !rtex->is_flushing_texture) {
2722 samplers->depth_texture_mask |= 1 << i;
2723 } else {
2724 samplers->depth_texture_mask &= ~(1 << i);
2725 }
2726 if (rtex->cmask.size || rtex->fmask.size) {
2727 samplers->compressed_colortex_mask |= 1 << i;
2728 } else {
2729 samplers->compressed_colortex_mask &= ~(1 << i);
2730 }
2731
2732 if (rtex->fmask.size) {
2733 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2734 views[i], rviews[i]->fmask_state);
2735 } else {
2736 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2737 NULL, NULL);
2738 }
2739 }
2740 }
2741 for (; i < samplers->n_views; i++) {
2742 samplers->depth_texture_mask &= ~(1 << i);
2743 samplers->compressed_colortex_mask &= ~(1 << i);
2744 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2745 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2746 NULL, NULL);
2747 }
2748
2749 samplers->n_views = count;
2750 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2751 }
2752
2753 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2754 void **states,
2755 struct r600_textures_info *samplers,
2756 unsigned user_data_reg)
2757 {
2758 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2759 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2760 uint32_t *border_color_table = NULL;
2761 int i, j;
2762
2763 if (!count)
2764 goto out;
2765
2766 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2767
2768 si_pm4_sh_data_begin(pm4);
2769 for (i = 0; i < count; i++) {
2770 if (rstates[i] &&
2771 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2772 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2773 if (!rctx->border_color_table ||
2774 ((rctx->border_color_offset + count - i) &
2775 C_008F3C_BORDER_COLOR_PTR)) {
2776 r600_resource_reference(&rctx->border_color_table, NULL);
2777 rctx->border_color_offset = 0;
2778
2779 rctx->border_color_table =
2780 r600_resource_create_custom(&rctx->screen->b.b,
2781 PIPE_USAGE_STAGING,
2782 4096 * 4 * 4);
2783 }
2784
2785 if (!border_color_table) {
2786 border_color_table =
2787 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2788 rctx->b.rings.gfx.cs,
2789 PIPE_TRANSFER_WRITE |
2790 PIPE_TRANSFER_UNSYNCHRONIZED);
2791 }
2792
2793 for (j = 0; j < 4; j++) {
2794 border_color_table[4 * rctx->border_color_offset + j] =
2795 util_le32_to_cpu(rstates[i]->border_color[j]);
2796 }
2797
2798 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2799 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2800 }
2801
2802 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2803 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2804 }
2805 }
2806 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2807
2808 if (border_color_table) {
2809 uint64_t va_offset =
2810 r600_resource_va(&rctx->screen->b.b,
2811 (void*)rctx->border_color_table);
2812
2813 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2814 if (rctx->b.chip_class >= CIK)
2815 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2816 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2817 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2818 }
2819
2820 memcpy(samplers->samplers, states, sizeof(void*) * count);
2821
2822 out:
2823 samplers->n_samplers = count;
2824 return pm4;
2825 }
2826
2827 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2828 {
2829 struct r600_context *rctx = (struct r600_context *)ctx;
2830 struct si_pm4_state *pm4;
2831
2832 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2833 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2834 si_pm4_set_state(rctx, vs_sampler, pm4);
2835 }
2836
2837 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2838 {
2839 struct r600_context *rctx = (struct r600_context *)ctx;
2840 struct si_pm4_state *pm4;
2841
2842 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2843 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2844 si_pm4_set_state(rctx, ps_sampler, pm4);
2845 }
2846
2847
2848 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2849 unsigned start, unsigned count,
2850 void **states)
2851 {
2852 assert(start == 0);
2853
2854 switch (shader) {
2855 case PIPE_SHADER_VERTEX:
2856 si_bind_vs_sampler_states(ctx, count, states);
2857 break;
2858 case PIPE_SHADER_FRAGMENT:
2859 si_bind_ps_sampler_states(ctx, count, states);
2860 break;
2861 default:
2862 ;
2863 }
2864 }
2865
2866
2867
2868 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2869 {
2870 struct r600_context *rctx = (struct r600_context *)ctx;
2871 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2872 uint16_t mask = sample_mask;
2873
2874 if (pm4 == NULL)
2875 return;
2876
2877 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2878 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2879
2880 si_pm4_set_state(rctx, sample_mask, pm4);
2881 }
2882
2883 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2884 {
2885 free(state);
2886 }
2887
2888 /*
2889 * Vertex elements & buffers
2890 */
2891
2892 static void *si_create_vertex_elements(struct pipe_context *ctx,
2893 unsigned count,
2894 const struct pipe_vertex_element *elements)
2895 {
2896 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2897 int i;
2898
2899 assert(count < PIPE_MAX_ATTRIBS);
2900 if (!v)
2901 return NULL;
2902
2903 v->count = count;
2904 for (i = 0; i < count; ++i) {
2905 const struct util_format_description *desc;
2906 unsigned data_format, num_format;
2907 int first_non_void;
2908
2909 desc = util_format_description(elements[i].src_format);
2910 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2911 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2912 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2913
2914 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2915 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2916 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2917 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2918 S_008F0C_NUM_FORMAT(num_format) |
2919 S_008F0C_DATA_FORMAT(data_format);
2920 }
2921 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2922
2923 return v;
2924 }
2925
2926 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2927 {
2928 struct r600_context *rctx = (struct r600_context *)ctx;
2929 struct si_vertex_element *v = (struct si_vertex_element*)state;
2930
2931 rctx->vertex_elements = v;
2932 }
2933
2934 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2935 {
2936 struct r600_context *rctx = (struct r600_context *)ctx;
2937
2938 if (rctx->vertex_elements == state)
2939 rctx->vertex_elements = NULL;
2940 FREE(state);
2941 }
2942
2943 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2944 const struct pipe_vertex_buffer *buffers)
2945 {
2946 struct r600_context *rctx = (struct r600_context *)ctx;
2947
2948 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2949 }
2950
2951 static void si_set_index_buffer(struct pipe_context *ctx,
2952 const struct pipe_index_buffer *ib)
2953 {
2954 struct r600_context *rctx = (struct r600_context *)ctx;
2955
2956 if (ib) {
2957 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2958 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2959 } else {
2960 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2961 }
2962 }
2963
2964 /*
2965 * Misc
2966 */
2967 static void si_set_polygon_stipple(struct pipe_context *ctx,
2968 const struct pipe_poly_stipple *state)
2969 {
2970 }
2971
2972 static void si_texture_barrier(struct pipe_context *ctx)
2973 {
2974 struct r600_context *rctx = (struct r600_context *)ctx;
2975
2976 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2977 R600_CONTEXT_FLUSH_AND_INV_CB;
2978 }
2979
2980 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
2981 {
2982 struct pipe_blend_state blend;
2983
2984 memset(&blend, 0, sizeof(blend));
2985 blend.independent_blend_enable = true;
2986 blend.rt[0].colormask = 0xf;
2987 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
2988 }
2989
2990 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
2991 struct pipe_resource *texture,
2992 const struct pipe_surface *surf_tmpl)
2993 {
2994 struct r600_texture *rtex = (struct r600_texture*)texture;
2995 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
2996 unsigned level = surf_tmpl->u.tex.level;
2997
2998 if (surface == NULL)
2999 return NULL;
3000
3001 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3002 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3003
3004 pipe_reference_init(&surface->base.reference, 1);
3005 pipe_resource_reference(&surface->base.texture, texture);
3006 surface->base.context = pipe;
3007 surface->base.format = surf_tmpl->format;
3008 surface->base.width = rtex->surface.level[level].npix_x;
3009 surface->base.height = rtex->surface.level[level].npix_y;
3010 surface->base.texture = texture;
3011 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3012 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3013 surface->base.u.tex.level = level;
3014
3015 return &surface->base;
3016 }
3017
3018 static void r600_surface_destroy(struct pipe_context *pipe,
3019 struct pipe_surface *surface)
3020 {
3021 pipe_resource_reference(&surface->texture, NULL);
3022 FREE(surface);
3023 }
3024
3025 static boolean si_dma_copy(struct pipe_context *ctx,
3026 struct pipe_resource *dst,
3027 unsigned dst_level,
3028 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3029 struct pipe_resource *src,
3030 unsigned src_level,
3031 const struct pipe_box *src_box)
3032 {
3033 /* XXX implement this or share evergreen_dma_blit with r600g */
3034 return FALSE;
3035 }
3036
3037 void si_init_state_functions(struct r600_context *rctx)
3038 {
3039 int i;
3040
3041 rctx->b.b.create_blend_state = si_create_blend_state;
3042 rctx->b.b.bind_blend_state = si_bind_blend_state;
3043 rctx->b.b.delete_blend_state = si_delete_blend_state;
3044 rctx->b.b.set_blend_color = si_set_blend_color;
3045
3046 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3047 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3048 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3049
3050 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3051 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3052 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3053
3054 for (i = 0; i < 8; i++) {
3055 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3056 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3057 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3058 }
3059 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3060 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3061 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3062
3063 rctx->b.b.set_clip_state = si_set_clip_state;
3064 rctx->b.b.set_scissor_states = si_set_scissor_states;
3065 rctx->b.b.set_viewport_states = si_set_viewport_states;
3066 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3067
3068 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3069 rctx->b.b.get_sample_position = si_get_sample_position;
3070
3071 rctx->b.b.create_vs_state = si_create_vs_state;
3072 rctx->b.b.create_fs_state = si_create_fs_state;
3073 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3074 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3075 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3076 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3077
3078 rctx->b.b.create_sampler_state = si_create_sampler_state;
3079 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3080 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3081
3082 rctx->b.b.create_sampler_view = si_create_sampler_view;
3083 rctx->b.b.set_sampler_views = si_set_sampler_views;
3084 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3085
3086 rctx->b.b.set_sample_mask = si_set_sample_mask;
3087
3088 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3089 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3090 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3091 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3092 rctx->b.b.set_index_buffer = si_set_index_buffer;
3093
3094 rctx->b.b.texture_barrier = si_texture_barrier;
3095 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3096 rctx->b.b.create_surface = r600_create_surface;
3097 rctx->b.b.surface_destroy = r600_surface_destroy;
3098 rctx->b.dma_copy = si_dma_copy;
3099
3100 rctx->b.b.draw_vbo = si_draw_vbo;
3101 }
3102
3103 void si_init_config(struct r600_context *rctx)
3104 {
3105 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3106
3107 if (pm4 == NULL)
3108 return;
3109
3110 si_cmd_context_control(pm4);
3111
3112 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3113
3114 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3115 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3116 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3117 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3118 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3119 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3120 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3121 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3122 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3123 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3124 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3125 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3126 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3127 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3128 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3129 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3130 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3131 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3132 if (rctx->b.chip_class == SI) {
3133 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3134 S_028AA8_SWITCH_ON_EOP(1) |
3135 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3136 S_028AA8_PRIMGROUP_SIZE(63));
3137 }
3138 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3139 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3140 if (rctx->b.chip_class < CIK)
3141 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3142 S_008A14_CLIP_VTX_REORDER_ENA(1));
3143
3144 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3145 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3146 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3147
3148 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3149
3150 if (rctx->b.chip_class >= CIK) {
3151 switch (rctx->screen->b.family) {
3152 case CHIP_BONAIRE:
3153 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3154 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3155 break;
3156 case CHIP_HAWAII:
3157 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3158 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3159 break;
3160 case CHIP_KAVERI:
3161 /* XXX todo */
3162 case CHIP_KABINI:
3163 /* XXX todo */
3164 default:
3165 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3166 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3167 break;
3168 }
3169 } else {
3170 switch (rctx->screen->b.family) {
3171 case CHIP_TAHITI:
3172 case CHIP_PITCAIRN:
3173 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3174 break;
3175 case CHIP_VERDE:
3176 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3177 break;
3178 case CHIP_OLAND:
3179 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3180 break;
3181 case CHIP_HAINAN:
3182 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3183 break;
3184 default:
3185 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3186 break;
3187 }
3188 }
3189
3190 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
3191 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3192 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3193 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3194 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
3195 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3196 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3197 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3198 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3199 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3200 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3201 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3202 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3203 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
3204 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3205 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3206 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3207 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3208 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3209 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3210 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3211 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3212
3213 if (rctx->b.chip_class >= CIK) {
3214 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3215 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3216 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3217 }
3218
3219 si_pm4_set_state(rctx, init, pm4);
3220 }