2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
38 unsigned img_format
:9;
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
46 #include "gfx10_format_table.h"
48 static unsigned si_map_swizzle(unsigned swizzle
)
52 return V_008F0C_SQ_SEL_Y
;
54 return V_008F0C_SQ_SEL_Z
;
56 return V_008F0C_SQ_SEL_W
;
58 return V_008F0C_SQ_SEL_0
;
60 return V_008F0C_SQ_SEL_1
;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X
;
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x
)
70 x
>= 4096 ? 0xffff : x
* 16;
74 * Inferred framebuffer and blender state.
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
79 static void si_emit_cb_render_state(struct si_context
*sctx
)
81 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
82 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
89 cb_target_mask
&= blend
->cb_target_mask
;
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
97 if (blend
&& blend
->dual_src_blend
&&
98 sctx
->ps_shader
.cso
&&
99 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
105 if (sctx
->screen
->dpbb_allowed
&&
106 sctx
->last_cb_target_mask
!= cb_target_mask
) {
107 sctx
->last_cb_target_mask
= cb_target_mask
;
109 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
110 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
113 unsigned initial_cdw
= cs
->current
.cdw
;
114 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
115 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
117 if (sctx
->chip_class
>= GFX8
) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
122 bool oc_disable
= blend
&&
123 blend
->blend_enable_4bit
& cb_target_mask
&&
124 sctx
->framebuffer
.nr_samples
>= 2;
125 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
127 radeon_opt_set_context_reg(
128 sctx
, R_028424_CB_DCC_CONTROL
,
129 SI_TRACKED_CB_DCC_CONTROL
,
130 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
131 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
132 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
133 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->has_dcc_constant_encode
));
136 /* RB+ register settings. */
137 if (sctx
->screen
->rbplus_allowed
) {
138 unsigned spi_shader_col_format
=
139 sctx
->ps_shader
.cso
?
140 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
141 unsigned sx_ps_downconvert
= 0;
142 unsigned sx_blend_opt_epsilon
= 0;
143 unsigned sx_blend_opt_control
= 0;
145 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
146 struct si_surface
*surf
=
147 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
148 unsigned format
, swap
, spi_format
, colormask
;
149 bool has_alpha
, has_rgb
;
152 /* If the color buffer is not set, the driver sets 32_R
153 * as the SPI color format, because the hw doesn't allow
154 * holes between color outputs, so also set this to
157 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
161 format
= G_028C70_FORMAT(surf
->cb_color_info
);
162 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
163 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
164 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
166 /* Set if RGB and A are present. */
167 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
169 if (format
== V_028C70_COLOR_8
||
170 format
== V_028C70_COLOR_16
||
171 format
== V_028C70_COLOR_32
)
172 has_rgb
= !has_alpha
;
176 /* Check the colormask and export format. */
177 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
179 if (!(colormask
& PIPE_MASK_A
))
182 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
187 /* Disable value checking for disabled channels. */
189 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
191 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
193 /* Enable down-conversion for 32bpp and smaller formats. */
195 case V_028C70_COLOR_8
:
196 case V_028C70_COLOR_8_8
:
197 case V_028C70_COLOR_8_8_8_8
:
198 /* For 1 and 2-channel formats, use the superset thereof. */
199 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
200 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
201 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
202 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
203 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
207 case V_028C70_COLOR_5_6_5
:
208 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
209 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
210 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
214 case V_028C70_COLOR_1_5_5_5
:
215 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
216 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
217 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
221 case V_028C70_COLOR_4_4_4_4
:
222 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
224 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
228 case V_028C70_COLOR_32
:
229 if (swap
== V_028C70_SWAP_STD
&&
230 spi_format
== V_028714_SPI_SHADER_32_R
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
232 else if (swap
== V_028C70_SWAP_ALT_REV
&&
233 spi_format
== V_028714_SPI_SHADER_32_AR
)
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
237 case V_028C70_COLOR_16
:
238 case V_028C70_COLOR_16_16
:
239 /* For 1-channel formats, use the superset thereof. */
240 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
241 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
242 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
243 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
244 if (swap
== V_028C70_SWAP_STD
||
245 swap
== V_028C70_SWAP_STD_REV
)
246 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
248 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
252 case V_028C70_COLOR_10_11_11
:
253 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
254 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
257 case V_028C70_COLOR_2_10_10_10
:
258 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
259 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
260 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
266 /* If there are no color outputs, the first color export is
267 * always enabled as 32_R, so also set this to enable RB+.
269 if (!sx_ps_downconvert
)
270 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
272 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
273 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
274 SI_TRACKED_SX_PS_DOWNCONVERT
,
275 sx_ps_downconvert
, sx_blend_opt_epsilon
,
276 sx_blend_opt_control
);
278 if (initial_cdw
!= cs
->current
.cdw
)
279 sctx
->context_roll
= true;
286 static uint32_t si_translate_blend_function(int blend_func
)
288 switch (blend_func
) {
290 return V_028780_COMB_DST_PLUS_SRC
;
291 case PIPE_BLEND_SUBTRACT
:
292 return V_028780_COMB_SRC_MINUS_DST
;
293 case PIPE_BLEND_REVERSE_SUBTRACT
:
294 return V_028780_COMB_DST_MINUS_SRC
;
296 return V_028780_COMB_MIN_DST_SRC
;
298 return V_028780_COMB_MAX_DST_SRC
;
300 PRINT_ERR("Unknown blend function %d\n", blend_func
);
307 static uint32_t si_translate_blend_factor(int blend_fact
)
309 switch (blend_fact
) {
310 case PIPE_BLENDFACTOR_ONE
:
311 return V_028780_BLEND_ONE
;
312 case PIPE_BLENDFACTOR_SRC_COLOR
:
313 return V_028780_BLEND_SRC_COLOR
;
314 case PIPE_BLENDFACTOR_SRC_ALPHA
:
315 return V_028780_BLEND_SRC_ALPHA
;
316 case PIPE_BLENDFACTOR_DST_ALPHA
:
317 return V_028780_BLEND_DST_ALPHA
;
318 case PIPE_BLENDFACTOR_DST_COLOR
:
319 return V_028780_BLEND_DST_COLOR
;
320 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
321 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
322 case PIPE_BLENDFACTOR_CONST_COLOR
:
323 return V_028780_BLEND_CONSTANT_COLOR
;
324 case PIPE_BLENDFACTOR_CONST_ALPHA
:
325 return V_028780_BLEND_CONSTANT_ALPHA
;
326 case PIPE_BLENDFACTOR_ZERO
:
327 return V_028780_BLEND_ZERO
;
328 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
330 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
331 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
332 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
333 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
334 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
335 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
336 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
337 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
338 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
340 case PIPE_BLENDFACTOR_SRC1_COLOR
:
341 return V_028780_BLEND_SRC1_COLOR
;
342 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
343 return V_028780_BLEND_SRC1_ALPHA
;
344 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
345 return V_028780_BLEND_INV_SRC1_COLOR
;
346 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
347 return V_028780_BLEND_INV_SRC1_ALPHA
;
349 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
356 static uint32_t si_translate_blend_opt_function(int blend_func
)
358 switch (blend_func
) {
360 return V_028760_OPT_COMB_ADD
;
361 case PIPE_BLEND_SUBTRACT
:
362 return V_028760_OPT_COMB_SUBTRACT
;
363 case PIPE_BLEND_REVERSE_SUBTRACT
:
364 return V_028760_OPT_COMB_REVSUBTRACT
;
366 return V_028760_OPT_COMB_MIN
;
368 return V_028760_OPT_COMB_MAX
;
370 return V_028760_OPT_COMB_BLEND_DISABLED
;
374 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
376 switch (blend_fact
) {
377 case PIPE_BLENDFACTOR_ZERO
:
378 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
379 case PIPE_BLENDFACTOR_ONE
:
380 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
381 case PIPE_BLENDFACTOR_SRC_COLOR
:
382 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
383 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
384 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
385 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
386 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
387 case PIPE_BLENDFACTOR_SRC_ALPHA
:
388 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
389 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
390 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
391 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
392 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
393 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
395 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
399 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
400 struct si_state_blend
*blend
,
401 enum pipe_blend_func func
,
402 enum pipe_blendfactor src
,
403 enum pipe_blendfactor dst
,
406 /* Src factor is allowed when it does not depend on Dst */
407 static const uint32_t src_allowed
=
408 (1u << PIPE_BLENDFACTOR_ONE
) |
409 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
412 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
413 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
414 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_ZERO
) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
418 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
419 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
420 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
421 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
422 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
424 if (dst
== PIPE_BLENDFACTOR_ONE
&&
425 (src_allowed
& (1u << src
))) {
426 /* Addition is commutative, but floating point addition isn't
427 * associative: subtle changes can be introduced via different
430 * Out-of-order is also non-deterministic, which means that
431 * this breaks OpenGL invariance requirements. So only enable
432 * out-of-order additive blending if explicitly allowed by a
435 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
436 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
437 blend
->commutative_4bit
|= chanmask
;
442 * Get rid of DST in the blend factors by commuting the operands:
443 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
445 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
446 unsigned *dst_factor
, unsigned expected_dst
,
447 unsigned replacement_src
)
449 if (*src_factor
== expected_dst
&&
450 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
451 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
452 *dst_factor
= replacement_src
;
454 /* Commuting the operands requires reversing subtractions. */
455 if (*func
== PIPE_BLEND_SUBTRACT
)
456 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
457 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
458 *func
= PIPE_BLEND_SUBTRACT
;
462 static bool si_blend_factor_uses_dst(unsigned factor
)
464 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
465 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
466 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
467 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
468 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
471 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
472 const struct pipe_blend_state
*state
,
475 struct si_context
*sctx
= (struct si_context
*)ctx
;
476 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
477 struct si_pm4_state
*pm4
= &blend
->pm4
;
478 uint32_t sx_mrt_blend_opt
[8] = {0};
479 uint32_t color_control
= 0;
484 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
485 blend
->alpha_to_one
= state
->alpha_to_one
;
486 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
487 blend
->logicop_enable
= state
->logicop_enable
;
489 if (state
->logicop_enable
) {
490 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
492 color_control
|= S_028808_ROP3(0xcc);
495 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
496 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
497 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
498 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
499 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
500 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
501 S_028B70_OFFSET_ROUND(1));
503 if (state
->alpha_to_coverage
)
504 blend
->need_src_alpha_4bit
|= 0xf;
506 blend
->cb_target_mask
= 0;
507 blend
->cb_target_enabled_4bit
= 0;
509 for (int i
= 0; i
< 8; i
++) {
510 /* state->rt entries > 0 only written if independent blending */
511 const int j
= state
->independent_blend_enable
? i
: 0;
513 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
514 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
515 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
516 unsigned eqA
= state
->rt
[j
].alpha_func
;
517 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
518 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
520 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
521 unsigned blend_cntl
= 0;
523 sx_mrt_blend_opt
[i
] =
524 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
525 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
527 /* Only set dual source blending for MRT0 to avoid a hang. */
528 if (i
>= 1 && blend
->dual_src_blend
) {
529 /* Vulkan does this for dual source blending. */
531 blend_cntl
|= S_028780_ENABLE(1);
533 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
537 /* Only addition and subtraction equations are supported with
538 * dual source blending.
540 if (blend
->dual_src_blend
&&
541 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
542 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
543 assert(!"Unsupported equation for dual source blending");
544 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
548 /* cb_render_state will disable unused ones */
549 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
550 if (state
->rt
[j
].colormask
)
551 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
553 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
554 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
558 si_blend_check_commutativity(sctx
->screen
, blend
,
559 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
560 si_blend_check_commutativity(sctx
->screen
, blend
,
561 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
563 /* Blending optimizations for RB+.
564 * These transformations don't change the behavior.
566 * First, get rid of DST in the blend factors:
567 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
569 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
570 PIPE_BLENDFACTOR_DST_COLOR
,
571 PIPE_BLENDFACTOR_SRC_COLOR
);
572 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
573 PIPE_BLENDFACTOR_DST_COLOR
,
574 PIPE_BLENDFACTOR_SRC_COLOR
);
575 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
576 PIPE_BLENDFACTOR_DST_ALPHA
,
577 PIPE_BLENDFACTOR_SRC_ALPHA
);
579 /* Look up the ideal settings from tables. */
580 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
581 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
582 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
583 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
585 /* Handle interdependencies. */
586 if (si_blend_factor_uses_dst(srcRGB
))
587 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
588 if (si_blend_factor_uses_dst(srcA
))
589 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
591 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
592 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
593 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
594 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
595 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
597 /* Set the final value. */
598 sx_mrt_blend_opt
[i
] =
599 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
600 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
601 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
602 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
603 S_028760_ALPHA_DST_OPT(dstA_opt
) |
604 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
606 /* Set blend state. */
607 blend_cntl
|= S_028780_ENABLE(1);
608 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
609 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
610 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
612 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
613 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
614 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
615 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
616 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
618 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
620 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
622 /* This is only important for formats without alpha. */
623 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
624 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
625 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
626 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
627 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
628 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
629 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
632 if (blend
->cb_target_mask
) {
633 color_control
|= S_028808_MODE(mode
);
635 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
638 if (sctx
->screen
->rbplus_allowed
) {
639 /* Disable RB+ blend optimizations for dual source blending.
642 if (blend
->dual_src_blend
) {
643 for (int i
= 0; i
< 8; i
++) {
644 sx_mrt_blend_opt
[i
] =
645 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
646 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
650 for (int i
= 0; i
< 8; i
++)
651 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
652 sx_mrt_blend_opt
[i
]);
654 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
655 if (blend
->dual_src_blend
|| state
->logicop_enable
||
656 mode
== V_028808_CB_RESOLVE
)
657 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
660 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
664 static void *si_create_blend_state(struct pipe_context
*ctx
,
665 const struct pipe_blend_state
*state
)
667 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
670 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
672 struct si_context
*sctx
= (struct si_context
*)ctx
;
673 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
674 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
679 si_pm4_bind_state(sctx
, blend
, state
);
682 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
683 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
684 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
685 sctx
->framebuffer
.nr_samples
>= 2 &&
686 sctx
->screen
->dcc_msaa_allowed
))
687 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
690 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
691 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
692 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
693 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
694 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
695 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
696 sctx
->do_update_shaders
= true;
698 if (sctx
->screen
->dpbb_allowed
&&
700 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
701 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
702 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
703 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
705 if (sctx
->screen
->has_out_of_order_rast
&&
707 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
708 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
709 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
710 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
711 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
714 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
716 struct si_context
*sctx
= (struct si_context
*)ctx
;
717 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
720 static void si_set_blend_color(struct pipe_context
*ctx
,
721 const struct pipe_blend_color
*state
)
723 struct si_context
*sctx
= (struct si_context
*)ctx
;
724 static const struct pipe_blend_color zeros
;
726 sctx
->blend_color
.state
= *state
;
727 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
728 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
731 static void si_emit_blend_color(struct si_context
*sctx
)
733 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
735 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
736 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
743 static void si_set_clip_state(struct pipe_context
*ctx
,
744 const struct pipe_clip_state
*state
)
746 struct si_context
*sctx
= (struct si_context
*)ctx
;
747 struct pipe_constant_buffer cb
;
748 static const struct pipe_clip_state zeros
;
750 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
753 sctx
->clip_state
.state
= *state
;
754 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
755 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
758 cb
.user_buffer
= state
->ucp
;
759 cb
.buffer_offset
= 0;
760 cb
.buffer_size
= 4*4*8;
761 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
762 pipe_resource_reference(&cb
.buffer
, NULL
);
765 static void si_emit_clip_state(struct si_context
*sctx
)
767 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
769 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
770 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
773 static void si_emit_clip_regs(struct si_context
*sctx
)
775 struct si_shader
*vs
= si_get_vs_state(sctx
);
776 struct si_shader_selector
*vs_sel
= vs
->selector
;
777 struct tgsi_shader_info
*info
= &vs_sel
->info
;
778 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
779 unsigned window_space
=
780 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
781 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
782 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
783 unsigned culldist_mask
= vs_sel
->culldist_mask
;
786 if (vs
->key
.opt
.clip_disable
) {
787 assert(!info
->culldist_writemask
);
791 total_mask
= clipdist_mask
| culldist_mask
;
793 /* Clip distances on points have no effect, so need to be implemented
794 * as cull distances. This applies for the clipvertex case as well.
796 * Setting this for primitives other than points should have no adverse
799 clipdist_mask
&= rs
->clip_plane_enable
;
800 culldist_mask
|= clipdist_mask
;
802 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
803 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
804 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
805 vs_sel
->pa_cl_vs_out_cntl
|
806 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
807 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
808 clipdist_mask
| (culldist_mask
<< 8));
809 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
810 SI_TRACKED_PA_CL_CLIP_CNTL
,
811 rs
->pa_cl_clip_cntl
|
813 S_028810_CLIP_DISABLE(window_space
));
815 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
816 sctx
->context_roll
= true;
820 * inferred state between framebuffer and rasterizer
822 static void si_update_poly_offset_state(struct si_context
*sctx
)
824 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
826 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
827 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
831 /* Use the user format, not db_render_format, so that the polygon
832 * offset behaves as expected by applications.
834 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
835 case PIPE_FORMAT_Z16_UNORM
:
836 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
838 default: /* 24-bit */
839 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
841 case PIPE_FORMAT_Z32_FLOAT
:
842 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
843 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
852 static uint32_t si_translate_fill(uint32_t func
)
855 case PIPE_POLYGON_MODE_FILL
:
856 return V_028814_X_DRAW_TRIANGLES
;
857 case PIPE_POLYGON_MODE_LINE
:
858 return V_028814_X_DRAW_LINES
;
859 case PIPE_POLYGON_MODE_POINT
:
860 return V_028814_X_DRAW_POINTS
;
863 return V_028814_X_DRAW_POINTS
;
867 static void *si_create_rs_state(struct pipe_context
*ctx
,
868 const struct pipe_rasterizer_state
*state
)
870 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
871 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
872 struct si_pm4_state
*pm4
= &rs
->pm4
;
874 float psize_min
, psize_max
;
880 if (!state
->front_ccw
) {
881 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
882 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
884 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
885 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
887 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
888 rs
->provoking_vertex_first
= state
->flatshade_first
;
889 rs
->scissor_enable
= state
->scissor
;
890 rs
->clip_halfz
= state
->clip_halfz
;
891 rs
->two_side
= state
->light_twoside
;
892 rs
->multisample_enable
= state
->multisample
;
893 rs
->force_persample_interp
= state
->force_persample_interp
;
894 rs
->clip_plane_enable
= state
->clip_plane_enable
;
895 rs
->half_pixel_center
= state
->half_pixel_center
;
896 rs
->line_stipple_enable
= state
->line_stipple_enable
;
897 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
898 rs
->line_smooth
= state
->line_smooth
;
899 rs
->line_width
= state
->line_width
;
900 rs
->poly_smooth
= state
->poly_smooth
;
901 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
903 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
904 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
905 rs
->flatshade
= state
->flatshade
;
906 rs
->flatshade_first
= state
->flatshade_first
;
907 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
908 rs
->rasterizer_discard
= state
->rasterizer_discard
;
909 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
910 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
911 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
912 rs
->pa_cl_clip_cntl
=
913 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
914 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
915 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
916 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
917 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
919 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
920 S_0286D4_FLAT_SHADE_ENA(1) |
921 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
922 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
923 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
924 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
925 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
926 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
928 /* point size 12.4 fixed point */
929 tmp
= (unsigned)(state
->point_size
* 8.0);
930 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
932 if (state
->point_size_per_vertex
) {
933 psize_min
= util_get_min_point_size(state
);
934 psize_max
= SI_MAX_POINT_SIZE
;
936 /* Force the point size to be as if the vertex output was disabled. */
937 psize_min
= state
->point_size
;
938 psize_max
= state
->point_size
;
940 rs
->max_point_size
= psize_max
;
942 /* Divide by two, because 0.5 = 1 pixel. */
943 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
944 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
945 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
947 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
948 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
949 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
950 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
951 S_028A48_MSAA_ENABLE(state
->multisample
||
952 state
->poly_smooth
||
953 state
->line_smooth
) |
954 S_028A48_VPORT_SCISSOR_ENABLE(1) |
955 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
957 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
958 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
959 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
960 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
961 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
962 S_028814_FACE(!state
->front_ccw
) |
963 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
964 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
965 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
966 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
967 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
968 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
969 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
971 if (!rs
->uses_poly_offset
)
974 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
975 if (!rs
->pm4_poly_offset
) {
980 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
981 for (i
= 0; i
< 3; i
++) {
982 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
983 float offset_units
= state
->offset_units
;
984 float offset_scale
= state
->offset_scale
* 16.0f
;
985 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
987 if (!state
->offset_units_unscaled
) {
989 case 0: /* 16-bit zbuffer */
990 offset_units
*= 4.0f
;
991 pa_su_poly_offset_db_fmt_cntl
=
992 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
994 case 1: /* 24-bit zbuffer */
995 offset_units
*= 2.0f
;
996 pa_su_poly_offset_db_fmt_cntl
=
997 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
999 case 2: /* 32-bit zbuffer */
1000 offset_units
*= 1.0f
;
1001 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1002 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1007 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
1009 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
1011 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
1013 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
1015 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
1016 pa_su_poly_offset_db_fmt_cntl
);
1022 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1024 struct si_context
*sctx
= (struct si_context
*)ctx
;
1025 struct si_state_rasterizer
*old_rs
=
1026 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1027 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1032 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1033 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1035 /* Update the small primitive filter workaround if necessary. */
1036 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1037 sctx
->framebuffer
.nr_samples
> 1)
1038 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1041 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1042 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1044 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1045 si_update_poly_offset_state(sctx
);
1048 old_rs
->scissor_enable
!= rs
->scissor_enable
)
1049 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1052 old_rs
->line_width
!= rs
->line_width
||
1053 old_rs
->max_point_size
!= rs
->max_point_size
||
1054 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1055 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1058 old_rs
->clip_halfz
!= rs
->clip_halfz
)
1059 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1062 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1063 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1064 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1066 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1067 rs
->line_stipple_enable
;
1070 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1071 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1072 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1073 old_rs
->flatshade
!= rs
->flatshade
||
1074 old_rs
->two_side
!= rs
->two_side
||
1075 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1076 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1077 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1078 old_rs
->line_smooth
!= rs
->line_smooth
||
1079 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1080 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1081 sctx
->do_update_shaders
= true;
1084 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1086 struct si_context
*sctx
= (struct si_context
*)ctx
;
1087 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1089 if (sctx
->queued
.named
.rasterizer
== state
)
1090 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1092 FREE(rs
->pm4_poly_offset
);
1093 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1097 * infeered state between dsa and stencil ref
1099 static void si_emit_stencil_ref(struct si_context
*sctx
)
1101 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1102 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1103 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1105 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1106 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1107 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1108 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1109 S_028430_STENCILOPVAL(1));
1110 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1111 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1112 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1113 S_028434_STENCILOPVAL_BF(1));
1116 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1117 const struct pipe_stencil_ref
*state
)
1119 struct si_context
*sctx
= (struct si_context
*)ctx
;
1121 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1124 sctx
->stencil_ref
.state
= *state
;
1125 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1133 static uint32_t si_translate_stencil_op(int s_op
)
1136 case PIPE_STENCIL_OP_KEEP
:
1137 return V_02842C_STENCIL_KEEP
;
1138 case PIPE_STENCIL_OP_ZERO
:
1139 return V_02842C_STENCIL_ZERO
;
1140 case PIPE_STENCIL_OP_REPLACE
:
1141 return V_02842C_STENCIL_REPLACE_TEST
;
1142 case PIPE_STENCIL_OP_INCR
:
1143 return V_02842C_STENCIL_ADD_CLAMP
;
1144 case PIPE_STENCIL_OP_DECR
:
1145 return V_02842C_STENCIL_SUB_CLAMP
;
1146 case PIPE_STENCIL_OP_INCR_WRAP
:
1147 return V_02842C_STENCIL_ADD_WRAP
;
1148 case PIPE_STENCIL_OP_DECR_WRAP
:
1149 return V_02842C_STENCIL_SUB_WRAP
;
1150 case PIPE_STENCIL_OP_INVERT
:
1151 return V_02842C_STENCIL_INVERT
;
1153 PRINT_ERR("Unknown stencil op %d", s_op
);
1160 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1162 return s
->enabled
&& s
->writemask
&&
1163 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1164 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1165 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1168 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1170 /* REPLACE is normally order invariant, except when the stencil
1171 * reference value is written by the fragment shader. Tracking this
1172 * interaction does not seem worth the effort, so be conservative. */
1173 return op
!= PIPE_STENCIL_OP_INCR
&&
1174 op
!= PIPE_STENCIL_OP_DECR
&&
1175 op
!= PIPE_STENCIL_OP_REPLACE
;
1178 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1179 * invariant in the sense that the set of passing fragments as well as the
1180 * final stencil buffer result does not depend on the order of fragments. */
1181 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1183 return !state
->enabled
|| !state
->writemask
||
1184 /* The following assumes that Z writes are disabled. */
1185 (state
->func
== PIPE_FUNC_ALWAYS
&&
1186 si_order_invariant_stencil_op(state
->zpass_op
) &&
1187 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1188 (state
->func
== PIPE_FUNC_NEVER
&&
1189 si_order_invariant_stencil_op(state
->fail_op
));
1192 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1193 const struct pipe_depth_stencil_alpha_state
*state
)
1195 struct si_context
*sctx
= (struct si_context
*)ctx
;
1196 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1197 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1198 unsigned db_depth_control
;
1199 uint32_t db_stencil_control
= 0;
1205 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1206 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1207 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1208 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1210 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1211 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1212 S_028800_ZFUNC(state
->depth
.func
) |
1213 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1216 if (state
->stencil
[0].enabled
) {
1217 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1218 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1219 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1220 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1221 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1223 if (state
->stencil
[1].enabled
) {
1224 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1225 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1226 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1227 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1228 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1233 if (state
->alpha
.enabled
) {
1234 dsa
->alpha_func
= state
->alpha
.func
;
1236 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1237 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1239 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1242 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1243 if (state
->stencil
[0].enabled
)
1244 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1245 if (state
->depth
.bounds_test
) {
1246 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1247 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1250 dsa
->depth_enabled
= state
->depth
.enabled
;
1251 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1252 state
->depth
.writemask
;
1253 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1254 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1255 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1256 si_dsa_writes_stencil(&state
->stencil
[1]));
1257 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1258 dsa
->stencil_write_enabled
;
1260 bool zfunc_is_ordered
=
1261 state
->depth
.func
== PIPE_FUNC_NEVER
||
1262 state
->depth
.func
== PIPE_FUNC_LESS
||
1263 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1264 state
->depth
.func
== PIPE_FUNC_GREATER
||
1265 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1267 bool nozwrite_and_order_invariant_stencil
=
1268 !dsa
->db_can_write
||
1269 (!dsa
->depth_write_enabled
&&
1270 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1271 si_order_invariant_stencil_state(&state
->stencil
[1]));
1273 dsa
->order_invariance
[1].zs
=
1274 nozwrite_and_order_invariant_stencil
||
1275 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1276 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1278 dsa
->order_invariance
[1].pass_set
=
1279 nozwrite_and_order_invariant_stencil
||
1280 (!dsa
->stencil_write_enabled
&&
1281 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1282 state
->depth
.func
== PIPE_FUNC_NEVER
));
1283 dsa
->order_invariance
[0].pass_set
=
1284 !dsa
->depth_write_enabled
||
1285 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1286 state
->depth
.func
== PIPE_FUNC_NEVER
);
1288 dsa
->order_invariance
[1].pass_last
=
1289 sctx
->screen
->assume_no_z_fights
&&
1290 !dsa
->stencil_write_enabled
&&
1291 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1292 dsa
->order_invariance
[0].pass_last
=
1293 sctx
->screen
->assume_no_z_fights
&&
1294 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1299 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1301 struct si_context
*sctx
= (struct si_context
*)ctx
;
1302 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1303 struct si_state_dsa
*dsa
= state
;
1308 si_pm4_bind_state(sctx
, dsa
, dsa
);
1310 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1311 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1312 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1313 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1316 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1317 sctx
->do_update_shaders
= true;
1319 if (sctx
->screen
->dpbb_allowed
&&
1321 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1322 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1323 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1324 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1326 if (sctx
->screen
->has_out_of_order_rast
&&
1328 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1329 sizeof(old_dsa
->order_invariance
))))
1330 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1333 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1335 struct si_context
*sctx
= (struct si_context
*)ctx
;
1336 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1339 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1341 struct pipe_depth_stencil_alpha_state dsa
= {};
1343 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1346 /* DB RENDER STATE */
1348 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1350 struct si_context
*sctx
= (struct si_context
*)ctx
;
1352 /* Pipeline stat & streamout queries. */
1354 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1355 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1357 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1358 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1361 /* Occlusion queries. */
1362 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1363 sctx
->occlusion_queries_disabled
= !enable
;
1364 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1368 void si_set_occlusion_query_state(struct si_context
*sctx
,
1369 bool old_perfect_enable
)
1371 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1373 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1375 if (perfect_enable
!= old_perfect_enable
)
1376 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1379 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1381 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1383 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1384 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1386 st
->saved_ssbo_writable_mask
= 0;
1388 for (unsigned i
= 0; i
< 3; i
++) {
1389 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1390 (1u << si_get_shaderbuf_slot(i
)))
1391 st
->saved_ssbo_writable_mask
|= 1 << i
;
1395 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1397 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1399 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1400 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1402 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1403 st
->saved_ssbo_writable_mask
);
1404 for (unsigned i
= 0; i
< 3; ++i
)
1405 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1408 static void si_emit_db_render_state(struct si_context
*sctx
)
1410 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1411 unsigned db_shader_control
, db_render_control
, db_count_control
;
1412 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1414 /* DB_RENDER_CONTROL */
1415 if (sctx
->dbcb_depth_copy_enabled
||
1416 sctx
->dbcb_stencil_copy_enabled
) {
1418 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1419 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1420 S_028000_COPY_CENTROID(1) |
1421 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1422 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1424 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1425 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1428 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1429 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1432 /* DB_COUNT_CONTROL (occlusion queries) */
1433 if (sctx
->num_occlusion_queries
> 0 &&
1434 !sctx
->occlusion_queries_disabled
) {
1435 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1436 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1438 if (sctx
->chip_class
>= GFX7
) {
1439 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1441 /* Stoney doesn't increment occlusion query counters
1442 * if the sample rate is 16x. Use 8x sample rate instead.
1444 if (sctx
->family
== CHIP_STONEY
)
1445 log_sample_rate
= MIN2(log_sample_rate
, 3);
1448 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1449 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1450 S_028004_SAMPLE_RATE(log_sample_rate
) |
1451 S_028004_ZPASS_ENABLE(1) |
1452 S_028004_SLICE_EVEN_ENABLE(1) |
1453 S_028004_SLICE_ODD_ENABLE(1);
1456 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1457 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1460 /* Disable occlusion queries. */
1461 if (sctx
->chip_class
>= GFX7
) {
1462 db_count_control
= 0;
1464 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1468 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1469 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1472 /* DB_RENDER_OVERRIDE2 */
1473 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1474 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1475 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1476 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1477 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1479 db_shader_control
= sctx
->ps_db_shader_control
;
1481 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1482 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1483 db_shader_control
&= C_02880C_Z_ORDER
;
1484 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1487 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1488 if (!rs
->multisample_enable
)
1489 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1491 if (sctx
->screen
->has_rbplus
&&
1492 !sctx
->screen
->rbplus_allowed
)
1493 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1495 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1496 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1498 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1499 sctx
->context_roll
= true;
1503 * format translation
1505 static uint32_t si_translate_colorformat(enum pipe_format format
)
1507 const struct util_format_description
*desc
= util_format_description(format
);
1509 return V_028C70_COLOR_INVALID
;
1511 #define HAS_SIZE(x,y,z,w) \
1512 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1513 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1515 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1516 return V_028C70_COLOR_10_11_11
;
1518 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1519 return V_028C70_COLOR_INVALID
;
1521 /* hw cannot support mixed formats (except depth/stencil, since
1522 * stencil is not written to). */
1523 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1524 return V_028C70_COLOR_INVALID
;
1526 switch (desc
->nr_channels
) {
1528 switch (desc
->channel
[0].size
) {
1530 return V_028C70_COLOR_8
;
1532 return V_028C70_COLOR_16
;
1534 return V_028C70_COLOR_32
;
1538 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1539 switch (desc
->channel
[0].size
) {
1541 return V_028C70_COLOR_8_8
;
1543 return V_028C70_COLOR_16_16
;
1545 return V_028C70_COLOR_32_32
;
1547 } else if (HAS_SIZE(8,24,0,0)) {
1548 return V_028C70_COLOR_24_8
;
1549 } else if (HAS_SIZE(24,8,0,0)) {
1550 return V_028C70_COLOR_8_24
;
1554 if (HAS_SIZE(5,6,5,0)) {
1555 return V_028C70_COLOR_5_6_5
;
1556 } else if (HAS_SIZE(32,8,24,0)) {
1557 return V_028C70_COLOR_X24_8_32_FLOAT
;
1561 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1562 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1563 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1564 switch (desc
->channel
[0].size
) {
1566 return V_028C70_COLOR_4_4_4_4
;
1568 return V_028C70_COLOR_8_8_8_8
;
1570 return V_028C70_COLOR_16_16_16_16
;
1572 return V_028C70_COLOR_32_32_32_32
;
1574 } else if (HAS_SIZE(5,5,5,1)) {
1575 return V_028C70_COLOR_1_5_5_5
;
1576 } else if (HAS_SIZE(1,5,5,5)) {
1577 return V_028C70_COLOR_5_5_5_1
;
1578 } else if (HAS_SIZE(10,10,10,2)) {
1579 return V_028C70_COLOR_2_10_10_10
;
1583 return V_028C70_COLOR_INVALID
;
1586 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1588 if (SI_BIG_ENDIAN
) {
1589 switch(colorformat
) {
1590 /* 8-bit buffers. */
1591 case V_028C70_COLOR_8
:
1592 return V_028C70_ENDIAN_NONE
;
1594 /* 16-bit buffers. */
1595 case V_028C70_COLOR_5_6_5
:
1596 case V_028C70_COLOR_1_5_5_5
:
1597 case V_028C70_COLOR_4_4_4_4
:
1598 case V_028C70_COLOR_16
:
1599 case V_028C70_COLOR_8_8
:
1600 return V_028C70_ENDIAN_8IN16
;
1602 /* 32-bit buffers. */
1603 case V_028C70_COLOR_8_8_8_8
:
1604 case V_028C70_COLOR_2_10_10_10
:
1605 case V_028C70_COLOR_8_24
:
1606 case V_028C70_COLOR_24_8
:
1607 case V_028C70_COLOR_16_16
:
1608 return V_028C70_ENDIAN_8IN32
;
1610 /* 64-bit buffers. */
1611 case V_028C70_COLOR_16_16_16_16
:
1612 return V_028C70_ENDIAN_8IN16
;
1614 case V_028C70_COLOR_32_32
:
1615 return V_028C70_ENDIAN_8IN32
;
1617 /* 128-bit buffers. */
1618 case V_028C70_COLOR_32_32_32_32
:
1619 return V_028C70_ENDIAN_8IN32
;
1621 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1624 return V_028C70_ENDIAN_NONE
;
1628 static uint32_t si_translate_dbformat(enum pipe_format format
)
1631 case PIPE_FORMAT_Z16_UNORM
:
1632 return V_028040_Z_16
;
1633 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1634 case PIPE_FORMAT_X8Z24_UNORM
:
1635 case PIPE_FORMAT_Z24X8_UNORM
:
1636 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1637 return V_028040_Z_24
; /* deprecated on AMD GCN */
1638 case PIPE_FORMAT_Z32_FLOAT
:
1639 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1640 return V_028040_Z_32_FLOAT
;
1642 return V_028040_Z_INVALID
;
1647 * Texture translation
1650 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1651 enum pipe_format format
,
1652 const struct util_format_description
*desc
,
1655 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1656 bool uniform
= true;
1659 assert(sscreen
->info
.chip_class
<= GFX9
);
1661 /* Colorspace (return non-RGB formats directly). */
1662 switch (desc
->colorspace
) {
1663 /* Depth stencil formats */
1664 case UTIL_FORMAT_COLORSPACE_ZS
:
1666 case PIPE_FORMAT_Z16_UNORM
:
1667 return V_008F14_IMG_DATA_FORMAT_16
;
1668 case PIPE_FORMAT_X24S8_UINT
:
1669 case PIPE_FORMAT_S8X24_UINT
:
1671 * Implemented as an 8_8_8_8 data format to fix texture
1672 * gathers in stencil sampling. This affects at least
1673 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1675 if (sscreen
->info
.chip_class
<= GFX8
)
1676 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1678 if (format
== PIPE_FORMAT_X24S8_UINT
)
1679 return V_008F14_IMG_DATA_FORMAT_8_24
;
1681 return V_008F14_IMG_DATA_FORMAT_24_8
;
1682 case PIPE_FORMAT_Z24X8_UNORM
:
1683 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1684 return V_008F14_IMG_DATA_FORMAT_8_24
;
1685 case PIPE_FORMAT_X8Z24_UNORM
:
1686 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1687 return V_008F14_IMG_DATA_FORMAT_24_8
;
1688 case PIPE_FORMAT_S8_UINT
:
1689 return V_008F14_IMG_DATA_FORMAT_8
;
1690 case PIPE_FORMAT_Z32_FLOAT
:
1691 return V_008F14_IMG_DATA_FORMAT_32
;
1692 case PIPE_FORMAT_X32_S8X24_UINT
:
1693 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1694 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1699 case UTIL_FORMAT_COLORSPACE_YUV
:
1700 goto out_unknown
; /* TODO */
1702 case UTIL_FORMAT_COLORSPACE_SRGB
:
1703 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1711 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1712 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1716 case PIPE_FORMAT_RGTC1_SNORM
:
1717 case PIPE_FORMAT_LATC1_SNORM
:
1718 case PIPE_FORMAT_RGTC1_UNORM
:
1719 case PIPE_FORMAT_LATC1_UNORM
:
1720 return V_008F14_IMG_DATA_FORMAT_BC4
;
1721 case PIPE_FORMAT_RGTC2_SNORM
:
1722 case PIPE_FORMAT_LATC2_SNORM
:
1723 case PIPE_FORMAT_RGTC2_UNORM
:
1724 case PIPE_FORMAT_LATC2_UNORM
:
1725 return V_008F14_IMG_DATA_FORMAT_BC5
;
1731 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1732 (sscreen
->info
.family
== CHIP_STONEY
||
1733 sscreen
->info
.family
== CHIP_VEGA10
||
1734 sscreen
->info
.family
== CHIP_RAVEN
)) {
1736 case PIPE_FORMAT_ETC1_RGB8
:
1737 case PIPE_FORMAT_ETC2_RGB8
:
1738 case PIPE_FORMAT_ETC2_SRGB8
:
1739 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1740 case PIPE_FORMAT_ETC2_RGB8A1
:
1741 case PIPE_FORMAT_ETC2_SRGB8A1
:
1742 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1743 case PIPE_FORMAT_ETC2_RGBA8
:
1744 case PIPE_FORMAT_ETC2_SRGBA8
:
1745 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1746 case PIPE_FORMAT_ETC2_R11_UNORM
:
1747 case PIPE_FORMAT_ETC2_R11_SNORM
:
1748 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1749 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1750 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1751 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1757 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1758 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1762 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1763 case PIPE_FORMAT_BPTC_SRGBA
:
1764 return V_008F14_IMG_DATA_FORMAT_BC7
;
1765 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1766 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1767 return V_008F14_IMG_DATA_FORMAT_BC6
;
1773 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1775 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1776 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1777 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1778 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1779 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1780 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1786 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1787 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1791 case PIPE_FORMAT_DXT1_RGB
:
1792 case PIPE_FORMAT_DXT1_RGBA
:
1793 case PIPE_FORMAT_DXT1_SRGB
:
1794 case PIPE_FORMAT_DXT1_SRGBA
:
1795 return V_008F14_IMG_DATA_FORMAT_BC1
;
1796 case PIPE_FORMAT_DXT3_RGBA
:
1797 case PIPE_FORMAT_DXT3_SRGBA
:
1798 return V_008F14_IMG_DATA_FORMAT_BC2
;
1799 case PIPE_FORMAT_DXT5_RGBA
:
1800 case PIPE_FORMAT_DXT5_SRGBA
:
1801 return V_008F14_IMG_DATA_FORMAT_BC3
;
1807 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1808 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1809 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1810 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1813 /* R8G8Bx_SNORM - TODO CxV8U8 */
1815 /* hw cannot support mixed formats (except depth/stencil, since only
1817 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1820 /* See whether the components are of the same size. */
1821 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1822 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1825 /* Non-uniform formats. */
1827 switch(desc
->nr_channels
) {
1829 if (desc
->channel
[0].size
== 5 &&
1830 desc
->channel
[1].size
== 6 &&
1831 desc
->channel
[2].size
== 5) {
1832 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1836 if (desc
->channel
[0].size
== 5 &&
1837 desc
->channel
[1].size
== 5 &&
1838 desc
->channel
[2].size
== 5 &&
1839 desc
->channel
[3].size
== 1) {
1840 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1842 if (desc
->channel
[0].size
== 1 &&
1843 desc
->channel
[1].size
== 5 &&
1844 desc
->channel
[2].size
== 5 &&
1845 desc
->channel
[3].size
== 5) {
1846 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1848 if (desc
->channel
[0].size
== 10 &&
1849 desc
->channel
[1].size
== 10 &&
1850 desc
->channel
[2].size
== 10 &&
1851 desc
->channel
[3].size
== 2) {
1852 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1859 if (first_non_void
< 0 || first_non_void
> 3)
1862 /* uniform formats */
1863 switch (desc
->channel
[first_non_void
].size
) {
1865 switch (desc
->nr_channels
) {
1866 #if 0 /* Not supported for render targets */
1868 return V_008F14_IMG_DATA_FORMAT_4_4
;
1871 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1875 switch (desc
->nr_channels
) {
1877 return V_008F14_IMG_DATA_FORMAT_8
;
1879 return V_008F14_IMG_DATA_FORMAT_8_8
;
1881 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1885 switch (desc
->nr_channels
) {
1887 return V_008F14_IMG_DATA_FORMAT_16
;
1889 return V_008F14_IMG_DATA_FORMAT_16_16
;
1891 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1895 switch (desc
->nr_channels
) {
1897 return V_008F14_IMG_DATA_FORMAT_32
;
1899 return V_008F14_IMG_DATA_FORMAT_32_32
;
1900 #if 0 /* Not supported for render targets */
1902 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1905 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1913 static unsigned si_tex_wrap(unsigned wrap
)
1917 case PIPE_TEX_WRAP_REPEAT
:
1918 return V_008F30_SQ_TEX_WRAP
;
1919 case PIPE_TEX_WRAP_CLAMP
:
1920 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1921 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1922 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1923 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1924 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1925 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1926 return V_008F30_SQ_TEX_MIRROR
;
1927 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1928 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1929 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1930 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1931 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1932 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1936 static unsigned si_tex_mipfilter(unsigned filter
)
1939 case PIPE_TEX_MIPFILTER_NEAREST
:
1940 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1941 case PIPE_TEX_MIPFILTER_LINEAR
:
1942 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1944 case PIPE_TEX_MIPFILTER_NONE
:
1945 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1949 static unsigned si_tex_compare(unsigned compare
)
1953 case PIPE_FUNC_NEVER
:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1955 case PIPE_FUNC_LESS
:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1957 case PIPE_FUNC_EQUAL
:
1958 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1959 case PIPE_FUNC_LEQUAL
:
1960 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1961 case PIPE_FUNC_GREATER
:
1962 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1963 case PIPE_FUNC_NOTEQUAL
:
1964 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1965 case PIPE_FUNC_GEQUAL
:
1966 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1967 case PIPE_FUNC_ALWAYS
:
1968 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1972 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1973 unsigned view_target
, unsigned nr_samples
)
1975 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1977 if (view_target
== PIPE_TEXTURE_CUBE
||
1978 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1979 res_target
= view_target
;
1980 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1981 else if (res_target
== PIPE_TEXTURE_CUBE
||
1982 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1983 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1985 /* GFX9 allocates 1D textures as 2D. */
1986 if ((res_target
== PIPE_TEXTURE_1D
||
1987 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1988 sscreen
->info
.chip_class
== GFX9
&&
1989 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1990 if (res_target
== PIPE_TEXTURE_1D
)
1991 res_target
= PIPE_TEXTURE_2D
;
1993 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1996 switch (res_target
) {
1998 case PIPE_TEXTURE_1D
:
1999 return V_008F1C_SQ_RSRC_IMG_1D
;
2000 case PIPE_TEXTURE_1D_ARRAY
:
2001 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
2002 case PIPE_TEXTURE_2D
:
2003 case PIPE_TEXTURE_RECT
:
2004 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
2005 V_008F1C_SQ_RSRC_IMG_2D
;
2006 case PIPE_TEXTURE_2D_ARRAY
:
2007 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
2008 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2009 case PIPE_TEXTURE_3D
:
2010 return V_008F1C_SQ_RSRC_IMG_3D
;
2011 case PIPE_TEXTURE_CUBE
:
2012 case PIPE_TEXTURE_CUBE_ARRAY
:
2013 return V_008F1C_SQ_RSRC_IMG_CUBE
;
2018 * Format support testing
2021 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
2023 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2025 if (sscreen
->info
.chip_class
>= GFX10
) {
2026 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2027 if (!fmt
->img_format
|| fmt
->buffers_only
)
2032 const struct util_format_description
*desc
= util_format_description(format
);
2036 return si_translate_texformat(screen
, format
, desc
,
2037 util_format_get_first_non_void_channel(format
)) != ~0U;
2040 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
2041 const struct util_format_description
*desc
,
2046 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2048 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2049 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
2051 assert(first_non_void
>= 0);
2053 if (desc
->nr_channels
== 4 &&
2054 desc
->channel
[0].size
== 10 &&
2055 desc
->channel
[1].size
== 10 &&
2056 desc
->channel
[2].size
== 10 &&
2057 desc
->channel
[3].size
== 2)
2058 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
2060 /* See whether the components are of the same size. */
2061 for (i
= 0; i
< desc
->nr_channels
; i
++) {
2062 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
2063 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2066 switch (desc
->channel
[first_non_void
].size
) {
2068 switch (desc
->nr_channels
) {
2070 case 3: /* 3 loads */
2071 return V_008F0C_BUF_DATA_FORMAT_8
;
2073 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2075 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2079 switch (desc
->nr_channels
) {
2081 case 3: /* 3 loads */
2082 return V_008F0C_BUF_DATA_FORMAT_16
;
2084 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2086 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2090 switch (desc
->nr_channels
) {
2092 return V_008F0C_BUF_DATA_FORMAT_32
;
2094 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2096 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2098 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2102 /* Legacy double formats. */
2103 switch (desc
->nr_channels
) {
2104 case 1: /* 1 load */
2105 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2106 case 2: /* 1 load */
2107 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2108 case 3: /* 3 loads */
2109 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2110 case 4: /* 2 loads */
2111 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2116 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2119 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2120 const struct util_format_description
*desc
,
2123 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2125 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2126 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2128 assert(first_non_void
>= 0);
2130 switch (desc
->channel
[first_non_void
].type
) {
2131 case UTIL_FORMAT_TYPE_SIGNED
:
2132 case UTIL_FORMAT_TYPE_FIXED
:
2133 if (desc
->channel
[first_non_void
].size
>= 32 ||
2134 desc
->channel
[first_non_void
].pure_integer
)
2135 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2136 else if (desc
->channel
[first_non_void
].normalized
)
2137 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2139 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2141 case UTIL_FORMAT_TYPE_UNSIGNED
:
2142 if (desc
->channel
[first_non_void
].size
>= 32 ||
2143 desc
->channel
[first_non_void
].pure_integer
)
2144 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2145 else if (desc
->channel
[first_non_void
].normalized
)
2146 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2148 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2150 case UTIL_FORMAT_TYPE_FLOAT
:
2152 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2156 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2157 enum pipe_format format
,
2160 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2161 const struct util_format_description
*desc
;
2163 unsigned data_format
;
2165 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2166 PIPE_BIND_SAMPLER_VIEW
|
2167 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2169 desc
= util_format_description(format
);
2173 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2174 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2175 * for read-only access (with caveats surrounding bounds checks), but
2176 * obviously fails for write access which we have to implement for
2177 * shader images. Luckily, OpenGL doesn't expect this to be supported
2178 * anyway, and so the only impact is on PBO uploads / downloads, which
2179 * shouldn't be expected to be fast for GL_RGB anyway.
2181 if (desc
->block
.bits
== 3 * 8 ||
2182 desc
->block
.bits
== 3 * 16) {
2183 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2184 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2190 if (sscreen
->info
.chip_class
>= GFX10
) {
2191 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2192 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2197 first_non_void
= util_format_get_first_non_void_channel(format
);
2198 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2199 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2205 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2207 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2208 si_translate_colorswap(format
, false) != ~0U;
2211 static bool si_is_zs_format_supported(enum pipe_format format
)
2213 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2216 static bool si_is_format_supported(struct pipe_screen
*screen
,
2217 enum pipe_format format
,
2218 enum pipe_texture_target target
,
2219 unsigned sample_count
,
2220 unsigned storage_sample_count
,
2223 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2224 unsigned retval
= 0;
2226 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2227 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2231 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2234 if (sample_count
> 1) {
2235 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2238 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2241 /* Only power-of-two sample counts are supported. */
2242 if (!util_is_power_of_two_or_zero(sample_count
) ||
2243 !util_is_power_of_two_or_zero(storage_sample_count
))
2246 /* MSAA support without framebuffer attachments. */
2247 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2250 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2251 util_format_is_depth_or_stencil(format
)) {
2252 /* Color without EQAA or depth/stencil. */
2253 if (sample_count
> 8 ||
2254 sample_count
!= storage_sample_count
)
2257 /* Color with EQAA. */
2258 if (sample_count
> 16 ||
2259 storage_sample_count
> 8)
2264 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2265 PIPE_BIND_SHADER_IMAGE
)) {
2266 if (target
== PIPE_BUFFER
) {
2267 retval
|= si_is_vertex_format_supported(
2268 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2269 PIPE_BIND_SHADER_IMAGE
));
2271 if (si_is_sampler_format_supported(screen
, format
))
2272 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2273 PIPE_BIND_SHADER_IMAGE
);
2277 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2278 PIPE_BIND_DISPLAY_TARGET
|
2281 PIPE_BIND_BLENDABLE
)) &&
2282 si_is_colorbuffer_format_supported(format
)) {
2284 (PIPE_BIND_RENDER_TARGET
|
2285 PIPE_BIND_DISPLAY_TARGET
|
2288 if (!util_format_is_pure_integer(format
) &&
2289 !util_format_is_depth_or_stencil(format
))
2290 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2293 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2294 si_is_zs_format_supported(format
)) {
2295 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2298 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2299 retval
|= si_is_vertex_format_supported(screen
, format
,
2300 PIPE_BIND_VERTEX_BUFFER
);
2303 if ((usage
& PIPE_BIND_LINEAR
) &&
2304 !util_format_is_compressed(format
) &&
2305 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2306 retval
|= PIPE_BIND_LINEAR
;
2308 return retval
== usage
;
2312 * framebuffer handling
2315 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2316 unsigned format
, unsigned swap
,
2317 unsigned ntype
, bool is_depth
)
2319 /* Alpha is needed for alpha-to-coverage.
2320 * Blending may be with or without alpha.
2322 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2323 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2324 unsigned blend
= 0; /* supports blending, but may not export alpha */
2325 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2327 /* Choose the SPI color formats. These are required values for RB+.
2328 * Other chips have multiple choices, though they are not necessarily better.
2331 case V_028C70_COLOR_5_6_5
:
2332 case V_028C70_COLOR_1_5_5_5
:
2333 case V_028C70_COLOR_5_5_5_1
:
2334 case V_028C70_COLOR_4_4_4_4
:
2335 case V_028C70_COLOR_10_11_11
:
2336 case V_028C70_COLOR_11_11_10
:
2337 case V_028C70_COLOR_8
:
2338 case V_028C70_COLOR_8_8
:
2339 case V_028C70_COLOR_8_8_8_8
:
2340 case V_028C70_COLOR_10_10_10_2
:
2341 case V_028C70_COLOR_2_10_10_10
:
2342 if (ntype
== V_028C70_NUMBER_UINT
)
2343 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2344 else if (ntype
== V_028C70_NUMBER_SINT
)
2345 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2347 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2350 case V_028C70_COLOR_16
:
2351 case V_028C70_COLOR_16_16
:
2352 case V_028C70_COLOR_16_16_16_16
:
2353 if (ntype
== V_028C70_NUMBER_UNORM
||
2354 ntype
== V_028C70_NUMBER_SNORM
) {
2355 /* UNORM16 and SNORM16 don't support blending */
2356 if (ntype
== V_028C70_NUMBER_UNORM
)
2357 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2359 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2361 /* Use 32 bits per channel for blending. */
2362 if (format
== V_028C70_COLOR_16
) {
2363 if (swap
== V_028C70_SWAP_STD
) { /* R */
2364 blend
= V_028714_SPI_SHADER_32_R
;
2365 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2366 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2367 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2370 } else if (format
== V_028C70_COLOR_16_16
) {
2371 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2372 blend
= V_028714_SPI_SHADER_32_GR
;
2373 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2374 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2375 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2378 } else /* 16_16_16_16 */
2379 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2380 } else if (ntype
== V_028C70_NUMBER_UINT
)
2381 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2382 else if (ntype
== V_028C70_NUMBER_SINT
)
2383 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2384 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2385 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2390 case V_028C70_COLOR_32
:
2391 if (swap
== V_028C70_SWAP_STD
) { /* R */
2392 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2393 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2394 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2395 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2400 case V_028C70_COLOR_32_32
:
2401 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2402 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2403 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2404 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2405 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2410 case V_028C70_COLOR_32_32_32_32
:
2411 case V_028C70_COLOR_8_24
:
2412 case V_028C70_COLOR_24_8
:
2413 case V_028C70_COLOR_X24_8_32_FLOAT
:
2414 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2422 /* The DB->CB copy needs 32_ABGR. */
2424 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2426 surf
->spi_shader_col_format
= normal
;
2427 surf
->spi_shader_col_format_alpha
= alpha
;
2428 surf
->spi_shader_col_format_blend
= blend
;
2429 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2432 static void si_initialize_color_surface(struct si_context
*sctx
,
2433 struct si_surface
*surf
)
2435 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2436 unsigned color_info
, color_attrib
;
2437 unsigned format
, swap
, ntype
, endian
;
2438 const struct util_format_description
*desc
;
2440 unsigned blend_clamp
= 0, blend_bypass
= 0;
2442 desc
= util_format_description(surf
->base
.format
);
2443 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2444 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2448 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2449 ntype
= V_028C70_NUMBER_FLOAT
;
2451 ntype
= V_028C70_NUMBER_UNORM
;
2452 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2453 ntype
= V_028C70_NUMBER_SRGB
;
2454 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2455 if (desc
->channel
[firstchan
].pure_integer
) {
2456 ntype
= V_028C70_NUMBER_SINT
;
2458 assert(desc
->channel
[firstchan
].normalized
);
2459 ntype
= V_028C70_NUMBER_SNORM
;
2461 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2462 if (desc
->channel
[firstchan
].pure_integer
) {
2463 ntype
= V_028C70_NUMBER_UINT
;
2465 assert(desc
->channel
[firstchan
].normalized
);
2466 ntype
= V_028C70_NUMBER_UNORM
;
2471 format
= si_translate_colorformat(surf
->base
.format
);
2472 if (format
== V_028C70_COLOR_INVALID
) {
2473 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2475 assert(format
!= V_028C70_COLOR_INVALID
);
2476 swap
= si_translate_colorswap(surf
->base
.format
, false);
2477 endian
= si_colorformat_endian_swap(format
);
2479 /* blend clamp should be set for all NORM/SRGB types */
2480 if (ntype
== V_028C70_NUMBER_UNORM
||
2481 ntype
== V_028C70_NUMBER_SNORM
||
2482 ntype
== V_028C70_NUMBER_SRGB
)
2485 /* set blend bypass according to docs if SINT/UINT or
2486 8/24 COLOR variants */
2487 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2488 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2489 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2494 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2495 if (format
== V_028C70_COLOR_8
||
2496 format
== V_028C70_COLOR_8_8
||
2497 format
== V_028C70_COLOR_8_8_8_8
)
2498 surf
->color_is_int8
= true;
2499 else if (format
== V_028C70_COLOR_10_10_10_2
||
2500 format
== V_028C70_COLOR_2_10_10_10
)
2501 surf
->color_is_int10
= true;
2504 color_info
= S_028C70_FORMAT(format
) |
2505 S_028C70_COMP_SWAP(swap
) |
2506 S_028C70_BLEND_CLAMP(blend_clamp
) |
2507 S_028C70_BLEND_BYPASS(blend_bypass
) |
2508 S_028C70_SIMPLE_FLOAT(1) |
2509 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2510 ntype
!= V_028C70_NUMBER_SNORM
&&
2511 ntype
!= V_028C70_NUMBER_SRGB
&&
2512 format
!= V_028C70_COLOR_8_24
&&
2513 format
!= V_028C70_COLOR_24_8
) |
2514 S_028C70_NUMBER_TYPE(ntype
) |
2515 S_028C70_ENDIAN(endian
);
2517 /* Intensity is implemented as Red, so treat it that way. */
2518 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2519 util_format_is_intensity(surf
->base
.format
));
2521 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2522 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2523 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2525 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2526 S_028C74_NUM_FRAGMENTS(log_fragments
);
2528 if (tex
->fmask_offset
) {
2529 color_info
|= S_028C70_COMPRESSION(1);
2530 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2532 if (sctx
->chip_class
== GFX6
) {
2533 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2534 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2539 if (sctx
->chip_class
>= GFX10
) {
2540 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2542 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2543 64 for APU because all of our APUs to date use DIMMs which have
2544 a request granularity size of 64B while all other chips have a
2546 if (!sctx
->screen
->info
.has_dedicated_vram
)
2547 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2549 surf
->cb_dcc_control
=
2550 S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2551 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2552 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2553 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2554 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2555 } else if (sctx
->chip_class
>= GFX8
) {
2556 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2557 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2559 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2560 64 for APU because all of our APUs to date use DIMMs which have
2561 a request granularity size of 64B while all other chips have a
2563 if (!sctx
->screen
->info
.has_dedicated_vram
)
2564 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2566 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2567 if (tex
->surface
.bpe
== 1)
2568 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2569 else if (tex
->surface
.bpe
== 2)
2570 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2573 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2574 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2575 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2578 /* This must be set for fast clear to work without FMASK. */
2579 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2580 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2581 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2584 /* GFX10 field has the same base shift as the GFX6 field */
2585 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2586 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2587 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2589 if (sctx
->chip_class
>= GFX10
) {
2590 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2592 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2593 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2594 S_028EE0_RESOURCE_LEVEL(1);
2595 } else if (sctx
->chip_class
== GFX9
) {
2596 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2597 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2598 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2601 if (sctx
->chip_class
>= GFX9
) {
2602 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2603 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2604 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2607 surf
->cb_color_view
= color_view
;
2608 surf
->cb_color_info
= color_info
;
2609 surf
->cb_color_attrib
= color_attrib
;
2611 /* Determine pixel shader export format */
2612 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2614 surf
->color_initialized
= true;
2617 static void si_init_depth_surface(struct si_context
*sctx
,
2618 struct si_surface
*surf
)
2620 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2621 unsigned level
= surf
->base
.u
.tex
.level
;
2622 unsigned format
, stencil_format
;
2623 uint32_t z_info
, s_info
;
2625 format
= si_translate_dbformat(tex
->db_render_format
);
2626 stencil_format
= tex
->surface
.has_stencil
?
2627 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2629 assert(format
!= V_028040_Z_INVALID
);
2630 if (format
== V_028040_Z_INVALID
)
2631 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2633 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2634 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2635 surf
->db_htile_data_base
= 0;
2636 surf
->db_htile_surface
= 0;
2638 if (sctx
->chip_class
>= GFX10
) {
2639 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2640 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2643 if (sctx
->chip_class
>= GFX9
) {
2644 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2645 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2646 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2647 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2648 z_info
= S_028038_FORMAT(format
) |
2649 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2650 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2651 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2652 s_info
= S_02803C_FORMAT(stencil_format
) |
2653 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2655 if (sctx
->chip_class
== GFX9
) {
2656 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2657 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2659 surf
->db_depth_view
|= S_028008_MIPID(level
);
2660 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2661 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2663 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2664 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2665 S_028038_ALLOW_EXPCLEAR(1);
2667 if (tex
->tc_compatible_htile
) {
2668 unsigned max_zplanes
= 4;
2670 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2671 tex
->buffer
.b
.b
.nr_samples
> 1)
2674 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2676 if (sctx
->chip_class
>= GFX10
) {
2677 z_info
|= S_028040_ITERATE_FLUSH(1);
2678 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2680 z_info
|= S_028038_ITERATE_FLUSH(1);
2681 s_info
|= S_02803C_ITERATE_FLUSH(1);
2685 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2686 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2687 * See that for explanation.
2689 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2691 /* Use all HTILE for depth if there's no stencil. */
2692 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2695 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2696 tex
->htile_offset
) >> 8;
2697 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2698 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2699 if (sctx
->chip_class
== GFX9
) {
2700 surf
->db_htile_surface
|=
2701 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2706 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2708 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2710 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2711 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2712 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2713 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2715 z_info
= S_028040_FORMAT(format
) |
2716 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2717 s_info
= S_028044_FORMAT(stencil_format
);
2718 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2720 if (sctx
->chip_class
>= GFX7
) {
2721 struct radeon_info
*info
= &sctx
->screen
->info
;
2722 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2723 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2724 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2725 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2726 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2727 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2729 surf
->db_depth_info
|=
2730 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2731 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2732 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2733 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2734 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2735 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2736 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2737 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2739 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2740 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2741 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2742 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2745 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2746 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2747 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2748 levelinfo
->nblk_y
) / 64 - 1);
2750 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2751 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2752 S_028040_ALLOW_EXPCLEAR(1);
2754 if (tex
->surface
.has_stencil
) {
2755 /* Workaround: For a not yet understood reason, the
2756 * combination of MSAA, fast stencil clear and stencil
2757 * decompress messes with subsequent stencil buffer
2758 * uses. Problem was reproduced on Verde, Bonaire,
2759 * Tonga, and Carrizo.
2761 * Disabling EXPCLEAR works around the problem.
2763 * Check piglit's arb_texture_multisample-stencil-clear
2764 * test if you want to try changing this.
2766 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2767 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2768 } else if (!tex
->tc_compatible_htile
) {
2769 /* Use all of the htile_buffer for depth if there's no stencil.
2770 * This must not be set when TC-compatible HTILE is enabled
2773 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2776 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2777 tex
->htile_offset
) >> 8;
2778 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2780 if (tex
->tc_compatible_htile
) {
2781 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2783 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2784 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2785 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2786 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2787 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2789 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2794 surf
->db_z_info
= z_info
;
2795 surf
->db_stencil_info
= s_info
;
2797 surf
->depth_initialized
= true;
2800 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2802 if (sctx
->decompression_enabled
)
2805 if (sctx
->framebuffer
.state
.zsbuf
) {
2806 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2807 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2809 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2811 if (tex
->surface
.has_stencil
)
2812 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2815 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2816 while (compressed_cb_mask
) {
2817 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2818 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2819 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2821 if (tex
->fmask_offset
)
2822 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2823 if (tex
->dcc_gather_statistics
)
2824 tex
->separate_dcc_dirty
= true;
2828 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2830 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2831 struct si_surface
*surf
= NULL
;
2832 struct si_texture
*tex
;
2834 if (!state
->cbufs
[i
])
2836 surf
= (struct si_surface
*)state
->cbufs
[i
];
2837 tex
= (struct si_texture
*)surf
->base
.texture
;
2839 p_atomic_dec(&tex
->framebuffers_bound
);
2843 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2844 const struct pipe_framebuffer_state
*state
)
2846 struct si_context
*sctx
= (struct si_context
*)ctx
;
2847 struct si_surface
*surf
= NULL
;
2848 struct si_texture
*tex
;
2849 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2850 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2851 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2852 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2853 bool old_has_stencil
=
2855 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2856 bool unbound
= false;
2859 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2860 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2861 * We could implement the full workaround here, but it's a useless case.
2863 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2864 unreachable("the framebuffer shouldn't have zero area");
2868 si_update_fb_dirtiness_after_rendering(sctx
);
2870 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2871 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2874 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2875 if (tex
->dcc_gather_statistics
)
2876 vi_separate_dcc_stop_query(sctx
, tex
);
2879 /* Disable DCC if the formats are incompatible. */
2880 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2881 if (!state
->cbufs
[i
])
2884 surf
= (struct si_surface
*)state
->cbufs
[i
];
2885 tex
= (struct si_texture
*)surf
->base
.texture
;
2887 if (!surf
->dcc_incompatible
)
2890 /* Since the DCC decompression calls back into set_framebuffer-
2891 * _state, we need to unbind the framebuffer, so that
2892 * vi_separate_dcc_stop_query isn't called twice with the same
2896 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2900 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2901 if (!si_texture_disable_dcc(sctx
, tex
))
2902 si_decompress_dcc(sctx
, tex
);
2904 surf
->dcc_incompatible
= false;
2907 /* Only flush TC when changing the framebuffer state, because
2908 * the only client not using TC that can change textures is
2911 * Wait for compute shaders because of possible transitions:
2912 * - FB write -> shader read
2913 * - shader write -> FB read
2915 * DB caches are flushed on demand (using si_decompress_textures).
2917 * When MSAA is enabled, CB and TC caches are flushed on demand
2918 * (after FMASK decompression). Shader write -> FB read transitions
2919 * cannot happen for MSAA textures, because MSAA shader images are
2922 * Only flush and wait for CB if there is actually a bound color buffer.
2924 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2925 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2926 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2927 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2930 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2932 /* u_blitter doesn't invoke depth decompression when it does multiple
2933 * blits in a row, but the only case when it matters for DB is when
2934 * doing generate_mipmap. So here we flush DB manually between
2935 * individual generate_mipmap blits.
2936 * Note that lower mipmap levels aren't compressed.
2938 if (sctx
->generate_mipmap_for_depth
) {
2939 si_make_DB_shader_coherent(sctx
, 1, false,
2940 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2941 } else if (sctx
->chip_class
== GFX9
) {
2942 /* It appears that DB metadata "leaks" in a sequence of:
2944 * - DCC decompress for shader image writes (with DB disabled)
2945 * - render with DEPTH_BEFORE_SHADER=1
2946 * Flushing DB metadata works around the problem.
2948 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2951 /* Take the maximum of the old and new count. If the new count is lower,
2952 * dirtying is needed to disable the unbound colorbuffers.
2954 sctx
->framebuffer
.dirty_cbufs
|=
2955 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2956 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2958 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2959 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2961 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2962 sctx
->framebuffer
.spi_shader_col_format
= 0;
2963 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2964 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2965 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2966 sctx
->framebuffer
.color_is_int8
= 0;
2967 sctx
->framebuffer
.color_is_int10
= 0;
2969 sctx
->framebuffer
.compressed_cb_mask
= 0;
2970 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2971 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2972 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2973 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2974 sctx
->framebuffer
.any_dst_linear
= false;
2975 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2976 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2977 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2978 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2980 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2981 if (!state
->cbufs
[i
])
2984 surf
= (struct si_surface
*)state
->cbufs
[i
];
2985 tex
= (struct si_texture
*)surf
->base
.texture
;
2987 if (!surf
->color_initialized
) {
2988 si_initialize_color_surface(sctx
, surf
);
2991 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2992 sctx
->framebuffer
.spi_shader_col_format
|=
2993 surf
->spi_shader_col_format
<< (i
* 4);
2994 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2995 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2996 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2997 surf
->spi_shader_col_format_blend
<< (i
* 4);
2998 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2999 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
3001 if (surf
->color_is_int8
)
3002 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
3003 if (surf
->color_is_int10
)
3004 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
3006 if (tex
->fmask_offset
)
3007 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3009 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
3011 /* Don't update nr_color_samples for non-AA buffers.
3012 * (e.g. destination of MSAA resolve)
3014 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
3015 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
3016 sctx
->framebuffer
.nr_color_samples
=
3017 MIN2(sctx
->framebuffer
.nr_color_samples
,
3018 tex
->buffer
.b
.b
.nr_storage_samples
);
3019 sctx
->framebuffer
.nr_color_samples
=
3020 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
3023 if (tex
->surface
.is_linear
)
3024 sctx
->framebuffer
.any_dst_linear
= true;
3026 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
3027 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
3029 if (sctx
->chip_class
>= GFX9
&&
3030 !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
3031 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
3034 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3036 p_atomic_inc(&tex
->framebuffers_bound
);
3038 if (tex
->dcc_gather_statistics
) {
3039 /* Dirty tracking must be enabled for DCC usage analysis. */
3040 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
3041 vi_separate_dcc_start_query(sctx
, tex
);
3044 /* Update the minimum but don't keep 0. */
3045 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3046 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3047 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
3050 /* For optimal DCC performance. */
3051 if (sctx
->chip_class
>= GFX10
)
3052 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
3054 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
3056 struct si_texture
*zstex
= NULL
;
3059 surf
= (struct si_surface
*)state
->zsbuf
;
3060 zstex
= (struct si_texture
*)surf
->base
.texture
;
3062 if (!surf
->depth_initialized
) {
3063 si_init_depth_surface(sctx
, surf
);
3066 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
,
3068 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
3070 si_context_add_resource_size(sctx
, surf
->base
.texture
);
3072 /* Update the minimum but don't keep 0. */
3073 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
3074 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
3075 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
3078 si_update_ps_colorbuf0_slot(sctx
);
3079 si_update_poly_offset_state(sctx
);
3080 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3081 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
3083 if (sctx
->screen
->dpbb_allowed
)
3084 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3086 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
3087 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3089 if (sctx
->screen
->has_out_of_order_rast
&&
3090 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
3091 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
3092 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
3093 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3095 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
3096 struct pipe_constant_buffer constbuf
= {0};
3098 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3099 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3101 constbuf
.buffer
= sctx
->sample_pos_buffer
;
3103 /* Set sample locations as fragment shader constants. */
3104 switch (sctx
->framebuffer
.nr_samples
) {
3106 constbuf
.buffer_offset
= 0;
3109 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
3110 (ubyte
*)sctx
->sample_positions
.x1
;
3113 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
3114 (ubyte
*)sctx
->sample_positions
.x1
;
3117 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
3118 (ubyte
*)sctx
->sample_positions
.x1
;
3121 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
3122 (ubyte
*)sctx
->sample_positions
.x1
;
3125 PRINT_ERR("Requested an invalid number of samples %i.\n",
3126 sctx
->framebuffer
.nr_samples
);
3129 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
3130 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
3132 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3135 sctx
->do_update_shaders
= true;
3137 if (!sctx
->decompression_enabled
) {
3138 /* Prevent textures decompression when the framebuffer state
3139 * changes come from the decompression passes themselves.
3141 sctx
->need_check_render_feedback
= true;
3145 static void si_emit_framebuffer_state(struct si_context
*sctx
)
3147 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3148 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3149 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3150 struct si_texture
*tex
= NULL
;
3151 struct si_surface
*cb
= NULL
;
3152 unsigned cb_color_info
= 0;
3155 for (i
= 0; i
< nr_cbufs
; i
++) {
3156 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3157 unsigned cb_color_attrib
;
3159 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3162 cb
= (struct si_surface
*)state
->cbufs
[i
];
3164 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3165 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3169 tex
= (struct si_texture
*)cb
->base
.texture
;
3170 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3171 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3172 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3173 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3174 RADEON_PRIO_COLOR_BUFFER
);
3176 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3177 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3178 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3179 RADEON_PRIO_SEPARATE_META
);
3182 if (tex
->dcc_separate_buffer
)
3183 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3184 tex
->dcc_separate_buffer
,
3185 RADEON_USAGE_READWRITE
,
3186 RADEON_PRIO_SEPARATE_META
);
3188 /* Compute mutable surface parameters. */
3189 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3191 cb_color_cmask
= tex
->cmask_base_address_reg
;
3193 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3194 cb_color_attrib
= cb
->cb_color_attrib
;
3196 if (cb
->base
.u
.tex
.level
> 0)
3197 cb_color_info
&= C_028C70_FAST_CLEAR
;
3199 if (tex
->fmask_offset
) {
3200 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3201 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3205 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3206 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3207 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3208 state
->cbufs
[1] == &cb
->base
&&
3209 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3211 if (!is_msaa_resolve_dst
)
3212 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3214 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3215 tex
->dcc_offset
) >> 8;
3217 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3218 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3219 cb_dcc_base
|= dcc_tile_swizzle
;
3222 if (sctx
->chip_class
>= GFX10
) {
3223 unsigned cb_color_attrib3
;
3225 /* Set mutable surface parameters. */
3226 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3227 cb_color_base
|= tex
->surface
.tile_swizzle
;
3228 if (!tex
->fmask_offset
)
3229 cb_color_fmask
= cb_color_base
;
3230 if (cb
->base
.u
.tex
.level
> 0)
3231 cb_color_cmask
= cb_color_base
;
3233 cb_color_attrib3
= cb
->cb_color_attrib3
|
3234 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3235 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3236 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3237 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3239 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3240 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3241 radeon_emit(cs
, 0); /* hole */
3242 radeon_emit(cs
, 0); /* hole */
3243 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3244 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3245 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3246 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3247 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3248 radeon_emit(cs
, 0); /* hole */
3249 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3250 radeon_emit(cs
, 0); /* hole */
3251 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3252 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3253 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3255 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4,
3256 cb_color_base
>> 32);
3257 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3258 cb_color_cmask
>> 32);
3259 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3260 cb_color_fmask
>> 32);
3261 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4,
3263 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4,
3264 cb
->cb_color_attrib2
);
3265 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4,
3267 } else if (sctx
->chip_class
== GFX9
) {
3268 struct gfx9_surf_meta_flags meta
;
3270 if (tex
->dcc_offset
)
3271 meta
= tex
->surface
.u
.gfx9
.dcc
;
3273 meta
= tex
->surface
.u
.gfx9
.cmask
;
3275 /* Set mutable surface parameters. */
3276 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3277 cb_color_base
|= tex
->surface
.tile_swizzle
;
3278 if (!tex
->fmask_offset
)
3279 cb_color_fmask
= cb_color_base
;
3280 if (cb
->base
.u
.tex
.level
> 0)
3281 cb_color_cmask
= cb_color_base
;
3282 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3283 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3284 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3285 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3287 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3288 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3289 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3290 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3291 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3292 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3293 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3294 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3295 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3296 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3297 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3298 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3299 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3300 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3301 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3302 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3304 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3305 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3307 /* Compute mutable surface parameters (GFX6-GFX8). */
3308 const struct legacy_surf_level
*level_info
=
3309 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3310 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3311 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3313 cb_color_base
+= level_info
->offset
>> 8;
3314 /* Only macrotiled modes can set tile swizzle. */
3315 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3316 cb_color_base
|= tex
->surface
.tile_swizzle
;
3318 if (!tex
->fmask_offset
)
3319 cb_color_fmask
= cb_color_base
;
3320 if (cb
->base
.u
.tex
.level
> 0)
3321 cb_color_cmask
= cb_color_base
;
3323 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3325 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3326 slice_tile_max
= level_info
->nblk_x
*
3327 level_info
->nblk_y
/ 64 - 1;
3328 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3330 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3331 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3332 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3334 if (tex
->fmask_offset
) {
3335 if (sctx
->chip_class
>= GFX7
)
3336 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3337 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3338 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3340 /* This must be set for fast clear to work without FMASK. */
3341 if (sctx
->chip_class
>= GFX7
)
3342 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3343 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3344 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3347 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3348 sctx
->chip_class
>= GFX8
? 14 : 13);
3349 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3350 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3351 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3352 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3353 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3354 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3355 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3356 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3357 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3358 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3359 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3360 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3361 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3363 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3364 radeon_emit(cs
, cb_dcc_base
);
3368 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3369 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3372 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3373 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3374 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3376 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3377 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3378 zb
->base
.texture
->nr_samples
> 1 ?
3379 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3380 RADEON_PRIO_DEPTH_BUFFER
);
3382 if (sctx
->chip_class
>= GFX10
) {
3383 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3384 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3386 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3387 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3388 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3389 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3390 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3391 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3392 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3393 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3394 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3396 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3397 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3398 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3399 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3400 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3401 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3402 } else if (sctx
->chip_class
== GFX9
) {
3403 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3404 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3405 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3406 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3408 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3409 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3410 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3411 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3412 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3413 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3414 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3415 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3416 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3417 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3418 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3419 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3421 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3422 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3423 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3425 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3427 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3428 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3429 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3430 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3431 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3432 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3433 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3434 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3435 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3436 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3437 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3440 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3441 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3442 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3444 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3445 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3446 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3447 if (sctx
->chip_class
== GFX9
)
3448 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3450 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3452 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3453 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3456 /* Framebuffer dimensions. */
3457 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3458 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3459 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3461 if (sctx
->screen
->dfsm_allowed
) {
3462 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3463 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3466 sctx
->framebuffer
.dirty_cbufs
= 0;
3467 sctx
->framebuffer
.dirty_zsbuf
= false;
3470 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3472 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3473 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3474 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3475 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3477 /* Smoothing (only possible with nr_samples == 1) uses the same
3478 * sample locations as the MSAA it simulates.
3480 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3481 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3483 /* On Polaris, the small primitive filter uses the sample locations
3484 * even when MSAA is off, so we need to make sure they're set to 0.
3486 * GFX10 uses sample locations unconditionally, so they always need
3489 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
||
3490 sctx
->chip_class
>= GFX10
) &&
3491 nr_samples
!= sctx
->sample_locs_num_samples
) {
3492 sctx
->sample_locs_num_samples
= nr_samples
;
3493 si_emit_sample_locations(cs
, nr_samples
);
3496 if (sctx
->family
>= CHIP_POLARIS10
) {
3497 unsigned small_prim_filter_cntl
=
3498 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3500 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3502 /* The alternative of setting sample locations to 0 would
3503 * require a DB flush to avoid Z errors, see
3504 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3506 if (has_msaa_sample_loc_bug
&&
3507 sctx
->framebuffer
.nr_samples
> 1 &&
3508 !rs
->multisample_enable
)
3509 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3511 radeon_opt_set_context_reg(sctx
,
3512 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3513 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3514 small_prim_filter_cntl
);
3517 /* The exclusion bits can be set to improve rasterization efficiency
3518 * if no sample lies on the pixel boundary (-8 sample offset).
3520 bool exclusion
= sctx
->chip_class
>= GFX7
&&
3521 (!rs
->multisample_enable
|| nr_samples
!= 16);
3522 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3523 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3524 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3525 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3528 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3530 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3531 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3533 if (!sctx
->screen
->has_out_of_order_rast
)
3536 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3539 colormask
&= blend
->cb_target_enabled_4bit
;
3544 /* Conservative: No logic op. */
3545 if (colormask
&& blend
->logicop_enable
)
3548 struct si_dsa_order_invariance dsa_order_invariant
= {
3549 .zs
= true, .pass_set
= true, .pass_last
= false
3552 if (sctx
->framebuffer
.state
.zsbuf
) {
3553 struct si_texture
*zstex
=
3554 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3555 bool has_stencil
= zstex
->surface
.has_stencil
;
3556 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3557 if (!dsa_order_invariant
.zs
)
3560 /* The set of PS invocations is always order invariant,
3561 * except when early Z/S tests are requested. */
3562 if (sctx
->ps_shader
.cso
&&
3563 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3564 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3565 !dsa_order_invariant
.pass_set
)
3568 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3569 !dsa_order_invariant
.pass_set
)
3576 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3579 /* Only commutative blending. */
3580 if (blendmask
& ~blend
->commutative_4bit
)
3583 if (!dsa_order_invariant
.pass_set
)
3587 if (colormask
& ~blendmask
) {
3588 if (!dsa_order_invariant
.pass_last
)
3595 static void si_emit_msaa_config(struct si_context
*sctx
)
3597 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3598 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3599 /* 33% faster rendering to linear color buffers */
3600 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3601 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3602 unsigned sc_mode_cntl_1
=
3603 S_028A4C_WALK_SIZE(dst_is_linear
) |
3604 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3605 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3606 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3607 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3609 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3610 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3611 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3612 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3613 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3614 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3615 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3616 S_028804_INCOHERENT_EQAA_READS(1) |
3617 S_028804_INTERPOLATE_COMP_Z(1) |
3618 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3619 unsigned coverage_samples
, color_samples
, z_samples
;
3620 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3622 /* S: Coverage samples (up to 16x):
3623 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3624 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3626 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3627 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3628 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3629 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3630 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3633 * F: Color samples (up to 8x, must be <= coverage samples):
3634 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3635 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3637 * Can be anything between coverage and color samples:
3638 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3639 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3640 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3641 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3642 * # All are currently set the same as coverage samples.
3644 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3645 * flag for undefined color samples. A shader-based resolve must handle unknowns
3646 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3647 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3648 * useful. The CB resolve always drops unknowns.
3650 * Sensible AA configurations:
3651 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3652 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3653 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3654 * EQAA 8s 8z 8f = 8x MSAA
3655 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3656 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3657 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3658 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3659 * EQAA 4s 4z 4f = 4x MSAA
3660 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3661 * EQAA 2s 2z 2f = 2x MSAA
3663 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3664 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3665 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3667 if (sctx
->framebuffer
.state
.zsbuf
) {
3668 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3669 z_samples
= MAX2(1, z_samples
);
3671 z_samples
= coverage_samples
;
3673 } else if (sctx
->smoothing_enabled
) {
3674 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3676 coverage_samples
= color_samples
= z_samples
= 1;
3679 /* Required by OpenGL line rasterization.
3681 * TODO: We should also enable perpendicular endcaps for AA lines,
3682 * but that requires implementing line stippling in the pixel
3683 * shader. SC can only do line stippling with axis-aligned
3686 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3687 unsigned sc_aa_config
= 0;
3689 if (coverage_samples
> 1) {
3690 /* distance from the pixel center, indexed by log2(nr_samples) */
3691 static unsigned max_dist
[] = {
3698 unsigned log_samples
= util_logbase2(coverage_samples
);
3699 unsigned log_z_samples
= util_logbase2(z_samples
);
3700 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3701 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3703 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3704 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3705 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3706 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3708 if (sctx
->framebuffer
.nr_samples
> 1) {
3709 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3710 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3711 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3712 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3713 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3714 } else if (sctx
->smoothing_enabled
) {
3715 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3719 unsigned initial_cdw
= cs
->current
.cdw
;
3721 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3722 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3723 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3725 /* R_028804_DB_EQAA */
3726 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3728 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3729 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3730 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3732 if (initial_cdw
!= cs
->current
.cdw
) {
3733 sctx
->context_roll
= true;
3735 /* GFX9: Flush DFSM when the AA mode changes. */
3736 if (sctx
->screen
->dfsm_allowed
) {
3737 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3738 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3743 void si_update_ps_iter_samples(struct si_context
*sctx
)
3745 if (sctx
->framebuffer
.nr_samples
> 1)
3746 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3747 if (sctx
->screen
->dpbb_allowed
)
3748 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3751 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3753 struct si_context
*sctx
= (struct si_context
*)ctx
;
3755 /* The hardware can only do sample shading with 2^n samples. */
3756 min_samples
= util_next_power_of_two(min_samples
);
3758 if (sctx
->ps_iter_samples
== min_samples
)
3761 sctx
->ps_iter_samples
= min_samples
;
3762 sctx
->do_update_shaders
= true;
3764 si_update_ps_iter_samples(sctx
);
3772 * Build the sampler view descriptor for a buffer texture.
3773 * @param state 256-bit descriptor; only the high 128 bits are filled in
3776 si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3777 enum pipe_format format
,
3778 unsigned offset
, unsigned size
,
3781 const struct util_format_description
*desc
;
3783 unsigned num_records
;
3785 desc
= util_format_description(format
);
3786 stride
= desc
->block
.bits
/ 8;
3788 num_records
= size
/ stride
;
3789 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3791 /* The NUM_RECORDS field has a different meaning depending on the chip,
3792 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3795 * - If STRIDE == 0, it's in byte units.
3796 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3799 * - For SMEM and STRIDE == 0, it's in byte units.
3800 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3801 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3802 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3803 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3804 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3805 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3806 * That way the same descriptor can be used by both SMEM and VMEM.
3809 * - For SMEM and STRIDE == 0, it's in byte units.
3810 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3811 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3812 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3814 if (screen
->info
.chip_class
== GFX9
&& HAVE_LLVM
< 0x0800)
3815 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3816 * from STRIDE to bytes. This works around it by setting
3817 * NUM_RECORDS to at least the size of one element, so that
3818 * the first element is readable when IDXEN == 0.
3820 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3821 else if (screen
->info
.chip_class
== GFX8
)
3822 num_records
*= stride
;
3825 state
[5] = S_008F04_STRIDE(stride
);
3826 state
[6] = num_records
;
3827 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3828 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3829 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3830 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3832 if (screen
->info
.chip_class
>= GFX10
) {
3833 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3835 /* OOB_SELECT chooses the out-of-bounds check:
3836 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3837 * - 1: index >= NUM_RECORDS
3838 * - 2: NUM_RECORDS == 0
3839 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3840 * else: swizzle_address >= NUM_RECORDS
3842 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3843 S_008F0C_OOB_SELECT(0) |
3844 S_008F0C_RESOURCE_LEVEL(1);
3847 unsigned num_format
, data_format
;
3849 first_non_void
= util_format_get_first_non_void_channel(format
);
3850 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3851 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3853 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) |
3854 S_008F0C_DATA_FORMAT(data_format
);
3858 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3860 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3862 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3863 /* For the pre-defined border color values (white, opaque
3864 * black, transparent black), the only thing that matters is
3865 * that the alpha channel winds up in the correct place
3866 * (because the RGB channels are all the same) so either of
3867 * these enumerations will work.
3869 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3870 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3872 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3873 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3874 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3875 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3877 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3878 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3879 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3880 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3881 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3888 * Build the sampler view descriptor for a texture.
3891 gfx10_make_texture_descriptor(struct si_screen
*screen
,
3892 struct si_texture
*tex
,
3894 enum pipe_texture_target target
,
3895 enum pipe_format pipe_format
,
3896 const unsigned char state_swizzle
[4],
3897 unsigned first_level
, unsigned last_level
,
3898 unsigned first_layer
, unsigned last_layer
,
3899 unsigned width
, unsigned height
, unsigned depth
,
3901 uint32_t *fmask_state
)
3903 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3904 const struct util_format_description
*desc
;
3905 unsigned img_format
;
3906 unsigned char swizzle
[4];
3910 desc
= util_format_description(pipe_format
);
3911 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3913 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3914 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3915 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3916 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3917 bool is_stencil
= false;
3919 switch (pipe_format
) {
3920 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3921 case PIPE_FORMAT_X32_S8X24_UINT
:
3922 case PIPE_FORMAT_X8Z24_UNORM
:
3923 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3926 case PIPE_FORMAT_X24S8_UINT
:
3928 * X24S8 is implemented as an 8_8_8_8 data format, to
3929 * fix texture gathers. This affects at least
3930 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3932 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3936 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3937 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3940 if (tex
->upgraded_depth
&& !is_stencil
) {
3941 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3942 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3945 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3949 (res
->target
== PIPE_TEXTURE_CUBE
||
3950 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3951 /* For the purpose of shader images, treat cube maps as 2D
3954 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3956 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3959 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3961 depth
= res
->array_size
;
3962 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3963 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3964 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3965 depth
= res
->array_size
;
3966 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3967 depth
= res
->array_size
/ 6;
3970 state
[1] = S_00A004_FORMAT(img_format
) |
3971 S_00A004_WIDTH_LO(width
- 1);
3972 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
3973 S_00A008_HEIGHT(height
- 1) |
3974 S_00A008_RESOURCE_LEVEL(1);
3975 state
[3] = S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3976 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3977 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3978 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3979 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ?
3981 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ?
3982 util_logbase2(res
->nr_samples
) :
3984 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) |
3985 S_00A00C_TYPE(type
);
3986 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3987 * to know the total number of layers.
3989 state
[4] = S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
)
3990 ? depth
- 1 : last_layer
) |
3991 S_00A010_BASE_ARRAY(first_layer
);
3992 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3993 S_00A014_MAX_MIP(res
->nr_samples
> 1 ?
3994 util_logbase2(res
->nr_samples
) :
3995 tex
->buffer
.b
.b
.last_level
) |
3996 S_00A014_PERF_MOD(4);
4000 if (tex
->dcc_offset
) {
4001 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
4002 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
4003 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4006 /* Initialize the sampler view for FMASK. */
4007 if (tex
->fmask_offset
) {
4010 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4012 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4013 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4015 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
4018 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
4021 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
4024 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
4027 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
4030 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
4033 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
4036 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
4039 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
4042 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
4045 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
4048 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
4051 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
4054 unreachable("invalid nr_samples");
4057 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4058 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) |
4059 S_00A004_FORMAT(format
) |
4060 S_00A004_WIDTH_LO(width
- 1);
4061 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) |
4062 S_00A008_HEIGHT(height
- 1) |
4063 S_00A008_RESOURCE_LEVEL(1);
4064 fmask_state
[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4065 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4066 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4067 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4068 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4069 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4070 fmask_state
[4] = S_00A010_DEPTH(last_layer
) |
4071 S_00A010_BASE_ARRAY(first_layer
);
4073 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
4079 * Build the sampler view descriptor for a texture (SI-GFX9).
4082 si_make_texture_descriptor(struct si_screen
*screen
,
4083 struct si_texture
*tex
,
4085 enum pipe_texture_target target
,
4086 enum pipe_format pipe_format
,
4087 const unsigned char state_swizzle
[4],
4088 unsigned first_level
, unsigned last_level
,
4089 unsigned first_layer
, unsigned last_layer
,
4090 unsigned width
, unsigned height
, unsigned depth
,
4092 uint32_t *fmask_state
)
4094 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
4095 const struct util_format_description
*desc
;
4096 unsigned char swizzle
[4];
4098 unsigned num_format
, data_format
, type
, num_samples
;
4101 desc
= util_format_description(pipe_format
);
4103 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
4104 MAX2(1, res
->nr_samples
) :
4105 MAX2(1, res
->nr_storage_samples
);
4107 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
4108 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
4109 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
4110 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
4112 switch (pipe_format
) {
4113 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4114 case PIPE_FORMAT_X32_S8X24_UINT
:
4115 case PIPE_FORMAT_X8Z24_UNORM
:
4116 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4118 case PIPE_FORMAT_X24S8_UINT
:
4120 * X24S8 is implemented as an 8_8_8_8 data format, to
4121 * fix texture gathers. This affects at least
4122 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
4124 if (screen
->info
.chip_class
<= GFX8
)
4125 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
4127 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
4130 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
4133 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
4136 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
4138 switch (pipe_format
) {
4139 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4140 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4143 if (first_non_void
< 0) {
4144 if (util_format_is_compressed(pipe_format
)) {
4145 switch (pipe_format
) {
4146 case PIPE_FORMAT_DXT1_SRGB
:
4147 case PIPE_FORMAT_DXT1_SRGBA
:
4148 case PIPE_FORMAT_DXT3_SRGBA
:
4149 case PIPE_FORMAT_DXT5_SRGBA
:
4150 case PIPE_FORMAT_BPTC_SRGBA
:
4151 case PIPE_FORMAT_ETC2_SRGB8
:
4152 case PIPE_FORMAT_ETC2_SRGB8A1
:
4153 case PIPE_FORMAT_ETC2_SRGBA8
:
4154 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4156 case PIPE_FORMAT_RGTC1_SNORM
:
4157 case PIPE_FORMAT_LATC1_SNORM
:
4158 case PIPE_FORMAT_RGTC2_SNORM
:
4159 case PIPE_FORMAT_LATC2_SNORM
:
4160 case PIPE_FORMAT_ETC2_R11_SNORM
:
4161 case PIPE_FORMAT_ETC2_RG11_SNORM
:
4162 /* implies float, so use SNORM/UNORM to determine
4163 whether data is signed or not */
4164 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
4165 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4168 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4171 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
4172 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4174 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4176 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
4177 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
4179 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4181 switch (desc
->channel
[first_non_void
].type
) {
4182 case UTIL_FORMAT_TYPE_FLOAT
:
4183 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
4185 case UTIL_FORMAT_TYPE_SIGNED
:
4186 if (desc
->channel
[first_non_void
].normalized
)
4187 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
4188 else if (desc
->channel
[first_non_void
].pure_integer
)
4189 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
4191 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
4193 case UTIL_FORMAT_TYPE_UNSIGNED
:
4194 if (desc
->channel
[first_non_void
].normalized
)
4195 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
4196 else if (desc
->channel
[first_non_void
].pure_integer
)
4197 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4199 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
4204 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
4205 if (data_format
== ~0) {
4209 /* S8 with Z32 HTILE needs a special format. */
4210 if (screen
->info
.chip_class
== GFX9
&&
4211 pipe_format
== PIPE_FORMAT_S8_UINT
&&
4212 tex
->tc_compatible_htile
)
4213 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4216 (res
->target
== PIPE_TEXTURE_CUBE
||
4217 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4218 (screen
->info
.chip_class
<= GFX8
&&
4219 res
->target
== PIPE_TEXTURE_3D
))) {
4220 /* For the purpose of shader images, treat cube maps and 3D
4221 * textures as 2D arrays. For 3D textures, the address
4222 * calculations for mipmaps are different, so we rely on the
4223 * caller to effectively disable mipmaps.
4225 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4227 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4229 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4232 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4234 depth
= res
->array_size
;
4235 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
4236 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4237 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4238 depth
= res
->array_size
;
4239 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4240 depth
= res
->array_size
/ 6;
4243 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
4244 S_008F14_NUM_FORMAT(num_format
));
4245 state
[2] = (S_008F18_WIDTH(width
- 1) |
4246 S_008F18_HEIGHT(height
- 1) |
4247 S_008F18_PERF_MOD(4));
4248 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4249 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4250 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4251 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4252 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4253 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
4254 util_logbase2(num_samples
) :
4256 S_008F1C_TYPE(type
));
4258 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4262 if (screen
->info
.chip_class
== GFX9
) {
4263 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4265 /* Depth is the the last accessible layer on Gfx9.
4266 * The hw doesn't need to know the total number of layers.
4268 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4269 state
[4] |= S_008F20_DEPTH(depth
- 1);
4271 state
[4] |= S_008F20_DEPTH(last_layer
);
4273 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4274 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
4275 util_logbase2(num_samples
) :
4276 tex
->buffer
.b
.b
.last_level
);
4278 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4279 state
[4] |= S_008F20_DEPTH(depth
- 1);
4280 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4283 if (tex
->dcc_offset
) {
4284 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4286 /* The last dword is unused by hw. The shader uses it to clear
4287 * bits in the first dword of sampler state.
4289 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4290 if (first_level
== last_level
)
4291 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4293 state
[7] = 0xffffffff;
4297 /* Initialize the sampler view for FMASK. */
4298 if (tex
->fmask_offset
) {
4299 uint32_t data_format
, num_format
;
4301 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
4303 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4304 if (screen
->info
.chip_class
== GFX9
) {
4305 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4306 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4308 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4311 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4314 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4317 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4320 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4323 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4326 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4329 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4332 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4335 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4338 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4341 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4344 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4347 unreachable("invalid nr_samples");
4350 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4352 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4355 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4358 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4361 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4364 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4367 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4370 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4373 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4376 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4379 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4382 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4385 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4388 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4391 unreachable("invalid nr_samples");
4393 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4397 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4398 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
4399 S_008F14_DATA_FORMAT(data_format
) |
4400 S_008F14_NUM_FORMAT(num_format
);
4401 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
4402 S_008F18_HEIGHT(height
- 1);
4403 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
4404 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4405 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
4406 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4407 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4409 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4413 if (screen
->info
.chip_class
== GFX9
) {
4414 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4415 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
4416 S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4417 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4418 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4420 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4421 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4422 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4423 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4429 * Create a sampler view.
4431 * @param ctx context
4432 * @param texture texture
4433 * @param state sampler view template
4434 * @param width0 width0 override (for compressed textures as int)
4435 * @param height0 height0 override (for compressed textures as int)
4436 * @param force_level set the base address to the level (for compressed textures)
4438 struct pipe_sampler_view
*
4439 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4440 struct pipe_resource
*texture
,
4441 const struct pipe_sampler_view
*state
,
4442 unsigned width0
, unsigned height0
,
4443 unsigned force_level
)
4445 struct si_context
*sctx
= (struct si_context
*)ctx
;
4446 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4447 struct si_texture
*tex
= (struct si_texture
*)texture
;
4448 unsigned base_level
, first_level
, last_level
;
4449 unsigned char state_swizzle
[4];
4450 unsigned height
, depth
, width
;
4451 unsigned last_layer
= state
->u
.tex
.last_layer
;
4452 enum pipe_format pipe_format
;
4453 const struct legacy_surf_level
*surflevel
;
4458 /* initialize base object */
4459 view
->base
= *state
;
4460 view
->base
.texture
= NULL
;
4461 view
->base
.reference
.count
= 1;
4462 view
->base
.context
= ctx
;
4465 pipe_resource_reference(&view
->base
.texture
, texture
);
4467 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4468 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4469 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4470 state
->format
== PIPE_FORMAT_S8_UINT
)
4471 view
->is_stencil_sampler
= true;
4473 /* Buffer resource. */
4474 if (texture
->target
== PIPE_BUFFER
) {
4475 si_make_buffer_descriptor(sctx
->screen
,
4476 si_resource(texture
),
4478 state
->u
.buf
.offset
,
4484 state_swizzle
[0] = state
->swizzle_r
;
4485 state_swizzle
[1] = state
->swizzle_g
;
4486 state_swizzle
[2] = state
->swizzle_b
;
4487 state_swizzle
[3] = state
->swizzle_a
;
4490 first_level
= state
->u
.tex
.first_level
;
4491 last_level
= state
->u
.tex
.last_level
;
4494 depth
= texture
->depth0
;
4496 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4497 assert(force_level
== first_level
&&
4498 force_level
== last_level
);
4499 base_level
= force_level
;
4502 width
= u_minify(width
, force_level
);
4503 height
= u_minify(height
, force_level
);
4504 depth
= u_minify(depth
, force_level
);
4507 /* This is not needed if state trackers set last_layer correctly. */
4508 if (state
->target
== PIPE_TEXTURE_1D
||
4509 state
->target
== PIPE_TEXTURE_2D
||
4510 state
->target
== PIPE_TEXTURE_RECT
||
4511 state
->target
== PIPE_TEXTURE_CUBE
)
4512 last_layer
= state
->u
.tex
.first_layer
;
4514 /* Texturing with separate depth and stencil. */
4515 pipe_format
= state
->format
;
4517 /* Depth/stencil texturing sometimes needs separate texture. */
4518 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4519 if (!tex
->flushed_depth_texture
&&
4520 !si_init_flushed_depth_texture(ctx
, texture
)) {
4521 pipe_resource_reference(&view
->base
.texture
, NULL
);
4526 assert(tex
->flushed_depth_texture
);
4528 /* Override format for the case where the flushed texture
4529 * contains only Z or only S.
4531 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4532 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4534 tex
= tex
->flushed_depth_texture
;
4537 surflevel
= tex
->surface
.u
.legacy
.level
;
4539 if (tex
->db_compatible
) {
4540 if (!view
->is_stencil_sampler
)
4541 pipe_format
= tex
->db_render_format
;
4543 switch (pipe_format
) {
4544 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4545 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4547 case PIPE_FORMAT_X8Z24_UNORM
:
4548 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4549 /* Z24 is always stored like this for DB
4552 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4554 case PIPE_FORMAT_X24S8_UINT
:
4555 case PIPE_FORMAT_S8X24_UINT
:
4556 case PIPE_FORMAT_X32_S8X24_UINT
:
4557 pipe_format
= PIPE_FORMAT_S8_UINT
;
4558 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4564 view
->dcc_incompatible
=
4565 vi_dcc_formats_are_incompatible(texture
,
4566 state
->u
.tex
.first_level
,
4569 sctx
->screen
->make_texture_descriptor(sctx
->screen
, tex
, true,
4570 state
->target
, pipe_format
, state_swizzle
,
4571 first_level
, last_level
,
4572 state
->u
.tex
.first_layer
, last_layer
,
4573 width
, height
, depth
,
4574 view
->state
, view
->fmask_state
);
4576 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4577 view
->is_integer
= false;
4579 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4580 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4583 /* Whether the number format is {U,S}{SCALED,INT} */
4585 (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4586 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4587 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4591 view
->base_level_info
= &surflevel
[base_level
];
4592 view
->base_level
= base_level
;
4593 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4597 static struct pipe_sampler_view
*
4598 si_create_sampler_view(struct pipe_context
*ctx
,
4599 struct pipe_resource
*texture
,
4600 const struct pipe_sampler_view
*state
)
4602 return si_create_sampler_view_custom(ctx
, texture
, state
,
4603 texture
? texture
->width0
: 0,
4604 texture
? texture
->height0
: 0, 0);
4607 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4608 struct pipe_sampler_view
*state
)
4610 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4612 pipe_resource_reference(&state
->texture
, NULL
);
4616 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4618 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4619 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4621 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4622 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4625 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4626 const struct pipe_sampler_state
*state
,
4627 const union pipe_color_union
*color
,
4630 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4631 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4633 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4634 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4635 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4636 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4638 #define simple_border_types(elt) \
4640 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4641 color->elt[2] == 0 && color->elt[3] == 0) \
4642 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4643 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4644 color->elt[2] == 0 && color->elt[3] == 1) \
4645 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4646 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4647 color->elt[2] == 1 && color->elt[3] == 1) \
4648 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4652 simple_border_types(ui
);
4654 simple_border_types(f
);
4656 #undef simple_border_types
4660 /* Check if the border has been uploaded already. */
4661 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4662 if (memcmp(&sctx
->border_color_table
[i
], color
,
4663 sizeof(*color
)) == 0)
4666 if (i
>= SI_MAX_BORDER_COLORS
) {
4667 /* Getting 4096 unique border colors is very unlikely. */
4668 fprintf(stderr
, "radeonsi: The border color table is full. "
4669 "Any new border colors will be just black. "
4670 "Please file a bug.\n");
4671 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4674 if (i
== sctx
->border_color_count
) {
4675 /* Upload a new border color. */
4676 memcpy(&sctx
->border_color_table
[i
], color
,
4678 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4679 color
, sizeof(*color
));
4680 sctx
->border_color_count
++;
4683 return S_008F3C_BORDER_COLOR_PTR(i
) |
4684 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4687 static inline int S_FIXED(float value
, unsigned frac_bits
)
4689 return value
* (1 << frac_bits
);
4692 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4694 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4695 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4696 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4698 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4699 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4702 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4715 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4716 const struct pipe_sampler_state
*state
)
4718 struct si_context
*sctx
= (struct si_context
*)ctx
;
4719 struct si_screen
*sscreen
= sctx
->screen
;
4720 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4721 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4722 : state
->max_anisotropy
;
4723 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4724 union pipe_color_union clamped_border_color
;
4731 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4733 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4734 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4735 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4736 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4737 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4738 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4739 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4740 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4741 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4742 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4743 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4744 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4745 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4746 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4747 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4748 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4749 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4750 S_008F38_MIP_POINT_PRECLAMP(0));
4751 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4753 if (sscreen
->info
.chip_class
>= GFX10
) {
4754 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4756 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4757 S_008F38_FILTER_PREC_FIX(1) |
4758 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4761 /* Create sampler resource for integer textures. */
4762 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4763 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4765 /* Create sampler resource for upgraded depth textures. */
4766 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4768 for (unsigned i
= 0; i
< 4; ++i
) {
4769 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4770 * when the border color is 1.0. */
4771 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4774 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4775 if (sscreen
->info
.chip_class
<= GFX9
)
4776 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4778 rstate
->upgraded_depth_val
[3] =
4779 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4785 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4787 struct si_context
*sctx
= (struct si_context
*)ctx
;
4789 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4792 sctx
->sample_mask
= sample_mask
;
4793 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4796 static void si_emit_sample_mask(struct si_context
*sctx
)
4798 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4799 unsigned mask
= sctx
->sample_mask
;
4801 /* Needed for line and polygon smoothing as well as for the Polaris
4802 * small primitive filter. We expect the state tracker to take care of
4805 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4806 (mask
& 1 && sctx
->blitter
->running
));
4808 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4809 radeon_emit(cs
, mask
| (mask
<< 16));
4810 radeon_emit(cs
, mask
| (mask
<< 16));
4813 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4816 struct si_sampler_state
*s
= state
;
4818 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4825 * Vertex elements & buffers
4828 struct si_fast_udiv_info32
4829 si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4831 struct util_fast_udiv_info info
=
4832 util_compute_fast_udiv_info(D
, num_bits
, 32);
4834 struct si_fast_udiv_info32 result
= {
4843 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4845 const struct pipe_vertex_element
*elements
)
4847 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4848 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4849 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4850 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4851 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4852 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4853 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4854 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4855 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4858 assert(count
<= SI_MAX_ATTRIBS
);
4863 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4865 for (i
= 0; i
< count
; ++i
) {
4866 const struct util_format_description
*desc
;
4867 const struct util_format_channel_description
*channel
;
4869 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4871 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4876 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4877 if (instance_divisor
) {
4878 v
->uses_instance_divisors
= true;
4880 if (instance_divisor
== 1) {
4881 v
->instance_divisor_is_one
|= 1u << i
;
4883 v
->instance_divisor_is_fetched
|= 1u << i
;
4884 divisor_factors
[i
] =
4885 si_compute_fast_udiv_info32(instance_divisor
, 32);
4889 if (!used
[vbo_index
]) {
4890 v
->first_vb_use_mask
|= 1 << i
;
4891 used
[vbo_index
] = true;
4894 desc
= util_format_description(elements
[i
].src_format
);
4895 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4896 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4898 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4899 v
->src_offset
[i
] = elements
[i
].src_offset
;
4900 v
->vertex_buffer_index
[i
] = vbo_index
;
4902 bool always_fix
= false;
4903 union si_vs_fix_fetch fix_fetch
;
4904 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4907 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4910 switch (channel
->type
) {
4911 case UTIL_FORMAT_TYPE_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4912 case UTIL_FORMAT_TYPE_FIXED
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
; break;
4913 case UTIL_FORMAT_TYPE_SIGNED
: {
4914 if (channel
->pure_integer
)
4915 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4916 else if (channel
->normalized
)
4917 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4919 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4922 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4923 if (channel
->pure_integer
)
4924 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4925 else if (channel
->normalized
)
4926 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4928 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4931 default: unreachable("bad format type");
4934 switch (elements
[i
].src_format
) {
4935 case PIPE_FORMAT_R11G11B10_FLOAT
: fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
; break;
4936 default: unreachable("bad other format");
4940 if (desc
->channel
[0].size
== 10) {
4941 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4942 log_hw_load_size
= 2;
4944 /* The hardware always treats the 2-bit alpha channel as
4945 * unsigned, so a shader workaround is needed. The affected
4946 * chips are GFX8 and older except Stoney (GFX8.1).
4948 always_fix
= sscreen
->info
.chip_class
<= GFX8
&&
4949 sscreen
->info
.family
!= CHIP_STONEY
&&
4950 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4951 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4952 fix_fetch
.u
.log_size
= 3; /* special encoding */
4953 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4954 log_hw_load_size
= 2;
4956 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4957 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4960 * - doubles (multiple loads + truncate to float)
4961 * - 32-bit requiring a conversion
4964 (fix_fetch
.u
.log_size
== 3) ||
4965 (fix_fetch
.u
.log_size
== 2 &&
4966 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4967 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4968 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4970 /* Also fixup 8_8_8 and 16_16_16. */
4971 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4973 log_hw_load_size
= fix_fetch
.u
.log_size
;
4977 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4978 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4979 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4980 fix_fetch
.u
.reverse
= 1;
4983 /* Force the workaround for unaligned access here already if the
4984 * offset relative to the vertex buffer base is unaligned.
4986 * There is a theoretical case in which this is too conservative:
4987 * if the vertex buffer's offset is also unaligned in just the
4988 * right way, we end up with an aligned address after all.
4989 * However, this case should be extremely rare in practice (it
4990 * won't happen in well-behaved applications), and taking it
4991 * into account would complicate the fast path (where everything
4992 * is nicely aligned).
4994 bool check_alignment
=
4995 log_hw_load_size
>= 1 &&
4996 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
== GFX10
);
4997 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4999 if (check_alignment
&&
5000 (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
5003 if (always_fix
|| check_alignment
|| opencode
)
5004 v
->fix_fetch
[i
] = fix_fetch
.bits
;
5007 v
->fix_fetch_opencode
|= 1 << i
;
5008 if (opencode
|| always_fix
)
5009 v
->fix_fetch_always
|= 1 << i
;
5011 if (check_alignment
&& !opencode
) {
5012 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
5014 v
->fix_fetch_unaligned
|= 1 << i
;
5015 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
5016 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
5019 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
5020 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
5021 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
5022 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
5024 if (sscreen
->info
.chip_class
>= GFX10
) {
5025 const struct gfx10_format
*fmt
=
5026 &gfx10_format_table
[elements
[i
].src_format
];
5027 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
5028 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) |
5029 S_008F0C_RESOURCE_LEVEL(1);
5031 unsigned data_format
, num_format
;
5032 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
5033 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
5034 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) |
5035 S_008F0C_DATA_FORMAT(data_format
);
5039 if (v
->instance_divisor_is_fetched
) {
5040 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
5042 v
->instance_divisor_factor_buffer
=
5043 (struct si_resource
*)
5044 pipe_buffer_create(&sscreen
->b
, 0, PIPE_USAGE_DEFAULT
,
5045 num_divisors
* sizeof(divisor_factors
[0]));
5046 if (!v
->instance_divisor_factor_buffer
) {
5050 void *map
= sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
,
5051 NULL
, PIPE_TRANSFER_WRITE
);
5052 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
5057 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
5059 struct si_context
*sctx
= (struct si_context
*)ctx
;
5060 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
5061 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5063 sctx
->vertex_elements
= v
;
5064 sctx
->vertex_buffers_dirty
= true;
5068 old
->count
!= v
->count
||
5069 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
5070 /* we don't check which divisors changed */
5071 v
->uses_instance_divisors
||
5072 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) & sctx
->vertex_buffer_unaligned
||
5073 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
5074 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
5075 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
5076 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
5077 * functions of fix_fetch and the src_offset alignment.
5078 * If they change and fix_fetch doesn't, it must be due to different
5079 * src_offset alignment, which is reflected in fix_fetch_opencode. */
5080 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
5081 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
5082 sctx
->do_update_shaders
= true;
5084 if (v
&& v
->instance_divisor_is_fetched
) {
5085 struct pipe_constant_buffer cb
;
5087 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
5088 cb
.user_buffer
= NULL
;
5089 cb
.buffer_offset
= 0;
5090 cb
.buffer_size
= 0xffffffff;
5091 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
5095 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
5097 struct si_context
*sctx
= (struct si_context
*)ctx
;
5098 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
5100 if (sctx
->vertex_elements
== state
)
5101 sctx
->vertex_elements
= NULL
;
5102 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
5106 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
5107 unsigned start_slot
, unsigned count
,
5108 const struct pipe_vertex_buffer
*buffers
)
5110 struct si_context
*sctx
= (struct si_context
*)ctx
;
5111 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
5112 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
5113 uint32_t unaligned
= orig_unaligned
;
5116 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
5119 for (i
= 0; i
< count
; i
++) {
5120 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
5121 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
5122 struct pipe_resource
*buf
= src
->buffer
.resource
;
5124 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
5125 dsti
->buffer_offset
= src
->buffer_offset
;
5126 dsti
->stride
= src
->stride
;
5127 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
5128 unaligned
|= 1 << (start_slot
+ i
);
5130 unaligned
&= ~(1 << (start_slot
+ i
));
5132 si_context_add_resource_size(sctx
, buf
);
5134 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
5137 for (i
= 0; i
< count
; i
++) {
5138 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
5140 unaligned
&= ~u_bit_consecutive(start_slot
, count
);
5142 sctx
->vertex_buffers_dirty
= true;
5143 sctx
->vertex_buffer_unaligned
= unaligned
;
5145 /* Check whether alignment may have changed in a way that requires
5146 * shader changes. This check is conservative: a vertex buffer can only
5147 * trigger a shader change if the misalignment amount changes (e.g.
5148 * from byte-aligned to short-aligned), but we only keep track of
5149 * whether buffers are at least dword-aligned, since that should always
5150 * be the case in well-behaved applications anyway.
5152 if (sctx
->vertex_elements
&&
5153 (sctx
->vertex_elements
->vb_alignment_check_mask
&
5154 (unaligned
| orig_unaligned
) & u_bit_consecutive(start_slot
, count
)))
5155 sctx
->do_update_shaders
= true;
5162 static void si_set_tess_state(struct pipe_context
*ctx
,
5163 const float default_outer_level
[4],
5164 const float default_inner_level
[2])
5166 struct si_context
*sctx
= (struct si_context
*)ctx
;
5167 struct pipe_constant_buffer cb
;
5170 memcpy(array
, default_outer_level
, sizeof(float) * 4);
5171 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
5174 cb
.user_buffer
= NULL
;
5175 cb
.buffer_size
= sizeof(array
);
5177 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
,
5178 (void*)array
, sizeof(array
),
5181 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
5182 pipe_resource_reference(&cb
.buffer
, NULL
);
5185 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
5187 struct si_context
*sctx
= (struct si_context
*)ctx
;
5189 si_update_fb_dirtiness_after_rendering(sctx
);
5191 /* Multisample surfaces are flushed in si_decompress_textures. */
5192 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
5193 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
5194 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
5195 sctx
->framebuffer
.all_DCC_pipe_aligned
);
5199 /* This only ensures coherency for shader image/buffer stores. */
5200 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
5202 struct si_context
*sctx
= (struct si_context
*)ctx
;
5204 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
5207 /* Subsequent commands must wait for all shader invocations to
5209 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
5210 SI_CONTEXT_CS_PARTIAL_FLUSH
;
5212 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
5213 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
|
5214 SI_CONTEXT_INV_VCACHE
;
5216 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
5217 PIPE_BARRIER_SHADER_BUFFER
|
5218 PIPE_BARRIER_TEXTURE
|
5219 PIPE_BARRIER_IMAGE
|
5220 PIPE_BARRIER_STREAMOUT_BUFFER
|
5221 PIPE_BARRIER_GLOBAL_BUFFER
)) {
5222 /* As far as I can tell, L1 contents are written back to L2
5223 * automatically at end of shader, but the contents of other
5224 * L1 caches might still be stale. */
5225 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
5228 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
5229 /* Indices are read through TC L2 since GFX8.
5232 if (sctx
->screen
->info
.chip_class
<= GFX7
)
5233 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5236 /* MSAA color, any depth and any stencil are flushed in
5237 * si_decompress_textures when needed.
5239 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
5240 sctx
->framebuffer
.uncompressed_cb_mask
) {
5241 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
5243 if (sctx
->chip_class
<= GFX8
)
5244 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5247 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
5248 if (sctx
->screen
->info
.chip_class
<= GFX8
&&
5249 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
5250 sctx
->flags
|= SI_CONTEXT_WB_L2
;
5253 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
5255 struct pipe_blend_state blend
;
5257 memset(&blend
, 0, sizeof(blend
));
5258 blend
.independent_blend_enable
= true;
5259 blend
.rt
[0].colormask
= 0xf;
5260 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
5263 static void si_init_config(struct si_context
*sctx
);
5265 void si_init_state_compute_functions(struct si_context
*sctx
)
5267 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5268 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5269 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5270 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5271 sctx
->b
.memory_barrier
= si_memory_barrier
;
5274 void si_init_state_functions(struct si_context
*sctx
)
5276 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5277 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5278 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5279 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5280 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5281 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5282 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5283 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5284 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5285 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5286 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5288 sctx
->b
.create_blend_state
= si_create_blend_state
;
5289 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5290 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5291 sctx
->b
.set_blend_color
= si_set_blend_color
;
5293 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5294 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5295 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5297 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5298 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5299 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5301 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5302 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5303 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5304 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5305 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5307 sctx
->b
.set_clip_state
= si_set_clip_state
;
5308 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5310 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5312 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5314 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5315 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5316 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5317 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5319 sctx
->b
.texture_barrier
= si_texture_barrier
;
5320 sctx
->b
.set_min_samples
= si_set_min_samples
;
5321 sctx
->b
.set_tess_state
= si_set_tess_state
;
5323 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5325 si_init_config(sctx
);
5328 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5330 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5332 if (sscreen
->info
.chip_class
>= GFX10
) {
5333 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5335 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5339 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
5340 struct si_pm4_state
*pm4
, unsigned value
)
5342 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
:
5343 R_00802C_GRBM_GFX_INDEX
;
5344 si_pm4_set_reg(pm4
, reg
, value
);
5347 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
5348 struct si_pm4_state
*pm4
, unsigned se
)
5350 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5351 si_set_grbm_gfx_index(sctx
, pm4
,
5352 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
5353 S_030800_SE_INDEX(se
)) |
5354 S_030800_SH_BROADCAST_WRITES(1) |
5355 S_030800_INSTANCE_BROADCAST_WRITES(1));
5359 si_write_harvested_raster_configs(struct si_context
*sctx
,
5360 struct si_pm4_state
*pm4
,
5361 unsigned raster_config
,
5362 unsigned raster_config_1
)
5364 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5365 unsigned raster_config_se
[4];
5368 ac_get_harvested_configs(&sctx
->screen
->info
,
5373 for (se
= 0; se
< num_se
; se
++) {
5374 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5375 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5377 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5379 if (sctx
->chip_class
>= GFX7
) {
5380 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5384 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5386 struct si_screen
*sscreen
= sctx
->screen
;
5387 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5388 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5389 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5390 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5392 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5393 /* Always use the default config when all backends are enabled
5394 * (or when we failed to determine the enabled backends).
5396 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
5398 if (sctx
->chip_class
>= GFX7
)
5399 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
5402 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5406 static void si_init_config(struct si_context
*sctx
)
5408 struct si_screen
*sscreen
= sctx
->screen
;
5409 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5410 bool has_clear_state
= sscreen
->has_clear_state
;
5411 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5416 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5417 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5418 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5419 si_pm4_cmd_end(pm4
, false);
5421 if (has_clear_state
) {
5422 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5423 si_pm4_cmd_add(pm4
, 0);
5424 si_pm4_cmd_end(pm4
, false);
5427 if (sctx
->chip_class
<= GFX8
)
5428 si_set_raster_config(sctx
, pm4
);
5430 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5431 if (!has_clear_state
)
5432 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5434 /* FIXME calculate these values somehow ??? */
5435 if (sctx
->chip_class
<= GFX8
) {
5436 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5437 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5440 if (!has_clear_state
) {
5441 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5442 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5443 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5446 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5447 if (!has_clear_state
)
5448 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5449 if (sctx
->chip_class
< GFX7
)
5450 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
5451 S_008A14_CLIP_VTX_REORDER_ENA(1));
5453 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5454 * I don't know why. Deduced by trial and error.
5456 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5457 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5458 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5459 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5460 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5461 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5462 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5463 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5464 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5467 if (!has_clear_state
) {
5468 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5469 S_028230_ER_TRI(0xA) |
5470 S_028230_ER_POINT(0xA) |
5471 S_028230_ER_RECT(0xA) |
5472 /* Required by DX10_DIAMOND_TEST_ENA: */
5473 S_028230_ER_LINE_LR(0x1A) |
5474 S_028230_ER_LINE_RL(0x26) |
5475 S_028230_ER_LINE_TB(0xA) |
5476 S_028230_ER_LINE_BT(0xA));
5477 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5478 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5479 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5480 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5481 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5484 if (sctx
->chip_class
>= GFX10
) {
5485 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5486 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5487 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5488 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5489 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5490 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5491 } else if (sctx
->chip_class
== GFX9
) {
5492 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5493 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5494 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5496 /* These registers, when written, also overwrite the CLEAR_STATE
5497 * context, so we can't rely on CLEAR_STATE setting them.
5498 * It would be an issue if there was another UMD changing them.
5500 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5501 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5502 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5505 if (sctx
->chip_class
>= GFX7
) {
5506 if (sctx
->chip_class
>= GFX10
) {
5507 /* Logical CUs 16 - 31 */
5508 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
,
5509 S_00B404_CU_EN(0xffff));
5510 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
,
5511 S_00B104_CU_EN(0xffff));
5512 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
,
5513 S_00B004_CU_EN(0xffff));
5516 if (sctx
->chip_class
>= GFX9
) {
5517 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5518 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5520 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5521 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5522 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5523 S_00B41C_WAVE_LIMIT(0x3F));
5524 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5525 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5527 /* If this is 0, Bonaire can hang even if GS isn't being used.
5528 * Other chips are unaffected. These are suboptimal values,
5529 * but we don't use on-chip GS.
5531 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5532 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5533 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5536 /* Compute LATE_ALLOC_VS.LIMIT. */
5537 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5538 unsigned late_alloc_limit
; /* The limit is per SH. */
5540 if (sctx
->family
== CHIP_KABINI
) {
5541 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5542 } else if (num_cu_per_sh
<= 4) {
5543 /* Too few available compute units per SH. Disallowing
5544 * VS to run on one CU could hurt us more than late VS
5545 * allocation would help.
5547 * 2 is the highest safe number that allows us to keep
5550 late_alloc_limit
= 2;
5552 /* This is a good initial value, allowing 1 late_alloc
5553 * wave per SIMD on num_cu - 2.
5555 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5558 unsigned cu_mask_vs
= 0xffff;
5559 unsigned cu_mask_gs
= 0xffff;
5561 if (late_alloc_limit
> 2) {
5562 if (sctx
->chip_class
>= GFX10
) {
5563 /* CU2 & CU3 disabled because of the dual CU design */
5564 cu_mask_vs
= 0xfff3;
5565 cu_mask_gs
= 0xfff3; /* NGG only */
5567 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5571 /* VS can't execute on one CU if the limit is > 2. */
5572 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5573 S_00B118_CU_EN(cu_mask_vs
) |
5574 S_00B118_WAVE_LIMIT(0x3F));
5575 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5576 S_00B11C_LIMIT(late_alloc_limit
));
5578 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5579 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5581 if (sctx
->chip_class
>= GFX10
) {
5582 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
5583 S_00B204_CU_EN(0xffff) |
5584 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_limit
));
5587 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5588 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5591 if (sctx
->chip_class
>= GFX10
) {
5592 /* Break up a pixel wave if it contains deallocs for more than
5593 * half the parameter cache.
5595 * To avoid a deadlock where pixel waves aren't launched
5596 * because they're waiting for more pixels while the frontend
5597 * is stuck waiting for PC space, the maximum allowed value is
5598 * the size of the PC minus the largest possible allocation for
5599 * a single primitive shader subgroup.
5601 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
,
5602 S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5603 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5604 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5605 sscreen
->info
.pa_sc_tile_steering_override
);
5607 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5608 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5609 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5610 S_02807C_HTILE_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5611 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5612 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5613 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5614 S_02807C_HTILE_RD_POLICY(V_02807C_CACHE_NOA_RD
));
5616 si_pm4_set_reg(pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5617 S_028410_CMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5618 S_028410_FMASK_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5619 S_028410_DCC_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5620 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5621 S_028410_CMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5622 S_028410_FMASK_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5623 S_028410_DCC_RD_POLICY(V_028410_CACHE_NOA_RD
) |
5624 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5625 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5627 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5628 S_00B0C0_SOFT_GROUPING_EN(1) |
5629 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5630 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5634 if (sctx
->chip_class
>= GFX8
) {
5635 unsigned vgt_tess_distribution
;
5637 vgt_tess_distribution
=
5638 S_028B50_ACCUM_ISOLINE(32) |
5639 S_028B50_ACCUM_TRI(11) |
5640 S_028B50_ACCUM_QUAD(11) |
5641 S_028B50_DONUT_SPLIT(16);
5643 /* Testing with Unigine Heaven extreme tesselation yielded best results
5644 * with TRAP_SPLIT = 3.
5646 if (sctx
->family
== CHIP_FIJI
||
5647 sctx
->family
>= CHIP_POLARIS10
)
5648 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5650 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5651 } else if (!has_clear_state
) {
5652 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5653 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5656 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5657 if (sctx
->chip_class
>= GFX7
) {
5658 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5659 S_028084_ADDRESS(border_color_va
>> 40));
5661 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5662 RADEON_PRIO_BORDER_COLORS
);
5664 if (sctx
->chip_class
>= GFX9
) {
5665 unsigned num_se
= sscreen
->info
.max_se
;
5666 unsigned pc_lines
= 0;
5667 unsigned max_alloc_count
= 0;
5669 switch (sctx
->family
) {
5688 if (sctx
->chip_class
>= GFX10
) {
5689 max_alloc_count
= pc_lines
/ 3;
5691 max_alloc_count
= MIN2(128, pc_lines
/ (4 * num_se
));
5694 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5695 S_028C48_MAX_ALLOC_COUNT(max_alloc_count
) |
5696 S_028C48_MAX_PRIM_PER_BATCH(1023));
5697 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5698 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5699 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5702 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5703 sctx
->init_config
= pm4
;