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c151a980e01cc7b29286ddf67d45eac09b812441
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x)
79 {
80 return x <= 0 ? 0 :
81 x >= 4096 ? 0xffff : x * 16;
82 }
83
84 /*
85 * Inferred framebuffer and blender state.
86 *
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
89 */
90 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
91 {
92 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
93 struct si_state_blend *blend = sctx->queued.named.blend;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
97 unsigned i;
98
99 if (blend)
100 cb_target_mask &= blend->cb_target_mask;
101
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
105 *
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
107 */
108 if (blend && blend->dual_src_blend &&
109 sctx->ps_shader.cso &&
110 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
111 cb_target_mask = 0;
112
113 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
114
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
117 */
118 if (sctx->b.chip_class >= GFX9 &&
119 sctx->last_cb_target_mask != cb_target_mask) {
120 sctx->last_cb_target_mask = cb_target_mask;
121
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->b.rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx->screen->b.has_rbplus) {
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 }
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 R600_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 /**
381 * Get rid of DST in the blend factors by commuting the operands:
382 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
383 */
384 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
385 unsigned *dst_factor, unsigned expected_dst,
386 unsigned replacement_src)
387 {
388 if (*src_factor == expected_dst &&
389 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
390 *src_factor = PIPE_BLENDFACTOR_ZERO;
391 *dst_factor = replacement_src;
392
393 /* Commuting the operands requires reversing subtractions. */
394 if (*func == PIPE_BLEND_SUBTRACT)
395 *func = PIPE_BLEND_REVERSE_SUBTRACT;
396 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
397 *func = PIPE_BLEND_SUBTRACT;
398 }
399 }
400
401 static bool si_blend_factor_uses_dst(unsigned factor)
402 {
403 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
404 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
405 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
406 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
407 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
408 }
409
410 static void *si_create_blend_state_mode(struct pipe_context *ctx,
411 const struct pipe_blend_state *state,
412 unsigned mode)
413 {
414 struct si_context *sctx = (struct si_context*)ctx;
415 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
416 struct si_pm4_state *pm4 = &blend->pm4;
417 uint32_t sx_mrt_blend_opt[8] = {0};
418 uint32_t color_control = 0;
419
420 if (!blend)
421 return NULL;
422
423 blend->alpha_to_coverage = state->alpha_to_coverage;
424 blend->alpha_to_one = state->alpha_to_one;
425 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
426
427 if (state->logicop_enable) {
428 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
429 } else {
430 color_control |= S_028808_ROP3(0xcc);
431 }
432
433 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
434 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
435 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
436 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
439
440 if (state->alpha_to_coverage)
441 blend->need_src_alpha_4bit |= 0xf;
442
443 blend->cb_target_mask = 0;
444 for (int i = 0; i < 8; i++) {
445 /* state->rt entries > 0 only written if independent blending */
446 const int j = state->independent_blend_enable ? i : 0;
447
448 unsigned eqRGB = state->rt[j].rgb_func;
449 unsigned srcRGB = state->rt[j].rgb_src_factor;
450 unsigned dstRGB = state->rt[j].rgb_dst_factor;
451 unsigned eqA = state->rt[j].alpha_func;
452 unsigned srcA = state->rt[j].alpha_src_factor;
453 unsigned dstA = state->rt[j].alpha_dst_factor;
454
455 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
456 unsigned blend_cntl = 0;
457
458 sx_mrt_blend_opt[i] =
459 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
460 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
461
462 /* Only set dual source blending for MRT0 to avoid a hang. */
463 if (i >= 1 && blend->dual_src_blend) {
464 /* Vulkan does this for dual source blending. */
465 if (i == 1)
466 blend_cntl |= S_028780_ENABLE(1);
467
468 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
469 continue;
470 }
471
472 /* Only addition and subtraction equations are supported with
473 * dual source blending.
474 */
475 if (blend->dual_src_blend &&
476 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
477 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
478 assert(!"Unsupported equation for dual source blending");
479 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
480 continue;
481 }
482
483 /* cb_render_state will disable unused ones */
484 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
485
486 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
487 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
488 continue;
489 }
490
491 /* Blending optimizations for RB+.
492 * These transformations don't change the behavior.
493 *
494 * First, get rid of DST in the blend factors:
495 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
496 */
497 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
498 PIPE_BLENDFACTOR_DST_COLOR,
499 PIPE_BLENDFACTOR_SRC_COLOR);
500 si_blend_remove_dst(&eqA, &srcA, &dstA,
501 PIPE_BLENDFACTOR_DST_COLOR,
502 PIPE_BLENDFACTOR_SRC_COLOR);
503 si_blend_remove_dst(&eqA, &srcA, &dstA,
504 PIPE_BLENDFACTOR_DST_ALPHA,
505 PIPE_BLENDFACTOR_SRC_ALPHA);
506
507 /* Look up the ideal settings from tables. */
508 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
509 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
510 srcA_opt = si_translate_blend_opt_factor(srcA, true);
511 dstA_opt = si_translate_blend_opt_factor(dstA, true);
512
513 /* Handle interdependencies. */
514 if (si_blend_factor_uses_dst(srcRGB))
515 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
516 if (si_blend_factor_uses_dst(srcA))
517 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
518
519 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
520 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
521 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
522 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
523 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
524
525 /* Set the final value. */
526 sx_mrt_blend_opt[i] =
527 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
528 S_028760_COLOR_DST_OPT(dstRGB_opt) |
529 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
530 S_028760_ALPHA_SRC_OPT(srcA_opt) |
531 S_028760_ALPHA_DST_OPT(dstA_opt) |
532 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
533
534 /* Set blend state. */
535 blend_cntl |= S_028780_ENABLE(1);
536 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
537 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
538 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
539
540 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
541 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
542 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
543 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
544 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
545 }
546 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
547
548 blend->blend_enable_4bit |= 0xfu << (i * 4);
549
550 /* This is only important for formats without alpha. */
551 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
552 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
553 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
554 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
555 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
556 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
557 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
558 }
559
560 if (blend->cb_target_mask) {
561 color_control |= S_028808_MODE(mode);
562 } else {
563 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
564 }
565
566 if (sctx->screen->b.has_rbplus) {
567 /* Disable RB+ blend optimizations for dual source blending.
568 * Vulkan does this.
569 */
570 if (blend->dual_src_blend) {
571 for (int i = 0; i < 8; i++) {
572 sx_mrt_blend_opt[i] =
573 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
574 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
575 }
576 }
577
578 for (int i = 0; i < 8; i++)
579 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
580 sx_mrt_blend_opt[i]);
581
582 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
583 if (blend->dual_src_blend || state->logicop_enable ||
584 mode == V_028808_CB_RESOLVE)
585 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
586 }
587
588 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
589 return blend;
590 }
591
592 static void *si_create_blend_state(struct pipe_context *ctx,
593 const struct pipe_blend_state *state)
594 {
595 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
596 }
597
598 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
599 {
600 struct si_context *sctx = (struct si_context *)ctx;
601 struct si_state_blend *old_blend = sctx->queued.named.blend;
602 struct si_state_blend *blend = (struct si_state_blend *)state;
603
604 if (!state)
605 return;
606
607 if (!old_blend ||
608 old_blend->cb_target_mask != blend->cb_target_mask ||
609 old_blend->dual_src_blend != blend->dual_src_blend)
610 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
611
612 si_pm4_bind_state(sctx, blend, state);
613
614 if (!old_blend ||
615 old_blend->cb_target_mask != blend->cb_target_mask ||
616 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
617 old_blend->alpha_to_one != blend->alpha_to_one ||
618 old_blend->dual_src_blend != blend->dual_src_blend ||
619 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
620 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
621 sctx->do_update_shaders = true;
622 }
623
624 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
625 {
626 struct si_context *sctx = (struct si_context *)ctx;
627 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
628 }
629
630 static void si_set_blend_color(struct pipe_context *ctx,
631 const struct pipe_blend_color *state)
632 {
633 struct si_context *sctx = (struct si_context *)ctx;
634 static const struct pipe_blend_color zeros;
635
636 sctx->blend_color.state = *state;
637 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
638 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
639 }
640
641 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
642 {
643 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
644
645 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
646 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
647 }
648
649 /*
650 * Clipping
651 */
652
653 static void si_set_clip_state(struct pipe_context *ctx,
654 const struct pipe_clip_state *state)
655 {
656 struct si_context *sctx = (struct si_context *)ctx;
657 struct pipe_constant_buffer cb;
658 static const struct pipe_clip_state zeros;
659
660 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
661 return;
662
663 sctx->clip_state.state = *state;
664 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
665 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
666
667 cb.buffer = NULL;
668 cb.user_buffer = state->ucp;
669 cb.buffer_offset = 0;
670 cb.buffer_size = 4*4*8;
671 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
672 pipe_resource_reference(&cb.buffer, NULL);
673 }
674
675 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
676 {
677 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
678
679 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
680 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
681 }
682
683 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
684 {
685 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
686 struct si_shader *vs = si_get_vs_state(sctx);
687 struct si_shader_selector *vs_sel = vs->selector;
688 struct tgsi_shader_info *info = &vs_sel->info;
689 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
690 unsigned window_space =
691 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
692 unsigned clipdist_mask = vs_sel->clipdist_mask;
693 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
694 unsigned culldist_mask = vs_sel->culldist_mask;
695 unsigned total_mask;
696
697 if (vs->key.opt.clip_disable) {
698 assert(!info->culldist_writemask);
699 clipdist_mask = 0;
700 culldist_mask = 0;
701 }
702 total_mask = clipdist_mask | culldist_mask;
703
704 /* Clip distances on points have no effect, so need to be implemented
705 * as cull distances. This applies for the clipvertex case as well.
706 *
707 * Setting this for primitives other than points should have no adverse
708 * effects.
709 */
710 clipdist_mask &= rs->clip_plane_enable;
711 culldist_mask |= clipdist_mask;
712
713 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
714 vs_sel->pa_cl_vs_out_cntl |
715 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
716 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
717 clipdist_mask | (culldist_mask << 8));
718 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
719 rs->pa_cl_clip_cntl |
720 ucp_mask |
721 S_028810_CLIP_DISABLE(window_space));
722
723 if (sctx->b.chip_class <= VI) {
724 /* reuse needs to be set off if we write oViewport */
725 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
726 S_028AB4_REUSE_OFF(info->writes_viewport_index));
727 }
728 }
729
730 /*
731 * inferred state between framebuffer and rasterizer
732 */
733 static void si_update_poly_offset_state(struct si_context *sctx)
734 {
735 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
736
737 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
738 si_pm4_bind_state(sctx, poly_offset, NULL);
739 return;
740 }
741
742 /* Use the user format, not db_render_format, so that the polygon
743 * offset behaves as expected by applications.
744 */
745 switch (sctx->framebuffer.state.zsbuf->texture->format) {
746 case PIPE_FORMAT_Z16_UNORM:
747 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
748 break;
749 default: /* 24-bit */
750 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
751 break;
752 case PIPE_FORMAT_Z32_FLOAT:
753 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
754 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
755 break;
756 }
757 }
758
759 /*
760 * Rasterizer
761 */
762
763 static uint32_t si_translate_fill(uint32_t func)
764 {
765 switch(func) {
766 case PIPE_POLYGON_MODE_FILL:
767 return V_028814_X_DRAW_TRIANGLES;
768 case PIPE_POLYGON_MODE_LINE:
769 return V_028814_X_DRAW_LINES;
770 case PIPE_POLYGON_MODE_POINT:
771 return V_028814_X_DRAW_POINTS;
772 default:
773 assert(0);
774 return V_028814_X_DRAW_POINTS;
775 }
776 }
777
778 static void *si_create_rs_state(struct pipe_context *ctx,
779 const struct pipe_rasterizer_state *state)
780 {
781 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
782 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
783 struct si_pm4_state *pm4 = &rs->pm4;
784 unsigned tmp, i;
785 float psize_min, psize_max;
786
787 if (!rs) {
788 return NULL;
789 }
790
791 rs->scissor_enable = state->scissor;
792 rs->clip_halfz = state->clip_halfz;
793 rs->two_side = state->light_twoside;
794 rs->multisample_enable = state->multisample;
795 rs->force_persample_interp = state->force_persample_interp;
796 rs->clip_plane_enable = state->clip_plane_enable;
797 rs->line_stipple_enable = state->line_stipple_enable;
798 rs->poly_stipple_enable = state->poly_stipple_enable;
799 rs->line_smooth = state->line_smooth;
800 rs->poly_smooth = state->poly_smooth;
801 rs->uses_poly_offset = state->offset_point || state->offset_line ||
802 state->offset_tri;
803 rs->clamp_fragment_color = state->clamp_fragment_color;
804 rs->clamp_vertex_color = state->clamp_vertex_color;
805 rs->flatshade = state->flatshade;
806 rs->sprite_coord_enable = state->sprite_coord_enable;
807 rs->rasterizer_discard = state->rasterizer_discard;
808 rs->pa_sc_line_stipple = state->line_stipple_enable ?
809 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
810 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
811 rs->pa_cl_clip_cntl =
812 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
813 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
814 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
815 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
816 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
817
818 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
819 S_0286D4_FLAT_SHADE_ENA(1) |
820 S_0286D4_PNT_SPRITE_ENA(1) |
821 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
822 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
823 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
824 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
825 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
826
827 /* point size 12.4 fixed point */
828 tmp = (unsigned)(state->point_size * 8.0);
829 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
830
831 if (state->point_size_per_vertex) {
832 psize_min = util_get_min_point_size(state);
833 psize_max = 8192;
834 } else {
835 /* Force the point size to be as if the vertex output was disabled. */
836 psize_min = state->point_size;
837 psize_max = state->point_size;
838 }
839 /* Divide by two, because 0.5 = 1 pixel. */
840 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
841 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
842 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
843
844 tmp = (unsigned)state->line_width * 8;
845 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
846 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
847 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
848 S_028A48_MSAA_ENABLE(state->multisample ||
849 state->poly_smooth ||
850 state->line_smooth) |
851 S_028A48_VPORT_SCISSOR_ENABLE(1) |
852 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
853
854 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
855 S_028BE4_PIX_CENTER(state->half_pixel_center) |
856 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
857
858 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
859 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
860 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
861 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
862 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
863 S_028814_FACE(!state->front_ccw) |
864 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
865 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
866 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
867 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
868 state->fill_back != PIPE_POLYGON_MODE_FILL) |
869 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
870 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
871
872 if (!rs->uses_poly_offset)
873 return rs;
874
875 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
876 if (!rs->pm4_poly_offset) {
877 FREE(rs);
878 return NULL;
879 }
880
881 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
882 for (i = 0; i < 3; i++) {
883 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
884 float offset_units = state->offset_units;
885 float offset_scale = state->offset_scale * 16.0f;
886 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
887
888 if (!state->offset_units_unscaled) {
889 switch (i) {
890 case 0: /* 16-bit zbuffer */
891 offset_units *= 4.0f;
892 pa_su_poly_offset_db_fmt_cntl =
893 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
894 break;
895 case 1: /* 24-bit zbuffer */
896 offset_units *= 2.0f;
897 pa_su_poly_offset_db_fmt_cntl =
898 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
899 break;
900 case 2: /* 32-bit zbuffer */
901 offset_units *= 1.0f;
902 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
903 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
904 break;
905 }
906 }
907
908 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
909 fui(offset_scale));
910 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
911 fui(offset_units));
912 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
913 fui(offset_scale));
914 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
915 fui(offset_units));
916 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
917 pa_su_poly_offset_db_fmt_cntl);
918 }
919
920 return rs;
921 }
922
923 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
924 {
925 struct si_context *sctx = (struct si_context *)ctx;
926 struct si_state_rasterizer *old_rs =
927 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
928 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
929
930 if (!state)
931 return;
932
933 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
934 si_mark_atom_dirty(sctx, &sctx->db_render_state);
935
936 /* Update the small primitive filter workaround if necessary. */
937 if (sctx->screen->has_msaa_sample_loc_bug &&
938 sctx->framebuffer.nr_samples > 1)
939 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
940 }
941
942 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
943 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
944
945 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
946
947 si_pm4_bind_state(sctx, rasterizer, rs);
948 si_update_poly_offset_state(sctx);
949
950 if (!old_rs ||
951 old_rs->clip_plane_enable != rs->clip_plane_enable ||
952 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
953 si_mark_atom_dirty(sctx, &sctx->clip_regs);
954
955 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
956 rs->line_stipple_enable;
957
958 if (!old_rs ||
959 old_rs->clip_plane_enable != rs->clip_plane_enable ||
960 old_rs->rasterizer_discard != rs->rasterizer_discard ||
961 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
962 old_rs->flatshade != rs->flatshade ||
963 old_rs->two_side != rs->two_side ||
964 old_rs->multisample_enable != rs->multisample_enable ||
965 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
966 old_rs->poly_smooth != rs->poly_smooth ||
967 old_rs->line_smooth != rs->line_smooth ||
968 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
969 old_rs->force_persample_interp != rs->force_persample_interp)
970 sctx->do_update_shaders = true;
971 }
972
973 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
974 {
975 struct si_context *sctx = (struct si_context *)ctx;
976 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
977
978 if (sctx->queued.named.rasterizer == state)
979 si_pm4_bind_state(sctx, poly_offset, NULL);
980
981 FREE(rs->pm4_poly_offset);
982 si_pm4_delete_state(sctx, rasterizer, rs);
983 }
984
985 /*
986 * infeered state between dsa and stencil ref
987 */
988 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
989 {
990 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
991 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
992 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
993
994 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
995 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
996 S_028430_STENCILMASK(dsa->valuemask[0]) |
997 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
998 S_028430_STENCILOPVAL(1));
999 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1000 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1001 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1002 S_028434_STENCILOPVAL_BF(1));
1003 }
1004
1005 static void si_set_stencil_ref(struct pipe_context *ctx,
1006 const struct pipe_stencil_ref *state)
1007 {
1008 struct si_context *sctx = (struct si_context *)ctx;
1009
1010 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1011 return;
1012
1013 sctx->stencil_ref.state = *state;
1014 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1015 }
1016
1017
1018 /*
1019 * DSA
1020 */
1021
1022 static uint32_t si_translate_stencil_op(int s_op)
1023 {
1024 switch (s_op) {
1025 case PIPE_STENCIL_OP_KEEP:
1026 return V_02842C_STENCIL_KEEP;
1027 case PIPE_STENCIL_OP_ZERO:
1028 return V_02842C_STENCIL_ZERO;
1029 case PIPE_STENCIL_OP_REPLACE:
1030 return V_02842C_STENCIL_REPLACE_TEST;
1031 case PIPE_STENCIL_OP_INCR:
1032 return V_02842C_STENCIL_ADD_CLAMP;
1033 case PIPE_STENCIL_OP_DECR:
1034 return V_02842C_STENCIL_SUB_CLAMP;
1035 case PIPE_STENCIL_OP_INCR_WRAP:
1036 return V_02842C_STENCIL_ADD_WRAP;
1037 case PIPE_STENCIL_OP_DECR_WRAP:
1038 return V_02842C_STENCIL_SUB_WRAP;
1039 case PIPE_STENCIL_OP_INVERT:
1040 return V_02842C_STENCIL_INVERT;
1041 default:
1042 R600_ERR("Unknown stencil op %d", s_op);
1043 assert(0);
1044 break;
1045 }
1046 return 0;
1047 }
1048
1049 static void *si_create_dsa_state(struct pipe_context *ctx,
1050 const struct pipe_depth_stencil_alpha_state *state)
1051 {
1052 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1053 struct si_pm4_state *pm4 = &dsa->pm4;
1054 unsigned db_depth_control;
1055 uint32_t db_stencil_control = 0;
1056
1057 if (!dsa) {
1058 return NULL;
1059 }
1060
1061 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1062 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1063 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1064 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1065
1066 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1067 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1068 S_028800_ZFUNC(state->depth.func) |
1069 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1070
1071 /* stencil */
1072 if (state->stencil[0].enabled) {
1073 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1074 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1075 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1076 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1077 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1078
1079 if (state->stencil[1].enabled) {
1080 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1081 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1082 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1083 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1084 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1085 }
1086 }
1087
1088 /* alpha */
1089 if (state->alpha.enabled) {
1090 dsa->alpha_func = state->alpha.func;
1091
1092 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1093 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1094 } else {
1095 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1096 }
1097
1098 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1099 if (state->stencil[0].enabled)
1100 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1101 if (state->depth.bounds_test) {
1102 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1103 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1104 }
1105
1106 return dsa;
1107 }
1108
1109 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1110 {
1111 struct si_context *sctx = (struct si_context *)ctx;
1112 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1113 struct si_state_dsa *dsa = state;
1114
1115 if (!state)
1116 return;
1117
1118 si_pm4_bind_state(sctx, dsa, dsa);
1119
1120 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1121 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1122 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1123 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1124 }
1125
1126 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1127 sctx->do_update_shaders = true;
1128 }
1129
1130 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1131 {
1132 struct si_context *sctx = (struct si_context *)ctx;
1133 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1134 }
1135
1136 static void *si_create_db_flush_dsa(struct si_context *sctx)
1137 {
1138 struct pipe_depth_stencil_alpha_state dsa = {};
1139
1140 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1141 }
1142
1143 /* DB RENDER STATE */
1144
1145 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1146 {
1147 struct si_context *sctx = (struct si_context*)ctx;
1148
1149 /* Pipeline stat & streamout queries. */
1150 if (enable) {
1151 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1152 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1153 } else {
1154 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1155 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1156 }
1157
1158 /* Occlusion queries. */
1159 if (sctx->occlusion_queries_disabled != !enable) {
1160 sctx->occlusion_queries_disabled = !enable;
1161 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1162 }
1163 }
1164
1165 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1166 {
1167 struct si_context *sctx = (struct si_context*)ctx;
1168
1169 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1170 }
1171
1172 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1173 {
1174 struct si_context *sctx = (struct si_context*)ctx;
1175
1176 st->saved_compute = sctx->cs_shader_state.program;
1177
1178 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1179 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1180 }
1181
1182 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1183 {
1184 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1185 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1186 unsigned db_shader_control;
1187
1188 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1189
1190 /* DB_RENDER_CONTROL */
1191 if (sctx->dbcb_depth_copy_enabled ||
1192 sctx->dbcb_stencil_copy_enabled) {
1193 radeon_emit(cs,
1194 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1195 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1196 S_028000_COPY_CENTROID(1) |
1197 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1198 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1199 radeon_emit(cs,
1200 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1201 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1202 } else {
1203 radeon_emit(cs,
1204 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1205 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1206 }
1207
1208 /* DB_COUNT_CONTROL (occlusion queries) */
1209 if (sctx->b.num_occlusion_queries > 0 &&
1210 !sctx->occlusion_queries_disabled) {
1211 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1212
1213 if (sctx->b.chip_class >= CIK) {
1214 radeon_emit(cs,
1215 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1216 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1217 S_028004_ZPASS_ENABLE(1) |
1218 S_028004_SLICE_EVEN_ENABLE(1) |
1219 S_028004_SLICE_ODD_ENABLE(1));
1220 } else {
1221 radeon_emit(cs,
1222 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1223 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1224 }
1225 } else {
1226 /* Disable occlusion queries. */
1227 if (sctx->b.chip_class >= CIK) {
1228 radeon_emit(cs, 0);
1229 } else {
1230 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1231 }
1232 }
1233
1234 /* DB_RENDER_OVERRIDE2 */
1235 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1236 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1237 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1238 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1239
1240 db_shader_control = sctx->ps_db_shader_control;
1241
1242 /* Bug workaround for smoothing (overrasterization) on SI. */
1243 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1244 db_shader_control &= C_02880C_Z_ORDER;
1245 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1246 }
1247
1248 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1249 if (!rs || !rs->multisample_enable)
1250 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1251
1252 if (sctx->screen->b.has_rbplus &&
1253 !sctx->screen->b.rbplus_allowed)
1254 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1255
1256 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1257 db_shader_control);
1258 }
1259
1260 /*
1261 * format translation
1262 */
1263 static uint32_t si_translate_colorformat(enum pipe_format format)
1264 {
1265 const struct util_format_description *desc = util_format_description(format);
1266
1267 #define HAS_SIZE(x,y,z,w) \
1268 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1269 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1270
1271 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1272 return V_028C70_COLOR_10_11_11;
1273
1274 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1275 return V_028C70_COLOR_INVALID;
1276
1277 /* hw cannot support mixed formats (except depth/stencil, since
1278 * stencil is not written to). */
1279 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1280 return V_028C70_COLOR_INVALID;
1281
1282 switch (desc->nr_channels) {
1283 case 1:
1284 switch (desc->channel[0].size) {
1285 case 8:
1286 return V_028C70_COLOR_8;
1287 case 16:
1288 return V_028C70_COLOR_16;
1289 case 32:
1290 return V_028C70_COLOR_32;
1291 }
1292 break;
1293 case 2:
1294 if (desc->channel[0].size == desc->channel[1].size) {
1295 switch (desc->channel[0].size) {
1296 case 8:
1297 return V_028C70_COLOR_8_8;
1298 case 16:
1299 return V_028C70_COLOR_16_16;
1300 case 32:
1301 return V_028C70_COLOR_32_32;
1302 }
1303 } else if (HAS_SIZE(8,24,0,0)) {
1304 return V_028C70_COLOR_24_8;
1305 } else if (HAS_SIZE(24,8,0,0)) {
1306 return V_028C70_COLOR_8_24;
1307 }
1308 break;
1309 case 3:
1310 if (HAS_SIZE(5,6,5,0)) {
1311 return V_028C70_COLOR_5_6_5;
1312 } else if (HAS_SIZE(32,8,24,0)) {
1313 return V_028C70_COLOR_X24_8_32_FLOAT;
1314 }
1315 break;
1316 case 4:
1317 if (desc->channel[0].size == desc->channel[1].size &&
1318 desc->channel[0].size == desc->channel[2].size &&
1319 desc->channel[0].size == desc->channel[3].size) {
1320 switch (desc->channel[0].size) {
1321 case 4:
1322 return V_028C70_COLOR_4_4_4_4;
1323 case 8:
1324 return V_028C70_COLOR_8_8_8_8;
1325 case 16:
1326 return V_028C70_COLOR_16_16_16_16;
1327 case 32:
1328 return V_028C70_COLOR_32_32_32_32;
1329 }
1330 } else if (HAS_SIZE(5,5,5,1)) {
1331 return V_028C70_COLOR_1_5_5_5;
1332 } else if (HAS_SIZE(10,10,10,2)) {
1333 return V_028C70_COLOR_2_10_10_10;
1334 }
1335 break;
1336 }
1337 return V_028C70_COLOR_INVALID;
1338 }
1339
1340 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1341 {
1342 if (SI_BIG_ENDIAN) {
1343 switch(colorformat) {
1344 /* 8-bit buffers. */
1345 case V_028C70_COLOR_8:
1346 return V_028C70_ENDIAN_NONE;
1347
1348 /* 16-bit buffers. */
1349 case V_028C70_COLOR_5_6_5:
1350 case V_028C70_COLOR_1_5_5_5:
1351 case V_028C70_COLOR_4_4_4_4:
1352 case V_028C70_COLOR_16:
1353 case V_028C70_COLOR_8_8:
1354 return V_028C70_ENDIAN_8IN16;
1355
1356 /* 32-bit buffers. */
1357 case V_028C70_COLOR_8_8_8_8:
1358 case V_028C70_COLOR_2_10_10_10:
1359 case V_028C70_COLOR_8_24:
1360 case V_028C70_COLOR_24_8:
1361 case V_028C70_COLOR_16_16:
1362 return V_028C70_ENDIAN_8IN32;
1363
1364 /* 64-bit buffers. */
1365 case V_028C70_COLOR_16_16_16_16:
1366 return V_028C70_ENDIAN_8IN16;
1367
1368 case V_028C70_COLOR_32_32:
1369 return V_028C70_ENDIAN_8IN32;
1370
1371 /* 128-bit buffers. */
1372 case V_028C70_COLOR_32_32_32_32:
1373 return V_028C70_ENDIAN_8IN32;
1374 default:
1375 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1376 }
1377 } else {
1378 return V_028C70_ENDIAN_NONE;
1379 }
1380 }
1381
1382 static uint32_t si_translate_dbformat(enum pipe_format format)
1383 {
1384 switch (format) {
1385 case PIPE_FORMAT_Z16_UNORM:
1386 return V_028040_Z_16;
1387 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1388 case PIPE_FORMAT_X8Z24_UNORM:
1389 case PIPE_FORMAT_Z24X8_UNORM:
1390 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1391 return V_028040_Z_24; /* deprecated on SI */
1392 case PIPE_FORMAT_Z32_FLOAT:
1393 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1394 return V_028040_Z_32_FLOAT;
1395 default:
1396 return V_028040_Z_INVALID;
1397 }
1398 }
1399
1400 /*
1401 * Texture translation
1402 */
1403
1404 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1405 enum pipe_format format,
1406 const struct util_format_description *desc,
1407 int first_non_void)
1408 {
1409 struct si_screen *sscreen = (struct si_screen*)screen;
1410 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1411 sscreen->b.info.drm_minor >= 31) ||
1412 sscreen->b.info.drm_major == 3;
1413 bool uniform = true;
1414 int i;
1415
1416 /* Colorspace (return non-RGB formats directly). */
1417 switch (desc->colorspace) {
1418 /* Depth stencil formats */
1419 case UTIL_FORMAT_COLORSPACE_ZS:
1420 switch (format) {
1421 case PIPE_FORMAT_Z16_UNORM:
1422 return V_008F14_IMG_DATA_FORMAT_16;
1423 case PIPE_FORMAT_X24S8_UINT:
1424 case PIPE_FORMAT_S8X24_UINT:
1425 /*
1426 * Implemented as an 8_8_8_8 data format to fix texture
1427 * gathers in stencil sampling. This affects at least
1428 * GL45-CTS.texture_cube_map_array.sampling on VI.
1429 */
1430 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1431 case PIPE_FORMAT_Z24X8_UNORM:
1432 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1433 return V_008F14_IMG_DATA_FORMAT_8_24;
1434 case PIPE_FORMAT_X8Z24_UNORM:
1435 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1436 return V_008F14_IMG_DATA_FORMAT_24_8;
1437 case PIPE_FORMAT_S8_UINT:
1438 return V_008F14_IMG_DATA_FORMAT_8;
1439 case PIPE_FORMAT_Z32_FLOAT:
1440 return V_008F14_IMG_DATA_FORMAT_32;
1441 case PIPE_FORMAT_X32_S8X24_UINT:
1442 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1443 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1444 default:
1445 goto out_unknown;
1446 }
1447
1448 case UTIL_FORMAT_COLORSPACE_YUV:
1449 goto out_unknown; /* TODO */
1450
1451 case UTIL_FORMAT_COLORSPACE_SRGB:
1452 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1453 goto out_unknown;
1454 break;
1455
1456 default:
1457 break;
1458 }
1459
1460 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1461 if (!enable_compressed_formats)
1462 goto out_unknown;
1463
1464 switch (format) {
1465 case PIPE_FORMAT_RGTC1_SNORM:
1466 case PIPE_FORMAT_LATC1_SNORM:
1467 case PIPE_FORMAT_RGTC1_UNORM:
1468 case PIPE_FORMAT_LATC1_UNORM:
1469 return V_008F14_IMG_DATA_FORMAT_BC4;
1470 case PIPE_FORMAT_RGTC2_SNORM:
1471 case PIPE_FORMAT_LATC2_SNORM:
1472 case PIPE_FORMAT_RGTC2_UNORM:
1473 case PIPE_FORMAT_LATC2_UNORM:
1474 return V_008F14_IMG_DATA_FORMAT_BC5;
1475 default:
1476 goto out_unknown;
1477 }
1478 }
1479
1480 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1481 (sscreen->b.family == CHIP_STONEY ||
1482 sscreen->b.chip_class >= GFX9)) {
1483 switch (format) {
1484 case PIPE_FORMAT_ETC1_RGB8:
1485 case PIPE_FORMAT_ETC2_RGB8:
1486 case PIPE_FORMAT_ETC2_SRGB8:
1487 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1488 case PIPE_FORMAT_ETC2_RGB8A1:
1489 case PIPE_FORMAT_ETC2_SRGB8A1:
1490 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1491 case PIPE_FORMAT_ETC2_RGBA8:
1492 case PIPE_FORMAT_ETC2_SRGBA8:
1493 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1494 case PIPE_FORMAT_ETC2_R11_UNORM:
1495 case PIPE_FORMAT_ETC2_R11_SNORM:
1496 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1497 case PIPE_FORMAT_ETC2_RG11_UNORM:
1498 case PIPE_FORMAT_ETC2_RG11_SNORM:
1499 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1500 default:
1501 goto out_unknown;
1502 }
1503 }
1504
1505 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1506 if (!enable_compressed_formats)
1507 goto out_unknown;
1508
1509 switch (format) {
1510 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1511 case PIPE_FORMAT_BPTC_SRGBA:
1512 return V_008F14_IMG_DATA_FORMAT_BC7;
1513 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1514 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1515 return V_008F14_IMG_DATA_FORMAT_BC6;
1516 default:
1517 goto out_unknown;
1518 }
1519 }
1520
1521 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1522 switch (format) {
1523 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1524 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1525 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1526 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1527 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1528 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1529 default:
1530 goto out_unknown;
1531 }
1532 }
1533
1534 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1535 if (!enable_compressed_formats)
1536 goto out_unknown;
1537
1538 if (!util_format_s3tc_enabled) {
1539 goto out_unknown;
1540 }
1541
1542 switch (format) {
1543 case PIPE_FORMAT_DXT1_RGB:
1544 case PIPE_FORMAT_DXT1_RGBA:
1545 case PIPE_FORMAT_DXT1_SRGB:
1546 case PIPE_FORMAT_DXT1_SRGBA:
1547 return V_008F14_IMG_DATA_FORMAT_BC1;
1548 case PIPE_FORMAT_DXT3_RGBA:
1549 case PIPE_FORMAT_DXT3_SRGBA:
1550 return V_008F14_IMG_DATA_FORMAT_BC2;
1551 case PIPE_FORMAT_DXT5_RGBA:
1552 case PIPE_FORMAT_DXT5_SRGBA:
1553 return V_008F14_IMG_DATA_FORMAT_BC3;
1554 default:
1555 goto out_unknown;
1556 }
1557 }
1558
1559 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1560 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1561 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1562 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1563 }
1564
1565 /* R8G8Bx_SNORM - TODO CxV8U8 */
1566
1567 /* hw cannot support mixed formats (except depth/stencil, since only
1568 * depth is read).*/
1569 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1570 goto out_unknown;
1571
1572 /* See whether the components are of the same size. */
1573 for (i = 1; i < desc->nr_channels; i++) {
1574 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1575 }
1576
1577 /* Non-uniform formats. */
1578 if (!uniform) {
1579 switch(desc->nr_channels) {
1580 case 3:
1581 if (desc->channel[0].size == 5 &&
1582 desc->channel[1].size == 6 &&
1583 desc->channel[2].size == 5) {
1584 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1585 }
1586 goto out_unknown;
1587 case 4:
1588 if (desc->channel[0].size == 5 &&
1589 desc->channel[1].size == 5 &&
1590 desc->channel[2].size == 5 &&
1591 desc->channel[3].size == 1) {
1592 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1593 }
1594 if (desc->channel[0].size == 10 &&
1595 desc->channel[1].size == 10 &&
1596 desc->channel[2].size == 10 &&
1597 desc->channel[3].size == 2) {
1598 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1599 }
1600 goto out_unknown;
1601 }
1602 goto out_unknown;
1603 }
1604
1605 if (first_non_void < 0 || first_non_void > 3)
1606 goto out_unknown;
1607
1608 /* uniform formats */
1609 switch (desc->channel[first_non_void].size) {
1610 case 4:
1611 switch (desc->nr_channels) {
1612 #if 0 /* Not supported for render targets */
1613 case 2:
1614 return V_008F14_IMG_DATA_FORMAT_4_4;
1615 #endif
1616 case 4:
1617 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1618 }
1619 break;
1620 case 8:
1621 switch (desc->nr_channels) {
1622 case 1:
1623 return V_008F14_IMG_DATA_FORMAT_8;
1624 case 2:
1625 return V_008F14_IMG_DATA_FORMAT_8_8;
1626 case 4:
1627 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1628 }
1629 break;
1630 case 16:
1631 switch (desc->nr_channels) {
1632 case 1:
1633 return V_008F14_IMG_DATA_FORMAT_16;
1634 case 2:
1635 return V_008F14_IMG_DATA_FORMAT_16_16;
1636 case 4:
1637 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1638 }
1639 break;
1640 case 32:
1641 switch (desc->nr_channels) {
1642 case 1:
1643 return V_008F14_IMG_DATA_FORMAT_32;
1644 case 2:
1645 return V_008F14_IMG_DATA_FORMAT_32_32;
1646 #if 0 /* Not supported for render targets */
1647 case 3:
1648 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1649 #endif
1650 case 4:
1651 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1652 }
1653 }
1654
1655 out_unknown:
1656 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1657 return ~0;
1658 }
1659
1660 static unsigned si_tex_wrap(unsigned wrap)
1661 {
1662 switch (wrap) {
1663 default:
1664 case PIPE_TEX_WRAP_REPEAT:
1665 return V_008F30_SQ_TEX_WRAP;
1666 case PIPE_TEX_WRAP_CLAMP:
1667 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1668 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1669 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1670 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1671 return V_008F30_SQ_TEX_CLAMP_BORDER;
1672 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1673 return V_008F30_SQ_TEX_MIRROR;
1674 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1675 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1676 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1677 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1678 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1679 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1680 }
1681 }
1682
1683 static unsigned si_tex_mipfilter(unsigned filter)
1684 {
1685 switch (filter) {
1686 case PIPE_TEX_MIPFILTER_NEAREST:
1687 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1688 case PIPE_TEX_MIPFILTER_LINEAR:
1689 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1690 default:
1691 case PIPE_TEX_MIPFILTER_NONE:
1692 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1693 }
1694 }
1695
1696 static unsigned si_tex_compare(unsigned compare)
1697 {
1698 switch (compare) {
1699 default:
1700 case PIPE_FUNC_NEVER:
1701 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1702 case PIPE_FUNC_LESS:
1703 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1704 case PIPE_FUNC_EQUAL:
1705 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1706 case PIPE_FUNC_LEQUAL:
1707 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1708 case PIPE_FUNC_GREATER:
1709 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1710 case PIPE_FUNC_NOTEQUAL:
1711 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1712 case PIPE_FUNC_GEQUAL:
1713 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1714 case PIPE_FUNC_ALWAYS:
1715 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1716 }
1717 }
1718
1719 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1720 unsigned view_target, unsigned nr_samples)
1721 {
1722 unsigned res_target = rtex->resource.b.b.target;
1723
1724 if (view_target == PIPE_TEXTURE_CUBE ||
1725 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1726 res_target = view_target;
1727 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1728 else if (res_target == PIPE_TEXTURE_CUBE ||
1729 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1730 res_target = PIPE_TEXTURE_2D_ARRAY;
1731
1732 /* GFX9 allocates 1D textures as 2D. */
1733 if ((res_target == PIPE_TEXTURE_1D ||
1734 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1735 sscreen->b.chip_class >= GFX9 &&
1736 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1737 if (res_target == PIPE_TEXTURE_1D)
1738 res_target = PIPE_TEXTURE_2D;
1739 else
1740 res_target = PIPE_TEXTURE_2D_ARRAY;
1741 }
1742
1743 switch (res_target) {
1744 default:
1745 case PIPE_TEXTURE_1D:
1746 return V_008F1C_SQ_RSRC_IMG_1D;
1747 case PIPE_TEXTURE_1D_ARRAY:
1748 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1749 case PIPE_TEXTURE_2D:
1750 case PIPE_TEXTURE_RECT:
1751 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1752 V_008F1C_SQ_RSRC_IMG_2D;
1753 case PIPE_TEXTURE_2D_ARRAY:
1754 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1755 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1756 case PIPE_TEXTURE_3D:
1757 return V_008F1C_SQ_RSRC_IMG_3D;
1758 case PIPE_TEXTURE_CUBE:
1759 case PIPE_TEXTURE_CUBE_ARRAY:
1760 return V_008F1C_SQ_RSRC_IMG_CUBE;
1761 }
1762 }
1763
1764 /*
1765 * Format support testing
1766 */
1767
1768 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1769 {
1770 return si_translate_texformat(screen, format, util_format_description(format),
1771 util_format_get_first_non_void_channel(format)) != ~0U;
1772 }
1773
1774 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1775 const struct util_format_description *desc,
1776 int first_non_void)
1777 {
1778 int i;
1779
1780 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1781 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1782
1783 assert(first_non_void >= 0);
1784
1785 if (desc->nr_channels == 4 &&
1786 desc->channel[0].size == 10 &&
1787 desc->channel[1].size == 10 &&
1788 desc->channel[2].size == 10 &&
1789 desc->channel[3].size == 2)
1790 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1791
1792 /* See whether the components are of the same size. */
1793 for (i = 0; i < desc->nr_channels; i++) {
1794 if (desc->channel[first_non_void].size != desc->channel[i].size)
1795 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1796 }
1797
1798 switch (desc->channel[first_non_void].size) {
1799 case 8:
1800 switch (desc->nr_channels) {
1801 case 1:
1802 case 3: /* 3 loads */
1803 return V_008F0C_BUF_DATA_FORMAT_8;
1804 case 2:
1805 return V_008F0C_BUF_DATA_FORMAT_8_8;
1806 case 4:
1807 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1808 }
1809 break;
1810 case 16:
1811 switch (desc->nr_channels) {
1812 case 1:
1813 case 3: /* 3 loads */
1814 return V_008F0C_BUF_DATA_FORMAT_16;
1815 case 2:
1816 return V_008F0C_BUF_DATA_FORMAT_16_16;
1817 case 4:
1818 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1819 }
1820 break;
1821 case 32:
1822 switch (desc->nr_channels) {
1823 case 1:
1824 return V_008F0C_BUF_DATA_FORMAT_32;
1825 case 2:
1826 return V_008F0C_BUF_DATA_FORMAT_32_32;
1827 case 3:
1828 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1829 case 4:
1830 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1831 }
1832 break;
1833 case 64:
1834 /* Legacy double formats. */
1835 switch (desc->nr_channels) {
1836 case 1: /* 1 load */
1837 return V_008F0C_BUF_DATA_FORMAT_32_32;
1838 case 2: /* 1 load */
1839 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1840 case 3: /* 3 loads */
1841 return V_008F0C_BUF_DATA_FORMAT_32_32;
1842 case 4: /* 2 loads */
1843 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1844 }
1845 break;
1846 }
1847
1848 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1849 }
1850
1851 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1852 const struct util_format_description *desc,
1853 int first_non_void)
1854 {
1855 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1856 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1857
1858 assert(first_non_void >= 0);
1859
1860 switch (desc->channel[first_non_void].type) {
1861 case UTIL_FORMAT_TYPE_SIGNED:
1862 case UTIL_FORMAT_TYPE_FIXED:
1863 if (desc->channel[first_non_void].size >= 32 ||
1864 desc->channel[first_non_void].pure_integer)
1865 return V_008F0C_BUF_NUM_FORMAT_SINT;
1866 else if (desc->channel[first_non_void].normalized)
1867 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1868 else
1869 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1870 break;
1871 case UTIL_FORMAT_TYPE_UNSIGNED:
1872 if (desc->channel[first_non_void].size >= 32 ||
1873 desc->channel[first_non_void].pure_integer)
1874 return V_008F0C_BUF_NUM_FORMAT_UINT;
1875 else if (desc->channel[first_non_void].normalized)
1876 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1877 else
1878 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1879 break;
1880 case UTIL_FORMAT_TYPE_FLOAT:
1881 default:
1882 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1883 }
1884 }
1885
1886 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1887 enum pipe_format format,
1888 unsigned usage)
1889 {
1890 const struct util_format_description *desc;
1891 int first_non_void;
1892 unsigned data_format;
1893
1894 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1895 PIPE_BIND_SAMPLER_VIEW |
1896 PIPE_BIND_VERTEX_BUFFER)) == 0);
1897
1898 desc = util_format_description(format);
1899
1900 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1901 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1902 * for read-only access (with caveats surrounding bounds checks), but
1903 * obviously fails for write access which we have to implement for
1904 * shader images. Luckily, OpenGL doesn't expect this to be supported
1905 * anyway, and so the only impact is on PBO uploads / downloads, which
1906 * shouldn't be expected to be fast for GL_RGB anyway.
1907 */
1908 if (desc->block.bits == 3 * 8 ||
1909 desc->block.bits == 3 * 16) {
1910 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1911 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1912 if (!usage)
1913 return 0;
1914 }
1915 }
1916
1917 first_non_void = util_format_get_first_non_void_channel(format);
1918 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1919 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1920 return 0;
1921
1922 return usage;
1923 }
1924
1925 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1926 {
1927 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1928 r600_translate_colorswap(format, false) != ~0U;
1929 }
1930
1931 static bool si_is_zs_format_supported(enum pipe_format format)
1932 {
1933 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1934 }
1935
1936 static boolean si_is_format_supported(struct pipe_screen *screen,
1937 enum pipe_format format,
1938 enum pipe_texture_target target,
1939 unsigned sample_count,
1940 unsigned usage)
1941 {
1942 unsigned retval = 0;
1943
1944 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1945 R600_ERR("r600: unsupported texture type %d\n", target);
1946 return false;
1947 }
1948
1949 if (!util_format_is_supported(format, usage))
1950 return false;
1951
1952 if (sample_count > 1) {
1953 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1954 return false;
1955
1956 if (usage & PIPE_BIND_SHADER_IMAGE)
1957 return false;
1958
1959 switch (sample_count) {
1960 case 2:
1961 case 4:
1962 case 8:
1963 break;
1964 case 16:
1965 if (format == PIPE_FORMAT_NONE)
1966 return true;
1967 else
1968 return false;
1969 default:
1970 return false;
1971 }
1972 }
1973
1974 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1975 PIPE_BIND_SHADER_IMAGE)) {
1976 if (target == PIPE_BUFFER) {
1977 retval |= si_is_vertex_format_supported(
1978 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1979 PIPE_BIND_SHADER_IMAGE));
1980 } else {
1981 if (si_is_sampler_format_supported(screen, format))
1982 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1983 PIPE_BIND_SHADER_IMAGE);
1984 }
1985 }
1986
1987 if ((usage & (PIPE_BIND_RENDER_TARGET |
1988 PIPE_BIND_DISPLAY_TARGET |
1989 PIPE_BIND_SCANOUT |
1990 PIPE_BIND_SHARED |
1991 PIPE_BIND_BLENDABLE)) &&
1992 si_is_colorbuffer_format_supported(format)) {
1993 retval |= usage &
1994 (PIPE_BIND_RENDER_TARGET |
1995 PIPE_BIND_DISPLAY_TARGET |
1996 PIPE_BIND_SCANOUT |
1997 PIPE_BIND_SHARED);
1998 if (!util_format_is_pure_integer(format) &&
1999 !util_format_is_depth_or_stencil(format))
2000 retval |= usage & PIPE_BIND_BLENDABLE;
2001 }
2002
2003 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2004 si_is_zs_format_supported(format)) {
2005 retval |= PIPE_BIND_DEPTH_STENCIL;
2006 }
2007
2008 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2009 retval |= si_is_vertex_format_supported(screen, format,
2010 PIPE_BIND_VERTEX_BUFFER);
2011 }
2012
2013 if ((usage & PIPE_BIND_LINEAR) &&
2014 !util_format_is_compressed(format) &&
2015 !(usage & PIPE_BIND_DEPTH_STENCIL))
2016 retval |= PIPE_BIND_LINEAR;
2017
2018 return retval == usage;
2019 }
2020
2021 /*
2022 * framebuffer handling
2023 */
2024
2025 static void si_choose_spi_color_formats(struct r600_surface *surf,
2026 unsigned format, unsigned swap,
2027 unsigned ntype, bool is_depth)
2028 {
2029 /* Alpha is needed for alpha-to-coverage.
2030 * Blending may be with or without alpha.
2031 */
2032 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2033 unsigned alpha = 0; /* exports alpha, but may not support blending */
2034 unsigned blend = 0; /* supports blending, but may not export alpha */
2035 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2036
2037 /* Choose the SPI color formats. These are required values for RB+.
2038 * Other chips have multiple choices, though they are not necessarily better.
2039 */
2040 switch (format) {
2041 case V_028C70_COLOR_5_6_5:
2042 case V_028C70_COLOR_1_5_5_5:
2043 case V_028C70_COLOR_5_5_5_1:
2044 case V_028C70_COLOR_4_4_4_4:
2045 case V_028C70_COLOR_10_11_11:
2046 case V_028C70_COLOR_11_11_10:
2047 case V_028C70_COLOR_8:
2048 case V_028C70_COLOR_8_8:
2049 case V_028C70_COLOR_8_8_8_8:
2050 case V_028C70_COLOR_10_10_10_2:
2051 case V_028C70_COLOR_2_10_10_10:
2052 if (ntype == V_028C70_NUMBER_UINT)
2053 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2054 else if (ntype == V_028C70_NUMBER_SINT)
2055 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2056 else
2057 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2058 break;
2059
2060 case V_028C70_COLOR_16:
2061 case V_028C70_COLOR_16_16:
2062 case V_028C70_COLOR_16_16_16_16:
2063 if (ntype == V_028C70_NUMBER_UNORM ||
2064 ntype == V_028C70_NUMBER_SNORM) {
2065 /* UNORM16 and SNORM16 don't support blending */
2066 if (ntype == V_028C70_NUMBER_UNORM)
2067 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2068 else
2069 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2070
2071 /* Use 32 bits per channel for blending. */
2072 if (format == V_028C70_COLOR_16) {
2073 if (swap == V_028C70_SWAP_STD) { /* R */
2074 blend = V_028714_SPI_SHADER_32_R;
2075 blend_alpha = V_028714_SPI_SHADER_32_AR;
2076 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2077 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2078 else
2079 assert(0);
2080 } else if (format == V_028C70_COLOR_16_16) {
2081 if (swap == V_028C70_SWAP_STD) { /* RG */
2082 blend = V_028714_SPI_SHADER_32_GR;
2083 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2084 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2085 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2086 else
2087 assert(0);
2088 } else /* 16_16_16_16 */
2089 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2090 } else if (ntype == V_028C70_NUMBER_UINT)
2091 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2092 else if (ntype == V_028C70_NUMBER_SINT)
2093 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2094 else if (ntype == V_028C70_NUMBER_FLOAT)
2095 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2096 else
2097 assert(0);
2098 break;
2099
2100 case V_028C70_COLOR_32:
2101 if (swap == V_028C70_SWAP_STD) { /* R */
2102 blend = normal = V_028714_SPI_SHADER_32_R;
2103 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2104 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2105 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2106 else
2107 assert(0);
2108 break;
2109
2110 case V_028C70_COLOR_32_32:
2111 if (swap == V_028C70_SWAP_STD) { /* RG */
2112 blend = normal = V_028714_SPI_SHADER_32_GR;
2113 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2114 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2115 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2116 else
2117 assert(0);
2118 break;
2119
2120 case V_028C70_COLOR_32_32_32_32:
2121 case V_028C70_COLOR_8_24:
2122 case V_028C70_COLOR_24_8:
2123 case V_028C70_COLOR_X24_8_32_FLOAT:
2124 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2125 break;
2126
2127 default:
2128 assert(0);
2129 return;
2130 }
2131
2132 /* The DB->CB copy needs 32_ABGR. */
2133 if (is_depth)
2134 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2135
2136 surf->spi_shader_col_format = normal;
2137 surf->spi_shader_col_format_alpha = alpha;
2138 surf->spi_shader_col_format_blend = blend;
2139 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2140 }
2141
2142 static void si_initialize_color_surface(struct si_context *sctx,
2143 struct r600_surface *surf)
2144 {
2145 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2146 unsigned color_info, color_attrib, color_view;
2147 unsigned format, swap, ntype, endian;
2148 const struct util_format_description *desc;
2149 int i;
2150 unsigned blend_clamp = 0, blend_bypass = 0;
2151
2152 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2153 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2154
2155 desc = util_format_description(surf->base.format);
2156 for (i = 0; i < 4; i++) {
2157 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2158 break;
2159 }
2160 }
2161 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2162 ntype = V_028C70_NUMBER_FLOAT;
2163 } else {
2164 ntype = V_028C70_NUMBER_UNORM;
2165 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2166 ntype = V_028C70_NUMBER_SRGB;
2167 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2168 if (desc->channel[i].pure_integer) {
2169 ntype = V_028C70_NUMBER_SINT;
2170 } else {
2171 assert(desc->channel[i].normalized);
2172 ntype = V_028C70_NUMBER_SNORM;
2173 }
2174 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2175 if (desc->channel[i].pure_integer) {
2176 ntype = V_028C70_NUMBER_UINT;
2177 } else {
2178 assert(desc->channel[i].normalized);
2179 ntype = V_028C70_NUMBER_UNORM;
2180 }
2181 }
2182 }
2183
2184 format = si_translate_colorformat(surf->base.format);
2185 if (format == V_028C70_COLOR_INVALID) {
2186 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2187 }
2188 assert(format != V_028C70_COLOR_INVALID);
2189 swap = r600_translate_colorswap(surf->base.format, false);
2190 endian = si_colorformat_endian_swap(format);
2191
2192 /* blend clamp should be set for all NORM/SRGB types */
2193 if (ntype == V_028C70_NUMBER_UNORM ||
2194 ntype == V_028C70_NUMBER_SNORM ||
2195 ntype == V_028C70_NUMBER_SRGB)
2196 blend_clamp = 1;
2197
2198 /* set blend bypass according to docs if SINT/UINT or
2199 8/24 COLOR variants */
2200 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2201 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2202 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2203 blend_clamp = 0;
2204 blend_bypass = 1;
2205 }
2206
2207 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2208 if (format == V_028C70_COLOR_8 ||
2209 format == V_028C70_COLOR_8_8 ||
2210 format == V_028C70_COLOR_8_8_8_8)
2211 surf->color_is_int8 = true;
2212 else if (format == V_028C70_COLOR_10_10_10_2 ||
2213 format == V_028C70_COLOR_2_10_10_10)
2214 surf->color_is_int10 = true;
2215 }
2216
2217 color_info = S_028C70_FORMAT(format) |
2218 S_028C70_COMP_SWAP(swap) |
2219 S_028C70_BLEND_CLAMP(blend_clamp) |
2220 S_028C70_BLEND_BYPASS(blend_bypass) |
2221 S_028C70_SIMPLE_FLOAT(1) |
2222 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2223 ntype != V_028C70_NUMBER_SNORM &&
2224 ntype != V_028C70_NUMBER_SRGB &&
2225 format != V_028C70_COLOR_8_24 &&
2226 format != V_028C70_COLOR_24_8) |
2227 S_028C70_NUMBER_TYPE(ntype) |
2228 S_028C70_ENDIAN(endian);
2229
2230 /* Intensity is implemented as Red, so treat it that way. */
2231 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2232 util_format_is_intensity(surf->base.format));
2233
2234 if (rtex->resource.b.b.nr_samples > 1) {
2235 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2236
2237 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2238 S_028C74_NUM_FRAGMENTS(log_samples);
2239
2240 if (rtex->fmask.size) {
2241 color_info |= S_028C70_COMPRESSION(1);
2242 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2243
2244 if (sctx->b.chip_class == SI) {
2245 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2246 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2247 }
2248 }
2249 }
2250
2251 surf->cb_color_view = color_view;
2252 surf->cb_color_info = color_info;
2253 surf->cb_color_attrib = color_attrib;
2254
2255 if (sctx->b.chip_class >= VI) {
2256 unsigned max_uncompressed_block_size = 2;
2257
2258 if (rtex->resource.b.b.nr_samples > 1) {
2259 if (rtex->surface.bpe == 1)
2260 max_uncompressed_block_size = 0;
2261 else if (rtex->surface.bpe == 2)
2262 max_uncompressed_block_size = 1;
2263 }
2264
2265 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2266 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2267 }
2268
2269 /* This must be set for fast clear to work without FMASK. */
2270 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2271 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2272 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2273 }
2274
2275 if (sctx->b.chip_class >= GFX9) {
2276 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2277
2278 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2279 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2280 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2281 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2282 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2283 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2284 }
2285
2286 /* Determine pixel shader export format */
2287 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2288
2289 surf->color_initialized = true;
2290 }
2291
2292 static void si_init_depth_surface(struct si_context *sctx,
2293 struct r600_surface *surf)
2294 {
2295 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2296 unsigned level = surf->base.u.tex.level;
2297 unsigned format, stencil_format;
2298 uint32_t z_info, s_info;
2299
2300 format = si_translate_dbformat(rtex->db_render_format);
2301 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2302 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2303
2304 assert(format != V_028040_Z_INVALID);
2305 if (format == V_028040_Z_INVALID)
2306 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2307
2308 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2309 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2310 surf->db_htile_data_base = 0;
2311 surf->db_htile_surface = 0;
2312
2313 if (sctx->b.chip_class >= GFX9) {
2314 assert(rtex->surface.u.gfx9.surf_offset == 0);
2315 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2316 surf->db_stencil_base = (rtex->resource.gpu_address +
2317 rtex->surface.u.gfx9.stencil_offset) >> 8;
2318 z_info = S_028038_FORMAT(format) |
2319 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2320 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2321 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2322 s_info = S_02803C_FORMAT(stencil_format) |
2323 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2324 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2325 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2326 surf->db_depth_view |= S_028008_MIPID(level);
2327 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2328 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2329
2330 /* Only use HTILE for the first level. */
2331 if (rtex->htile_offset && !level) {
2332 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2333 S_028038_ALLOW_EXPCLEAR(1);
2334
2335 if (rtex->tc_compatible_htile) {
2336 unsigned max_zplanes = 4;
2337
2338 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2339 rtex->resource.b.b.nr_samples > 1)
2340 max_zplanes = 2;
2341
2342 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2343 S_028038_ITERATE_FLUSH(1);
2344 s_info |= S_02803C_ITERATE_FLUSH(1);
2345 }
2346
2347 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2348 /* Stencil buffer workaround ported from the SI-CI-VI code.
2349 * See that for explanation.
2350 */
2351 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2352 } else {
2353 /* Use all HTILE for depth if there's no stencil. */
2354 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2355 }
2356
2357 surf->db_htile_data_base = (rtex->resource.gpu_address +
2358 rtex->htile_offset) >> 8;
2359 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2360 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2361 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2362 }
2363 } else {
2364 /* SI-CI-VI */
2365 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2366
2367 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2368
2369 surf->db_depth_base = (rtex->resource.gpu_address +
2370 rtex->surface.u.legacy.level[level].offset) >> 8;
2371 surf->db_stencil_base = (rtex->resource.gpu_address +
2372 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2373
2374 z_info = S_028040_FORMAT(format) |
2375 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2376 s_info = S_028044_FORMAT(stencil_format);
2377 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2378
2379 if (sctx->b.chip_class >= CIK) {
2380 struct radeon_info *info = &sctx->screen->b.info;
2381 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2382 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2383 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2384 unsigned tile_mode = info->si_tile_mode_array[index];
2385 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2386 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2387
2388 surf->db_depth_info |=
2389 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2390 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2391 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2392 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2393 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2394 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2395 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2396 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2397 } else {
2398 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2399 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2400 tile_mode_index = si_tile_mode_index(rtex, level, true);
2401 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2402 }
2403
2404 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2405 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2406 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2407 levelinfo->nblk_y) / 64 - 1);
2408
2409 /* Only use HTILE for the first level. */
2410 if (rtex->htile_offset && !level) {
2411 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2412 S_028040_ALLOW_EXPCLEAR(1);
2413
2414 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2415 /* Workaround: For a not yet understood reason, the
2416 * combination of MSAA, fast stencil clear and stencil
2417 * decompress messes with subsequent stencil buffer
2418 * uses. Problem was reproduced on Verde, Bonaire,
2419 * Tonga, and Carrizo.
2420 *
2421 * Disabling EXPCLEAR works around the problem.
2422 *
2423 * Check piglit's arb_texture_multisample-stencil-clear
2424 * test if you want to try changing this.
2425 */
2426 if (rtex->resource.b.b.nr_samples <= 1)
2427 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2428 } else if (!rtex->tc_compatible_htile) {
2429 /* Use all of the htile_buffer for depth if there's no stencil.
2430 * This must not be set when TC-compatible HTILE is enabled
2431 * due to a hw bug.
2432 */
2433 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2434 }
2435
2436 surf->db_htile_data_base = (rtex->resource.gpu_address +
2437 rtex->htile_offset) >> 8;
2438 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2439
2440 if (rtex->tc_compatible_htile) {
2441 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2442
2443 if (rtex->resource.b.b.nr_samples <= 1)
2444 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2445 else if (rtex->resource.b.b.nr_samples <= 4)
2446 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2447 else
2448 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2449 }
2450 }
2451 }
2452
2453 surf->db_z_info = z_info;
2454 surf->db_stencil_info = s_info;
2455
2456 surf->depth_initialized = true;
2457 }
2458
2459 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2460 {
2461 if (sctx->decompression_enabled)
2462 return;
2463
2464 if (sctx->framebuffer.state.zsbuf) {
2465 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2466 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2467
2468 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2469
2470 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2471 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2472 }
2473 if (sctx->framebuffer.compressed_cb_mask) {
2474 struct pipe_surface *surf;
2475 struct r600_texture *rtex;
2476 unsigned mask = sctx->framebuffer.compressed_cb_mask;
2477
2478 do {
2479 unsigned i = u_bit_scan(&mask);
2480 surf = sctx->framebuffer.state.cbufs[i];
2481 rtex = (struct r600_texture*)surf->texture;
2482
2483 if (rtex->fmask.size)
2484 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2485 if (rtex->dcc_gather_statistics)
2486 rtex->separate_dcc_dirty = true;
2487 } while (mask);
2488 }
2489 }
2490
2491 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2492 {
2493 for (int i = 0; i < state->nr_cbufs; ++i) {
2494 struct r600_surface *surf = NULL;
2495 struct r600_texture *rtex;
2496
2497 if (!state->cbufs[i])
2498 continue;
2499 surf = (struct r600_surface*)state->cbufs[i];
2500 rtex = (struct r600_texture*)surf->base.texture;
2501
2502 p_atomic_dec(&rtex->framebuffers_bound);
2503 }
2504 }
2505
2506 static void si_set_framebuffer_state(struct pipe_context *ctx,
2507 const struct pipe_framebuffer_state *state)
2508 {
2509 struct si_context *sctx = (struct si_context *)ctx;
2510 struct pipe_constant_buffer constbuf = {0};
2511 struct r600_surface *surf = NULL;
2512 struct r600_texture *rtex;
2513 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2514 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2515 bool unbound = false;
2516 int i;
2517
2518 si_update_fb_dirtiness_after_rendering(sctx);
2519
2520 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2521 if (!sctx->framebuffer.state.cbufs[i])
2522 continue;
2523
2524 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2525 if (rtex->dcc_gather_statistics)
2526 vi_separate_dcc_stop_query(ctx, rtex);
2527 }
2528
2529 /* Disable DCC if the formats are incompatible. */
2530 for (i = 0; i < state->nr_cbufs; i++) {
2531 if (!state->cbufs[i])
2532 continue;
2533
2534 surf = (struct r600_surface*)state->cbufs[i];
2535 rtex = (struct r600_texture*)surf->base.texture;
2536
2537 if (!surf->dcc_incompatible)
2538 continue;
2539
2540 /* Since the DCC decompression calls back into set_framebuffer-
2541 * _state, we need to unbind the framebuffer, so that
2542 * vi_separate_dcc_stop_query isn't called twice with the same
2543 * color buffer.
2544 */
2545 if (!unbound) {
2546 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2547 unbound = true;
2548 }
2549
2550 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2551 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2552 sctx->b.decompress_dcc(ctx, rtex);
2553
2554 surf->dcc_incompatible = false;
2555 }
2556
2557 /* Only flush TC when changing the framebuffer state, because
2558 * the only client not using TC that can change textures is
2559 * the framebuffer.
2560 *
2561 * Wait for compute shaders because of possible transitions:
2562 * - FB write -> shader read
2563 * - shader write -> FB read
2564 *
2565 * DB caches are flushed on demand (using si_decompress_textures).
2566 *
2567 * When MSAA is enabled, CB and TC caches are flushed on demand
2568 * (after FMASK decompression). Shader write -> FB read transitions
2569 * cannot happen for MSAA textures, because MSAA shader images are
2570 * not supported.
2571 *
2572 * Only flush and wait for CB if there is actually a bound color buffer.
2573 */
2574 if (sctx->framebuffer.nr_samples <= 1 &&
2575 sctx->framebuffer.state.nr_cbufs) {
2576 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2577 SI_CONTEXT_INV_GLOBAL_L2 |
2578 SI_CONTEXT_FLUSH_AND_INV_CB;
2579 }
2580 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2581
2582 /* u_blitter doesn't invoke depth decompression when it does multiple
2583 * blits in a row, but the only case when it matters for DB is when
2584 * doing generate_mipmap. So here we flush DB manually between
2585 * individual generate_mipmap blits.
2586 * Note that lower mipmap levels aren't compressed.
2587 */
2588 if (sctx->generate_mipmap_for_depth) {
2589 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2590 SI_CONTEXT_INV_GLOBAL_L2 |
2591 SI_CONTEXT_FLUSH_AND_INV_DB;
2592 }
2593
2594 /* Take the maximum of the old and new count. If the new count is lower,
2595 * dirtying is needed to disable the unbound colorbuffers.
2596 */
2597 sctx->framebuffer.dirty_cbufs |=
2598 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2599 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2600
2601 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2602 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2603
2604 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2605 sctx->framebuffer.spi_shader_col_format = 0;
2606 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2607 sctx->framebuffer.spi_shader_col_format_blend = 0;
2608 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2609 sctx->framebuffer.color_is_int8 = 0;
2610 sctx->framebuffer.color_is_int10 = 0;
2611
2612 sctx->framebuffer.compressed_cb_mask = 0;
2613 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2614 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2615 sctx->framebuffer.any_dst_linear = false;
2616
2617 for (i = 0; i < state->nr_cbufs; i++) {
2618 if (!state->cbufs[i])
2619 continue;
2620
2621 surf = (struct r600_surface*)state->cbufs[i];
2622 rtex = (struct r600_texture*)surf->base.texture;
2623
2624 if (!surf->color_initialized) {
2625 si_initialize_color_surface(sctx, surf);
2626 }
2627
2628 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2629 sctx->framebuffer.spi_shader_col_format |=
2630 surf->spi_shader_col_format << (i * 4);
2631 sctx->framebuffer.spi_shader_col_format_alpha |=
2632 surf->spi_shader_col_format_alpha << (i * 4);
2633 sctx->framebuffer.spi_shader_col_format_blend |=
2634 surf->spi_shader_col_format_blend << (i * 4);
2635 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2636 surf->spi_shader_col_format_blend_alpha << (i * 4);
2637
2638 if (surf->color_is_int8)
2639 sctx->framebuffer.color_is_int8 |= 1 << i;
2640 if (surf->color_is_int10)
2641 sctx->framebuffer.color_is_int10 |= 1 << i;
2642
2643 if (rtex->fmask.size) {
2644 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2645 }
2646
2647 if (rtex->surface.is_linear)
2648 sctx->framebuffer.any_dst_linear = true;
2649
2650 r600_context_add_resource_size(ctx, surf->base.texture);
2651
2652 p_atomic_inc(&rtex->framebuffers_bound);
2653
2654 if (rtex->dcc_gather_statistics) {
2655 /* Dirty tracking must be enabled for DCC usage analysis. */
2656 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2657 vi_separate_dcc_start_query(ctx, rtex);
2658 }
2659 }
2660
2661 if (state->zsbuf) {
2662 surf = (struct r600_surface*)state->zsbuf;
2663 rtex = (struct r600_texture*)surf->base.texture;
2664
2665 if (!surf->depth_initialized) {
2666 si_init_depth_surface(sctx, surf);
2667 }
2668 r600_context_add_resource_size(ctx, surf->base.texture);
2669 }
2670
2671 si_update_poly_offset_state(sctx);
2672 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2673 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2674
2675 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2676 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2677
2678 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2679 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2680 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2681
2682 /* Set sample locations as fragment shader constants. */
2683 switch (sctx->framebuffer.nr_samples) {
2684 case 1:
2685 constbuf.user_buffer = sctx->b.sample_locations_1x;
2686 break;
2687 case 2:
2688 constbuf.user_buffer = sctx->b.sample_locations_2x;
2689 break;
2690 case 4:
2691 constbuf.user_buffer = sctx->b.sample_locations_4x;
2692 break;
2693 case 8:
2694 constbuf.user_buffer = sctx->b.sample_locations_8x;
2695 break;
2696 case 16:
2697 constbuf.user_buffer = sctx->b.sample_locations_16x;
2698 break;
2699 default:
2700 R600_ERR("Requested an invalid number of samples %i.\n",
2701 sctx->framebuffer.nr_samples);
2702 assert(0);
2703 }
2704 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2705 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2706
2707 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2708 }
2709
2710 sctx->do_update_shaders = true;
2711
2712 if (!sctx->decompression_enabled) {
2713 /* Prevent textures decompression when the framebuffer state
2714 * changes come from the decompression passes themselves.
2715 */
2716 sctx->need_check_render_feedback = true;
2717 }
2718 }
2719
2720 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2721 {
2722 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2723 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2724 unsigned i, nr_cbufs = state->nr_cbufs;
2725 struct r600_texture *tex = NULL;
2726 struct r600_surface *cb = NULL;
2727 unsigned cb_color_info = 0;
2728
2729 /* Colorbuffers. */
2730 for (i = 0; i < nr_cbufs; i++) {
2731 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2732 unsigned cb_color_attrib;
2733
2734 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2735 continue;
2736
2737 cb = (struct r600_surface*)state->cbufs[i];
2738 if (!cb) {
2739 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2740 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2741 continue;
2742 }
2743
2744 tex = (struct r600_texture *)cb->base.texture;
2745 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2746 &tex->resource, RADEON_USAGE_READWRITE,
2747 tex->resource.b.b.nr_samples > 1 ?
2748 RADEON_PRIO_COLOR_BUFFER_MSAA :
2749 RADEON_PRIO_COLOR_BUFFER);
2750
2751 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2752 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2753 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2754 RADEON_PRIO_CMASK);
2755 }
2756
2757 if (tex->dcc_separate_buffer)
2758 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2759 tex->dcc_separate_buffer,
2760 RADEON_USAGE_READWRITE,
2761 RADEON_PRIO_DCC);
2762
2763 /* Compute mutable surface parameters. */
2764 cb_color_base = tex->resource.gpu_address >> 8;
2765 cb_color_fmask = cb_color_base;
2766 cb_dcc_base = 0;
2767 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2768 cb_color_attrib = cb->cb_color_attrib;
2769
2770 if (tex->fmask.size)
2771 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2772
2773 /* Set up DCC. */
2774 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2775 bool is_msaa_resolve_dst = state->cbufs[0] &&
2776 state->cbufs[0]->texture->nr_samples > 1 &&
2777 state->cbufs[1] == &cb->base &&
2778 state->cbufs[1]->texture->nr_samples <= 1;
2779
2780 if (!is_msaa_resolve_dst)
2781 cb_color_info |= S_028C70_DCC_ENABLE(1);
2782
2783 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2784 tex->dcc_offset) >> 8;
2785 }
2786
2787 if (sctx->b.chip_class >= GFX9) {
2788 struct gfx9_surf_meta_flags meta;
2789
2790 if (tex->dcc_offset)
2791 meta = tex->surface.u.gfx9.dcc;
2792 else
2793 meta = tex->surface.u.gfx9.cmask;
2794
2795 /* Set mutable surface parameters. */
2796 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2797 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2798 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2799 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2800 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2801
2802 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2803 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2804 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2805 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2806 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2807 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2808 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2809 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2810 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2811 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2812 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2813 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2814 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2815 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2816 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2817 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2818
2819 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2820 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2821 } else {
2822 /* Compute mutable surface parameters (SI-CI-VI). */
2823 const struct legacy_surf_level *level_info =
2824 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2825 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2826 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2827
2828 cb_color_base += level_info->offset >> 8;
2829 if (cb_dcc_base)
2830 cb_dcc_base += level_info->dcc_offset >> 8;
2831
2832 pitch_tile_max = level_info->nblk_x / 8 - 1;
2833 slice_tile_max = level_info->nblk_x *
2834 level_info->nblk_y / 64 - 1;
2835 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2836
2837 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2838 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2839 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2840
2841 if (tex->fmask.size) {
2842 if (sctx->b.chip_class >= CIK)
2843 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2844 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2845 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2846 } else {
2847 /* This must be set for fast clear to work without FMASK. */
2848 if (sctx->b.chip_class >= CIK)
2849 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2850 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2851 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2852 }
2853
2854 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2855 sctx->b.chip_class >= VI ? 14 : 13);
2856 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2857 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2858 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2859 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2860 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2861 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2862 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2863 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2864 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2865 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2866 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2867 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2868 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2869
2870 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2871 radeon_emit(cs, cb_dcc_base);
2872 }
2873 }
2874 for (; i < 8 ; i++)
2875 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2876 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2877
2878 /* ZS buffer. */
2879 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2880 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2881 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2882
2883 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2884 &rtex->resource, RADEON_USAGE_READWRITE,
2885 zb->base.texture->nr_samples > 1 ?
2886 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2887 RADEON_PRIO_DEPTH_BUFFER);
2888
2889 if (sctx->b.chip_class >= GFX9) {
2890 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2891 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2892 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2893 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2894
2895 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2896 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2897 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2898 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2899 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2900 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2901 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2902 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2903 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2904 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2905 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2906 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2907
2908 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2909 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2910 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2911 } else {
2912 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2913
2914 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2915 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2916 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2917 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2918 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2919 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2920 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2921 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2922 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2923 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2924 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2925 }
2926
2927 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2928 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2929 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2930
2931 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2932 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2933 } else if (sctx->framebuffer.dirty_zsbuf) {
2934 if (sctx->b.chip_class >= GFX9)
2935 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2936 else
2937 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2938
2939 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2940 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2941 }
2942
2943 /* Framebuffer dimensions. */
2944 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2945 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2946 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2947
2948 if (sctx->b.chip_class >= GFX9) {
2949 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2950 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2951 }
2952
2953 sctx->framebuffer.dirty_cbufs = 0;
2954 sctx->framebuffer.dirty_zsbuf = false;
2955 }
2956
2957 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2958 struct r600_atom *atom)
2959 {
2960 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2961 unsigned nr_samples = sctx->framebuffer.nr_samples;
2962 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2963
2964 /* Smoothing (only possible with nr_samples == 1) uses the same
2965 * sample locations as the MSAA it simulates.
2966 */
2967 if (nr_samples <= 1 && sctx->smoothing_enabled)
2968 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2969
2970 /* On Polaris, the small primitive filter uses the sample locations
2971 * even when MSAA is off, so we need to make sure they're set to 0.
2972 */
2973 if (has_msaa_sample_loc_bug)
2974 nr_samples = MAX2(nr_samples, 1);
2975
2976 if (nr_samples >= 1 &&
2977 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2978 sctx->msaa_sample_locs.nr_samples = nr_samples;
2979 cayman_emit_msaa_sample_locs(cs, nr_samples);
2980 }
2981
2982 if (sctx->b.family >= CHIP_POLARIS10) {
2983 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2984 unsigned small_prim_filter_cntl =
2985 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2986 /* line bug */
2987 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2988
2989 /* The alternative of setting sample locations to 0 would
2990 * require a DB flush to avoid Z errors, see
2991 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2992 */
2993 if (has_msaa_sample_loc_bug &&
2994 sctx->framebuffer.nr_samples > 1 &&
2995 rs && !rs->multisample_enable)
2996 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2997
2998 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2999 small_prim_filter_cntl);
3000 }
3001 }
3002
3003 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3004 {
3005 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3006 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
3007 /* 33% faster rendering to linear color buffers */
3008 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3009 unsigned sc_mode_cntl_1 =
3010 S_028A4C_WALK_SIZE(dst_is_linear) |
3011 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3012 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3013 /* always 1: */
3014 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3015 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3016 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3017 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3018 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3019 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3020
3021 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
3022 sctx->ps_iter_samples,
3023 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
3024 sc_mode_cntl_1);
3025
3026 /* GFX9: Flush DFSM when the AA mode changes. */
3027 if (sctx->b.chip_class >= GFX9) {
3028 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3029 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3030 }
3031 }
3032
3033 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3034 {
3035 struct si_context *sctx = (struct si_context *)ctx;
3036
3037 if (sctx->ps_iter_samples == min_samples)
3038 return;
3039
3040 sctx->ps_iter_samples = min_samples;
3041 sctx->do_update_shaders = true;
3042
3043 if (sctx->framebuffer.nr_samples > 1)
3044 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3045 }
3046
3047 /*
3048 * Samplers
3049 */
3050
3051 /**
3052 * Build the sampler view descriptor for a buffer texture.
3053 * @param state 256-bit descriptor; only the high 128 bits are filled in
3054 */
3055 void
3056 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3057 enum pipe_format format,
3058 unsigned offset, unsigned size,
3059 uint32_t *state)
3060 {
3061 const struct util_format_description *desc;
3062 int first_non_void;
3063 unsigned stride;
3064 unsigned num_records;
3065 unsigned num_format, data_format;
3066
3067 desc = util_format_description(format);
3068 first_non_void = util_format_get_first_non_void_channel(format);
3069 stride = desc->block.bits / 8;
3070 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3071 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3072
3073 num_records = size / stride;
3074 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3075
3076 /* The NUM_RECORDS field has a different meaning depending on the chip,
3077 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3078 *
3079 * SI-CIK:
3080 * - If STRIDE == 0, it's in byte units.
3081 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3082 *
3083 * VI:
3084 * - For SMEM and STRIDE == 0, it's in byte units.
3085 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3086 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3087 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3088 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3089 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3090 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3091 * That way the same descriptor can be used by both SMEM and VMEM.
3092 *
3093 * GFX9:
3094 * - For SMEM and STRIDE == 0, it's in byte units.
3095 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3096 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3097 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3098 */
3099 if (screen->b.chip_class >= GFX9)
3100 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3101 * from STRIDE to bytes. This works around it by setting
3102 * NUM_RECORDS to at least the size of one element, so that
3103 * the first element is readable when IDXEN == 0.
3104 *
3105 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3106 * IDXEN is enforced?
3107 */
3108 num_records = num_records ? MAX2(num_records, stride) : 0;
3109 else if (screen->b.chip_class == VI)
3110 num_records *= stride;
3111
3112 state[4] = 0;
3113 state[5] = S_008F04_STRIDE(stride);
3114 state[6] = num_records;
3115 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3116 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3117 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3118 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3119 S_008F0C_NUM_FORMAT(num_format) |
3120 S_008F0C_DATA_FORMAT(data_format);
3121 }
3122
3123 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3124 {
3125 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3126
3127 if (swizzle[3] == PIPE_SWIZZLE_X) {
3128 /* For the pre-defined border color values (white, opaque
3129 * black, transparent black), the only thing that matters is
3130 * that the alpha channel winds up in the correct place
3131 * (because the RGB channels are all the same) so either of
3132 * these enumerations will work.
3133 */
3134 if (swizzle[2] == PIPE_SWIZZLE_Y)
3135 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3136 else
3137 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3138 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3139 if (swizzle[1] == PIPE_SWIZZLE_Y)
3140 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3141 else
3142 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3143 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3144 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3145 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3146 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3147 }
3148
3149 return bc_swizzle;
3150 }
3151
3152 /**
3153 * Build the sampler view descriptor for a texture.
3154 */
3155 void
3156 si_make_texture_descriptor(struct si_screen *screen,
3157 struct r600_texture *tex,
3158 bool sampler,
3159 enum pipe_texture_target target,
3160 enum pipe_format pipe_format,
3161 const unsigned char state_swizzle[4],
3162 unsigned first_level, unsigned last_level,
3163 unsigned first_layer, unsigned last_layer,
3164 unsigned width, unsigned height, unsigned depth,
3165 uint32_t *state,
3166 uint32_t *fmask_state)
3167 {
3168 struct pipe_resource *res = &tex->resource.b.b;
3169 const struct util_format_description *base_desc, *desc;
3170 unsigned char swizzle[4];
3171 int first_non_void;
3172 unsigned num_format, data_format, type;
3173 uint64_t va;
3174
3175 desc = util_format_description(pipe_format);
3176 base_desc = util_format_description(res->format);
3177
3178 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3179 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3180 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3181 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3182
3183 switch (pipe_format) {
3184 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3185 case PIPE_FORMAT_X32_S8X24_UINT:
3186 case PIPE_FORMAT_X8Z24_UNORM:
3187 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3188 break;
3189 case PIPE_FORMAT_X24S8_UINT:
3190 /*
3191 * X24S8 is implemented as an 8_8_8_8 data format, to
3192 * fix texture gathers. This affects at least
3193 * GL45-CTS.texture_cube_map_array.sampling on VI.
3194 */
3195 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3196 break;
3197 default:
3198 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3199 }
3200 } else {
3201 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3202 }
3203
3204 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3205
3206 switch (pipe_format) {
3207 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3208 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3209 break;
3210 default:
3211 if (first_non_void < 0) {
3212 if (util_format_is_compressed(pipe_format)) {
3213 switch (pipe_format) {
3214 case PIPE_FORMAT_DXT1_SRGB:
3215 case PIPE_FORMAT_DXT1_SRGBA:
3216 case PIPE_FORMAT_DXT3_SRGBA:
3217 case PIPE_FORMAT_DXT5_SRGBA:
3218 case PIPE_FORMAT_BPTC_SRGBA:
3219 case PIPE_FORMAT_ETC2_SRGB8:
3220 case PIPE_FORMAT_ETC2_SRGB8A1:
3221 case PIPE_FORMAT_ETC2_SRGBA8:
3222 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3223 break;
3224 case PIPE_FORMAT_RGTC1_SNORM:
3225 case PIPE_FORMAT_LATC1_SNORM:
3226 case PIPE_FORMAT_RGTC2_SNORM:
3227 case PIPE_FORMAT_LATC2_SNORM:
3228 case PIPE_FORMAT_ETC2_R11_SNORM:
3229 case PIPE_FORMAT_ETC2_RG11_SNORM:
3230 /* implies float, so use SNORM/UNORM to determine
3231 whether data is signed or not */
3232 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3233 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3234 break;
3235 default:
3236 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3237 break;
3238 }
3239 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3240 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3241 } else {
3242 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3243 }
3244 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3245 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3246 } else {
3247 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3248
3249 switch (desc->channel[first_non_void].type) {
3250 case UTIL_FORMAT_TYPE_FLOAT:
3251 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3252 break;
3253 case UTIL_FORMAT_TYPE_SIGNED:
3254 if (desc->channel[first_non_void].normalized)
3255 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3256 else if (desc->channel[first_non_void].pure_integer)
3257 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3258 else
3259 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3260 break;
3261 case UTIL_FORMAT_TYPE_UNSIGNED:
3262 if (desc->channel[first_non_void].normalized)
3263 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3264 else if (desc->channel[first_non_void].pure_integer)
3265 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3266 else
3267 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3268 }
3269 }
3270 }
3271
3272 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3273 if (data_format == ~0) {
3274 data_format = 0;
3275 }
3276
3277 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3278 if (screen->b.chip_class >= GFX9 &&
3279 util_format_has_depth(desc) &&
3280 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3281 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3282 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3283 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3284 }
3285
3286 /* S8 with Z32 HTILE needs a special format. */
3287 if (screen->b.chip_class >= GFX9 &&
3288 pipe_format == PIPE_FORMAT_S8_UINT &&
3289 tex->tc_compatible_htile)
3290 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3291
3292 if (!sampler &&
3293 (res->target == PIPE_TEXTURE_CUBE ||
3294 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3295 (screen->b.chip_class <= VI &&
3296 res->target == PIPE_TEXTURE_3D))) {
3297 /* For the purpose of shader images, treat cube maps and 3D
3298 * textures as 2D arrays. For 3D textures, the address
3299 * calculations for mipmaps are different, so we rely on the
3300 * caller to effectively disable mipmaps.
3301 */
3302 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3303
3304 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3305 } else {
3306 type = si_tex_dim(screen, tex, target, res->nr_samples);
3307 }
3308
3309 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3310 height = 1;
3311 depth = res->array_size;
3312 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3313 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3314 if (sampler || res->target != PIPE_TEXTURE_3D)
3315 depth = res->array_size;
3316 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3317 depth = res->array_size / 6;
3318
3319 state[0] = 0;
3320 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3321 S_008F14_NUM_FORMAT_GFX6(num_format));
3322 state[2] = (S_008F18_WIDTH(width - 1) |
3323 S_008F18_HEIGHT(height - 1) |
3324 S_008F18_PERF_MOD(4));
3325 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3326 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3327 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3328 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3329 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3330 0 : first_level) |
3331 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3332 util_logbase2(res->nr_samples) :
3333 last_level) |
3334 S_008F1C_TYPE(type));
3335 state[4] = 0;
3336 state[5] = S_008F24_BASE_ARRAY(first_layer);
3337 state[6] = 0;
3338 state[7] = 0;
3339
3340 if (screen->b.chip_class >= GFX9) {
3341 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3342
3343 /* Depth is the the last accessible layer on Gfx9.
3344 * The hw doesn't need to know the total number of layers.
3345 */
3346 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3347 state[4] |= S_008F20_DEPTH(depth - 1);
3348 else
3349 state[4] |= S_008F20_DEPTH(last_layer);
3350
3351 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3352 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3353 util_logbase2(res->nr_samples) :
3354 tex->resource.b.b.last_level);
3355 } else {
3356 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3357 state[4] |= S_008F20_DEPTH(depth - 1);
3358 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3359 }
3360
3361 if (tex->dcc_offset) {
3362 unsigned swap = r600_translate_colorswap(pipe_format, false);
3363
3364 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3365 } else {
3366 /* The last dword is unused by hw. The shader uses it to clear
3367 * bits in the first dword of sampler state.
3368 */
3369 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3370 if (first_level == last_level)
3371 state[7] = C_008F30_MAX_ANISO_RATIO;
3372 else
3373 state[7] = 0xffffffff;
3374 }
3375 }
3376
3377 /* Initialize the sampler view for FMASK. */
3378 if (tex->fmask.size) {
3379 uint32_t data_format, num_format;
3380
3381 va = tex->resource.gpu_address + tex->fmask.offset;
3382
3383 if (screen->b.chip_class >= GFX9) {
3384 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3385 switch (res->nr_samples) {
3386 case 2:
3387 num_format = V_008F14_IMG_FMASK_8_2_2;
3388 break;
3389 case 4:
3390 num_format = V_008F14_IMG_FMASK_8_4_4;
3391 break;
3392 case 8:
3393 num_format = V_008F14_IMG_FMASK_32_8_8;
3394 break;
3395 default:
3396 unreachable("invalid nr_samples");
3397 }
3398 } else {
3399 switch (res->nr_samples) {
3400 case 2:
3401 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3402 break;
3403 case 4:
3404 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3405 break;
3406 case 8:
3407 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3408 break;
3409 default:
3410 unreachable("invalid nr_samples");
3411 }
3412 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3413 }
3414
3415 fmask_state[0] = va >> 8;
3416 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3417 S_008F14_DATA_FORMAT_GFX6(data_format) |
3418 S_008F14_NUM_FORMAT_GFX6(num_format);
3419 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3420 S_008F18_HEIGHT(height - 1);
3421 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3422 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3423 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3424 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3425 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3426 fmask_state[4] = 0;
3427 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3428 fmask_state[6] = 0;
3429 fmask_state[7] = 0;
3430
3431 if (screen->b.chip_class >= GFX9) {
3432 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3433 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3434 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3435 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3436 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3437 } else {
3438 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3439 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3440 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3441 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3442 }
3443 }
3444 }
3445
3446 /**
3447 * Create a sampler view.
3448 *
3449 * @param ctx context
3450 * @param texture texture
3451 * @param state sampler view template
3452 * @param width0 width0 override (for compressed textures as int)
3453 * @param height0 height0 override (for compressed textures as int)
3454 * @param force_level set the base address to the level (for compressed textures)
3455 */
3456 struct pipe_sampler_view *
3457 si_create_sampler_view_custom(struct pipe_context *ctx,
3458 struct pipe_resource *texture,
3459 const struct pipe_sampler_view *state,
3460 unsigned width0, unsigned height0,
3461 unsigned force_level)
3462 {
3463 struct si_context *sctx = (struct si_context*)ctx;
3464 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3465 struct r600_texture *tmp = (struct r600_texture*)texture;
3466 unsigned base_level, first_level, last_level;
3467 unsigned char state_swizzle[4];
3468 unsigned height, depth, width;
3469 unsigned last_layer = state->u.tex.last_layer;
3470 enum pipe_format pipe_format;
3471 const struct legacy_surf_level *surflevel;
3472
3473 if (!view)
3474 return NULL;
3475
3476 /* initialize base object */
3477 view->base = *state;
3478 view->base.texture = NULL;
3479 view->base.reference.count = 1;
3480 view->base.context = ctx;
3481
3482 assert(texture);
3483 pipe_resource_reference(&view->base.texture, texture);
3484
3485 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3486 state->format == PIPE_FORMAT_S8X24_UINT ||
3487 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3488 state->format == PIPE_FORMAT_S8_UINT)
3489 view->is_stencil_sampler = true;
3490
3491 /* Buffer resource. */
3492 if (texture->target == PIPE_BUFFER) {
3493 si_make_buffer_descriptor(sctx->screen,
3494 (struct r600_resource *)texture,
3495 state->format,
3496 state->u.buf.offset,
3497 state->u.buf.size,
3498 view->state);
3499 return &view->base;
3500 }
3501
3502 state_swizzle[0] = state->swizzle_r;
3503 state_swizzle[1] = state->swizzle_g;
3504 state_swizzle[2] = state->swizzle_b;
3505 state_swizzle[3] = state->swizzle_a;
3506
3507 base_level = 0;
3508 first_level = state->u.tex.first_level;
3509 last_level = state->u.tex.last_level;
3510 width = width0;
3511 height = height0;
3512 depth = texture->depth0;
3513
3514 if (sctx->b.chip_class <= VI && force_level) {
3515 assert(force_level == first_level &&
3516 force_level == last_level);
3517 base_level = force_level;
3518 first_level = 0;
3519 last_level = 0;
3520 width = u_minify(width, force_level);
3521 height = u_minify(height, force_level);
3522 depth = u_minify(depth, force_level);
3523 }
3524
3525 /* This is not needed if state trackers set last_layer correctly. */
3526 if (state->target == PIPE_TEXTURE_1D ||
3527 state->target == PIPE_TEXTURE_2D ||
3528 state->target == PIPE_TEXTURE_RECT ||
3529 state->target == PIPE_TEXTURE_CUBE)
3530 last_layer = state->u.tex.first_layer;
3531
3532 /* Texturing with separate depth and stencil. */
3533 pipe_format = state->format;
3534
3535 /* Depth/stencil texturing sometimes needs separate texture. */
3536 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3537 if (!tmp->flushed_depth_texture &&
3538 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3539 pipe_resource_reference(&view->base.texture, NULL);
3540 FREE(view);
3541 return NULL;
3542 }
3543
3544 assert(tmp->flushed_depth_texture);
3545
3546 /* Override format for the case where the flushed texture
3547 * contains only Z or only S.
3548 */
3549 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3550 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3551
3552 tmp = tmp->flushed_depth_texture;
3553 }
3554
3555 surflevel = tmp->surface.u.legacy.level;
3556
3557 if (tmp->db_compatible) {
3558 if (!view->is_stencil_sampler)
3559 pipe_format = tmp->db_render_format;
3560
3561 switch (pipe_format) {
3562 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3563 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3564 break;
3565 case PIPE_FORMAT_X8Z24_UNORM:
3566 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3567 /* Z24 is always stored like this for DB
3568 * compatibility.
3569 */
3570 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3571 break;
3572 case PIPE_FORMAT_X24S8_UINT:
3573 case PIPE_FORMAT_S8X24_UINT:
3574 case PIPE_FORMAT_X32_S8X24_UINT:
3575 pipe_format = PIPE_FORMAT_S8_UINT;
3576 surflevel = tmp->surface.u.legacy.stencil_level;
3577 break;
3578 default:;
3579 }
3580 }
3581
3582 view->dcc_incompatible =
3583 vi_dcc_formats_are_incompatible(texture,
3584 state->u.tex.first_level,
3585 state->format);
3586
3587 si_make_texture_descriptor(sctx->screen, tmp, true,
3588 state->target, pipe_format, state_swizzle,
3589 first_level, last_level,
3590 state->u.tex.first_layer, last_layer,
3591 width, height, depth,
3592 view->state, view->fmask_state);
3593
3594 view->base_level_info = &surflevel[base_level];
3595 view->base_level = base_level;
3596 view->block_width = util_format_get_blockwidth(pipe_format);
3597 return &view->base;
3598 }
3599
3600 static struct pipe_sampler_view *
3601 si_create_sampler_view(struct pipe_context *ctx,
3602 struct pipe_resource *texture,
3603 const struct pipe_sampler_view *state)
3604 {
3605 return si_create_sampler_view_custom(ctx, texture, state,
3606 texture ? texture->width0 : 0,
3607 texture ? texture->height0 : 0, 0);
3608 }
3609
3610 static void si_sampler_view_destroy(struct pipe_context *ctx,
3611 struct pipe_sampler_view *state)
3612 {
3613 struct si_sampler_view *view = (struct si_sampler_view *)state;
3614
3615 pipe_resource_reference(&state->texture, NULL);
3616 FREE(view);
3617 }
3618
3619 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3620 {
3621 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3622 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3623 (linear_filter &&
3624 (wrap == PIPE_TEX_WRAP_CLAMP ||
3625 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3626 }
3627
3628 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3629 {
3630 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3631 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3632
3633 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3634 state->border_color.ui[2] || state->border_color.ui[3]) &&
3635 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3636 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3637 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3638 }
3639
3640 static void *si_create_sampler_state(struct pipe_context *ctx,
3641 const struct pipe_sampler_state *state)
3642 {
3643 struct si_context *sctx = (struct si_context *)ctx;
3644 struct r600_common_screen *rscreen = sctx->b.screen;
3645 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3646 unsigned border_color_type, border_color_index = 0;
3647 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3648 : state->max_anisotropy;
3649 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3650
3651 if (!rstate) {
3652 return NULL;
3653 }
3654
3655 if (!sampler_state_needs_border_color(state))
3656 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3657 else if (state->border_color.f[0] == 0 &&
3658 state->border_color.f[1] == 0 &&
3659 state->border_color.f[2] == 0 &&
3660 state->border_color.f[3] == 0)
3661 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3662 else if (state->border_color.f[0] == 0 &&
3663 state->border_color.f[1] == 0 &&
3664 state->border_color.f[2] == 0 &&
3665 state->border_color.f[3] == 1)
3666 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3667 else if (state->border_color.f[0] == 1 &&
3668 state->border_color.f[1] == 1 &&
3669 state->border_color.f[2] == 1 &&
3670 state->border_color.f[3] == 1)
3671 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3672 else {
3673 int i;
3674
3675 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3676
3677 /* Check if the border has been uploaded already. */
3678 for (i = 0; i < sctx->border_color_count; i++)
3679 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3680 sizeof(state->border_color)) == 0)
3681 break;
3682
3683 if (i >= SI_MAX_BORDER_COLORS) {
3684 /* Getting 4096 unique border colors is very unlikely. */
3685 fprintf(stderr, "radeonsi: The border color table is full. "
3686 "Any new border colors will be just black. "
3687 "Please file a bug.\n");
3688 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3689 } else {
3690 if (i == sctx->border_color_count) {
3691 /* Upload a new border color. */
3692 memcpy(&sctx->border_color_table[i], &state->border_color,
3693 sizeof(state->border_color));
3694 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3695 &state->border_color,
3696 sizeof(state->border_color));
3697 sctx->border_color_count++;
3698 }
3699
3700 border_color_index = i;
3701 }
3702 }
3703
3704 #ifdef DEBUG
3705 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3706 #endif
3707 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3708 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3709 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3710 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3711 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3712 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3713 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3714 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3715 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3716 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3717 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3718 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3719 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3720 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3721 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3722 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3723 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3724 S_008F38_MIP_POINT_PRECLAMP(1) |
3725 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3726 S_008F38_FILTER_PREC_FIX(1) |
3727 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3728 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3729 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3730 return rstate;
3731 }
3732
3733 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3734 {
3735 struct si_context *sctx = (struct si_context *)ctx;
3736
3737 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3738 return;
3739
3740 sctx->sample_mask.sample_mask = sample_mask;
3741 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3742 }
3743
3744 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3745 {
3746 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3747 unsigned mask = sctx->sample_mask.sample_mask;
3748
3749 /* Needed for line and polygon smoothing as well as for the Polaris
3750 * small primitive filter. We expect the state tracker to take care of
3751 * this for us.
3752 */
3753 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3754 (mask & 1 && sctx->blitter->running));
3755
3756 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3757 radeon_emit(cs, mask | (mask << 16));
3758 radeon_emit(cs, mask | (mask << 16));
3759 }
3760
3761 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3762 {
3763 #ifdef DEBUG
3764 struct si_sampler_state *s = state;
3765
3766 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3767 s->magic = 0;
3768 #endif
3769 free(state);
3770 }
3771
3772 /*
3773 * Vertex elements & buffers
3774 */
3775
3776 static void *si_create_vertex_elements(struct pipe_context *ctx,
3777 unsigned count,
3778 const struct pipe_vertex_element *elements)
3779 {
3780 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3781 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
3782 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3783 int i;
3784
3785 assert(count <= SI_MAX_ATTRIBS);
3786 if (!v)
3787 return NULL;
3788
3789 v->count = count;
3790 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3791
3792 for (i = 0; i < count; ++i) {
3793 const struct util_format_description *desc;
3794 const struct util_format_channel_description *channel;
3795 unsigned data_format, num_format;
3796 int first_non_void;
3797 unsigned vbo_index = elements[i].vertex_buffer_index;
3798 unsigned char swizzle[4];
3799
3800 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3801 FREE(v);
3802 return NULL;
3803 }
3804
3805 if (elements[i].instance_divisor) {
3806 v->uses_instance_divisors = true;
3807 v->instance_divisors[i] = elements[i].instance_divisor;
3808
3809 if (v->instance_divisors[i] == 1)
3810 v->instance_divisor_is_one |= 1u << i;
3811 else
3812 v->instance_divisor_is_fetched |= 1u << i;
3813 }
3814
3815 if (!used[vbo_index]) {
3816 v->first_vb_use_mask |= 1 << i;
3817 used[vbo_index] = true;
3818 }
3819
3820 desc = util_format_description(elements[i].src_format);
3821 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3822 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3823 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3824 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3825 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3826
3827 v->format_size[i] = desc->block.bits / 8;
3828 v->src_offset[i] = elements[i].src_offset;
3829 v->vertex_buffer_index[i] = vbo_index;
3830
3831 /* The hardware always treats the 2-bit alpha channel as
3832 * unsigned, so a shader workaround is needed. The affected
3833 * chips are VI and older except Stoney (GFX8.1).
3834 */
3835 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3836 sscreen->b.chip_class <= VI &&
3837 sscreen->b.family != CHIP_STONEY) {
3838 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3839 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3840 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3841 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3842 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3843 /* This isn't actually used in OpenGL. */
3844 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3845 }
3846 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3847 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3848 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3849 else
3850 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3851 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3852 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3853 if (channel->normalized) {
3854 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3855 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3856 else
3857 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3858 } else {
3859 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3860 }
3861 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3862 if (channel->normalized) {
3863 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3864 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3865 else
3866 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3867 } else {
3868 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3869 }
3870 }
3871 } else if (channel && channel->size == 64 &&
3872 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3873 switch (desc->nr_channels) {
3874 case 1:
3875 case 2:
3876 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3877 swizzle[0] = PIPE_SWIZZLE_X;
3878 swizzle[1] = PIPE_SWIZZLE_Y;
3879 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3880 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3881 break;
3882 case 3:
3883 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3884 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3885 swizzle[1] = PIPE_SWIZZLE_Y;
3886 swizzle[2] = PIPE_SWIZZLE_0;
3887 swizzle[3] = PIPE_SWIZZLE_0;
3888 break;
3889 case 4:
3890 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3891 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3892 swizzle[1] = PIPE_SWIZZLE_Y;
3893 swizzle[2] = PIPE_SWIZZLE_Z;
3894 swizzle[3] = PIPE_SWIZZLE_W;
3895 break;
3896 default:
3897 assert(0);
3898 }
3899 } else if (channel && desc->nr_channels == 3) {
3900 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3901
3902 if (channel->size == 8) {
3903 if (channel->pure_integer)
3904 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3905 else
3906 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3907 } else if (channel->size == 16) {
3908 if (channel->pure_integer)
3909 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3910 else
3911 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3912 }
3913 }
3914
3915 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3916 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3917 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3918 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3919 S_008F0C_NUM_FORMAT(num_format) |
3920 S_008F0C_DATA_FORMAT(data_format);
3921 }
3922 return v;
3923 }
3924
3925 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3926 {
3927 struct si_context *sctx = (struct si_context *)ctx;
3928 struct si_vertex_elements *old = sctx->vertex_elements;
3929 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
3930
3931 sctx->vertex_elements = v;
3932 sctx->vertex_buffers_dirty = true;
3933
3934 if (v &&
3935 (!old ||
3936 old->count != v->count ||
3937 old->uses_instance_divisors != v->uses_instance_divisors ||
3938 v->uses_instance_divisors || /* we don't check which divisors changed */
3939 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
3940 sctx->do_update_shaders = true;
3941
3942 if (v && v->instance_divisor_is_fetched) {
3943 struct pipe_constant_buffer cb;
3944
3945 cb.buffer = NULL;
3946 cb.user_buffer = v->instance_divisors;
3947 cb.buffer_offset = 0;
3948 cb.buffer_size = sizeof(uint32_t) * v->count;
3949 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
3950 }
3951 }
3952
3953 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3954 {
3955 struct si_context *sctx = (struct si_context *)ctx;
3956
3957 if (sctx->vertex_elements == state)
3958 sctx->vertex_elements = NULL;
3959 FREE(state);
3960 }
3961
3962 static void si_set_vertex_buffers(struct pipe_context *ctx,
3963 unsigned start_slot, unsigned count,
3964 const struct pipe_vertex_buffer *buffers)
3965 {
3966 struct si_context *sctx = (struct si_context *)ctx;
3967 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3968 int i;
3969
3970 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3971
3972 if (buffers) {
3973 for (i = 0; i < count; i++) {
3974 const struct pipe_vertex_buffer *src = buffers + i;
3975 struct pipe_vertex_buffer *dsti = dst + i;
3976 struct pipe_resource *buf = src->buffer.resource;
3977
3978 pipe_resource_reference(&dsti->buffer.resource, buf);
3979 dsti->buffer_offset = src->buffer_offset;
3980 dsti->stride = src->stride;
3981 r600_context_add_resource_size(ctx, buf);
3982 if (buf)
3983 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3984 }
3985 } else {
3986 for (i = 0; i < count; i++) {
3987 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3988 }
3989 }
3990 sctx->vertex_buffers_dirty = true;
3991 }
3992
3993 /*
3994 * Misc
3995 */
3996
3997 static void si_set_tess_state(struct pipe_context *ctx,
3998 const float default_outer_level[4],
3999 const float default_inner_level[2])
4000 {
4001 struct si_context *sctx = (struct si_context *)ctx;
4002 struct pipe_constant_buffer cb;
4003 float array[8];
4004
4005 memcpy(array, default_outer_level, sizeof(float) * 4);
4006 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4007
4008 cb.buffer = NULL;
4009 cb.user_buffer = NULL;
4010 cb.buffer_size = sizeof(array);
4011
4012 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4013 (void*)array, sizeof(array),
4014 &cb.buffer_offset);
4015
4016 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4017 pipe_resource_reference(&cb.buffer, NULL);
4018 }
4019
4020 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4021 {
4022 struct si_context *sctx = (struct si_context *)ctx;
4023
4024 si_update_fb_dirtiness_after_rendering(sctx);
4025
4026 /* Multisample surfaces are flushed in si_decompress_textures. */
4027 if (sctx->framebuffer.nr_samples <= 1 &&
4028 sctx->framebuffer.state.nr_cbufs) {
4029 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
4030 SI_CONTEXT_INV_GLOBAL_L2 |
4031 SI_CONTEXT_FLUSH_AND_INV_CB;
4032 }
4033 }
4034
4035 /* This only ensures coherency for shader image/buffer stores. */
4036 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4037 {
4038 struct si_context *sctx = (struct si_context *)ctx;
4039
4040 /* Subsequent commands must wait for all shader invocations to
4041 * complete. */
4042 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4043 SI_CONTEXT_CS_PARTIAL_FLUSH;
4044
4045 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4046 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4047 SI_CONTEXT_INV_VMEM_L1;
4048
4049 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4050 PIPE_BARRIER_SHADER_BUFFER |
4051 PIPE_BARRIER_TEXTURE |
4052 PIPE_BARRIER_IMAGE |
4053 PIPE_BARRIER_STREAMOUT_BUFFER |
4054 PIPE_BARRIER_GLOBAL_BUFFER)) {
4055 /* As far as I can tell, L1 contents are written back to L2
4056 * automatically at end of shader, but the contents of other
4057 * L1 caches might still be stale. */
4058 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4059 }
4060
4061 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4062 /* Indices are read through TC L2 since VI.
4063 * L1 isn't used.
4064 */
4065 if (sctx->screen->b.chip_class <= CIK)
4066 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4067 }
4068
4069 /* MSAA color, any depth and any stencil are flushed in
4070 * si_decompress_textures when needed.
4071 */
4072 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4073 sctx->framebuffer.nr_samples <= 1 &&
4074 sctx->framebuffer.state.nr_cbufs) {
4075 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
4076 SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4077 }
4078
4079 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4080 if (sctx->screen->b.chip_class <= VI &&
4081 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4082 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4083 }
4084
4085 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4086 {
4087 struct pipe_blend_state blend;
4088
4089 memset(&blend, 0, sizeof(blend));
4090 blend.independent_blend_enable = true;
4091 blend.rt[0].colormask = 0xf;
4092 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4093 }
4094
4095 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4096 bool include_draw_vbo)
4097 {
4098 si_need_cs_space((struct si_context*)ctx);
4099 }
4100
4101 static void si_init_config(struct si_context *sctx);
4102
4103 void si_init_state_functions(struct si_context *sctx)
4104 {
4105 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4106 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4107 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4108 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4109 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4110
4111 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4112 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4113 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4114 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4115 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4116 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4117 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4118 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4119 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4120 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4121
4122 sctx->b.b.create_blend_state = si_create_blend_state;
4123 sctx->b.b.bind_blend_state = si_bind_blend_state;
4124 sctx->b.b.delete_blend_state = si_delete_blend_state;
4125 sctx->b.b.set_blend_color = si_set_blend_color;
4126
4127 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4128 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4129 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4130
4131 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4132 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4133 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4134
4135 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4136 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4137 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4138 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4139 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4140
4141 sctx->b.b.set_clip_state = si_set_clip_state;
4142 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4143
4144 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4145 sctx->b.b.get_sample_position = cayman_get_sample_position;
4146
4147 sctx->b.b.create_sampler_state = si_create_sampler_state;
4148 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4149
4150 sctx->b.b.create_sampler_view = si_create_sampler_view;
4151 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4152
4153 sctx->b.b.set_sample_mask = si_set_sample_mask;
4154
4155 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4156 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4157 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4158 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4159
4160 sctx->b.b.texture_barrier = si_texture_barrier;
4161 sctx->b.b.memory_barrier = si_memory_barrier;
4162 sctx->b.b.set_min_samples = si_set_min_samples;
4163 sctx->b.b.set_tess_state = si_set_tess_state;
4164
4165 sctx->b.b.set_active_query_state = si_set_active_query_state;
4166 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4167 sctx->b.save_qbo_state = si_save_qbo_state;
4168 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4169
4170 sctx->b.b.draw_vbo = si_draw_vbo;
4171
4172 si_init_config(sctx);
4173 }
4174
4175 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4176 {
4177 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4178 }
4179
4180 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4181 struct r600_texture *rtex,
4182 struct radeon_bo_metadata *md)
4183 {
4184 struct si_screen *sscreen = (struct si_screen*)rscreen;
4185 struct pipe_resource *res = &rtex->resource.b.b;
4186 static const unsigned char swizzle[] = {
4187 PIPE_SWIZZLE_X,
4188 PIPE_SWIZZLE_Y,
4189 PIPE_SWIZZLE_Z,
4190 PIPE_SWIZZLE_W
4191 };
4192 uint32_t desc[8], i;
4193 bool is_array = util_resource_is_array_texture(res);
4194
4195 /* DRM 2.x.x doesn't support this. */
4196 if (rscreen->info.drm_major != 3)
4197 return;
4198
4199 assert(rtex->dcc_separate_buffer == NULL);
4200 assert(rtex->fmask.size == 0);
4201
4202 /* Metadata image format format version 1:
4203 * [0] = 1 (metadata format identifier)
4204 * [1] = (VENDOR_ID << 16) | PCI_ID
4205 * [2:9] = image descriptor for the whole resource
4206 * [2] is always 0, because the base address is cleared
4207 * [9] is the DCC offset bits [39:8] from the beginning of
4208 * the buffer
4209 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4210 */
4211
4212 md->metadata[0] = 1; /* metadata image format version 1 */
4213
4214 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4215 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4216
4217 si_make_texture_descriptor(sscreen, rtex, true,
4218 res->target, res->format,
4219 swizzle, 0, res->last_level, 0,
4220 is_array ? res->array_size - 1 : 0,
4221 res->width0, res->height0, res->depth0,
4222 desc, NULL);
4223
4224 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4225 0, 0, rtex->surface.blk_w, false, desc);
4226
4227 /* Clear the base address and set the relative DCC offset. */
4228 desc[0] = 0;
4229 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4230 desc[7] = rtex->dcc_offset >> 8;
4231
4232 /* Dwords [2:9] contain the image descriptor. */
4233 memcpy(&md->metadata[2], desc, sizeof(desc));
4234 md->size_metadata = 10 * 4;
4235
4236 /* Dwords [10:..] contain the mipmap level offsets. */
4237 if (rscreen->chip_class <= VI) {
4238 for (i = 0; i <= res->last_level; i++)
4239 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4240
4241 md->size_metadata += (1 + res->last_level) * 4;
4242 }
4243 }
4244
4245 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4246 struct r600_texture *rtex,
4247 struct radeon_bo_metadata *md)
4248 {
4249 uint32_t *desc = &md->metadata[2];
4250
4251 if (rscreen->chip_class < VI)
4252 return;
4253
4254 /* Return if DCC is enabled. The texture should be set up with it
4255 * already.
4256 */
4257 if (md->size_metadata >= 11 * 4 &&
4258 md->metadata[0] != 0 &&
4259 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4260 G_008F28_COMPRESSION_EN(desc[6])) {
4261 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4262 return;
4263 }
4264
4265 /* Disable DCC. These are always set by texture_from_handle and must
4266 * be cleared here.
4267 */
4268 rtex->dcc_offset = 0;
4269 }
4270
4271 void si_init_screen_state_functions(struct si_screen *sscreen)
4272 {
4273 sscreen->b.b.is_format_supported = si_is_format_supported;
4274 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4275 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4276 }
4277
4278 static void
4279 si_write_harvested_raster_configs(struct si_context *sctx,
4280 struct si_pm4_state *pm4,
4281 unsigned raster_config,
4282 unsigned raster_config_1)
4283 {
4284 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4285 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4286 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4287 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4288 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4289 unsigned rb_per_se = num_rb / num_se;
4290 unsigned se_mask[4];
4291 unsigned se;
4292
4293 se_mask[0] = ((1 << rb_per_se) - 1);
4294 se_mask[1] = (se_mask[0] << rb_per_se);
4295 se_mask[2] = (se_mask[1] << rb_per_se);
4296 se_mask[3] = (se_mask[2] << rb_per_se);
4297
4298 se_mask[0] &= rb_mask;
4299 se_mask[1] &= rb_mask;
4300 se_mask[2] &= rb_mask;
4301 se_mask[3] &= rb_mask;
4302
4303 assert(num_se == 1 || num_se == 2 || num_se == 4);
4304 assert(sh_per_se == 1 || sh_per_se == 2);
4305 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4306
4307 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4308 * fields are for, so I'm leaving them as their default
4309 * values. */
4310
4311 for (se = 0; se < num_se; se++) {
4312 unsigned raster_config_se = raster_config;
4313 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4314 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4315 int idx = (se / 2) * 2;
4316
4317 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4318 raster_config_se &= C_028350_SE_MAP;
4319
4320 if (!se_mask[idx]) {
4321 raster_config_se |=
4322 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4323 } else {
4324 raster_config_se |=
4325 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4326 }
4327 }
4328
4329 pkr0_mask &= rb_mask;
4330 pkr1_mask &= rb_mask;
4331 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4332 raster_config_se &= C_028350_PKR_MAP;
4333
4334 if (!pkr0_mask) {
4335 raster_config_se |=
4336 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4337 } else {
4338 raster_config_se |=
4339 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4340 }
4341 }
4342
4343 if (rb_per_se >= 2) {
4344 unsigned rb0_mask = 1 << (se * rb_per_se);
4345 unsigned rb1_mask = rb0_mask << 1;
4346
4347 rb0_mask &= rb_mask;
4348 rb1_mask &= rb_mask;
4349 if (!rb0_mask || !rb1_mask) {
4350 raster_config_se &= C_028350_RB_MAP_PKR0;
4351
4352 if (!rb0_mask) {
4353 raster_config_se |=
4354 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4355 } else {
4356 raster_config_se |=
4357 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4358 }
4359 }
4360
4361 if (rb_per_se > 2) {
4362 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4363 rb1_mask = rb0_mask << 1;
4364 rb0_mask &= rb_mask;
4365 rb1_mask &= rb_mask;
4366 if (!rb0_mask || !rb1_mask) {
4367 raster_config_se &= C_028350_RB_MAP_PKR1;
4368
4369 if (!rb0_mask) {
4370 raster_config_se |=
4371 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4372 } else {
4373 raster_config_se |=
4374 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4375 }
4376 }
4377 }
4378 }
4379
4380 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4381 if (sctx->b.chip_class < CIK)
4382 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4383 SE_INDEX(se) | SH_BROADCAST_WRITES |
4384 INSTANCE_BROADCAST_WRITES);
4385 else
4386 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4387 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4388 S_030800_INSTANCE_BROADCAST_WRITES(1));
4389 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4390 }
4391
4392 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4393 if (sctx->b.chip_class < CIK)
4394 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4395 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4396 INSTANCE_BROADCAST_WRITES);
4397 else {
4398 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4399 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4400 S_030800_INSTANCE_BROADCAST_WRITES(1));
4401
4402 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4403 (!se_mask[2] && !se_mask[3]))) {
4404 raster_config_1 &= C_028354_SE_PAIR_MAP;
4405
4406 if (!se_mask[0] && !se_mask[1]) {
4407 raster_config_1 |=
4408 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4409 } else {
4410 raster_config_1 |=
4411 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4412 }
4413 }
4414
4415 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4416 }
4417 }
4418
4419 static void si_init_config(struct si_context *sctx)
4420 {
4421 struct si_screen *sscreen = sctx->screen;
4422 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4423 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4424 unsigned raster_config, raster_config_1;
4425 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4426 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4427
4428 if (!pm4)
4429 return;
4430
4431 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4432 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4433 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4434 si_pm4_cmd_end(pm4, false);
4435
4436 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4437 si_pm4_cmd_add(pm4, 0);
4438 si_pm4_cmd_end(pm4, false);
4439
4440 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4441
4442 /* FIXME calculate these values somehow ??? */
4443 if (sctx->b.chip_class <= VI) {
4444 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4445 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4446 }
4447
4448 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4449 if (sctx->b.chip_class < CIK)
4450 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4451 S_008A14_CLIP_VTX_REORDER_ENA(1));
4452
4453 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4454 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4455
4456 switch (sctx->screen->b.family) {
4457 case CHIP_TAHITI:
4458 case CHIP_PITCAIRN:
4459 raster_config = 0x2a00126a;
4460 raster_config_1 = 0x00000000;
4461 break;
4462 case CHIP_VERDE:
4463 raster_config = 0x0000124a;
4464 raster_config_1 = 0x00000000;
4465 break;
4466 case CHIP_OLAND:
4467 raster_config = 0x00000082;
4468 raster_config_1 = 0x00000000;
4469 break;
4470 case CHIP_HAINAN:
4471 raster_config = 0x00000000;
4472 raster_config_1 = 0x00000000;
4473 break;
4474 case CHIP_BONAIRE:
4475 raster_config = 0x16000012;
4476 raster_config_1 = 0x00000000;
4477 break;
4478 case CHIP_HAWAII:
4479 raster_config = 0x3a00161a;
4480 raster_config_1 = 0x0000002e;
4481 break;
4482 case CHIP_FIJI:
4483 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4484 /* old kernels with old tiling config */
4485 raster_config = 0x16000012;
4486 raster_config_1 = 0x0000002a;
4487 } else {
4488 raster_config = 0x3a00161a;
4489 raster_config_1 = 0x0000002e;
4490 }
4491 break;
4492 case CHIP_POLARIS10:
4493 raster_config = 0x16000012;
4494 raster_config_1 = 0x0000002a;
4495 break;
4496 case CHIP_POLARIS11:
4497 case CHIP_POLARIS12:
4498 raster_config = 0x16000012;
4499 raster_config_1 = 0x00000000;
4500 break;
4501 case CHIP_TONGA:
4502 raster_config = 0x16000012;
4503 raster_config_1 = 0x0000002a;
4504 break;
4505 case CHIP_ICELAND:
4506 if (num_rb == 1)
4507 raster_config = 0x00000000;
4508 else
4509 raster_config = 0x00000002;
4510 raster_config_1 = 0x00000000;
4511 break;
4512 case CHIP_CARRIZO:
4513 raster_config = 0x00000002;
4514 raster_config_1 = 0x00000000;
4515 break;
4516 case CHIP_KAVERI:
4517 /* KV should be 0x00000002, but that causes problems with radeon */
4518 raster_config = 0x00000000; /* 0x00000002 */
4519 raster_config_1 = 0x00000000;
4520 break;
4521 case CHIP_KABINI:
4522 case CHIP_MULLINS:
4523 case CHIP_STONEY:
4524 raster_config = 0x00000000;
4525 raster_config_1 = 0x00000000;
4526 break;
4527 default:
4528 if (sctx->b.chip_class <= VI) {
4529 fprintf(stderr,
4530 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4531 raster_config = 0x00000000;
4532 raster_config_1 = 0x00000000;
4533 }
4534 break;
4535 }
4536
4537 if (sctx->b.chip_class <= VI) {
4538 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4539 /* Always use the default config when all backends are enabled
4540 * (or when we failed to determine the enabled backends).
4541 */
4542 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4543 raster_config);
4544 if (sctx->b.chip_class >= CIK)
4545 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4546 raster_config_1);
4547 } else {
4548 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4549 }
4550 }
4551
4552 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4553 * I don't know why. Deduced by trial and error.
4554 */
4555 if (sctx->b.chip_class <= CIK) {
4556 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4557 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4558 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4559 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4560 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4561 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4562 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4563 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4564 }
4565
4566 if (sctx->b.chip_class >= GFX9) {
4567 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4568 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4569 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4570 } else {
4571 /* These registers, when written, also overwrite the CLEAR_STATE
4572 * context, so we can't rely on CLEAR_STATE setting them.
4573 * It would be an issue if there was another UMD changing them.
4574 */
4575 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4576 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4577 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4578 }
4579
4580 if (sctx->b.chip_class >= CIK) {
4581 if (sctx->b.chip_class >= GFX9) {
4582 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4583 } else {
4584 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4585 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4586 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4587
4588 /* If this is 0, Bonaire can hang even if GS isn't being used.
4589 * Other chips are unaffected. These are suboptimal values,
4590 * but we don't use on-chip GS.
4591 */
4592 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4593 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4594 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4595 }
4596 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4597
4598 if (sscreen->b.info.num_good_compute_units /
4599 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4600 /* Too few available compute units per SH. Disallowing
4601 * VS to run on CU0 could hurt us more than late VS
4602 * allocation would help.
4603 *
4604 * LATE_ALLOC_VS = 2 is the highest safe number.
4605 */
4606 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4607 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4608 } else {
4609 /* Set LATE_ALLOC_VS == 31. It should be less than
4610 * the number of scratch waves. Limitations:
4611 * - VS can't execute on CU0.
4612 * - If HS writes outputs to LDS, LS can't execute on CU0.
4613 */
4614 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4615 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4616 }
4617
4618 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4619 }
4620
4621 if (sctx->b.chip_class >= VI) {
4622 unsigned vgt_tess_distribution;
4623
4624 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4625 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4626 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4627
4628 vgt_tess_distribution =
4629 S_028B50_ACCUM_ISOLINE(32) |
4630 S_028B50_ACCUM_TRI(11) |
4631 S_028B50_ACCUM_QUAD(11) |
4632 S_028B50_DONUT_SPLIT(16);
4633
4634 /* Testing with Unigine Heaven extreme tesselation yielded best results
4635 * with TRAP_SPLIT = 3.
4636 */
4637 if (sctx->b.family == CHIP_FIJI ||
4638 sctx->b.family >= CHIP_POLARIS10)
4639 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4640
4641 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4642 }
4643
4644 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4645 if (sctx->b.chip_class >= CIK)
4646 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4647 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4648 RADEON_PRIO_BORDER_COLORS);
4649
4650 if (sctx->b.chip_class >= GFX9) {
4651 unsigned num_se = sscreen->b.info.max_se;
4652 unsigned pc_lines = 0;
4653
4654 switch (sctx->b.family) {
4655 case CHIP_VEGA10:
4656 pc_lines = 4096;
4657 break;
4658 case CHIP_RAVEN:
4659 pc_lines = 1024;
4660 break;
4661 default:
4662 assert(0);
4663 }
4664
4665 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4666 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4667 /* TODO: Enable the binner: */
4668 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4669 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4670 S_028C44_DISABLE_START_OF_PRIM(1));
4671 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4672 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4673 S_028C48_MAX_PRIM_PER_BATCH(1023));
4674 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4675 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4676 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4677 }
4678
4679 si_pm4_upload_indirect_buffer(sctx, pm4);
4680 sctx->init_config = pm4;
4681 }