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radeonsi: switch radeon_add_to_buffer_list parameter to si_context
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28 #include "radeon/r600_query.h"
29
30 #include "util/u_dual_blend.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34 #include "util/u_resource.h"
35 #include "util/u_upload_mgr.h"
36
37 /* Initialize an external atom (owned by ../radeon). */
38 static void
39 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
40 struct r600_atom **list_elem)
41 {
42 atom->id = list_elem - sctx->atoms.array;
43 *list_elem = atom;
44 }
45
46 /* Initialize an atom owned by radeonsi. */
47 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
48 struct r600_atom **list_elem,
49 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
50 {
51 atom->emit = emit_func;
52 atom->id = list_elem - sctx->atoms.array;
53 *list_elem = atom;
54 }
55
56 static unsigned si_map_swizzle(unsigned swizzle)
57 {
58 switch (swizzle) {
59 case PIPE_SWIZZLE_Y:
60 return V_008F0C_SQ_SEL_Y;
61 case PIPE_SWIZZLE_Z:
62 return V_008F0C_SQ_SEL_Z;
63 case PIPE_SWIZZLE_W:
64 return V_008F0C_SQ_SEL_W;
65 case PIPE_SWIZZLE_0:
66 return V_008F0C_SQ_SEL_0;
67 case PIPE_SWIZZLE_1:
68 return V_008F0C_SQ_SEL_1;
69 default: /* PIPE_SWIZZLE_X */
70 return V_008F0C_SQ_SEL_X;
71 }
72 }
73
74 /* 12.4 fixed-point */
75 static unsigned si_pack_float_12p4(float x)
76 {
77 return x <= 0 ? 0 :
78 x >= 4096 ? 0xffff : x * 16;
79 }
80
81 /*
82 * Inferred framebuffer and blender state.
83 *
84 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
85 * if there is not enough PS outputs.
86 */
87 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
88 {
89 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
90 struct si_state_blend *blend = sctx->queued.named.blend;
91 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
92 * but you never know. */
93 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
94 unsigned i;
95
96 if (blend)
97 cb_target_mask &= blend->cb_target_mask;
98
99 /* Avoid a hang that happens when dual source blending is enabled
100 * but there is not enough color outputs. This is undefined behavior,
101 * so disable color writes completely.
102 *
103 * Reproducible with Unigine Heaven 4.0 and drirc missing.
104 */
105 if (blend && blend->dual_src_blend &&
106 sctx->ps_shader.cso &&
107 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
108 cb_target_mask = 0;
109
110 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
111
112 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
113 * I think we don't have to do anything between IBs.
114 */
115 if (sctx->screen->dfsm_allowed &&
116 sctx->last_cb_target_mask != cb_target_mask) {
117 sctx->last_cb_target_mask = cb_target_mask;
118
119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
120 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
121 }
122
123 if (sctx->b.chip_class >= VI) {
124 /* DCC MSAA workaround for blending.
125 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
126 * COMBINER_DISABLE, but that would be more complicated.
127 */
128 bool oc_disable = (sctx->b.chip_class == VI ||
129 sctx->b.chip_class == GFX9) &&
130 blend &&
131 blend->blend_enable_4bit & cb_target_mask &&
132 sctx->framebuffer.nr_samples >= 2;
133
134 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
135 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
136 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
137 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
138 }
139
140 /* RB+ register settings. */
141 if (sctx->screen->rbplus_allowed) {
142 unsigned spi_shader_col_format =
143 sctx->ps_shader.cso ?
144 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
145 unsigned sx_ps_downconvert = 0;
146 unsigned sx_blend_opt_epsilon = 0;
147 unsigned sx_blend_opt_control = 0;
148
149 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
150 struct r600_surface *surf =
151 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
152 unsigned format, swap, spi_format, colormask;
153 bool has_alpha, has_rgb;
154
155 if (!surf)
156 continue;
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
253 }
254 break;
255
256 case V_028C70_COLOR_2_10_10_10:
257 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
258 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
259 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
260 }
261 break;
262 }
263 }
264
265 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
266 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
267 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
268 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
269 } else if (sctx->screen->has_rbplus) {
270 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
271 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
272 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
273 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
274 }
275 }
276
277 /*
278 * Blender functions
279 */
280
281 static uint32_t si_translate_blend_function(int blend_func)
282 {
283 switch (blend_func) {
284 case PIPE_BLEND_ADD:
285 return V_028780_COMB_DST_PLUS_SRC;
286 case PIPE_BLEND_SUBTRACT:
287 return V_028780_COMB_SRC_MINUS_DST;
288 case PIPE_BLEND_REVERSE_SUBTRACT:
289 return V_028780_COMB_DST_MINUS_SRC;
290 case PIPE_BLEND_MIN:
291 return V_028780_COMB_MIN_DST_SRC;
292 case PIPE_BLEND_MAX:
293 return V_028780_COMB_MAX_DST_SRC;
294 default:
295 R600_ERR("Unknown blend function %d\n", blend_func);
296 assert(0);
297 break;
298 }
299 return 0;
300 }
301
302 static uint32_t si_translate_blend_factor(int blend_fact)
303 {
304 switch (blend_fact) {
305 case PIPE_BLENDFACTOR_ONE:
306 return V_028780_BLEND_ONE;
307 case PIPE_BLENDFACTOR_SRC_COLOR:
308 return V_028780_BLEND_SRC_COLOR;
309 case PIPE_BLENDFACTOR_SRC_ALPHA:
310 return V_028780_BLEND_SRC_ALPHA;
311 case PIPE_BLENDFACTOR_DST_ALPHA:
312 return V_028780_BLEND_DST_ALPHA;
313 case PIPE_BLENDFACTOR_DST_COLOR:
314 return V_028780_BLEND_DST_COLOR;
315 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
316 return V_028780_BLEND_SRC_ALPHA_SATURATE;
317 case PIPE_BLENDFACTOR_CONST_COLOR:
318 return V_028780_BLEND_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_CONST_ALPHA:
320 return V_028780_BLEND_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_ZERO:
322 return V_028780_BLEND_ZERO;
323 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
324 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
325 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
326 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
327 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_COLOR:
330 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
331 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
335 case PIPE_BLENDFACTOR_SRC1_COLOR:
336 return V_028780_BLEND_SRC1_COLOR;
337 case PIPE_BLENDFACTOR_SRC1_ALPHA:
338 return V_028780_BLEND_SRC1_ALPHA;
339 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
340 return V_028780_BLEND_INV_SRC1_COLOR;
341 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
342 return V_028780_BLEND_INV_SRC1_ALPHA;
343 default:
344 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
345 assert(0);
346 break;
347 }
348 return 0;
349 }
350
351 static uint32_t si_translate_blend_opt_function(int blend_func)
352 {
353 switch (blend_func) {
354 case PIPE_BLEND_ADD:
355 return V_028760_OPT_COMB_ADD;
356 case PIPE_BLEND_SUBTRACT:
357 return V_028760_OPT_COMB_SUBTRACT;
358 case PIPE_BLEND_REVERSE_SUBTRACT:
359 return V_028760_OPT_COMB_REVSUBTRACT;
360 case PIPE_BLEND_MIN:
361 return V_028760_OPT_COMB_MIN;
362 case PIPE_BLEND_MAX:
363 return V_028760_OPT_COMB_MAX;
364 default:
365 return V_028760_OPT_COMB_BLEND_DISABLED;
366 }
367 }
368
369 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
370 {
371 switch (blend_fact) {
372 case PIPE_BLENDFACTOR_ZERO:
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
374 case PIPE_BLENDFACTOR_ONE:
375 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
376 case PIPE_BLENDFACTOR_SRC_COLOR:
377 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
378 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
379 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
380 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
381 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
382 case PIPE_BLENDFACTOR_SRC_ALPHA:
383 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
384 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
386 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
387 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
388 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
389 default:
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
391 }
392 }
393
394 static void si_blend_check_commutativity(struct si_screen *sscreen,
395 struct si_state_blend *blend,
396 enum pipe_blend_func func,
397 enum pipe_blendfactor src,
398 enum pipe_blendfactor dst,
399 unsigned chanmask)
400 {
401 /* Src factor is allowed when it does not depend on Dst */
402 static const uint32_t src_allowed =
403 (1u << PIPE_BLENDFACTOR_ONE) |
404 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
405 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
406 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
407 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
408 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
409 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
410 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_ZERO) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
414 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
418
419 if (dst == PIPE_BLENDFACTOR_ONE &&
420 (src_allowed & (1u << src))) {
421 /* Addition is commutative, but floating point addition isn't
422 * associative: subtle changes can be introduced via different
423 * rounding.
424 *
425 * Out-of-order is also non-deterministic, which means that
426 * this breaks OpenGL invariance requirements. So only enable
427 * out-of-order additive blending if explicitly allowed by a
428 * setting.
429 */
430 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
431 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
432 blend->commutative_4bit |= chanmask;
433 }
434 }
435
436 /**
437 * Get rid of DST in the blend factors by commuting the operands:
438 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
439 */
440 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
441 unsigned *dst_factor, unsigned expected_dst,
442 unsigned replacement_src)
443 {
444 if (*src_factor == expected_dst &&
445 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
446 *src_factor = PIPE_BLENDFACTOR_ZERO;
447 *dst_factor = replacement_src;
448
449 /* Commuting the operands requires reversing subtractions. */
450 if (*func == PIPE_BLEND_SUBTRACT)
451 *func = PIPE_BLEND_REVERSE_SUBTRACT;
452 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
453 *func = PIPE_BLEND_SUBTRACT;
454 }
455 }
456
457 static bool si_blend_factor_uses_dst(unsigned factor)
458 {
459 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
460 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
461 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
462 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
464 }
465
466 static void *si_create_blend_state_mode(struct pipe_context *ctx,
467 const struct pipe_blend_state *state,
468 unsigned mode)
469 {
470 struct si_context *sctx = (struct si_context*)ctx;
471 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
472 struct si_pm4_state *pm4 = &blend->pm4;
473 uint32_t sx_mrt_blend_opt[8] = {0};
474 uint32_t color_control = 0;
475
476 if (!blend)
477 return NULL;
478
479 blend->alpha_to_coverage = state->alpha_to_coverage;
480 blend->alpha_to_one = state->alpha_to_one;
481 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
482 blend->logicop_enable = state->logicop_enable;
483
484 if (state->logicop_enable) {
485 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
486 } else {
487 color_control |= S_028808_ROP3(0xcc);
488 }
489
490 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
491 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
492 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
493 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
495 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
496
497 if (state->alpha_to_coverage)
498 blend->need_src_alpha_4bit |= 0xf;
499
500 blend->cb_target_mask = 0;
501 blend->cb_target_enabled_4bit = 0;
502
503 for (int i = 0; i < 8; i++) {
504 /* state->rt entries > 0 only written if independent blending */
505 const int j = state->independent_blend_enable ? i : 0;
506
507 unsigned eqRGB = state->rt[j].rgb_func;
508 unsigned srcRGB = state->rt[j].rgb_src_factor;
509 unsigned dstRGB = state->rt[j].rgb_dst_factor;
510 unsigned eqA = state->rt[j].alpha_func;
511 unsigned srcA = state->rt[j].alpha_src_factor;
512 unsigned dstA = state->rt[j].alpha_dst_factor;
513
514 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
515 unsigned blend_cntl = 0;
516
517 sx_mrt_blend_opt[i] =
518 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
519 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
520
521 /* Only set dual source blending for MRT0 to avoid a hang. */
522 if (i >= 1 && blend->dual_src_blend) {
523 /* Vulkan does this for dual source blending. */
524 if (i == 1)
525 blend_cntl |= S_028780_ENABLE(1);
526
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 /* Only addition and subtraction equations are supported with
532 * dual source blending.
533 */
534 if (blend->dual_src_blend &&
535 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
536 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
537 assert(!"Unsupported equation for dual source blending");
538 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
539 continue;
540 }
541
542 /* cb_render_state will disable unused ones */
543 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
544 if (state->rt[j].colormask)
545 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
546
547 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
548 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
549 continue;
550 }
551
552 si_blend_check_commutativity(sctx->screen, blend,
553 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
554 si_blend_check_commutativity(sctx->screen, blend,
555 eqA, srcA, dstA, 0x8 << (4 * i));
556
557 /* Blending optimizations for RB+.
558 * These transformations don't change the behavior.
559 *
560 * First, get rid of DST in the blend factors:
561 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
562 */
563 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
564 PIPE_BLENDFACTOR_DST_COLOR,
565 PIPE_BLENDFACTOR_SRC_COLOR);
566 si_blend_remove_dst(&eqA, &srcA, &dstA,
567 PIPE_BLENDFACTOR_DST_COLOR,
568 PIPE_BLENDFACTOR_SRC_COLOR);
569 si_blend_remove_dst(&eqA, &srcA, &dstA,
570 PIPE_BLENDFACTOR_DST_ALPHA,
571 PIPE_BLENDFACTOR_SRC_ALPHA);
572
573 /* Look up the ideal settings from tables. */
574 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
575 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
576 srcA_opt = si_translate_blend_opt_factor(srcA, true);
577 dstA_opt = si_translate_blend_opt_factor(dstA, true);
578
579 /* Handle interdependencies. */
580 if (si_blend_factor_uses_dst(srcRGB))
581 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
582 if (si_blend_factor_uses_dst(srcA))
583 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
584
585 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
586 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
587 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
588 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
589 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
590
591 /* Set the final value. */
592 sx_mrt_blend_opt[i] =
593 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
594 S_028760_COLOR_DST_OPT(dstRGB_opt) |
595 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
596 S_028760_ALPHA_SRC_OPT(srcA_opt) |
597 S_028760_ALPHA_DST_OPT(dstA_opt) |
598 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
599
600 /* Set blend state. */
601 blend_cntl |= S_028780_ENABLE(1);
602 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
603 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
604 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
605
606 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
607 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
608 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
609 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
610 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
611 }
612 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
613
614 blend->blend_enable_4bit |= 0xfu << (i * 4);
615
616 /* This is only important for formats without alpha. */
617 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
618 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
619 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
620 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
621 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
622 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
623 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
624 }
625
626 if (blend->cb_target_mask) {
627 color_control |= S_028808_MODE(mode);
628 } else {
629 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
630 }
631
632 if (sctx->screen->has_rbplus) {
633 /* Disable RB+ blend optimizations for dual source blending.
634 * Vulkan does this.
635 */
636 if (blend->dual_src_blend) {
637 for (int i = 0; i < 8; i++) {
638 sx_mrt_blend_opt[i] =
639 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
640 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
641 }
642 }
643
644 for (int i = 0; i < 8; i++)
645 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
646 sx_mrt_blend_opt[i]);
647
648 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
649 if (blend->dual_src_blend || state->logicop_enable ||
650 mode == V_028808_CB_RESOLVE)
651 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
652 }
653
654 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
655 return blend;
656 }
657
658 static void *si_create_blend_state(struct pipe_context *ctx,
659 const struct pipe_blend_state *state)
660 {
661 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
662 }
663
664 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
665 {
666 struct si_context *sctx = (struct si_context *)ctx;
667 struct si_state_blend *old_blend = sctx->queued.named.blend;
668 struct si_state_blend *blend = (struct si_state_blend *)state;
669
670 if (!state)
671 return;
672
673 si_pm4_bind_state(sctx, blend, state);
674
675 if (!old_blend ||
676 old_blend->cb_target_mask != blend->cb_target_mask ||
677 old_blend->dual_src_blend != blend->dual_src_blend ||
678 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
679 sctx->framebuffer.nr_samples >= 2 &&
680 sctx->screen->dcc_msaa_allowed))
681 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
682
683 if (!old_blend ||
684 old_blend->cb_target_mask != blend->cb_target_mask ||
685 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
686 old_blend->alpha_to_one != blend->alpha_to_one ||
687 old_blend->dual_src_blend != blend->dual_src_blend ||
688 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
689 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
690 sctx->do_update_shaders = true;
691
692 if (sctx->screen->dpbb_allowed &&
693 (!old_blend ||
694 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
695 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
696 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
697 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
698
699 if (sctx->screen->has_out_of_order_rast &&
700 (!old_blend ||
701 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
702 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
703 old_blend->commutative_4bit != blend->commutative_4bit ||
704 old_blend->logicop_enable != blend->logicop_enable)))
705 si_mark_atom_dirty(sctx, &sctx->msaa_config);
706 }
707
708 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
709 {
710 struct si_context *sctx = (struct si_context *)ctx;
711 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
712 }
713
714 static void si_set_blend_color(struct pipe_context *ctx,
715 const struct pipe_blend_color *state)
716 {
717 struct si_context *sctx = (struct si_context *)ctx;
718 static const struct pipe_blend_color zeros;
719
720 sctx->blend_color.state = *state;
721 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
722 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
723 }
724
725 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
726 {
727 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
728
729 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
730 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
731 }
732
733 /*
734 * Clipping
735 */
736
737 static void si_set_clip_state(struct pipe_context *ctx,
738 const struct pipe_clip_state *state)
739 {
740 struct si_context *sctx = (struct si_context *)ctx;
741 struct pipe_constant_buffer cb;
742 static const struct pipe_clip_state zeros;
743
744 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
745 return;
746
747 sctx->clip_state.state = *state;
748 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
749 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
750
751 cb.buffer = NULL;
752 cb.user_buffer = state->ucp;
753 cb.buffer_offset = 0;
754 cb.buffer_size = 4*4*8;
755 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
756 pipe_resource_reference(&cb.buffer, NULL);
757 }
758
759 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
760 {
761 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
762
763 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
764 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
765 }
766
767 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
768 {
769 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
770 struct si_shader *vs = si_get_vs_state(sctx);
771 struct si_shader_selector *vs_sel = vs->selector;
772 struct tgsi_shader_info *info = &vs_sel->info;
773 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
774 unsigned window_space =
775 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
776 unsigned clipdist_mask = vs_sel->clipdist_mask;
777 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
778 unsigned culldist_mask = vs_sel->culldist_mask;
779 unsigned total_mask;
780
781 if (vs->key.opt.clip_disable) {
782 assert(!info->culldist_writemask);
783 clipdist_mask = 0;
784 culldist_mask = 0;
785 }
786 total_mask = clipdist_mask | culldist_mask;
787
788 /* Clip distances on points have no effect, so need to be implemented
789 * as cull distances. This applies for the clipvertex case as well.
790 *
791 * Setting this for primitives other than points should have no adverse
792 * effects.
793 */
794 clipdist_mask &= rs->clip_plane_enable;
795 culldist_mask |= clipdist_mask;
796
797 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
798 vs_sel->pa_cl_vs_out_cntl |
799 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
800 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
801 clipdist_mask | (culldist_mask << 8));
802 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
803 rs->pa_cl_clip_cntl |
804 ucp_mask |
805 S_028810_CLIP_DISABLE(window_space));
806 }
807
808 /*
809 * inferred state between framebuffer and rasterizer
810 */
811 static void si_update_poly_offset_state(struct si_context *sctx)
812 {
813 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
814
815 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
816 si_pm4_bind_state(sctx, poly_offset, NULL);
817 return;
818 }
819
820 /* Use the user format, not db_render_format, so that the polygon
821 * offset behaves as expected by applications.
822 */
823 switch (sctx->framebuffer.state.zsbuf->texture->format) {
824 case PIPE_FORMAT_Z16_UNORM:
825 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
826 break;
827 default: /* 24-bit */
828 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
829 break;
830 case PIPE_FORMAT_Z32_FLOAT:
831 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
832 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
833 break;
834 }
835 }
836
837 /*
838 * Rasterizer
839 */
840
841 static uint32_t si_translate_fill(uint32_t func)
842 {
843 switch(func) {
844 case PIPE_POLYGON_MODE_FILL:
845 return V_028814_X_DRAW_TRIANGLES;
846 case PIPE_POLYGON_MODE_LINE:
847 return V_028814_X_DRAW_LINES;
848 case PIPE_POLYGON_MODE_POINT:
849 return V_028814_X_DRAW_POINTS;
850 default:
851 assert(0);
852 return V_028814_X_DRAW_POINTS;
853 }
854 }
855
856 static void *si_create_rs_state(struct pipe_context *ctx,
857 const struct pipe_rasterizer_state *state)
858 {
859 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
860 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
861 struct si_pm4_state *pm4 = &rs->pm4;
862 unsigned tmp, i;
863 float psize_min, psize_max;
864
865 if (!rs) {
866 return NULL;
867 }
868
869 rs->scissor_enable = state->scissor;
870 rs->clip_halfz = state->clip_halfz;
871 rs->two_side = state->light_twoside;
872 rs->multisample_enable = state->multisample;
873 rs->force_persample_interp = state->force_persample_interp;
874 rs->clip_plane_enable = state->clip_plane_enable;
875 rs->line_stipple_enable = state->line_stipple_enable;
876 rs->poly_stipple_enable = state->poly_stipple_enable;
877 rs->line_smooth = state->line_smooth;
878 rs->line_width = state->line_width;
879 rs->poly_smooth = state->poly_smooth;
880 rs->uses_poly_offset = state->offset_point || state->offset_line ||
881 state->offset_tri;
882 rs->clamp_fragment_color = state->clamp_fragment_color;
883 rs->clamp_vertex_color = state->clamp_vertex_color;
884 rs->flatshade = state->flatshade;
885 rs->sprite_coord_enable = state->sprite_coord_enable;
886 rs->rasterizer_discard = state->rasterizer_discard;
887 rs->pa_sc_line_stipple = state->line_stipple_enable ?
888 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
889 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
890 rs->pa_cl_clip_cntl =
891 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
892 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
893 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
894 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
895 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
896
897 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
898 S_0286D4_FLAT_SHADE_ENA(1) |
899 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
900 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
901 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
902 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
903 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
904 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
905
906 /* point size 12.4 fixed point */
907 tmp = (unsigned)(state->point_size * 8.0);
908 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
909
910 if (state->point_size_per_vertex) {
911 psize_min = util_get_min_point_size(state);
912 psize_max = 8192;
913 } else {
914 /* Force the point size to be as if the vertex output was disabled. */
915 psize_min = state->point_size;
916 psize_max = state->point_size;
917 }
918 rs->max_point_size = psize_max;
919
920 /* Divide by two, because 0.5 = 1 pixel. */
921 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
922 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
923 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
924
925 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
926 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
927 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
928 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
929 S_028A48_MSAA_ENABLE(state->multisample ||
930 state->poly_smooth ||
931 state->line_smooth) |
932 S_028A48_VPORT_SCISSOR_ENABLE(1) |
933 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
934
935 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
936 S_028BE4_PIX_CENTER(state->half_pixel_center) |
937 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
938
939 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
940 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
941 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
942 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
943 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
944 S_028814_FACE(!state->front_ccw) |
945 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
946 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
947 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
948 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
949 state->fill_back != PIPE_POLYGON_MODE_FILL) |
950 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
951 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
952
953 if (!rs->uses_poly_offset)
954 return rs;
955
956 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
957 if (!rs->pm4_poly_offset) {
958 FREE(rs);
959 return NULL;
960 }
961
962 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
963 for (i = 0; i < 3; i++) {
964 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
965 float offset_units = state->offset_units;
966 float offset_scale = state->offset_scale * 16.0f;
967 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
968
969 if (!state->offset_units_unscaled) {
970 switch (i) {
971 case 0: /* 16-bit zbuffer */
972 offset_units *= 4.0f;
973 pa_su_poly_offset_db_fmt_cntl =
974 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
975 break;
976 case 1: /* 24-bit zbuffer */
977 offset_units *= 2.0f;
978 pa_su_poly_offset_db_fmt_cntl =
979 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
980 break;
981 case 2: /* 32-bit zbuffer */
982 offset_units *= 1.0f;
983 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
984 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
985 break;
986 }
987 }
988
989 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
990 fui(offset_scale));
991 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
992 fui(offset_units));
993 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
994 fui(offset_scale));
995 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
996 fui(offset_units));
997 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
998 pa_su_poly_offset_db_fmt_cntl);
999 }
1000
1001 return rs;
1002 }
1003
1004 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1005 {
1006 struct si_context *sctx = (struct si_context *)ctx;
1007 struct si_state_rasterizer *old_rs =
1008 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1009 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1010
1011 if (!state)
1012 return;
1013
1014 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1015 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1016
1017 /* Update the small primitive filter workaround if necessary. */
1018 if (sctx->screen->has_msaa_sample_loc_bug &&
1019 sctx->framebuffer.nr_samples > 1)
1020 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1021 }
1022
1023 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1024 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1025
1026 si_pm4_bind_state(sctx, rasterizer, rs);
1027 si_update_poly_offset_state(sctx);
1028
1029 if (!old_rs ||
1030 (old_rs->scissor_enable != rs->scissor_enable ||
1031 old_rs->line_width != rs->line_width ||
1032 old_rs->max_point_size != rs->max_point_size)) {
1033 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1034 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1035 }
1036
1037 if (!old_rs ||
1038 old_rs->clip_halfz != rs->clip_halfz) {
1039 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1040 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1041 }
1042
1043 if (!old_rs ||
1044 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1045 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1046 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1047
1048 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1049 rs->line_stipple_enable;
1050
1051 if (!old_rs ||
1052 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1053 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1054 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1055 old_rs->flatshade != rs->flatshade ||
1056 old_rs->two_side != rs->two_side ||
1057 old_rs->multisample_enable != rs->multisample_enable ||
1058 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1059 old_rs->poly_smooth != rs->poly_smooth ||
1060 old_rs->line_smooth != rs->line_smooth ||
1061 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1062 old_rs->force_persample_interp != rs->force_persample_interp)
1063 sctx->do_update_shaders = true;
1064 }
1065
1066 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1067 {
1068 struct si_context *sctx = (struct si_context *)ctx;
1069 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1070
1071 if (sctx->queued.named.rasterizer == state)
1072 si_pm4_bind_state(sctx, poly_offset, NULL);
1073
1074 FREE(rs->pm4_poly_offset);
1075 si_pm4_delete_state(sctx, rasterizer, rs);
1076 }
1077
1078 /*
1079 * infeered state between dsa and stencil ref
1080 */
1081 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1082 {
1083 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
1084 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1085 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1086
1087 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1088 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1089 S_028430_STENCILMASK(dsa->valuemask[0]) |
1090 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1091 S_028430_STENCILOPVAL(1));
1092 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1093 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1094 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1095 S_028434_STENCILOPVAL_BF(1));
1096 }
1097
1098 static void si_set_stencil_ref(struct pipe_context *ctx,
1099 const struct pipe_stencil_ref *state)
1100 {
1101 struct si_context *sctx = (struct si_context *)ctx;
1102
1103 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1104 return;
1105
1106 sctx->stencil_ref.state = *state;
1107 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1108 }
1109
1110
1111 /*
1112 * DSA
1113 */
1114
1115 static uint32_t si_translate_stencil_op(int s_op)
1116 {
1117 switch (s_op) {
1118 case PIPE_STENCIL_OP_KEEP:
1119 return V_02842C_STENCIL_KEEP;
1120 case PIPE_STENCIL_OP_ZERO:
1121 return V_02842C_STENCIL_ZERO;
1122 case PIPE_STENCIL_OP_REPLACE:
1123 return V_02842C_STENCIL_REPLACE_TEST;
1124 case PIPE_STENCIL_OP_INCR:
1125 return V_02842C_STENCIL_ADD_CLAMP;
1126 case PIPE_STENCIL_OP_DECR:
1127 return V_02842C_STENCIL_SUB_CLAMP;
1128 case PIPE_STENCIL_OP_INCR_WRAP:
1129 return V_02842C_STENCIL_ADD_WRAP;
1130 case PIPE_STENCIL_OP_DECR_WRAP:
1131 return V_02842C_STENCIL_SUB_WRAP;
1132 case PIPE_STENCIL_OP_INVERT:
1133 return V_02842C_STENCIL_INVERT;
1134 default:
1135 R600_ERR("Unknown stencil op %d", s_op);
1136 assert(0);
1137 break;
1138 }
1139 return 0;
1140 }
1141
1142 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1143 {
1144 return s->enabled && s->writemask &&
1145 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1146 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1147 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1148 }
1149
1150 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1151 {
1152 /* REPLACE is normally order invariant, except when the stencil
1153 * reference value is written by the fragment shader. Tracking this
1154 * interaction does not seem worth the effort, so be conservative. */
1155 return op != PIPE_STENCIL_OP_INCR &&
1156 op != PIPE_STENCIL_OP_DECR &&
1157 op != PIPE_STENCIL_OP_REPLACE;
1158 }
1159
1160 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1161 * invariant in the sense that the set of passing fragments as well as the
1162 * final stencil buffer result does not depend on the order of fragments. */
1163 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1164 {
1165 return !state->enabled || !state->writemask ||
1166 /* The following assumes that Z writes are disabled. */
1167 (state->func == PIPE_FUNC_ALWAYS &&
1168 si_order_invariant_stencil_op(state->zpass_op) &&
1169 si_order_invariant_stencil_op(state->zfail_op)) ||
1170 (state->func == PIPE_FUNC_NEVER &&
1171 si_order_invariant_stencil_op(state->fail_op));
1172 }
1173
1174 static void *si_create_dsa_state(struct pipe_context *ctx,
1175 const struct pipe_depth_stencil_alpha_state *state)
1176 {
1177 struct si_context *sctx = (struct si_context *)ctx;
1178 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1179 struct si_pm4_state *pm4 = &dsa->pm4;
1180 unsigned db_depth_control;
1181 uint32_t db_stencil_control = 0;
1182
1183 if (!dsa) {
1184 return NULL;
1185 }
1186
1187 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1188 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1189 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1190 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1191
1192 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1193 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1194 S_028800_ZFUNC(state->depth.func) |
1195 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1196
1197 /* stencil */
1198 if (state->stencil[0].enabled) {
1199 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1200 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1201 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1202 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1203 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1204
1205 if (state->stencil[1].enabled) {
1206 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1207 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1208 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1209 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1210 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1211 }
1212 }
1213
1214 /* alpha */
1215 if (state->alpha.enabled) {
1216 dsa->alpha_func = state->alpha.func;
1217
1218 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1219 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1220 } else {
1221 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1222 }
1223
1224 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1225 if (state->stencil[0].enabled)
1226 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1227 if (state->depth.bounds_test) {
1228 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1229 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1230 }
1231
1232 dsa->depth_enabled = state->depth.enabled;
1233 dsa->depth_write_enabled = state->depth.enabled &&
1234 state->depth.writemask;
1235 dsa->stencil_enabled = state->stencil[0].enabled;
1236 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1237 (si_dsa_writes_stencil(&state->stencil[0]) ||
1238 si_dsa_writes_stencil(&state->stencil[1]));
1239 dsa->db_can_write = dsa->depth_write_enabled ||
1240 dsa->stencil_write_enabled;
1241
1242 bool zfunc_is_ordered =
1243 state->depth.func == PIPE_FUNC_NEVER ||
1244 state->depth.func == PIPE_FUNC_LESS ||
1245 state->depth.func == PIPE_FUNC_LEQUAL ||
1246 state->depth.func == PIPE_FUNC_GREATER ||
1247 state->depth.func == PIPE_FUNC_GEQUAL;
1248
1249 bool nozwrite_and_order_invariant_stencil =
1250 !dsa->db_can_write ||
1251 (!dsa->depth_write_enabled &&
1252 si_order_invariant_stencil_state(&state->stencil[0]) &&
1253 si_order_invariant_stencil_state(&state->stencil[1]));
1254
1255 dsa->order_invariance[1].zs =
1256 nozwrite_and_order_invariant_stencil ||
1257 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1258 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1259
1260 dsa->order_invariance[1].pass_set =
1261 nozwrite_and_order_invariant_stencil ||
1262 (!dsa->stencil_write_enabled &&
1263 (state->depth.func == PIPE_FUNC_ALWAYS ||
1264 state->depth.func == PIPE_FUNC_NEVER));
1265 dsa->order_invariance[0].pass_set =
1266 !dsa->depth_write_enabled ||
1267 (state->depth.func == PIPE_FUNC_ALWAYS ||
1268 state->depth.func == PIPE_FUNC_NEVER);
1269
1270 dsa->order_invariance[1].pass_last =
1271 sctx->screen->assume_no_z_fights &&
1272 !dsa->stencil_write_enabled &&
1273 dsa->depth_write_enabled && zfunc_is_ordered;
1274 dsa->order_invariance[0].pass_last =
1275 sctx->screen->assume_no_z_fights &&
1276 dsa->depth_write_enabled && zfunc_is_ordered;
1277
1278 return dsa;
1279 }
1280
1281 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1282 {
1283 struct si_context *sctx = (struct si_context *)ctx;
1284 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1285 struct si_state_dsa *dsa = state;
1286
1287 if (!state)
1288 return;
1289
1290 si_pm4_bind_state(sctx, dsa, dsa);
1291
1292 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1293 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1294 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1295 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1296 }
1297
1298 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1299 sctx->do_update_shaders = true;
1300
1301 if (sctx->screen->dpbb_allowed &&
1302 (!old_dsa ||
1303 (old_dsa->depth_enabled != dsa->depth_enabled ||
1304 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1305 old_dsa->db_can_write != dsa->db_can_write)))
1306 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1307
1308 if (sctx->screen->has_out_of_order_rast &&
1309 (!old_dsa ||
1310 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1311 sizeof(old_dsa->order_invariance))))
1312 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1313 }
1314
1315 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1316 {
1317 struct si_context *sctx = (struct si_context *)ctx;
1318 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1319 }
1320
1321 static void *si_create_db_flush_dsa(struct si_context *sctx)
1322 {
1323 struct pipe_depth_stencil_alpha_state dsa = {};
1324
1325 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1326 }
1327
1328 /* DB RENDER STATE */
1329
1330 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1331 {
1332 struct si_context *sctx = (struct si_context*)ctx;
1333
1334 /* Pipeline stat & streamout queries. */
1335 if (enable) {
1336 sctx->b.flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1337 sctx->b.flags |= SI_CONTEXT_START_PIPELINE_STATS;
1338 } else {
1339 sctx->b.flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1340 sctx->b.flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1341 }
1342
1343 /* Occlusion queries. */
1344 if (sctx->occlusion_queries_disabled != !enable) {
1345 sctx->occlusion_queries_disabled = !enable;
1346 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1347 }
1348 }
1349
1350 void si_set_occlusion_query_state(struct pipe_context *ctx,
1351 bool old_perfect_enable)
1352 {
1353 struct si_context *sctx = (struct si_context*)ctx;
1354
1355 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1356
1357 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
1358
1359 if (perfect_enable != old_perfect_enable)
1360 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1361 }
1362
1363 void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1364 {
1365 struct si_context *sctx = (struct si_context*)ctx;
1366
1367 st->saved_compute = sctx->cs_shader_state.program;
1368
1369 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1370 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1371 }
1372
1373 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1374 {
1375 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
1376 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1377 unsigned db_shader_control;
1378
1379 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1380
1381 /* DB_RENDER_CONTROL */
1382 if (sctx->dbcb_depth_copy_enabled ||
1383 sctx->dbcb_stencil_copy_enabled) {
1384 radeon_emit(cs,
1385 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1386 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1387 S_028000_COPY_CENTROID(1) |
1388 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1389 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1390 radeon_emit(cs,
1391 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1392 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1393 } else {
1394 radeon_emit(cs,
1395 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1396 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1397 }
1398
1399 /* DB_COUNT_CONTROL (occlusion queries) */
1400 if (sctx->b.num_occlusion_queries > 0 &&
1401 !sctx->occlusion_queries_disabled) {
1402 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1403
1404 if (sctx->b.chip_class >= CIK) {
1405 radeon_emit(cs,
1406 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1407 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1408 S_028004_ZPASS_ENABLE(1) |
1409 S_028004_SLICE_EVEN_ENABLE(1) |
1410 S_028004_SLICE_ODD_ENABLE(1));
1411 } else {
1412 radeon_emit(cs,
1413 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1414 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1415 }
1416 } else {
1417 /* Disable occlusion queries. */
1418 if (sctx->b.chip_class >= CIK) {
1419 radeon_emit(cs, 0);
1420 } else {
1421 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1422 }
1423 }
1424
1425 /* DB_RENDER_OVERRIDE2 */
1426 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1427 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1428 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1429 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1430
1431 db_shader_control = sctx->ps_db_shader_control;
1432
1433 /* Bug workaround for smoothing (overrasterization) on SI. */
1434 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1435 db_shader_control &= C_02880C_Z_ORDER;
1436 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1437 }
1438
1439 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1440 if (!rs || !rs->multisample_enable)
1441 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1442
1443 if (sctx->screen->has_rbplus &&
1444 !sctx->screen->rbplus_allowed)
1445 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1446
1447 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1448 db_shader_control);
1449 }
1450
1451 /*
1452 * format translation
1453 */
1454 static uint32_t si_translate_colorformat(enum pipe_format format)
1455 {
1456 const struct util_format_description *desc = util_format_description(format);
1457 if (!desc)
1458 return V_028C70_COLOR_INVALID;
1459
1460 #define HAS_SIZE(x,y,z,w) \
1461 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1462 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1463
1464 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1465 return V_028C70_COLOR_10_11_11;
1466
1467 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1468 return V_028C70_COLOR_INVALID;
1469
1470 /* hw cannot support mixed formats (except depth/stencil, since
1471 * stencil is not written to). */
1472 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1473 return V_028C70_COLOR_INVALID;
1474
1475 switch (desc->nr_channels) {
1476 case 1:
1477 switch (desc->channel[0].size) {
1478 case 8:
1479 return V_028C70_COLOR_8;
1480 case 16:
1481 return V_028C70_COLOR_16;
1482 case 32:
1483 return V_028C70_COLOR_32;
1484 }
1485 break;
1486 case 2:
1487 if (desc->channel[0].size == desc->channel[1].size) {
1488 switch (desc->channel[0].size) {
1489 case 8:
1490 return V_028C70_COLOR_8_8;
1491 case 16:
1492 return V_028C70_COLOR_16_16;
1493 case 32:
1494 return V_028C70_COLOR_32_32;
1495 }
1496 } else if (HAS_SIZE(8,24,0,0)) {
1497 return V_028C70_COLOR_24_8;
1498 } else if (HAS_SIZE(24,8,0,0)) {
1499 return V_028C70_COLOR_8_24;
1500 }
1501 break;
1502 case 3:
1503 if (HAS_SIZE(5,6,5,0)) {
1504 return V_028C70_COLOR_5_6_5;
1505 } else if (HAS_SIZE(32,8,24,0)) {
1506 return V_028C70_COLOR_X24_8_32_FLOAT;
1507 }
1508 break;
1509 case 4:
1510 if (desc->channel[0].size == desc->channel[1].size &&
1511 desc->channel[0].size == desc->channel[2].size &&
1512 desc->channel[0].size == desc->channel[3].size) {
1513 switch (desc->channel[0].size) {
1514 case 4:
1515 return V_028C70_COLOR_4_4_4_4;
1516 case 8:
1517 return V_028C70_COLOR_8_8_8_8;
1518 case 16:
1519 return V_028C70_COLOR_16_16_16_16;
1520 case 32:
1521 return V_028C70_COLOR_32_32_32_32;
1522 }
1523 } else if (HAS_SIZE(5,5,5,1)) {
1524 return V_028C70_COLOR_1_5_5_5;
1525 } else if (HAS_SIZE(1,5,5,5)) {
1526 return V_028C70_COLOR_5_5_5_1;
1527 } else if (HAS_SIZE(10,10,10,2)) {
1528 return V_028C70_COLOR_2_10_10_10;
1529 }
1530 break;
1531 }
1532 return V_028C70_COLOR_INVALID;
1533 }
1534
1535 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1536 {
1537 if (SI_BIG_ENDIAN) {
1538 switch(colorformat) {
1539 /* 8-bit buffers. */
1540 case V_028C70_COLOR_8:
1541 return V_028C70_ENDIAN_NONE;
1542
1543 /* 16-bit buffers. */
1544 case V_028C70_COLOR_5_6_5:
1545 case V_028C70_COLOR_1_5_5_5:
1546 case V_028C70_COLOR_4_4_4_4:
1547 case V_028C70_COLOR_16:
1548 case V_028C70_COLOR_8_8:
1549 return V_028C70_ENDIAN_8IN16;
1550
1551 /* 32-bit buffers. */
1552 case V_028C70_COLOR_8_8_8_8:
1553 case V_028C70_COLOR_2_10_10_10:
1554 case V_028C70_COLOR_8_24:
1555 case V_028C70_COLOR_24_8:
1556 case V_028C70_COLOR_16_16:
1557 return V_028C70_ENDIAN_8IN32;
1558
1559 /* 64-bit buffers. */
1560 case V_028C70_COLOR_16_16_16_16:
1561 return V_028C70_ENDIAN_8IN16;
1562
1563 case V_028C70_COLOR_32_32:
1564 return V_028C70_ENDIAN_8IN32;
1565
1566 /* 128-bit buffers. */
1567 case V_028C70_COLOR_32_32_32_32:
1568 return V_028C70_ENDIAN_8IN32;
1569 default:
1570 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1571 }
1572 } else {
1573 return V_028C70_ENDIAN_NONE;
1574 }
1575 }
1576
1577 static uint32_t si_translate_dbformat(enum pipe_format format)
1578 {
1579 switch (format) {
1580 case PIPE_FORMAT_Z16_UNORM:
1581 return V_028040_Z_16;
1582 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1583 case PIPE_FORMAT_X8Z24_UNORM:
1584 case PIPE_FORMAT_Z24X8_UNORM:
1585 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1586 return V_028040_Z_24; /* deprecated on SI */
1587 case PIPE_FORMAT_Z32_FLOAT:
1588 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1589 return V_028040_Z_32_FLOAT;
1590 default:
1591 return V_028040_Z_INVALID;
1592 }
1593 }
1594
1595 /*
1596 * Texture translation
1597 */
1598
1599 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1600 enum pipe_format format,
1601 const struct util_format_description *desc,
1602 int first_non_void)
1603 {
1604 struct si_screen *sscreen = (struct si_screen*)screen;
1605 bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
1606 sscreen->info.drm_minor >= 31) ||
1607 sscreen->info.drm_major == 3;
1608 bool uniform = true;
1609 int i;
1610
1611 /* Colorspace (return non-RGB formats directly). */
1612 switch (desc->colorspace) {
1613 /* Depth stencil formats */
1614 case UTIL_FORMAT_COLORSPACE_ZS:
1615 switch (format) {
1616 case PIPE_FORMAT_Z16_UNORM:
1617 return V_008F14_IMG_DATA_FORMAT_16;
1618 case PIPE_FORMAT_X24S8_UINT:
1619 case PIPE_FORMAT_S8X24_UINT:
1620 /*
1621 * Implemented as an 8_8_8_8 data format to fix texture
1622 * gathers in stencil sampling. This affects at least
1623 * GL45-CTS.texture_cube_map_array.sampling on VI.
1624 */
1625 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1626 case PIPE_FORMAT_Z24X8_UNORM:
1627 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1628 return V_008F14_IMG_DATA_FORMAT_8_24;
1629 case PIPE_FORMAT_X8Z24_UNORM:
1630 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1631 return V_008F14_IMG_DATA_FORMAT_24_8;
1632 case PIPE_FORMAT_S8_UINT:
1633 return V_008F14_IMG_DATA_FORMAT_8;
1634 case PIPE_FORMAT_Z32_FLOAT:
1635 return V_008F14_IMG_DATA_FORMAT_32;
1636 case PIPE_FORMAT_X32_S8X24_UINT:
1637 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1638 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1639 default:
1640 goto out_unknown;
1641 }
1642
1643 case UTIL_FORMAT_COLORSPACE_YUV:
1644 goto out_unknown; /* TODO */
1645
1646 case UTIL_FORMAT_COLORSPACE_SRGB:
1647 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1648 goto out_unknown;
1649 break;
1650
1651 default:
1652 break;
1653 }
1654
1655 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1656 if (!enable_compressed_formats)
1657 goto out_unknown;
1658
1659 switch (format) {
1660 case PIPE_FORMAT_RGTC1_SNORM:
1661 case PIPE_FORMAT_LATC1_SNORM:
1662 case PIPE_FORMAT_RGTC1_UNORM:
1663 case PIPE_FORMAT_LATC1_UNORM:
1664 return V_008F14_IMG_DATA_FORMAT_BC4;
1665 case PIPE_FORMAT_RGTC2_SNORM:
1666 case PIPE_FORMAT_LATC2_SNORM:
1667 case PIPE_FORMAT_RGTC2_UNORM:
1668 case PIPE_FORMAT_LATC2_UNORM:
1669 return V_008F14_IMG_DATA_FORMAT_BC5;
1670 default:
1671 goto out_unknown;
1672 }
1673 }
1674
1675 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1676 (sscreen->info.family == CHIP_STONEY ||
1677 sscreen->info.family == CHIP_VEGA10 ||
1678 sscreen->info.family == CHIP_RAVEN)) {
1679 switch (format) {
1680 case PIPE_FORMAT_ETC1_RGB8:
1681 case PIPE_FORMAT_ETC2_RGB8:
1682 case PIPE_FORMAT_ETC2_SRGB8:
1683 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1684 case PIPE_FORMAT_ETC2_RGB8A1:
1685 case PIPE_FORMAT_ETC2_SRGB8A1:
1686 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1687 case PIPE_FORMAT_ETC2_RGBA8:
1688 case PIPE_FORMAT_ETC2_SRGBA8:
1689 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1690 case PIPE_FORMAT_ETC2_R11_UNORM:
1691 case PIPE_FORMAT_ETC2_R11_SNORM:
1692 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1693 case PIPE_FORMAT_ETC2_RG11_UNORM:
1694 case PIPE_FORMAT_ETC2_RG11_SNORM:
1695 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1696 default:
1697 goto out_unknown;
1698 }
1699 }
1700
1701 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1702 if (!enable_compressed_formats)
1703 goto out_unknown;
1704
1705 switch (format) {
1706 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1707 case PIPE_FORMAT_BPTC_SRGBA:
1708 return V_008F14_IMG_DATA_FORMAT_BC7;
1709 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1710 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1711 return V_008F14_IMG_DATA_FORMAT_BC6;
1712 default:
1713 goto out_unknown;
1714 }
1715 }
1716
1717 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1718 switch (format) {
1719 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1720 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1721 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1722 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1723 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1724 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1725 default:
1726 goto out_unknown;
1727 }
1728 }
1729
1730 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1731 if (!enable_compressed_formats)
1732 goto out_unknown;
1733
1734 switch (format) {
1735 case PIPE_FORMAT_DXT1_RGB:
1736 case PIPE_FORMAT_DXT1_RGBA:
1737 case PIPE_FORMAT_DXT1_SRGB:
1738 case PIPE_FORMAT_DXT1_SRGBA:
1739 return V_008F14_IMG_DATA_FORMAT_BC1;
1740 case PIPE_FORMAT_DXT3_RGBA:
1741 case PIPE_FORMAT_DXT3_SRGBA:
1742 return V_008F14_IMG_DATA_FORMAT_BC2;
1743 case PIPE_FORMAT_DXT5_RGBA:
1744 case PIPE_FORMAT_DXT5_SRGBA:
1745 return V_008F14_IMG_DATA_FORMAT_BC3;
1746 default:
1747 goto out_unknown;
1748 }
1749 }
1750
1751 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1752 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1753 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1754 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1755 }
1756
1757 /* R8G8Bx_SNORM - TODO CxV8U8 */
1758
1759 /* hw cannot support mixed formats (except depth/stencil, since only
1760 * depth is read).*/
1761 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1762 goto out_unknown;
1763
1764 /* See whether the components are of the same size. */
1765 for (i = 1; i < desc->nr_channels; i++) {
1766 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1767 }
1768
1769 /* Non-uniform formats. */
1770 if (!uniform) {
1771 switch(desc->nr_channels) {
1772 case 3:
1773 if (desc->channel[0].size == 5 &&
1774 desc->channel[1].size == 6 &&
1775 desc->channel[2].size == 5) {
1776 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1777 }
1778 goto out_unknown;
1779 case 4:
1780 if (desc->channel[0].size == 5 &&
1781 desc->channel[1].size == 5 &&
1782 desc->channel[2].size == 5 &&
1783 desc->channel[3].size == 1) {
1784 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1785 }
1786 if (desc->channel[0].size == 1 &&
1787 desc->channel[1].size == 5 &&
1788 desc->channel[2].size == 5 &&
1789 desc->channel[3].size == 5) {
1790 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1791 }
1792 if (desc->channel[0].size == 10 &&
1793 desc->channel[1].size == 10 &&
1794 desc->channel[2].size == 10 &&
1795 desc->channel[3].size == 2) {
1796 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1797 }
1798 goto out_unknown;
1799 }
1800 goto out_unknown;
1801 }
1802
1803 if (first_non_void < 0 || first_non_void > 3)
1804 goto out_unknown;
1805
1806 /* uniform formats */
1807 switch (desc->channel[first_non_void].size) {
1808 case 4:
1809 switch (desc->nr_channels) {
1810 #if 0 /* Not supported for render targets */
1811 case 2:
1812 return V_008F14_IMG_DATA_FORMAT_4_4;
1813 #endif
1814 case 4:
1815 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1816 }
1817 break;
1818 case 8:
1819 switch (desc->nr_channels) {
1820 case 1:
1821 return V_008F14_IMG_DATA_FORMAT_8;
1822 case 2:
1823 return V_008F14_IMG_DATA_FORMAT_8_8;
1824 case 4:
1825 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1826 }
1827 break;
1828 case 16:
1829 switch (desc->nr_channels) {
1830 case 1:
1831 return V_008F14_IMG_DATA_FORMAT_16;
1832 case 2:
1833 return V_008F14_IMG_DATA_FORMAT_16_16;
1834 case 4:
1835 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1836 }
1837 break;
1838 case 32:
1839 switch (desc->nr_channels) {
1840 case 1:
1841 return V_008F14_IMG_DATA_FORMAT_32;
1842 case 2:
1843 return V_008F14_IMG_DATA_FORMAT_32_32;
1844 #if 0 /* Not supported for render targets */
1845 case 3:
1846 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1847 #endif
1848 case 4:
1849 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1850 }
1851 }
1852
1853 out_unknown:
1854 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1855 return ~0;
1856 }
1857
1858 static unsigned si_tex_wrap(unsigned wrap)
1859 {
1860 switch (wrap) {
1861 default:
1862 case PIPE_TEX_WRAP_REPEAT:
1863 return V_008F30_SQ_TEX_WRAP;
1864 case PIPE_TEX_WRAP_CLAMP:
1865 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1866 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1867 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1868 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1869 return V_008F30_SQ_TEX_CLAMP_BORDER;
1870 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1871 return V_008F30_SQ_TEX_MIRROR;
1872 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1873 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1874 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1875 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1876 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1877 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1878 }
1879 }
1880
1881 static unsigned si_tex_mipfilter(unsigned filter)
1882 {
1883 switch (filter) {
1884 case PIPE_TEX_MIPFILTER_NEAREST:
1885 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1886 case PIPE_TEX_MIPFILTER_LINEAR:
1887 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1888 default:
1889 case PIPE_TEX_MIPFILTER_NONE:
1890 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1891 }
1892 }
1893
1894 static unsigned si_tex_compare(unsigned compare)
1895 {
1896 switch (compare) {
1897 default:
1898 case PIPE_FUNC_NEVER:
1899 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1900 case PIPE_FUNC_LESS:
1901 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1902 case PIPE_FUNC_EQUAL:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1904 case PIPE_FUNC_LEQUAL:
1905 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1906 case PIPE_FUNC_GREATER:
1907 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1908 case PIPE_FUNC_NOTEQUAL:
1909 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1910 case PIPE_FUNC_GEQUAL:
1911 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1912 case PIPE_FUNC_ALWAYS:
1913 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1914 }
1915 }
1916
1917 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1918 unsigned view_target, unsigned nr_samples)
1919 {
1920 unsigned res_target = rtex->resource.b.b.target;
1921
1922 if (view_target == PIPE_TEXTURE_CUBE ||
1923 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1924 res_target = view_target;
1925 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1926 else if (res_target == PIPE_TEXTURE_CUBE ||
1927 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1928 res_target = PIPE_TEXTURE_2D_ARRAY;
1929
1930 /* GFX9 allocates 1D textures as 2D. */
1931 if ((res_target == PIPE_TEXTURE_1D ||
1932 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1933 sscreen->info.chip_class >= GFX9 &&
1934 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1935 if (res_target == PIPE_TEXTURE_1D)
1936 res_target = PIPE_TEXTURE_2D;
1937 else
1938 res_target = PIPE_TEXTURE_2D_ARRAY;
1939 }
1940
1941 switch (res_target) {
1942 default:
1943 case PIPE_TEXTURE_1D:
1944 return V_008F1C_SQ_RSRC_IMG_1D;
1945 case PIPE_TEXTURE_1D_ARRAY:
1946 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1947 case PIPE_TEXTURE_2D:
1948 case PIPE_TEXTURE_RECT:
1949 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1950 V_008F1C_SQ_RSRC_IMG_2D;
1951 case PIPE_TEXTURE_2D_ARRAY:
1952 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1953 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1954 case PIPE_TEXTURE_3D:
1955 return V_008F1C_SQ_RSRC_IMG_3D;
1956 case PIPE_TEXTURE_CUBE:
1957 case PIPE_TEXTURE_CUBE_ARRAY:
1958 return V_008F1C_SQ_RSRC_IMG_CUBE;
1959 }
1960 }
1961
1962 /*
1963 * Format support testing
1964 */
1965
1966 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1967 {
1968 const struct util_format_description *desc = util_format_description(format);
1969 if (!desc)
1970 return false;
1971
1972 return si_translate_texformat(screen, format, desc,
1973 util_format_get_first_non_void_channel(format)) != ~0U;
1974 }
1975
1976 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1977 const struct util_format_description *desc,
1978 int first_non_void)
1979 {
1980 int i;
1981
1982 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1983 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1984
1985 assert(first_non_void >= 0);
1986
1987 if (desc->nr_channels == 4 &&
1988 desc->channel[0].size == 10 &&
1989 desc->channel[1].size == 10 &&
1990 desc->channel[2].size == 10 &&
1991 desc->channel[3].size == 2)
1992 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1993
1994 /* See whether the components are of the same size. */
1995 for (i = 0; i < desc->nr_channels; i++) {
1996 if (desc->channel[first_non_void].size != desc->channel[i].size)
1997 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1998 }
1999
2000 switch (desc->channel[first_non_void].size) {
2001 case 8:
2002 switch (desc->nr_channels) {
2003 case 1:
2004 case 3: /* 3 loads */
2005 return V_008F0C_BUF_DATA_FORMAT_8;
2006 case 2:
2007 return V_008F0C_BUF_DATA_FORMAT_8_8;
2008 case 4:
2009 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2010 }
2011 break;
2012 case 16:
2013 switch (desc->nr_channels) {
2014 case 1:
2015 case 3: /* 3 loads */
2016 return V_008F0C_BUF_DATA_FORMAT_16;
2017 case 2:
2018 return V_008F0C_BUF_DATA_FORMAT_16_16;
2019 case 4:
2020 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2021 }
2022 break;
2023 case 32:
2024 switch (desc->nr_channels) {
2025 case 1:
2026 return V_008F0C_BUF_DATA_FORMAT_32;
2027 case 2:
2028 return V_008F0C_BUF_DATA_FORMAT_32_32;
2029 case 3:
2030 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2031 case 4:
2032 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2033 }
2034 break;
2035 case 64:
2036 /* Legacy double formats. */
2037 switch (desc->nr_channels) {
2038 case 1: /* 1 load */
2039 return V_008F0C_BUF_DATA_FORMAT_32_32;
2040 case 2: /* 1 load */
2041 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2042 case 3: /* 3 loads */
2043 return V_008F0C_BUF_DATA_FORMAT_32_32;
2044 case 4: /* 2 loads */
2045 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2046 }
2047 break;
2048 }
2049
2050 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2051 }
2052
2053 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2054 const struct util_format_description *desc,
2055 int first_non_void)
2056 {
2057 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2058 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2059
2060 assert(first_non_void >= 0);
2061
2062 switch (desc->channel[first_non_void].type) {
2063 case UTIL_FORMAT_TYPE_SIGNED:
2064 case UTIL_FORMAT_TYPE_FIXED:
2065 if (desc->channel[first_non_void].size >= 32 ||
2066 desc->channel[first_non_void].pure_integer)
2067 return V_008F0C_BUF_NUM_FORMAT_SINT;
2068 else if (desc->channel[first_non_void].normalized)
2069 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2070 else
2071 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2072 break;
2073 case UTIL_FORMAT_TYPE_UNSIGNED:
2074 if (desc->channel[first_non_void].size >= 32 ||
2075 desc->channel[first_non_void].pure_integer)
2076 return V_008F0C_BUF_NUM_FORMAT_UINT;
2077 else if (desc->channel[first_non_void].normalized)
2078 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2079 else
2080 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2081 break;
2082 case UTIL_FORMAT_TYPE_FLOAT:
2083 default:
2084 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2085 }
2086 }
2087
2088 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2089 enum pipe_format format,
2090 unsigned usage)
2091 {
2092 const struct util_format_description *desc;
2093 int first_non_void;
2094 unsigned data_format;
2095
2096 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2097 PIPE_BIND_SAMPLER_VIEW |
2098 PIPE_BIND_VERTEX_BUFFER)) == 0);
2099
2100 desc = util_format_description(format);
2101 if (!desc)
2102 return 0;
2103
2104 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2105 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2106 * for read-only access (with caveats surrounding bounds checks), but
2107 * obviously fails for write access which we have to implement for
2108 * shader images. Luckily, OpenGL doesn't expect this to be supported
2109 * anyway, and so the only impact is on PBO uploads / downloads, which
2110 * shouldn't be expected to be fast for GL_RGB anyway.
2111 */
2112 if (desc->block.bits == 3 * 8 ||
2113 desc->block.bits == 3 * 16) {
2114 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2115 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2116 if (!usage)
2117 return 0;
2118 }
2119 }
2120
2121 first_non_void = util_format_get_first_non_void_channel(format);
2122 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2123 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2124 return 0;
2125
2126 return usage;
2127 }
2128
2129 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2130 {
2131 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2132 si_translate_colorswap(format, false) != ~0U;
2133 }
2134
2135 static bool si_is_zs_format_supported(enum pipe_format format)
2136 {
2137 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2138 }
2139
2140 static boolean si_is_format_supported(struct pipe_screen *screen,
2141 enum pipe_format format,
2142 enum pipe_texture_target target,
2143 unsigned sample_count,
2144 unsigned usage)
2145 {
2146 unsigned retval = 0;
2147
2148 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2149 R600_ERR("r600: unsupported texture type %d\n", target);
2150 return false;
2151 }
2152
2153 if (!util_format_is_supported(format, usage))
2154 return false;
2155
2156 if (sample_count > 1) {
2157 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2158 return false;
2159
2160 if (usage & PIPE_BIND_SHADER_IMAGE)
2161 return false;
2162
2163 switch (sample_count) {
2164 case 2:
2165 case 4:
2166 case 8:
2167 break;
2168 case 16:
2169 if (format == PIPE_FORMAT_NONE)
2170 return true;
2171 else
2172 return false;
2173 default:
2174 return false;
2175 }
2176 }
2177
2178 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2179 PIPE_BIND_SHADER_IMAGE)) {
2180 if (target == PIPE_BUFFER) {
2181 retval |= si_is_vertex_format_supported(
2182 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2183 PIPE_BIND_SHADER_IMAGE));
2184 } else {
2185 if (si_is_sampler_format_supported(screen, format))
2186 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2187 PIPE_BIND_SHADER_IMAGE);
2188 }
2189 }
2190
2191 if ((usage & (PIPE_BIND_RENDER_TARGET |
2192 PIPE_BIND_DISPLAY_TARGET |
2193 PIPE_BIND_SCANOUT |
2194 PIPE_BIND_SHARED |
2195 PIPE_BIND_BLENDABLE)) &&
2196 si_is_colorbuffer_format_supported(format)) {
2197 retval |= usage &
2198 (PIPE_BIND_RENDER_TARGET |
2199 PIPE_BIND_DISPLAY_TARGET |
2200 PIPE_BIND_SCANOUT |
2201 PIPE_BIND_SHARED);
2202 if (!util_format_is_pure_integer(format) &&
2203 !util_format_is_depth_or_stencil(format))
2204 retval |= usage & PIPE_BIND_BLENDABLE;
2205 }
2206
2207 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2208 si_is_zs_format_supported(format)) {
2209 retval |= PIPE_BIND_DEPTH_STENCIL;
2210 }
2211
2212 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2213 retval |= si_is_vertex_format_supported(screen, format,
2214 PIPE_BIND_VERTEX_BUFFER);
2215 }
2216
2217 if ((usage & PIPE_BIND_LINEAR) &&
2218 !util_format_is_compressed(format) &&
2219 !(usage & PIPE_BIND_DEPTH_STENCIL))
2220 retval |= PIPE_BIND_LINEAR;
2221
2222 return retval == usage;
2223 }
2224
2225 /*
2226 * framebuffer handling
2227 */
2228
2229 static void si_choose_spi_color_formats(struct r600_surface *surf,
2230 unsigned format, unsigned swap,
2231 unsigned ntype, bool is_depth)
2232 {
2233 /* Alpha is needed for alpha-to-coverage.
2234 * Blending may be with or without alpha.
2235 */
2236 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2237 unsigned alpha = 0; /* exports alpha, but may not support blending */
2238 unsigned blend = 0; /* supports blending, but may not export alpha */
2239 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2240
2241 /* Choose the SPI color formats. These are required values for RB+.
2242 * Other chips have multiple choices, though they are not necessarily better.
2243 */
2244 switch (format) {
2245 case V_028C70_COLOR_5_6_5:
2246 case V_028C70_COLOR_1_5_5_5:
2247 case V_028C70_COLOR_5_5_5_1:
2248 case V_028C70_COLOR_4_4_4_4:
2249 case V_028C70_COLOR_10_11_11:
2250 case V_028C70_COLOR_11_11_10:
2251 case V_028C70_COLOR_8:
2252 case V_028C70_COLOR_8_8:
2253 case V_028C70_COLOR_8_8_8_8:
2254 case V_028C70_COLOR_10_10_10_2:
2255 case V_028C70_COLOR_2_10_10_10:
2256 if (ntype == V_028C70_NUMBER_UINT)
2257 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2258 else if (ntype == V_028C70_NUMBER_SINT)
2259 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2260 else
2261 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2262 break;
2263
2264 case V_028C70_COLOR_16:
2265 case V_028C70_COLOR_16_16:
2266 case V_028C70_COLOR_16_16_16_16:
2267 if (ntype == V_028C70_NUMBER_UNORM ||
2268 ntype == V_028C70_NUMBER_SNORM) {
2269 /* UNORM16 and SNORM16 don't support blending */
2270 if (ntype == V_028C70_NUMBER_UNORM)
2271 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2272 else
2273 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2274
2275 /* Use 32 bits per channel for blending. */
2276 if (format == V_028C70_COLOR_16) {
2277 if (swap == V_028C70_SWAP_STD) { /* R */
2278 blend = V_028714_SPI_SHADER_32_R;
2279 blend_alpha = V_028714_SPI_SHADER_32_AR;
2280 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2281 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2282 else
2283 assert(0);
2284 } else if (format == V_028C70_COLOR_16_16) {
2285 if (swap == V_028C70_SWAP_STD) { /* RG */
2286 blend = V_028714_SPI_SHADER_32_GR;
2287 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2288 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2289 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2290 else
2291 assert(0);
2292 } else /* 16_16_16_16 */
2293 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2294 } else if (ntype == V_028C70_NUMBER_UINT)
2295 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2296 else if (ntype == V_028C70_NUMBER_SINT)
2297 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2298 else if (ntype == V_028C70_NUMBER_FLOAT)
2299 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2300 else
2301 assert(0);
2302 break;
2303
2304 case V_028C70_COLOR_32:
2305 if (swap == V_028C70_SWAP_STD) { /* R */
2306 blend = normal = V_028714_SPI_SHADER_32_R;
2307 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2308 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2309 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2310 else
2311 assert(0);
2312 break;
2313
2314 case V_028C70_COLOR_32_32:
2315 if (swap == V_028C70_SWAP_STD) { /* RG */
2316 blend = normal = V_028714_SPI_SHADER_32_GR;
2317 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2318 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2319 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2320 else
2321 assert(0);
2322 break;
2323
2324 case V_028C70_COLOR_32_32_32_32:
2325 case V_028C70_COLOR_8_24:
2326 case V_028C70_COLOR_24_8:
2327 case V_028C70_COLOR_X24_8_32_FLOAT:
2328 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2329 break;
2330
2331 default:
2332 assert(0);
2333 return;
2334 }
2335
2336 /* The DB->CB copy needs 32_ABGR. */
2337 if (is_depth)
2338 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2339
2340 surf->spi_shader_col_format = normal;
2341 surf->spi_shader_col_format_alpha = alpha;
2342 surf->spi_shader_col_format_blend = blend;
2343 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2344 }
2345
2346 static void si_initialize_color_surface(struct si_context *sctx,
2347 struct r600_surface *surf)
2348 {
2349 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2350 unsigned color_info, color_attrib;
2351 unsigned format, swap, ntype, endian;
2352 const struct util_format_description *desc;
2353 int firstchan;
2354 unsigned blend_clamp = 0, blend_bypass = 0;
2355
2356 desc = util_format_description(surf->base.format);
2357 for (firstchan = 0; firstchan < 4; firstchan++) {
2358 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2359 break;
2360 }
2361 }
2362 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2363 ntype = V_028C70_NUMBER_FLOAT;
2364 } else {
2365 ntype = V_028C70_NUMBER_UNORM;
2366 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2367 ntype = V_028C70_NUMBER_SRGB;
2368 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2369 if (desc->channel[firstchan].pure_integer) {
2370 ntype = V_028C70_NUMBER_SINT;
2371 } else {
2372 assert(desc->channel[firstchan].normalized);
2373 ntype = V_028C70_NUMBER_SNORM;
2374 }
2375 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2376 if (desc->channel[firstchan].pure_integer) {
2377 ntype = V_028C70_NUMBER_UINT;
2378 } else {
2379 assert(desc->channel[firstchan].normalized);
2380 ntype = V_028C70_NUMBER_UNORM;
2381 }
2382 }
2383 }
2384
2385 format = si_translate_colorformat(surf->base.format);
2386 if (format == V_028C70_COLOR_INVALID) {
2387 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2388 }
2389 assert(format != V_028C70_COLOR_INVALID);
2390 swap = si_translate_colorswap(surf->base.format, false);
2391 endian = si_colorformat_endian_swap(format);
2392
2393 /* blend clamp should be set for all NORM/SRGB types */
2394 if (ntype == V_028C70_NUMBER_UNORM ||
2395 ntype == V_028C70_NUMBER_SNORM ||
2396 ntype == V_028C70_NUMBER_SRGB)
2397 blend_clamp = 1;
2398
2399 /* set blend bypass according to docs if SINT/UINT or
2400 8/24 COLOR variants */
2401 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2402 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2403 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2404 blend_clamp = 0;
2405 blend_bypass = 1;
2406 }
2407
2408 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2409 if (format == V_028C70_COLOR_8 ||
2410 format == V_028C70_COLOR_8_8 ||
2411 format == V_028C70_COLOR_8_8_8_8)
2412 surf->color_is_int8 = true;
2413 else if (format == V_028C70_COLOR_10_10_10_2 ||
2414 format == V_028C70_COLOR_2_10_10_10)
2415 surf->color_is_int10 = true;
2416 }
2417
2418 color_info = S_028C70_FORMAT(format) |
2419 S_028C70_COMP_SWAP(swap) |
2420 S_028C70_BLEND_CLAMP(blend_clamp) |
2421 S_028C70_BLEND_BYPASS(blend_bypass) |
2422 S_028C70_SIMPLE_FLOAT(1) |
2423 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2424 ntype != V_028C70_NUMBER_SNORM &&
2425 ntype != V_028C70_NUMBER_SRGB &&
2426 format != V_028C70_COLOR_8_24 &&
2427 format != V_028C70_COLOR_24_8) |
2428 S_028C70_NUMBER_TYPE(ntype) |
2429 S_028C70_ENDIAN(endian);
2430
2431 /* Intensity is implemented as Red, so treat it that way. */
2432 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2433 util_format_is_intensity(surf->base.format));
2434
2435 if (rtex->resource.b.b.nr_samples > 1) {
2436 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2437
2438 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2439 S_028C74_NUM_FRAGMENTS(log_samples);
2440
2441 if (rtex->fmask.size) {
2442 color_info |= S_028C70_COMPRESSION(1);
2443 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2444
2445 if (sctx->b.chip_class == SI) {
2446 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2447 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2448 }
2449 }
2450 }
2451
2452 if (sctx->b.chip_class >= VI) {
2453 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2454 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2455
2456 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2457 64 for APU because all of our APUs to date use DIMMs which have
2458 a request granularity size of 64B while all other chips have a
2459 32B request size */
2460 if (!sctx->screen->info.has_dedicated_vram)
2461 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2462
2463 if (rtex->resource.b.b.nr_samples > 1) {
2464 if (rtex->surface.bpe == 1)
2465 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2466 else if (rtex->surface.bpe == 2)
2467 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2468 }
2469
2470 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2471 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2472 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2473 }
2474
2475 /* This must be set for fast clear to work without FMASK. */
2476 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2477 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2478 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2479 }
2480
2481 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2482 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2483
2484 if (sctx->b.chip_class >= GFX9) {
2485 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2486
2487 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2488 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2489 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2490 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2491 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2492 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2493 }
2494
2495 surf->cb_color_view = color_view;
2496 surf->cb_color_info = color_info;
2497 surf->cb_color_attrib = color_attrib;
2498
2499 /* Determine pixel shader export format */
2500 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2501
2502 surf->color_initialized = true;
2503 }
2504
2505 static void si_init_depth_surface(struct si_context *sctx,
2506 struct r600_surface *surf)
2507 {
2508 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2509 unsigned level = surf->base.u.tex.level;
2510 unsigned format, stencil_format;
2511 uint32_t z_info, s_info;
2512
2513 format = si_translate_dbformat(rtex->db_render_format);
2514 stencil_format = rtex->surface.has_stencil ?
2515 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2516
2517 assert(format != V_028040_Z_INVALID);
2518 if (format == V_028040_Z_INVALID)
2519 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2520
2521 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2522 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2523 surf->db_htile_data_base = 0;
2524 surf->db_htile_surface = 0;
2525
2526 if (sctx->b.chip_class >= GFX9) {
2527 assert(rtex->surface.u.gfx9.surf_offset == 0);
2528 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2529 surf->db_stencil_base = (rtex->resource.gpu_address +
2530 rtex->surface.u.gfx9.stencil_offset) >> 8;
2531 z_info = S_028038_FORMAT(format) |
2532 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2533 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2534 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2535 s_info = S_02803C_FORMAT(stencil_format) |
2536 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2537 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2538 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2539 surf->db_depth_view |= S_028008_MIPID(level);
2540 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2541 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2542
2543 if (si_htile_enabled(rtex, level)) {
2544 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2545 S_028038_ALLOW_EXPCLEAR(1);
2546
2547 if (rtex->tc_compatible_htile) {
2548 unsigned max_zplanes = 4;
2549
2550 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2551 rtex->resource.b.b.nr_samples > 1)
2552 max_zplanes = 2;
2553
2554 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2555 S_028038_ITERATE_FLUSH(1);
2556 s_info |= S_02803C_ITERATE_FLUSH(1);
2557 }
2558
2559 if (rtex->surface.has_stencil) {
2560 /* Stencil buffer workaround ported from the SI-CI-VI code.
2561 * See that for explanation.
2562 */
2563 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2564 } else {
2565 /* Use all HTILE for depth if there's no stencil. */
2566 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2567 }
2568
2569 surf->db_htile_data_base = (rtex->resource.gpu_address +
2570 rtex->htile_offset) >> 8;
2571 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2572 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2573 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2574 }
2575 } else {
2576 /* SI-CI-VI */
2577 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2578
2579 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2580
2581 surf->db_depth_base = (rtex->resource.gpu_address +
2582 rtex->surface.u.legacy.level[level].offset) >> 8;
2583 surf->db_stencil_base = (rtex->resource.gpu_address +
2584 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2585
2586 z_info = S_028040_FORMAT(format) |
2587 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2588 s_info = S_028044_FORMAT(stencil_format);
2589 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2590
2591 if (sctx->b.chip_class >= CIK) {
2592 struct radeon_info *info = &sctx->screen->info;
2593 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2594 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2595 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2596 unsigned tile_mode = info->si_tile_mode_array[index];
2597 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2598 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2599
2600 surf->db_depth_info |=
2601 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2602 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2603 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2604 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2605 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2606 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2607 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2608 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2609 } else {
2610 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2611 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2612 tile_mode_index = si_tile_mode_index(rtex, level, true);
2613 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2614 }
2615
2616 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2617 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2618 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2619 levelinfo->nblk_y) / 64 - 1);
2620
2621 if (si_htile_enabled(rtex, level)) {
2622 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2623 S_028040_ALLOW_EXPCLEAR(1);
2624
2625 if (rtex->surface.has_stencil) {
2626 /* Workaround: For a not yet understood reason, the
2627 * combination of MSAA, fast stencil clear and stencil
2628 * decompress messes with subsequent stencil buffer
2629 * uses. Problem was reproduced on Verde, Bonaire,
2630 * Tonga, and Carrizo.
2631 *
2632 * Disabling EXPCLEAR works around the problem.
2633 *
2634 * Check piglit's arb_texture_multisample-stencil-clear
2635 * test if you want to try changing this.
2636 */
2637 if (rtex->resource.b.b.nr_samples <= 1)
2638 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2639 } else if (!rtex->tc_compatible_htile) {
2640 /* Use all of the htile_buffer for depth if there's no stencil.
2641 * This must not be set when TC-compatible HTILE is enabled
2642 * due to a hw bug.
2643 */
2644 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2645 }
2646
2647 surf->db_htile_data_base = (rtex->resource.gpu_address +
2648 rtex->htile_offset) >> 8;
2649 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2650
2651 if (rtex->tc_compatible_htile) {
2652 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2653
2654 if (rtex->resource.b.b.nr_samples <= 1)
2655 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2656 else if (rtex->resource.b.b.nr_samples <= 4)
2657 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2658 else
2659 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2660 }
2661 }
2662 }
2663
2664 surf->db_z_info = z_info;
2665 surf->db_stencil_info = s_info;
2666
2667 surf->depth_initialized = true;
2668 }
2669
2670 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2671 {
2672 if (sctx->decompression_enabled)
2673 return;
2674
2675 if (sctx->framebuffer.state.zsbuf) {
2676 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2677 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2678
2679 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2680
2681 if (rtex->surface.has_stencil)
2682 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2683 }
2684
2685 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2686 while (compressed_cb_mask) {
2687 unsigned i = u_bit_scan(&compressed_cb_mask);
2688 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2689 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2690
2691 if (rtex->fmask.size)
2692 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2693 if (rtex->dcc_gather_statistics)
2694 rtex->separate_dcc_dirty = true;
2695 }
2696 }
2697
2698 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2699 {
2700 for (int i = 0; i < state->nr_cbufs; ++i) {
2701 struct r600_surface *surf = NULL;
2702 struct r600_texture *rtex;
2703
2704 if (!state->cbufs[i])
2705 continue;
2706 surf = (struct r600_surface*)state->cbufs[i];
2707 rtex = (struct r600_texture*)surf->base.texture;
2708
2709 p_atomic_dec(&rtex->framebuffers_bound);
2710 }
2711 }
2712
2713 static void si_set_framebuffer_state(struct pipe_context *ctx,
2714 const struct pipe_framebuffer_state *state)
2715 {
2716 struct si_context *sctx = (struct si_context *)ctx;
2717 struct pipe_constant_buffer constbuf = {0};
2718 struct r600_surface *surf = NULL;
2719 struct r600_texture *rtex;
2720 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2721 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2722 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2723 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2724 bool old_has_stencil =
2725 old_has_zsbuf &&
2726 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2727 bool unbound = false;
2728 int i;
2729
2730 si_update_fb_dirtiness_after_rendering(sctx);
2731
2732 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2733 if (!sctx->framebuffer.state.cbufs[i])
2734 continue;
2735
2736 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2737 if (rtex->dcc_gather_statistics)
2738 vi_separate_dcc_stop_query(ctx, rtex);
2739 }
2740
2741 /* Disable DCC if the formats are incompatible. */
2742 for (i = 0; i < state->nr_cbufs; i++) {
2743 if (!state->cbufs[i])
2744 continue;
2745
2746 surf = (struct r600_surface*)state->cbufs[i];
2747 rtex = (struct r600_texture*)surf->base.texture;
2748
2749 if (!surf->dcc_incompatible)
2750 continue;
2751
2752 /* Since the DCC decompression calls back into set_framebuffer-
2753 * _state, we need to unbind the framebuffer, so that
2754 * vi_separate_dcc_stop_query isn't called twice with the same
2755 * color buffer.
2756 */
2757 if (!unbound) {
2758 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2759 unbound = true;
2760 }
2761
2762 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2763 if (!si_texture_disable_dcc(sctx, rtex))
2764 si_decompress_dcc(ctx, rtex);
2765
2766 surf->dcc_incompatible = false;
2767 }
2768
2769 /* Only flush TC when changing the framebuffer state, because
2770 * the only client not using TC that can change textures is
2771 * the framebuffer.
2772 *
2773 * Wait for compute shaders because of possible transitions:
2774 * - FB write -> shader read
2775 * - shader write -> FB read
2776 *
2777 * DB caches are flushed on demand (using si_decompress_textures).
2778 *
2779 * When MSAA is enabled, CB and TC caches are flushed on demand
2780 * (after FMASK decompression). Shader write -> FB read transitions
2781 * cannot happen for MSAA textures, because MSAA shader images are
2782 * not supported.
2783 *
2784 * Only flush and wait for CB if there is actually a bound color buffer.
2785 */
2786 if (sctx->framebuffer.uncompressed_cb_mask)
2787 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2788 sctx->framebuffer.CB_has_shader_readable_metadata);
2789
2790 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2791
2792 /* u_blitter doesn't invoke depth decompression when it does multiple
2793 * blits in a row, but the only case when it matters for DB is when
2794 * doing generate_mipmap. So here we flush DB manually between
2795 * individual generate_mipmap blits.
2796 * Note that lower mipmap levels aren't compressed.
2797 */
2798 if (sctx->generate_mipmap_for_depth) {
2799 si_make_DB_shader_coherent(sctx, 1, false,
2800 sctx->framebuffer.DB_has_shader_readable_metadata);
2801 } else if (sctx->b.chip_class == GFX9) {
2802 /* It appears that DB metadata "leaks" in a sequence of:
2803 * - depth clear
2804 * - DCC decompress for shader image writes (with DB disabled)
2805 * - render with DEPTH_BEFORE_SHADER=1
2806 * Flushing DB metadata works around the problem.
2807 */
2808 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2809 }
2810
2811 /* Take the maximum of the old and new count. If the new count is lower,
2812 * dirtying is needed to disable the unbound colorbuffers.
2813 */
2814 sctx->framebuffer.dirty_cbufs |=
2815 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2816 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2817
2818 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2819 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2820
2821 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2822 sctx->framebuffer.spi_shader_col_format = 0;
2823 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2824 sctx->framebuffer.spi_shader_col_format_blend = 0;
2825 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2826 sctx->framebuffer.color_is_int8 = 0;
2827 sctx->framebuffer.color_is_int10 = 0;
2828
2829 sctx->framebuffer.compressed_cb_mask = 0;
2830 sctx->framebuffer.uncompressed_cb_mask = 0;
2831 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2832 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2833 sctx->framebuffer.any_dst_linear = false;
2834 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2835 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2836
2837 for (i = 0; i < state->nr_cbufs; i++) {
2838 if (!state->cbufs[i])
2839 continue;
2840
2841 surf = (struct r600_surface*)state->cbufs[i];
2842 rtex = (struct r600_texture*)surf->base.texture;
2843
2844 if (!surf->color_initialized) {
2845 si_initialize_color_surface(sctx, surf);
2846 }
2847
2848 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2849 sctx->framebuffer.spi_shader_col_format |=
2850 surf->spi_shader_col_format << (i * 4);
2851 sctx->framebuffer.spi_shader_col_format_alpha |=
2852 surf->spi_shader_col_format_alpha << (i * 4);
2853 sctx->framebuffer.spi_shader_col_format_blend |=
2854 surf->spi_shader_col_format_blend << (i * 4);
2855 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2856 surf->spi_shader_col_format_blend_alpha << (i * 4);
2857
2858 if (surf->color_is_int8)
2859 sctx->framebuffer.color_is_int8 |= 1 << i;
2860 if (surf->color_is_int10)
2861 sctx->framebuffer.color_is_int10 |= 1 << i;
2862
2863 if (rtex->fmask.size)
2864 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2865 else
2866 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2867
2868 if (rtex->surface.is_linear)
2869 sctx->framebuffer.any_dst_linear = true;
2870
2871 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2872 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2873
2874 si_context_add_resource_size(ctx, surf->base.texture);
2875
2876 p_atomic_inc(&rtex->framebuffers_bound);
2877
2878 if (rtex->dcc_gather_statistics) {
2879 /* Dirty tracking must be enabled for DCC usage analysis. */
2880 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2881 vi_separate_dcc_start_query(ctx, rtex);
2882 }
2883 }
2884
2885 struct r600_texture *zstex = NULL;
2886
2887 if (state->zsbuf) {
2888 surf = (struct r600_surface*)state->zsbuf;
2889 zstex = (struct r600_texture*)surf->base.texture;
2890
2891 if (!surf->depth_initialized) {
2892 si_init_depth_surface(sctx, surf);
2893 }
2894
2895 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2896 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2897
2898 si_context_add_resource_size(ctx, surf->base.texture);
2899 }
2900
2901 si_update_ps_colorbuf0_slot(sctx);
2902 si_update_poly_offset_state(sctx);
2903 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2904 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2905
2906 if (sctx->screen->dpbb_allowed)
2907 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2908
2909 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2910 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2911
2912 if (sctx->screen->has_out_of_order_rast &&
2913 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2914 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2915 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2916 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2917
2918 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2919 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2920 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2921
2922 /* Set sample locations as fragment shader constants. */
2923 switch (sctx->framebuffer.nr_samples) {
2924 case 1:
2925 constbuf.user_buffer = sctx->sample_locations_1x;
2926 break;
2927 case 2:
2928 constbuf.user_buffer = sctx->sample_locations_2x;
2929 break;
2930 case 4:
2931 constbuf.user_buffer = sctx->sample_locations_4x;
2932 break;
2933 case 8:
2934 constbuf.user_buffer = sctx->sample_locations_8x;
2935 break;
2936 case 16:
2937 constbuf.user_buffer = sctx->sample_locations_16x;
2938 break;
2939 default:
2940 R600_ERR("Requested an invalid number of samples %i.\n",
2941 sctx->framebuffer.nr_samples);
2942 assert(0);
2943 }
2944 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2945 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2946
2947 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2948 }
2949
2950 sctx->do_update_shaders = true;
2951
2952 if (!sctx->decompression_enabled) {
2953 /* Prevent textures decompression when the framebuffer state
2954 * changes come from the decompression passes themselves.
2955 */
2956 sctx->need_check_render_feedback = true;
2957 }
2958 }
2959
2960 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2961 {
2962 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
2963 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2964 unsigned i, nr_cbufs = state->nr_cbufs;
2965 struct r600_texture *tex = NULL;
2966 struct r600_surface *cb = NULL;
2967 unsigned cb_color_info = 0;
2968
2969 /* Colorbuffers. */
2970 for (i = 0; i < nr_cbufs; i++) {
2971 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2972 unsigned cb_color_attrib;
2973
2974 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2975 continue;
2976
2977 cb = (struct r600_surface*)state->cbufs[i];
2978 if (!cb) {
2979 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2980 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2981 continue;
2982 }
2983
2984 tex = (struct r600_texture *)cb->base.texture;
2985 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
2986 &tex->resource, RADEON_USAGE_READWRITE,
2987 tex->resource.b.b.nr_samples > 1 ?
2988 RADEON_PRIO_COLOR_BUFFER_MSAA :
2989 RADEON_PRIO_COLOR_BUFFER);
2990
2991 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2992 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
2993 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2994 RADEON_PRIO_CMASK);
2995 }
2996
2997 if (tex->dcc_separate_buffer)
2998 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
2999 tex->dcc_separate_buffer,
3000 RADEON_USAGE_READWRITE,
3001 RADEON_PRIO_DCC);
3002
3003 /* Compute mutable surface parameters. */
3004 cb_color_base = tex->resource.gpu_address >> 8;
3005 cb_color_fmask = 0;
3006 cb_dcc_base = 0;
3007 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3008 cb_color_attrib = cb->cb_color_attrib;
3009
3010 if (tex->fmask.size) {
3011 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
3012 cb_color_fmask |= tex->fmask.tile_swizzle;
3013 }
3014
3015 /* Set up DCC. */
3016 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3017 bool is_msaa_resolve_dst = state->cbufs[0] &&
3018 state->cbufs[0]->texture->nr_samples > 1 &&
3019 state->cbufs[1] == &cb->base &&
3020 state->cbufs[1]->texture->nr_samples <= 1;
3021
3022 if (!is_msaa_resolve_dst)
3023 cb_color_info |= S_028C70_DCC_ENABLE(1);
3024
3025 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3026 tex->dcc_offset) >> 8;
3027 cb_dcc_base |= tex->surface.tile_swizzle;
3028 }
3029
3030 if (sctx->b.chip_class >= GFX9) {
3031 struct gfx9_surf_meta_flags meta;
3032
3033 if (tex->dcc_offset)
3034 meta = tex->surface.u.gfx9.dcc;
3035 else
3036 meta = tex->surface.u.gfx9.cmask;
3037
3038 /* Set mutable surface parameters. */
3039 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3040 cb_color_base |= tex->surface.tile_swizzle;
3041 if (!tex->fmask.size)
3042 cb_color_fmask = cb_color_base;
3043 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3044 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3045 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3046 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3047
3048 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3049 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3050 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3051 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3052 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3053 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3054 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3055 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3056 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3057 radeon_emit(cs, S_028C80_BASE_256B(tex->cmask.base_address_reg >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3058 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3059 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3060 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3061 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3062 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3063 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3064
3065 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3066 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3067 } else {
3068 /* Compute mutable surface parameters (SI-CI-VI). */
3069 const struct legacy_surf_level *level_info =
3070 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3071 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3072 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3073
3074 cb_color_base += level_info->offset >> 8;
3075 /* Only macrotiled modes can set tile swizzle. */
3076 if (level_info->mode == RADEON_SURF_MODE_2D)
3077 cb_color_base |= tex->surface.tile_swizzle;
3078
3079 if (!tex->fmask.size)
3080 cb_color_fmask = cb_color_base;
3081 if (cb_dcc_base)
3082 cb_dcc_base += level_info->dcc_offset >> 8;
3083
3084 pitch_tile_max = level_info->nblk_x / 8 - 1;
3085 slice_tile_max = level_info->nblk_x *
3086 level_info->nblk_y / 64 - 1;
3087 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3088
3089 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3090 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3091 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3092
3093 if (tex->fmask.size) {
3094 if (sctx->b.chip_class >= CIK)
3095 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3096 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3097 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3098 } else {
3099 /* This must be set for fast clear to work without FMASK. */
3100 if (sctx->b.chip_class >= CIK)
3101 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3102 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3103 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3104 }
3105
3106 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3107 sctx->b.chip_class >= VI ? 14 : 13);
3108 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3109 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3110 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3111 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3112 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3113 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3114 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3115 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3116 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3117 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3118 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3119 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3120 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3121
3122 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3123 radeon_emit(cs, cb_dcc_base);
3124 }
3125 }
3126 for (; i < 8 ; i++)
3127 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3128 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3129
3130 /* ZS buffer. */
3131 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3132 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3133 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3134
3135 radeon_add_to_buffer_list(sctx, sctx->b.gfx_cs,
3136 &rtex->resource, RADEON_USAGE_READWRITE,
3137 zb->base.texture->nr_samples > 1 ?
3138 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3139 RADEON_PRIO_DEPTH_BUFFER);
3140
3141 if (sctx->b.chip_class >= GFX9) {
3142 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3143 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3144 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3145 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3146
3147 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3148 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3149 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3150 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3151 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3152 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3153 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3154 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3155 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3156 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3157 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3158 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3159
3160 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3161 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3162 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3163 } else {
3164 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3165
3166 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3167 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3168 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3169 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3170 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3171 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3172 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3173 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3174 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3175 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3176 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3177 }
3178
3179 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3180 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3181 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3182
3183 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3184 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3185 } else if (sctx->framebuffer.dirty_zsbuf) {
3186 if (sctx->b.chip_class >= GFX9)
3187 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3188 else
3189 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3190
3191 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3192 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3193 }
3194
3195 /* Framebuffer dimensions. */
3196 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3197 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3198 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3199
3200 if (sctx->screen->dfsm_allowed) {
3201 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3202 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3203 }
3204
3205 sctx->framebuffer.dirty_cbufs = 0;
3206 sctx->framebuffer.dirty_zsbuf = false;
3207 }
3208
3209 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3210 struct r600_atom *atom)
3211 {
3212 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
3213 unsigned nr_samples = sctx->framebuffer.nr_samples;
3214 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3215
3216 /* Smoothing (only possible with nr_samples == 1) uses the same
3217 * sample locations as the MSAA it simulates.
3218 */
3219 if (nr_samples <= 1 && sctx->smoothing_enabled)
3220 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3221
3222 /* On Polaris, the small primitive filter uses the sample locations
3223 * even when MSAA is off, so we need to make sure they're set to 0.
3224 */
3225 if (has_msaa_sample_loc_bug)
3226 nr_samples = MAX2(nr_samples, 1);
3227
3228 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3229 sctx->msaa_sample_locs.nr_samples = nr_samples;
3230 si_emit_sample_locations(cs, nr_samples);
3231 }
3232
3233 if (sctx->b.family >= CHIP_POLARIS10) {
3234 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3235 unsigned small_prim_filter_cntl =
3236 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3237 /* line bug */
3238 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3239
3240 /* The alternative of setting sample locations to 0 would
3241 * require a DB flush to avoid Z errors, see
3242 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3243 */
3244 if (has_msaa_sample_loc_bug &&
3245 sctx->framebuffer.nr_samples > 1 &&
3246 rs && !rs->multisample_enable)
3247 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3248
3249 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3250 small_prim_filter_cntl);
3251 }
3252 }
3253
3254 static bool si_out_of_order_rasterization(struct si_context *sctx)
3255 {
3256 struct si_state_blend *blend = sctx->queued.named.blend;
3257 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3258
3259 if (!sctx->screen->has_out_of_order_rast)
3260 return false;
3261
3262 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3263
3264 if (blend) {
3265 colormask &= blend->cb_target_enabled_4bit;
3266 } else {
3267 colormask = 0;
3268 }
3269
3270 /* Conservative: No logic op. */
3271 if (colormask && blend->logicop_enable)
3272 return false;
3273
3274 struct si_dsa_order_invariance dsa_order_invariant = {
3275 .zs = true, .pass_set = true, .pass_last = false
3276 };
3277
3278 if (sctx->framebuffer.state.zsbuf) {
3279 struct r600_texture *zstex =
3280 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3281 bool has_stencil = zstex->surface.has_stencil;
3282 dsa_order_invariant = dsa->order_invariance[has_stencil];
3283 if (!dsa_order_invariant.zs)
3284 return false;
3285
3286 /* The set of PS invocations is always order invariant,
3287 * except when early Z/S tests are requested. */
3288 if (sctx->ps_shader.cso &&
3289 sctx->ps_shader.cso->info.writes_memory &&
3290 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3291 !dsa_order_invariant.pass_set)
3292 return false;
3293
3294 if (sctx->b.num_perfect_occlusion_queries != 0 &&
3295 !dsa_order_invariant.pass_set)
3296 return false;
3297 }
3298
3299 if (!colormask)
3300 return true;
3301
3302 unsigned blendmask = colormask & blend->blend_enable_4bit;
3303
3304 if (blendmask) {
3305 /* Only commutative blending. */
3306 if (blendmask & ~blend->commutative_4bit)
3307 return false;
3308
3309 if (!dsa_order_invariant.pass_set)
3310 return false;
3311 }
3312
3313 if (colormask & ~blendmask) {
3314 if (!dsa_order_invariant.pass_last)
3315 return false;
3316 }
3317
3318 return true;
3319 }
3320
3321 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3322 {
3323 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
3324 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3325 /* 33% faster rendering to linear color buffers */
3326 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3327 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3328 unsigned sc_mode_cntl_1 =
3329 S_028A4C_WALK_SIZE(dst_is_linear) |
3330 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3331 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3332 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3333 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3334 /* always 1: */
3335 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3336 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3337 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3338 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3339 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3340 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3341
3342 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3343 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3344
3345 /* Required by OpenGL line rasterization.
3346 *
3347 * TODO: We should also enable perpendicular endcaps for AA lines,
3348 * but that requires implementing line stippling in the pixel
3349 * shader. SC can only do line stippling with axis-aligned
3350 * endcaps.
3351 */
3352 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3353
3354 if (setup_samples > 1) {
3355 /* distance from the pixel center, indexed by log2(nr_samples) */
3356 static unsigned max_dist[] = {
3357 0, /* unused */
3358 4, /* 2x MSAA */
3359 6, /* 4x MSAA */
3360 7, /* 8x MSAA */
3361 8, /* 16x MSAA */
3362 };
3363 unsigned log_samples = util_logbase2(setup_samples);
3364 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3365 unsigned log_ps_iter_samples =
3366 util_logbase2(util_next_power_of_two(ps_iter_samples));
3367
3368 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3369 radeon_emit(cs, sc_line_cntl |
3370 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3371 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3372 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3373 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3374
3375 if (sctx->framebuffer.nr_samples > 1) {
3376 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3377 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3378 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3379 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3380 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3381 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3382 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3383 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3384 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3385 sc_mode_cntl_1);
3386 } else if (sctx->smoothing_enabled) {
3387 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3388 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3389 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3390 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3391 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3392 sc_mode_cntl_1);
3393 }
3394 } else {
3395 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3396 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3397 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3398
3399 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3400 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3401 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3402 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3403 sc_mode_cntl_1);
3404 }
3405
3406 /* GFX9: Flush DFSM when the AA mode changes. */
3407 if (sctx->screen->dfsm_allowed) {
3408 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3409 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3410 }
3411 }
3412
3413 void si_update_ps_iter_samples(struct si_context *sctx)
3414 {
3415 if (sctx->framebuffer.nr_samples > 1)
3416 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3417 if (sctx->screen->dpbb_allowed)
3418 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3419 }
3420
3421 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3422 {
3423 struct si_context *sctx = (struct si_context *)ctx;
3424
3425 if (sctx->ps_iter_samples == min_samples)
3426 return;
3427
3428 sctx->ps_iter_samples = min_samples;
3429 sctx->do_update_shaders = true;
3430
3431 si_update_ps_iter_samples(sctx);
3432 }
3433
3434 /*
3435 * Samplers
3436 */
3437
3438 /**
3439 * Build the sampler view descriptor for a buffer texture.
3440 * @param state 256-bit descriptor; only the high 128 bits are filled in
3441 */
3442 void
3443 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3444 enum pipe_format format,
3445 unsigned offset, unsigned size,
3446 uint32_t *state)
3447 {
3448 const struct util_format_description *desc;
3449 int first_non_void;
3450 unsigned stride;
3451 unsigned num_records;
3452 unsigned num_format, data_format;
3453
3454 desc = util_format_description(format);
3455 first_non_void = util_format_get_first_non_void_channel(format);
3456 stride = desc->block.bits / 8;
3457 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3458 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3459
3460 num_records = size / stride;
3461 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3462
3463 /* The NUM_RECORDS field has a different meaning depending on the chip,
3464 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3465 *
3466 * SI-CIK:
3467 * - If STRIDE == 0, it's in byte units.
3468 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3469 *
3470 * VI:
3471 * - For SMEM and STRIDE == 0, it's in byte units.
3472 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3473 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3474 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3475 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3476 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3477 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3478 * That way the same descriptor can be used by both SMEM and VMEM.
3479 *
3480 * GFX9:
3481 * - For SMEM and STRIDE == 0, it's in byte units.
3482 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3483 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3484 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3485 */
3486 if (screen->info.chip_class >= GFX9)
3487 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3488 * from STRIDE to bytes. This works around it by setting
3489 * NUM_RECORDS to at least the size of one element, so that
3490 * the first element is readable when IDXEN == 0.
3491 *
3492 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3493 * IDXEN is enforced?
3494 */
3495 num_records = num_records ? MAX2(num_records, stride) : 0;
3496 else if (screen->info.chip_class == VI)
3497 num_records *= stride;
3498
3499 state[4] = 0;
3500 state[5] = S_008F04_STRIDE(stride);
3501 state[6] = num_records;
3502 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3503 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3504 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3505 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3506 S_008F0C_NUM_FORMAT(num_format) |
3507 S_008F0C_DATA_FORMAT(data_format);
3508 }
3509
3510 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3511 {
3512 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3513
3514 if (swizzle[3] == PIPE_SWIZZLE_X) {
3515 /* For the pre-defined border color values (white, opaque
3516 * black, transparent black), the only thing that matters is
3517 * that the alpha channel winds up in the correct place
3518 * (because the RGB channels are all the same) so either of
3519 * these enumerations will work.
3520 */
3521 if (swizzle[2] == PIPE_SWIZZLE_Y)
3522 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3523 else
3524 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3525 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3526 if (swizzle[1] == PIPE_SWIZZLE_Y)
3527 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3528 else
3529 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3530 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3531 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3532 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3533 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3534 }
3535
3536 return bc_swizzle;
3537 }
3538
3539 /**
3540 * Build the sampler view descriptor for a texture.
3541 */
3542 void
3543 si_make_texture_descriptor(struct si_screen *screen,
3544 struct r600_texture *tex,
3545 bool sampler,
3546 enum pipe_texture_target target,
3547 enum pipe_format pipe_format,
3548 const unsigned char state_swizzle[4],
3549 unsigned first_level, unsigned last_level,
3550 unsigned first_layer, unsigned last_layer,
3551 unsigned width, unsigned height, unsigned depth,
3552 uint32_t *state,
3553 uint32_t *fmask_state)
3554 {
3555 struct pipe_resource *res = &tex->resource.b.b;
3556 const struct util_format_description *desc;
3557 unsigned char swizzle[4];
3558 int first_non_void;
3559 unsigned num_format, data_format, type;
3560 uint64_t va;
3561
3562 desc = util_format_description(pipe_format);
3563
3564 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3565 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3566 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3567 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3568
3569 switch (pipe_format) {
3570 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3571 case PIPE_FORMAT_X32_S8X24_UINT:
3572 case PIPE_FORMAT_X8Z24_UNORM:
3573 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3574 break;
3575 case PIPE_FORMAT_X24S8_UINT:
3576 /*
3577 * X24S8 is implemented as an 8_8_8_8 data format, to
3578 * fix texture gathers. This affects at least
3579 * GL45-CTS.texture_cube_map_array.sampling on VI.
3580 */
3581 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3582 break;
3583 default:
3584 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3585 }
3586 } else {
3587 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3588 }
3589
3590 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3591
3592 switch (pipe_format) {
3593 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3594 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3595 break;
3596 default:
3597 if (first_non_void < 0) {
3598 if (util_format_is_compressed(pipe_format)) {
3599 switch (pipe_format) {
3600 case PIPE_FORMAT_DXT1_SRGB:
3601 case PIPE_FORMAT_DXT1_SRGBA:
3602 case PIPE_FORMAT_DXT3_SRGBA:
3603 case PIPE_FORMAT_DXT5_SRGBA:
3604 case PIPE_FORMAT_BPTC_SRGBA:
3605 case PIPE_FORMAT_ETC2_SRGB8:
3606 case PIPE_FORMAT_ETC2_SRGB8A1:
3607 case PIPE_FORMAT_ETC2_SRGBA8:
3608 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3609 break;
3610 case PIPE_FORMAT_RGTC1_SNORM:
3611 case PIPE_FORMAT_LATC1_SNORM:
3612 case PIPE_FORMAT_RGTC2_SNORM:
3613 case PIPE_FORMAT_LATC2_SNORM:
3614 case PIPE_FORMAT_ETC2_R11_SNORM:
3615 case PIPE_FORMAT_ETC2_RG11_SNORM:
3616 /* implies float, so use SNORM/UNORM to determine
3617 whether data is signed or not */
3618 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3619 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3620 break;
3621 default:
3622 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3623 break;
3624 }
3625 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3626 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3627 } else {
3628 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3629 }
3630 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3631 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3632 } else {
3633 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3634
3635 switch (desc->channel[first_non_void].type) {
3636 case UTIL_FORMAT_TYPE_FLOAT:
3637 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3638 break;
3639 case UTIL_FORMAT_TYPE_SIGNED:
3640 if (desc->channel[first_non_void].normalized)
3641 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3642 else if (desc->channel[first_non_void].pure_integer)
3643 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3644 else
3645 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3646 break;
3647 case UTIL_FORMAT_TYPE_UNSIGNED:
3648 if (desc->channel[first_non_void].normalized)
3649 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3650 else if (desc->channel[first_non_void].pure_integer)
3651 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3652 else
3653 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3654 }
3655 }
3656 }
3657
3658 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3659 if (data_format == ~0) {
3660 data_format = 0;
3661 }
3662
3663 /* S8 with Z32 HTILE needs a special format. */
3664 if (screen->info.chip_class >= GFX9 &&
3665 pipe_format == PIPE_FORMAT_S8_UINT &&
3666 tex->tc_compatible_htile)
3667 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3668
3669 if (!sampler &&
3670 (res->target == PIPE_TEXTURE_CUBE ||
3671 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3672 (screen->info.chip_class <= VI &&
3673 res->target == PIPE_TEXTURE_3D))) {
3674 /* For the purpose of shader images, treat cube maps and 3D
3675 * textures as 2D arrays. For 3D textures, the address
3676 * calculations for mipmaps are different, so we rely on the
3677 * caller to effectively disable mipmaps.
3678 */
3679 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3680
3681 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3682 } else {
3683 type = si_tex_dim(screen, tex, target, res->nr_samples);
3684 }
3685
3686 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3687 height = 1;
3688 depth = res->array_size;
3689 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3690 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3691 if (sampler || res->target != PIPE_TEXTURE_3D)
3692 depth = res->array_size;
3693 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3694 depth = res->array_size / 6;
3695
3696 state[0] = 0;
3697 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3698 S_008F14_NUM_FORMAT_GFX6(num_format));
3699 state[2] = (S_008F18_WIDTH(width - 1) |
3700 S_008F18_HEIGHT(height - 1) |
3701 S_008F18_PERF_MOD(4));
3702 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3703 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3704 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3705 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3706 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3707 0 : first_level) |
3708 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3709 util_logbase2(res->nr_samples) :
3710 last_level) |
3711 S_008F1C_TYPE(type));
3712 state[4] = 0;
3713 state[5] = S_008F24_BASE_ARRAY(first_layer);
3714 state[6] = 0;
3715 state[7] = 0;
3716
3717 if (screen->info.chip_class >= GFX9) {
3718 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3719
3720 /* Depth is the the last accessible layer on Gfx9.
3721 * The hw doesn't need to know the total number of layers.
3722 */
3723 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3724 state[4] |= S_008F20_DEPTH(depth - 1);
3725 else
3726 state[4] |= S_008F20_DEPTH(last_layer);
3727
3728 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3729 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3730 util_logbase2(res->nr_samples) :
3731 tex->resource.b.b.last_level);
3732 } else {
3733 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3734 state[4] |= S_008F20_DEPTH(depth - 1);
3735 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3736 }
3737
3738 if (tex->dcc_offset) {
3739 unsigned swap = si_translate_colorswap(pipe_format, false);
3740
3741 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3742 } else {
3743 /* The last dword is unused by hw. The shader uses it to clear
3744 * bits in the first dword of sampler state.
3745 */
3746 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3747 if (first_level == last_level)
3748 state[7] = C_008F30_MAX_ANISO_RATIO;
3749 else
3750 state[7] = 0xffffffff;
3751 }
3752 }
3753
3754 /* Initialize the sampler view for FMASK. */
3755 if (tex->fmask.size) {
3756 uint32_t data_format, num_format;
3757
3758 va = tex->resource.gpu_address + tex->fmask.offset;
3759
3760 if (screen->info.chip_class >= GFX9) {
3761 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3762 switch (res->nr_samples) {
3763 case 2:
3764 num_format = V_008F14_IMG_FMASK_8_2_2;
3765 break;
3766 case 4:
3767 num_format = V_008F14_IMG_FMASK_8_4_4;
3768 break;
3769 case 8:
3770 num_format = V_008F14_IMG_FMASK_32_8_8;
3771 break;
3772 default:
3773 unreachable("invalid nr_samples");
3774 }
3775 } else {
3776 switch (res->nr_samples) {
3777 case 2:
3778 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3779 break;
3780 case 4:
3781 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3782 break;
3783 case 8:
3784 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3785 break;
3786 default:
3787 unreachable("invalid nr_samples");
3788 }
3789 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3790 }
3791
3792 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3793 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3794 S_008F14_DATA_FORMAT_GFX6(data_format) |
3795 S_008F14_NUM_FORMAT_GFX6(num_format);
3796 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3797 S_008F18_HEIGHT(height - 1);
3798 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3799 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3800 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3801 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3802 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3803 fmask_state[4] = 0;
3804 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3805 fmask_state[6] = 0;
3806 fmask_state[7] = 0;
3807
3808 if (screen->info.chip_class >= GFX9) {
3809 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3810 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3811 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3812 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3813 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3814 } else {
3815 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3816 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3817 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3818 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3819 }
3820 }
3821 }
3822
3823 /**
3824 * Create a sampler view.
3825 *
3826 * @param ctx context
3827 * @param texture texture
3828 * @param state sampler view template
3829 * @param width0 width0 override (for compressed textures as int)
3830 * @param height0 height0 override (for compressed textures as int)
3831 * @param force_level set the base address to the level (for compressed textures)
3832 */
3833 struct pipe_sampler_view *
3834 si_create_sampler_view_custom(struct pipe_context *ctx,
3835 struct pipe_resource *texture,
3836 const struct pipe_sampler_view *state,
3837 unsigned width0, unsigned height0,
3838 unsigned force_level)
3839 {
3840 struct si_context *sctx = (struct si_context*)ctx;
3841 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3842 struct r600_texture *tmp = (struct r600_texture*)texture;
3843 unsigned base_level, first_level, last_level;
3844 unsigned char state_swizzle[4];
3845 unsigned height, depth, width;
3846 unsigned last_layer = state->u.tex.last_layer;
3847 enum pipe_format pipe_format;
3848 const struct legacy_surf_level *surflevel;
3849
3850 if (!view)
3851 return NULL;
3852
3853 /* initialize base object */
3854 view->base = *state;
3855 view->base.texture = NULL;
3856 view->base.reference.count = 1;
3857 view->base.context = ctx;
3858
3859 assert(texture);
3860 pipe_resource_reference(&view->base.texture, texture);
3861
3862 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3863 state->format == PIPE_FORMAT_S8X24_UINT ||
3864 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3865 state->format == PIPE_FORMAT_S8_UINT)
3866 view->is_stencil_sampler = true;
3867
3868 /* Buffer resource. */
3869 if (texture->target == PIPE_BUFFER) {
3870 si_make_buffer_descriptor(sctx->screen,
3871 (struct r600_resource *)texture,
3872 state->format,
3873 state->u.buf.offset,
3874 state->u.buf.size,
3875 view->state);
3876 return &view->base;
3877 }
3878
3879 state_swizzle[0] = state->swizzle_r;
3880 state_swizzle[1] = state->swizzle_g;
3881 state_swizzle[2] = state->swizzle_b;
3882 state_swizzle[3] = state->swizzle_a;
3883
3884 base_level = 0;
3885 first_level = state->u.tex.first_level;
3886 last_level = state->u.tex.last_level;
3887 width = width0;
3888 height = height0;
3889 depth = texture->depth0;
3890
3891 if (sctx->b.chip_class <= VI && force_level) {
3892 assert(force_level == first_level &&
3893 force_level == last_level);
3894 base_level = force_level;
3895 first_level = 0;
3896 last_level = 0;
3897 width = u_minify(width, force_level);
3898 height = u_minify(height, force_level);
3899 depth = u_minify(depth, force_level);
3900 }
3901
3902 /* This is not needed if state trackers set last_layer correctly. */
3903 if (state->target == PIPE_TEXTURE_1D ||
3904 state->target == PIPE_TEXTURE_2D ||
3905 state->target == PIPE_TEXTURE_RECT ||
3906 state->target == PIPE_TEXTURE_CUBE)
3907 last_layer = state->u.tex.first_layer;
3908
3909 /* Texturing with separate depth and stencil. */
3910 pipe_format = state->format;
3911
3912 /* Depth/stencil texturing sometimes needs separate texture. */
3913 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
3914 if (!tmp->flushed_depth_texture &&
3915 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3916 pipe_resource_reference(&view->base.texture, NULL);
3917 FREE(view);
3918 return NULL;
3919 }
3920
3921 assert(tmp->flushed_depth_texture);
3922
3923 /* Override format for the case where the flushed texture
3924 * contains only Z or only S.
3925 */
3926 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3927 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3928
3929 tmp = tmp->flushed_depth_texture;
3930 }
3931
3932 surflevel = tmp->surface.u.legacy.level;
3933
3934 if (tmp->db_compatible) {
3935 if (!view->is_stencil_sampler)
3936 pipe_format = tmp->db_render_format;
3937
3938 switch (pipe_format) {
3939 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3940 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3941 break;
3942 case PIPE_FORMAT_X8Z24_UNORM:
3943 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3944 /* Z24 is always stored like this for DB
3945 * compatibility.
3946 */
3947 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3948 break;
3949 case PIPE_FORMAT_X24S8_UINT:
3950 case PIPE_FORMAT_S8X24_UINT:
3951 case PIPE_FORMAT_X32_S8X24_UINT:
3952 pipe_format = PIPE_FORMAT_S8_UINT;
3953 surflevel = tmp->surface.u.legacy.stencil_level;
3954 break;
3955 default:;
3956 }
3957 }
3958
3959 view->dcc_incompatible =
3960 vi_dcc_formats_are_incompatible(texture,
3961 state->u.tex.first_level,
3962 state->format);
3963
3964 si_make_texture_descriptor(sctx->screen, tmp, true,
3965 state->target, pipe_format, state_swizzle,
3966 first_level, last_level,
3967 state->u.tex.first_layer, last_layer,
3968 width, height, depth,
3969 view->state, view->fmask_state);
3970
3971 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3972 view->is_integer =
3973 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3974 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3975 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3976 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3977 view->base_level_info = &surflevel[base_level];
3978 view->base_level = base_level;
3979 view->block_width = util_format_get_blockwidth(pipe_format);
3980 return &view->base;
3981 }
3982
3983 static struct pipe_sampler_view *
3984 si_create_sampler_view(struct pipe_context *ctx,
3985 struct pipe_resource *texture,
3986 const struct pipe_sampler_view *state)
3987 {
3988 return si_create_sampler_view_custom(ctx, texture, state,
3989 texture ? texture->width0 : 0,
3990 texture ? texture->height0 : 0, 0);
3991 }
3992
3993 static void si_sampler_view_destroy(struct pipe_context *ctx,
3994 struct pipe_sampler_view *state)
3995 {
3996 struct si_sampler_view *view = (struct si_sampler_view *)state;
3997
3998 pipe_resource_reference(&state->texture, NULL);
3999 FREE(view);
4000 }
4001
4002 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4003 {
4004 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4005 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4006 (linear_filter &&
4007 (wrap == PIPE_TEX_WRAP_CLAMP ||
4008 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4009 }
4010
4011 static uint32_t si_translate_border_color(struct si_context *sctx,
4012 const struct pipe_sampler_state *state,
4013 const union pipe_color_union *color,
4014 bool is_integer)
4015 {
4016 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4017 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4018
4019 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4020 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4021 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4022 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4023
4024 #define simple_border_types(elt) \
4025 do { \
4026 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4027 color->elt[2] == 0 && color->elt[3] == 0) \
4028 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4029 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4030 color->elt[2] == 0 && color->elt[3] == 1) \
4031 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4032 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4033 color->elt[2] == 1 && color->elt[3] == 1) \
4034 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4035 } while (false)
4036
4037 if (is_integer)
4038 simple_border_types(ui);
4039 else
4040 simple_border_types(f);
4041
4042 #undef simple_border_types
4043
4044 int i;
4045
4046 /* Check if the border has been uploaded already. */
4047 for (i = 0; i < sctx->border_color_count; i++)
4048 if (memcmp(&sctx->border_color_table[i], color,
4049 sizeof(*color)) == 0)
4050 break;
4051
4052 if (i >= SI_MAX_BORDER_COLORS) {
4053 /* Getting 4096 unique border colors is very unlikely. */
4054 fprintf(stderr, "radeonsi: The border color table is full. "
4055 "Any new border colors will be just black. "
4056 "Please file a bug.\n");
4057 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4058 }
4059
4060 if (i == sctx->border_color_count) {
4061 /* Upload a new border color. */
4062 memcpy(&sctx->border_color_table[i], color,
4063 sizeof(*color));
4064 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4065 color, sizeof(*color));
4066 sctx->border_color_count++;
4067 }
4068
4069 return S_008F3C_BORDER_COLOR_PTR(i) |
4070 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4071 }
4072
4073 static inline int S_FIXED(float value, unsigned frac_bits)
4074 {
4075 return value * (1 << frac_bits);
4076 }
4077
4078 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4079 {
4080 if (filter == PIPE_TEX_FILTER_LINEAR)
4081 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4082 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4083 else
4084 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4085 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4086 }
4087
4088 static inline unsigned si_tex_aniso_filter(unsigned filter)
4089 {
4090 if (filter < 2)
4091 return 0;
4092 if (filter < 4)
4093 return 1;
4094 if (filter < 8)
4095 return 2;
4096 if (filter < 16)
4097 return 3;
4098 return 4;
4099 }
4100
4101 static void *si_create_sampler_state(struct pipe_context *ctx,
4102 const struct pipe_sampler_state *state)
4103 {
4104 struct si_context *sctx = (struct si_context *)ctx;
4105 struct si_screen *sscreen = sctx->screen;
4106 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4107 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4108 : state->max_anisotropy;
4109 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4110 union pipe_color_union clamped_border_color;
4111
4112 if (!rstate) {
4113 return NULL;
4114 }
4115
4116 #ifdef DEBUG
4117 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4118 #endif
4119 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4120 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4121 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4122 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4123 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4124 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4125 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4126 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4127 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4128 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
4129 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4130 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4131 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4132 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4133 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4134 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4135 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4136 S_008F38_MIP_POINT_PRECLAMP(0) |
4137 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
4138 S_008F38_FILTER_PREC_FIX(1) |
4139 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
4140 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4141
4142 /* Create sampler resource for integer textures. */
4143 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4144 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4145
4146 /* Create sampler resource for upgraded depth textures. */
4147 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4148
4149 for (unsigned i = 0; i < 4; ++i) {
4150 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4151 * when the border color is 1.0. */
4152 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4153 }
4154
4155 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4156 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4157 else
4158 rstate->upgraded_depth_val[3] =
4159 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4160 S_008F3C_UPGRADED_DEPTH(1);
4161
4162 return rstate;
4163 }
4164
4165 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4166 {
4167 struct si_context *sctx = (struct si_context *)ctx;
4168
4169 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4170 return;
4171
4172 sctx->sample_mask.sample_mask = sample_mask;
4173 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4174 }
4175
4176 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4177 {
4178 struct radeon_winsys_cs *cs = sctx->b.gfx_cs;
4179 unsigned mask = sctx->sample_mask.sample_mask;
4180
4181 /* Needed for line and polygon smoothing as well as for the Polaris
4182 * small primitive filter. We expect the state tracker to take care of
4183 * this for us.
4184 */
4185 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4186 (mask & 1 && sctx->blitter->running));
4187
4188 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4189 radeon_emit(cs, mask | (mask << 16));
4190 radeon_emit(cs, mask | (mask << 16));
4191 }
4192
4193 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4194 {
4195 #ifdef DEBUG
4196 struct si_sampler_state *s = state;
4197
4198 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4199 s->magic = 0;
4200 #endif
4201 free(state);
4202 }
4203
4204 /*
4205 * Vertex elements & buffers
4206 */
4207
4208 static void *si_create_vertex_elements(struct pipe_context *ctx,
4209 unsigned count,
4210 const struct pipe_vertex_element *elements)
4211 {
4212 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4213 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4214 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4215 int i;
4216
4217 assert(count <= SI_MAX_ATTRIBS);
4218 if (!v)
4219 return NULL;
4220
4221 v->count = count;
4222 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4223
4224 for (i = 0; i < count; ++i) {
4225 const struct util_format_description *desc;
4226 const struct util_format_channel_description *channel;
4227 unsigned data_format, num_format;
4228 int first_non_void;
4229 unsigned vbo_index = elements[i].vertex_buffer_index;
4230 unsigned char swizzle[4];
4231
4232 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4233 FREE(v);
4234 return NULL;
4235 }
4236
4237 if (elements[i].instance_divisor) {
4238 v->uses_instance_divisors = true;
4239 v->instance_divisors[i] = elements[i].instance_divisor;
4240
4241 if (v->instance_divisors[i] == 1)
4242 v->instance_divisor_is_one |= 1u << i;
4243 else
4244 v->instance_divisor_is_fetched |= 1u << i;
4245 }
4246
4247 if (!used[vbo_index]) {
4248 v->first_vb_use_mask |= 1 << i;
4249 used[vbo_index] = true;
4250 }
4251
4252 desc = util_format_description(elements[i].src_format);
4253 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4254 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4255 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4256 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4257 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4258
4259 v->format_size[i] = desc->block.bits / 8;
4260 v->src_offset[i] = elements[i].src_offset;
4261 v->vertex_buffer_index[i] = vbo_index;
4262
4263 /* The hardware always treats the 2-bit alpha channel as
4264 * unsigned, so a shader workaround is needed. The affected
4265 * chips are VI and older except Stoney (GFX8.1).
4266 */
4267 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4268 sscreen->info.chip_class <= VI &&
4269 sscreen->info.family != CHIP_STONEY) {
4270 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4271 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4272 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4273 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4274 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4275 /* This isn't actually used in OpenGL. */
4276 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4277 }
4278 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4279 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4280 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4281 else
4282 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4283 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4284 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4285 if (channel->normalized) {
4286 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4287 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4288 else
4289 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4290 } else {
4291 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4292 }
4293 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4294 if (channel->normalized) {
4295 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4296 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4297 else
4298 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4299 } else {
4300 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4301 }
4302 }
4303 } else if (channel && channel->size == 64 &&
4304 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4305 switch (desc->nr_channels) {
4306 case 1:
4307 case 2:
4308 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4309 swizzle[0] = PIPE_SWIZZLE_X;
4310 swizzle[1] = PIPE_SWIZZLE_Y;
4311 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4312 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4313 break;
4314 case 3:
4315 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4316 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4317 swizzle[1] = PIPE_SWIZZLE_Y;
4318 swizzle[2] = PIPE_SWIZZLE_0;
4319 swizzle[3] = PIPE_SWIZZLE_0;
4320 break;
4321 case 4:
4322 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4323 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4324 swizzle[1] = PIPE_SWIZZLE_Y;
4325 swizzle[2] = PIPE_SWIZZLE_Z;
4326 swizzle[3] = PIPE_SWIZZLE_W;
4327 break;
4328 default:
4329 assert(0);
4330 }
4331 } else if (channel && desc->nr_channels == 3) {
4332 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4333
4334 if (channel->size == 8) {
4335 if (channel->pure_integer)
4336 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4337 else
4338 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4339 } else if (channel->size == 16) {
4340 if (channel->pure_integer)
4341 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4342 else
4343 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4344 }
4345 }
4346
4347 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4348 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4349 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4350 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4351 S_008F0C_NUM_FORMAT(num_format) |
4352 S_008F0C_DATA_FORMAT(data_format);
4353 }
4354 return v;
4355 }
4356
4357 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4358 {
4359 struct si_context *sctx = (struct si_context *)ctx;
4360 struct si_vertex_elements *old = sctx->vertex_elements;
4361 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4362
4363 sctx->vertex_elements = v;
4364 sctx->vertex_buffers_dirty = true;
4365
4366 if (v &&
4367 (!old ||
4368 old->count != v->count ||
4369 old->uses_instance_divisors != v->uses_instance_divisors ||
4370 v->uses_instance_divisors || /* we don't check which divisors changed */
4371 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4372 sctx->do_update_shaders = true;
4373
4374 if (v && v->instance_divisor_is_fetched) {
4375 struct pipe_constant_buffer cb;
4376
4377 cb.buffer = NULL;
4378 cb.user_buffer = v->instance_divisors;
4379 cb.buffer_offset = 0;
4380 cb.buffer_size = sizeof(uint32_t) * v->count;
4381 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4382 }
4383 }
4384
4385 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4386 {
4387 struct si_context *sctx = (struct si_context *)ctx;
4388
4389 if (sctx->vertex_elements == state)
4390 sctx->vertex_elements = NULL;
4391 FREE(state);
4392 }
4393
4394 static void si_set_vertex_buffers(struct pipe_context *ctx,
4395 unsigned start_slot, unsigned count,
4396 const struct pipe_vertex_buffer *buffers)
4397 {
4398 struct si_context *sctx = (struct si_context *)ctx;
4399 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4400 int i;
4401
4402 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4403
4404 if (buffers) {
4405 for (i = 0; i < count; i++) {
4406 const struct pipe_vertex_buffer *src = buffers + i;
4407 struct pipe_vertex_buffer *dsti = dst + i;
4408 struct pipe_resource *buf = src->buffer.resource;
4409
4410 pipe_resource_reference(&dsti->buffer.resource, buf);
4411 dsti->buffer_offset = src->buffer_offset;
4412 dsti->stride = src->stride;
4413 si_context_add_resource_size(ctx, buf);
4414 if (buf)
4415 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4416 }
4417 } else {
4418 for (i = 0; i < count; i++) {
4419 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4420 }
4421 }
4422 sctx->vertex_buffers_dirty = true;
4423 }
4424
4425 /*
4426 * Misc
4427 */
4428
4429 static void si_set_tess_state(struct pipe_context *ctx,
4430 const float default_outer_level[4],
4431 const float default_inner_level[2])
4432 {
4433 struct si_context *sctx = (struct si_context *)ctx;
4434 struct pipe_constant_buffer cb;
4435 float array[8];
4436
4437 memcpy(array, default_outer_level, sizeof(float) * 4);
4438 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4439
4440 cb.buffer = NULL;
4441 cb.user_buffer = NULL;
4442 cb.buffer_size = sizeof(array);
4443
4444 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4445 (void*)array, sizeof(array),
4446 &cb.buffer_offset);
4447
4448 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4449 pipe_resource_reference(&cb.buffer, NULL);
4450 }
4451
4452 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4453 {
4454 struct si_context *sctx = (struct si_context *)ctx;
4455
4456 si_update_fb_dirtiness_after_rendering(sctx);
4457
4458 /* Multisample surfaces are flushed in si_decompress_textures. */
4459 if (sctx->framebuffer.uncompressed_cb_mask)
4460 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4461 sctx->framebuffer.CB_has_shader_readable_metadata);
4462 }
4463
4464 /* This only ensures coherency for shader image/buffer stores. */
4465 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4466 {
4467 struct si_context *sctx = (struct si_context *)ctx;
4468
4469 /* Subsequent commands must wait for all shader invocations to
4470 * complete. */
4471 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4472 SI_CONTEXT_CS_PARTIAL_FLUSH;
4473
4474 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4475 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4476 SI_CONTEXT_INV_VMEM_L1;
4477
4478 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4479 PIPE_BARRIER_SHADER_BUFFER |
4480 PIPE_BARRIER_TEXTURE |
4481 PIPE_BARRIER_IMAGE |
4482 PIPE_BARRIER_STREAMOUT_BUFFER |
4483 PIPE_BARRIER_GLOBAL_BUFFER)) {
4484 /* As far as I can tell, L1 contents are written back to L2
4485 * automatically at end of shader, but the contents of other
4486 * L1 caches might still be stale. */
4487 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4488 }
4489
4490 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4491 /* Indices are read through TC L2 since VI.
4492 * L1 isn't used.
4493 */
4494 if (sctx->screen->info.chip_class <= CIK)
4495 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4496 }
4497
4498 /* MSAA color, any depth and any stencil are flushed in
4499 * si_decompress_textures when needed.
4500 */
4501 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4502 sctx->framebuffer.uncompressed_cb_mask) {
4503 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4504
4505 if (sctx->b.chip_class <= VI)
4506 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4507 }
4508
4509 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4510 if (sctx->screen->info.chip_class <= VI &&
4511 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4512 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4513 }
4514
4515 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4516 {
4517 struct pipe_blend_state blend;
4518
4519 memset(&blend, 0, sizeof(blend));
4520 blend.independent_blend_enable = true;
4521 blend.rt[0].colormask = 0xf;
4522 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4523 }
4524
4525 static void si_init_config(struct si_context *sctx);
4526
4527 void si_init_state_functions(struct si_context *sctx)
4528 {
4529 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4530 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4531 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4532 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4533 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4534
4535 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4536 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4537 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4538 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4539 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4540 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4541 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4542 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4543 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4544 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4545 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4546
4547 sctx->b.b.create_blend_state = si_create_blend_state;
4548 sctx->b.b.bind_blend_state = si_bind_blend_state;
4549 sctx->b.b.delete_blend_state = si_delete_blend_state;
4550 sctx->b.b.set_blend_color = si_set_blend_color;
4551
4552 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4553 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4554 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4555
4556 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4557 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4558 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4559
4560 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4561 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4562 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4563 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4564 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4565
4566 sctx->b.b.set_clip_state = si_set_clip_state;
4567 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4568
4569 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4570
4571 sctx->b.b.create_sampler_state = si_create_sampler_state;
4572 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4573
4574 sctx->b.b.create_sampler_view = si_create_sampler_view;
4575 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4576
4577 sctx->b.b.set_sample_mask = si_set_sample_mask;
4578
4579 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4580 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4581 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4582 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4583
4584 sctx->b.b.texture_barrier = si_texture_barrier;
4585 sctx->b.b.memory_barrier = si_memory_barrier;
4586 sctx->b.b.set_min_samples = si_set_min_samples;
4587 sctx->b.b.set_tess_state = si_set_tess_state;
4588
4589 sctx->b.b.set_active_query_state = si_set_active_query_state;
4590
4591 sctx->b.b.draw_vbo = si_draw_vbo;
4592
4593 si_init_config(sctx);
4594 }
4595
4596 void si_init_screen_state_functions(struct si_screen *sscreen)
4597 {
4598 sscreen->b.is_format_supported = si_is_format_supported;
4599 }
4600
4601 static void si_set_grbm_gfx_index(struct si_context *sctx,
4602 struct si_pm4_state *pm4, unsigned value)
4603 {
4604 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4605 R_00802C_GRBM_GFX_INDEX;
4606 si_pm4_set_reg(pm4, reg, value);
4607 }
4608
4609 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4610 struct si_pm4_state *pm4, unsigned se)
4611 {
4612 assert(se == ~0 || se < sctx->screen->info.max_se);
4613 si_set_grbm_gfx_index(sctx, pm4,
4614 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4615 S_030800_SE_INDEX(se)) |
4616 S_030800_SH_BROADCAST_WRITES(1) |
4617 S_030800_INSTANCE_BROADCAST_WRITES(1));
4618 }
4619
4620 static void
4621 si_write_harvested_raster_configs(struct si_context *sctx,
4622 struct si_pm4_state *pm4,
4623 unsigned raster_config,
4624 unsigned raster_config_1)
4625 {
4626 unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1);
4627 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4628 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4629 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4630 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4631 unsigned rb_per_se = num_rb / num_se;
4632 unsigned se_mask[4];
4633 unsigned se;
4634
4635 se_mask[0] = ((1 << rb_per_se) - 1);
4636 se_mask[1] = (se_mask[0] << rb_per_se);
4637 se_mask[2] = (se_mask[1] << rb_per_se);
4638 se_mask[3] = (se_mask[2] << rb_per_se);
4639
4640 se_mask[0] &= rb_mask;
4641 se_mask[1] &= rb_mask;
4642 se_mask[2] &= rb_mask;
4643 se_mask[3] &= rb_mask;
4644
4645 assert(num_se == 1 || num_se == 2 || num_se == 4);
4646 assert(sh_per_se == 1 || sh_per_se == 2);
4647 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4648
4649 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4650 * fields are for, so I'm leaving them as their default
4651 * values. */
4652
4653 for (se = 0; se < num_se; se++) {
4654 unsigned raster_config_se = raster_config;
4655 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4656 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4657 int idx = (se / 2) * 2;
4658
4659 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4660 raster_config_se &= C_028350_SE_MAP;
4661
4662 if (!se_mask[idx]) {
4663 raster_config_se |=
4664 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4665 } else {
4666 raster_config_se |=
4667 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4668 }
4669 }
4670
4671 pkr0_mask &= rb_mask;
4672 pkr1_mask &= rb_mask;
4673 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4674 raster_config_se &= C_028350_PKR_MAP;
4675
4676 if (!pkr0_mask) {
4677 raster_config_se |=
4678 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4679 } else {
4680 raster_config_se |=
4681 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4682 }
4683 }
4684
4685 if (rb_per_se >= 2) {
4686 unsigned rb0_mask = 1 << (se * rb_per_se);
4687 unsigned rb1_mask = rb0_mask << 1;
4688
4689 rb0_mask &= rb_mask;
4690 rb1_mask &= rb_mask;
4691 if (!rb0_mask || !rb1_mask) {
4692 raster_config_se &= C_028350_RB_MAP_PKR0;
4693
4694 if (!rb0_mask) {
4695 raster_config_se |=
4696 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4697 } else {
4698 raster_config_se |=
4699 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4700 }
4701 }
4702
4703 if (rb_per_se > 2) {
4704 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4705 rb1_mask = rb0_mask << 1;
4706 rb0_mask &= rb_mask;
4707 rb1_mask &= rb_mask;
4708 if (!rb0_mask || !rb1_mask) {
4709 raster_config_se &= C_028350_RB_MAP_PKR1;
4710
4711 if (!rb0_mask) {
4712 raster_config_se |=
4713 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4714 } else {
4715 raster_config_se |=
4716 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4717 }
4718 }
4719 }
4720 }
4721
4722 si_set_grbm_gfx_index_se(sctx, pm4, se);
4723 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4724 }
4725 si_set_grbm_gfx_index(sctx, pm4, ~0);
4726
4727 if (sctx->b.chip_class >= CIK) {
4728 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4729 (!se_mask[2] && !se_mask[3]))) {
4730 raster_config_1 &= C_028354_SE_PAIR_MAP;
4731
4732 if (!se_mask[0] && !se_mask[1]) {
4733 raster_config_1 |=
4734 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4735 } else {
4736 raster_config_1 |=
4737 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4738 }
4739 }
4740
4741 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4742 }
4743 }
4744
4745 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4746 {
4747 struct si_screen *sscreen = sctx->screen;
4748 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4749 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4750 unsigned raster_config, raster_config_1;
4751
4752 switch (sctx->b.family) {
4753 case CHIP_TAHITI:
4754 case CHIP_PITCAIRN:
4755 raster_config = 0x2a00126a;
4756 raster_config_1 = 0x00000000;
4757 break;
4758 case CHIP_VERDE:
4759 raster_config = 0x0000124a;
4760 raster_config_1 = 0x00000000;
4761 break;
4762 case CHIP_OLAND:
4763 raster_config = 0x00000082;
4764 raster_config_1 = 0x00000000;
4765 break;
4766 case CHIP_HAINAN:
4767 raster_config = 0x00000000;
4768 raster_config_1 = 0x00000000;
4769 break;
4770 case CHIP_BONAIRE:
4771 raster_config = 0x16000012;
4772 raster_config_1 = 0x00000000;
4773 break;
4774 case CHIP_HAWAII:
4775 raster_config = 0x3a00161a;
4776 raster_config_1 = 0x0000002e;
4777 break;
4778 case CHIP_FIJI:
4779 if (sscreen->info.cik_macrotile_mode_array[0] == 0x000000e8) {
4780 /* old kernels with old tiling config */
4781 raster_config = 0x16000012;
4782 raster_config_1 = 0x0000002a;
4783 } else {
4784 raster_config = 0x3a00161a;
4785 raster_config_1 = 0x0000002e;
4786 }
4787 break;
4788 case CHIP_POLARIS10:
4789 raster_config = 0x16000012;
4790 raster_config_1 = 0x0000002a;
4791 break;
4792 case CHIP_POLARIS11:
4793 case CHIP_POLARIS12:
4794 raster_config = 0x16000012;
4795 raster_config_1 = 0x00000000;
4796 break;
4797 case CHIP_TONGA:
4798 raster_config = 0x16000012;
4799 raster_config_1 = 0x0000002a;
4800 break;
4801 case CHIP_ICELAND:
4802 if (num_rb == 1)
4803 raster_config = 0x00000000;
4804 else
4805 raster_config = 0x00000002;
4806 raster_config_1 = 0x00000000;
4807 break;
4808 case CHIP_CARRIZO:
4809 raster_config = 0x00000002;
4810 raster_config_1 = 0x00000000;
4811 break;
4812 case CHIP_KAVERI:
4813 /* KV should be 0x00000002, but that causes problems with radeon */
4814 raster_config = 0x00000000; /* 0x00000002 */
4815 raster_config_1 = 0x00000000;
4816 break;
4817 case CHIP_KABINI:
4818 case CHIP_MULLINS:
4819 case CHIP_STONEY:
4820 raster_config = 0x00000000;
4821 raster_config_1 = 0x00000000;
4822 break;
4823 default:
4824 fprintf(stderr,
4825 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4826 raster_config = 0x00000000;
4827 raster_config_1 = 0x00000000;
4828 }
4829
4830 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4831 /* Always use the default config when all backends are enabled
4832 * (or when we failed to determine the enabled backends).
4833 */
4834 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4835 raster_config);
4836 if (sctx->b.chip_class >= CIK)
4837 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4838 raster_config_1);
4839 } else {
4840 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4841 }
4842 }
4843
4844 static void si_init_config(struct si_context *sctx)
4845 {
4846 struct si_screen *sscreen = sctx->screen;
4847 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4848 bool has_clear_state = sscreen->has_clear_state;
4849 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4850
4851 /* Only SI can disable CLEAR_STATE for now. */
4852 assert(has_clear_state || sscreen->info.chip_class == SI);
4853
4854 if (!pm4)
4855 return;
4856
4857 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4858 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4859 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4860 si_pm4_cmd_end(pm4, false);
4861
4862 if (has_clear_state) {
4863 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4864 si_pm4_cmd_add(pm4, 0);
4865 si_pm4_cmd_end(pm4, false);
4866 }
4867
4868 if (sctx->b.chip_class <= VI)
4869 si_set_raster_config(sctx, pm4);
4870
4871 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4872 if (!has_clear_state)
4873 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4874
4875 /* FIXME calculate these values somehow ??? */
4876 if (sctx->b.chip_class <= VI) {
4877 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4878 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4879 }
4880
4881 if (!has_clear_state) {
4882 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4883 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4884 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4885 }
4886
4887 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4888 if (!has_clear_state)
4889 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4890 if (sctx->b.chip_class < CIK)
4891 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4892 S_008A14_CLIP_VTX_REORDER_ENA(1));
4893
4894 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4895 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4896
4897 if (!has_clear_state)
4898 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4899
4900 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4901 * I don't know why. Deduced by trial and error.
4902 */
4903 if (sctx->b.chip_class <= CIK) {
4904 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4905 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4906 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4907 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4908 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4909 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4910 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4911 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4912 }
4913
4914 if (!has_clear_state) {
4915 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4916 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4917 S_028230_ER_TRI(0xA) |
4918 S_028230_ER_POINT(0xA) |
4919 S_028230_ER_RECT(0xA) |
4920 /* Required by DX10_DIAMOND_TEST_ENA: */
4921 S_028230_ER_LINE_LR(0x1A) |
4922 S_028230_ER_LINE_RL(0x26) |
4923 S_028230_ER_LINE_TB(0xA) |
4924 S_028230_ER_LINE_BT(0xA));
4925 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4926 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4927 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4928 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4929 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4930 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4931 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4932 }
4933
4934 if (sctx->b.chip_class >= GFX9) {
4935 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4936 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4937 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4938 } else {
4939 /* These registers, when written, also overwrite the CLEAR_STATE
4940 * context, so we can't rely on CLEAR_STATE setting them.
4941 * It would be an issue if there was another UMD changing them.
4942 */
4943 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4944 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4945 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4946 }
4947
4948 if (sctx->b.chip_class >= CIK) {
4949 if (sctx->b.chip_class >= GFX9) {
4950 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4951 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4952 } else {
4953 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4954 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4955 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4956 S_00B41C_WAVE_LIMIT(0x3F));
4957 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4958 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4959
4960 /* If this is 0, Bonaire can hang even if GS isn't being used.
4961 * Other chips are unaffected. These are suboptimal values,
4962 * but we don't use on-chip GS.
4963 */
4964 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4965 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4966 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4967 }
4968 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4969 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4970
4971 /* Compute LATE_ALLOC_VS.LIMIT. */
4972 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4973 (sscreen->info.max_se *
4974 sscreen->info.max_sh_per_se);
4975 unsigned late_alloc_limit; /* The limit is per SH. */
4976
4977 if (sctx->b.family == CHIP_KABINI) {
4978 late_alloc_limit = 0; /* Potential hang on Kabini. */
4979 } else if (num_cu_per_sh <= 4) {
4980 /* Too few available compute units per SH. Disallowing
4981 * VS to run on one CU could hurt us more than late VS
4982 * allocation would help.
4983 *
4984 * 2 is the highest safe number that allows us to keep
4985 * all CUs enabled.
4986 */
4987 late_alloc_limit = 2;
4988 } else {
4989 /* This is a good initial value, allowing 1 late_alloc
4990 * wave per SIMD on num_cu - 2.
4991 */
4992 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4993
4994 /* The limit is 0-based, so 0 means 1. */
4995 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4996 late_alloc_limit -= 1;
4997 }
4998
4999 /* VS can't execute on one CU if the limit is > 2. */
5000 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5001 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5002 S_00B118_WAVE_LIMIT(0x3F));
5003 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5004 S_00B11C_LIMIT(late_alloc_limit));
5005 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5006 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5007 }
5008
5009 if (sctx->b.chip_class >= VI) {
5010 unsigned vgt_tess_distribution;
5011
5012 vgt_tess_distribution =
5013 S_028B50_ACCUM_ISOLINE(32) |
5014 S_028B50_ACCUM_TRI(11) |
5015 S_028B50_ACCUM_QUAD(11) |
5016 S_028B50_DONUT_SPLIT(16);
5017
5018 /* Testing with Unigine Heaven extreme tesselation yielded best results
5019 * with TRAP_SPLIT = 3.
5020 */
5021 if (sctx->b.family == CHIP_FIJI ||
5022 sctx->b.family >= CHIP_POLARIS10)
5023 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5024
5025 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5026 } else if (!has_clear_state) {
5027 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5028 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5029 }
5030
5031 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5032 if (sctx->b.chip_class >= CIK) {
5033 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5034 S_028084_ADDRESS(border_color_va >> 40));
5035 }
5036 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5037 RADEON_PRIO_BORDER_COLORS);
5038
5039 if (sctx->b.chip_class >= GFX9) {
5040 unsigned num_se = sscreen->info.max_se;
5041 unsigned pc_lines = 0;
5042
5043 switch (sctx->b.family) {
5044 case CHIP_VEGA10:
5045 case CHIP_VEGA12:
5046 pc_lines = 4096;
5047 break;
5048 case CHIP_RAVEN:
5049 pc_lines = 1024;
5050 break;
5051 default:
5052 assert(0);
5053 }
5054
5055 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5056 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5057 S_028C48_MAX_PRIM_PER_BATCH(1023));
5058 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5059 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5060 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5061 }
5062
5063 si_pm4_upload_indirect_buffer(sctx, pm4);
5064 sctx->init_config = pm4;
5065 }