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[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 /* Initialize an external atom (owned by ../radeon). */
37 static void
38 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
39 struct r600_atom **list_elem)
40 {
41 atom->id = list_elem - sctx->atoms.array;
42 *list_elem = atom;
43 }
44
45 /* Initialize an atom owned by radeonsi. */
46 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
47 struct r600_atom **list_elem,
48 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
49 {
50 atom->emit = emit_func;
51 atom->id = list_elem - sctx->atoms.array;
52 *list_elem = atom;
53 }
54
55 static unsigned si_map_swizzle(unsigned swizzle)
56 {
57 switch (swizzle) {
58 case PIPE_SWIZZLE_Y:
59 return V_008F0C_SQ_SEL_Y;
60 case PIPE_SWIZZLE_Z:
61 return V_008F0C_SQ_SEL_Z;
62 case PIPE_SWIZZLE_W:
63 return V_008F0C_SQ_SEL_W;
64 case PIPE_SWIZZLE_0:
65 return V_008F0C_SQ_SEL_0;
66 case PIPE_SWIZZLE_1:
67 return V_008F0C_SQ_SEL_1;
68 default: /* PIPE_SWIZZLE_X */
69 return V_008F0C_SQ_SEL_X;
70 }
71 }
72
73 /* 12.4 fixed-point */
74 static unsigned si_pack_float_12p4(float x)
75 {
76 return x <= 0 ? 0 :
77 x >= 4096 ? 0xffff : x * 16;
78 }
79
80 /*
81 * Inferred framebuffer and blender state.
82 *
83 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
84 * if there is not enough PS outputs.
85 */
86 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
87 {
88 struct radeon_winsys_cs *cs = sctx->gfx_cs;
89 struct si_state_blend *blend = sctx->queued.named.blend;
90 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
91 * but you never know. */
92 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
93 unsigned i;
94
95 if (blend)
96 cb_target_mask &= blend->cb_target_mask;
97
98 /* Avoid a hang that happens when dual source blending is enabled
99 * but there is not enough color outputs. This is undefined behavior,
100 * so disable color writes completely.
101 *
102 * Reproducible with Unigine Heaven 4.0 and drirc missing.
103 */
104 if (blend && blend->dual_src_blend &&
105 sctx->ps_shader.cso &&
106 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
107 cb_target_mask = 0;
108
109 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
110
111 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
112 * I think we don't have to do anything between IBs.
113 */
114 if (sctx->screen->dfsm_allowed &&
115 sctx->last_cb_target_mask != cb_target_mask) {
116 sctx->last_cb_target_mask = cb_target_mask;
117
118 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
119 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
120 }
121
122 if (sctx->chip_class >= VI) {
123 /* DCC MSAA workaround for blending.
124 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
125 * COMBINER_DISABLE, but that would be more complicated.
126 */
127 bool oc_disable = (sctx->chip_class == VI ||
128 sctx->chip_class == GFX9) &&
129 blend &&
130 blend->blend_enable_4bit & cb_target_mask &&
131 sctx->framebuffer.nr_samples >= 2;
132
133 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
134 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
135 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
136 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
137 }
138
139 /* RB+ register settings. */
140 if (sctx->screen->rbplus_allowed) {
141 unsigned spi_shader_col_format =
142 sctx->ps_shader.cso ?
143 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
144 unsigned sx_ps_downconvert = 0;
145 unsigned sx_blend_opt_epsilon = 0;
146 unsigned sx_blend_opt_control = 0;
147
148 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
149 struct r600_surface *surf =
150 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
151 unsigned format, swap, spi_format, colormask;
152 bool has_alpha, has_rgb;
153
154 if (!surf)
155 continue;
156
157 format = G_028C70_FORMAT(surf->cb_color_info);
158 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
159 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
160 colormask = (cb_target_mask >> (i * 4)) & 0xf;
161
162 /* Set if RGB and A are present. */
163 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
164
165 if (format == V_028C70_COLOR_8 ||
166 format == V_028C70_COLOR_16 ||
167 format == V_028C70_COLOR_32)
168 has_rgb = !has_alpha;
169 else
170 has_rgb = true;
171
172 /* Check the colormask and export format. */
173 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
174 has_rgb = false;
175 if (!(colormask & PIPE_MASK_A))
176 has_alpha = false;
177
178 if (spi_format == V_028714_SPI_SHADER_ZERO) {
179 has_rgb = false;
180 has_alpha = false;
181 }
182
183 /* Disable value checking for disabled channels. */
184 if (!has_rgb)
185 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
186 if (!has_alpha)
187 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
188
189 /* Enable down-conversion for 32bpp and smaller formats. */
190 switch (format) {
191 case V_028C70_COLOR_8:
192 case V_028C70_COLOR_8_8:
193 case V_028C70_COLOR_8_8_8_8:
194 /* For 1 and 2-channel formats, use the superset thereof. */
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
196 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_5_6_5:
204 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
205 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
206 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
207 }
208 break;
209
210 case V_028C70_COLOR_1_5_5_5:
211 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
212 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
213 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
214 }
215 break;
216
217 case V_028C70_COLOR_4_4_4_4:
218 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
220 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
221 }
222 break;
223
224 case V_028C70_COLOR_32:
225 if (swap == V_028C70_SWAP_STD &&
226 spi_format == V_028714_SPI_SHADER_32_R)
227 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
228 else if (swap == V_028C70_SWAP_ALT_REV &&
229 spi_format == V_028714_SPI_SHADER_32_AR)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
231 break;
232
233 case V_028C70_COLOR_16:
234 case V_028C70_COLOR_16_16:
235 /* For 1-channel formats, use the superset thereof. */
236 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
237 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
240 if (swap == V_028C70_SWAP_STD ||
241 swap == V_028C70_SWAP_STD_REV)
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
243 else
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
245 }
246 break;
247
248 case V_028C70_COLOR_10_11_11:
249 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
250 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
251 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
252 }
253 break;
254
255 case V_028C70_COLOR_2_10_10_10:
256 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
257 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
258 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
259 }
260 break;
261 }
262 }
263
264 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
265 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
266 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
267 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
268 } else if (sctx->screen->has_rbplus) {
269 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
270 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
271 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
272 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
273 }
274 }
275
276 /*
277 * Blender functions
278 */
279
280 static uint32_t si_translate_blend_function(int blend_func)
281 {
282 switch (blend_func) {
283 case PIPE_BLEND_ADD:
284 return V_028780_COMB_DST_PLUS_SRC;
285 case PIPE_BLEND_SUBTRACT:
286 return V_028780_COMB_SRC_MINUS_DST;
287 case PIPE_BLEND_REVERSE_SUBTRACT:
288 return V_028780_COMB_DST_MINUS_SRC;
289 case PIPE_BLEND_MIN:
290 return V_028780_COMB_MIN_DST_SRC;
291 case PIPE_BLEND_MAX:
292 return V_028780_COMB_MAX_DST_SRC;
293 default:
294 PRINT_ERR("Unknown blend function %d\n", blend_func);
295 assert(0);
296 break;
297 }
298 return 0;
299 }
300
301 static uint32_t si_translate_blend_factor(int blend_fact)
302 {
303 switch (blend_fact) {
304 case PIPE_BLENDFACTOR_ONE:
305 return V_028780_BLEND_ONE;
306 case PIPE_BLENDFACTOR_SRC_COLOR:
307 return V_028780_BLEND_SRC_COLOR;
308 case PIPE_BLENDFACTOR_SRC_ALPHA:
309 return V_028780_BLEND_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case PIPE_BLENDFACTOR_DST_COLOR:
313 return V_028780_BLEND_DST_COLOR;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE;
316 case PIPE_BLENDFACTOR_CONST_COLOR:
317 return V_028780_BLEND_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_CONST_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_ZERO:
321 return V_028780_BLEND_ZERO;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
334 case PIPE_BLENDFACTOR_SRC1_COLOR:
335 return V_028780_BLEND_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA:
337 return V_028780_BLEND_SRC1_ALPHA;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
339 return V_028780_BLEND_INV_SRC1_COLOR;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
341 return V_028780_BLEND_INV_SRC1_ALPHA;
342 default:
343 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
344 assert(0);
345 break;
346 }
347 return 0;
348 }
349
350 static uint32_t si_translate_blend_opt_function(int blend_func)
351 {
352 switch (blend_func) {
353 case PIPE_BLEND_ADD:
354 return V_028760_OPT_COMB_ADD;
355 case PIPE_BLEND_SUBTRACT:
356 return V_028760_OPT_COMB_SUBTRACT;
357 case PIPE_BLEND_REVERSE_SUBTRACT:
358 return V_028760_OPT_COMB_REVSUBTRACT;
359 case PIPE_BLEND_MIN:
360 return V_028760_OPT_COMB_MIN;
361 case PIPE_BLEND_MAX:
362 return V_028760_OPT_COMB_MAX;
363 default:
364 return V_028760_OPT_COMB_BLEND_DISABLED;
365 }
366 }
367
368 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
369 {
370 switch (blend_fact) {
371 case PIPE_BLENDFACTOR_ZERO:
372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
373 case PIPE_BLENDFACTOR_ONE:
374 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
375 case PIPE_BLENDFACTOR_SRC_COLOR:
376 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
377 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
378 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
380 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
381 case PIPE_BLENDFACTOR_SRC_ALPHA:
382 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
383 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
384 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
385 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
386 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
387 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
388 default:
389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
390 }
391 }
392
393 static void si_blend_check_commutativity(struct si_screen *sscreen,
394 struct si_state_blend *blend,
395 enum pipe_blend_func func,
396 enum pipe_blendfactor src,
397 enum pipe_blendfactor dst,
398 unsigned chanmask)
399 {
400 /* Src factor is allowed when it does not depend on Dst */
401 static const uint32_t src_allowed =
402 (1u << PIPE_BLENDFACTOR_ONE) |
403 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
404 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
405 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
406 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
407 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
408 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
409 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
410 (1u << PIPE_BLENDFACTOR_ZERO) |
411 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
413 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
414 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
415 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
416 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
417
418 if (dst == PIPE_BLENDFACTOR_ONE &&
419 (src_allowed & (1u << src))) {
420 /* Addition is commutative, but floating point addition isn't
421 * associative: subtle changes can be introduced via different
422 * rounding.
423 *
424 * Out-of-order is also non-deterministic, which means that
425 * this breaks OpenGL invariance requirements. So only enable
426 * out-of-order additive blending if explicitly allowed by a
427 * setting.
428 */
429 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
430 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
431 blend->commutative_4bit |= chanmask;
432 }
433 }
434
435 /**
436 * Get rid of DST in the blend factors by commuting the operands:
437 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
438 */
439 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
440 unsigned *dst_factor, unsigned expected_dst,
441 unsigned replacement_src)
442 {
443 if (*src_factor == expected_dst &&
444 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
445 *src_factor = PIPE_BLENDFACTOR_ZERO;
446 *dst_factor = replacement_src;
447
448 /* Commuting the operands requires reversing subtractions. */
449 if (*func == PIPE_BLEND_SUBTRACT)
450 *func = PIPE_BLEND_REVERSE_SUBTRACT;
451 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
452 *func = PIPE_BLEND_SUBTRACT;
453 }
454 }
455
456 static bool si_blend_factor_uses_dst(unsigned factor)
457 {
458 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
459 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
460 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
461 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
462 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
463 }
464
465 static void *si_create_blend_state_mode(struct pipe_context *ctx,
466 const struct pipe_blend_state *state,
467 unsigned mode)
468 {
469 struct si_context *sctx = (struct si_context*)ctx;
470 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
471 struct si_pm4_state *pm4 = &blend->pm4;
472 uint32_t sx_mrt_blend_opt[8] = {0};
473 uint32_t color_control = 0;
474
475 if (!blend)
476 return NULL;
477
478 blend->alpha_to_coverage = state->alpha_to_coverage;
479 blend->alpha_to_one = state->alpha_to_one;
480 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
481 blend->logicop_enable = state->logicop_enable;
482
483 if (state->logicop_enable) {
484 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
485 } else {
486 color_control |= S_028808_ROP3(0xcc);
487 }
488
489 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
490 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
491 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
492 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
493 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
495
496 if (state->alpha_to_coverage)
497 blend->need_src_alpha_4bit |= 0xf;
498
499 blend->cb_target_mask = 0;
500 blend->cb_target_enabled_4bit = 0;
501
502 for (int i = 0; i < 8; i++) {
503 /* state->rt entries > 0 only written if independent blending */
504 const int j = state->independent_blend_enable ? i : 0;
505
506 unsigned eqRGB = state->rt[j].rgb_func;
507 unsigned srcRGB = state->rt[j].rgb_src_factor;
508 unsigned dstRGB = state->rt[j].rgb_dst_factor;
509 unsigned eqA = state->rt[j].alpha_func;
510 unsigned srcA = state->rt[j].alpha_src_factor;
511 unsigned dstA = state->rt[j].alpha_dst_factor;
512
513 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
514 unsigned blend_cntl = 0;
515
516 sx_mrt_blend_opt[i] =
517 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
518 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
519
520 /* Only set dual source blending for MRT0 to avoid a hang. */
521 if (i >= 1 && blend->dual_src_blend) {
522 /* Vulkan does this for dual source blending. */
523 if (i == 1)
524 blend_cntl |= S_028780_ENABLE(1);
525
526 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
527 continue;
528 }
529
530 /* Only addition and subtraction equations are supported with
531 * dual source blending.
532 */
533 if (blend->dual_src_blend &&
534 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
535 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
536 assert(!"Unsupported equation for dual source blending");
537 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
538 continue;
539 }
540
541 /* cb_render_state will disable unused ones */
542 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
543 if (state->rt[j].colormask)
544 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
545
546 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
547 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
548 continue;
549 }
550
551 si_blend_check_commutativity(sctx->screen, blend,
552 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
553 si_blend_check_commutativity(sctx->screen, blend,
554 eqA, srcA, dstA, 0x8 << (4 * i));
555
556 /* Blending optimizations for RB+.
557 * These transformations don't change the behavior.
558 *
559 * First, get rid of DST in the blend factors:
560 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
561 */
562 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
563 PIPE_BLENDFACTOR_DST_COLOR,
564 PIPE_BLENDFACTOR_SRC_COLOR);
565 si_blend_remove_dst(&eqA, &srcA, &dstA,
566 PIPE_BLENDFACTOR_DST_COLOR,
567 PIPE_BLENDFACTOR_SRC_COLOR);
568 si_blend_remove_dst(&eqA, &srcA, &dstA,
569 PIPE_BLENDFACTOR_DST_ALPHA,
570 PIPE_BLENDFACTOR_SRC_ALPHA);
571
572 /* Look up the ideal settings from tables. */
573 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
574 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
575 srcA_opt = si_translate_blend_opt_factor(srcA, true);
576 dstA_opt = si_translate_blend_opt_factor(dstA, true);
577
578 /* Handle interdependencies. */
579 if (si_blend_factor_uses_dst(srcRGB))
580 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
581 if (si_blend_factor_uses_dst(srcA))
582 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
583
584 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
585 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
586 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
587 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
588 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
589
590 /* Set the final value. */
591 sx_mrt_blend_opt[i] =
592 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
593 S_028760_COLOR_DST_OPT(dstRGB_opt) |
594 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
595 S_028760_ALPHA_SRC_OPT(srcA_opt) |
596 S_028760_ALPHA_DST_OPT(dstA_opt) |
597 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
598
599 /* Set blend state. */
600 blend_cntl |= S_028780_ENABLE(1);
601 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
602 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
603 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
604
605 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
606 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
607 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
608 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
609 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
610 }
611 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
612
613 blend->blend_enable_4bit |= 0xfu << (i * 4);
614
615 /* This is only important for formats without alpha. */
616 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
617 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
618 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
619 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
620 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
621 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
622 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
623 }
624
625 if (blend->cb_target_mask) {
626 color_control |= S_028808_MODE(mode);
627 } else {
628 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
629 }
630
631 if (sctx->screen->has_rbplus) {
632 /* Disable RB+ blend optimizations for dual source blending.
633 * Vulkan does this.
634 */
635 if (blend->dual_src_blend) {
636 for (int i = 0; i < 8; i++) {
637 sx_mrt_blend_opt[i] =
638 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
639 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
640 }
641 }
642
643 for (int i = 0; i < 8; i++)
644 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
645 sx_mrt_blend_opt[i]);
646
647 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
648 if (blend->dual_src_blend || state->logicop_enable ||
649 mode == V_028808_CB_RESOLVE)
650 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
651 }
652
653 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
654 return blend;
655 }
656
657 static void *si_create_blend_state(struct pipe_context *ctx,
658 const struct pipe_blend_state *state)
659 {
660 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
661 }
662
663 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
664 {
665 struct si_context *sctx = (struct si_context *)ctx;
666 struct si_state_blend *old_blend = sctx->queued.named.blend;
667 struct si_state_blend *blend = (struct si_state_blend *)state;
668
669 if (!state)
670 return;
671
672 si_pm4_bind_state(sctx, blend, state);
673
674 if (!old_blend ||
675 old_blend->cb_target_mask != blend->cb_target_mask ||
676 old_blend->dual_src_blend != blend->dual_src_blend ||
677 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
678 sctx->framebuffer.nr_samples >= 2 &&
679 sctx->screen->dcc_msaa_allowed))
680 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
681
682 if (!old_blend ||
683 old_blend->cb_target_mask != blend->cb_target_mask ||
684 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
685 old_blend->alpha_to_one != blend->alpha_to_one ||
686 old_blend->dual_src_blend != blend->dual_src_blend ||
687 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
688 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
689 sctx->do_update_shaders = true;
690
691 if (sctx->screen->dpbb_allowed &&
692 (!old_blend ||
693 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
694 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
695 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
696 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
697
698 if (sctx->screen->has_out_of_order_rast &&
699 (!old_blend ||
700 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
701 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
702 old_blend->commutative_4bit != blend->commutative_4bit ||
703 old_blend->logicop_enable != blend->logicop_enable)))
704 si_mark_atom_dirty(sctx, &sctx->msaa_config);
705 }
706
707 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
708 {
709 struct si_context *sctx = (struct si_context *)ctx;
710 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
711 }
712
713 static void si_set_blend_color(struct pipe_context *ctx,
714 const struct pipe_blend_color *state)
715 {
716 struct si_context *sctx = (struct si_context *)ctx;
717 static const struct pipe_blend_color zeros;
718
719 sctx->blend_color.state = *state;
720 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
721 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
722 }
723
724 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
725 {
726 struct radeon_winsys_cs *cs = sctx->gfx_cs;
727
728 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
729 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
730 }
731
732 /*
733 * Clipping
734 */
735
736 static void si_set_clip_state(struct pipe_context *ctx,
737 const struct pipe_clip_state *state)
738 {
739 struct si_context *sctx = (struct si_context *)ctx;
740 struct pipe_constant_buffer cb;
741 static const struct pipe_clip_state zeros;
742
743 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
744 return;
745
746 sctx->clip_state.state = *state;
747 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
748 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
749
750 cb.buffer = NULL;
751 cb.user_buffer = state->ucp;
752 cb.buffer_offset = 0;
753 cb.buffer_size = 4*4*8;
754 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
755 pipe_resource_reference(&cb.buffer, NULL);
756 }
757
758 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
759 {
760 struct radeon_winsys_cs *cs = sctx->gfx_cs;
761
762 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
763 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
764 }
765
766 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
767 {
768 struct radeon_winsys_cs *cs = sctx->gfx_cs;
769 struct si_shader *vs = si_get_vs_state(sctx);
770 struct si_shader_selector *vs_sel = vs->selector;
771 struct tgsi_shader_info *info = &vs_sel->info;
772 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
773 unsigned window_space =
774 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
775 unsigned clipdist_mask = vs_sel->clipdist_mask;
776 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
777 unsigned culldist_mask = vs_sel->culldist_mask;
778 unsigned total_mask;
779
780 if (vs->key.opt.clip_disable) {
781 assert(!info->culldist_writemask);
782 clipdist_mask = 0;
783 culldist_mask = 0;
784 }
785 total_mask = clipdist_mask | culldist_mask;
786
787 /* Clip distances on points have no effect, so need to be implemented
788 * as cull distances. This applies for the clipvertex case as well.
789 *
790 * Setting this for primitives other than points should have no adverse
791 * effects.
792 */
793 clipdist_mask &= rs->clip_plane_enable;
794 culldist_mask |= clipdist_mask;
795
796 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
797 vs_sel->pa_cl_vs_out_cntl |
798 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
799 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
800 clipdist_mask | (culldist_mask << 8));
801 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
802 rs->pa_cl_clip_cntl |
803 ucp_mask |
804 S_028810_CLIP_DISABLE(window_space));
805 }
806
807 /*
808 * inferred state between framebuffer and rasterizer
809 */
810 static void si_update_poly_offset_state(struct si_context *sctx)
811 {
812 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
813
814 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
815 si_pm4_bind_state(sctx, poly_offset, NULL);
816 return;
817 }
818
819 /* Use the user format, not db_render_format, so that the polygon
820 * offset behaves as expected by applications.
821 */
822 switch (sctx->framebuffer.state.zsbuf->texture->format) {
823 case PIPE_FORMAT_Z16_UNORM:
824 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
825 break;
826 default: /* 24-bit */
827 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
828 break;
829 case PIPE_FORMAT_Z32_FLOAT:
830 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
831 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
832 break;
833 }
834 }
835
836 /*
837 * Rasterizer
838 */
839
840 static uint32_t si_translate_fill(uint32_t func)
841 {
842 switch(func) {
843 case PIPE_POLYGON_MODE_FILL:
844 return V_028814_X_DRAW_TRIANGLES;
845 case PIPE_POLYGON_MODE_LINE:
846 return V_028814_X_DRAW_LINES;
847 case PIPE_POLYGON_MODE_POINT:
848 return V_028814_X_DRAW_POINTS;
849 default:
850 assert(0);
851 return V_028814_X_DRAW_POINTS;
852 }
853 }
854
855 static void *si_create_rs_state(struct pipe_context *ctx,
856 const struct pipe_rasterizer_state *state)
857 {
858 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
859 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
860 struct si_pm4_state *pm4 = &rs->pm4;
861 unsigned tmp, i;
862 float psize_min, psize_max;
863
864 if (!rs) {
865 return NULL;
866 }
867
868 rs->scissor_enable = state->scissor;
869 rs->clip_halfz = state->clip_halfz;
870 rs->two_side = state->light_twoside;
871 rs->multisample_enable = state->multisample;
872 rs->force_persample_interp = state->force_persample_interp;
873 rs->clip_plane_enable = state->clip_plane_enable;
874 rs->line_stipple_enable = state->line_stipple_enable;
875 rs->poly_stipple_enable = state->poly_stipple_enable;
876 rs->line_smooth = state->line_smooth;
877 rs->line_width = state->line_width;
878 rs->poly_smooth = state->poly_smooth;
879 rs->uses_poly_offset = state->offset_point || state->offset_line ||
880 state->offset_tri;
881 rs->clamp_fragment_color = state->clamp_fragment_color;
882 rs->clamp_vertex_color = state->clamp_vertex_color;
883 rs->flatshade = state->flatshade;
884 rs->sprite_coord_enable = state->sprite_coord_enable;
885 rs->rasterizer_discard = state->rasterizer_discard;
886 rs->pa_sc_line_stipple = state->line_stipple_enable ?
887 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
888 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
889 rs->pa_cl_clip_cntl =
890 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
891 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
892 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
893 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
894 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
895
896 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
897 S_0286D4_FLAT_SHADE_ENA(1) |
898 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
899 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
903 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
904
905 /* point size 12.4 fixed point */
906 tmp = (unsigned)(state->point_size * 8.0);
907 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
908
909 if (state->point_size_per_vertex) {
910 psize_min = util_get_min_point_size(state);
911 psize_max = 8192;
912 } else {
913 /* Force the point size to be as if the vertex output was disabled. */
914 psize_min = state->point_size;
915 psize_max = state->point_size;
916 }
917 rs->max_point_size = psize_max;
918
919 /* Divide by two, because 0.5 = 1 pixel. */
920 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
921 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
922 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
923
924 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
925 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
926 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
927 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
928 S_028A48_MSAA_ENABLE(state->multisample ||
929 state->poly_smooth ||
930 state->line_smooth) |
931 S_028A48_VPORT_SCISSOR_ENABLE(1) |
932 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
933
934 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
935 S_028BE4_PIX_CENTER(state->half_pixel_center) |
936 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
937
938 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
939 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
940 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
941 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
942 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
943 S_028814_FACE(!state->front_ccw) |
944 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
945 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
946 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
947 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
948 state->fill_back != PIPE_POLYGON_MODE_FILL) |
949 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
950 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
951
952 if (!rs->uses_poly_offset)
953 return rs;
954
955 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
956 if (!rs->pm4_poly_offset) {
957 FREE(rs);
958 return NULL;
959 }
960
961 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
962 for (i = 0; i < 3; i++) {
963 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
964 float offset_units = state->offset_units;
965 float offset_scale = state->offset_scale * 16.0f;
966 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
967
968 if (!state->offset_units_unscaled) {
969 switch (i) {
970 case 0: /* 16-bit zbuffer */
971 offset_units *= 4.0f;
972 pa_su_poly_offset_db_fmt_cntl =
973 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
974 break;
975 case 1: /* 24-bit zbuffer */
976 offset_units *= 2.0f;
977 pa_su_poly_offset_db_fmt_cntl =
978 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
979 break;
980 case 2: /* 32-bit zbuffer */
981 offset_units *= 1.0f;
982 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
983 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
984 break;
985 }
986 }
987
988 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
989 fui(offset_scale));
990 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
991 fui(offset_units));
992 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
993 fui(offset_scale));
994 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
995 fui(offset_units));
996 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
997 pa_su_poly_offset_db_fmt_cntl);
998 }
999
1000 return rs;
1001 }
1002
1003 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1004 {
1005 struct si_context *sctx = (struct si_context *)ctx;
1006 struct si_state_rasterizer *old_rs =
1007 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1008 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1009
1010 if (!state)
1011 return;
1012
1013 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1014 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1015
1016 /* Update the small primitive filter workaround if necessary. */
1017 if (sctx->screen->has_msaa_sample_loc_bug &&
1018 sctx->framebuffer.nr_samples > 1)
1019 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1020 }
1021
1022 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1023 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1024
1025 si_pm4_bind_state(sctx, rasterizer, rs);
1026 si_update_poly_offset_state(sctx);
1027
1028 if (!old_rs ||
1029 (old_rs->scissor_enable != rs->scissor_enable ||
1030 old_rs->line_width != rs->line_width ||
1031 old_rs->max_point_size != rs->max_point_size)) {
1032 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1033 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1034 }
1035
1036 if (!old_rs ||
1037 old_rs->clip_halfz != rs->clip_halfz) {
1038 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1039 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1040 }
1041
1042 if (!old_rs ||
1043 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1044 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1045 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1046
1047 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1048 rs->line_stipple_enable;
1049
1050 if (!old_rs ||
1051 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1052 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1053 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1054 old_rs->flatshade != rs->flatshade ||
1055 old_rs->two_side != rs->two_side ||
1056 old_rs->multisample_enable != rs->multisample_enable ||
1057 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1058 old_rs->poly_smooth != rs->poly_smooth ||
1059 old_rs->line_smooth != rs->line_smooth ||
1060 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1061 old_rs->force_persample_interp != rs->force_persample_interp)
1062 sctx->do_update_shaders = true;
1063 }
1064
1065 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1066 {
1067 struct si_context *sctx = (struct si_context *)ctx;
1068 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1069
1070 if (sctx->queued.named.rasterizer == state)
1071 si_pm4_bind_state(sctx, poly_offset, NULL);
1072
1073 FREE(rs->pm4_poly_offset);
1074 si_pm4_delete_state(sctx, rasterizer, rs);
1075 }
1076
1077 /*
1078 * infeered state between dsa and stencil ref
1079 */
1080 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1081 {
1082 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1083 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1084 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1085
1086 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1087 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1088 S_028430_STENCILMASK(dsa->valuemask[0]) |
1089 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1090 S_028430_STENCILOPVAL(1));
1091 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1092 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1093 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1094 S_028434_STENCILOPVAL_BF(1));
1095 }
1096
1097 static void si_set_stencil_ref(struct pipe_context *ctx,
1098 const struct pipe_stencil_ref *state)
1099 {
1100 struct si_context *sctx = (struct si_context *)ctx;
1101
1102 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1103 return;
1104
1105 sctx->stencil_ref.state = *state;
1106 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1107 }
1108
1109
1110 /*
1111 * DSA
1112 */
1113
1114 static uint32_t si_translate_stencil_op(int s_op)
1115 {
1116 switch (s_op) {
1117 case PIPE_STENCIL_OP_KEEP:
1118 return V_02842C_STENCIL_KEEP;
1119 case PIPE_STENCIL_OP_ZERO:
1120 return V_02842C_STENCIL_ZERO;
1121 case PIPE_STENCIL_OP_REPLACE:
1122 return V_02842C_STENCIL_REPLACE_TEST;
1123 case PIPE_STENCIL_OP_INCR:
1124 return V_02842C_STENCIL_ADD_CLAMP;
1125 case PIPE_STENCIL_OP_DECR:
1126 return V_02842C_STENCIL_SUB_CLAMP;
1127 case PIPE_STENCIL_OP_INCR_WRAP:
1128 return V_02842C_STENCIL_ADD_WRAP;
1129 case PIPE_STENCIL_OP_DECR_WRAP:
1130 return V_02842C_STENCIL_SUB_WRAP;
1131 case PIPE_STENCIL_OP_INVERT:
1132 return V_02842C_STENCIL_INVERT;
1133 default:
1134 PRINT_ERR("Unknown stencil op %d", s_op);
1135 assert(0);
1136 break;
1137 }
1138 return 0;
1139 }
1140
1141 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1142 {
1143 return s->enabled && s->writemask &&
1144 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1145 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1146 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1147 }
1148
1149 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1150 {
1151 /* REPLACE is normally order invariant, except when the stencil
1152 * reference value is written by the fragment shader. Tracking this
1153 * interaction does not seem worth the effort, so be conservative. */
1154 return op != PIPE_STENCIL_OP_INCR &&
1155 op != PIPE_STENCIL_OP_DECR &&
1156 op != PIPE_STENCIL_OP_REPLACE;
1157 }
1158
1159 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1160 * invariant in the sense that the set of passing fragments as well as the
1161 * final stencil buffer result does not depend on the order of fragments. */
1162 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1163 {
1164 return !state->enabled || !state->writemask ||
1165 /* The following assumes that Z writes are disabled. */
1166 (state->func == PIPE_FUNC_ALWAYS &&
1167 si_order_invariant_stencil_op(state->zpass_op) &&
1168 si_order_invariant_stencil_op(state->zfail_op)) ||
1169 (state->func == PIPE_FUNC_NEVER &&
1170 si_order_invariant_stencil_op(state->fail_op));
1171 }
1172
1173 static void *si_create_dsa_state(struct pipe_context *ctx,
1174 const struct pipe_depth_stencil_alpha_state *state)
1175 {
1176 struct si_context *sctx = (struct si_context *)ctx;
1177 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1178 struct si_pm4_state *pm4 = &dsa->pm4;
1179 unsigned db_depth_control;
1180 uint32_t db_stencil_control = 0;
1181
1182 if (!dsa) {
1183 return NULL;
1184 }
1185
1186 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1187 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1188 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1189 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1190
1191 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1192 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1193 S_028800_ZFUNC(state->depth.func) |
1194 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1195
1196 /* stencil */
1197 if (state->stencil[0].enabled) {
1198 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1199 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1200 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1201 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1202 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1203
1204 if (state->stencil[1].enabled) {
1205 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1206 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1207 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1208 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1209 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1210 }
1211 }
1212
1213 /* alpha */
1214 if (state->alpha.enabled) {
1215 dsa->alpha_func = state->alpha.func;
1216
1217 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1218 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1219 } else {
1220 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1221 }
1222
1223 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1224 if (state->stencil[0].enabled)
1225 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1226 if (state->depth.bounds_test) {
1227 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1228 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1229 }
1230
1231 dsa->depth_enabled = state->depth.enabled;
1232 dsa->depth_write_enabled = state->depth.enabled &&
1233 state->depth.writemask;
1234 dsa->stencil_enabled = state->stencil[0].enabled;
1235 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1236 (si_dsa_writes_stencil(&state->stencil[0]) ||
1237 si_dsa_writes_stencil(&state->stencil[1]));
1238 dsa->db_can_write = dsa->depth_write_enabled ||
1239 dsa->stencil_write_enabled;
1240
1241 bool zfunc_is_ordered =
1242 state->depth.func == PIPE_FUNC_NEVER ||
1243 state->depth.func == PIPE_FUNC_LESS ||
1244 state->depth.func == PIPE_FUNC_LEQUAL ||
1245 state->depth.func == PIPE_FUNC_GREATER ||
1246 state->depth.func == PIPE_FUNC_GEQUAL;
1247
1248 bool nozwrite_and_order_invariant_stencil =
1249 !dsa->db_can_write ||
1250 (!dsa->depth_write_enabled &&
1251 si_order_invariant_stencil_state(&state->stencil[0]) &&
1252 si_order_invariant_stencil_state(&state->stencil[1]));
1253
1254 dsa->order_invariance[1].zs =
1255 nozwrite_and_order_invariant_stencil ||
1256 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1257 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1258
1259 dsa->order_invariance[1].pass_set =
1260 nozwrite_and_order_invariant_stencil ||
1261 (!dsa->stencil_write_enabled &&
1262 (state->depth.func == PIPE_FUNC_ALWAYS ||
1263 state->depth.func == PIPE_FUNC_NEVER));
1264 dsa->order_invariance[0].pass_set =
1265 !dsa->depth_write_enabled ||
1266 (state->depth.func == PIPE_FUNC_ALWAYS ||
1267 state->depth.func == PIPE_FUNC_NEVER);
1268
1269 dsa->order_invariance[1].pass_last =
1270 sctx->screen->assume_no_z_fights &&
1271 !dsa->stencil_write_enabled &&
1272 dsa->depth_write_enabled && zfunc_is_ordered;
1273 dsa->order_invariance[0].pass_last =
1274 sctx->screen->assume_no_z_fights &&
1275 dsa->depth_write_enabled && zfunc_is_ordered;
1276
1277 return dsa;
1278 }
1279
1280 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1281 {
1282 struct si_context *sctx = (struct si_context *)ctx;
1283 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1284 struct si_state_dsa *dsa = state;
1285
1286 if (!state)
1287 return;
1288
1289 si_pm4_bind_state(sctx, dsa, dsa);
1290
1291 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1292 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1293 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1294 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1295 }
1296
1297 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1298 sctx->do_update_shaders = true;
1299
1300 if (sctx->screen->dpbb_allowed &&
1301 (!old_dsa ||
1302 (old_dsa->depth_enabled != dsa->depth_enabled ||
1303 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1304 old_dsa->db_can_write != dsa->db_can_write)))
1305 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1306
1307 if (sctx->screen->has_out_of_order_rast &&
1308 (!old_dsa ||
1309 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1310 sizeof(old_dsa->order_invariance))))
1311 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1312 }
1313
1314 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1315 {
1316 struct si_context *sctx = (struct si_context *)ctx;
1317 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1318 }
1319
1320 static void *si_create_db_flush_dsa(struct si_context *sctx)
1321 {
1322 struct pipe_depth_stencil_alpha_state dsa = {};
1323
1324 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1325 }
1326
1327 /* DB RENDER STATE */
1328
1329 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1330 {
1331 struct si_context *sctx = (struct si_context*)ctx;
1332
1333 /* Pipeline stat & streamout queries. */
1334 if (enable) {
1335 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1336 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1337 } else {
1338 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1339 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1340 }
1341
1342 /* Occlusion queries. */
1343 if (sctx->occlusion_queries_disabled != !enable) {
1344 sctx->occlusion_queries_disabled = !enable;
1345 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1346 }
1347 }
1348
1349 void si_set_occlusion_query_state(struct si_context *sctx,
1350 bool old_perfect_enable)
1351 {
1352 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1353
1354 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1355
1356 if (perfect_enable != old_perfect_enable)
1357 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1358 }
1359
1360 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1361 {
1362 st->saved_compute = sctx->cs_shader_state.program;
1363
1364 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1365 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1366 }
1367
1368 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1369 {
1370 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1371 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1372 unsigned db_shader_control;
1373
1374 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1375
1376 /* DB_RENDER_CONTROL */
1377 if (sctx->dbcb_depth_copy_enabled ||
1378 sctx->dbcb_stencil_copy_enabled) {
1379 radeon_emit(cs,
1380 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1381 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1382 S_028000_COPY_CENTROID(1) |
1383 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1384 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1385 radeon_emit(cs,
1386 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1387 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1388 } else {
1389 radeon_emit(cs,
1390 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1391 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1392 }
1393
1394 /* DB_COUNT_CONTROL (occlusion queries) */
1395 if (sctx->num_occlusion_queries > 0 &&
1396 !sctx->occlusion_queries_disabled) {
1397 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1398
1399 if (sctx->chip_class >= CIK) {
1400 radeon_emit(cs,
1401 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1402 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1403 S_028004_ZPASS_ENABLE(1) |
1404 S_028004_SLICE_EVEN_ENABLE(1) |
1405 S_028004_SLICE_ODD_ENABLE(1));
1406 } else {
1407 radeon_emit(cs,
1408 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1409 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1410 }
1411 } else {
1412 /* Disable occlusion queries. */
1413 if (sctx->chip_class >= CIK) {
1414 radeon_emit(cs, 0);
1415 } else {
1416 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1417 }
1418 }
1419
1420 /* DB_RENDER_OVERRIDE2 */
1421 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1422 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1423 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1424 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1425
1426 db_shader_control = sctx->ps_db_shader_control;
1427
1428 /* Bug workaround for smoothing (overrasterization) on SI. */
1429 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1430 db_shader_control &= C_02880C_Z_ORDER;
1431 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1432 }
1433
1434 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1435 if (!rs || !rs->multisample_enable)
1436 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1437
1438 if (sctx->screen->has_rbplus &&
1439 !sctx->screen->rbplus_allowed)
1440 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1441
1442 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1443 db_shader_control);
1444 }
1445
1446 /*
1447 * format translation
1448 */
1449 static uint32_t si_translate_colorformat(enum pipe_format format)
1450 {
1451 const struct util_format_description *desc = util_format_description(format);
1452 if (!desc)
1453 return V_028C70_COLOR_INVALID;
1454
1455 #define HAS_SIZE(x,y,z,w) \
1456 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1457 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1458
1459 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1460 return V_028C70_COLOR_10_11_11;
1461
1462 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1463 return V_028C70_COLOR_INVALID;
1464
1465 /* hw cannot support mixed formats (except depth/stencil, since
1466 * stencil is not written to). */
1467 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1468 return V_028C70_COLOR_INVALID;
1469
1470 switch (desc->nr_channels) {
1471 case 1:
1472 switch (desc->channel[0].size) {
1473 case 8:
1474 return V_028C70_COLOR_8;
1475 case 16:
1476 return V_028C70_COLOR_16;
1477 case 32:
1478 return V_028C70_COLOR_32;
1479 }
1480 break;
1481 case 2:
1482 if (desc->channel[0].size == desc->channel[1].size) {
1483 switch (desc->channel[0].size) {
1484 case 8:
1485 return V_028C70_COLOR_8_8;
1486 case 16:
1487 return V_028C70_COLOR_16_16;
1488 case 32:
1489 return V_028C70_COLOR_32_32;
1490 }
1491 } else if (HAS_SIZE(8,24,0,0)) {
1492 return V_028C70_COLOR_24_8;
1493 } else if (HAS_SIZE(24,8,0,0)) {
1494 return V_028C70_COLOR_8_24;
1495 }
1496 break;
1497 case 3:
1498 if (HAS_SIZE(5,6,5,0)) {
1499 return V_028C70_COLOR_5_6_5;
1500 } else if (HAS_SIZE(32,8,24,0)) {
1501 return V_028C70_COLOR_X24_8_32_FLOAT;
1502 }
1503 break;
1504 case 4:
1505 if (desc->channel[0].size == desc->channel[1].size &&
1506 desc->channel[0].size == desc->channel[2].size &&
1507 desc->channel[0].size == desc->channel[3].size) {
1508 switch (desc->channel[0].size) {
1509 case 4:
1510 return V_028C70_COLOR_4_4_4_4;
1511 case 8:
1512 return V_028C70_COLOR_8_8_8_8;
1513 case 16:
1514 return V_028C70_COLOR_16_16_16_16;
1515 case 32:
1516 return V_028C70_COLOR_32_32_32_32;
1517 }
1518 } else if (HAS_SIZE(5,5,5,1)) {
1519 return V_028C70_COLOR_1_5_5_5;
1520 } else if (HAS_SIZE(1,5,5,5)) {
1521 return V_028C70_COLOR_5_5_5_1;
1522 } else if (HAS_SIZE(10,10,10,2)) {
1523 return V_028C70_COLOR_2_10_10_10;
1524 }
1525 break;
1526 }
1527 return V_028C70_COLOR_INVALID;
1528 }
1529
1530 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1531 {
1532 if (SI_BIG_ENDIAN) {
1533 switch(colorformat) {
1534 /* 8-bit buffers. */
1535 case V_028C70_COLOR_8:
1536 return V_028C70_ENDIAN_NONE;
1537
1538 /* 16-bit buffers. */
1539 case V_028C70_COLOR_5_6_5:
1540 case V_028C70_COLOR_1_5_5_5:
1541 case V_028C70_COLOR_4_4_4_4:
1542 case V_028C70_COLOR_16:
1543 case V_028C70_COLOR_8_8:
1544 return V_028C70_ENDIAN_8IN16;
1545
1546 /* 32-bit buffers. */
1547 case V_028C70_COLOR_8_8_8_8:
1548 case V_028C70_COLOR_2_10_10_10:
1549 case V_028C70_COLOR_8_24:
1550 case V_028C70_COLOR_24_8:
1551 case V_028C70_COLOR_16_16:
1552 return V_028C70_ENDIAN_8IN32;
1553
1554 /* 64-bit buffers. */
1555 case V_028C70_COLOR_16_16_16_16:
1556 return V_028C70_ENDIAN_8IN16;
1557
1558 case V_028C70_COLOR_32_32:
1559 return V_028C70_ENDIAN_8IN32;
1560
1561 /* 128-bit buffers. */
1562 case V_028C70_COLOR_32_32_32_32:
1563 return V_028C70_ENDIAN_8IN32;
1564 default:
1565 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1566 }
1567 } else {
1568 return V_028C70_ENDIAN_NONE;
1569 }
1570 }
1571
1572 static uint32_t si_translate_dbformat(enum pipe_format format)
1573 {
1574 switch (format) {
1575 case PIPE_FORMAT_Z16_UNORM:
1576 return V_028040_Z_16;
1577 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1578 case PIPE_FORMAT_X8Z24_UNORM:
1579 case PIPE_FORMAT_Z24X8_UNORM:
1580 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1581 return V_028040_Z_24; /* deprecated on SI */
1582 case PIPE_FORMAT_Z32_FLOAT:
1583 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1584 return V_028040_Z_32_FLOAT;
1585 default:
1586 return V_028040_Z_INVALID;
1587 }
1588 }
1589
1590 /*
1591 * Texture translation
1592 */
1593
1594 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1595 enum pipe_format format,
1596 const struct util_format_description *desc,
1597 int first_non_void)
1598 {
1599 struct si_screen *sscreen = (struct si_screen*)screen;
1600 bool enable_compressed_formats = (sscreen->info.drm_major == 2 &&
1601 sscreen->info.drm_minor >= 31) ||
1602 sscreen->info.drm_major == 3;
1603 bool uniform = true;
1604 int i;
1605
1606 /* Colorspace (return non-RGB formats directly). */
1607 switch (desc->colorspace) {
1608 /* Depth stencil formats */
1609 case UTIL_FORMAT_COLORSPACE_ZS:
1610 switch (format) {
1611 case PIPE_FORMAT_Z16_UNORM:
1612 return V_008F14_IMG_DATA_FORMAT_16;
1613 case PIPE_FORMAT_X24S8_UINT:
1614 case PIPE_FORMAT_S8X24_UINT:
1615 /*
1616 * Implemented as an 8_8_8_8 data format to fix texture
1617 * gathers in stencil sampling. This affects at least
1618 * GL45-CTS.texture_cube_map_array.sampling on VI.
1619 */
1620 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1621 case PIPE_FORMAT_Z24X8_UNORM:
1622 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1623 return V_008F14_IMG_DATA_FORMAT_8_24;
1624 case PIPE_FORMAT_X8Z24_UNORM:
1625 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1626 return V_008F14_IMG_DATA_FORMAT_24_8;
1627 case PIPE_FORMAT_S8_UINT:
1628 return V_008F14_IMG_DATA_FORMAT_8;
1629 case PIPE_FORMAT_Z32_FLOAT:
1630 return V_008F14_IMG_DATA_FORMAT_32;
1631 case PIPE_FORMAT_X32_S8X24_UINT:
1632 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1633 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1634 default:
1635 goto out_unknown;
1636 }
1637
1638 case UTIL_FORMAT_COLORSPACE_YUV:
1639 goto out_unknown; /* TODO */
1640
1641 case UTIL_FORMAT_COLORSPACE_SRGB:
1642 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1643 goto out_unknown;
1644 break;
1645
1646 default:
1647 break;
1648 }
1649
1650 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1651 if (!enable_compressed_formats)
1652 goto out_unknown;
1653
1654 switch (format) {
1655 case PIPE_FORMAT_RGTC1_SNORM:
1656 case PIPE_FORMAT_LATC1_SNORM:
1657 case PIPE_FORMAT_RGTC1_UNORM:
1658 case PIPE_FORMAT_LATC1_UNORM:
1659 return V_008F14_IMG_DATA_FORMAT_BC4;
1660 case PIPE_FORMAT_RGTC2_SNORM:
1661 case PIPE_FORMAT_LATC2_SNORM:
1662 case PIPE_FORMAT_RGTC2_UNORM:
1663 case PIPE_FORMAT_LATC2_UNORM:
1664 return V_008F14_IMG_DATA_FORMAT_BC5;
1665 default:
1666 goto out_unknown;
1667 }
1668 }
1669
1670 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1671 (sscreen->info.family == CHIP_STONEY ||
1672 sscreen->info.family == CHIP_VEGA10 ||
1673 sscreen->info.family == CHIP_RAVEN)) {
1674 switch (format) {
1675 case PIPE_FORMAT_ETC1_RGB8:
1676 case PIPE_FORMAT_ETC2_RGB8:
1677 case PIPE_FORMAT_ETC2_SRGB8:
1678 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1679 case PIPE_FORMAT_ETC2_RGB8A1:
1680 case PIPE_FORMAT_ETC2_SRGB8A1:
1681 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1682 case PIPE_FORMAT_ETC2_RGBA8:
1683 case PIPE_FORMAT_ETC2_SRGBA8:
1684 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1685 case PIPE_FORMAT_ETC2_R11_UNORM:
1686 case PIPE_FORMAT_ETC2_R11_SNORM:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1688 case PIPE_FORMAT_ETC2_RG11_UNORM:
1689 case PIPE_FORMAT_ETC2_RG11_SNORM:
1690 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1691 default:
1692 goto out_unknown;
1693 }
1694 }
1695
1696 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1697 if (!enable_compressed_formats)
1698 goto out_unknown;
1699
1700 switch (format) {
1701 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1702 case PIPE_FORMAT_BPTC_SRGBA:
1703 return V_008F14_IMG_DATA_FORMAT_BC7;
1704 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1705 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1706 return V_008F14_IMG_DATA_FORMAT_BC6;
1707 default:
1708 goto out_unknown;
1709 }
1710 }
1711
1712 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1713 switch (format) {
1714 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1715 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1716 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1717 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1718 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1719 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1720 default:
1721 goto out_unknown;
1722 }
1723 }
1724
1725 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1726 if (!enable_compressed_formats)
1727 goto out_unknown;
1728
1729 switch (format) {
1730 case PIPE_FORMAT_DXT1_RGB:
1731 case PIPE_FORMAT_DXT1_RGBA:
1732 case PIPE_FORMAT_DXT1_SRGB:
1733 case PIPE_FORMAT_DXT1_SRGBA:
1734 return V_008F14_IMG_DATA_FORMAT_BC1;
1735 case PIPE_FORMAT_DXT3_RGBA:
1736 case PIPE_FORMAT_DXT3_SRGBA:
1737 return V_008F14_IMG_DATA_FORMAT_BC2;
1738 case PIPE_FORMAT_DXT5_RGBA:
1739 case PIPE_FORMAT_DXT5_SRGBA:
1740 return V_008F14_IMG_DATA_FORMAT_BC3;
1741 default:
1742 goto out_unknown;
1743 }
1744 }
1745
1746 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1747 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1748 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1749 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1750 }
1751
1752 /* R8G8Bx_SNORM - TODO CxV8U8 */
1753
1754 /* hw cannot support mixed formats (except depth/stencil, since only
1755 * depth is read).*/
1756 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1757 goto out_unknown;
1758
1759 /* See whether the components are of the same size. */
1760 for (i = 1; i < desc->nr_channels; i++) {
1761 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1762 }
1763
1764 /* Non-uniform formats. */
1765 if (!uniform) {
1766 switch(desc->nr_channels) {
1767 case 3:
1768 if (desc->channel[0].size == 5 &&
1769 desc->channel[1].size == 6 &&
1770 desc->channel[2].size == 5) {
1771 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1772 }
1773 goto out_unknown;
1774 case 4:
1775 if (desc->channel[0].size == 5 &&
1776 desc->channel[1].size == 5 &&
1777 desc->channel[2].size == 5 &&
1778 desc->channel[3].size == 1) {
1779 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1780 }
1781 if (desc->channel[0].size == 1 &&
1782 desc->channel[1].size == 5 &&
1783 desc->channel[2].size == 5 &&
1784 desc->channel[3].size == 5) {
1785 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1786 }
1787 if (desc->channel[0].size == 10 &&
1788 desc->channel[1].size == 10 &&
1789 desc->channel[2].size == 10 &&
1790 desc->channel[3].size == 2) {
1791 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1792 }
1793 goto out_unknown;
1794 }
1795 goto out_unknown;
1796 }
1797
1798 if (first_non_void < 0 || first_non_void > 3)
1799 goto out_unknown;
1800
1801 /* uniform formats */
1802 switch (desc->channel[first_non_void].size) {
1803 case 4:
1804 switch (desc->nr_channels) {
1805 #if 0 /* Not supported for render targets */
1806 case 2:
1807 return V_008F14_IMG_DATA_FORMAT_4_4;
1808 #endif
1809 case 4:
1810 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1811 }
1812 break;
1813 case 8:
1814 switch (desc->nr_channels) {
1815 case 1:
1816 return V_008F14_IMG_DATA_FORMAT_8;
1817 case 2:
1818 return V_008F14_IMG_DATA_FORMAT_8_8;
1819 case 4:
1820 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1821 }
1822 break;
1823 case 16:
1824 switch (desc->nr_channels) {
1825 case 1:
1826 return V_008F14_IMG_DATA_FORMAT_16;
1827 case 2:
1828 return V_008F14_IMG_DATA_FORMAT_16_16;
1829 case 4:
1830 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1831 }
1832 break;
1833 case 32:
1834 switch (desc->nr_channels) {
1835 case 1:
1836 return V_008F14_IMG_DATA_FORMAT_32;
1837 case 2:
1838 return V_008F14_IMG_DATA_FORMAT_32_32;
1839 #if 0 /* Not supported for render targets */
1840 case 3:
1841 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1842 #endif
1843 case 4:
1844 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1845 }
1846 }
1847
1848 out_unknown:
1849 return ~0;
1850 }
1851
1852 static unsigned si_tex_wrap(unsigned wrap)
1853 {
1854 switch (wrap) {
1855 default:
1856 case PIPE_TEX_WRAP_REPEAT:
1857 return V_008F30_SQ_TEX_WRAP;
1858 case PIPE_TEX_WRAP_CLAMP:
1859 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1860 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1861 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1862 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1863 return V_008F30_SQ_TEX_CLAMP_BORDER;
1864 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1865 return V_008F30_SQ_TEX_MIRROR;
1866 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1867 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1868 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1869 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1870 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1871 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1872 }
1873 }
1874
1875 static unsigned si_tex_mipfilter(unsigned filter)
1876 {
1877 switch (filter) {
1878 case PIPE_TEX_MIPFILTER_NEAREST:
1879 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1880 case PIPE_TEX_MIPFILTER_LINEAR:
1881 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1882 default:
1883 case PIPE_TEX_MIPFILTER_NONE:
1884 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1885 }
1886 }
1887
1888 static unsigned si_tex_compare(unsigned compare)
1889 {
1890 switch (compare) {
1891 default:
1892 case PIPE_FUNC_NEVER:
1893 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1894 case PIPE_FUNC_LESS:
1895 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1896 case PIPE_FUNC_EQUAL:
1897 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1898 case PIPE_FUNC_LEQUAL:
1899 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1900 case PIPE_FUNC_GREATER:
1901 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1902 case PIPE_FUNC_NOTEQUAL:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1904 case PIPE_FUNC_GEQUAL:
1905 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1906 case PIPE_FUNC_ALWAYS:
1907 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1908 }
1909 }
1910
1911 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1912 unsigned view_target, unsigned nr_samples)
1913 {
1914 unsigned res_target = rtex->resource.b.b.target;
1915
1916 if (view_target == PIPE_TEXTURE_CUBE ||
1917 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1918 res_target = view_target;
1919 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1920 else if (res_target == PIPE_TEXTURE_CUBE ||
1921 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1922 res_target = PIPE_TEXTURE_2D_ARRAY;
1923
1924 /* GFX9 allocates 1D textures as 2D. */
1925 if ((res_target == PIPE_TEXTURE_1D ||
1926 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1927 sscreen->info.chip_class >= GFX9 &&
1928 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1929 if (res_target == PIPE_TEXTURE_1D)
1930 res_target = PIPE_TEXTURE_2D;
1931 else
1932 res_target = PIPE_TEXTURE_2D_ARRAY;
1933 }
1934
1935 switch (res_target) {
1936 default:
1937 case PIPE_TEXTURE_1D:
1938 return V_008F1C_SQ_RSRC_IMG_1D;
1939 case PIPE_TEXTURE_1D_ARRAY:
1940 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1941 case PIPE_TEXTURE_2D:
1942 case PIPE_TEXTURE_RECT:
1943 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1944 V_008F1C_SQ_RSRC_IMG_2D;
1945 case PIPE_TEXTURE_2D_ARRAY:
1946 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1947 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1948 case PIPE_TEXTURE_3D:
1949 return V_008F1C_SQ_RSRC_IMG_3D;
1950 case PIPE_TEXTURE_CUBE:
1951 case PIPE_TEXTURE_CUBE_ARRAY:
1952 return V_008F1C_SQ_RSRC_IMG_CUBE;
1953 }
1954 }
1955
1956 /*
1957 * Format support testing
1958 */
1959
1960 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1961 {
1962 const struct util_format_description *desc = util_format_description(format);
1963 if (!desc)
1964 return false;
1965
1966 return si_translate_texformat(screen, format, desc,
1967 util_format_get_first_non_void_channel(format)) != ~0U;
1968 }
1969
1970 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1971 const struct util_format_description *desc,
1972 int first_non_void)
1973 {
1974 int i;
1975
1976 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1977 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1978
1979 assert(first_non_void >= 0);
1980
1981 if (desc->nr_channels == 4 &&
1982 desc->channel[0].size == 10 &&
1983 desc->channel[1].size == 10 &&
1984 desc->channel[2].size == 10 &&
1985 desc->channel[3].size == 2)
1986 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1987
1988 /* See whether the components are of the same size. */
1989 for (i = 0; i < desc->nr_channels; i++) {
1990 if (desc->channel[first_non_void].size != desc->channel[i].size)
1991 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1992 }
1993
1994 switch (desc->channel[first_non_void].size) {
1995 case 8:
1996 switch (desc->nr_channels) {
1997 case 1:
1998 case 3: /* 3 loads */
1999 return V_008F0C_BUF_DATA_FORMAT_8;
2000 case 2:
2001 return V_008F0C_BUF_DATA_FORMAT_8_8;
2002 case 4:
2003 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2004 }
2005 break;
2006 case 16:
2007 switch (desc->nr_channels) {
2008 case 1:
2009 case 3: /* 3 loads */
2010 return V_008F0C_BUF_DATA_FORMAT_16;
2011 case 2:
2012 return V_008F0C_BUF_DATA_FORMAT_16_16;
2013 case 4:
2014 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2015 }
2016 break;
2017 case 32:
2018 switch (desc->nr_channels) {
2019 case 1:
2020 return V_008F0C_BUF_DATA_FORMAT_32;
2021 case 2:
2022 return V_008F0C_BUF_DATA_FORMAT_32_32;
2023 case 3:
2024 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2025 case 4:
2026 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2027 }
2028 break;
2029 case 64:
2030 /* Legacy double formats. */
2031 switch (desc->nr_channels) {
2032 case 1: /* 1 load */
2033 return V_008F0C_BUF_DATA_FORMAT_32_32;
2034 case 2: /* 1 load */
2035 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2036 case 3: /* 3 loads */
2037 return V_008F0C_BUF_DATA_FORMAT_32_32;
2038 case 4: /* 2 loads */
2039 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2040 }
2041 break;
2042 }
2043
2044 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2045 }
2046
2047 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2048 const struct util_format_description *desc,
2049 int first_non_void)
2050 {
2051 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2052 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2053
2054 assert(first_non_void >= 0);
2055
2056 switch (desc->channel[first_non_void].type) {
2057 case UTIL_FORMAT_TYPE_SIGNED:
2058 case UTIL_FORMAT_TYPE_FIXED:
2059 if (desc->channel[first_non_void].size >= 32 ||
2060 desc->channel[first_non_void].pure_integer)
2061 return V_008F0C_BUF_NUM_FORMAT_SINT;
2062 else if (desc->channel[first_non_void].normalized)
2063 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2064 else
2065 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2066 break;
2067 case UTIL_FORMAT_TYPE_UNSIGNED:
2068 if (desc->channel[first_non_void].size >= 32 ||
2069 desc->channel[first_non_void].pure_integer)
2070 return V_008F0C_BUF_NUM_FORMAT_UINT;
2071 else if (desc->channel[first_non_void].normalized)
2072 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2073 else
2074 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2075 break;
2076 case UTIL_FORMAT_TYPE_FLOAT:
2077 default:
2078 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2079 }
2080 }
2081
2082 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2083 enum pipe_format format,
2084 unsigned usage)
2085 {
2086 const struct util_format_description *desc;
2087 int first_non_void;
2088 unsigned data_format;
2089
2090 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2091 PIPE_BIND_SAMPLER_VIEW |
2092 PIPE_BIND_VERTEX_BUFFER)) == 0);
2093
2094 desc = util_format_description(format);
2095 if (!desc)
2096 return 0;
2097
2098 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2099 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2100 * for read-only access (with caveats surrounding bounds checks), but
2101 * obviously fails for write access which we have to implement for
2102 * shader images. Luckily, OpenGL doesn't expect this to be supported
2103 * anyway, and so the only impact is on PBO uploads / downloads, which
2104 * shouldn't be expected to be fast for GL_RGB anyway.
2105 */
2106 if (desc->block.bits == 3 * 8 ||
2107 desc->block.bits == 3 * 16) {
2108 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2109 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2110 if (!usage)
2111 return 0;
2112 }
2113 }
2114
2115 first_non_void = util_format_get_first_non_void_channel(format);
2116 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2117 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2118 return 0;
2119
2120 return usage;
2121 }
2122
2123 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2124 {
2125 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2126 si_translate_colorswap(format, false) != ~0U;
2127 }
2128
2129 static bool si_is_zs_format_supported(enum pipe_format format)
2130 {
2131 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2132 }
2133
2134 static boolean si_is_format_supported(struct pipe_screen *screen,
2135 enum pipe_format format,
2136 enum pipe_texture_target target,
2137 unsigned sample_count,
2138 unsigned usage)
2139 {
2140 unsigned retval = 0;
2141
2142 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2143 PRINT_ERR("r600: unsupported texture type %d\n", target);
2144 return false;
2145 }
2146
2147 if (!util_format_is_supported(format, usage))
2148 return false;
2149
2150 if (sample_count > 1) {
2151 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2152 return false;
2153
2154 if (usage & PIPE_BIND_SHADER_IMAGE)
2155 return false;
2156
2157 switch (sample_count) {
2158 case 2:
2159 case 4:
2160 case 8:
2161 break;
2162 case 16:
2163 if (format == PIPE_FORMAT_NONE)
2164 return true;
2165 else
2166 return false;
2167 default:
2168 return false;
2169 }
2170 }
2171
2172 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2173 PIPE_BIND_SHADER_IMAGE)) {
2174 if (target == PIPE_BUFFER) {
2175 retval |= si_is_vertex_format_supported(
2176 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2177 PIPE_BIND_SHADER_IMAGE));
2178 } else {
2179 if (si_is_sampler_format_supported(screen, format))
2180 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2181 PIPE_BIND_SHADER_IMAGE);
2182 }
2183 }
2184
2185 if ((usage & (PIPE_BIND_RENDER_TARGET |
2186 PIPE_BIND_DISPLAY_TARGET |
2187 PIPE_BIND_SCANOUT |
2188 PIPE_BIND_SHARED |
2189 PIPE_BIND_BLENDABLE)) &&
2190 si_is_colorbuffer_format_supported(format)) {
2191 retval |= usage &
2192 (PIPE_BIND_RENDER_TARGET |
2193 PIPE_BIND_DISPLAY_TARGET |
2194 PIPE_BIND_SCANOUT |
2195 PIPE_BIND_SHARED);
2196 if (!util_format_is_pure_integer(format) &&
2197 !util_format_is_depth_or_stencil(format))
2198 retval |= usage & PIPE_BIND_BLENDABLE;
2199 }
2200
2201 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2202 si_is_zs_format_supported(format)) {
2203 retval |= PIPE_BIND_DEPTH_STENCIL;
2204 }
2205
2206 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2207 retval |= si_is_vertex_format_supported(screen, format,
2208 PIPE_BIND_VERTEX_BUFFER);
2209 }
2210
2211 if ((usage & PIPE_BIND_LINEAR) &&
2212 !util_format_is_compressed(format) &&
2213 !(usage & PIPE_BIND_DEPTH_STENCIL))
2214 retval |= PIPE_BIND_LINEAR;
2215
2216 return retval == usage;
2217 }
2218
2219 /*
2220 * framebuffer handling
2221 */
2222
2223 static void si_choose_spi_color_formats(struct r600_surface *surf,
2224 unsigned format, unsigned swap,
2225 unsigned ntype, bool is_depth)
2226 {
2227 /* Alpha is needed for alpha-to-coverage.
2228 * Blending may be with or without alpha.
2229 */
2230 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2231 unsigned alpha = 0; /* exports alpha, but may not support blending */
2232 unsigned blend = 0; /* supports blending, but may not export alpha */
2233 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2234
2235 /* Choose the SPI color formats. These are required values for RB+.
2236 * Other chips have multiple choices, though they are not necessarily better.
2237 */
2238 switch (format) {
2239 case V_028C70_COLOR_5_6_5:
2240 case V_028C70_COLOR_1_5_5_5:
2241 case V_028C70_COLOR_5_5_5_1:
2242 case V_028C70_COLOR_4_4_4_4:
2243 case V_028C70_COLOR_10_11_11:
2244 case V_028C70_COLOR_11_11_10:
2245 case V_028C70_COLOR_8:
2246 case V_028C70_COLOR_8_8:
2247 case V_028C70_COLOR_8_8_8_8:
2248 case V_028C70_COLOR_10_10_10_2:
2249 case V_028C70_COLOR_2_10_10_10:
2250 if (ntype == V_028C70_NUMBER_UINT)
2251 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2252 else if (ntype == V_028C70_NUMBER_SINT)
2253 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2254 else
2255 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2256 break;
2257
2258 case V_028C70_COLOR_16:
2259 case V_028C70_COLOR_16_16:
2260 case V_028C70_COLOR_16_16_16_16:
2261 if (ntype == V_028C70_NUMBER_UNORM ||
2262 ntype == V_028C70_NUMBER_SNORM) {
2263 /* UNORM16 and SNORM16 don't support blending */
2264 if (ntype == V_028C70_NUMBER_UNORM)
2265 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2266 else
2267 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2268
2269 /* Use 32 bits per channel for blending. */
2270 if (format == V_028C70_COLOR_16) {
2271 if (swap == V_028C70_SWAP_STD) { /* R */
2272 blend = V_028714_SPI_SHADER_32_R;
2273 blend_alpha = V_028714_SPI_SHADER_32_AR;
2274 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2275 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2276 else
2277 assert(0);
2278 } else if (format == V_028C70_COLOR_16_16) {
2279 if (swap == V_028C70_SWAP_STD) { /* RG */
2280 blend = V_028714_SPI_SHADER_32_GR;
2281 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2282 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2283 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2284 else
2285 assert(0);
2286 } else /* 16_16_16_16 */
2287 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2288 } else if (ntype == V_028C70_NUMBER_UINT)
2289 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2290 else if (ntype == V_028C70_NUMBER_SINT)
2291 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2292 else if (ntype == V_028C70_NUMBER_FLOAT)
2293 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2294 else
2295 assert(0);
2296 break;
2297
2298 case V_028C70_COLOR_32:
2299 if (swap == V_028C70_SWAP_STD) { /* R */
2300 blend = normal = V_028714_SPI_SHADER_32_R;
2301 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2302 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2303 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2304 else
2305 assert(0);
2306 break;
2307
2308 case V_028C70_COLOR_32_32:
2309 if (swap == V_028C70_SWAP_STD) { /* RG */
2310 blend = normal = V_028714_SPI_SHADER_32_GR;
2311 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2312 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2313 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2314 else
2315 assert(0);
2316 break;
2317
2318 case V_028C70_COLOR_32_32_32_32:
2319 case V_028C70_COLOR_8_24:
2320 case V_028C70_COLOR_24_8:
2321 case V_028C70_COLOR_X24_8_32_FLOAT:
2322 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2323 break;
2324
2325 default:
2326 assert(0);
2327 return;
2328 }
2329
2330 /* The DB->CB copy needs 32_ABGR. */
2331 if (is_depth)
2332 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2333
2334 surf->spi_shader_col_format = normal;
2335 surf->spi_shader_col_format_alpha = alpha;
2336 surf->spi_shader_col_format_blend = blend;
2337 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2338 }
2339
2340 static void si_initialize_color_surface(struct si_context *sctx,
2341 struct r600_surface *surf)
2342 {
2343 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2344 unsigned color_info, color_attrib;
2345 unsigned format, swap, ntype, endian;
2346 const struct util_format_description *desc;
2347 int firstchan;
2348 unsigned blend_clamp = 0, blend_bypass = 0;
2349
2350 desc = util_format_description(surf->base.format);
2351 for (firstchan = 0; firstchan < 4; firstchan++) {
2352 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2353 break;
2354 }
2355 }
2356 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2357 ntype = V_028C70_NUMBER_FLOAT;
2358 } else {
2359 ntype = V_028C70_NUMBER_UNORM;
2360 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2361 ntype = V_028C70_NUMBER_SRGB;
2362 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2363 if (desc->channel[firstchan].pure_integer) {
2364 ntype = V_028C70_NUMBER_SINT;
2365 } else {
2366 assert(desc->channel[firstchan].normalized);
2367 ntype = V_028C70_NUMBER_SNORM;
2368 }
2369 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2370 if (desc->channel[firstchan].pure_integer) {
2371 ntype = V_028C70_NUMBER_UINT;
2372 } else {
2373 assert(desc->channel[firstchan].normalized);
2374 ntype = V_028C70_NUMBER_UNORM;
2375 }
2376 }
2377 }
2378
2379 format = si_translate_colorformat(surf->base.format);
2380 if (format == V_028C70_COLOR_INVALID) {
2381 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2382 }
2383 assert(format != V_028C70_COLOR_INVALID);
2384 swap = si_translate_colorswap(surf->base.format, false);
2385 endian = si_colorformat_endian_swap(format);
2386
2387 /* blend clamp should be set for all NORM/SRGB types */
2388 if (ntype == V_028C70_NUMBER_UNORM ||
2389 ntype == V_028C70_NUMBER_SNORM ||
2390 ntype == V_028C70_NUMBER_SRGB)
2391 blend_clamp = 1;
2392
2393 /* set blend bypass according to docs if SINT/UINT or
2394 8/24 COLOR variants */
2395 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2396 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2397 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2398 blend_clamp = 0;
2399 blend_bypass = 1;
2400 }
2401
2402 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2403 if (format == V_028C70_COLOR_8 ||
2404 format == V_028C70_COLOR_8_8 ||
2405 format == V_028C70_COLOR_8_8_8_8)
2406 surf->color_is_int8 = true;
2407 else if (format == V_028C70_COLOR_10_10_10_2 ||
2408 format == V_028C70_COLOR_2_10_10_10)
2409 surf->color_is_int10 = true;
2410 }
2411
2412 color_info = S_028C70_FORMAT(format) |
2413 S_028C70_COMP_SWAP(swap) |
2414 S_028C70_BLEND_CLAMP(blend_clamp) |
2415 S_028C70_BLEND_BYPASS(blend_bypass) |
2416 S_028C70_SIMPLE_FLOAT(1) |
2417 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2418 ntype != V_028C70_NUMBER_SNORM &&
2419 ntype != V_028C70_NUMBER_SRGB &&
2420 format != V_028C70_COLOR_8_24 &&
2421 format != V_028C70_COLOR_24_8) |
2422 S_028C70_NUMBER_TYPE(ntype) |
2423 S_028C70_ENDIAN(endian);
2424
2425 /* Intensity is implemented as Red, so treat it that way. */
2426 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2427 util_format_is_intensity(surf->base.format));
2428
2429 if (rtex->resource.b.b.nr_samples > 1) {
2430 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2431
2432 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2433 S_028C74_NUM_FRAGMENTS(log_samples);
2434
2435 if (rtex->fmask.size) {
2436 color_info |= S_028C70_COMPRESSION(1);
2437 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2438
2439 if (sctx->chip_class == SI) {
2440 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2441 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2442 }
2443 }
2444 }
2445
2446 if (sctx->chip_class >= VI) {
2447 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2448 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2449
2450 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2451 64 for APU because all of our APUs to date use DIMMs which have
2452 a request granularity size of 64B while all other chips have a
2453 32B request size */
2454 if (!sctx->screen->info.has_dedicated_vram)
2455 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2456
2457 if (rtex->resource.b.b.nr_samples > 1) {
2458 if (rtex->surface.bpe == 1)
2459 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2460 else if (rtex->surface.bpe == 2)
2461 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2462 }
2463
2464 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2465 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2466 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2467 }
2468
2469 /* This must be set for fast clear to work without FMASK. */
2470 if (!rtex->fmask.size && sctx->chip_class == SI) {
2471 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2472 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2473 }
2474
2475 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2476 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2477
2478 if (sctx->chip_class >= GFX9) {
2479 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2480
2481 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2482 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2483 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2484 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2485 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2486 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2487 }
2488
2489 surf->cb_color_view = color_view;
2490 surf->cb_color_info = color_info;
2491 surf->cb_color_attrib = color_attrib;
2492
2493 /* Determine pixel shader export format */
2494 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2495
2496 surf->color_initialized = true;
2497 }
2498
2499 static void si_init_depth_surface(struct si_context *sctx,
2500 struct r600_surface *surf)
2501 {
2502 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2503 unsigned level = surf->base.u.tex.level;
2504 unsigned format, stencil_format;
2505 uint32_t z_info, s_info;
2506
2507 format = si_translate_dbformat(rtex->db_render_format);
2508 stencil_format = rtex->surface.has_stencil ?
2509 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2510
2511 assert(format != V_028040_Z_INVALID);
2512 if (format == V_028040_Z_INVALID)
2513 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2514
2515 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2516 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2517 surf->db_htile_data_base = 0;
2518 surf->db_htile_surface = 0;
2519
2520 if (sctx->chip_class >= GFX9) {
2521 assert(rtex->surface.u.gfx9.surf_offset == 0);
2522 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2523 surf->db_stencil_base = (rtex->resource.gpu_address +
2524 rtex->surface.u.gfx9.stencil_offset) >> 8;
2525 z_info = S_028038_FORMAT(format) |
2526 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2527 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2528 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2529 s_info = S_02803C_FORMAT(stencil_format) |
2530 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2531 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2532 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2533 surf->db_depth_view |= S_028008_MIPID(level);
2534 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2535 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2536
2537 if (si_htile_enabled(rtex, level)) {
2538 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2539 S_028038_ALLOW_EXPCLEAR(1);
2540
2541 if (rtex->tc_compatible_htile) {
2542 unsigned max_zplanes = 4;
2543
2544 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2545 rtex->resource.b.b.nr_samples > 1)
2546 max_zplanes = 2;
2547
2548 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2549 S_028038_ITERATE_FLUSH(1);
2550 s_info |= S_02803C_ITERATE_FLUSH(1);
2551 }
2552
2553 if (rtex->surface.has_stencil) {
2554 /* Stencil buffer workaround ported from the SI-CI-VI code.
2555 * See that for explanation.
2556 */
2557 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2558 } else {
2559 /* Use all HTILE for depth if there's no stencil. */
2560 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2561 }
2562
2563 surf->db_htile_data_base = (rtex->resource.gpu_address +
2564 rtex->htile_offset) >> 8;
2565 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2566 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2567 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2568 }
2569 } else {
2570 /* SI-CI-VI */
2571 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2572
2573 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2574
2575 surf->db_depth_base = (rtex->resource.gpu_address +
2576 rtex->surface.u.legacy.level[level].offset) >> 8;
2577 surf->db_stencil_base = (rtex->resource.gpu_address +
2578 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2579
2580 z_info = S_028040_FORMAT(format) |
2581 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2582 s_info = S_028044_FORMAT(stencil_format);
2583 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2584
2585 if (sctx->chip_class >= CIK) {
2586 struct radeon_info *info = &sctx->screen->info;
2587 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2588 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2589 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2590 unsigned tile_mode = info->si_tile_mode_array[index];
2591 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2592 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2593
2594 surf->db_depth_info |=
2595 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2596 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2597 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2598 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2599 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2600 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2601 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2602 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2603 } else {
2604 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2605 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2606 tile_mode_index = si_tile_mode_index(rtex, level, true);
2607 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2608 }
2609
2610 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2611 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2612 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2613 levelinfo->nblk_y) / 64 - 1);
2614
2615 if (si_htile_enabled(rtex, level)) {
2616 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2617 S_028040_ALLOW_EXPCLEAR(1);
2618
2619 if (rtex->surface.has_stencil) {
2620 /* Workaround: For a not yet understood reason, the
2621 * combination of MSAA, fast stencil clear and stencil
2622 * decompress messes with subsequent stencil buffer
2623 * uses. Problem was reproduced on Verde, Bonaire,
2624 * Tonga, and Carrizo.
2625 *
2626 * Disabling EXPCLEAR works around the problem.
2627 *
2628 * Check piglit's arb_texture_multisample-stencil-clear
2629 * test if you want to try changing this.
2630 */
2631 if (rtex->resource.b.b.nr_samples <= 1)
2632 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2633 } else if (!rtex->tc_compatible_htile) {
2634 /* Use all of the htile_buffer for depth if there's no stencil.
2635 * This must not be set when TC-compatible HTILE is enabled
2636 * due to a hw bug.
2637 */
2638 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2639 }
2640
2641 surf->db_htile_data_base = (rtex->resource.gpu_address +
2642 rtex->htile_offset) >> 8;
2643 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2644
2645 if (rtex->tc_compatible_htile) {
2646 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2647
2648 if (rtex->resource.b.b.nr_samples <= 1)
2649 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2650 else if (rtex->resource.b.b.nr_samples <= 4)
2651 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2652 else
2653 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2654 }
2655 }
2656 }
2657
2658 surf->db_z_info = z_info;
2659 surf->db_stencil_info = s_info;
2660
2661 surf->depth_initialized = true;
2662 }
2663
2664 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2665 {
2666 if (sctx->decompression_enabled)
2667 return;
2668
2669 if (sctx->framebuffer.state.zsbuf) {
2670 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2671 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2672
2673 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2674
2675 if (rtex->surface.has_stencil)
2676 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2677 }
2678
2679 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2680 while (compressed_cb_mask) {
2681 unsigned i = u_bit_scan(&compressed_cb_mask);
2682 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2683 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2684
2685 if (rtex->fmask.size)
2686 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2687 if (rtex->dcc_gather_statistics)
2688 rtex->separate_dcc_dirty = true;
2689 }
2690 }
2691
2692 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2693 {
2694 for (int i = 0; i < state->nr_cbufs; ++i) {
2695 struct r600_surface *surf = NULL;
2696 struct r600_texture *rtex;
2697
2698 if (!state->cbufs[i])
2699 continue;
2700 surf = (struct r600_surface*)state->cbufs[i];
2701 rtex = (struct r600_texture*)surf->base.texture;
2702
2703 p_atomic_dec(&rtex->framebuffers_bound);
2704 }
2705 }
2706
2707 static void si_set_framebuffer_state(struct pipe_context *ctx,
2708 const struct pipe_framebuffer_state *state)
2709 {
2710 struct si_context *sctx = (struct si_context *)ctx;
2711 struct pipe_constant_buffer constbuf = {0};
2712 struct r600_surface *surf = NULL;
2713 struct r600_texture *rtex;
2714 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2715 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2716 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2717 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2718 bool old_has_stencil =
2719 old_has_zsbuf &&
2720 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2721 bool unbound = false;
2722 int i;
2723
2724 si_update_fb_dirtiness_after_rendering(sctx);
2725
2726 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2727 if (!sctx->framebuffer.state.cbufs[i])
2728 continue;
2729
2730 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2731 if (rtex->dcc_gather_statistics)
2732 vi_separate_dcc_stop_query(sctx, rtex);
2733 }
2734
2735 /* Disable DCC if the formats are incompatible. */
2736 for (i = 0; i < state->nr_cbufs; i++) {
2737 if (!state->cbufs[i])
2738 continue;
2739
2740 surf = (struct r600_surface*)state->cbufs[i];
2741 rtex = (struct r600_texture*)surf->base.texture;
2742
2743 if (!surf->dcc_incompatible)
2744 continue;
2745
2746 /* Since the DCC decompression calls back into set_framebuffer-
2747 * _state, we need to unbind the framebuffer, so that
2748 * vi_separate_dcc_stop_query isn't called twice with the same
2749 * color buffer.
2750 */
2751 if (!unbound) {
2752 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2753 unbound = true;
2754 }
2755
2756 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2757 if (!si_texture_disable_dcc(sctx, rtex))
2758 si_decompress_dcc(sctx, rtex);
2759
2760 surf->dcc_incompatible = false;
2761 }
2762
2763 /* Only flush TC when changing the framebuffer state, because
2764 * the only client not using TC that can change textures is
2765 * the framebuffer.
2766 *
2767 * Wait for compute shaders because of possible transitions:
2768 * - FB write -> shader read
2769 * - shader write -> FB read
2770 *
2771 * DB caches are flushed on demand (using si_decompress_textures).
2772 *
2773 * When MSAA is enabled, CB and TC caches are flushed on demand
2774 * (after FMASK decompression). Shader write -> FB read transitions
2775 * cannot happen for MSAA textures, because MSAA shader images are
2776 * not supported.
2777 *
2778 * Only flush and wait for CB if there is actually a bound color buffer.
2779 */
2780 if (sctx->framebuffer.uncompressed_cb_mask)
2781 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2782 sctx->framebuffer.CB_has_shader_readable_metadata);
2783
2784 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2785
2786 /* u_blitter doesn't invoke depth decompression when it does multiple
2787 * blits in a row, but the only case when it matters for DB is when
2788 * doing generate_mipmap. So here we flush DB manually between
2789 * individual generate_mipmap blits.
2790 * Note that lower mipmap levels aren't compressed.
2791 */
2792 if (sctx->generate_mipmap_for_depth) {
2793 si_make_DB_shader_coherent(sctx, 1, false,
2794 sctx->framebuffer.DB_has_shader_readable_metadata);
2795 } else if (sctx->chip_class == GFX9) {
2796 /* It appears that DB metadata "leaks" in a sequence of:
2797 * - depth clear
2798 * - DCC decompress for shader image writes (with DB disabled)
2799 * - render with DEPTH_BEFORE_SHADER=1
2800 * Flushing DB metadata works around the problem.
2801 */
2802 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2803 }
2804
2805 /* Take the maximum of the old and new count. If the new count is lower,
2806 * dirtying is needed to disable the unbound colorbuffers.
2807 */
2808 sctx->framebuffer.dirty_cbufs |=
2809 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2810 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2811
2812 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2813 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2814
2815 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2816 sctx->framebuffer.spi_shader_col_format = 0;
2817 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2818 sctx->framebuffer.spi_shader_col_format_blend = 0;
2819 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2820 sctx->framebuffer.color_is_int8 = 0;
2821 sctx->framebuffer.color_is_int10 = 0;
2822
2823 sctx->framebuffer.compressed_cb_mask = 0;
2824 sctx->framebuffer.uncompressed_cb_mask = 0;
2825 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2826 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2827 sctx->framebuffer.any_dst_linear = false;
2828 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2829 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2830
2831 for (i = 0; i < state->nr_cbufs; i++) {
2832 if (!state->cbufs[i])
2833 continue;
2834
2835 surf = (struct r600_surface*)state->cbufs[i];
2836 rtex = (struct r600_texture*)surf->base.texture;
2837
2838 if (!surf->color_initialized) {
2839 si_initialize_color_surface(sctx, surf);
2840 }
2841
2842 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2843 sctx->framebuffer.spi_shader_col_format |=
2844 surf->spi_shader_col_format << (i * 4);
2845 sctx->framebuffer.spi_shader_col_format_alpha |=
2846 surf->spi_shader_col_format_alpha << (i * 4);
2847 sctx->framebuffer.spi_shader_col_format_blend |=
2848 surf->spi_shader_col_format_blend << (i * 4);
2849 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2850 surf->spi_shader_col_format_blend_alpha << (i * 4);
2851
2852 if (surf->color_is_int8)
2853 sctx->framebuffer.color_is_int8 |= 1 << i;
2854 if (surf->color_is_int10)
2855 sctx->framebuffer.color_is_int10 |= 1 << i;
2856
2857 if (rtex->fmask.size)
2858 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2859 else
2860 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2861
2862 if (rtex->surface.is_linear)
2863 sctx->framebuffer.any_dst_linear = true;
2864
2865 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2866 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2867
2868 si_context_add_resource_size(sctx, surf->base.texture);
2869
2870 p_atomic_inc(&rtex->framebuffers_bound);
2871
2872 if (rtex->dcc_gather_statistics) {
2873 /* Dirty tracking must be enabled for DCC usage analysis. */
2874 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2875 vi_separate_dcc_start_query(sctx, rtex);
2876 }
2877 }
2878
2879 struct r600_texture *zstex = NULL;
2880
2881 if (state->zsbuf) {
2882 surf = (struct r600_surface*)state->zsbuf;
2883 zstex = (struct r600_texture*)surf->base.texture;
2884
2885 if (!surf->depth_initialized) {
2886 si_init_depth_surface(sctx, surf);
2887 }
2888
2889 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2890 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2891
2892 si_context_add_resource_size(sctx, surf->base.texture);
2893 }
2894
2895 si_update_ps_colorbuf0_slot(sctx);
2896 si_update_poly_offset_state(sctx);
2897 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2898 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2899
2900 if (sctx->screen->dpbb_allowed)
2901 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2902
2903 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2904 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2905
2906 if (sctx->screen->has_out_of_order_rast &&
2907 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2908 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2909 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2910 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2911
2912 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2913 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2914 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2915
2916 /* Set sample locations as fragment shader constants. */
2917 switch (sctx->framebuffer.nr_samples) {
2918 case 1:
2919 constbuf.user_buffer = sctx->sample_locations_1x;
2920 break;
2921 case 2:
2922 constbuf.user_buffer = sctx->sample_locations_2x;
2923 break;
2924 case 4:
2925 constbuf.user_buffer = sctx->sample_locations_4x;
2926 break;
2927 case 8:
2928 constbuf.user_buffer = sctx->sample_locations_8x;
2929 break;
2930 case 16:
2931 constbuf.user_buffer = sctx->sample_locations_16x;
2932 break;
2933 default:
2934 PRINT_ERR("Requested an invalid number of samples %i.\n",
2935 sctx->framebuffer.nr_samples);
2936 assert(0);
2937 }
2938 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2939 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2940
2941 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2942 }
2943
2944 sctx->do_update_shaders = true;
2945
2946 if (!sctx->decompression_enabled) {
2947 /* Prevent textures decompression when the framebuffer state
2948 * changes come from the decompression passes themselves.
2949 */
2950 sctx->need_check_render_feedback = true;
2951 }
2952 }
2953
2954 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2955 {
2956 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2957 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2958 unsigned i, nr_cbufs = state->nr_cbufs;
2959 struct r600_texture *tex = NULL;
2960 struct r600_surface *cb = NULL;
2961 unsigned cb_color_info = 0;
2962
2963 /* Colorbuffers. */
2964 for (i = 0; i < nr_cbufs; i++) {
2965 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2966 unsigned cb_color_attrib;
2967
2968 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2969 continue;
2970
2971 cb = (struct r600_surface*)state->cbufs[i];
2972 if (!cb) {
2973 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2974 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2975 continue;
2976 }
2977
2978 tex = (struct r600_texture *)cb->base.texture;
2979 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2980 &tex->resource, RADEON_USAGE_READWRITE,
2981 tex->resource.b.b.nr_samples > 1 ?
2982 RADEON_PRIO_COLOR_BUFFER_MSAA :
2983 RADEON_PRIO_COLOR_BUFFER);
2984
2985 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2986 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2987 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2988 RADEON_PRIO_CMASK);
2989 }
2990
2991 if (tex->dcc_separate_buffer)
2992 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2993 tex->dcc_separate_buffer,
2994 RADEON_USAGE_READWRITE,
2995 RADEON_PRIO_DCC);
2996
2997 /* Compute mutable surface parameters. */
2998 cb_color_base = tex->resource.gpu_address >> 8;
2999 cb_color_fmask = 0;
3000 cb_dcc_base = 0;
3001 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3002 cb_color_attrib = cb->cb_color_attrib;
3003
3004 if (tex->fmask.size) {
3005 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
3006 cb_color_fmask |= tex->fmask.tile_swizzle;
3007 }
3008
3009 /* Set up DCC. */
3010 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3011 bool is_msaa_resolve_dst = state->cbufs[0] &&
3012 state->cbufs[0]->texture->nr_samples > 1 &&
3013 state->cbufs[1] == &cb->base &&
3014 state->cbufs[1]->texture->nr_samples <= 1;
3015
3016 if (!is_msaa_resolve_dst)
3017 cb_color_info |= S_028C70_DCC_ENABLE(1);
3018
3019 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3020 tex->dcc_offset) >> 8;
3021 cb_dcc_base |= tex->surface.tile_swizzle;
3022 }
3023
3024 if (sctx->chip_class >= GFX9) {
3025 struct gfx9_surf_meta_flags meta;
3026
3027 if (tex->dcc_offset)
3028 meta = tex->surface.u.gfx9.dcc;
3029 else
3030 meta = tex->surface.u.gfx9.cmask;
3031
3032 /* Set mutable surface parameters. */
3033 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3034 cb_color_base |= tex->surface.tile_swizzle;
3035 if (!tex->fmask.size)
3036 cb_color_fmask = cb_color_base;
3037 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3038 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3039 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3040 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3041
3042 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3043 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3044 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3045 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3046 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3047 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3048 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3049 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3050 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3051 radeon_emit(cs, S_028C80_BASE_256B(tex->cmask.base_address_reg >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3052 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3053 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3054 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3055 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3056 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3057 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3058
3059 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3060 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3061 } else {
3062 /* Compute mutable surface parameters (SI-CI-VI). */
3063 const struct legacy_surf_level *level_info =
3064 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3065 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3066 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3067
3068 cb_color_base += level_info->offset >> 8;
3069 /* Only macrotiled modes can set tile swizzle. */
3070 if (level_info->mode == RADEON_SURF_MODE_2D)
3071 cb_color_base |= tex->surface.tile_swizzle;
3072
3073 if (!tex->fmask.size)
3074 cb_color_fmask = cb_color_base;
3075 if (cb_dcc_base)
3076 cb_dcc_base += level_info->dcc_offset >> 8;
3077
3078 pitch_tile_max = level_info->nblk_x / 8 - 1;
3079 slice_tile_max = level_info->nblk_x *
3080 level_info->nblk_y / 64 - 1;
3081 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3082
3083 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3084 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3085 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3086
3087 if (tex->fmask.size) {
3088 if (sctx->chip_class >= CIK)
3089 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3090 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3091 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3092 } else {
3093 /* This must be set for fast clear to work without FMASK. */
3094 if (sctx->chip_class >= CIK)
3095 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3096 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3097 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3098 }
3099
3100 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3101 sctx->chip_class >= VI ? 14 : 13);
3102 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3103 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3104 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3105 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3106 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3107 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3108 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3109 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3110 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3111 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3112 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3113 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3114 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3115
3116 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3117 radeon_emit(cs, cb_dcc_base);
3118 }
3119 }
3120 for (; i < 8 ; i++)
3121 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3122 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3123
3124 /* ZS buffer. */
3125 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3126 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3127 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3128
3129 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3130 &rtex->resource, RADEON_USAGE_READWRITE,
3131 zb->base.texture->nr_samples > 1 ?
3132 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3133 RADEON_PRIO_DEPTH_BUFFER);
3134
3135 if (sctx->chip_class >= GFX9) {
3136 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3137 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3138 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3139 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3140
3141 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3142 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3143 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3144 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3145 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3146 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3147 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3148 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3149 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3150 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3151 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3152 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3153
3154 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3155 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3156 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3157 } else {
3158 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3159
3160 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3161 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3162 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3163 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3164 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3165 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3166 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3167 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3168 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3169 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3170 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3171 }
3172
3173 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3174 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3175 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3176
3177 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3178 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3179 } else if (sctx->framebuffer.dirty_zsbuf) {
3180 if (sctx->chip_class >= GFX9)
3181 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3182 else
3183 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3184
3185 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3186 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3187 }
3188
3189 /* Framebuffer dimensions. */
3190 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3191 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3192 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3193
3194 if (sctx->screen->dfsm_allowed) {
3195 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3196 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3197 }
3198
3199 sctx->framebuffer.dirty_cbufs = 0;
3200 sctx->framebuffer.dirty_zsbuf = false;
3201 }
3202
3203 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3204 struct r600_atom *atom)
3205 {
3206 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3207 unsigned nr_samples = sctx->framebuffer.nr_samples;
3208 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3209
3210 /* Smoothing (only possible with nr_samples == 1) uses the same
3211 * sample locations as the MSAA it simulates.
3212 */
3213 if (nr_samples <= 1 && sctx->smoothing_enabled)
3214 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3215
3216 /* On Polaris, the small primitive filter uses the sample locations
3217 * even when MSAA is off, so we need to make sure they're set to 0.
3218 */
3219 if (has_msaa_sample_loc_bug)
3220 nr_samples = MAX2(nr_samples, 1);
3221
3222 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3223 sctx->msaa_sample_locs.nr_samples = nr_samples;
3224 si_emit_sample_locations(cs, nr_samples);
3225 }
3226
3227 if (sctx->family >= CHIP_POLARIS10) {
3228 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3229 unsigned small_prim_filter_cntl =
3230 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3231 /* line bug */
3232 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3233
3234 /* The alternative of setting sample locations to 0 would
3235 * require a DB flush to avoid Z errors, see
3236 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3237 */
3238 if (has_msaa_sample_loc_bug &&
3239 sctx->framebuffer.nr_samples > 1 &&
3240 rs && !rs->multisample_enable)
3241 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3242
3243 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3244 small_prim_filter_cntl);
3245 }
3246 }
3247
3248 static bool si_out_of_order_rasterization(struct si_context *sctx)
3249 {
3250 struct si_state_blend *blend = sctx->queued.named.blend;
3251 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3252
3253 if (!sctx->screen->has_out_of_order_rast)
3254 return false;
3255
3256 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3257
3258 if (blend) {
3259 colormask &= blend->cb_target_enabled_4bit;
3260 } else {
3261 colormask = 0;
3262 }
3263
3264 /* Conservative: No logic op. */
3265 if (colormask && blend->logicop_enable)
3266 return false;
3267
3268 struct si_dsa_order_invariance dsa_order_invariant = {
3269 .zs = true, .pass_set = true, .pass_last = false
3270 };
3271
3272 if (sctx->framebuffer.state.zsbuf) {
3273 struct r600_texture *zstex =
3274 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3275 bool has_stencil = zstex->surface.has_stencil;
3276 dsa_order_invariant = dsa->order_invariance[has_stencil];
3277 if (!dsa_order_invariant.zs)
3278 return false;
3279
3280 /* The set of PS invocations is always order invariant,
3281 * except when early Z/S tests are requested. */
3282 if (sctx->ps_shader.cso &&
3283 sctx->ps_shader.cso->info.writes_memory &&
3284 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3285 !dsa_order_invariant.pass_set)
3286 return false;
3287
3288 if (sctx->num_perfect_occlusion_queries != 0 &&
3289 !dsa_order_invariant.pass_set)
3290 return false;
3291 }
3292
3293 if (!colormask)
3294 return true;
3295
3296 unsigned blendmask = colormask & blend->blend_enable_4bit;
3297
3298 if (blendmask) {
3299 /* Only commutative blending. */
3300 if (blendmask & ~blend->commutative_4bit)
3301 return false;
3302
3303 if (!dsa_order_invariant.pass_set)
3304 return false;
3305 }
3306
3307 if (colormask & ~blendmask) {
3308 if (!dsa_order_invariant.pass_last)
3309 return false;
3310 }
3311
3312 return true;
3313 }
3314
3315 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3316 {
3317 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3318 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3319 /* 33% faster rendering to linear color buffers */
3320 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3321 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3322 unsigned sc_mode_cntl_1 =
3323 S_028A4C_WALK_SIZE(dst_is_linear) |
3324 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3325 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3326 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3327 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3328 /* always 1: */
3329 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3330 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3331 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3332 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3333 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3334 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3335
3336 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3337 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3338
3339 /* Required by OpenGL line rasterization.
3340 *
3341 * TODO: We should also enable perpendicular endcaps for AA lines,
3342 * but that requires implementing line stippling in the pixel
3343 * shader. SC can only do line stippling with axis-aligned
3344 * endcaps.
3345 */
3346 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3347
3348 if (setup_samples > 1) {
3349 /* distance from the pixel center, indexed by log2(nr_samples) */
3350 static unsigned max_dist[] = {
3351 0, /* unused */
3352 4, /* 2x MSAA */
3353 6, /* 4x MSAA */
3354 7, /* 8x MSAA */
3355 8, /* 16x MSAA */
3356 };
3357 unsigned log_samples = util_logbase2(setup_samples);
3358 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3359 unsigned log_ps_iter_samples =
3360 util_logbase2(util_next_power_of_two(ps_iter_samples));
3361
3362 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3363 radeon_emit(cs, sc_line_cntl |
3364 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3365 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3366 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3367 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3368
3369 if (sctx->framebuffer.nr_samples > 1) {
3370 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3371 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3372 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3373 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3374 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3375 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3376 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3377 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3378 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3379 sc_mode_cntl_1);
3380 } else if (sctx->smoothing_enabled) {
3381 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3382 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3383 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3384 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3385 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3386 sc_mode_cntl_1);
3387 }
3388 } else {
3389 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3390 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3391 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3392
3393 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3394 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3395 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3396 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3397 sc_mode_cntl_1);
3398 }
3399
3400 /* GFX9: Flush DFSM when the AA mode changes. */
3401 if (sctx->screen->dfsm_allowed) {
3402 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3403 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3404 }
3405 }
3406
3407 void si_update_ps_iter_samples(struct si_context *sctx)
3408 {
3409 if (sctx->framebuffer.nr_samples > 1)
3410 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3411 if (sctx->screen->dpbb_allowed)
3412 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3413 }
3414
3415 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3416 {
3417 struct si_context *sctx = (struct si_context *)ctx;
3418
3419 if (sctx->ps_iter_samples == min_samples)
3420 return;
3421
3422 sctx->ps_iter_samples = min_samples;
3423 sctx->do_update_shaders = true;
3424
3425 si_update_ps_iter_samples(sctx);
3426 }
3427
3428 /*
3429 * Samplers
3430 */
3431
3432 /**
3433 * Build the sampler view descriptor for a buffer texture.
3434 * @param state 256-bit descriptor; only the high 128 bits are filled in
3435 */
3436 void
3437 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3438 enum pipe_format format,
3439 unsigned offset, unsigned size,
3440 uint32_t *state)
3441 {
3442 const struct util_format_description *desc;
3443 int first_non_void;
3444 unsigned stride;
3445 unsigned num_records;
3446 unsigned num_format, data_format;
3447
3448 desc = util_format_description(format);
3449 first_non_void = util_format_get_first_non_void_channel(format);
3450 stride = desc->block.bits / 8;
3451 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3452 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3453
3454 num_records = size / stride;
3455 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3456
3457 /* The NUM_RECORDS field has a different meaning depending on the chip,
3458 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3459 *
3460 * SI-CIK:
3461 * - If STRIDE == 0, it's in byte units.
3462 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3463 *
3464 * VI:
3465 * - For SMEM and STRIDE == 0, it's in byte units.
3466 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3467 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3468 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3469 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3470 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3471 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3472 * That way the same descriptor can be used by both SMEM and VMEM.
3473 *
3474 * GFX9:
3475 * - For SMEM and STRIDE == 0, it's in byte units.
3476 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3477 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3478 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3479 */
3480 if (screen->info.chip_class >= GFX9)
3481 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3482 * from STRIDE to bytes. This works around it by setting
3483 * NUM_RECORDS to at least the size of one element, so that
3484 * the first element is readable when IDXEN == 0.
3485 *
3486 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3487 * IDXEN is enforced?
3488 */
3489 num_records = num_records ? MAX2(num_records, stride) : 0;
3490 else if (screen->info.chip_class == VI)
3491 num_records *= stride;
3492
3493 state[4] = 0;
3494 state[5] = S_008F04_STRIDE(stride);
3495 state[6] = num_records;
3496 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3497 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3498 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3499 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3500 S_008F0C_NUM_FORMAT(num_format) |
3501 S_008F0C_DATA_FORMAT(data_format);
3502 }
3503
3504 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3505 {
3506 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3507
3508 if (swizzle[3] == PIPE_SWIZZLE_X) {
3509 /* For the pre-defined border color values (white, opaque
3510 * black, transparent black), the only thing that matters is
3511 * that the alpha channel winds up in the correct place
3512 * (because the RGB channels are all the same) so either of
3513 * these enumerations will work.
3514 */
3515 if (swizzle[2] == PIPE_SWIZZLE_Y)
3516 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3517 else
3518 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3519 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3520 if (swizzle[1] == PIPE_SWIZZLE_Y)
3521 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3522 else
3523 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3524 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3525 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3526 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3527 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3528 }
3529
3530 return bc_swizzle;
3531 }
3532
3533 /**
3534 * Build the sampler view descriptor for a texture.
3535 */
3536 void
3537 si_make_texture_descriptor(struct si_screen *screen,
3538 struct r600_texture *tex,
3539 bool sampler,
3540 enum pipe_texture_target target,
3541 enum pipe_format pipe_format,
3542 const unsigned char state_swizzle[4],
3543 unsigned first_level, unsigned last_level,
3544 unsigned first_layer, unsigned last_layer,
3545 unsigned width, unsigned height, unsigned depth,
3546 uint32_t *state,
3547 uint32_t *fmask_state)
3548 {
3549 struct pipe_resource *res = &tex->resource.b.b;
3550 const struct util_format_description *desc;
3551 unsigned char swizzle[4];
3552 int first_non_void;
3553 unsigned num_format, data_format, type;
3554 uint64_t va;
3555
3556 desc = util_format_description(pipe_format);
3557
3558 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3559 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3560 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3561 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3562
3563 switch (pipe_format) {
3564 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3565 case PIPE_FORMAT_X32_S8X24_UINT:
3566 case PIPE_FORMAT_X8Z24_UNORM:
3567 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3568 break;
3569 case PIPE_FORMAT_X24S8_UINT:
3570 /*
3571 * X24S8 is implemented as an 8_8_8_8 data format, to
3572 * fix texture gathers. This affects at least
3573 * GL45-CTS.texture_cube_map_array.sampling on VI.
3574 */
3575 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3576 break;
3577 default:
3578 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3579 }
3580 } else {
3581 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3582 }
3583
3584 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3585
3586 switch (pipe_format) {
3587 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3588 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3589 break;
3590 default:
3591 if (first_non_void < 0) {
3592 if (util_format_is_compressed(pipe_format)) {
3593 switch (pipe_format) {
3594 case PIPE_FORMAT_DXT1_SRGB:
3595 case PIPE_FORMAT_DXT1_SRGBA:
3596 case PIPE_FORMAT_DXT3_SRGBA:
3597 case PIPE_FORMAT_DXT5_SRGBA:
3598 case PIPE_FORMAT_BPTC_SRGBA:
3599 case PIPE_FORMAT_ETC2_SRGB8:
3600 case PIPE_FORMAT_ETC2_SRGB8A1:
3601 case PIPE_FORMAT_ETC2_SRGBA8:
3602 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3603 break;
3604 case PIPE_FORMAT_RGTC1_SNORM:
3605 case PIPE_FORMAT_LATC1_SNORM:
3606 case PIPE_FORMAT_RGTC2_SNORM:
3607 case PIPE_FORMAT_LATC2_SNORM:
3608 case PIPE_FORMAT_ETC2_R11_SNORM:
3609 case PIPE_FORMAT_ETC2_RG11_SNORM:
3610 /* implies float, so use SNORM/UNORM to determine
3611 whether data is signed or not */
3612 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3613 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3614 break;
3615 default:
3616 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3617 break;
3618 }
3619 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3620 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3621 } else {
3622 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3623 }
3624 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3625 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3626 } else {
3627 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3628
3629 switch (desc->channel[first_non_void].type) {
3630 case UTIL_FORMAT_TYPE_FLOAT:
3631 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3632 break;
3633 case UTIL_FORMAT_TYPE_SIGNED:
3634 if (desc->channel[first_non_void].normalized)
3635 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3636 else if (desc->channel[first_non_void].pure_integer)
3637 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3638 else
3639 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3640 break;
3641 case UTIL_FORMAT_TYPE_UNSIGNED:
3642 if (desc->channel[first_non_void].normalized)
3643 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3644 else if (desc->channel[first_non_void].pure_integer)
3645 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3646 else
3647 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3648 }
3649 }
3650 }
3651
3652 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3653 if (data_format == ~0) {
3654 data_format = 0;
3655 }
3656
3657 /* S8 with Z32 HTILE needs a special format. */
3658 if (screen->info.chip_class >= GFX9 &&
3659 pipe_format == PIPE_FORMAT_S8_UINT &&
3660 tex->tc_compatible_htile)
3661 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3662
3663 if (!sampler &&
3664 (res->target == PIPE_TEXTURE_CUBE ||
3665 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3666 (screen->info.chip_class <= VI &&
3667 res->target == PIPE_TEXTURE_3D))) {
3668 /* For the purpose of shader images, treat cube maps and 3D
3669 * textures as 2D arrays. For 3D textures, the address
3670 * calculations for mipmaps are different, so we rely on the
3671 * caller to effectively disable mipmaps.
3672 */
3673 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3674
3675 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3676 } else {
3677 type = si_tex_dim(screen, tex, target, res->nr_samples);
3678 }
3679
3680 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3681 height = 1;
3682 depth = res->array_size;
3683 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3684 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3685 if (sampler || res->target != PIPE_TEXTURE_3D)
3686 depth = res->array_size;
3687 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3688 depth = res->array_size / 6;
3689
3690 state[0] = 0;
3691 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3692 S_008F14_NUM_FORMAT_GFX6(num_format));
3693 state[2] = (S_008F18_WIDTH(width - 1) |
3694 S_008F18_HEIGHT(height - 1) |
3695 S_008F18_PERF_MOD(4));
3696 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3697 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3698 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3699 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3700 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3701 0 : first_level) |
3702 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3703 util_logbase2(res->nr_samples) :
3704 last_level) |
3705 S_008F1C_TYPE(type));
3706 state[4] = 0;
3707 state[5] = S_008F24_BASE_ARRAY(first_layer);
3708 state[6] = 0;
3709 state[7] = 0;
3710
3711 if (screen->info.chip_class >= GFX9) {
3712 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3713
3714 /* Depth is the the last accessible layer on Gfx9.
3715 * The hw doesn't need to know the total number of layers.
3716 */
3717 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3718 state[4] |= S_008F20_DEPTH(depth - 1);
3719 else
3720 state[4] |= S_008F20_DEPTH(last_layer);
3721
3722 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3723 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3724 util_logbase2(res->nr_samples) :
3725 tex->resource.b.b.last_level);
3726 } else {
3727 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3728 state[4] |= S_008F20_DEPTH(depth - 1);
3729 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3730 }
3731
3732 if (tex->dcc_offset) {
3733 unsigned swap = si_translate_colorswap(pipe_format, false);
3734
3735 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3736 } else {
3737 /* The last dword is unused by hw. The shader uses it to clear
3738 * bits in the first dword of sampler state.
3739 */
3740 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3741 if (first_level == last_level)
3742 state[7] = C_008F30_MAX_ANISO_RATIO;
3743 else
3744 state[7] = 0xffffffff;
3745 }
3746 }
3747
3748 /* Initialize the sampler view for FMASK. */
3749 if (tex->fmask.size) {
3750 uint32_t data_format, num_format;
3751
3752 va = tex->resource.gpu_address + tex->fmask.offset;
3753
3754 if (screen->info.chip_class >= GFX9) {
3755 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3756 switch (res->nr_samples) {
3757 case 2:
3758 num_format = V_008F14_IMG_FMASK_8_2_2;
3759 break;
3760 case 4:
3761 num_format = V_008F14_IMG_FMASK_8_4_4;
3762 break;
3763 case 8:
3764 num_format = V_008F14_IMG_FMASK_32_8_8;
3765 break;
3766 default:
3767 unreachable("invalid nr_samples");
3768 }
3769 } else {
3770 switch (res->nr_samples) {
3771 case 2:
3772 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3773 break;
3774 case 4:
3775 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3776 break;
3777 case 8:
3778 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3779 break;
3780 default:
3781 unreachable("invalid nr_samples");
3782 }
3783 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3784 }
3785
3786 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3787 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3788 S_008F14_DATA_FORMAT_GFX6(data_format) |
3789 S_008F14_NUM_FORMAT_GFX6(num_format);
3790 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3791 S_008F18_HEIGHT(height - 1);
3792 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3793 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3794 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3795 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3796 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3797 fmask_state[4] = 0;
3798 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3799 fmask_state[6] = 0;
3800 fmask_state[7] = 0;
3801
3802 if (screen->info.chip_class >= GFX9) {
3803 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3804 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3805 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3806 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3807 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3808 } else {
3809 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3810 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3811 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3812 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3813 }
3814 }
3815 }
3816
3817 /**
3818 * Create a sampler view.
3819 *
3820 * @param ctx context
3821 * @param texture texture
3822 * @param state sampler view template
3823 * @param width0 width0 override (for compressed textures as int)
3824 * @param height0 height0 override (for compressed textures as int)
3825 * @param force_level set the base address to the level (for compressed textures)
3826 */
3827 struct pipe_sampler_view *
3828 si_create_sampler_view_custom(struct pipe_context *ctx,
3829 struct pipe_resource *texture,
3830 const struct pipe_sampler_view *state,
3831 unsigned width0, unsigned height0,
3832 unsigned force_level)
3833 {
3834 struct si_context *sctx = (struct si_context*)ctx;
3835 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3836 struct r600_texture *tmp = (struct r600_texture*)texture;
3837 unsigned base_level, first_level, last_level;
3838 unsigned char state_swizzle[4];
3839 unsigned height, depth, width;
3840 unsigned last_layer = state->u.tex.last_layer;
3841 enum pipe_format pipe_format;
3842 const struct legacy_surf_level *surflevel;
3843
3844 if (!view)
3845 return NULL;
3846
3847 /* initialize base object */
3848 view->base = *state;
3849 view->base.texture = NULL;
3850 view->base.reference.count = 1;
3851 view->base.context = ctx;
3852
3853 assert(texture);
3854 pipe_resource_reference(&view->base.texture, texture);
3855
3856 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3857 state->format == PIPE_FORMAT_S8X24_UINT ||
3858 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3859 state->format == PIPE_FORMAT_S8_UINT)
3860 view->is_stencil_sampler = true;
3861
3862 /* Buffer resource. */
3863 if (texture->target == PIPE_BUFFER) {
3864 si_make_buffer_descriptor(sctx->screen,
3865 (struct r600_resource *)texture,
3866 state->format,
3867 state->u.buf.offset,
3868 state->u.buf.size,
3869 view->state);
3870 return &view->base;
3871 }
3872
3873 state_swizzle[0] = state->swizzle_r;
3874 state_swizzle[1] = state->swizzle_g;
3875 state_swizzle[2] = state->swizzle_b;
3876 state_swizzle[3] = state->swizzle_a;
3877
3878 base_level = 0;
3879 first_level = state->u.tex.first_level;
3880 last_level = state->u.tex.last_level;
3881 width = width0;
3882 height = height0;
3883 depth = texture->depth0;
3884
3885 if (sctx->chip_class <= VI && force_level) {
3886 assert(force_level == first_level &&
3887 force_level == last_level);
3888 base_level = force_level;
3889 first_level = 0;
3890 last_level = 0;
3891 width = u_minify(width, force_level);
3892 height = u_minify(height, force_level);
3893 depth = u_minify(depth, force_level);
3894 }
3895
3896 /* This is not needed if state trackers set last_layer correctly. */
3897 if (state->target == PIPE_TEXTURE_1D ||
3898 state->target == PIPE_TEXTURE_2D ||
3899 state->target == PIPE_TEXTURE_RECT ||
3900 state->target == PIPE_TEXTURE_CUBE)
3901 last_layer = state->u.tex.first_layer;
3902
3903 /* Texturing with separate depth and stencil. */
3904 pipe_format = state->format;
3905
3906 /* Depth/stencil texturing sometimes needs separate texture. */
3907 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
3908 if (!tmp->flushed_depth_texture &&
3909 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3910 pipe_resource_reference(&view->base.texture, NULL);
3911 FREE(view);
3912 return NULL;
3913 }
3914
3915 assert(tmp->flushed_depth_texture);
3916
3917 /* Override format for the case where the flushed texture
3918 * contains only Z or only S.
3919 */
3920 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3921 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3922
3923 tmp = tmp->flushed_depth_texture;
3924 }
3925
3926 surflevel = tmp->surface.u.legacy.level;
3927
3928 if (tmp->db_compatible) {
3929 if (!view->is_stencil_sampler)
3930 pipe_format = tmp->db_render_format;
3931
3932 switch (pipe_format) {
3933 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3934 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3935 break;
3936 case PIPE_FORMAT_X8Z24_UNORM:
3937 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3938 /* Z24 is always stored like this for DB
3939 * compatibility.
3940 */
3941 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3942 break;
3943 case PIPE_FORMAT_X24S8_UINT:
3944 case PIPE_FORMAT_S8X24_UINT:
3945 case PIPE_FORMAT_X32_S8X24_UINT:
3946 pipe_format = PIPE_FORMAT_S8_UINT;
3947 surflevel = tmp->surface.u.legacy.stencil_level;
3948 break;
3949 default:;
3950 }
3951 }
3952
3953 view->dcc_incompatible =
3954 vi_dcc_formats_are_incompatible(texture,
3955 state->u.tex.first_level,
3956 state->format);
3957
3958 si_make_texture_descriptor(sctx->screen, tmp, true,
3959 state->target, pipe_format, state_swizzle,
3960 first_level, last_level,
3961 state->u.tex.first_layer, last_layer,
3962 width, height, depth,
3963 view->state, view->fmask_state);
3964
3965 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3966 view->is_integer =
3967 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3968 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3969 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3970 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3971 view->base_level_info = &surflevel[base_level];
3972 view->base_level = base_level;
3973 view->block_width = util_format_get_blockwidth(pipe_format);
3974 return &view->base;
3975 }
3976
3977 static struct pipe_sampler_view *
3978 si_create_sampler_view(struct pipe_context *ctx,
3979 struct pipe_resource *texture,
3980 const struct pipe_sampler_view *state)
3981 {
3982 return si_create_sampler_view_custom(ctx, texture, state,
3983 texture ? texture->width0 : 0,
3984 texture ? texture->height0 : 0, 0);
3985 }
3986
3987 static void si_sampler_view_destroy(struct pipe_context *ctx,
3988 struct pipe_sampler_view *state)
3989 {
3990 struct si_sampler_view *view = (struct si_sampler_view *)state;
3991
3992 pipe_resource_reference(&state->texture, NULL);
3993 FREE(view);
3994 }
3995
3996 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3997 {
3998 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3999 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4000 (linear_filter &&
4001 (wrap == PIPE_TEX_WRAP_CLAMP ||
4002 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4003 }
4004
4005 static uint32_t si_translate_border_color(struct si_context *sctx,
4006 const struct pipe_sampler_state *state,
4007 const union pipe_color_union *color,
4008 bool is_integer)
4009 {
4010 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4011 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4012
4013 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4014 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4015 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4016 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4017
4018 #define simple_border_types(elt) \
4019 do { \
4020 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4021 color->elt[2] == 0 && color->elt[3] == 0) \
4022 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4023 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4024 color->elt[2] == 0 && color->elt[3] == 1) \
4025 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4026 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4027 color->elt[2] == 1 && color->elt[3] == 1) \
4028 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4029 } while (false)
4030
4031 if (is_integer)
4032 simple_border_types(ui);
4033 else
4034 simple_border_types(f);
4035
4036 #undef simple_border_types
4037
4038 int i;
4039
4040 /* Check if the border has been uploaded already. */
4041 for (i = 0; i < sctx->border_color_count; i++)
4042 if (memcmp(&sctx->border_color_table[i], color,
4043 sizeof(*color)) == 0)
4044 break;
4045
4046 if (i >= SI_MAX_BORDER_COLORS) {
4047 /* Getting 4096 unique border colors is very unlikely. */
4048 fprintf(stderr, "radeonsi: The border color table is full. "
4049 "Any new border colors will be just black. "
4050 "Please file a bug.\n");
4051 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4052 }
4053
4054 if (i == sctx->border_color_count) {
4055 /* Upload a new border color. */
4056 memcpy(&sctx->border_color_table[i], color,
4057 sizeof(*color));
4058 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4059 color, sizeof(*color));
4060 sctx->border_color_count++;
4061 }
4062
4063 return S_008F3C_BORDER_COLOR_PTR(i) |
4064 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4065 }
4066
4067 static inline int S_FIXED(float value, unsigned frac_bits)
4068 {
4069 return value * (1 << frac_bits);
4070 }
4071
4072 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4073 {
4074 if (filter == PIPE_TEX_FILTER_LINEAR)
4075 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4076 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4077 else
4078 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4079 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4080 }
4081
4082 static inline unsigned si_tex_aniso_filter(unsigned filter)
4083 {
4084 if (filter < 2)
4085 return 0;
4086 if (filter < 4)
4087 return 1;
4088 if (filter < 8)
4089 return 2;
4090 if (filter < 16)
4091 return 3;
4092 return 4;
4093 }
4094
4095 static void *si_create_sampler_state(struct pipe_context *ctx,
4096 const struct pipe_sampler_state *state)
4097 {
4098 struct si_context *sctx = (struct si_context *)ctx;
4099 struct si_screen *sscreen = sctx->screen;
4100 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4101 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4102 : state->max_anisotropy;
4103 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4104 union pipe_color_union clamped_border_color;
4105
4106 if (!rstate) {
4107 return NULL;
4108 }
4109
4110 #ifdef DEBUG
4111 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4112 #endif
4113 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4114 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4115 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4116 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4117 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4118 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4119 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4120 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4121 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4122 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4123 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4124 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4125 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4126 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4127 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4128 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4129 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4130 S_008F38_MIP_POINT_PRECLAMP(0) |
4131 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4132 S_008F38_FILTER_PREC_FIX(1) |
4133 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4134 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4135
4136 /* Create sampler resource for integer textures. */
4137 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4138 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4139
4140 /* Create sampler resource for upgraded depth textures. */
4141 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4142
4143 for (unsigned i = 0; i < 4; ++i) {
4144 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4145 * when the border color is 1.0. */
4146 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4147 }
4148
4149 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4150 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4151 else
4152 rstate->upgraded_depth_val[3] =
4153 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4154 S_008F3C_UPGRADED_DEPTH(1);
4155
4156 return rstate;
4157 }
4158
4159 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4160 {
4161 struct si_context *sctx = (struct si_context *)ctx;
4162
4163 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4164 return;
4165
4166 sctx->sample_mask.sample_mask = sample_mask;
4167 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4168 }
4169
4170 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4171 {
4172 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4173 unsigned mask = sctx->sample_mask.sample_mask;
4174
4175 /* Needed for line and polygon smoothing as well as for the Polaris
4176 * small primitive filter. We expect the state tracker to take care of
4177 * this for us.
4178 */
4179 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4180 (mask & 1 && sctx->blitter->running));
4181
4182 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4183 radeon_emit(cs, mask | (mask << 16));
4184 radeon_emit(cs, mask | (mask << 16));
4185 }
4186
4187 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4188 {
4189 #ifdef DEBUG
4190 struct si_sampler_state *s = state;
4191
4192 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4193 s->magic = 0;
4194 #endif
4195 free(state);
4196 }
4197
4198 /*
4199 * Vertex elements & buffers
4200 */
4201
4202 static void *si_create_vertex_elements(struct pipe_context *ctx,
4203 unsigned count,
4204 const struct pipe_vertex_element *elements)
4205 {
4206 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4207 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4208 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4209 int i;
4210
4211 assert(count <= SI_MAX_ATTRIBS);
4212 if (!v)
4213 return NULL;
4214
4215 v->count = count;
4216 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4217
4218 for (i = 0; i < count; ++i) {
4219 const struct util_format_description *desc;
4220 const struct util_format_channel_description *channel;
4221 unsigned data_format, num_format;
4222 int first_non_void;
4223 unsigned vbo_index = elements[i].vertex_buffer_index;
4224 unsigned char swizzle[4];
4225
4226 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4227 FREE(v);
4228 return NULL;
4229 }
4230
4231 if (elements[i].instance_divisor) {
4232 v->uses_instance_divisors = true;
4233 v->instance_divisors[i] = elements[i].instance_divisor;
4234
4235 if (v->instance_divisors[i] == 1)
4236 v->instance_divisor_is_one |= 1u << i;
4237 else
4238 v->instance_divisor_is_fetched |= 1u << i;
4239 }
4240
4241 if (!used[vbo_index]) {
4242 v->first_vb_use_mask |= 1 << i;
4243 used[vbo_index] = true;
4244 }
4245
4246 desc = util_format_description(elements[i].src_format);
4247 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4248 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4249 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4250 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4251 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4252
4253 v->format_size[i] = desc->block.bits / 8;
4254 v->src_offset[i] = elements[i].src_offset;
4255 v->vertex_buffer_index[i] = vbo_index;
4256
4257 /* The hardware always treats the 2-bit alpha channel as
4258 * unsigned, so a shader workaround is needed. The affected
4259 * chips are VI and older except Stoney (GFX8.1).
4260 */
4261 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4262 sscreen->info.chip_class <= VI &&
4263 sscreen->info.family != CHIP_STONEY) {
4264 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4265 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4266 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4267 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4268 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4269 /* This isn't actually used in OpenGL. */
4270 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4271 }
4272 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4273 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4274 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4275 else
4276 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4277 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4278 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4279 if (channel->normalized) {
4280 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4281 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4282 else
4283 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4284 } else {
4285 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4286 }
4287 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4288 if (channel->normalized) {
4289 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4290 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4291 else
4292 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4293 } else {
4294 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4295 }
4296 }
4297 } else if (channel && channel->size == 64 &&
4298 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4299 switch (desc->nr_channels) {
4300 case 1:
4301 case 2:
4302 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4303 swizzle[0] = PIPE_SWIZZLE_X;
4304 swizzle[1] = PIPE_SWIZZLE_Y;
4305 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4306 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4307 break;
4308 case 3:
4309 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4310 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4311 swizzle[1] = PIPE_SWIZZLE_Y;
4312 swizzle[2] = PIPE_SWIZZLE_0;
4313 swizzle[3] = PIPE_SWIZZLE_0;
4314 break;
4315 case 4:
4316 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4317 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4318 swizzle[1] = PIPE_SWIZZLE_Y;
4319 swizzle[2] = PIPE_SWIZZLE_Z;
4320 swizzle[3] = PIPE_SWIZZLE_W;
4321 break;
4322 default:
4323 assert(0);
4324 }
4325 } else if (channel && desc->nr_channels == 3) {
4326 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4327
4328 if (channel->size == 8) {
4329 if (channel->pure_integer)
4330 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4331 else
4332 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4333 } else if (channel->size == 16) {
4334 if (channel->pure_integer)
4335 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4336 else
4337 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4338 }
4339 }
4340
4341 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4342 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4343 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4344 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4345 S_008F0C_NUM_FORMAT(num_format) |
4346 S_008F0C_DATA_FORMAT(data_format);
4347 }
4348 return v;
4349 }
4350
4351 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4352 {
4353 struct si_context *sctx = (struct si_context *)ctx;
4354 struct si_vertex_elements *old = sctx->vertex_elements;
4355 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4356
4357 sctx->vertex_elements = v;
4358 sctx->vertex_buffers_dirty = true;
4359
4360 if (v &&
4361 (!old ||
4362 old->count != v->count ||
4363 old->uses_instance_divisors != v->uses_instance_divisors ||
4364 v->uses_instance_divisors || /* we don't check which divisors changed */
4365 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4366 sctx->do_update_shaders = true;
4367
4368 if (v && v->instance_divisor_is_fetched) {
4369 struct pipe_constant_buffer cb;
4370
4371 cb.buffer = NULL;
4372 cb.user_buffer = v->instance_divisors;
4373 cb.buffer_offset = 0;
4374 cb.buffer_size = sizeof(uint32_t) * v->count;
4375 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4376 }
4377 }
4378
4379 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4380 {
4381 struct si_context *sctx = (struct si_context *)ctx;
4382
4383 if (sctx->vertex_elements == state)
4384 sctx->vertex_elements = NULL;
4385 FREE(state);
4386 }
4387
4388 static void si_set_vertex_buffers(struct pipe_context *ctx,
4389 unsigned start_slot, unsigned count,
4390 const struct pipe_vertex_buffer *buffers)
4391 {
4392 struct si_context *sctx = (struct si_context *)ctx;
4393 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4394 int i;
4395
4396 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4397
4398 if (buffers) {
4399 for (i = 0; i < count; i++) {
4400 const struct pipe_vertex_buffer *src = buffers + i;
4401 struct pipe_vertex_buffer *dsti = dst + i;
4402 struct pipe_resource *buf = src->buffer.resource;
4403
4404 pipe_resource_reference(&dsti->buffer.resource, buf);
4405 dsti->buffer_offset = src->buffer_offset;
4406 dsti->stride = src->stride;
4407 si_context_add_resource_size(sctx, buf);
4408 if (buf)
4409 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4410 }
4411 } else {
4412 for (i = 0; i < count; i++) {
4413 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4414 }
4415 }
4416 sctx->vertex_buffers_dirty = true;
4417 }
4418
4419 /*
4420 * Misc
4421 */
4422
4423 static void si_set_tess_state(struct pipe_context *ctx,
4424 const float default_outer_level[4],
4425 const float default_inner_level[2])
4426 {
4427 struct si_context *sctx = (struct si_context *)ctx;
4428 struct pipe_constant_buffer cb;
4429 float array[8];
4430
4431 memcpy(array, default_outer_level, sizeof(float) * 4);
4432 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4433
4434 cb.buffer = NULL;
4435 cb.user_buffer = NULL;
4436 cb.buffer_size = sizeof(array);
4437
4438 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4439 (void*)array, sizeof(array),
4440 &cb.buffer_offset);
4441
4442 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4443 pipe_resource_reference(&cb.buffer, NULL);
4444 }
4445
4446 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4447 {
4448 struct si_context *sctx = (struct si_context *)ctx;
4449
4450 si_update_fb_dirtiness_after_rendering(sctx);
4451
4452 /* Multisample surfaces are flushed in si_decompress_textures. */
4453 if (sctx->framebuffer.uncompressed_cb_mask)
4454 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4455 sctx->framebuffer.CB_has_shader_readable_metadata);
4456 }
4457
4458 /* This only ensures coherency for shader image/buffer stores. */
4459 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4460 {
4461 struct si_context *sctx = (struct si_context *)ctx;
4462
4463 /* Subsequent commands must wait for all shader invocations to
4464 * complete. */
4465 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4466 SI_CONTEXT_CS_PARTIAL_FLUSH;
4467
4468 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4469 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4470 SI_CONTEXT_INV_VMEM_L1;
4471
4472 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4473 PIPE_BARRIER_SHADER_BUFFER |
4474 PIPE_BARRIER_TEXTURE |
4475 PIPE_BARRIER_IMAGE |
4476 PIPE_BARRIER_STREAMOUT_BUFFER |
4477 PIPE_BARRIER_GLOBAL_BUFFER)) {
4478 /* As far as I can tell, L1 contents are written back to L2
4479 * automatically at end of shader, but the contents of other
4480 * L1 caches might still be stale. */
4481 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4482 }
4483
4484 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4485 /* Indices are read through TC L2 since VI.
4486 * L1 isn't used.
4487 */
4488 if (sctx->screen->info.chip_class <= CIK)
4489 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4490 }
4491
4492 /* MSAA color, any depth and any stencil are flushed in
4493 * si_decompress_textures when needed.
4494 */
4495 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4496 sctx->framebuffer.uncompressed_cb_mask) {
4497 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4498
4499 if (sctx->chip_class <= VI)
4500 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4501 }
4502
4503 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4504 if (sctx->screen->info.chip_class <= VI &&
4505 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4506 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4507 }
4508
4509 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4510 {
4511 struct pipe_blend_state blend;
4512
4513 memset(&blend, 0, sizeof(blend));
4514 blend.independent_blend_enable = true;
4515 blend.rt[0].colormask = 0xf;
4516 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4517 }
4518
4519 static void si_init_config(struct si_context *sctx);
4520
4521 void si_init_state_functions(struct si_context *sctx)
4522 {
4523 si_init_external_atom(sctx, &sctx->render_cond_atom, &sctx->atoms.s.render_cond);
4524 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4525 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4526 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4527 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4528
4529 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4530 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4531 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4532 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4533 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4534 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4535 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4536 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4537 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4538 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4539 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4540
4541 sctx->b.create_blend_state = si_create_blend_state;
4542 sctx->b.bind_blend_state = si_bind_blend_state;
4543 sctx->b.delete_blend_state = si_delete_blend_state;
4544 sctx->b.set_blend_color = si_set_blend_color;
4545
4546 sctx->b.create_rasterizer_state = si_create_rs_state;
4547 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4548 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4549
4550 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4551 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4552 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4553
4554 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4555 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4556 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4557 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4558 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4559
4560 sctx->b.set_clip_state = si_set_clip_state;
4561 sctx->b.set_stencil_ref = si_set_stencil_ref;
4562
4563 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4564
4565 sctx->b.create_sampler_state = si_create_sampler_state;
4566 sctx->b.delete_sampler_state = si_delete_sampler_state;
4567
4568 sctx->b.create_sampler_view = si_create_sampler_view;
4569 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4570
4571 sctx->b.set_sample_mask = si_set_sample_mask;
4572
4573 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4574 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4575 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4576 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4577
4578 sctx->b.texture_barrier = si_texture_barrier;
4579 sctx->b.memory_barrier = si_memory_barrier;
4580 sctx->b.set_min_samples = si_set_min_samples;
4581 sctx->b.set_tess_state = si_set_tess_state;
4582
4583 sctx->b.set_active_query_state = si_set_active_query_state;
4584
4585 sctx->b.draw_vbo = si_draw_vbo;
4586
4587 si_init_config(sctx);
4588 }
4589
4590 void si_init_screen_state_functions(struct si_screen *sscreen)
4591 {
4592 sscreen->b.is_format_supported = si_is_format_supported;
4593 }
4594
4595 static void si_set_grbm_gfx_index(struct si_context *sctx,
4596 struct si_pm4_state *pm4, unsigned value)
4597 {
4598 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4599 R_00802C_GRBM_GFX_INDEX;
4600 si_pm4_set_reg(pm4, reg, value);
4601 }
4602
4603 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4604 struct si_pm4_state *pm4, unsigned se)
4605 {
4606 assert(se == ~0 || se < sctx->screen->info.max_se);
4607 si_set_grbm_gfx_index(sctx, pm4,
4608 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4609 S_030800_SE_INDEX(se)) |
4610 S_030800_SH_BROADCAST_WRITES(1) |
4611 S_030800_INSTANCE_BROADCAST_WRITES(1));
4612 }
4613
4614 static void
4615 si_write_harvested_raster_configs(struct si_context *sctx,
4616 struct si_pm4_state *pm4,
4617 unsigned raster_config,
4618 unsigned raster_config_1)
4619 {
4620 unsigned sh_per_se = MAX2(sctx->screen->info.max_sh_per_se, 1);
4621 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4622 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4623 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4624 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4625 unsigned rb_per_se = num_rb / num_se;
4626 unsigned se_mask[4];
4627 unsigned se;
4628
4629 se_mask[0] = ((1 << rb_per_se) - 1);
4630 se_mask[1] = (se_mask[0] << rb_per_se);
4631 se_mask[2] = (se_mask[1] << rb_per_se);
4632 se_mask[3] = (se_mask[2] << rb_per_se);
4633
4634 se_mask[0] &= rb_mask;
4635 se_mask[1] &= rb_mask;
4636 se_mask[2] &= rb_mask;
4637 se_mask[3] &= rb_mask;
4638
4639 assert(num_se == 1 || num_se == 2 || num_se == 4);
4640 assert(sh_per_se == 1 || sh_per_se == 2);
4641 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4642
4643 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4644 * fields are for, so I'm leaving them as their default
4645 * values. */
4646
4647 for (se = 0; se < num_se; se++) {
4648 unsigned raster_config_se = raster_config;
4649 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4650 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4651 int idx = (se / 2) * 2;
4652
4653 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4654 raster_config_se &= C_028350_SE_MAP;
4655
4656 if (!se_mask[idx]) {
4657 raster_config_se |=
4658 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4659 } else {
4660 raster_config_se |=
4661 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4662 }
4663 }
4664
4665 pkr0_mask &= rb_mask;
4666 pkr1_mask &= rb_mask;
4667 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4668 raster_config_se &= C_028350_PKR_MAP;
4669
4670 if (!pkr0_mask) {
4671 raster_config_se |=
4672 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4673 } else {
4674 raster_config_se |=
4675 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4676 }
4677 }
4678
4679 if (rb_per_se >= 2) {
4680 unsigned rb0_mask = 1 << (se * rb_per_se);
4681 unsigned rb1_mask = rb0_mask << 1;
4682
4683 rb0_mask &= rb_mask;
4684 rb1_mask &= rb_mask;
4685 if (!rb0_mask || !rb1_mask) {
4686 raster_config_se &= C_028350_RB_MAP_PKR0;
4687
4688 if (!rb0_mask) {
4689 raster_config_se |=
4690 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4691 } else {
4692 raster_config_se |=
4693 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4694 }
4695 }
4696
4697 if (rb_per_se > 2) {
4698 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4699 rb1_mask = rb0_mask << 1;
4700 rb0_mask &= rb_mask;
4701 rb1_mask &= rb_mask;
4702 if (!rb0_mask || !rb1_mask) {
4703 raster_config_se &= C_028350_RB_MAP_PKR1;
4704
4705 if (!rb0_mask) {
4706 raster_config_se |=
4707 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4708 } else {
4709 raster_config_se |=
4710 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4711 }
4712 }
4713 }
4714 }
4715
4716 si_set_grbm_gfx_index_se(sctx, pm4, se);
4717 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4718 }
4719 si_set_grbm_gfx_index(sctx, pm4, ~0);
4720
4721 if (sctx->chip_class >= CIK) {
4722 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4723 (!se_mask[2] && !se_mask[3]))) {
4724 raster_config_1 &= C_028354_SE_PAIR_MAP;
4725
4726 if (!se_mask[0] && !se_mask[1]) {
4727 raster_config_1 |=
4728 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4729 } else {
4730 raster_config_1 |=
4731 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4732 }
4733 }
4734
4735 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4736 }
4737 }
4738
4739 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4740 {
4741 struct si_screen *sscreen = sctx->screen;
4742 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4743 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4744 unsigned raster_config, raster_config_1;
4745
4746 switch (sctx->family) {
4747 case CHIP_TAHITI:
4748 case CHIP_PITCAIRN:
4749 raster_config = 0x2a00126a;
4750 raster_config_1 = 0x00000000;
4751 break;
4752 case CHIP_VERDE:
4753 raster_config = 0x0000124a;
4754 raster_config_1 = 0x00000000;
4755 break;
4756 case CHIP_OLAND:
4757 raster_config = 0x00000082;
4758 raster_config_1 = 0x00000000;
4759 break;
4760 case CHIP_HAINAN:
4761 raster_config = 0x00000000;
4762 raster_config_1 = 0x00000000;
4763 break;
4764 case CHIP_BONAIRE:
4765 raster_config = 0x16000012;
4766 raster_config_1 = 0x00000000;
4767 break;
4768 case CHIP_HAWAII:
4769 raster_config = 0x3a00161a;
4770 raster_config_1 = 0x0000002e;
4771 break;
4772 case CHIP_FIJI:
4773 if (sscreen->info.cik_macrotile_mode_array[0] == 0x000000e8) {
4774 /* old kernels with old tiling config */
4775 raster_config = 0x16000012;
4776 raster_config_1 = 0x0000002a;
4777 } else {
4778 raster_config = 0x3a00161a;
4779 raster_config_1 = 0x0000002e;
4780 }
4781 break;
4782 case CHIP_POLARIS10:
4783 raster_config = 0x16000012;
4784 raster_config_1 = 0x0000002a;
4785 break;
4786 case CHIP_POLARIS11:
4787 case CHIP_POLARIS12:
4788 raster_config = 0x16000012;
4789 raster_config_1 = 0x00000000;
4790 break;
4791 case CHIP_TONGA:
4792 raster_config = 0x16000012;
4793 raster_config_1 = 0x0000002a;
4794 break;
4795 case CHIP_ICELAND:
4796 if (num_rb == 1)
4797 raster_config = 0x00000000;
4798 else
4799 raster_config = 0x00000002;
4800 raster_config_1 = 0x00000000;
4801 break;
4802 case CHIP_CARRIZO:
4803 raster_config = 0x00000002;
4804 raster_config_1 = 0x00000000;
4805 break;
4806 case CHIP_KAVERI:
4807 /* KV should be 0x00000002, but that causes problems with radeon */
4808 raster_config = 0x00000000; /* 0x00000002 */
4809 raster_config_1 = 0x00000000;
4810 break;
4811 case CHIP_KABINI:
4812 case CHIP_MULLINS:
4813 case CHIP_STONEY:
4814 raster_config = 0x00000000;
4815 raster_config_1 = 0x00000000;
4816 break;
4817 default:
4818 fprintf(stderr,
4819 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4820 raster_config = 0x00000000;
4821 raster_config_1 = 0x00000000;
4822 }
4823
4824 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4825 /* Always use the default config when all backends are enabled
4826 * (or when we failed to determine the enabled backends).
4827 */
4828 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4829 raster_config);
4830 if (sctx->chip_class >= CIK)
4831 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4832 raster_config_1);
4833 } else {
4834 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4835 }
4836 }
4837
4838 static void si_init_config(struct si_context *sctx)
4839 {
4840 struct si_screen *sscreen = sctx->screen;
4841 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4842 bool has_clear_state = sscreen->has_clear_state;
4843 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4844
4845 /* Only SI can disable CLEAR_STATE for now. */
4846 assert(has_clear_state || sscreen->info.chip_class == SI);
4847
4848 if (!pm4)
4849 return;
4850
4851 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4852 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4853 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4854 si_pm4_cmd_end(pm4, false);
4855
4856 if (has_clear_state) {
4857 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4858 si_pm4_cmd_add(pm4, 0);
4859 si_pm4_cmd_end(pm4, false);
4860 }
4861
4862 if (sctx->chip_class <= VI)
4863 si_set_raster_config(sctx, pm4);
4864
4865 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4866 if (!has_clear_state)
4867 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4868
4869 /* FIXME calculate these values somehow ??? */
4870 if (sctx->chip_class <= VI) {
4871 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4872 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4873 }
4874
4875 if (!has_clear_state) {
4876 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4877 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4878 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4879 }
4880
4881 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4882 if (!has_clear_state)
4883 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4884 if (sctx->chip_class < CIK)
4885 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4886 S_008A14_CLIP_VTX_REORDER_ENA(1));
4887
4888 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4889 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4890
4891 if (!has_clear_state)
4892 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4893
4894 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4895 * I don't know why. Deduced by trial and error.
4896 */
4897 if (sctx->chip_class <= CIK) {
4898 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4899 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4900 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4901 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4902 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4903 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4904 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4905 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4906 }
4907
4908 if (!has_clear_state) {
4909 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4910 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4911 S_028230_ER_TRI(0xA) |
4912 S_028230_ER_POINT(0xA) |
4913 S_028230_ER_RECT(0xA) |
4914 /* Required by DX10_DIAMOND_TEST_ENA: */
4915 S_028230_ER_LINE_LR(0x1A) |
4916 S_028230_ER_LINE_RL(0x26) |
4917 S_028230_ER_LINE_TB(0xA) |
4918 S_028230_ER_LINE_BT(0xA));
4919 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4920 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4921 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4922 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4923 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4924 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4925 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4926 }
4927
4928 if (sctx->chip_class >= GFX9) {
4929 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4930 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4931 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4932 } else {
4933 /* These registers, when written, also overwrite the CLEAR_STATE
4934 * context, so we can't rely on CLEAR_STATE setting them.
4935 * It would be an issue if there was another UMD changing them.
4936 */
4937 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4938 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4939 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4940 }
4941
4942 if (sctx->chip_class >= CIK) {
4943 if (sctx->chip_class >= GFX9) {
4944 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4945 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4946 } else {
4947 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4948 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4949 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4950 S_00B41C_WAVE_LIMIT(0x3F));
4951 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4952 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4953
4954 /* If this is 0, Bonaire can hang even if GS isn't being used.
4955 * Other chips are unaffected. These are suboptimal values,
4956 * but we don't use on-chip GS.
4957 */
4958 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4959 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4960 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4961 }
4962 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4963 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4964
4965 /* Compute LATE_ALLOC_VS.LIMIT. */
4966 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4967 (sscreen->info.max_se *
4968 sscreen->info.max_sh_per_se);
4969 unsigned late_alloc_limit; /* The limit is per SH. */
4970
4971 if (sctx->family == CHIP_KABINI) {
4972 late_alloc_limit = 0; /* Potential hang on Kabini. */
4973 } else if (num_cu_per_sh <= 4) {
4974 /* Too few available compute units per SH. Disallowing
4975 * VS to run on one CU could hurt us more than late VS
4976 * allocation would help.
4977 *
4978 * 2 is the highest safe number that allows us to keep
4979 * all CUs enabled.
4980 */
4981 late_alloc_limit = 2;
4982 } else {
4983 /* This is a good initial value, allowing 1 late_alloc
4984 * wave per SIMD on num_cu - 2.
4985 */
4986 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4987
4988 /* The limit is 0-based, so 0 means 1. */
4989 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4990 late_alloc_limit -= 1;
4991 }
4992
4993 /* VS can't execute on one CU if the limit is > 2. */
4994 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4995 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4996 S_00B118_WAVE_LIMIT(0x3F));
4997 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4998 S_00B11C_LIMIT(late_alloc_limit));
4999 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5000 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5001 }
5002
5003 if (sctx->chip_class >= VI) {
5004 unsigned vgt_tess_distribution;
5005
5006 vgt_tess_distribution =
5007 S_028B50_ACCUM_ISOLINE(32) |
5008 S_028B50_ACCUM_TRI(11) |
5009 S_028B50_ACCUM_QUAD(11) |
5010 S_028B50_DONUT_SPLIT(16);
5011
5012 /* Testing with Unigine Heaven extreme tesselation yielded best results
5013 * with TRAP_SPLIT = 3.
5014 */
5015 if (sctx->family == CHIP_FIJI ||
5016 sctx->family >= CHIP_POLARIS10)
5017 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5018
5019 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5020 } else if (!has_clear_state) {
5021 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5022 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5023 }
5024
5025 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5026 if (sctx->chip_class >= CIK) {
5027 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5028 S_028084_ADDRESS(border_color_va >> 40));
5029 }
5030 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5031 RADEON_PRIO_BORDER_COLORS);
5032
5033 if (sctx->chip_class >= GFX9) {
5034 unsigned num_se = sscreen->info.max_se;
5035 unsigned pc_lines = 0;
5036
5037 switch (sctx->family) {
5038 case CHIP_VEGA10:
5039 case CHIP_VEGA12:
5040 pc_lines = 4096;
5041 break;
5042 case CHIP_RAVEN:
5043 pc_lines = 1024;
5044 break;
5045 default:
5046 assert(0);
5047 }
5048
5049 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5050 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5051 S_028C48_MAX_PRIM_PER_BATCH(1023));
5052 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5053 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5054 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5055 }
5056
5057 si_pm4_upload_indirect_buffer(sctx, pm4);
5058 sctx->init_config = pm4;
5059 }