2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "radeon/r600_cs.h"
28 #include "radeon/r600_query.h"
30 #include "util/u_dual_blend.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34 #include "util/u_resource.h"
35 #include "util/u_upload_mgr.h"
37 /* Initialize an external atom (owned by ../radeon). */
39 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
40 struct r600_atom
**list_elem
)
42 atom
->id
= list_elem
- sctx
->atoms
.array
;
46 /* Initialize an atom owned by radeonsi. */
47 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
48 struct r600_atom
**list_elem
,
49 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
51 atom
->emit
= (void*)emit_func
;
52 atom
->id
= list_elem
- sctx
->atoms
.array
;
56 static unsigned si_map_swizzle(unsigned swizzle
)
60 return V_008F0C_SQ_SEL_Y
;
62 return V_008F0C_SQ_SEL_Z
;
64 return V_008F0C_SQ_SEL_W
;
66 return V_008F0C_SQ_SEL_0
;
68 return V_008F0C_SQ_SEL_1
;
69 default: /* PIPE_SWIZZLE_X */
70 return V_008F0C_SQ_SEL_X
;
74 /* 12.4 fixed-point */
75 static unsigned si_pack_float_12p4(float x
)
78 x
>= 4096 ? 0xffff : x
* 16;
82 * Inferred framebuffer and blender state.
84 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
85 * if there is not enough PS outputs.
87 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
89 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
90 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
91 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
92 * but you never know. */
93 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
97 cb_target_mask
&= blend
->cb_target_mask
;
99 /* Avoid a hang that happens when dual source blending is enabled
100 * but there is not enough color outputs. This is undefined behavior,
101 * so disable color writes completely.
103 * Reproducible with Unigine Heaven 4.0 and drirc missing.
105 if (blend
&& blend
->dual_src_blend
&&
106 sctx
->ps_shader
.cso
&&
107 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
110 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
112 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
113 * I think we don't have to do anything between IBs.
115 if (sctx
->screen
->dfsm_allowed
&&
116 sctx
->last_cb_target_mask
!= cb_target_mask
) {
117 sctx
->last_cb_target_mask
= cb_target_mask
;
119 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
120 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
123 if (sctx
->b
.chip_class
>= VI
) {
124 /* DCC MSAA workaround for blending.
125 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
126 * COMBINER_DISABLE, but that would be more complicated.
128 bool oc_disable
= (sctx
->b
.chip_class
== VI
||
129 sctx
->b
.chip_class
== GFX9
) &&
131 blend
->blend_enable_4bit
& cb_target_mask
&&
132 sctx
->framebuffer
.nr_samples
>= 2;
134 radeon_set_context_reg(cs
, R_028424_CB_DCC_CONTROL
,
135 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
136 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
137 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
));
140 /* RB+ register settings. */
141 if (sctx
->screen
->rbplus_allowed
) {
142 unsigned spi_shader_col_format
=
143 sctx
->ps_shader
.cso
?
144 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
145 unsigned sx_ps_downconvert
= 0;
146 unsigned sx_blend_opt_epsilon
= 0;
147 unsigned sx_blend_opt_control
= 0;
149 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
150 struct r600_surface
*surf
=
151 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
152 unsigned format
, swap
, spi_format
, colormask
;
153 bool has_alpha
, has_rgb
;
158 format
= G_028C70_FORMAT(surf
->cb_color_info
);
159 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
160 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
161 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
163 /* Set if RGB and A are present. */
164 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
166 if (format
== V_028C70_COLOR_8
||
167 format
== V_028C70_COLOR_16
||
168 format
== V_028C70_COLOR_32
)
169 has_rgb
= !has_alpha
;
173 /* Check the colormask and export format. */
174 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
176 if (!(colormask
& PIPE_MASK_A
))
179 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
184 /* Disable value checking for disabled channels. */
186 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
188 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
190 /* Enable down-conversion for 32bpp and smaller formats. */
192 case V_028C70_COLOR_8
:
193 case V_028C70_COLOR_8_8
:
194 case V_028C70_COLOR_8_8_8_8
:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
197 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
198 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
199 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
200 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
204 case V_028C70_COLOR_5_6_5
:
205 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
207 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
211 case V_028C70_COLOR_1_5_5_5
:
212 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
213 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
214 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
218 case V_028C70_COLOR_4_4_4_4
:
219 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
220 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
221 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
225 case V_028C70_COLOR_32
:
226 if (swap
== V_028C70_SWAP_STD
&&
227 spi_format
== V_028714_SPI_SHADER_32_R
)
228 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
229 else if (swap
== V_028C70_SWAP_ALT_REV
&&
230 spi_format
== V_028714_SPI_SHADER_32_AR
)
231 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
234 case V_028C70_COLOR_16
:
235 case V_028C70_COLOR_16_16
:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
238 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
239 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
240 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
241 if (swap
== V_028C70_SWAP_STD
||
242 swap
== V_028C70_SWAP_STD_REV
)
243 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
249 case V_028C70_COLOR_10_11_11
:
250 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
251 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
252 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
256 case V_028C70_COLOR_2_10_10_10
:
257 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
258 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
259 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
265 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
266 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
267 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
268 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
269 } else if (sctx
->screen
->has_rbplus
) {
270 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
271 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
272 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
273 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
281 static uint32_t si_translate_blend_function(int blend_func
)
283 switch (blend_func
) {
285 return V_028780_COMB_DST_PLUS_SRC
;
286 case PIPE_BLEND_SUBTRACT
:
287 return V_028780_COMB_SRC_MINUS_DST
;
288 case PIPE_BLEND_REVERSE_SUBTRACT
:
289 return V_028780_COMB_DST_MINUS_SRC
;
291 return V_028780_COMB_MIN_DST_SRC
;
293 return V_028780_COMB_MAX_DST_SRC
;
295 R600_ERR("Unknown blend function %d\n", blend_func
);
302 static uint32_t si_translate_blend_factor(int blend_fact
)
304 switch (blend_fact
) {
305 case PIPE_BLENDFACTOR_ONE
:
306 return V_028780_BLEND_ONE
;
307 case PIPE_BLENDFACTOR_SRC_COLOR
:
308 return V_028780_BLEND_SRC_COLOR
;
309 case PIPE_BLENDFACTOR_SRC_ALPHA
:
310 return V_028780_BLEND_SRC_ALPHA
;
311 case PIPE_BLENDFACTOR_DST_ALPHA
:
312 return V_028780_BLEND_DST_ALPHA
;
313 case PIPE_BLENDFACTOR_DST_COLOR
:
314 return V_028780_BLEND_DST_COLOR
;
315 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
316 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
317 case PIPE_BLENDFACTOR_CONST_COLOR
:
318 return V_028780_BLEND_CONSTANT_COLOR
;
319 case PIPE_BLENDFACTOR_CONST_ALPHA
:
320 return V_028780_BLEND_CONSTANT_ALPHA
;
321 case PIPE_BLENDFACTOR_ZERO
:
322 return V_028780_BLEND_ZERO
;
323 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
324 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
325 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
326 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
327 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
328 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
329 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
330 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
331 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
333 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
335 case PIPE_BLENDFACTOR_SRC1_COLOR
:
336 return V_028780_BLEND_SRC1_COLOR
;
337 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
338 return V_028780_BLEND_SRC1_ALPHA
;
339 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
340 return V_028780_BLEND_INV_SRC1_COLOR
;
341 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
342 return V_028780_BLEND_INV_SRC1_ALPHA
;
344 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
351 static uint32_t si_translate_blend_opt_function(int blend_func
)
353 switch (blend_func
) {
355 return V_028760_OPT_COMB_ADD
;
356 case PIPE_BLEND_SUBTRACT
:
357 return V_028760_OPT_COMB_SUBTRACT
;
358 case PIPE_BLEND_REVERSE_SUBTRACT
:
359 return V_028760_OPT_COMB_REVSUBTRACT
;
361 return V_028760_OPT_COMB_MIN
;
363 return V_028760_OPT_COMB_MAX
;
365 return V_028760_OPT_COMB_BLEND_DISABLED
;
369 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
371 switch (blend_fact
) {
372 case PIPE_BLENDFACTOR_ZERO
:
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
374 case PIPE_BLENDFACTOR_ONE
:
375 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
376 case PIPE_BLENDFACTOR_SRC_COLOR
:
377 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
378 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
379 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
380 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
381 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
382 case PIPE_BLENDFACTOR_SRC_ALPHA
:
383 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
384 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
385 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
386 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
387 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
388 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
394 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
395 struct si_state_blend
*blend
,
396 enum pipe_blend_func func
,
397 enum pipe_blendfactor src
,
398 enum pipe_blendfactor dst
,
401 /* Src factor is allowed when it does not depend on Dst */
402 static const uint32_t src_allowed
=
403 (1u << PIPE_BLENDFACTOR_ONE
) |
404 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
405 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
406 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
407 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
408 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
409 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
410 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
411 (1u << PIPE_BLENDFACTOR_ZERO
) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
414 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
415 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
416 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
419 if (dst
== PIPE_BLENDFACTOR_ONE
&&
420 (src_allowed
& (1u << src
))) {
421 /* Addition is commutative, but floating point addition isn't
422 * associative: subtle changes can be introduced via different
425 * Out-of-order is also non-deterministic, which means that
426 * this breaks OpenGL invariance requirements. So only enable
427 * out-of-order additive blending if explicitly allowed by a
430 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
431 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
432 blend
->commutative_4bit
|= chanmask
;
437 * Get rid of DST in the blend factors by commuting the operands:
438 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
440 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
441 unsigned *dst_factor
, unsigned expected_dst
,
442 unsigned replacement_src
)
444 if (*src_factor
== expected_dst
&&
445 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
446 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
447 *dst_factor
= replacement_src
;
449 /* Commuting the operands requires reversing subtractions. */
450 if (*func
== PIPE_BLEND_SUBTRACT
)
451 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
452 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
453 *func
= PIPE_BLEND_SUBTRACT
;
457 static bool si_blend_factor_uses_dst(unsigned factor
)
459 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
460 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
461 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
462 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
463 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
466 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
467 const struct pipe_blend_state
*state
,
470 struct si_context
*sctx
= (struct si_context
*)ctx
;
471 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
472 struct si_pm4_state
*pm4
= &blend
->pm4
;
473 uint32_t sx_mrt_blend_opt
[8] = {0};
474 uint32_t color_control
= 0;
479 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
480 blend
->alpha_to_one
= state
->alpha_to_one
;
481 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
482 blend
->logicop_enable
= state
->logicop_enable
;
484 if (state
->logicop_enable
) {
485 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
487 color_control
|= S_028808_ROP3(0xcc);
490 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
491 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
492 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
493 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
495 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
497 if (state
->alpha_to_coverage
)
498 blend
->need_src_alpha_4bit
|= 0xf;
500 blend
->cb_target_mask
= 0;
501 blend
->cb_target_enabled_4bit
= 0;
503 for (int i
= 0; i
< 8; i
++) {
504 /* state->rt entries > 0 only written if independent blending */
505 const int j
= state
->independent_blend_enable
? i
: 0;
507 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
508 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
509 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
510 unsigned eqA
= state
->rt
[j
].alpha_func
;
511 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
512 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
514 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
515 unsigned blend_cntl
= 0;
517 sx_mrt_blend_opt
[i
] =
518 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
519 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
521 /* Only set dual source blending for MRT0 to avoid a hang. */
522 if (i
>= 1 && blend
->dual_src_blend
) {
523 /* Vulkan does this for dual source blending. */
525 blend_cntl
|= S_028780_ENABLE(1);
527 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
531 /* Only addition and subtraction equations are supported with
532 * dual source blending.
534 if (blend
->dual_src_blend
&&
535 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
536 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
537 assert(!"Unsupported equation for dual source blending");
538 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
542 /* cb_render_state will disable unused ones */
543 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
544 if (state
->rt
[j
].colormask
)
545 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
547 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
548 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
552 si_blend_check_commutativity(sctx
->screen
, blend
,
553 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
554 si_blend_check_commutativity(sctx
->screen
, blend
,
555 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
557 /* Blending optimizations for RB+.
558 * These transformations don't change the behavior.
560 * First, get rid of DST in the blend factors:
561 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
563 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
564 PIPE_BLENDFACTOR_DST_COLOR
,
565 PIPE_BLENDFACTOR_SRC_COLOR
);
566 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
567 PIPE_BLENDFACTOR_DST_COLOR
,
568 PIPE_BLENDFACTOR_SRC_COLOR
);
569 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
570 PIPE_BLENDFACTOR_DST_ALPHA
,
571 PIPE_BLENDFACTOR_SRC_ALPHA
);
573 /* Look up the ideal settings from tables. */
574 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
575 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
576 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
577 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
579 /* Handle interdependencies. */
580 if (si_blend_factor_uses_dst(srcRGB
))
581 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
582 if (si_blend_factor_uses_dst(srcA
))
583 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
585 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
586 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
587 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
588 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
589 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
591 /* Set the final value. */
592 sx_mrt_blend_opt
[i
] =
593 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
594 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
595 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
596 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
597 S_028760_ALPHA_DST_OPT(dstA_opt
) |
598 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
600 /* Set blend state. */
601 blend_cntl
|= S_028780_ENABLE(1);
602 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
603 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
604 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
606 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
607 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
608 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
609 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
610 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
612 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
614 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
616 /* This is only important for formats without alpha. */
617 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
618 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
619 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
620 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
621 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
622 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
623 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
626 if (blend
->cb_target_mask
) {
627 color_control
|= S_028808_MODE(mode
);
629 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
632 if (sctx
->screen
->has_rbplus
) {
633 /* Disable RB+ blend optimizations for dual source blending.
636 if (blend
->dual_src_blend
) {
637 for (int i
= 0; i
< 8; i
++) {
638 sx_mrt_blend_opt
[i
] =
639 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
640 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
644 for (int i
= 0; i
< 8; i
++)
645 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
646 sx_mrt_blend_opt
[i
]);
648 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
649 if (blend
->dual_src_blend
|| state
->logicop_enable
||
650 mode
== V_028808_CB_RESOLVE
)
651 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
654 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
658 static void *si_create_blend_state(struct pipe_context
*ctx
,
659 const struct pipe_blend_state
*state
)
661 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
664 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
666 struct si_context
*sctx
= (struct si_context
*)ctx
;
667 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
668 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
673 si_pm4_bind_state(sctx
, blend
, state
);
676 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
677 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
678 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
679 sctx
->framebuffer
.nr_samples
>= 2 &&
680 sctx
->screen
->dcc_msaa_allowed
))
681 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
684 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
685 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
686 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
687 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
688 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
689 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
690 sctx
->do_update_shaders
= true;
692 if (sctx
->screen
->dpbb_allowed
&&
694 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
695 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
696 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
697 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
699 if (sctx
->screen
->has_out_of_order_rast
&&
701 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
702 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
703 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
704 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
705 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
708 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
710 struct si_context
*sctx
= (struct si_context
*)ctx
;
711 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
714 static void si_set_blend_color(struct pipe_context
*ctx
,
715 const struct pipe_blend_color
*state
)
717 struct si_context
*sctx
= (struct si_context
*)ctx
;
718 static const struct pipe_blend_color zeros
;
720 sctx
->blend_color
.state
= *state
;
721 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
722 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
725 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
727 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
729 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
730 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
737 static void si_set_clip_state(struct pipe_context
*ctx
,
738 const struct pipe_clip_state
*state
)
740 struct si_context
*sctx
= (struct si_context
*)ctx
;
741 struct pipe_constant_buffer cb
;
742 static const struct pipe_clip_state zeros
;
744 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
747 sctx
->clip_state
.state
= *state
;
748 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
749 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
752 cb
.user_buffer
= state
->ucp
;
753 cb
.buffer_offset
= 0;
754 cb
.buffer_size
= 4*4*8;
755 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
756 pipe_resource_reference(&cb
.buffer
, NULL
);
759 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
761 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
763 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
764 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
767 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
769 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
770 struct si_shader
*vs
= si_get_vs_state(sctx
);
771 struct si_shader_selector
*vs_sel
= vs
->selector
;
772 struct tgsi_shader_info
*info
= &vs_sel
->info
;
773 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
774 unsigned window_space
=
775 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
776 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
777 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
778 unsigned culldist_mask
= vs_sel
->culldist_mask
;
781 if (vs
->key
.opt
.clip_disable
) {
782 assert(!info
->culldist_writemask
);
786 total_mask
= clipdist_mask
| culldist_mask
;
788 /* Clip distances on points have no effect, so need to be implemented
789 * as cull distances. This applies for the clipvertex case as well.
791 * Setting this for primitives other than points should have no adverse
794 clipdist_mask
&= rs
->clip_plane_enable
;
795 culldist_mask
|= clipdist_mask
;
797 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
798 vs_sel
->pa_cl_vs_out_cntl
|
799 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
800 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
801 clipdist_mask
| (culldist_mask
<< 8));
802 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
803 rs
->pa_cl_clip_cntl
|
805 S_028810_CLIP_DISABLE(window_space
));
809 * inferred state between framebuffer and rasterizer
811 static void si_update_poly_offset_state(struct si_context
*sctx
)
813 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
815 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
816 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
820 /* Use the user format, not db_render_format, so that the polygon
821 * offset behaves as expected by applications.
823 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
824 case PIPE_FORMAT_Z16_UNORM
:
825 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
827 default: /* 24-bit */
828 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
830 case PIPE_FORMAT_Z32_FLOAT
:
831 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
832 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
841 static uint32_t si_translate_fill(uint32_t func
)
844 case PIPE_POLYGON_MODE_FILL
:
845 return V_028814_X_DRAW_TRIANGLES
;
846 case PIPE_POLYGON_MODE_LINE
:
847 return V_028814_X_DRAW_LINES
;
848 case PIPE_POLYGON_MODE_POINT
:
849 return V_028814_X_DRAW_POINTS
;
852 return V_028814_X_DRAW_POINTS
;
856 static void *si_create_rs_state(struct pipe_context
*ctx
,
857 const struct pipe_rasterizer_state
*state
)
859 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
860 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
861 struct si_pm4_state
*pm4
= &rs
->pm4
;
863 float psize_min
, psize_max
;
869 rs
->scissor_enable
= state
->scissor
;
870 rs
->clip_halfz
= state
->clip_halfz
;
871 rs
->two_side
= state
->light_twoside
;
872 rs
->multisample_enable
= state
->multisample
;
873 rs
->force_persample_interp
= state
->force_persample_interp
;
874 rs
->clip_plane_enable
= state
->clip_plane_enable
;
875 rs
->line_stipple_enable
= state
->line_stipple_enable
;
876 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
877 rs
->line_smooth
= state
->line_smooth
;
878 rs
->line_width
= state
->line_width
;
879 rs
->poly_smooth
= state
->poly_smooth
;
880 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
882 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
883 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
884 rs
->flatshade
= state
->flatshade
;
885 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
886 rs
->rasterizer_discard
= state
->rasterizer_discard
;
887 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
888 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
889 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
890 rs
->pa_cl_clip_cntl
=
891 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
892 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
893 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
894 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
895 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
897 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
898 S_0286D4_FLAT_SHADE_ENA(1) |
899 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
900 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
901 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
902 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
903 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
904 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
906 /* point size 12.4 fixed point */
907 tmp
= (unsigned)(state
->point_size
* 8.0);
908 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
910 if (state
->point_size_per_vertex
) {
911 psize_min
= util_get_min_point_size(state
);
914 /* Force the point size to be as if the vertex output was disabled. */
915 psize_min
= state
->point_size
;
916 psize_max
= state
->point_size
;
918 rs
->max_point_size
= psize_max
;
920 /* Divide by two, because 0.5 = 1 pixel. */
921 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
922 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
923 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
925 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
926 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
927 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
928 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
929 S_028A48_MSAA_ENABLE(state
->multisample
||
930 state
->poly_smooth
||
931 state
->line_smooth
) |
932 S_028A48_VPORT_SCISSOR_ENABLE(1) |
933 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
935 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
936 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
937 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
939 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
940 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
941 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
942 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
943 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
944 S_028814_FACE(!state
->front_ccw
) |
945 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
946 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
947 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
948 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
949 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
950 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
951 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
953 if (!rs
->uses_poly_offset
)
956 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
957 if (!rs
->pm4_poly_offset
) {
962 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
963 for (i
= 0; i
< 3; i
++) {
964 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
965 float offset_units
= state
->offset_units
;
966 float offset_scale
= state
->offset_scale
* 16.0f
;
967 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
969 if (!state
->offset_units_unscaled
) {
971 case 0: /* 16-bit zbuffer */
972 offset_units
*= 4.0f
;
973 pa_su_poly_offset_db_fmt_cntl
=
974 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
976 case 1: /* 24-bit zbuffer */
977 offset_units
*= 2.0f
;
978 pa_su_poly_offset_db_fmt_cntl
=
979 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
981 case 2: /* 32-bit zbuffer */
982 offset_units
*= 1.0f
;
983 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
984 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
989 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
991 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
993 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
995 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
997 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
998 pa_su_poly_offset_db_fmt_cntl
);
1004 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
1006 struct si_context
*sctx
= (struct si_context
*)ctx
;
1007 struct si_state_rasterizer
*old_rs
=
1008 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
1009 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1014 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
1015 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1017 /* Update the small primitive filter workaround if necessary. */
1018 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
1019 sctx
->framebuffer
.nr_samples
> 1)
1020 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
1023 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1024 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1026 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1027 si_update_poly_offset_state(sctx
);
1030 (old_rs
->scissor_enable
!= rs
->scissor_enable
||
1031 old_rs
->line_width
!= rs
->line_width
||
1032 old_rs
->max_point_size
!= rs
->max_point_size
)) {
1033 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1034 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
1038 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1039 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1040 si_mark_atom_dirty(sctx
, &sctx
->viewports
.atom
);
1044 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1045 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1046 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1048 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1049 rs
->line_stipple_enable
;
1052 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1053 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1054 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1055 old_rs
->flatshade
!= rs
->flatshade
||
1056 old_rs
->two_side
!= rs
->two_side
||
1057 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1058 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1059 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1060 old_rs
->line_smooth
!= rs
->line_smooth
||
1061 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1062 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1063 sctx
->do_update_shaders
= true;
1066 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1068 struct si_context
*sctx
= (struct si_context
*)ctx
;
1069 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1071 if (sctx
->queued
.named
.rasterizer
== state
)
1072 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1074 FREE(rs
->pm4_poly_offset
);
1075 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1079 * infeered state between dsa and stencil ref
1081 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
1083 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1084 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1085 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1087 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1088 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1089 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1090 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1091 S_028430_STENCILOPVAL(1));
1092 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1093 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1094 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1095 S_028434_STENCILOPVAL_BF(1));
1098 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1099 const struct pipe_stencil_ref
*state
)
1101 struct si_context
*sctx
= (struct si_context
*)ctx
;
1103 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1106 sctx
->stencil_ref
.state
= *state
;
1107 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1115 static uint32_t si_translate_stencil_op(int s_op
)
1118 case PIPE_STENCIL_OP_KEEP
:
1119 return V_02842C_STENCIL_KEEP
;
1120 case PIPE_STENCIL_OP_ZERO
:
1121 return V_02842C_STENCIL_ZERO
;
1122 case PIPE_STENCIL_OP_REPLACE
:
1123 return V_02842C_STENCIL_REPLACE_TEST
;
1124 case PIPE_STENCIL_OP_INCR
:
1125 return V_02842C_STENCIL_ADD_CLAMP
;
1126 case PIPE_STENCIL_OP_DECR
:
1127 return V_02842C_STENCIL_SUB_CLAMP
;
1128 case PIPE_STENCIL_OP_INCR_WRAP
:
1129 return V_02842C_STENCIL_ADD_WRAP
;
1130 case PIPE_STENCIL_OP_DECR_WRAP
:
1131 return V_02842C_STENCIL_SUB_WRAP
;
1132 case PIPE_STENCIL_OP_INVERT
:
1133 return V_02842C_STENCIL_INVERT
;
1135 R600_ERR("Unknown stencil op %d", s_op
);
1142 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1144 return s
->enabled
&& s
->writemask
&&
1145 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1146 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1147 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1150 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1152 /* REPLACE is normally order invariant, except when the stencil
1153 * reference value is written by the fragment shader. Tracking this
1154 * interaction does not seem worth the effort, so be conservative. */
1155 return op
!= PIPE_STENCIL_OP_INCR
&&
1156 op
!= PIPE_STENCIL_OP_DECR
&&
1157 op
!= PIPE_STENCIL_OP_REPLACE
;
1160 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1161 * invariant in the sense that the set of passing fragments as well as the
1162 * final stencil buffer result does not depend on the order of fragments. */
1163 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1165 return !state
->enabled
|| !state
->writemask
||
1166 /* The following assumes that Z writes are disabled. */
1167 (state
->func
== PIPE_FUNC_ALWAYS
&&
1168 si_order_invariant_stencil_op(state
->zpass_op
) &&
1169 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1170 (state
->func
== PIPE_FUNC_NEVER
&&
1171 si_order_invariant_stencil_op(state
->fail_op
));
1174 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1175 const struct pipe_depth_stencil_alpha_state
*state
)
1177 struct si_context
*sctx
= (struct si_context
*)ctx
;
1178 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1179 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1180 unsigned db_depth_control
;
1181 uint32_t db_stencil_control
= 0;
1187 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1188 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1189 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1190 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1192 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1193 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1194 S_028800_ZFUNC(state
->depth
.func
) |
1195 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1198 if (state
->stencil
[0].enabled
) {
1199 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1200 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1201 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1202 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1203 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1205 if (state
->stencil
[1].enabled
) {
1206 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1207 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1208 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1209 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1210 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1215 if (state
->alpha
.enabled
) {
1216 dsa
->alpha_func
= state
->alpha
.func
;
1218 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1219 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1221 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1224 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1225 if (state
->stencil
[0].enabled
)
1226 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1227 if (state
->depth
.bounds_test
) {
1228 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1229 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1232 dsa
->depth_enabled
= state
->depth
.enabled
;
1233 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1234 state
->depth
.writemask
;
1235 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1236 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1237 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1238 si_dsa_writes_stencil(&state
->stencil
[1]));
1239 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1240 dsa
->stencil_write_enabled
;
1242 bool zfunc_is_ordered
=
1243 state
->depth
.func
== PIPE_FUNC_NEVER
||
1244 state
->depth
.func
== PIPE_FUNC_LESS
||
1245 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1246 state
->depth
.func
== PIPE_FUNC_GREATER
||
1247 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1249 bool nozwrite_and_order_invariant_stencil
=
1250 !dsa
->db_can_write
||
1251 (!dsa
->depth_write_enabled
&&
1252 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1253 si_order_invariant_stencil_state(&state
->stencil
[1]));
1255 dsa
->order_invariance
[1].zs
=
1256 nozwrite_and_order_invariant_stencil
||
1257 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1258 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1260 dsa
->order_invariance
[1].pass_set
=
1261 nozwrite_and_order_invariant_stencil
||
1262 (!dsa
->stencil_write_enabled
&&
1263 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1264 state
->depth
.func
== PIPE_FUNC_NEVER
));
1265 dsa
->order_invariance
[0].pass_set
=
1266 !dsa
->depth_write_enabled
||
1267 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1268 state
->depth
.func
== PIPE_FUNC_NEVER
);
1270 dsa
->order_invariance
[1].pass_last
=
1271 sctx
->screen
->assume_no_z_fights
&&
1272 !dsa
->stencil_write_enabled
&&
1273 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1274 dsa
->order_invariance
[0].pass_last
=
1275 sctx
->screen
->assume_no_z_fights
&&
1276 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1281 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1283 struct si_context
*sctx
= (struct si_context
*)ctx
;
1284 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1285 struct si_state_dsa
*dsa
= state
;
1290 si_pm4_bind_state(sctx
, dsa
, dsa
);
1292 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1293 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1294 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1295 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1298 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1299 sctx
->do_update_shaders
= true;
1301 if (sctx
->screen
->dpbb_allowed
&&
1303 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1304 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1305 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1306 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
1308 if (sctx
->screen
->has_out_of_order_rast
&&
1310 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1311 sizeof(old_dsa
->order_invariance
))))
1312 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1315 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1317 struct si_context
*sctx
= (struct si_context
*)ctx
;
1318 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1321 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1323 struct pipe_depth_stencil_alpha_state dsa
= {};
1325 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1328 /* DB RENDER STATE */
1330 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1332 struct si_context
*sctx
= (struct si_context
*)ctx
;
1334 /* Pipeline stat & streamout queries. */
1336 sctx
->b
.flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1337 sctx
->b
.flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1339 sctx
->b
.flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1340 sctx
->b
.flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1343 /* Occlusion queries. */
1344 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1345 sctx
->occlusion_queries_disabled
= !enable
;
1346 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1350 static void si_set_occlusion_query_state(struct pipe_context
*ctx
,
1352 bool old_perfect_enable
)
1354 struct si_context
*sctx
= (struct si_context
*)ctx
;
1356 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1358 bool perfect_enable
= sctx
->b
.num_perfect_occlusion_queries
!= 0;
1360 if (perfect_enable
!= old_perfect_enable
)
1361 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1364 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1366 struct si_context
*sctx
= (struct si_context
*)ctx
;
1368 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1370 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1371 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1374 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1376 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1377 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1378 unsigned db_shader_control
;
1380 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1382 /* DB_RENDER_CONTROL */
1383 if (sctx
->dbcb_depth_copy_enabled
||
1384 sctx
->dbcb_stencil_copy_enabled
) {
1386 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1387 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1388 S_028000_COPY_CENTROID(1) |
1389 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1390 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1392 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1393 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1396 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1397 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1400 /* DB_COUNT_CONTROL (occlusion queries) */
1401 if (sctx
->b
.num_occlusion_queries
> 0 &&
1402 !sctx
->occlusion_queries_disabled
) {
1403 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1405 if (sctx
->b
.chip_class
>= CIK
) {
1407 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1408 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1409 S_028004_ZPASS_ENABLE(1) |
1410 S_028004_SLICE_EVEN_ENABLE(1) |
1411 S_028004_SLICE_ODD_ENABLE(1));
1414 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1415 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1418 /* Disable occlusion queries. */
1419 if (sctx
->b
.chip_class
>= CIK
) {
1422 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1426 /* DB_RENDER_OVERRIDE2 */
1427 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1428 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1429 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1430 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1432 db_shader_control
= sctx
->ps_db_shader_control
;
1434 /* Bug workaround for smoothing (overrasterization) on SI. */
1435 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1436 db_shader_control
&= C_02880C_Z_ORDER
;
1437 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1440 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1441 if (!rs
|| !rs
->multisample_enable
)
1442 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1444 if (sctx
->screen
->has_rbplus
&&
1445 !sctx
->screen
->rbplus_allowed
)
1446 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1448 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1453 * format translation
1455 static uint32_t si_translate_colorformat(enum pipe_format format
)
1457 const struct util_format_description
*desc
= util_format_description(format
);
1459 return V_028C70_COLOR_INVALID
;
1461 #define HAS_SIZE(x,y,z,w) \
1462 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1463 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1465 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1466 return V_028C70_COLOR_10_11_11
;
1468 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1469 return V_028C70_COLOR_INVALID
;
1471 /* hw cannot support mixed formats (except depth/stencil, since
1472 * stencil is not written to). */
1473 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1474 return V_028C70_COLOR_INVALID
;
1476 switch (desc
->nr_channels
) {
1478 switch (desc
->channel
[0].size
) {
1480 return V_028C70_COLOR_8
;
1482 return V_028C70_COLOR_16
;
1484 return V_028C70_COLOR_32
;
1488 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1489 switch (desc
->channel
[0].size
) {
1491 return V_028C70_COLOR_8_8
;
1493 return V_028C70_COLOR_16_16
;
1495 return V_028C70_COLOR_32_32
;
1497 } else if (HAS_SIZE(8,24,0,0)) {
1498 return V_028C70_COLOR_24_8
;
1499 } else if (HAS_SIZE(24,8,0,0)) {
1500 return V_028C70_COLOR_8_24
;
1504 if (HAS_SIZE(5,6,5,0)) {
1505 return V_028C70_COLOR_5_6_5
;
1506 } else if (HAS_SIZE(32,8,24,0)) {
1507 return V_028C70_COLOR_X24_8_32_FLOAT
;
1511 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1512 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1513 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1514 switch (desc
->channel
[0].size
) {
1516 return V_028C70_COLOR_4_4_4_4
;
1518 return V_028C70_COLOR_8_8_8_8
;
1520 return V_028C70_COLOR_16_16_16_16
;
1522 return V_028C70_COLOR_32_32_32_32
;
1524 } else if (HAS_SIZE(5,5,5,1)) {
1525 return V_028C70_COLOR_1_5_5_5
;
1526 } else if (HAS_SIZE(1,5,5,5)) {
1527 return V_028C70_COLOR_5_5_5_1
;
1528 } else if (HAS_SIZE(10,10,10,2)) {
1529 return V_028C70_COLOR_2_10_10_10
;
1533 return V_028C70_COLOR_INVALID
;
1536 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1538 if (SI_BIG_ENDIAN
) {
1539 switch(colorformat
) {
1540 /* 8-bit buffers. */
1541 case V_028C70_COLOR_8
:
1542 return V_028C70_ENDIAN_NONE
;
1544 /* 16-bit buffers. */
1545 case V_028C70_COLOR_5_6_5
:
1546 case V_028C70_COLOR_1_5_5_5
:
1547 case V_028C70_COLOR_4_4_4_4
:
1548 case V_028C70_COLOR_16
:
1549 case V_028C70_COLOR_8_8
:
1550 return V_028C70_ENDIAN_8IN16
;
1552 /* 32-bit buffers. */
1553 case V_028C70_COLOR_8_8_8_8
:
1554 case V_028C70_COLOR_2_10_10_10
:
1555 case V_028C70_COLOR_8_24
:
1556 case V_028C70_COLOR_24_8
:
1557 case V_028C70_COLOR_16_16
:
1558 return V_028C70_ENDIAN_8IN32
;
1560 /* 64-bit buffers. */
1561 case V_028C70_COLOR_16_16_16_16
:
1562 return V_028C70_ENDIAN_8IN16
;
1564 case V_028C70_COLOR_32_32
:
1565 return V_028C70_ENDIAN_8IN32
;
1567 /* 128-bit buffers. */
1568 case V_028C70_COLOR_32_32_32_32
:
1569 return V_028C70_ENDIAN_8IN32
;
1571 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1574 return V_028C70_ENDIAN_NONE
;
1578 static uint32_t si_translate_dbformat(enum pipe_format format
)
1581 case PIPE_FORMAT_Z16_UNORM
:
1582 return V_028040_Z_16
;
1583 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1584 case PIPE_FORMAT_X8Z24_UNORM
:
1585 case PIPE_FORMAT_Z24X8_UNORM
:
1586 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1587 return V_028040_Z_24
; /* deprecated on SI */
1588 case PIPE_FORMAT_Z32_FLOAT
:
1589 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1590 return V_028040_Z_32_FLOAT
;
1592 return V_028040_Z_INVALID
;
1597 * Texture translation
1600 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1601 enum pipe_format format
,
1602 const struct util_format_description
*desc
,
1605 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1606 bool enable_compressed_formats
= (sscreen
->info
.drm_major
== 2 &&
1607 sscreen
->info
.drm_minor
>= 31) ||
1608 sscreen
->info
.drm_major
== 3;
1609 bool uniform
= true;
1612 /* Colorspace (return non-RGB formats directly). */
1613 switch (desc
->colorspace
) {
1614 /* Depth stencil formats */
1615 case UTIL_FORMAT_COLORSPACE_ZS
:
1617 case PIPE_FORMAT_Z16_UNORM
:
1618 return V_008F14_IMG_DATA_FORMAT_16
;
1619 case PIPE_FORMAT_X24S8_UINT
:
1620 case PIPE_FORMAT_S8X24_UINT
:
1622 * Implemented as an 8_8_8_8 data format to fix texture
1623 * gathers in stencil sampling. This affects at least
1624 * GL45-CTS.texture_cube_map_array.sampling on VI.
1626 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1627 case PIPE_FORMAT_Z24X8_UNORM
:
1628 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1629 return V_008F14_IMG_DATA_FORMAT_8_24
;
1630 case PIPE_FORMAT_X8Z24_UNORM
:
1631 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1632 return V_008F14_IMG_DATA_FORMAT_24_8
;
1633 case PIPE_FORMAT_S8_UINT
:
1634 return V_008F14_IMG_DATA_FORMAT_8
;
1635 case PIPE_FORMAT_Z32_FLOAT
:
1636 return V_008F14_IMG_DATA_FORMAT_32
;
1637 case PIPE_FORMAT_X32_S8X24_UINT
:
1638 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1639 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1644 case UTIL_FORMAT_COLORSPACE_YUV
:
1645 goto out_unknown
; /* TODO */
1647 case UTIL_FORMAT_COLORSPACE_SRGB
:
1648 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1656 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1657 if (!enable_compressed_formats
)
1661 case PIPE_FORMAT_RGTC1_SNORM
:
1662 case PIPE_FORMAT_LATC1_SNORM
:
1663 case PIPE_FORMAT_RGTC1_UNORM
:
1664 case PIPE_FORMAT_LATC1_UNORM
:
1665 return V_008F14_IMG_DATA_FORMAT_BC4
;
1666 case PIPE_FORMAT_RGTC2_SNORM
:
1667 case PIPE_FORMAT_LATC2_SNORM
:
1668 case PIPE_FORMAT_RGTC2_UNORM
:
1669 case PIPE_FORMAT_LATC2_UNORM
:
1670 return V_008F14_IMG_DATA_FORMAT_BC5
;
1676 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1677 (sscreen
->info
.family
== CHIP_STONEY
||
1678 sscreen
->info
.family
== CHIP_VEGA10
||
1679 sscreen
->info
.family
== CHIP_RAVEN
)) {
1681 case PIPE_FORMAT_ETC1_RGB8
:
1682 case PIPE_FORMAT_ETC2_RGB8
:
1683 case PIPE_FORMAT_ETC2_SRGB8
:
1684 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1685 case PIPE_FORMAT_ETC2_RGB8A1
:
1686 case PIPE_FORMAT_ETC2_SRGB8A1
:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1688 case PIPE_FORMAT_ETC2_RGBA8
:
1689 case PIPE_FORMAT_ETC2_SRGBA8
:
1690 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1691 case PIPE_FORMAT_ETC2_R11_UNORM
:
1692 case PIPE_FORMAT_ETC2_R11_SNORM
:
1693 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1694 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1695 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1696 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1702 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1703 if (!enable_compressed_formats
)
1707 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1708 case PIPE_FORMAT_BPTC_SRGBA
:
1709 return V_008F14_IMG_DATA_FORMAT_BC7
;
1710 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1711 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1712 return V_008F14_IMG_DATA_FORMAT_BC6
;
1718 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1720 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1721 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1722 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1723 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1724 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1725 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1731 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1732 if (!enable_compressed_formats
)
1736 case PIPE_FORMAT_DXT1_RGB
:
1737 case PIPE_FORMAT_DXT1_RGBA
:
1738 case PIPE_FORMAT_DXT1_SRGB
:
1739 case PIPE_FORMAT_DXT1_SRGBA
:
1740 return V_008F14_IMG_DATA_FORMAT_BC1
;
1741 case PIPE_FORMAT_DXT3_RGBA
:
1742 case PIPE_FORMAT_DXT3_SRGBA
:
1743 return V_008F14_IMG_DATA_FORMAT_BC2
;
1744 case PIPE_FORMAT_DXT5_RGBA
:
1745 case PIPE_FORMAT_DXT5_SRGBA
:
1746 return V_008F14_IMG_DATA_FORMAT_BC3
;
1752 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1753 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1754 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1755 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1758 /* R8G8Bx_SNORM - TODO CxV8U8 */
1760 /* hw cannot support mixed formats (except depth/stencil, since only
1762 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1765 /* See whether the components are of the same size. */
1766 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1767 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1770 /* Non-uniform formats. */
1772 switch(desc
->nr_channels
) {
1774 if (desc
->channel
[0].size
== 5 &&
1775 desc
->channel
[1].size
== 6 &&
1776 desc
->channel
[2].size
== 5) {
1777 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1781 if (desc
->channel
[0].size
== 5 &&
1782 desc
->channel
[1].size
== 5 &&
1783 desc
->channel
[2].size
== 5 &&
1784 desc
->channel
[3].size
== 1) {
1785 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1787 if (desc
->channel
[0].size
== 1 &&
1788 desc
->channel
[1].size
== 5 &&
1789 desc
->channel
[2].size
== 5 &&
1790 desc
->channel
[3].size
== 5) {
1791 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1793 if (desc
->channel
[0].size
== 10 &&
1794 desc
->channel
[1].size
== 10 &&
1795 desc
->channel
[2].size
== 10 &&
1796 desc
->channel
[3].size
== 2) {
1797 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1804 if (first_non_void
< 0 || first_non_void
> 3)
1807 /* uniform formats */
1808 switch (desc
->channel
[first_non_void
].size
) {
1810 switch (desc
->nr_channels
) {
1811 #if 0 /* Not supported for render targets */
1813 return V_008F14_IMG_DATA_FORMAT_4_4
;
1816 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1820 switch (desc
->nr_channels
) {
1822 return V_008F14_IMG_DATA_FORMAT_8
;
1824 return V_008F14_IMG_DATA_FORMAT_8_8
;
1826 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1830 switch (desc
->nr_channels
) {
1832 return V_008F14_IMG_DATA_FORMAT_16
;
1834 return V_008F14_IMG_DATA_FORMAT_16_16
;
1836 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1840 switch (desc
->nr_channels
) {
1842 return V_008F14_IMG_DATA_FORMAT_32
;
1844 return V_008F14_IMG_DATA_FORMAT_32_32
;
1845 #if 0 /* Not supported for render targets */
1847 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1850 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1855 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1859 static unsigned si_tex_wrap(unsigned wrap
)
1863 case PIPE_TEX_WRAP_REPEAT
:
1864 return V_008F30_SQ_TEX_WRAP
;
1865 case PIPE_TEX_WRAP_CLAMP
:
1866 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1867 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1868 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1869 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1870 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1871 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1872 return V_008F30_SQ_TEX_MIRROR
;
1873 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1874 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1875 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1876 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1877 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1878 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1882 static unsigned si_tex_mipfilter(unsigned filter
)
1885 case PIPE_TEX_MIPFILTER_NEAREST
:
1886 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1887 case PIPE_TEX_MIPFILTER_LINEAR
:
1888 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1890 case PIPE_TEX_MIPFILTER_NONE
:
1891 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1895 static unsigned si_tex_compare(unsigned compare
)
1899 case PIPE_FUNC_NEVER
:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1901 case PIPE_FUNC_LESS
:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1903 case PIPE_FUNC_EQUAL
:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1905 case PIPE_FUNC_LEQUAL
:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1907 case PIPE_FUNC_GREATER
:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1909 case PIPE_FUNC_NOTEQUAL
:
1910 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1911 case PIPE_FUNC_GEQUAL
:
1912 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1913 case PIPE_FUNC_ALWAYS
:
1914 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1918 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1919 unsigned view_target
, unsigned nr_samples
)
1921 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1923 if (view_target
== PIPE_TEXTURE_CUBE
||
1924 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1925 res_target
= view_target
;
1926 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1927 else if (res_target
== PIPE_TEXTURE_CUBE
||
1928 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1929 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1931 /* GFX9 allocates 1D textures as 2D. */
1932 if ((res_target
== PIPE_TEXTURE_1D
||
1933 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1934 sscreen
->info
.chip_class
>= GFX9
&&
1935 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1936 if (res_target
== PIPE_TEXTURE_1D
)
1937 res_target
= PIPE_TEXTURE_2D
;
1939 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1942 switch (res_target
) {
1944 case PIPE_TEXTURE_1D
:
1945 return V_008F1C_SQ_RSRC_IMG_1D
;
1946 case PIPE_TEXTURE_1D_ARRAY
:
1947 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1948 case PIPE_TEXTURE_2D
:
1949 case PIPE_TEXTURE_RECT
:
1950 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1951 V_008F1C_SQ_RSRC_IMG_2D
;
1952 case PIPE_TEXTURE_2D_ARRAY
:
1953 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1954 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1955 case PIPE_TEXTURE_3D
:
1956 return V_008F1C_SQ_RSRC_IMG_3D
;
1957 case PIPE_TEXTURE_CUBE
:
1958 case PIPE_TEXTURE_CUBE_ARRAY
:
1959 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1964 * Format support testing
1967 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1969 const struct util_format_description
*desc
= util_format_description(format
);
1973 return si_translate_texformat(screen
, format
, desc
,
1974 util_format_get_first_non_void_channel(format
)) != ~0U;
1977 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1978 const struct util_format_description
*desc
,
1983 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1984 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1986 assert(first_non_void
>= 0);
1988 if (desc
->nr_channels
== 4 &&
1989 desc
->channel
[0].size
== 10 &&
1990 desc
->channel
[1].size
== 10 &&
1991 desc
->channel
[2].size
== 10 &&
1992 desc
->channel
[3].size
== 2)
1993 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1995 /* See whether the components are of the same size. */
1996 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1997 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1998 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2001 switch (desc
->channel
[first_non_void
].size
) {
2003 switch (desc
->nr_channels
) {
2005 case 3: /* 3 loads */
2006 return V_008F0C_BUF_DATA_FORMAT_8
;
2008 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2010 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2014 switch (desc
->nr_channels
) {
2016 case 3: /* 3 loads */
2017 return V_008F0C_BUF_DATA_FORMAT_16
;
2019 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2021 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2025 switch (desc
->nr_channels
) {
2027 return V_008F0C_BUF_DATA_FORMAT_32
;
2029 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2031 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2033 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2037 /* Legacy double formats. */
2038 switch (desc
->nr_channels
) {
2039 case 1: /* 1 load */
2040 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2041 case 2: /* 1 load */
2042 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2043 case 3: /* 3 loads */
2044 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2045 case 4: /* 2 loads */
2046 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2051 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2054 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2055 const struct util_format_description
*desc
,
2058 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2059 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2061 assert(first_non_void
>= 0);
2063 switch (desc
->channel
[first_non_void
].type
) {
2064 case UTIL_FORMAT_TYPE_SIGNED
:
2065 case UTIL_FORMAT_TYPE_FIXED
:
2066 if (desc
->channel
[first_non_void
].size
>= 32 ||
2067 desc
->channel
[first_non_void
].pure_integer
)
2068 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2069 else if (desc
->channel
[first_non_void
].normalized
)
2070 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2072 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2074 case UTIL_FORMAT_TYPE_UNSIGNED
:
2075 if (desc
->channel
[first_non_void
].size
>= 32 ||
2076 desc
->channel
[first_non_void
].pure_integer
)
2077 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2078 else if (desc
->channel
[first_non_void
].normalized
)
2079 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2081 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2083 case UTIL_FORMAT_TYPE_FLOAT
:
2085 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2089 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2090 enum pipe_format format
,
2093 const struct util_format_description
*desc
;
2095 unsigned data_format
;
2097 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2098 PIPE_BIND_SAMPLER_VIEW
|
2099 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2101 desc
= util_format_description(format
);
2105 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2106 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2107 * for read-only access (with caveats surrounding bounds checks), but
2108 * obviously fails for write access which we have to implement for
2109 * shader images. Luckily, OpenGL doesn't expect this to be supported
2110 * anyway, and so the only impact is on PBO uploads / downloads, which
2111 * shouldn't be expected to be fast for GL_RGB anyway.
2113 if (desc
->block
.bits
== 3 * 8 ||
2114 desc
->block
.bits
== 3 * 16) {
2115 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2116 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2122 first_non_void
= util_format_get_first_non_void_channel(format
);
2123 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2124 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2130 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2132 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2133 si_translate_colorswap(format
, false) != ~0U;
2136 static bool si_is_zs_format_supported(enum pipe_format format
)
2138 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2141 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2142 enum pipe_format format
,
2143 enum pipe_texture_target target
,
2144 unsigned sample_count
,
2147 unsigned retval
= 0;
2149 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2150 R600_ERR("r600: unsupported texture type %d\n", target
);
2154 if (!util_format_is_supported(format
, usage
))
2157 if (sample_count
> 1) {
2158 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2161 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2164 switch (sample_count
) {
2170 if (format
== PIPE_FORMAT_NONE
)
2179 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2180 PIPE_BIND_SHADER_IMAGE
)) {
2181 if (target
== PIPE_BUFFER
) {
2182 retval
|= si_is_vertex_format_supported(
2183 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2184 PIPE_BIND_SHADER_IMAGE
));
2186 if (si_is_sampler_format_supported(screen
, format
))
2187 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2188 PIPE_BIND_SHADER_IMAGE
);
2192 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2193 PIPE_BIND_DISPLAY_TARGET
|
2196 PIPE_BIND_BLENDABLE
)) &&
2197 si_is_colorbuffer_format_supported(format
)) {
2199 (PIPE_BIND_RENDER_TARGET
|
2200 PIPE_BIND_DISPLAY_TARGET
|
2203 if (!util_format_is_pure_integer(format
) &&
2204 !util_format_is_depth_or_stencil(format
))
2205 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2208 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2209 si_is_zs_format_supported(format
)) {
2210 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2213 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2214 retval
|= si_is_vertex_format_supported(screen
, format
,
2215 PIPE_BIND_VERTEX_BUFFER
);
2218 if ((usage
& PIPE_BIND_LINEAR
) &&
2219 !util_format_is_compressed(format
) &&
2220 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2221 retval
|= PIPE_BIND_LINEAR
;
2223 return retval
== usage
;
2227 * framebuffer handling
2230 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2231 unsigned format
, unsigned swap
,
2232 unsigned ntype
, bool is_depth
)
2234 /* Alpha is needed for alpha-to-coverage.
2235 * Blending may be with or without alpha.
2237 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2238 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2239 unsigned blend
= 0; /* supports blending, but may not export alpha */
2240 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2242 /* Choose the SPI color formats. These are required values for RB+.
2243 * Other chips have multiple choices, though they are not necessarily better.
2246 case V_028C70_COLOR_5_6_5
:
2247 case V_028C70_COLOR_1_5_5_5
:
2248 case V_028C70_COLOR_5_5_5_1
:
2249 case V_028C70_COLOR_4_4_4_4
:
2250 case V_028C70_COLOR_10_11_11
:
2251 case V_028C70_COLOR_11_11_10
:
2252 case V_028C70_COLOR_8
:
2253 case V_028C70_COLOR_8_8
:
2254 case V_028C70_COLOR_8_8_8_8
:
2255 case V_028C70_COLOR_10_10_10_2
:
2256 case V_028C70_COLOR_2_10_10_10
:
2257 if (ntype
== V_028C70_NUMBER_UINT
)
2258 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2259 else if (ntype
== V_028C70_NUMBER_SINT
)
2260 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2262 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2265 case V_028C70_COLOR_16
:
2266 case V_028C70_COLOR_16_16
:
2267 case V_028C70_COLOR_16_16_16_16
:
2268 if (ntype
== V_028C70_NUMBER_UNORM
||
2269 ntype
== V_028C70_NUMBER_SNORM
) {
2270 /* UNORM16 and SNORM16 don't support blending */
2271 if (ntype
== V_028C70_NUMBER_UNORM
)
2272 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2274 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2276 /* Use 32 bits per channel for blending. */
2277 if (format
== V_028C70_COLOR_16
) {
2278 if (swap
== V_028C70_SWAP_STD
) { /* R */
2279 blend
= V_028714_SPI_SHADER_32_R
;
2280 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2281 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2282 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2285 } else if (format
== V_028C70_COLOR_16_16
) {
2286 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2287 blend
= V_028714_SPI_SHADER_32_GR
;
2288 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2289 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2290 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2293 } else /* 16_16_16_16 */
2294 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2295 } else if (ntype
== V_028C70_NUMBER_UINT
)
2296 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2297 else if (ntype
== V_028C70_NUMBER_SINT
)
2298 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2299 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2300 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2305 case V_028C70_COLOR_32
:
2306 if (swap
== V_028C70_SWAP_STD
) { /* R */
2307 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2308 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2309 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2310 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2315 case V_028C70_COLOR_32_32
:
2316 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2317 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2318 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2319 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2320 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2325 case V_028C70_COLOR_32_32_32_32
:
2326 case V_028C70_COLOR_8_24
:
2327 case V_028C70_COLOR_24_8
:
2328 case V_028C70_COLOR_X24_8_32_FLOAT
:
2329 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2337 /* The DB->CB copy needs 32_ABGR. */
2339 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2341 surf
->spi_shader_col_format
= normal
;
2342 surf
->spi_shader_col_format_alpha
= alpha
;
2343 surf
->spi_shader_col_format_blend
= blend
;
2344 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2347 static void si_initialize_color_surface(struct si_context
*sctx
,
2348 struct r600_surface
*surf
)
2350 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2351 unsigned color_info
, color_attrib
;
2352 unsigned format
, swap
, ntype
, endian
;
2353 const struct util_format_description
*desc
;
2355 unsigned blend_clamp
= 0, blend_bypass
= 0;
2357 desc
= util_format_description(surf
->base
.format
);
2358 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2359 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2363 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2364 ntype
= V_028C70_NUMBER_FLOAT
;
2366 ntype
= V_028C70_NUMBER_UNORM
;
2367 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2368 ntype
= V_028C70_NUMBER_SRGB
;
2369 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2370 if (desc
->channel
[firstchan
].pure_integer
) {
2371 ntype
= V_028C70_NUMBER_SINT
;
2373 assert(desc
->channel
[firstchan
].normalized
);
2374 ntype
= V_028C70_NUMBER_SNORM
;
2376 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2377 if (desc
->channel
[firstchan
].pure_integer
) {
2378 ntype
= V_028C70_NUMBER_UINT
;
2380 assert(desc
->channel
[firstchan
].normalized
);
2381 ntype
= V_028C70_NUMBER_UNORM
;
2386 format
= si_translate_colorformat(surf
->base
.format
);
2387 if (format
== V_028C70_COLOR_INVALID
) {
2388 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2390 assert(format
!= V_028C70_COLOR_INVALID
);
2391 swap
= si_translate_colorswap(surf
->base
.format
, false);
2392 endian
= si_colorformat_endian_swap(format
);
2394 /* blend clamp should be set for all NORM/SRGB types */
2395 if (ntype
== V_028C70_NUMBER_UNORM
||
2396 ntype
== V_028C70_NUMBER_SNORM
||
2397 ntype
== V_028C70_NUMBER_SRGB
)
2400 /* set blend bypass according to docs if SINT/UINT or
2401 8/24 COLOR variants */
2402 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2403 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2404 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2409 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2410 if (format
== V_028C70_COLOR_8
||
2411 format
== V_028C70_COLOR_8_8
||
2412 format
== V_028C70_COLOR_8_8_8_8
)
2413 surf
->color_is_int8
= true;
2414 else if (format
== V_028C70_COLOR_10_10_10_2
||
2415 format
== V_028C70_COLOR_2_10_10_10
)
2416 surf
->color_is_int10
= true;
2419 color_info
= S_028C70_FORMAT(format
) |
2420 S_028C70_COMP_SWAP(swap
) |
2421 S_028C70_BLEND_CLAMP(blend_clamp
) |
2422 S_028C70_BLEND_BYPASS(blend_bypass
) |
2423 S_028C70_SIMPLE_FLOAT(1) |
2424 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2425 ntype
!= V_028C70_NUMBER_SNORM
&&
2426 ntype
!= V_028C70_NUMBER_SRGB
&&
2427 format
!= V_028C70_COLOR_8_24
&&
2428 format
!= V_028C70_COLOR_24_8
) |
2429 S_028C70_NUMBER_TYPE(ntype
) |
2430 S_028C70_ENDIAN(endian
);
2432 /* Intensity is implemented as Red, so treat it that way. */
2433 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2434 util_format_is_intensity(surf
->base
.format
));
2436 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2437 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2439 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2440 S_028C74_NUM_FRAGMENTS(log_samples
);
2442 if (rtex
->fmask
.size
) {
2443 color_info
|= S_028C70_COMPRESSION(1);
2444 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2446 if (sctx
->b
.chip_class
== SI
) {
2447 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2448 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2453 if (sctx
->b
.chip_class
>= VI
) {
2454 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2455 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2457 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2458 64 for APU because all of our APUs to date use DIMMs which have
2459 a request granularity size of 64B while all other chips have a
2461 if (!sctx
->screen
->info
.has_dedicated_vram
)
2462 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2464 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2465 if (rtex
->surface
.bpe
== 1)
2466 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2467 else if (rtex
->surface
.bpe
== 2)
2468 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2471 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2472 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2473 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2476 /* This must be set for fast clear to work without FMASK. */
2477 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2478 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2479 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2482 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2483 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2485 if (sctx
->b
.chip_class
>= GFX9
) {
2486 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2488 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2489 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2490 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2491 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2492 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2493 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2496 surf
->cb_color_view
= color_view
;
2497 surf
->cb_color_info
= color_info
;
2498 surf
->cb_color_attrib
= color_attrib
;
2500 /* Determine pixel shader export format */
2501 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2503 surf
->color_initialized
= true;
2506 static void si_init_depth_surface(struct si_context
*sctx
,
2507 struct r600_surface
*surf
)
2509 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2510 unsigned level
= surf
->base
.u
.tex
.level
;
2511 unsigned format
, stencil_format
;
2512 uint32_t z_info
, s_info
;
2514 format
= si_translate_dbformat(rtex
->db_render_format
);
2515 stencil_format
= rtex
->surface
.has_stencil
?
2516 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2518 assert(format
!= V_028040_Z_INVALID
);
2519 if (format
== V_028040_Z_INVALID
)
2520 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2522 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2523 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2524 surf
->db_htile_data_base
= 0;
2525 surf
->db_htile_surface
= 0;
2527 if (sctx
->b
.chip_class
>= GFX9
) {
2528 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2529 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2530 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2531 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2532 z_info
= S_028038_FORMAT(format
) |
2533 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2534 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2535 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2536 s_info
= S_02803C_FORMAT(stencil_format
) |
2537 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2538 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2539 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2540 surf
->db_depth_view
|= S_028008_MIPID(level
);
2541 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2542 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2544 if (si_htile_enabled(rtex
, level
)) {
2545 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2546 S_028038_ALLOW_EXPCLEAR(1);
2548 if (rtex
->tc_compatible_htile
) {
2549 unsigned max_zplanes
= 4;
2551 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2552 rtex
->resource
.b
.b
.nr_samples
> 1)
2555 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2556 S_028038_ITERATE_FLUSH(1);
2557 s_info
|= S_02803C_ITERATE_FLUSH(1);
2560 if (rtex
->surface
.has_stencil
) {
2561 /* Stencil buffer workaround ported from the SI-CI-VI code.
2562 * See that for explanation.
2564 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2566 /* Use all HTILE for depth if there's no stencil. */
2567 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2570 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2571 rtex
->htile_offset
) >> 8;
2572 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2573 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2574 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2578 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2580 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2582 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2583 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2584 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2585 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2587 z_info
= S_028040_FORMAT(format
) |
2588 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2589 s_info
= S_028044_FORMAT(stencil_format
);
2590 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2592 if (sctx
->b
.chip_class
>= CIK
) {
2593 struct radeon_info
*info
= &sctx
->screen
->info
;
2594 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2595 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2596 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2597 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2598 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2599 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2601 surf
->db_depth_info
|=
2602 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2603 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2604 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2605 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2606 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2607 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2608 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2609 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2611 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2612 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2613 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2614 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2617 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2618 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2619 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2620 levelinfo
->nblk_y
) / 64 - 1);
2622 if (si_htile_enabled(rtex
, level
)) {
2623 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2624 S_028040_ALLOW_EXPCLEAR(1);
2626 if (rtex
->surface
.has_stencil
) {
2627 /* Workaround: For a not yet understood reason, the
2628 * combination of MSAA, fast stencil clear and stencil
2629 * decompress messes with subsequent stencil buffer
2630 * uses. Problem was reproduced on Verde, Bonaire,
2631 * Tonga, and Carrizo.
2633 * Disabling EXPCLEAR works around the problem.
2635 * Check piglit's arb_texture_multisample-stencil-clear
2636 * test if you want to try changing this.
2638 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2639 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2640 } else if (!rtex
->tc_compatible_htile
) {
2641 /* Use all of the htile_buffer for depth if there's no stencil.
2642 * This must not be set when TC-compatible HTILE is enabled
2645 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2648 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2649 rtex
->htile_offset
) >> 8;
2650 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2652 if (rtex
->tc_compatible_htile
) {
2653 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2655 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2656 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2657 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2658 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2660 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2665 surf
->db_z_info
= z_info
;
2666 surf
->db_stencil_info
= s_info
;
2668 surf
->depth_initialized
= true;
2671 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2673 if (sctx
->decompression_enabled
)
2676 if (sctx
->framebuffer
.state
.zsbuf
) {
2677 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2678 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2680 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2682 if (rtex
->surface
.has_stencil
)
2683 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2686 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2687 while (compressed_cb_mask
) {
2688 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2689 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2690 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2692 if (rtex
->fmask
.size
)
2693 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2694 if (rtex
->dcc_gather_statistics
)
2695 rtex
->separate_dcc_dirty
= true;
2699 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2701 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2702 struct r600_surface
*surf
= NULL
;
2703 struct r600_texture
*rtex
;
2705 if (!state
->cbufs
[i
])
2707 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2708 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2710 p_atomic_dec(&rtex
->framebuffers_bound
);
2714 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2715 const struct pipe_framebuffer_state
*state
)
2717 struct si_context
*sctx
= (struct si_context
*)ctx
;
2718 struct pipe_constant_buffer constbuf
= {0};
2719 struct r600_surface
*surf
= NULL
;
2720 struct r600_texture
*rtex
;
2721 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2722 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2723 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2724 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2725 bool old_has_stencil
=
2727 ((struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2728 bool unbound
= false;
2731 si_update_fb_dirtiness_after_rendering(sctx
);
2733 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2734 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2737 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2738 if (rtex
->dcc_gather_statistics
)
2739 vi_separate_dcc_stop_query(ctx
, rtex
);
2742 /* Disable DCC if the formats are incompatible. */
2743 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2744 if (!state
->cbufs
[i
])
2747 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2748 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2750 if (!surf
->dcc_incompatible
)
2753 /* Since the DCC decompression calls back into set_framebuffer-
2754 * _state, we need to unbind the framebuffer, so that
2755 * vi_separate_dcc_stop_query isn't called twice with the same
2759 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2763 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2764 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
2765 sctx
->b
.decompress_dcc(ctx
, rtex
);
2767 surf
->dcc_incompatible
= false;
2770 /* Only flush TC when changing the framebuffer state, because
2771 * the only client not using TC that can change textures is
2774 * Wait for compute shaders because of possible transitions:
2775 * - FB write -> shader read
2776 * - shader write -> FB read
2778 * DB caches are flushed on demand (using si_decompress_textures).
2780 * When MSAA is enabled, CB and TC caches are flushed on demand
2781 * (after FMASK decompression). Shader write -> FB read transitions
2782 * cannot happen for MSAA textures, because MSAA shader images are
2785 * Only flush and wait for CB if there is actually a bound color buffer.
2787 if (sctx
->framebuffer
.uncompressed_cb_mask
)
2788 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2789 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2791 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2793 /* u_blitter doesn't invoke depth decompression when it does multiple
2794 * blits in a row, but the only case when it matters for DB is when
2795 * doing generate_mipmap. So here we flush DB manually between
2796 * individual generate_mipmap blits.
2797 * Note that lower mipmap levels aren't compressed.
2799 if (sctx
->generate_mipmap_for_depth
) {
2800 si_make_DB_shader_coherent(sctx
, 1, false,
2801 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2802 } else if (sctx
->b
.chip_class
== GFX9
) {
2803 /* It appears that DB metadata "leaks" in a sequence of:
2805 * - DCC decompress for shader image writes (with DB disabled)
2806 * - render with DEPTH_BEFORE_SHADER=1
2807 * Flushing DB metadata works around the problem.
2809 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2812 /* Take the maximum of the old and new count. If the new count is lower,
2813 * dirtying is needed to disable the unbound colorbuffers.
2815 sctx
->framebuffer
.dirty_cbufs
|=
2816 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2817 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2819 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2820 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2822 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2823 sctx
->framebuffer
.spi_shader_col_format
= 0;
2824 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2825 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2826 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2827 sctx
->framebuffer
.color_is_int8
= 0;
2828 sctx
->framebuffer
.color_is_int10
= 0;
2830 sctx
->framebuffer
.compressed_cb_mask
= 0;
2831 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2832 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2833 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2834 sctx
->framebuffer
.any_dst_linear
= false;
2835 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2836 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2838 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2839 if (!state
->cbufs
[i
])
2842 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2843 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2845 if (!surf
->color_initialized
) {
2846 si_initialize_color_surface(sctx
, surf
);
2849 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2850 sctx
->framebuffer
.spi_shader_col_format
|=
2851 surf
->spi_shader_col_format
<< (i
* 4);
2852 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2853 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2854 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2855 surf
->spi_shader_col_format_blend
<< (i
* 4);
2856 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2857 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2859 if (surf
->color_is_int8
)
2860 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2861 if (surf
->color_is_int10
)
2862 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2864 if (rtex
->fmask
.size
)
2865 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2867 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2869 if (rtex
->surface
.is_linear
)
2870 sctx
->framebuffer
.any_dst_linear
= true;
2872 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2873 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2875 si_context_add_resource_size(ctx
, surf
->base
.texture
);
2877 p_atomic_inc(&rtex
->framebuffers_bound
);
2879 if (rtex
->dcc_gather_statistics
) {
2880 /* Dirty tracking must be enabled for DCC usage analysis. */
2881 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2882 vi_separate_dcc_start_query(ctx
, rtex
);
2886 struct r600_texture
*zstex
= NULL
;
2889 surf
= (struct r600_surface
*)state
->zsbuf
;
2890 zstex
= (struct r600_texture
*)surf
->base
.texture
;
2892 if (!surf
->depth_initialized
) {
2893 si_init_depth_surface(sctx
, surf
);
2896 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2897 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2899 si_context_add_resource_size(ctx
, surf
->base
.texture
);
2902 si_update_poly_offset_state(sctx
);
2903 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2904 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2906 if (sctx
->screen
->dpbb_allowed
)
2907 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
2909 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2910 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2912 if (sctx
->screen
->has_out_of_order_rast
&&
2913 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2914 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2915 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2916 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2918 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2919 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2920 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2922 /* Set sample locations as fragment shader constants. */
2923 switch (sctx
->framebuffer
.nr_samples
) {
2925 constbuf
.user_buffer
= sctx
->sample_locations_1x
;
2928 constbuf
.user_buffer
= sctx
->sample_locations_2x
;
2931 constbuf
.user_buffer
= sctx
->sample_locations_4x
;
2934 constbuf
.user_buffer
= sctx
->sample_locations_8x
;
2937 constbuf
.user_buffer
= sctx
->sample_locations_16x
;
2940 R600_ERR("Requested an invalid number of samples %i.\n",
2941 sctx
->framebuffer
.nr_samples
);
2944 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2945 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2947 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2950 sctx
->do_update_shaders
= true;
2952 if (!sctx
->decompression_enabled
) {
2953 /* Prevent textures decompression when the framebuffer state
2954 * changes come from the decompression passes themselves.
2956 sctx
->need_check_render_feedback
= true;
2960 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2962 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2963 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2964 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2965 struct r600_texture
*tex
= NULL
;
2966 struct r600_surface
*cb
= NULL
;
2967 unsigned cb_color_info
= 0;
2970 for (i
= 0; i
< nr_cbufs
; i
++) {
2971 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2972 unsigned cb_color_attrib
;
2974 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2977 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2979 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2980 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2984 tex
= (struct r600_texture
*)cb
->base
.texture
;
2985 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2986 &tex
->resource
, RADEON_USAGE_READWRITE
,
2987 tex
->resource
.b
.b
.nr_samples
> 1 ?
2988 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2989 RADEON_PRIO_COLOR_BUFFER
);
2991 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2992 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2993 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2997 if (tex
->dcc_separate_buffer
)
2998 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2999 tex
->dcc_separate_buffer
,
3000 RADEON_USAGE_READWRITE
,
3003 /* Compute mutable surface parameters. */
3004 cb_color_base
= tex
->resource
.gpu_address
>> 8;
3007 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3008 cb_color_attrib
= cb
->cb_color_attrib
;
3010 if (tex
->fmask
.size
) {
3011 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
3012 cb_color_fmask
|= tex
->fmask
.tile_swizzle
;
3016 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3017 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3018 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3019 state
->cbufs
[1] == &cb
->base
&&
3020 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3022 if (!is_msaa_resolve_dst
)
3023 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3025 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
3026 tex
->dcc_offset
) >> 8;
3027 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3030 if (sctx
->b
.chip_class
>= GFX9
) {
3031 struct gfx9_surf_meta_flags meta
;
3033 if (tex
->dcc_offset
)
3034 meta
= tex
->surface
.u
.gfx9
.dcc
;
3036 meta
= tex
->surface
.u
.gfx9
.cmask
;
3038 /* Set mutable surface parameters. */
3039 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3040 cb_color_base
|= tex
->surface
.tile_swizzle
;
3041 if (!tex
->fmask
.size
)
3042 cb_color_fmask
= cb_color_base
;
3043 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3044 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3045 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3046 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3048 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3049 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3050 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3051 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3052 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3053 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3054 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3055 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3056 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3057 radeon_emit(cs
, S_028C80_BASE_256B(tex
->cmask
.base_address_reg
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3058 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3059 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3060 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3061 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3062 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3063 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3065 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3066 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3068 /* Compute mutable surface parameters (SI-CI-VI). */
3069 const struct legacy_surf_level
*level_info
=
3070 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3071 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3072 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3074 cb_color_base
+= level_info
->offset
>> 8;
3075 /* Only macrotiled modes can set tile swizzle. */
3076 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3077 cb_color_base
|= tex
->surface
.tile_swizzle
;
3079 if (!tex
->fmask
.size
)
3080 cb_color_fmask
= cb_color_base
;
3082 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3084 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3085 slice_tile_max
= level_info
->nblk_x
*
3086 level_info
->nblk_y
/ 64 - 1;
3087 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3089 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3090 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3091 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3093 if (tex
->fmask
.size
) {
3094 if (sctx
->b
.chip_class
>= CIK
)
3095 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
3096 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
3097 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
3099 /* This must be set for fast clear to work without FMASK. */
3100 if (sctx
->b
.chip_class
>= CIK
)
3101 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3102 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3103 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3106 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3107 sctx
->b
.chip_class
>= VI
? 14 : 13);
3108 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3109 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3110 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3111 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3112 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3113 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3114 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3115 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3116 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3117 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3118 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3119 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3120 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3122 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3123 radeon_emit(cs
, cb_dcc_base
);
3127 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3128 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3131 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3132 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
3133 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
3135 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3136 &rtex
->resource
, RADEON_USAGE_READWRITE
,
3137 zb
->base
.texture
->nr_samples
> 1 ?
3138 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3139 RADEON_PRIO_DEPTH_BUFFER
);
3141 if (sctx
->b
.chip_class
>= GFX9
) {
3142 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3143 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3144 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3145 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3147 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3148 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3149 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3150 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3151 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3152 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3153 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3154 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3155 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3156 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3157 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3158 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3160 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3161 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3162 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3164 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3166 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3167 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3168 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3169 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3170 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3171 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3172 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3173 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3174 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3175 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3176 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3179 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3180 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3181 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3183 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3184 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3185 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3186 if (sctx
->b
.chip_class
>= GFX9
)
3187 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3189 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3191 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3192 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3195 /* Framebuffer dimensions. */
3196 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3197 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3198 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3200 if (sctx
->screen
->dfsm_allowed
) {
3201 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3202 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3205 sctx
->framebuffer
.dirty_cbufs
= 0;
3206 sctx
->framebuffer
.dirty_zsbuf
= false;
3209 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
3210 struct r600_atom
*atom
)
3212 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3213 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3214 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3216 /* Smoothing (only possible with nr_samples == 1) uses the same
3217 * sample locations as the MSAA it simulates.
3219 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3220 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3222 /* On Polaris, the small primitive filter uses the sample locations
3223 * even when MSAA is off, so we need to make sure they're set to 0.
3225 if (has_msaa_sample_loc_bug
)
3226 nr_samples
= MAX2(nr_samples
, 1);
3228 if (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
) {
3229 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
3230 si_emit_sample_locations(cs
, nr_samples
);
3233 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
3234 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3235 unsigned small_prim_filter_cntl
=
3236 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3238 S_028830_LINE_FILTER_DISABLE(sctx
->b
.family
<= CHIP_POLARIS12
);
3240 /* The alternative of setting sample locations to 0 would
3241 * require a DB flush to avoid Z errors, see
3242 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3244 if (has_msaa_sample_loc_bug
&&
3245 sctx
->framebuffer
.nr_samples
> 1 &&
3246 rs
&& !rs
->multisample_enable
)
3247 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3249 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3250 small_prim_filter_cntl
);
3254 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3256 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3257 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3259 if (!sctx
->screen
->has_out_of_order_rast
)
3262 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3265 colormask
&= blend
->cb_target_enabled_4bit
;
3270 /* Conservative: No logic op. */
3271 if (colormask
&& blend
->logicop_enable
)
3274 struct si_dsa_order_invariance dsa_order_invariant
= {
3275 .zs
= true, .pass_set
= true, .pass_last
= false
3278 if (sctx
->framebuffer
.state
.zsbuf
) {
3279 struct r600_texture
*zstex
=
3280 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3281 bool has_stencil
= zstex
->surface
.has_stencil
;
3282 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3283 if (!dsa_order_invariant
.zs
)
3286 /* The set of PS invocations is always order invariant,
3287 * except when early Z/S tests are requested. */
3288 if (sctx
->ps_shader
.cso
&&
3289 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3290 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3291 !dsa_order_invariant
.pass_set
)
3294 if (sctx
->b
.num_perfect_occlusion_queries
!= 0 &&
3295 !dsa_order_invariant
.pass_set
)
3302 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3305 /* Only commutative blending. */
3306 if (blendmask
& ~blend
->commutative_4bit
)
3309 if (!dsa_order_invariant
.pass_set
)
3313 if (colormask
& ~blendmask
) {
3314 if (!dsa_order_invariant
.pass_last
)
3321 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
3323 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3324 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3325 /* 33% faster rendering to linear color buffers */
3326 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3327 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3328 unsigned sc_mode_cntl_1
=
3329 S_028A4C_WALK_SIZE(dst_is_linear
) |
3330 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3331 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3332 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3333 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3335 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3336 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3337 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3338 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3339 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3340 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3342 int setup_samples
= sctx
->framebuffer
.nr_samples
> 1 ? sctx
->framebuffer
.nr_samples
:
3343 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0;
3345 /* Required by OpenGL line rasterization.
3347 * TODO: We should also enable perpendicular endcaps for AA lines,
3348 * but that requires implementing line stippling in the pixel
3349 * shader. SC can only do line stippling with axis-aligned
3352 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3354 if (setup_samples
> 1) {
3355 /* distance from the pixel center, indexed by log2(nr_samples) */
3356 static unsigned max_dist
[] = {
3363 unsigned log_samples
= util_logbase2(setup_samples
);
3364 unsigned log_ps_iter_samples
=
3365 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
3367 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3368 radeon_emit(cs
, sc_line_cntl
|
3369 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3370 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3371 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3372 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3374 if (sctx
->framebuffer
.nr_samples
> 1) {
3375 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3376 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
3377 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3378 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3379 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
3380 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3381 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3382 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3383 S_028A4C_PS_ITER_SAMPLE(sctx
->ps_iter_samples
> 1) |
3385 } else if (sctx
->smoothing_enabled
) {
3386 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3387 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3388 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3389 S_028804_OVERRASTERIZATION_AMOUNT(log_samples
));
3390 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3394 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3395 radeon_emit(cs
, sc_line_cntl
); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3396 radeon_emit(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3398 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3399 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3400 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3401 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3405 /* GFX9: Flush DFSM when the AA mode changes. */
3406 if (sctx
->screen
->dfsm_allowed
) {
3407 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3408 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3412 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3414 struct si_context
*sctx
= (struct si_context
*)ctx
;
3416 if (sctx
->ps_iter_samples
== min_samples
)
3419 sctx
->ps_iter_samples
= min_samples
;
3420 sctx
->do_update_shaders
= true;
3422 if (sctx
->framebuffer
.nr_samples
> 1)
3423 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3424 if (sctx
->screen
->dpbb_allowed
)
3425 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3433 * Build the sampler view descriptor for a buffer texture.
3434 * @param state 256-bit descriptor; only the high 128 bits are filled in
3437 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3438 enum pipe_format format
,
3439 unsigned offset
, unsigned size
,
3442 const struct util_format_description
*desc
;
3445 unsigned num_records
;
3446 unsigned num_format
, data_format
;
3448 desc
= util_format_description(format
);
3449 first_non_void
= util_format_get_first_non_void_channel(format
);
3450 stride
= desc
->block
.bits
/ 8;
3451 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3452 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3454 num_records
= size
/ stride
;
3455 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3457 /* The NUM_RECORDS field has a different meaning depending on the chip,
3458 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3461 * - If STRIDE == 0, it's in byte units.
3462 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3465 * - For SMEM and STRIDE == 0, it's in byte units.
3466 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3467 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3468 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3469 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3470 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3471 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3472 * That way the same descriptor can be used by both SMEM and VMEM.
3475 * - For SMEM and STRIDE == 0, it's in byte units.
3476 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3477 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3478 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3480 if (screen
->info
.chip_class
>= GFX9
)
3481 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3482 * from STRIDE to bytes. This works around it by setting
3483 * NUM_RECORDS to at least the size of one element, so that
3484 * the first element is readable when IDXEN == 0.
3486 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3487 * IDXEN is enforced?
3489 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3490 else if (screen
->info
.chip_class
== VI
)
3491 num_records
*= stride
;
3494 state
[5] = S_008F04_STRIDE(stride
);
3495 state
[6] = num_records
;
3496 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3497 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3498 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3499 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3500 S_008F0C_NUM_FORMAT(num_format
) |
3501 S_008F0C_DATA_FORMAT(data_format
);
3504 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3506 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3508 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3509 /* For the pre-defined border color values (white, opaque
3510 * black, transparent black), the only thing that matters is
3511 * that the alpha channel winds up in the correct place
3512 * (because the RGB channels are all the same) so either of
3513 * these enumerations will work.
3515 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3516 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3518 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3519 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3520 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3521 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3523 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3524 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3525 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3526 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3527 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3534 * Build the sampler view descriptor for a texture.
3537 si_make_texture_descriptor(struct si_screen
*screen
,
3538 struct r600_texture
*tex
,
3540 enum pipe_texture_target target
,
3541 enum pipe_format pipe_format
,
3542 const unsigned char state_swizzle
[4],
3543 unsigned first_level
, unsigned last_level
,
3544 unsigned first_layer
, unsigned last_layer
,
3545 unsigned width
, unsigned height
, unsigned depth
,
3547 uint32_t *fmask_state
)
3549 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
3550 const struct util_format_description
*desc
;
3551 unsigned char swizzle
[4];
3553 unsigned num_format
, data_format
, type
;
3556 desc
= util_format_description(pipe_format
);
3558 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3559 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3560 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3561 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3563 switch (pipe_format
) {
3564 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3565 case PIPE_FORMAT_X32_S8X24_UINT
:
3566 case PIPE_FORMAT_X8Z24_UNORM
:
3567 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3569 case PIPE_FORMAT_X24S8_UINT
:
3571 * X24S8 is implemented as an 8_8_8_8 data format, to
3572 * fix texture gathers. This affects at least
3573 * GL45-CTS.texture_cube_map_array.sampling on VI.
3575 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3578 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3581 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3584 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3586 switch (pipe_format
) {
3587 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3588 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3591 if (first_non_void
< 0) {
3592 if (util_format_is_compressed(pipe_format
)) {
3593 switch (pipe_format
) {
3594 case PIPE_FORMAT_DXT1_SRGB
:
3595 case PIPE_FORMAT_DXT1_SRGBA
:
3596 case PIPE_FORMAT_DXT3_SRGBA
:
3597 case PIPE_FORMAT_DXT5_SRGBA
:
3598 case PIPE_FORMAT_BPTC_SRGBA
:
3599 case PIPE_FORMAT_ETC2_SRGB8
:
3600 case PIPE_FORMAT_ETC2_SRGB8A1
:
3601 case PIPE_FORMAT_ETC2_SRGBA8
:
3602 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3604 case PIPE_FORMAT_RGTC1_SNORM
:
3605 case PIPE_FORMAT_LATC1_SNORM
:
3606 case PIPE_FORMAT_RGTC2_SNORM
:
3607 case PIPE_FORMAT_LATC2_SNORM
:
3608 case PIPE_FORMAT_ETC2_R11_SNORM
:
3609 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3610 /* implies float, so use SNORM/UNORM to determine
3611 whether data is signed or not */
3612 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3613 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3616 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3619 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3620 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3622 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3624 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3625 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3627 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3629 switch (desc
->channel
[first_non_void
].type
) {
3630 case UTIL_FORMAT_TYPE_FLOAT
:
3631 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3633 case UTIL_FORMAT_TYPE_SIGNED
:
3634 if (desc
->channel
[first_non_void
].normalized
)
3635 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3636 else if (desc
->channel
[first_non_void
].pure_integer
)
3637 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3639 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3641 case UTIL_FORMAT_TYPE_UNSIGNED
:
3642 if (desc
->channel
[first_non_void
].normalized
)
3643 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3644 else if (desc
->channel
[first_non_void
].pure_integer
)
3645 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3647 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3652 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3653 if (data_format
== ~0) {
3657 /* S8 with Z32 HTILE needs a special format. */
3658 if (screen
->info
.chip_class
>= GFX9
&&
3659 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3660 tex
->tc_compatible_htile
)
3661 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3664 (res
->target
== PIPE_TEXTURE_CUBE
||
3665 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3666 (screen
->info
.chip_class
<= VI
&&
3667 res
->target
== PIPE_TEXTURE_3D
))) {
3668 /* For the purpose of shader images, treat cube maps and 3D
3669 * textures as 2D arrays. For 3D textures, the address
3670 * calculations for mipmaps are different, so we rely on the
3671 * caller to effectively disable mipmaps.
3673 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3675 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3677 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3680 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3682 depth
= res
->array_size
;
3683 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3684 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3685 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3686 depth
= res
->array_size
;
3687 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3688 depth
= res
->array_size
/ 6;
3691 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3692 S_008F14_NUM_FORMAT_GFX6(num_format
));
3693 state
[2] = (S_008F18_WIDTH(width
- 1) |
3694 S_008F18_HEIGHT(height
- 1) |
3695 S_008F18_PERF_MOD(4));
3696 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3697 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3698 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3699 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3700 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3702 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3703 util_logbase2(res
->nr_samples
) :
3705 S_008F1C_TYPE(type
));
3707 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3711 if (screen
->info
.chip_class
>= GFX9
) {
3712 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3714 /* Depth is the the last accessible layer on Gfx9.
3715 * The hw doesn't need to know the total number of layers.
3717 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3718 state
[4] |= S_008F20_DEPTH(depth
- 1);
3720 state
[4] |= S_008F20_DEPTH(last_layer
);
3722 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3723 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3724 util_logbase2(res
->nr_samples
) :
3725 tex
->resource
.b
.b
.last_level
);
3727 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3728 state
[4] |= S_008F20_DEPTH(depth
- 1);
3729 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3732 if (tex
->dcc_offset
) {
3733 unsigned swap
= si_translate_colorswap(pipe_format
, false);
3735 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3737 /* The last dword is unused by hw. The shader uses it to clear
3738 * bits in the first dword of sampler state.
3740 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3741 if (first_level
== last_level
)
3742 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3744 state
[7] = 0xffffffff;
3748 /* Initialize the sampler view for FMASK. */
3749 if (tex
->fmask
.size
) {
3750 uint32_t data_format
, num_format
;
3752 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3754 if (screen
->info
.chip_class
>= GFX9
) {
3755 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3756 switch (res
->nr_samples
) {
3758 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3761 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3764 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3767 unreachable("invalid nr_samples");
3770 switch (res
->nr_samples
) {
3772 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3775 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3778 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3781 unreachable("invalid nr_samples");
3783 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3786 fmask_state
[0] = (va
>> 8) | tex
->fmask
.tile_swizzle
;
3787 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3788 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3789 S_008F14_NUM_FORMAT_GFX6(num_format
);
3790 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3791 S_008F18_HEIGHT(height
- 1);
3792 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3793 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3794 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3795 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3796 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3798 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3802 if (screen
->info
.chip_class
>= GFX9
) {
3803 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3804 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3805 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3806 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3807 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3809 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3810 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3811 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3812 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3818 * Create a sampler view.
3820 * @param ctx context
3821 * @param texture texture
3822 * @param state sampler view template
3823 * @param width0 width0 override (for compressed textures as int)
3824 * @param height0 height0 override (for compressed textures as int)
3825 * @param force_level set the base address to the level (for compressed textures)
3827 struct pipe_sampler_view
*
3828 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3829 struct pipe_resource
*texture
,
3830 const struct pipe_sampler_view
*state
,
3831 unsigned width0
, unsigned height0
,
3832 unsigned force_level
)
3834 struct si_context
*sctx
= (struct si_context
*)ctx
;
3835 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3836 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3837 unsigned base_level
, first_level
, last_level
;
3838 unsigned char state_swizzle
[4];
3839 unsigned height
, depth
, width
;
3840 unsigned last_layer
= state
->u
.tex
.last_layer
;
3841 enum pipe_format pipe_format
;
3842 const struct legacy_surf_level
*surflevel
;
3847 /* initialize base object */
3848 view
->base
= *state
;
3849 view
->base
.texture
= NULL
;
3850 view
->base
.reference
.count
= 1;
3851 view
->base
.context
= ctx
;
3854 pipe_resource_reference(&view
->base
.texture
, texture
);
3856 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3857 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3858 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3859 state
->format
== PIPE_FORMAT_S8_UINT
)
3860 view
->is_stencil_sampler
= true;
3862 /* Buffer resource. */
3863 if (texture
->target
== PIPE_BUFFER
) {
3864 si_make_buffer_descriptor(sctx
->screen
,
3865 (struct r600_resource
*)texture
,
3867 state
->u
.buf
.offset
,
3873 state_swizzle
[0] = state
->swizzle_r
;
3874 state_swizzle
[1] = state
->swizzle_g
;
3875 state_swizzle
[2] = state
->swizzle_b
;
3876 state_swizzle
[3] = state
->swizzle_a
;
3879 first_level
= state
->u
.tex
.first_level
;
3880 last_level
= state
->u
.tex
.last_level
;
3883 depth
= texture
->depth0
;
3885 if (sctx
->b
.chip_class
<= VI
&& force_level
) {
3886 assert(force_level
== first_level
&&
3887 force_level
== last_level
);
3888 base_level
= force_level
;
3891 width
= u_minify(width
, force_level
);
3892 height
= u_minify(height
, force_level
);
3893 depth
= u_minify(depth
, force_level
);
3896 /* This is not needed if state trackers set last_layer correctly. */
3897 if (state
->target
== PIPE_TEXTURE_1D
||
3898 state
->target
== PIPE_TEXTURE_2D
||
3899 state
->target
== PIPE_TEXTURE_RECT
||
3900 state
->target
== PIPE_TEXTURE_CUBE
)
3901 last_layer
= state
->u
.tex
.first_layer
;
3903 /* Texturing with separate depth and stencil. */
3904 pipe_format
= state
->format
;
3906 /* Depth/stencil texturing sometimes needs separate texture. */
3907 if (tmp
->is_depth
&& !si_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3908 if (!tmp
->flushed_depth_texture
&&
3909 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3910 pipe_resource_reference(&view
->base
.texture
, NULL
);
3915 assert(tmp
->flushed_depth_texture
);
3917 /* Override format for the case where the flushed texture
3918 * contains only Z or only S.
3920 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3921 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3923 tmp
= tmp
->flushed_depth_texture
;
3926 surflevel
= tmp
->surface
.u
.legacy
.level
;
3928 if (tmp
->db_compatible
) {
3929 if (!view
->is_stencil_sampler
)
3930 pipe_format
= tmp
->db_render_format
;
3932 switch (pipe_format
) {
3933 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3934 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3936 case PIPE_FORMAT_X8Z24_UNORM
:
3937 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3938 /* Z24 is always stored like this for DB
3941 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3943 case PIPE_FORMAT_X24S8_UINT
:
3944 case PIPE_FORMAT_S8X24_UINT
:
3945 case PIPE_FORMAT_X32_S8X24_UINT
:
3946 pipe_format
= PIPE_FORMAT_S8_UINT
;
3947 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3953 view
->dcc_incompatible
=
3954 vi_dcc_formats_are_incompatible(texture
,
3955 state
->u
.tex
.first_level
,
3958 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3959 state
->target
, pipe_format
, state_swizzle
,
3960 first_level
, last_level
,
3961 state
->u
.tex
.first_layer
, last_layer
,
3962 width
, height
, depth
,
3963 view
->state
, view
->fmask_state
);
3965 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
3967 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
3968 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
3969 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
3970 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
3971 view
->base_level_info
= &surflevel
[base_level
];
3972 view
->base_level
= base_level
;
3973 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3977 static struct pipe_sampler_view
*
3978 si_create_sampler_view(struct pipe_context
*ctx
,
3979 struct pipe_resource
*texture
,
3980 const struct pipe_sampler_view
*state
)
3982 return si_create_sampler_view_custom(ctx
, texture
, state
,
3983 texture
? texture
->width0
: 0,
3984 texture
? texture
->height0
: 0, 0);
3987 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3988 struct pipe_sampler_view
*state
)
3990 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3992 pipe_resource_reference(&state
->texture
, NULL
);
3996 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3998 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3999 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4001 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4002 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4005 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4006 const struct pipe_sampler_state
*state
,
4007 const union pipe_color_union
*color
,
4010 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4011 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4013 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4014 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4015 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4016 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4018 #define simple_border_types(elt) \
4020 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4021 color->elt[2] == 0 && color->elt[3] == 0) \
4022 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4023 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4024 color->elt[2] == 0 && color->elt[3] == 1) \
4025 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4026 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4027 color->elt[2] == 1 && color->elt[3] == 1) \
4028 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4032 simple_border_types(ui
);
4034 simple_border_types(f
);
4036 #undef simple_border_types
4040 /* Check if the border has been uploaded already. */
4041 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4042 if (memcmp(&sctx
->border_color_table
[i
], color
,
4043 sizeof(*color
)) == 0)
4046 if (i
>= SI_MAX_BORDER_COLORS
) {
4047 /* Getting 4096 unique border colors is very unlikely. */
4048 fprintf(stderr
, "radeonsi: The border color table is full. "
4049 "Any new border colors will be just black. "
4050 "Please file a bug.\n");
4051 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4054 if (i
== sctx
->border_color_count
) {
4055 /* Upload a new border color. */
4056 memcpy(&sctx
->border_color_table
[i
], color
,
4058 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4059 color
, sizeof(*color
));
4060 sctx
->border_color_count
++;
4063 return S_008F3C_BORDER_COLOR_PTR(i
) |
4064 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4067 static inline int S_FIXED(float value
, unsigned frac_bits
)
4069 return value
* (1 << frac_bits
);
4072 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4074 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4075 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4076 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4078 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4079 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4082 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4095 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4096 const struct pipe_sampler_state
*state
)
4098 struct si_context
*sctx
= (struct si_context
*)ctx
;
4099 struct si_screen
*sscreen
= sctx
->screen
;
4100 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4101 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4102 : state
->max_anisotropy
;
4103 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4104 union pipe_color_union clamped_border_color
;
4111 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4113 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4114 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4115 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4116 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4117 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4118 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4119 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4120 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4121 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4122 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
4123 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4124 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4125 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4126 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4127 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4128 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4129 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4130 S_008F38_MIP_POINT_PRECLAMP(0) |
4131 S_008F38_DISABLE_LSB_CEIL(sctx
->b
.chip_class
<= VI
) |
4132 S_008F38_FILTER_PREC_FIX(1) |
4133 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
4134 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4136 /* Create sampler resource for integer textures. */
4137 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4138 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4140 /* Create sampler resource for upgraded depth textures. */
4141 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4143 for (unsigned i
= 0; i
< 4; ++i
) {
4144 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4145 * when the border color is 1.0. */
4146 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4149 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4150 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4152 rstate
->upgraded_depth_val
[3] =
4153 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4154 S_008F3C_UPGRADED_DEPTH(1);
4159 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4161 struct si_context
*sctx
= (struct si_context
*)ctx
;
4163 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
4166 sctx
->sample_mask
.sample_mask
= sample_mask
;
4167 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
4170 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
4172 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
4173 unsigned mask
= sctx
->sample_mask
.sample_mask
;
4175 /* Needed for line and polygon smoothing as well as for the Polaris
4176 * small primitive filter. We expect the state tracker to take care of
4179 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4180 (mask
& 1 && sctx
->blitter
->running
));
4182 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4183 radeon_emit(cs
, mask
| (mask
<< 16));
4184 radeon_emit(cs
, mask
| (mask
<< 16));
4187 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4190 struct si_sampler_state
*s
= state
;
4192 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4199 * Vertex elements & buffers
4202 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4204 const struct pipe_vertex_element
*elements
)
4206 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4207 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4208 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4211 assert(count
<= SI_MAX_ATTRIBS
);
4216 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4218 for (i
= 0; i
< count
; ++i
) {
4219 const struct util_format_description
*desc
;
4220 const struct util_format_channel_description
*channel
;
4221 unsigned data_format
, num_format
;
4223 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4224 unsigned char swizzle
[4];
4226 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4231 if (elements
[i
].instance_divisor
) {
4232 v
->uses_instance_divisors
= true;
4233 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4235 if (v
->instance_divisors
[i
] == 1)
4236 v
->instance_divisor_is_one
|= 1u << i
;
4238 v
->instance_divisor_is_fetched
|= 1u << i
;
4241 if (!used
[vbo_index
]) {
4242 v
->first_vb_use_mask
|= 1 << i
;
4243 used
[vbo_index
] = true;
4246 desc
= util_format_description(elements
[i
].src_format
);
4247 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4248 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4249 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4250 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4251 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4253 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4254 v
->src_offset
[i
] = elements
[i
].src_offset
;
4255 v
->vertex_buffer_index
[i
] = vbo_index
;
4257 /* The hardware always treats the 2-bit alpha channel as
4258 * unsigned, so a shader workaround is needed. The affected
4259 * chips are VI and older except Stoney (GFX8.1).
4261 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4262 sscreen
->info
.chip_class
<= VI
&&
4263 sscreen
->info
.family
!= CHIP_STONEY
) {
4264 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4265 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4266 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4267 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4268 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4269 /* This isn't actually used in OpenGL. */
4270 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4272 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4273 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4274 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4276 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4277 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4278 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4279 if (channel
->normalized
) {
4280 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4281 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4283 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4285 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4287 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4288 if (channel
->normalized
) {
4289 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4290 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4292 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4294 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4297 } else if (channel
&& channel
->size
== 64 &&
4298 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4299 switch (desc
->nr_channels
) {
4302 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4303 swizzle
[0] = PIPE_SWIZZLE_X
;
4304 swizzle
[1] = PIPE_SWIZZLE_Y
;
4305 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4306 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4309 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4310 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4311 swizzle
[1] = PIPE_SWIZZLE_Y
;
4312 swizzle
[2] = PIPE_SWIZZLE_0
;
4313 swizzle
[3] = PIPE_SWIZZLE_0
;
4316 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4317 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4318 swizzle
[1] = PIPE_SWIZZLE_Y
;
4319 swizzle
[2] = PIPE_SWIZZLE_Z
;
4320 swizzle
[3] = PIPE_SWIZZLE_W
;
4325 } else if (channel
&& desc
->nr_channels
== 3) {
4326 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4328 if (channel
->size
== 8) {
4329 if (channel
->pure_integer
)
4330 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4332 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4333 } else if (channel
->size
== 16) {
4334 if (channel
->pure_integer
)
4335 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4337 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4341 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4342 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4343 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4344 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4345 S_008F0C_NUM_FORMAT(num_format
) |
4346 S_008F0C_DATA_FORMAT(data_format
);
4351 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4353 struct si_context
*sctx
= (struct si_context
*)ctx
;
4354 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4355 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4357 sctx
->vertex_elements
= v
;
4358 sctx
->vertex_buffers_dirty
= true;
4362 old
->count
!= v
->count
||
4363 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4364 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4365 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4366 sctx
->do_update_shaders
= true;
4368 if (v
&& v
->instance_divisor_is_fetched
) {
4369 struct pipe_constant_buffer cb
;
4372 cb
.user_buffer
= v
->instance_divisors
;
4373 cb
.buffer_offset
= 0;
4374 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4375 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4379 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4381 struct si_context
*sctx
= (struct si_context
*)ctx
;
4383 if (sctx
->vertex_elements
== state
)
4384 sctx
->vertex_elements
= NULL
;
4388 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4389 unsigned start_slot
, unsigned count
,
4390 const struct pipe_vertex_buffer
*buffers
)
4392 struct si_context
*sctx
= (struct si_context
*)ctx
;
4393 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4396 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4399 for (i
= 0; i
< count
; i
++) {
4400 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4401 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4402 struct pipe_resource
*buf
= src
->buffer
.resource
;
4404 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4405 dsti
->buffer_offset
= src
->buffer_offset
;
4406 dsti
->stride
= src
->stride
;
4407 si_context_add_resource_size(ctx
, buf
);
4409 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4412 for (i
= 0; i
< count
; i
++) {
4413 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4416 sctx
->vertex_buffers_dirty
= true;
4423 static void si_set_tess_state(struct pipe_context
*ctx
,
4424 const float default_outer_level
[4],
4425 const float default_inner_level
[2])
4427 struct si_context
*sctx
= (struct si_context
*)ctx
;
4428 struct pipe_constant_buffer cb
;
4431 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4432 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4435 cb
.user_buffer
= NULL
;
4436 cb
.buffer_size
= sizeof(array
);
4438 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4439 (void*)array
, sizeof(array
),
4442 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4443 pipe_resource_reference(&cb
.buffer
, NULL
);
4446 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4448 struct si_context
*sctx
= (struct si_context
*)ctx
;
4450 si_update_fb_dirtiness_after_rendering(sctx
);
4452 /* Multisample surfaces are flushed in si_decompress_textures. */
4453 if (sctx
->framebuffer
.uncompressed_cb_mask
)
4454 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4455 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4458 /* This only ensures coherency for shader image/buffer stores. */
4459 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4461 struct si_context
*sctx
= (struct si_context
*)ctx
;
4463 /* Subsequent commands must wait for all shader invocations to
4465 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4466 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4468 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4469 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
4470 SI_CONTEXT_INV_VMEM_L1
;
4472 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4473 PIPE_BARRIER_SHADER_BUFFER
|
4474 PIPE_BARRIER_TEXTURE
|
4475 PIPE_BARRIER_IMAGE
|
4476 PIPE_BARRIER_STREAMOUT_BUFFER
|
4477 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4478 /* As far as I can tell, L1 contents are written back to L2
4479 * automatically at end of shader, but the contents of other
4480 * L1 caches might still be stale. */
4481 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
4484 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4485 /* Indices are read through TC L2 since VI.
4488 if (sctx
->screen
->info
.chip_class
<= CIK
)
4489 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4492 /* MSAA color, any depth and any stencil are flushed in
4493 * si_decompress_textures when needed.
4495 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4496 sctx
->framebuffer
.uncompressed_cb_mask
) {
4497 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4499 if (sctx
->b
.chip_class
<= VI
)
4500 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4503 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4504 if (sctx
->screen
->info
.chip_class
<= VI
&&
4505 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4506 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4509 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4511 struct pipe_blend_state blend
;
4513 memset(&blend
, 0, sizeof(blend
));
4514 blend
.independent_blend_enable
= true;
4515 blend
.rt
[0].colormask
= 0xf;
4516 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
4519 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
4520 bool include_draw_vbo
)
4522 si_need_cs_space((struct si_context
*)ctx
);
4525 static void si_init_config(struct si_context
*sctx
);
4527 void si_init_state_functions(struct si_context
*sctx
)
4529 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
4530 si_init_external_atom(sctx
, &sctx
->streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
4531 si_init_external_atom(sctx
, &sctx
->streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
4532 si_init_external_atom(sctx
, &sctx
->scissors
.atom
, &sctx
->atoms
.s
.scissors
);
4533 si_init_external_atom(sctx
, &sctx
->viewports
.atom
, &sctx
->atoms
.s
.viewports
);
4535 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
4536 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
4537 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
4538 si_init_atom(sctx
, &sctx
->dpbb_state
, &sctx
->atoms
.s
.dpbb_state
, si_emit_dpbb_state
);
4539 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
4540 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
4541 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
4542 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
4543 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
4544 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
4545 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
4547 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
4548 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
4549 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
4550 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
4552 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
4553 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
4554 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
4556 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4557 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4558 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4560 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4561 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4562 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4563 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4564 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4566 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
4567 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
4569 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
4571 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
4572 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
4574 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
4575 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
4577 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
4579 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
4580 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4581 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4582 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
4584 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
4585 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
4586 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
4587 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
4589 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
4590 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
4591 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
4592 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
4594 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
4596 si_init_config(sctx
);
4599 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4601 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4604 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4605 struct si_pm4_state
*pm4
, unsigned value
)
4607 unsigned reg
= sctx
->b
.chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4608 R_00802C_GRBM_GFX_INDEX
;
4609 si_pm4_set_reg(pm4
, reg
, value
);
4612 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4613 struct si_pm4_state
*pm4
, unsigned se
)
4615 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4616 si_set_grbm_gfx_index(sctx
, pm4
,
4617 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4618 S_030800_SE_INDEX(se
)) |
4619 S_030800_SH_BROADCAST_WRITES(1) |
4620 S_030800_INSTANCE_BROADCAST_WRITES(1));
4624 si_write_harvested_raster_configs(struct si_context
*sctx
,
4625 struct si_pm4_state
*pm4
,
4626 unsigned raster_config
,
4627 unsigned raster_config_1
)
4629 unsigned sh_per_se
= MAX2(sctx
->screen
->info
.max_sh_per_se
, 1);
4630 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4631 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4632 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4633 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4634 unsigned rb_per_se
= num_rb
/ num_se
;
4635 unsigned se_mask
[4];
4638 se_mask
[0] = ((1 << rb_per_se
) - 1);
4639 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4640 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4641 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4643 se_mask
[0] &= rb_mask
;
4644 se_mask
[1] &= rb_mask
;
4645 se_mask
[2] &= rb_mask
;
4646 se_mask
[3] &= rb_mask
;
4648 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4649 assert(sh_per_se
== 1 || sh_per_se
== 2);
4650 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4652 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4653 * fields are for, so I'm leaving them as their default
4656 for (se
= 0; se
< num_se
; se
++) {
4657 unsigned raster_config_se
= raster_config
;
4658 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4659 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4660 int idx
= (se
/ 2) * 2;
4662 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4663 raster_config_se
&= C_028350_SE_MAP
;
4665 if (!se_mask
[idx
]) {
4667 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4670 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4674 pkr0_mask
&= rb_mask
;
4675 pkr1_mask
&= rb_mask
;
4676 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4677 raster_config_se
&= C_028350_PKR_MAP
;
4681 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4684 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4688 if (rb_per_se
>= 2) {
4689 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4690 unsigned rb1_mask
= rb0_mask
<< 1;
4692 rb0_mask
&= rb_mask
;
4693 rb1_mask
&= rb_mask
;
4694 if (!rb0_mask
|| !rb1_mask
) {
4695 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4699 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4702 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4706 if (rb_per_se
> 2) {
4707 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4708 rb1_mask
= rb0_mask
<< 1;
4709 rb0_mask
&= rb_mask
;
4710 rb1_mask
&= rb_mask
;
4711 if (!rb0_mask
|| !rb1_mask
) {
4712 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4716 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4719 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4725 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4726 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4728 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4730 if (sctx
->b
.chip_class
>= CIK
) {
4731 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4732 (!se_mask
[2] && !se_mask
[3]))) {
4733 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4735 if (!se_mask
[0] && !se_mask
[1]) {
4737 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4740 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4744 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4748 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4750 struct si_screen
*sscreen
= sctx
->screen
;
4751 unsigned num_rb
= MIN2(sctx
->screen
->info
.num_render_backends
, 16);
4752 unsigned rb_mask
= sctx
->screen
->info
.enabled_rb_mask
;
4753 unsigned raster_config
, raster_config_1
;
4755 switch (sctx
->b
.family
) {
4758 raster_config
= 0x2a00126a;
4759 raster_config_1
= 0x00000000;
4762 raster_config
= 0x0000124a;
4763 raster_config_1
= 0x00000000;
4766 raster_config
= 0x00000082;
4767 raster_config_1
= 0x00000000;
4770 raster_config
= 0x00000000;
4771 raster_config_1
= 0x00000000;
4774 raster_config
= 0x16000012;
4775 raster_config_1
= 0x00000000;
4778 raster_config
= 0x3a00161a;
4779 raster_config_1
= 0x0000002e;
4782 if (sscreen
->info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4783 /* old kernels with old tiling config */
4784 raster_config
= 0x16000012;
4785 raster_config_1
= 0x0000002a;
4787 raster_config
= 0x3a00161a;
4788 raster_config_1
= 0x0000002e;
4791 case CHIP_POLARIS10
:
4792 raster_config
= 0x16000012;
4793 raster_config_1
= 0x0000002a;
4795 case CHIP_POLARIS11
:
4796 case CHIP_POLARIS12
:
4797 raster_config
= 0x16000012;
4798 raster_config_1
= 0x00000000;
4801 raster_config
= 0x16000012;
4802 raster_config_1
= 0x0000002a;
4806 raster_config
= 0x00000000;
4808 raster_config
= 0x00000002;
4809 raster_config_1
= 0x00000000;
4812 raster_config
= 0x00000002;
4813 raster_config_1
= 0x00000000;
4816 /* KV should be 0x00000002, but that causes problems with radeon */
4817 raster_config
= 0x00000000; /* 0x00000002 */
4818 raster_config_1
= 0x00000000;
4823 raster_config
= 0x00000000;
4824 raster_config_1
= 0x00000000;
4828 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4829 raster_config
= 0x00000000;
4830 raster_config_1
= 0x00000000;
4833 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4834 /* Always use the default config when all backends are enabled
4835 * (or when we failed to determine the enabled backends).
4837 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4839 if (sctx
->b
.chip_class
>= CIK
)
4840 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4843 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4847 static void si_init_config(struct si_context
*sctx
)
4849 struct si_screen
*sscreen
= sctx
->screen
;
4850 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4851 bool has_clear_state
= sscreen
->has_clear_state
;
4852 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4854 /* Only SI can disable CLEAR_STATE for now. */
4855 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
);
4860 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4861 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4862 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4863 si_pm4_cmd_end(pm4
, false);
4865 if (has_clear_state
) {
4866 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4867 si_pm4_cmd_add(pm4
, 0);
4868 si_pm4_cmd_end(pm4
, false);
4871 if (sctx
->b
.chip_class
<= VI
)
4872 si_set_raster_config(sctx
, pm4
);
4874 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4875 if (!has_clear_state
)
4876 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4878 /* FIXME calculate these values somehow ??? */
4879 if (sctx
->b
.chip_class
<= VI
) {
4880 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4881 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4884 if (!has_clear_state
) {
4885 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4886 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4887 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4890 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4891 if (!has_clear_state
)
4892 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4893 if (sctx
->b
.chip_class
< CIK
)
4894 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4895 S_008A14_CLIP_VTX_REORDER_ENA(1));
4897 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4898 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4900 if (!has_clear_state
)
4901 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4903 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4904 * I don't know why. Deduced by trial and error.
4906 if (sctx
->b
.chip_class
<= CIK
) {
4907 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4908 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4909 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4910 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4911 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4912 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4913 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4914 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4917 if (!has_clear_state
) {
4918 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4919 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4920 S_028230_ER_TRI(0xA) |
4921 S_028230_ER_POINT(0xA) |
4922 S_028230_ER_RECT(0xA) |
4923 /* Required by DX10_DIAMOND_TEST_ENA: */
4924 S_028230_ER_LINE_LR(0x1A) |
4925 S_028230_ER_LINE_RL(0x26) |
4926 S_028230_ER_LINE_TB(0xA) |
4927 S_028230_ER_LINE_BT(0xA));
4928 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4929 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4930 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4931 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4932 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4933 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4934 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4937 if (sctx
->b
.chip_class
>= GFX9
) {
4938 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4939 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4940 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4942 /* These registers, when written, also overwrite the CLEAR_STATE
4943 * context, so we can't rely on CLEAR_STATE setting them.
4944 * It would be an issue if there was another UMD changing them.
4946 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4947 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4948 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4951 if (sctx
->b
.chip_class
>= CIK
) {
4952 if (sctx
->b
.chip_class
>= GFX9
) {
4953 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4954 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4956 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4957 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4958 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4959 S_00B41C_WAVE_LIMIT(0x3F));
4960 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
4961 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4963 /* If this is 0, Bonaire can hang even if GS isn't being used.
4964 * Other chips are unaffected. These are suboptimal values,
4965 * but we don't use on-chip GS.
4967 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4968 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4969 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4971 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
4972 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4974 /* Compute LATE_ALLOC_VS.LIMIT. */
4975 unsigned num_cu_per_sh
= sscreen
->info
.num_good_compute_units
/
4976 (sscreen
->info
.max_se
*
4977 sscreen
->info
.max_sh_per_se
);
4978 unsigned late_alloc_limit
; /* The limit is per SH. */
4980 if (sctx
->b
.family
== CHIP_KABINI
) {
4981 late_alloc_limit
= 0; /* Potential hang on Kabini. */
4982 } else if (num_cu_per_sh
<= 4) {
4983 /* Too few available compute units per SH. Disallowing
4984 * VS to run on one CU could hurt us more than late VS
4985 * allocation would help.
4987 * 2 is the highest safe number that allows us to keep
4990 late_alloc_limit
= 2;
4992 /* This is a good initial value, allowing 1 late_alloc
4993 * wave per SIMD on num_cu - 2.
4995 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
4997 /* The limit is 0-based, so 0 means 1. */
4998 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
4999 late_alloc_limit
-= 1;
5002 /* VS can't execute on one CU if the limit is > 2. */
5003 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5004 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
5005 S_00B118_WAVE_LIMIT(0x3F));
5006 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5007 S_00B11C_LIMIT(late_alloc_limit
));
5008 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5009 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5012 if (sctx
->b
.chip_class
>= VI
) {
5013 unsigned vgt_tess_distribution
;
5015 vgt_tess_distribution
=
5016 S_028B50_ACCUM_ISOLINE(32) |
5017 S_028B50_ACCUM_TRI(11) |
5018 S_028B50_ACCUM_QUAD(11) |
5019 S_028B50_DONUT_SPLIT(16);
5021 /* Testing with Unigine Heaven extreme tesselation yielded best results
5022 * with TRAP_SPLIT = 3.
5024 if (sctx
->b
.family
== CHIP_FIJI
||
5025 sctx
->b
.family
>= CHIP_POLARIS10
)
5026 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5028 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5029 } else if (!has_clear_state
) {
5030 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5031 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5034 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5035 if (sctx
->b
.chip_class
>= CIK
) {
5036 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5037 S_028084_ADDRESS(border_color_va
>> 40));
5039 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5040 RADEON_PRIO_BORDER_COLORS
);
5042 if (sctx
->b
.chip_class
>= GFX9
) {
5043 unsigned num_se
= sscreen
->info
.max_se
;
5044 unsigned pc_lines
= 0;
5046 switch (sctx
->b
.family
) {
5058 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5059 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5060 S_028C48_MAX_PRIM_PER_BATCH(1023));
5061 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5062 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5063 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5066 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5067 sctx
->init_config
= pm4
;