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[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_pstipple.h"
36
37 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
38 void (*emit)(struct si_context *ctx, struct r600_atom *state),
39 unsigned num_dw)
40 {
41 atom->emit = (void*)emit;
42 atom->num_dw = num_dw;
43 atom->dirty = false;
44 *list_elem = atom;
45 }
46
47 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
48 {
49 if (sscreen->b.chip_class == CIK &&
50 sscreen->b.info.cik_macrotile_mode_array_valid) {
51 unsigned index, tileb;
52
53 tileb = 8 * 8 * tex->surface.bpe;
54 tileb = MIN2(tex->surface.tile_split, tileb);
55
56 for (index = 0; tileb > 64; index++) {
57 tileb >>= 1;
58 }
59 assert(index < 16);
60
61 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
62 }
63
64 if (sscreen->b.chip_class == SI &&
65 sscreen->b.info.si_tile_mode_array_valid) {
66 /* Don't use stencil_tiling_index, because num_banks is always
67 * read from the depth mode. */
68 unsigned tile_mode_index = tex->surface.tiling_index[0];
69 assert(tile_mode_index < 32);
70
71 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
72 }
73
74 /* The old way. */
75 switch (sscreen->b.tiling_info.num_banks) {
76 case 2:
77 return V_02803C_ADDR_SURF_2_BANK;
78 case 4:
79 return V_02803C_ADDR_SURF_4_BANK;
80 case 8:
81 default:
82 return V_02803C_ADDR_SURF_8_BANK;
83 case 16:
84 return V_02803C_ADDR_SURF_16_BANK;
85 }
86 }
87
88 unsigned cik_tile_split(unsigned tile_split)
89 {
90 switch (tile_split) {
91 case 64:
92 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
93 break;
94 case 128:
95 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
96 break;
97 case 256:
98 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
99 break;
100 case 512:
101 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
102 break;
103 default:
104 case 1024:
105 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
106 break;
107 case 2048:
108 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
109 break;
110 case 4096:
111 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
112 break;
113 }
114 return tile_split;
115 }
116
117 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
118 {
119 switch (macro_tile_aspect) {
120 default:
121 case 1:
122 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
123 break;
124 case 2:
125 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
126 break;
127 case 4:
128 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
129 break;
130 case 8:
131 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
132 break;
133 }
134 return macro_tile_aspect;
135 }
136
137 unsigned cik_bank_wh(unsigned bankwh)
138 {
139 switch (bankwh) {
140 default:
141 case 1:
142 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
143 break;
144 case 2:
145 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
146 break;
147 case 4:
148 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
149 break;
150 case 8:
151 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
152 break;
153 }
154 return bankwh;
155 }
156
157 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
158 {
159 if (sscreen->b.info.si_tile_mode_array_valid) {
160 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
161
162 return G_009910_PIPE_CONFIG(gb_tile_mode);
163 }
164
165 /* This is probably broken for a lot of chips, but it's only used
166 * if the kernel cannot return the tile mode array for CIK. */
167 switch (sscreen->b.info.r600_num_tile_pipes) {
168 case 16:
169 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
170 case 8:
171 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
172 case 4:
173 default:
174 if (sscreen->b.info.r600_num_backends == 4)
175 return V_02803C_X_ADDR_SURF_P4_16X16;
176 else
177 return V_02803C_X_ADDR_SURF_P4_8X16;
178 case 2:
179 return V_02803C_ADDR_SURF_P2;
180 }
181 }
182
183 static unsigned si_map_swizzle(unsigned swizzle)
184 {
185 switch (swizzle) {
186 case UTIL_FORMAT_SWIZZLE_Y:
187 return V_008F0C_SQ_SEL_Y;
188 case UTIL_FORMAT_SWIZZLE_Z:
189 return V_008F0C_SQ_SEL_Z;
190 case UTIL_FORMAT_SWIZZLE_W:
191 return V_008F0C_SQ_SEL_W;
192 case UTIL_FORMAT_SWIZZLE_0:
193 return V_008F0C_SQ_SEL_0;
194 case UTIL_FORMAT_SWIZZLE_1:
195 return V_008F0C_SQ_SEL_1;
196 default: /* UTIL_FORMAT_SWIZZLE_X */
197 return V_008F0C_SQ_SEL_X;
198 }
199 }
200
201 static uint32_t S_FIXED(float value, uint32_t frac_bits)
202 {
203 return value * (1 << frac_bits);
204 }
205
206 /* 12.4 fixed-point */
207 static unsigned si_pack_float_12p4(float x)
208 {
209 return x <= 0 ? 0 :
210 x >= 4096 ? 0xffff : x * 16;
211 }
212
213 /*
214 * Inferred framebuffer and blender state.
215 *
216 * One of the reasons this must be derived from the framebuffer state is that:
217 * - The blend state mask is 0xf most of the time.
218 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
219 * so COLOR1 is enabled pretty much all the time.
220 * So CB_TARGET_MASK is the only register that can disable COLOR1.
221 */
222 static void si_update_fb_blend_state(struct si_context *sctx)
223 {
224 struct si_pm4_state *pm4;
225 struct si_state_blend *blend = sctx->queued.named.blend;
226 uint32_t mask = 0, i;
227
228 if (blend == NULL)
229 return;
230
231 pm4 = CALLOC_STRUCT(si_pm4_state);
232 if (pm4 == NULL)
233 return;
234
235 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
236 if (sctx->framebuffer.state.cbufs[i])
237 mask |= 0xf << (4*i);
238 mask &= blend->cb_target_mask;
239
240 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
241 si_pm4_set_state(sctx, fb_blend, pm4);
242 }
243
244 /*
245 * Blender functions
246 */
247
248 static uint32_t si_translate_blend_function(int blend_func)
249 {
250 switch (blend_func) {
251 case PIPE_BLEND_ADD:
252 return V_028780_COMB_DST_PLUS_SRC;
253 case PIPE_BLEND_SUBTRACT:
254 return V_028780_COMB_SRC_MINUS_DST;
255 case PIPE_BLEND_REVERSE_SUBTRACT:
256 return V_028780_COMB_DST_MINUS_SRC;
257 case PIPE_BLEND_MIN:
258 return V_028780_COMB_MIN_DST_SRC;
259 case PIPE_BLEND_MAX:
260 return V_028780_COMB_MAX_DST_SRC;
261 default:
262 R600_ERR("Unknown blend function %d\n", blend_func);
263 assert(0);
264 break;
265 }
266 return 0;
267 }
268
269 static uint32_t si_translate_blend_factor(int blend_fact)
270 {
271 switch (blend_fact) {
272 case PIPE_BLENDFACTOR_ONE:
273 return V_028780_BLEND_ONE;
274 case PIPE_BLENDFACTOR_SRC_COLOR:
275 return V_028780_BLEND_SRC_COLOR;
276 case PIPE_BLENDFACTOR_SRC_ALPHA:
277 return V_028780_BLEND_SRC_ALPHA;
278 case PIPE_BLENDFACTOR_DST_ALPHA:
279 return V_028780_BLEND_DST_ALPHA;
280 case PIPE_BLENDFACTOR_DST_COLOR:
281 return V_028780_BLEND_DST_COLOR;
282 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
283 return V_028780_BLEND_SRC_ALPHA_SATURATE;
284 case PIPE_BLENDFACTOR_CONST_COLOR:
285 return V_028780_BLEND_CONSTANT_COLOR;
286 case PIPE_BLENDFACTOR_CONST_ALPHA:
287 return V_028780_BLEND_CONSTANT_ALPHA;
288 case PIPE_BLENDFACTOR_ZERO:
289 return V_028780_BLEND_ZERO;
290 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
291 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
292 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
293 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
294 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
295 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
296 case PIPE_BLENDFACTOR_INV_DST_COLOR:
297 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
298 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
299 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
300 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
301 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
302 case PIPE_BLENDFACTOR_SRC1_COLOR:
303 return V_028780_BLEND_SRC1_COLOR;
304 case PIPE_BLENDFACTOR_SRC1_ALPHA:
305 return V_028780_BLEND_SRC1_ALPHA;
306 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
307 return V_028780_BLEND_INV_SRC1_COLOR;
308 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
309 return V_028780_BLEND_INV_SRC1_ALPHA;
310 default:
311 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
312 assert(0);
313 break;
314 }
315 return 0;
316 }
317
318 static void *si_create_blend_state_mode(struct pipe_context *ctx,
319 const struct pipe_blend_state *state,
320 unsigned mode)
321 {
322 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
323 struct si_pm4_state *pm4 = &blend->pm4;
324
325 uint32_t color_control = 0;
326
327 if (blend == NULL)
328 return NULL;
329
330 blend->alpha_to_one = state->alpha_to_one;
331
332 if (state->logicop_enable) {
333 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
334 } else {
335 color_control |= S_028808_ROP3(0xcc);
336 }
337
338 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
339 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
340 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
341 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
342 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
343 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
344
345 blend->cb_target_mask = 0;
346 for (int i = 0; i < 8; i++) {
347 /* state->rt entries > 0 only written if independent blending */
348 const int j = state->independent_blend_enable ? i : 0;
349
350 unsigned eqRGB = state->rt[j].rgb_func;
351 unsigned srcRGB = state->rt[j].rgb_src_factor;
352 unsigned dstRGB = state->rt[j].rgb_dst_factor;
353 unsigned eqA = state->rt[j].alpha_func;
354 unsigned srcA = state->rt[j].alpha_src_factor;
355 unsigned dstA = state->rt[j].alpha_dst_factor;
356
357 unsigned blend_cntl = 0;
358
359 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
360 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
361
362 if (!state->rt[j].blend_enable) {
363 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
364 continue;
365 }
366
367 blend_cntl |= S_028780_ENABLE(1);
368 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
369 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
370 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
371
372 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
373 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
374 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
375 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
376 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
377 }
378 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
379 }
380
381 if (blend->cb_target_mask) {
382 color_control |= S_028808_MODE(mode);
383 } else {
384 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
385 }
386 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
387
388 return blend;
389 }
390
391 static void *si_create_blend_state(struct pipe_context *ctx,
392 const struct pipe_blend_state *state)
393 {
394 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
395 }
396
397 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
398 {
399 struct si_context *sctx = (struct si_context *)ctx;
400 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
401 si_update_fb_blend_state(sctx);
402 }
403
404 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
405 {
406 struct si_context *sctx = (struct si_context *)ctx;
407 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
408 }
409
410 static void si_set_blend_color(struct pipe_context *ctx,
411 const struct pipe_blend_color *state)
412 {
413 struct si_context *sctx = (struct si_context *)ctx;
414 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
415
416 if (pm4 == NULL)
417 return;
418
419 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
420 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
421 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
422 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
423
424 si_pm4_set_state(sctx, blend_color, pm4);
425 }
426
427 /*
428 * Clipping, scissors and viewport
429 */
430
431 static void si_set_clip_state(struct pipe_context *ctx,
432 const struct pipe_clip_state *state)
433 {
434 struct si_context *sctx = (struct si_context *)ctx;
435 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
436 struct pipe_constant_buffer cb;
437
438 if (pm4 == NULL)
439 return;
440
441 for (int i = 0; i < 6; i++) {
442 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
443 fui(state->ucp[i][0]));
444 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
445 fui(state->ucp[i][1]));
446 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
447 fui(state->ucp[i][2]));
448 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
449 fui(state->ucp[i][3]));
450 }
451
452 cb.buffer = NULL;
453 cb.user_buffer = state->ucp;
454 cb.buffer_offset = 0;
455 cb.buffer_size = 4*4*8;
456 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
457 pipe_resource_reference(&cb.buffer, NULL);
458
459 si_pm4_set_state(sctx, clip, pm4);
460 }
461
462 #define SIX_BITS 0x3F
463
464 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
465 {
466 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
467 struct tgsi_shader_info *info = si_get_vs_info(sctx);
468 unsigned window_space =
469 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
470 unsigned clipdist_mask =
471 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
472
473 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
474 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
475 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
476 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
477 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
478 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
479 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
480 info->writes_edgeflag ||
481 info->writes_layer) |
482 (sctx->queued.named.rasterizer->clip_plane_enable &
483 clipdist_mask));
484 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
485 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
486 (clipdist_mask ? 0 :
487 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
488 S_028810_CLIP_DISABLE(window_space));
489 }
490
491 static void si_set_scissor_states(struct pipe_context *ctx,
492 unsigned start_slot,
493 unsigned num_scissors,
494 const struct pipe_scissor_state *state)
495 {
496 struct si_context *sctx = (struct si_context *)ctx;
497 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
498 struct si_pm4_state *pm4 = &scissor->pm4;
499
500 if (scissor == NULL)
501 return;
502
503 scissor->scissor = *state;
504 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
505 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
506 S_028250_WINDOW_OFFSET_DISABLE(1));
507 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
508 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
509
510 si_pm4_set_state(sctx, scissor, scissor);
511 }
512
513 static void si_set_viewport_states(struct pipe_context *ctx,
514 unsigned start_slot,
515 unsigned num_viewports,
516 const struct pipe_viewport_state *state)
517 {
518 struct si_context *sctx = (struct si_context *)ctx;
519 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
520 struct si_pm4_state *pm4 = &viewport->pm4;
521
522 if (viewport == NULL)
523 return;
524
525 viewport->viewport = *state;
526 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
527 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
528 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
529 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
530 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
531 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
532
533 si_pm4_set_state(sctx, viewport, viewport);
534 }
535
536 /*
537 * inferred state between framebuffer and rasterizer
538 */
539 static void si_update_fb_rs_state(struct si_context *sctx)
540 {
541 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
542 struct si_pm4_state *pm4;
543 float offset_units;
544
545 if (!rs || !sctx->framebuffer.state.zsbuf)
546 return;
547
548 offset_units = sctx->queued.named.rasterizer->offset_units;
549 switch (sctx->framebuffer.state.zsbuf->texture->format) {
550 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
551 case PIPE_FORMAT_X8Z24_UNORM:
552 case PIPE_FORMAT_Z24X8_UNORM:
553 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
554 offset_units *= 2.0f;
555 break;
556 case PIPE_FORMAT_Z32_FLOAT:
557 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
558 offset_units *= 1.0f;
559 break;
560 case PIPE_FORMAT_Z16_UNORM:
561 offset_units *= 4.0f;
562 break;
563 default:
564 return;
565 }
566
567 pm4 = CALLOC_STRUCT(si_pm4_state);
568
569 if (pm4 == NULL)
570 return;
571
572 /* FIXME some of those reg can be computed with cso */
573 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
574 fui(sctx->queued.named.rasterizer->offset_scale));
575 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
576 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
577 fui(sctx->queued.named.rasterizer->offset_scale));
578 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
579
580 si_pm4_set_state(sctx, fb_rs, pm4);
581 }
582
583 /*
584 * Rasterizer
585 */
586
587 static uint32_t si_translate_fill(uint32_t func)
588 {
589 switch(func) {
590 case PIPE_POLYGON_MODE_FILL:
591 return V_028814_X_DRAW_TRIANGLES;
592 case PIPE_POLYGON_MODE_LINE:
593 return V_028814_X_DRAW_LINES;
594 case PIPE_POLYGON_MODE_POINT:
595 return V_028814_X_DRAW_POINTS;
596 default:
597 assert(0);
598 return V_028814_X_DRAW_POINTS;
599 }
600 }
601
602 static void *si_create_rs_state(struct pipe_context *ctx,
603 const struct pipe_rasterizer_state *state)
604 {
605 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
606 struct si_pm4_state *pm4 = &rs->pm4;
607 unsigned tmp;
608 float psize_min, psize_max;
609
610 if (rs == NULL) {
611 return NULL;
612 }
613
614 rs->two_side = state->light_twoside;
615 rs->multisample_enable = state->multisample;
616 rs->clip_plane_enable = state->clip_plane_enable;
617 rs->line_stipple_enable = state->line_stipple_enable;
618 rs->poly_stipple_enable = state->poly_stipple_enable;
619 rs->line_smooth = state->line_smooth;
620 rs->poly_smooth = state->poly_smooth;
621
622 rs->flatshade = state->flatshade;
623 rs->sprite_coord_enable = state->sprite_coord_enable;
624 rs->pa_sc_line_stipple = state->line_stipple_enable ?
625 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
626 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
627 rs->pa_cl_clip_cntl =
628 S_028810_PS_UCP_MODE(3) |
629 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
630 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
631 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
632 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
633 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
634
635 /* offset */
636 rs->offset_units = state->offset_units;
637 rs->offset_scale = state->offset_scale * 12.0f;
638
639 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
640 S_0286D4_FLAT_SHADE_ENA(1) |
641 S_0286D4_PNT_SPRITE_ENA(1) |
642 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
643 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
644 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
645 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
646 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
647
648 /* point size 12.4 fixed point */
649 tmp = (unsigned)(state->point_size * 8.0);
650 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
651
652 if (state->point_size_per_vertex) {
653 psize_min = util_get_min_point_size(state);
654 psize_max = 8192;
655 } else {
656 /* Force the point size to be as if the vertex output was disabled. */
657 psize_min = state->point_size;
658 psize_max = state->point_size;
659 }
660 /* Divide by two, because 0.5 = 1 pixel. */
661 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
662 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
663 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
664
665 tmp = (unsigned)state->line_width * 8;
666 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
667 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
668 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
669 S_028A48_MSAA_ENABLE(state->multisample ||
670 state->poly_smooth ||
671 state->line_smooth) |
672 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
673
674 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
675 S_028BE4_PIX_CENTER(state->half_pixel_center) |
676 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
677
678 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
679 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
680 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
681 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
682 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
683 S_028814_FACE(!state->front_ccw) |
684 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
685 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
686 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
687 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
688 state->fill_back != PIPE_POLYGON_MODE_FILL) |
689 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
690 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
691 return rs;
692 }
693
694 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 struct si_state_rasterizer *old_rs =
698 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
699 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
700
701 if (state == NULL)
702 return;
703
704 if (sctx->framebuffer.nr_samples > 1 &&
705 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
706 sctx->db_render_state.dirty = true;
707
708 si_pm4_bind_state(sctx, rasterizer, rs);
709 si_update_fb_rs_state(sctx);
710
711 sctx->clip_regs.dirty = true;
712 }
713
714 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
715 {
716 struct si_context *sctx = (struct si_context *)ctx;
717 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
718 }
719
720 /*
721 * infeered state between dsa and stencil ref
722 */
723 static void si_update_dsa_stencil_ref(struct si_context *sctx)
724 {
725 struct si_pm4_state *pm4;
726 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
727 struct si_state_dsa *dsa = sctx->queued.named.dsa;
728
729 if (!dsa)
730 return;
731
732 pm4 = CALLOC_STRUCT(si_pm4_state);
733 if (pm4 == NULL)
734 return;
735
736 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
737 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
738 S_028430_STENCILMASK(dsa->valuemask[0]) |
739 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
740 S_028430_STENCILOPVAL(1));
741 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
742 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
743 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
744 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
745 S_028434_STENCILOPVAL_BF(1));
746
747 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
748 }
749
750 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
751 const struct pipe_stencil_ref *state)
752 {
753 struct si_context *sctx = (struct si_context *)ctx;
754 sctx->stencil_ref = *state;
755 si_update_dsa_stencil_ref(sctx);
756 }
757
758
759 /*
760 * DSA
761 */
762
763 static uint32_t si_translate_stencil_op(int s_op)
764 {
765 switch (s_op) {
766 case PIPE_STENCIL_OP_KEEP:
767 return V_02842C_STENCIL_KEEP;
768 case PIPE_STENCIL_OP_ZERO:
769 return V_02842C_STENCIL_ZERO;
770 case PIPE_STENCIL_OP_REPLACE:
771 return V_02842C_STENCIL_REPLACE_TEST;
772 case PIPE_STENCIL_OP_INCR:
773 return V_02842C_STENCIL_ADD_CLAMP;
774 case PIPE_STENCIL_OP_DECR:
775 return V_02842C_STENCIL_SUB_CLAMP;
776 case PIPE_STENCIL_OP_INCR_WRAP:
777 return V_02842C_STENCIL_ADD_WRAP;
778 case PIPE_STENCIL_OP_DECR_WRAP:
779 return V_02842C_STENCIL_SUB_WRAP;
780 case PIPE_STENCIL_OP_INVERT:
781 return V_02842C_STENCIL_INVERT;
782 default:
783 R600_ERR("Unknown stencil op %d", s_op);
784 assert(0);
785 break;
786 }
787 return 0;
788 }
789
790 static void *si_create_dsa_state(struct pipe_context *ctx,
791 const struct pipe_depth_stencil_alpha_state *state)
792 {
793 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
794 struct si_pm4_state *pm4 = &dsa->pm4;
795 unsigned db_depth_control;
796 uint32_t db_stencil_control = 0;
797
798 if (dsa == NULL) {
799 return NULL;
800 }
801
802 dsa->valuemask[0] = state->stencil[0].valuemask;
803 dsa->valuemask[1] = state->stencil[1].valuemask;
804 dsa->writemask[0] = state->stencil[0].writemask;
805 dsa->writemask[1] = state->stencil[1].writemask;
806
807 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
808 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
809 S_028800_ZFUNC(state->depth.func);
810
811 /* stencil */
812 if (state->stencil[0].enabled) {
813 db_depth_control |= S_028800_STENCIL_ENABLE(1);
814 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
815 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
816 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
817 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
818
819 if (state->stencil[1].enabled) {
820 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
821 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
822 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
823 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
824 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
825 }
826 }
827
828 /* alpha */
829 if (state->alpha.enabled) {
830 dsa->alpha_func = state->alpha.func;
831
832 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
833 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
834 } else {
835 dsa->alpha_func = PIPE_FUNC_ALWAYS;
836 }
837
838 /* misc */
839 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
840 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
841
842 return dsa;
843 }
844
845 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
846 {
847 struct si_context *sctx = (struct si_context *)ctx;
848 struct si_state_dsa *dsa = state;
849
850 if (state == NULL)
851 return;
852
853 si_pm4_bind_state(sctx, dsa, dsa);
854 si_update_dsa_stencil_ref(sctx);
855 }
856
857 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
858 {
859 struct si_context *sctx = (struct si_context *)ctx;
860 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
861 }
862
863 static void *si_create_db_flush_dsa(struct si_context *sctx)
864 {
865 struct pipe_depth_stencil_alpha_state dsa = {};
866
867 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
868 }
869
870 /* DB RENDER STATE */
871
872 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
873 {
874 struct si_context *sctx = (struct si_context*)ctx;
875
876 sctx->db_render_state.dirty = true;
877 }
878
879 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
880 {
881 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
882 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
883 unsigned db_shader_control;
884
885 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
886
887 /* DB_RENDER_CONTROL */
888 if (sctx->dbcb_depth_copy_enabled ||
889 sctx->dbcb_stencil_copy_enabled) {
890 radeon_emit(cs,
891 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
892 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
893 S_028000_COPY_CENTROID(1) |
894 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
895 } else if (sctx->db_inplace_flush_enabled) {
896 radeon_emit(cs,
897 S_028000_DEPTH_COMPRESS_DISABLE(1) |
898 S_028000_STENCIL_COMPRESS_DISABLE(1));
899 } else if (sctx->db_depth_clear) {
900 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
901 } else {
902 radeon_emit(cs, 0);
903 }
904
905 /* DB_COUNT_CONTROL (occlusion queries) */
906 if (sctx->b.num_occlusion_queries > 0) {
907 if (sctx->b.chip_class >= CIK) {
908 radeon_emit(cs,
909 S_028004_PERFECT_ZPASS_COUNTS(1) |
910 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
911 S_028004_ZPASS_ENABLE(1) |
912 S_028004_SLICE_EVEN_ENABLE(1) |
913 S_028004_SLICE_ODD_ENABLE(1));
914 } else {
915 radeon_emit(cs,
916 S_028004_PERFECT_ZPASS_COUNTS(1) |
917 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
918 }
919 } else {
920 /* Disable occlusion queries. */
921 if (sctx->b.chip_class >= CIK) {
922 radeon_emit(cs, 0);
923 } else {
924 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
925 }
926 }
927
928 /* DB_RENDER_OVERRIDE2 */
929 if (sctx->db_depth_disable_expclear) {
930 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
931 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
932 } else {
933 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
934 }
935
936 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
937 sctx->ps_db_shader_control;
938
939 /* Bug workaround for smoothing (overrasterization) on SI. */
940 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
941 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
942 else
943 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
944
945 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
946 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
947 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
948
949 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
950 db_shader_control);
951 }
952
953 /*
954 * format translation
955 */
956 static uint32_t si_translate_colorformat(enum pipe_format format)
957 {
958 const struct util_format_description *desc = util_format_description(format);
959
960 #define HAS_SIZE(x,y,z,w) \
961 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
962 desc->channel[2].size == (z) && desc->channel[3].size == (w))
963
964 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
965 return V_028C70_COLOR_10_11_11;
966
967 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
968 return V_028C70_COLOR_INVALID;
969
970 switch (desc->nr_channels) {
971 case 1:
972 switch (desc->channel[0].size) {
973 case 8:
974 return V_028C70_COLOR_8;
975 case 16:
976 return V_028C70_COLOR_16;
977 case 32:
978 return V_028C70_COLOR_32;
979 }
980 break;
981 case 2:
982 if (desc->channel[0].size == desc->channel[1].size) {
983 switch (desc->channel[0].size) {
984 case 8:
985 return V_028C70_COLOR_8_8;
986 case 16:
987 return V_028C70_COLOR_16_16;
988 case 32:
989 return V_028C70_COLOR_32_32;
990 }
991 } else if (HAS_SIZE(8,24,0,0)) {
992 return V_028C70_COLOR_24_8;
993 } else if (HAS_SIZE(24,8,0,0)) {
994 return V_028C70_COLOR_8_24;
995 }
996 break;
997 case 3:
998 if (HAS_SIZE(5,6,5,0)) {
999 return V_028C70_COLOR_5_6_5;
1000 } else if (HAS_SIZE(32,8,24,0)) {
1001 return V_028C70_COLOR_X24_8_32_FLOAT;
1002 }
1003 break;
1004 case 4:
1005 if (desc->channel[0].size == desc->channel[1].size &&
1006 desc->channel[0].size == desc->channel[2].size &&
1007 desc->channel[0].size == desc->channel[3].size) {
1008 switch (desc->channel[0].size) {
1009 case 4:
1010 return V_028C70_COLOR_4_4_4_4;
1011 case 8:
1012 return V_028C70_COLOR_8_8_8_8;
1013 case 16:
1014 return V_028C70_COLOR_16_16_16_16;
1015 case 32:
1016 return V_028C70_COLOR_32_32_32_32;
1017 }
1018 } else if (HAS_SIZE(5,5,5,1)) {
1019 return V_028C70_COLOR_1_5_5_5;
1020 } else if (HAS_SIZE(10,10,10,2)) {
1021 return V_028C70_COLOR_2_10_10_10;
1022 }
1023 break;
1024 }
1025 return V_028C70_COLOR_INVALID;
1026 }
1027
1028 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1029 {
1030 if (SI_BIG_ENDIAN) {
1031 switch(colorformat) {
1032 /* 8-bit buffers. */
1033 case V_028C70_COLOR_8:
1034 return V_028C70_ENDIAN_NONE;
1035
1036 /* 16-bit buffers. */
1037 case V_028C70_COLOR_5_6_5:
1038 case V_028C70_COLOR_1_5_5_5:
1039 case V_028C70_COLOR_4_4_4_4:
1040 case V_028C70_COLOR_16:
1041 case V_028C70_COLOR_8_8:
1042 return V_028C70_ENDIAN_8IN16;
1043
1044 /* 32-bit buffers. */
1045 case V_028C70_COLOR_8_8_8_8:
1046 case V_028C70_COLOR_2_10_10_10:
1047 case V_028C70_COLOR_8_24:
1048 case V_028C70_COLOR_24_8:
1049 case V_028C70_COLOR_16_16:
1050 return V_028C70_ENDIAN_8IN32;
1051
1052 /* 64-bit buffers. */
1053 case V_028C70_COLOR_16_16_16_16:
1054 return V_028C70_ENDIAN_8IN16;
1055
1056 case V_028C70_COLOR_32_32:
1057 return V_028C70_ENDIAN_8IN32;
1058
1059 /* 128-bit buffers. */
1060 case V_028C70_COLOR_32_32_32_32:
1061 return V_028C70_ENDIAN_8IN32;
1062 default:
1063 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1064 }
1065 } else {
1066 return V_028C70_ENDIAN_NONE;
1067 }
1068 }
1069
1070 /* Returns the size in bits of the widest component of a CB format */
1071 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1072 {
1073 switch(colorformat) {
1074 case V_028C70_COLOR_4_4_4_4:
1075 return 4;
1076
1077 case V_028C70_COLOR_1_5_5_5:
1078 case V_028C70_COLOR_5_5_5_1:
1079 return 5;
1080
1081 case V_028C70_COLOR_5_6_5:
1082 return 6;
1083
1084 case V_028C70_COLOR_8:
1085 case V_028C70_COLOR_8_8:
1086 case V_028C70_COLOR_8_8_8_8:
1087 return 8;
1088
1089 case V_028C70_COLOR_10_10_10_2:
1090 case V_028C70_COLOR_2_10_10_10:
1091 return 10;
1092
1093 case V_028C70_COLOR_10_11_11:
1094 case V_028C70_COLOR_11_11_10:
1095 return 11;
1096
1097 case V_028C70_COLOR_16:
1098 case V_028C70_COLOR_16_16:
1099 case V_028C70_COLOR_16_16_16_16:
1100 return 16;
1101
1102 case V_028C70_COLOR_8_24:
1103 case V_028C70_COLOR_24_8:
1104 return 24;
1105
1106 case V_028C70_COLOR_32:
1107 case V_028C70_COLOR_32_32:
1108 case V_028C70_COLOR_32_32_32_32:
1109 case V_028C70_COLOR_X24_8_32_FLOAT:
1110 return 32;
1111 }
1112
1113 assert(!"Unknown maximum component size");
1114 return 0;
1115 }
1116
1117 static uint32_t si_translate_dbformat(enum pipe_format format)
1118 {
1119 switch (format) {
1120 case PIPE_FORMAT_Z16_UNORM:
1121 return V_028040_Z_16;
1122 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1123 case PIPE_FORMAT_X8Z24_UNORM:
1124 case PIPE_FORMAT_Z24X8_UNORM:
1125 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1126 return V_028040_Z_24; /* deprecated on SI */
1127 case PIPE_FORMAT_Z32_FLOAT:
1128 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1129 return V_028040_Z_32_FLOAT;
1130 default:
1131 return V_028040_Z_INVALID;
1132 }
1133 }
1134
1135 /*
1136 * Texture translation
1137 */
1138
1139 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1140 enum pipe_format format,
1141 const struct util_format_description *desc,
1142 int first_non_void)
1143 {
1144 struct si_screen *sscreen = (struct si_screen*)screen;
1145 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1146 boolean uniform = TRUE;
1147 int i;
1148
1149 /* Colorspace (return non-RGB formats directly). */
1150 switch (desc->colorspace) {
1151 /* Depth stencil formats */
1152 case UTIL_FORMAT_COLORSPACE_ZS:
1153 switch (format) {
1154 case PIPE_FORMAT_Z16_UNORM:
1155 return V_008F14_IMG_DATA_FORMAT_16;
1156 case PIPE_FORMAT_X24S8_UINT:
1157 case PIPE_FORMAT_Z24X8_UNORM:
1158 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1159 return V_008F14_IMG_DATA_FORMAT_8_24;
1160 case PIPE_FORMAT_X8Z24_UNORM:
1161 case PIPE_FORMAT_S8X24_UINT:
1162 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1163 return V_008F14_IMG_DATA_FORMAT_24_8;
1164 case PIPE_FORMAT_S8_UINT:
1165 return V_008F14_IMG_DATA_FORMAT_8;
1166 case PIPE_FORMAT_Z32_FLOAT:
1167 return V_008F14_IMG_DATA_FORMAT_32;
1168 case PIPE_FORMAT_X32_S8X24_UINT:
1169 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1170 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1171 default:
1172 goto out_unknown;
1173 }
1174
1175 case UTIL_FORMAT_COLORSPACE_YUV:
1176 goto out_unknown; /* TODO */
1177
1178 case UTIL_FORMAT_COLORSPACE_SRGB:
1179 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1180 goto out_unknown;
1181 break;
1182
1183 default:
1184 break;
1185 }
1186
1187 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1188 if (!enable_s3tc)
1189 goto out_unknown;
1190
1191 switch (format) {
1192 case PIPE_FORMAT_RGTC1_SNORM:
1193 case PIPE_FORMAT_LATC1_SNORM:
1194 case PIPE_FORMAT_RGTC1_UNORM:
1195 case PIPE_FORMAT_LATC1_UNORM:
1196 return V_008F14_IMG_DATA_FORMAT_BC4;
1197 case PIPE_FORMAT_RGTC2_SNORM:
1198 case PIPE_FORMAT_LATC2_SNORM:
1199 case PIPE_FORMAT_RGTC2_UNORM:
1200 case PIPE_FORMAT_LATC2_UNORM:
1201 return V_008F14_IMG_DATA_FORMAT_BC5;
1202 default:
1203 goto out_unknown;
1204 }
1205 }
1206
1207 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1208 if (!enable_s3tc)
1209 goto out_unknown;
1210
1211 switch (format) {
1212 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1213 case PIPE_FORMAT_BPTC_SRGBA:
1214 return V_008F14_IMG_DATA_FORMAT_BC7;
1215 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1216 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1217 return V_008F14_IMG_DATA_FORMAT_BC6;
1218 default:
1219 goto out_unknown;
1220 }
1221 }
1222
1223 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1224 switch (format) {
1225 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1226 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1227 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1228 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1229 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1230 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1231 default:
1232 goto out_unknown;
1233 }
1234 }
1235
1236 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1237
1238 if (!enable_s3tc)
1239 goto out_unknown;
1240
1241 if (!util_format_s3tc_enabled) {
1242 goto out_unknown;
1243 }
1244
1245 switch (format) {
1246 case PIPE_FORMAT_DXT1_RGB:
1247 case PIPE_FORMAT_DXT1_RGBA:
1248 case PIPE_FORMAT_DXT1_SRGB:
1249 case PIPE_FORMAT_DXT1_SRGBA:
1250 return V_008F14_IMG_DATA_FORMAT_BC1;
1251 case PIPE_FORMAT_DXT3_RGBA:
1252 case PIPE_FORMAT_DXT3_SRGBA:
1253 return V_008F14_IMG_DATA_FORMAT_BC2;
1254 case PIPE_FORMAT_DXT5_RGBA:
1255 case PIPE_FORMAT_DXT5_SRGBA:
1256 return V_008F14_IMG_DATA_FORMAT_BC3;
1257 default:
1258 goto out_unknown;
1259 }
1260 }
1261
1262 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1263 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1264 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1265 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1266 }
1267
1268 /* R8G8Bx_SNORM - TODO CxV8U8 */
1269
1270 /* See whether the components are of the same size. */
1271 for (i = 1; i < desc->nr_channels; i++) {
1272 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1273 }
1274
1275 /* Non-uniform formats. */
1276 if (!uniform) {
1277 switch(desc->nr_channels) {
1278 case 3:
1279 if (desc->channel[0].size == 5 &&
1280 desc->channel[1].size == 6 &&
1281 desc->channel[2].size == 5) {
1282 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1283 }
1284 goto out_unknown;
1285 case 4:
1286 if (desc->channel[0].size == 5 &&
1287 desc->channel[1].size == 5 &&
1288 desc->channel[2].size == 5 &&
1289 desc->channel[3].size == 1) {
1290 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1291 }
1292 if (desc->channel[0].size == 10 &&
1293 desc->channel[1].size == 10 &&
1294 desc->channel[2].size == 10 &&
1295 desc->channel[3].size == 2) {
1296 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1297 }
1298 goto out_unknown;
1299 }
1300 goto out_unknown;
1301 }
1302
1303 if (first_non_void < 0 || first_non_void > 3)
1304 goto out_unknown;
1305
1306 /* uniform formats */
1307 switch (desc->channel[first_non_void].size) {
1308 case 4:
1309 switch (desc->nr_channels) {
1310 #if 0 /* Not supported for render targets */
1311 case 2:
1312 return V_008F14_IMG_DATA_FORMAT_4_4;
1313 #endif
1314 case 4:
1315 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1316 }
1317 break;
1318 case 8:
1319 switch (desc->nr_channels) {
1320 case 1:
1321 return V_008F14_IMG_DATA_FORMAT_8;
1322 case 2:
1323 return V_008F14_IMG_DATA_FORMAT_8_8;
1324 case 4:
1325 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1326 }
1327 break;
1328 case 16:
1329 switch (desc->nr_channels) {
1330 case 1:
1331 return V_008F14_IMG_DATA_FORMAT_16;
1332 case 2:
1333 return V_008F14_IMG_DATA_FORMAT_16_16;
1334 case 4:
1335 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1336 }
1337 break;
1338 case 32:
1339 switch (desc->nr_channels) {
1340 case 1:
1341 return V_008F14_IMG_DATA_FORMAT_32;
1342 case 2:
1343 return V_008F14_IMG_DATA_FORMAT_32_32;
1344 #if 0 /* Not supported for render targets */
1345 case 3:
1346 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1347 #endif
1348 case 4:
1349 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1350 }
1351 }
1352
1353 out_unknown:
1354 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1355 return ~0;
1356 }
1357
1358 static unsigned si_tex_wrap(unsigned wrap)
1359 {
1360 switch (wrap) {
1361 default:
1362 case PIPE_TEX_WRAP_REPEAT:
1363 return V_008F30_SQ_TEX_WRAP;
1364 case PIPE_TEX_WRAP_CLAMP:
1365 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1366 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1367 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1368 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1369 return V_008F30_SQ_TEX_CLAMP_BORDER;
1370 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1371 return V_008F30_SQ_TEX_MIRROR;
1372 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1373 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1374 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1375 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1376 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1377 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1378 }
1379 }
1380
1381 static unsigned si_tex_filter(unsigned filter)
1382 {
1383 switch (filter) {
1384 default:
1385 case PIPE_TEX_FILTER_NEAREST:
1386 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1387 case PIPE_TEX_FILTER_LINEAR:
1388 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1389 }
1390 }
1391
1392 static unsigned si_tex_mipfilter(unsigned filter)
1393 {
1394 switch (filter) {
1395 case PIPE_TEX_MIPFILTER_NEAREST:
1396 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1397 case PIPE_TEX_MIPFILTER_LINEAR:
1398 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1399 default:
1400 case PIPE_TEX_MIPFILTER_NONE:
1401 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1402 }
1403 }
1404
1405 static unsigned si_tex_compare(unsigned compare)
1406 {
1407 switch (compare) {
1408 default:
1409 case PIPE_FUNC_NEVER:
1410 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1411 case PIPE_FUNC_LESS:
1412 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1413 case PIPE_FUNC_EQUAL:
1414 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1415 case PIPE_FUNC_LEQUAL:
1416 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1417 case PIPE_FUNC_GREATER:
1418 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1419 case PIPE_FUNC_NOTEQUAL:
1420 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1421 case PIPE_FUNC_GEQUAL:
1422 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1423 case PIPE_FUNC_ALWAYS:
1424 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1425 }
1426 }
1427
1428 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1429 {
1430 switch (dim) {
1431 default:
1432 case PIPE_TEXTURE_1D:
1433 return V_008F1C_SQ_RSRC_IMG_1D;
1434 case PIPE_TEXTURE_1D_ARRAY:
1435 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1436 case PIPE_TEXTURE_2D:
1437 case PIPE_TEXTURE_RECT:
1438 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1439 V_008F1C_SQ_RSRC_IMG_2D;
1440 case PIPE_TEXTURE_2D_ARRAY:
1441 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1442 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1443 case PIPE_TEXTURE_3D:
1444 return V_008F1C_SQ_RSRC_IMG_3D;
1445 case PIPE_TEXTURE_CUBE:
1446 case PIPE_TEXTURE_CUBE_ARRAY:
1447 return V_008F1C_SQ_RSRC_IMG_CUBE;
1448 }
1449 }
1450
1451 /*
1452 * Format support testing
1453 */
1454
1455 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1456 {
1457 return si_translate_texformat(screen, format, util_format_description(format),
1458 util_format_get_first_non_void_channel(format)) != ~0U;
1459 }
1460
1461 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1462 const struct util_format_description *desc,
1463 int first_non_void)
1464 {
1465 unsigned type = desc->channel[first_non_void].type;
1466 int i;
1467
1468 if (type == UTIL_FORMAT_TYPE_FIXED)
1469 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1470
1471 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1472 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1473
1474 if (desc->nr_channels == 4 &&
1475 desc->channel[0].size == 10 &&
1476 desc->channel[1].size == 10 &&
1477 desc->channel[2].size == 10 &&
1478 desc->channel[3].size == 2)
1479 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1480
1481 /* See whether the components are of the same size. */
1482 for (i = 0; i < desc->nr_channels; i++) {
1483 if (desc->channel[first_non_void].size != desc->channel[i].size)
1484 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1485 }
1486
1487 switch (desc->channel[first_non_void].size) {
1488 case 8:
1489 switch (desc->nr_channels) {
1490 case 1:
1491 return V_008F0C_BUF_DATA_FORMAT_8;
1492 case 2:
1493 return V_008F0C_BUF_DATA_FORMAT_8_8;
1494 case 3:
1495 case 4:
1496 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1497 }
1498 break;
1499 case 16:
1500 switch (desc->nr_channels) {
1501 case 1:
1502 return V_008F0C_BUF_DATA_FORMAT_16;
1503 case 2:
1504 return V_008F0C_BUF_DATA_FORMAT_16_16;
1505 case 3:
1506 case 4:
1507 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1508 }
1509 break;
1510 case 32:
1511 /* From the Southern Islands ISA documentation about MTBUF:
1512 * 'Memory reads of data in memory that is 32 or 64 bits do not
1513 * undergo any format conversion.'
1514 */
1515 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1516 !desc->channel[first_non_void].pure_integer)
1517 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1518
1519 switch (desc->nr_channels) {
1520 case 1:
1521 return V_008F0C_BUF_DATA_FORMAT_32;
1522 case 2:
1523 return V_008F0C_BUF_DATA_FORMAT_32_32;
1524 case 3:
1525 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1526 case 4:
1527 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1528 }
1529 break;
1530 }
1531
1532 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1533 }
1534
1535 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1536 const struct util_format_description *desc,
1537 int first_non_void)
1538 {
1539 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1540 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1541
1542 switch (desc->channel[first_non_void].type) {
1543 case UTIL_FORMAT_TYPE_SIGNED:
1544 if (desc->channel[first_non_void].normalized)
1545 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1546 else if (desc->channel[first_non_void].pure_integer)
1547 return V_008F0C_BUF_NUM_FORMAT_SINT;
1548 else
1549 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1550 break;
1551 case UTIL_FORMAT_TYPE_UNSIGNED:
1552 if (desc->channel[first_non_void].normalized)
1553 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1554 else if (desc->channel[first_non_void].pure_integer)
1555 return V_008F0C_BUF_NUM_FORMAT_UINT;
1556 else
1557 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1558 break;
1559 case UTIL_FORMAT_TYPE_FLOAT:
1560 default:
1561 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1562 }
1563 }
1564
1565 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1566 {
1567 const struct util_format_description *desc;
1568 int first_non_void;
1569 unsigned data_format;
1570
1571 desc = util_format_description(format);
1572 first_non_void = util_format_get_first_non_void_channel(format);
1573 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1574 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1575 }
1576
1577 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1578 {
1579 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1580 r600_translate_colorswap(format) != ~0U;
1581 }
1582
1583 static bool si_is_zs_format_supported(enum pipe_format format)
1584 {
1585 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1586 }
1587
1588 boolean si_is_format_supported(struct pipe_screen *screen,
1589 enum pipe_format format,
1590 enum pipe_texture_target target,
1591 unsigned sample_count,
1592 unsigned usage)
1593 {
1594 struct si_screen *sscreen = (struct si_screen *)screen;
1595 unsigned retval = 0;
1596
1597 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1598 R600_ERR("r600: unsupported texture type %d\n", target);
1599 return FALSE;
1600 }
1601
1602 if (!util_format_is_supported(format, usage))
1603 return FALSE;
1604
1605 if (sample_count > 1) {
1606 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1607 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1608 return FALSE;
1609
1610 switch (sample_count) {
1611 case 2:
1612 case 4:
1613 case 8:
1614 break;
1615 default:
1616 return FALSE;
1617 }
1618 }
1619
1620 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1621 if (target == PIPE_BUFFER) {
1622 if (si_is_vertex_format_supported(screen, format))
1623 retval |= PIPE_BIND_SAMPLER_VIEW;
1624 } else {
1625 if (si_is_sampler_format_supported(screen, format))
1626 retval |= PIPE_BIND_SAMPLER_VIEW;
1627 }
1628 }
1629
1630 if ((usage & (PIPE_BIND_RENDER_TARGET |
1631 PIPE_BIND_DISPLAY_TARGET |
1632 PIPE_BIND_SCANOUT |
1633 PIPE_BIND_SHARED |
1634 PIPE_BIND_BLENDABLE)) &&
1635 si_is_colorbuffer_format_supported(format)) {
1636 retval |= usage &
1637 (PIPE_BIND_RENDER_TARGET |
1638 PIPE_BIND_DISPLAY_TARGET |
1639 PIPE_BIND_SCANOUT |
1640 PIPE_BIND_SHARED);
1641 if (!util_format_is_pure_integer(format) &&
1642 !util_format_is_depth_or_stencil(format))
1643 retval |= usage & PIPE_BIND_BLENDABLE;
1644 }
1645
1646 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1647 si_is_zs_format_supported(format)) {
1648 retval |= PIPE_BIND_DEPTH_STENCIL;
1649 }
1650
1651 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1652 si_is_vertex_format_supported(screen, format)) {
1653 retval |= PIPE_BIND_VERTEX_BUFFER;
1654 }
1655
1656 if (usage & PIPE_BIND_TRANSFER_READ)
1657 retval |= PIPE_BIND_TRANSFER_READ;
1658 if (usage & PIPE_BIND_TRANSFER_WRITE)
1659 retval |= PIPE_BIND_TRANSFER_WRITE;
1660
1661 return retval == usage;
1662 }
1663
1664 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1665 {
1666 unsigned tile_mode_index = 0;
1667
1668 if (stencil) {
1669 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1670 } else {
1671 tile_mode_index = rtex->surface.tiling_index[level];
1672 }
1673 return tile_mode_index;
1674 }
1675
1676 /*
1677 * framebuffer handling
1678 */
1679
1680 static void si_initialize_color_surface(struct si_context *sctx,
1681 struct r600_surface *surf)
1682 {
1683 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1684 unsigned level = surf->base.u.tex.level;
1685 uint64_t offset = rtex->surface.level[level].offset;
1686 unsigned pitch, slice;
1687 unsigned color_info, color_attrib, color_pitch, color_view;
1688 unsigned tile_mode_index;
1689 unsigned format, swap, ntype, endian;
1690 const struct util_format_description *desc;
1691 int i;
1692 unsigned blend_clamp = 0, blend_bypass = 0;
1693 unsigned max_comp_size;
1694
1695 /* Layered rendering doesn't work with LINEAR_GENERAL.
1696 * (LINEAR_ALIGNED and others work) */
1697 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1698 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1699 offset += rtex->surface.level[level].slice_size *
1700 surf->base.u.tex.first_layer;
1701 color_view = 0;
1702 } else {
1703 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1704 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1705 }
1706
1707 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1708 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1709 if (slice) {
1710 slice = slice - 1;
1711 }
1712
1713 tile_mode_index = si_tile_mode_index(rtex, level, false);
1714
1715 desc = util_format_description(surf->base.format);
1716 for (i = 0; i < 4; i++) {
1717 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1718 break;
1719 }
1720 }
1721 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1722 ntype = V_028C70_NUMBER_FLOAT;
1723 } else {
1724 ntype = V_028C70_NUMBER_UNORM;
1725 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1726 ntype = V_028C70_NUMBER_SRGB;
1727 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1728 if (desc->channel[i].pure_integer) {
1729 ntype = V_028C70_NUMBER_SINT;
1730 } else {
1731 assert(desc->channel[i].normalized);
1732 ntype = V_028C70_NUMBER_SNORM;
1733 }
1734 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1735 if (desc->channel[i].pure_integer) {
1736 ntype = V_028C70_NUMBER_UINT;
1737 } else {
1738 assert(desc->channel[i].normalized);
1739 ntype = V_028C70_NUMBER_UNORM;
1740 }
1741 }
1742 }
1743
1744 format = si_translate_colorformat(surf->base.format);
1745 if (format == V_028C70_COLOR_INVALID) {
1746 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1747 }
1748 assert(format != V_028C70_COLOR_INVALID);
1749 swap = r600_translate_colorswap(surf->base.format);
1750 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1751 endian = V_028C70_ENDIAN_NONE;
1752 } else {
1753 endian = si_colorformat_endian_swap(format);
1754 }
1755
1756 /* blend clamp should be set for all NORM/SRGB types */
1757 if (ntype == V_028C70_NUMBER_UNORM ||
1758 ntype == V_028C70_NUMBER_SNORM ||
1759 ntype == V_028C70_NUMBER_SRGB)
1760 blend_clamp = 1;
1761
1762 /* set blend bypass according to docs if SINT/UINT or
1763 8/24 COLOR variants */
1764 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1765 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1766 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1767 blend_clamp = 0;
1768 blend_bypass = 1;
1769 }
1770
1771 color_info = S_028C70_FORMAT(format) |
1772 S_028C70_COMP_SWAP(swap) |
1773 S_028C70_BLEND_CLAMP(blend_clamp) |
1774 S_028C70_BLEND_BYPASS(blend_bypass) |
1775 S_028C70_NUMBER_TYPE(ntype) |
1776 S_028C70_ENDIAN(endian);
1777
1778 color_pitch = S_028C64_TILE_MAX(pitch);
1779
1780 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1781 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1782
1783 if (rtex->resource.b.b.nr_samples > 1) {
1784 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1785
1786 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1787 S_028C74_NUM_FRAGMENTS(log_samples);
1788
1789 if (rtex->fmask.size) {
1790 color_info |= S_028C70_COMPRESSION(1);
1791 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1792
1793 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1794
1795 if (sctx->b.chip_class == SI) {
1796 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1797 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1798 }
1799 if (sctx->b.chip_class >= CIK) {
1800 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1801 }
1802 }
1803 }
1804
1805 offset += rtex->resource.gpu_address;
1806
1807 surf->cb_color_base = offset >> 8;
1808 surf->cb_color_pitch = color_pitch;
1809 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1810 surf->cb_color_view = color_view;
1811 surf->cb_color_info = color_info;
1812 surf->cb_color_attrib = color_attrib;
1813
1814 if (rtex->fmask.size) {
1815 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1816 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1817 } else {
1818 /* This must be set for fast clear to work without FMASK. */
1819 surf->cb_color_fmask = surf->cb_color_base;
1820 surf->cb_color_fmask_slice = surf->cb_color_slice;
1821 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1822
1823 if (sctx->b.chip_class == SI) {
1824 unsigned bankh = util_logbase2(rtex->surface.bankh);
1825 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1826 }
1827
1828 if (sctx->b.chip_class >= CIK) {
1829 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1830 }
1831 }
1832
1833 /* Determine pixel shader export format */
1834 max_comp_size = si_colorformat_max_comp_size(format);
1835 if (ntype == V_028C70_NUMBER_SRGB ||
1836 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1837 max_comp_size <= 10) ||
1838 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1839 surf->export_16bpc = true;
1840 }
1841
1842 surf->color_initialized = true;
1843 }
1844
1845 static void si_init_depth_surface(struct si_context *sctx,
1846 struct r600_surface *surf)
1847 {
1848 struct si_screen *sscreen = sctx->screen;
1849 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1850 unsigned level = surf->base.u.tex.level;
1851 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1852 unsigned format, tile_mode_index, array_mode;
1853 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1854 uint32_t z_info, s_info, db_depth_info;
1855 uint64_t z_offs, s_offs;
1856 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1857
1858 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1859 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1860 case PIPE_FORMAT_X8Z24_UNORM:
1861 case PIPE_FORMAT_Z24X8_UNORM:
1862 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1863 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1864 break;
1865 case PIPE_FORMAT_Z32_FLOAT:
1866 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1867 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1868 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1869 break;
1870 case PIPE_FORMAT_Z16_UNORM:
1871 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1872 break;
1873 default:
1874 assert(0);
1875 }
1876
1877 format = si_translate_dbformat(rtex->resource.b.b.format);
1878
1879 if (format == V_028040_Z_INVALID) {
1880 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1881 }
1882 assert(format != V_028040_Z_INVALID);
1883
1884 s_offs = z_offs = rtex->resource.gpu_address;
1885 z_offs += rtex->surface.level[level].offset;
1886 s_offs += rtex->surface.stencil_level[level].offset;
1887
1888 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1889
1890 z_info = S_028040_FORMAT(format);
1891 if (rtex->resource.b.b.nr_samples > 1) {
1892 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1893 }
1894
1895 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1896 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1897 else
1898 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1899
1900 if (sctx->b.chip_class >= CIK) {
1901 switch (rtex->surface.level[level].mode) {
1902 case RADEON_SURF_MODE_2D:
1903 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1904 break;
1905 case RADEON_SURF_MODE_1D:
1906 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1907 case RADEON_SURF_MODE_LINEAR:
1908 default:
1909 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1910 break;
1911 }
1912 tile_split = rtex->surface.tile_split;
1913 stile_split = rtex->surface.stencil_tile_split;
1914 macro_aspect = rtex->surface.mtilea;
1915 bankw = rtex->surface.bankw;
1916 bankh = rtex->surface.bankh;
1917 tile_split = cik_tile_split(tile_split);
1918 stile_split = cik_tile_split(stile_split);
1919 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1920 bankw = cik_bank_wh(bankw);
1921 bankh = cik_bank_wh(bankh);
1922 nbanks = si_num_banks(sscreen, rtex);
1923 tile_mode_index = si_tile_mode_index(rtex, level, false);
1924 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1925
1926 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1927 S_02803C_PIPE_CONFIG(pipe_config) |
1928 S_02803C_BANK_WIDTH(bankw) |
1929 S_02803C_BANK_HEIGHT(bankh) |
1930 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1931 S_02803C_NUM_BANKS(nbanks);
1932 z_info |= S_028040_TILE_SPLIT(tile_split);
1933 s_info |= S_028044_TILE_SPLIT(stile_split);
1934 } else {
1935 tile_mode_index = si_tile_mode_index(rtex, level, false);
1936 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1937 tile_mode_index = si_tile_mode_index(rtex, level, true);
1938 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1939 }
1940
1941 /* HiZ aka depth buffer htile */
1942 /* use htile only for first level */
1943 if (rtex->htile_buffer && !level) {
1944 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1945 S_028040_ALLOW_EXPCLEAR(1);
1946
1947 /* Use all of the htile_buffer for depth, because we don't
1948 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1949 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1950
1951 uint64_t va = rtex->htile_buffer->gpu_address;
1952 db_htile_data_base = va >> 8;
1953 db_htile_surface = S_028ABC_FULL_CACHE(1);
1954 } else {
1955 db_htile_data_base = 0;
1956 db_htile_surface = 0;
1957 }
1958
1959 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1960
1961 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1962 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1963 surf->db_htile_data_base = db_htile_data_base;
1964 surf->db_depth_info = db_depth_info;
1965 surf->db_z_info = z_info;
1966 surf->db_stencil_info = s_info;
1967 surf->db_depth_base = z_offs >> 8;
1968 surf->db_stencil_base = s_offs >> 8;
1969 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1970 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1971 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1972 levelinfo->nblk_y) / 64 - 1);
1973 surf->db_htile_surface = db_htile_surface;
1974 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1975
1976 surf->depth_initialized = true;
1977 }
1978
1979 static void si_set_framebuffer_state(struct pipe_context *ctx,
1980 const struct pipe_framebuffer_state *state)
1981 {
1982 struct si_context *sctx = (struct si_context *)ctx;
1983 struct pipe_constant_buffer constbuf = {0};
1984 struct r600_surface *surf = NULL;
1985 struct r600_texture *rtex;
1986 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
1987 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
1988 int i;
1989
1990 /* Only flush TC when changing the framebuffer state, because
1991 * the only client not using TC that can change textures is
1992 * the framebuffer.
1993 *
1994 * Flush all CB and DB caches here because all buffers can be used
1995 * for write by both TC (with shader image stores) and CB/DB.
1996 */
1997 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
1998 SI_CONTEXT_INV_TC_L2 |
1999 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2000
2001 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2002
2003 sctx->framebuffer.export_16bpc = 0;
2004 sctx->framebuffer.compressed_cb_mask = 0;
2005 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2006 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2007 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2008 util_format_is_pure_integer(state->cbufs[0]->format);
2009
2010 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2011 sctx->db_render_state.dirty = true;
2012
2013 for (i = 0; i < state->nr_cbufs; i++) {
2014 if (!state->cbufs[i])
2015 continue;
2016
2017 surf = (struct r600_surface*)state->cbufs[i];
2018 rtex = (struct r600_texture*)surf->base.texture;
2019
2020 if (!surf->color_initialized) {
2021 si_initialize_color_surface(sctx, surf);
2022 }
2023
2024 if (surf->export_16bpc) {
2025 sctx->framebuffer.export_16bpc |= 1 << i;
2026 }
2027
2028 if (rtex->fmask.size && rtex->cmask.size) {
2029 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2030 }
2031 }
2032 /* Set the 16BPC export for possible dual-src blending. */
2033 if (i == 1 && surf && surf->export_16bpc) {
2034 sctx->framebuffer.export_16bpc |= 1 << 1;
2035 }
2036
2037 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2038
2039 if (state->zsbuf) {
2040 surf = (struct r600_surface*)state->zsbuf;
2041
2042 if (!surf->depth_initialized) {
2043 si_init_depth_surface(sctx, surf);
2044 }
2045 }
2046
2047 si_update_fb_rs_state(sctx);
2048 si_update_fb_blend_state(sctx);
2049
2050 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2051 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2052 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2053 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2054 sctx->framebuffer.atom.dirty = true;
2055
2056 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2057 sctx->msaa_config.dirty = true;
2058 sctx->db_render_state.dirty = true;
2059
2060 /* Set sample locations as fragment shader constants. */
2061 switch (sctx->framebuffer.nr_samples) {
2062 case 1:
2063 constbuf.user_buffer = sctx->b.sample_locations_1x;
2064 break;
2065 case 2:
2066 constbuf.user_buffer = sctx->b.sample_locations_2x;
2067 break;
2068 case 4:
2069 constbuf.user_buffer = sctx->b.sample_locations_4x;
2070 break;
2071 case 8:
2072 constbuf.user_buffer = sctx->b.sample_locations_8x;
2073 break;
2074 case 16:
2075 constbuf.user_buffer = sctx->b.sample_locations_16x;
2076 break;
2077 default:
2078 assert(0);
2079 }
2080 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2081 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2082 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2083
2084 /* Smoothing (only possible with nr_samples == 1) uses the same
2085 * sample locations as the MSAA it simulates.
2086 *
2087 * Therefore, don't update the sample locations when
2088 * transitioning from no AA to smoothing-equivalent AA, and
2089 * vice versa.
2090 */
2091 if ((sctx->framebuffer.nr_samples != 1 ||
2092 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2093 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2094 old_nr_samples != 1))
2095 sctx->msaa_sample_locs.dirty = true;
2096 }
2097 }
2098
2099 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2100 {
2101 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2102 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2103 unsigned i, nr_cbufs = state->nr_cbufs;
2104 struct r600_texture *tex = NULL;
2105 struct r600_surface *cb = NULL;
2106
2107 /* Colorbuffers. */
2108 for (i = 0; i < nr_cbufs; i++) {
2109 cb = (struct r600_surface*)state->cbufs[i];
2110 if (!cb) {
2111 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2112 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2113 continue;
2114 }
2115
2116 tex = (struct r600_texture *)cb->base.texture;
2117 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2118 &tex->resource, RADEON_USAGE_READWRITE,
2119 tex->surface.nsamples > 1 ?
2120 RADEON_PRIO_COLOR_BUFFER_MSAA :
2121 RADEON_PRIO_COLOR_BUFFER);
2122
2123 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2124 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2125 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2126 RADEON_PRIO_COLOR_META);
2127 }
2128
2129 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2130 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2131 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2132 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2133 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2134 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2135 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2136 radeon_emit(cs, 0); /* R_028C78 unused */
2137 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2138 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2139 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2140 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2141 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2142 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2143 }
2144 /* set CB_COLOR1_INFO for possible dual-src blending */
2145 if (i == 1 && state->cbufs[0]) {
2146 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2147 cb->cb_color_info | tex->cb_color_info);
2148 i++;
2149 }
2150 for (; i < 8 ; i++) {
2151 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2152 }
2153
2154 /* ZS buffer. */
2155 if (state->zsbuf) {
2156 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2157 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2158
2159 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2160 &rtex->resource, RADEON_USAGE_READWRITE,
2161 zb->base.texture->nr_samples > 1 ?
2162 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2163 RADEON_PRIO_DEPTH_BUFFER);
2164
2165 if (zb->db_htile_data_base) {
2166 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2167 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2168 RADEON_PRIO_DEPTH_META);
2169 }
2170
2171 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2172 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2173
2174 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2175 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2176 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2177 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2178 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2179 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2180 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2181 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2182 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2183 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2184 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2185
2186 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2187 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2188 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2189 zb->pa_su_poly_offset_db_fmt_cntl);
2190 } else {
2191 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2192 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2193 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2194 }
2195
2196 /* Framebuffer dimensions. */
2197 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2198 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2199 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2200 }
2201
2202 static void si_emit_msaa_sample_locs(struct r600_common_context *rctx,
2203 struct r600_atom *atom)
2204 {
2205 struct si_context *sctx = (struct si_context *)rctx;
2206 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2207 unsigned nr_samples = sctx->framebuffer.nr_samples;
2208
2209 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2210 SI_NUM_SMOOTH_AA_SAMPLES);
2211 }
2212
2213 const struct r600_atom si_atom_msaa_sample_locs = { si_emit_msaa_sample_locs, 18 }; /* number of CS dwords */
2214
2215 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2216 {
2217 struct si_context *sctx = (struct si_context *)rctx;
2218 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2219
2220 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2221 sctx->ps_iter_samples,
2222 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2223 }
2224
2225 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2226
2227 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2228 {
2229 struct si_context *sctx = (struct si_context *)ctx;
2230
2231 if (sctx->ps_iter_samples == min_samples)
2232 return;
2233
2234 sctx->ps_iter_samples = min_samples;
2235
2236 if (sctx->framebuffer.nr_samples > 1)
2237 sctx->msaa_config.dirty = true;
2238 }
2239
2240 /*
2241 * Samplers
2242 */
2243
2244 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2245 struct pipe_resource *texture,
2246 const struct pipe_sampler_view *state)
2247 {
2248 struct si_context *sctx = (struct si_context*)ctx;
2249 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2250 struct r600_texture *tmp = (struct r600_texture*)texture;
2251 const struct util_format_description *desc;
2252 unsigned format, num_format;
2253 uint32_t pitch = 0;
2254 unsigned char state_swizzle[4], swizzle[4];
2255 unsigned height, depth, width;
2256 enum pipe_format pipe_format = state->format;
2257 struct radeon_surf_level *surflevel;
2258 int first_non_void;
2259 uint64_t va;
2260
2261 if (view == NULL)
2262 return NULL;
2263
2264 /* initialize base object */
2265 view->base = *state;
2266 view->base.texture = NULL;
2267 view->base.reference.count = 1;
2268 view->base.context = ctx;
2269
2270 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2271 if (!texture) {
2272 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2273 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2274 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2275 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2276 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2277 return &view->base;
2278 }
2279
2280 pipe_resource_reference(&view->base.texture, texture);
2281 view->resource = &tmp->resource;
2282
2283 /* Buffer resource. */
2284 if (texture->target == PIPE_BUFFER) {
2285 unsigned stride;
2286
2287 desc = util_format_description(state->format);
2288 first_non_void = util_format_get_first_non_void_channel(state->format);
2289 stride = desc->block.bits / 8;
2290 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2291 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2292 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2293
2294 view->state[4] = va;
2295 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2296 S_008F04_STRIDE(stride);
2297 view->state[6] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2298 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2299 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2300 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2301 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2302 S_008F0C_NUM_FORMAT(num_format) |
2303 S_008F0C_DATA_FORMAT(format);
2304
2305 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2306 return &view->base;
2307 }
2308
2309 state_swizzle[0] = state->swizzle_r;
2310 state_swizzle[1] = state->swizzle_g;
2311 state_swizzle[2] = state->swizzle_b;
2312 state_swizzle[3] = state->swizzle_a;
2313
2314 surflevel = tmp->surface.level;
2315
2316 /* Texturing with separate depth and stencil. */
2317 if (tmp->is_depth && !tmp->is_flushing_texture) {
2318 switch (pipe_format) {
2319 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2320 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2321 break;
2322 case PIPE_FORMAT_X8Z24_UNORM:
2323 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2324 /* Z24 is always stored like this. */
2325 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2326 break;
2327 case PIPE_FORMAT_X24S8_UINT:
2328 case PIPE_FORMAT_S8X24_UINT:
2329 case PIPE_FORMAT_X32_S8X24_UINT:
2330 pipe_format = PIPE_FORMAT_S8_UINT;
2331 surflevel = tmp->surface.stencil_level;
2332 break;
2333 default:;
2334 }
2335 }
2336
2337 desc = util_format_description(pipe_format);
2338
2339 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2340 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2341 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2342
2343 switch (pipe_format) {
2344 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2345 case PIPE_FORMAT_X24S8_UINT:
2346 case PIPE_FORMAT_X32_S8X24_UINT:
2347 case PIPE_FORMAT_X8Z24_UNORM:
2348 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2349 break;
2350 default:
2351 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2352 }
2353 } else {
2354 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2355 }
2356
2357 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2358
2359 switch (pipe_format) {
2360 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2361 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2362 break;
2363 default:
2364 if (first_non_void < 0) {
2365 if (util_format_is_compressed(pipe_format)) {
2366 switch (pipe_format) {
2367 case PIPE_FORMAT_DXT1_SRGB:
2368 case PIPE_FORMAT_DXT1_SRGBA:
2369 case PIPE_FORMAT_DXT3_SRGBA:
2370 case PIPE_FORMAT_DXT5_SRGBA:
2371 case PIPE_FORMAT_BPTC_SRGBA:
2372 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2373 break;
2374 case PIPE_FORMAT_RGTC1_SNORM:
2375 case PIPE_FORMAT_LATC1_SNORM:
2376 case PIPE_FORMAT_RGTC2_SNORM:
2377 case PIPE_FORMAT_LATC2_SNORM:
2378 /* implies float, so use SNORM/UNORM to determine
2379 whether data is signed or not */
2380 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2381 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2382 break;
2383 default:
2384 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2385 break;
2386 }
2387 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2388 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2389 } else {
2390 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2391 }
2392 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2393 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2394 } else {
2395 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2396
2397 switch (desc->channel[first_non_void].type) {
2398 case UTIL_FORMAT_TYPE_FLOAT:
2399 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2400 break;
2401 case UTIL_FORMAT_TYPE_SIGNED:
2402 if (desc->channel[first_non_void].normalized)
2403 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2404 else if (desc->channel[first_non_void].pure_integer)
2405 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2406 else
2407 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2408 break;
2409 case UTIL_FORMAT_TYPE_UNSIGNED:
2410 if (desc->channel[first_non_void].normalized)
2411 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2412 else if (desc->channel[first_non_void].pure_integer)
2413 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2414 else
2415 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2416 }
2417 }
2418 }
2419
2420 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2421 if (format == ~0) {
2422 format = 0;
2423 }
2424
2425 /* not supported any more */
2426 //endian = si_colorformat_endian_swap(format);
2427
2428 width = surflevel[0].npix_x;
2429 height = surflevel[0].npix_y;
2430 depth = surflevel[0].npix_z;
2431 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2432
2433 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2434 height = 1;
2435 depth = texture->array_size;
2436 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2437 depth = texture->array_size;
2438 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2439 depth = texture->array_size / 6;
2440
2441 va = tmp->resource.gpu_address + surflevel[0].offset;
2442 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2443
2444 view->state[0] = va >> 8;
2445 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2446 S_008F14_DATA_FORMAT(format) |
2447 S_008F14_NUM_FORMAT(num_format));
2448 view->state[2] = (S_008F18_WIDTH(width - 1) |
2449 S_008F18_HEIGHT(height - 1));
2450 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2451 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2452 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2453 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2454 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2455 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2456 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2457 util_logbase2(texture->nr_samples) :
2458 state->u.tex.last_level - tmp->mipmap_shift) |
2459 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2460 S_008F1C_POW2_PAD(texture->last_level > 0) |
2461 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2462 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2463 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2464 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2465 view->state[6] = 0;
2466 view->state[7] = 0;
2467
2468 /* Initialize the sampler view for FMASK. */
2469 if (tmp->fmask.size) {
2470 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2471 uint32_t fmask_format;
2472
2473 switch (texture->nr_samples) {
2474 case 2:
2475 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2476 break;
2477 case 4:
2478 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2479 break;
2480 case 8:
2481 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2482 break;
2483 default:
2484 assert(0);
2485 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2486 }
2487
2488 view->fmask_state[0] = va >> 8;
2489 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2490 S_008F14_DATA_FORMAT(fmask_format) |
2491 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2492 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2493 S_008F18_HEIGHT(height - 1);
2494 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2495 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2496 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2497 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2498 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2499 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2500 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2501 S_008F20_PITCH(tmp->fmask.pitch - 1);
2502 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2503 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2504 view->fmask_state[6] = 0;
2505 view->fmask_state[7] = 0;
2506 }
2507
2508 return &view->base;
2509 }
2510
2511 static void si_sampler_view_destroy(struct pipe_context *ctx,
2512 struct pipe_sampler_view *state)
2513 {
2514 struct si_sampler_view *view = (struct si_sampler_view *)state;
2515
2516 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2517 LIST_DELINIT(&view->list);
2518
2519 pipe_resource_reference(&state->texture, NULL);
2520 FREE(view);
2521 }
2522
2523 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2524 {
2525 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2526 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2527 (linear_filter &&
2528 (wrap == PIPE_TEX_WRAP_CLAMP ||
2529 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2530 }
2531
2532 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2533 {
2534 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2535 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2536
2537 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2538 state->border_color.ui[2] || state->border_color.ui[3]) &&
2539 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2540 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2541 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2542 }
2543
2544 static void *si_create_sampler_state(struct pipe_context *ctx,
2545 const struct pipe_sampler_state *state)
2546 {
2547 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2548 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2549 unsigned border_color_type;
2550
2551 if (rstate == NULL) {
2552 return NULL;
2553 }
2554
2555 if (sampler_state_needs_border_color(state))
2556 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2557 else
2558 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2559
2560 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2561 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2562 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2563 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2564 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2565 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2566 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2567 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2568 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2569 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2570 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2571 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2572 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2573 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2574
2575 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2576 memcpy(rstate->border_color, state->border_color.ui,
2577 sizeof(rstate->border_color));
2578 }
2579
2580 return rstate;
2581 }
2582
2583 /* Upload border colors and update the pointers in resource descriptors.
2584 * There can only be 4096 border colors per context.
2585 *
2586 * XXX: This is broken if the buffer gets reallocated.
2587 */
2588 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2589 void **states)
2590 {
2591 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2592 uint32_t *border_color_table = NULL;
2593 int i, j;
2594
2595 for (i = 0; i < count; i++) {
2596 if (rstates[i] &&
2597 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2598 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2599 if (!sctx->border_color_table ||
2600 ((sctx->border_color_offset + count - i) &
2601 C_008F3C_BORDER_COLOR_PTR)) {
2602 r600_resource_reference(&sctx->border_color_table, NULL);
2603 sctx->border_color_offset = 0;
2604
2605 sctx->border_color_table =
2606 si_resource_create_custom(&sctx->screen->b.b,
2607 PIPE_USAGE_DYNAMIC,
2608 4096 * 4 * 4);
2609 }
2610
2611 if (!border_color_table) {
2612 border_color_table =
2613 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2614 sctx->b.rings.gfx.cs,
2615 PIPE_TRANSFER_WRITE |
2616 PIPE_TRANSFER_UNSYNCHRONIZED);
2617 }
2618
2619 for (j = 0; j < 4; j++) {
2620 border_color_table[4 * sctx->border_color_offset + j] =
2621 util_le32_to_cpu(rstates[i]->border_color[j]);
2622 }
2623
2624 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2625 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2626 }
2627 }
2628
2629 if (border_color_table) {
2630 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2631
2632 uint64_t va_offset = sctx->border_color_table->gpu_address;
2633
2634 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2635 if (sctx->b.chip_class >= CIK)
2636 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2637 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2638 RADEON_PRIO_SHADER_DATA);
2639 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2640 }
2641 }
2642
2643 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2644 unsigned start, unsigned count,
2645 void **states)
2646 {
2647 struct si_context *sctx = (struct si_context *)ctx;
2648
2649 if (!count || shader >= SI_NUM_SHADERS)
2650 return;
2651
2652 si_set_border_colors(sctx, count, states);
2653 si_set_sampler_descriptors(sctx, shader, start, count, states);
2654 }
2655
2656 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2657 {
2658 struct si_context *sctx = (struct si_context *)ctx;
2659 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2660 struct si_pm4_state *pm4 = &state->pm4;
2661 uint16_t mask = sample_mask;
2662
2663 if (state == NULL)
2664 return;
2665
2666 state->sample_mask = mask;
2667 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2668 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2669
2670 si_pm4_set_state(sctx, sample_mask, state);
2671 }
2672
2673 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2674 {
2675 free(state);
2676 }
2677
2678 /*
2679 * Vertex elements & buffers
2680 */
2681
2682 static void *si_create_vertex_elements(struct pipe_context *ctx,
2683 unsigned count,
2684 const struct pipe_vertex_element *elements)
2685 {
2686 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2687 int i;
2688
2689 assert(count < PIPE_MAX_ATTRIBS);
2690 if (!v)
2691 return NULL;
2692
2693 v->count = count;
2694 for (i = 0; i < count; ++i) {
2695 const struct util_format_description *desc;
2696 unsigned data_format, num_format;
2697 int first_non_void;
2698
2699 desc = util_format_description(elements[i].src_format);
2700 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2701 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2702 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2703
2704 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2705 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2706 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2707 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2708 S_008F0C_NUM_FORMAT(num_format) |
2709 S_008F0C_DATA_FORMAT(data_format);
2710 v->format_size[i] = desc->block.bits / 8;
2711 }
2712 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2713
2714 return v;
2715 }
2716
2717 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2718 {
2719 struct si_context *sctx = (struct si_context *)ctx;
2720 struct si_vertex_element *v = (struct si_vertex_element*)state;
2721
2722 sctx->vertex_elements = v;
2723 sctx->vertex_buffers_dirty = true;
2724 }
2725
2726 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2727 {
2728 struct si_context *sctx = (struct si_context *)ctx;
2729
2730 if (sctx->vertex_elements == state)
2731 sctx->vertex_elements = NULL;
2732 FREE(state);
2733 }
2734
2735 static void si_set_vertex_buffers(struct pipe_context *ctx,
2736 unsigned start_slot, unsigned count,
2737 const struct pipe_vertex_buffer *buffers)
2738 {
2739 struct si_context *sctx = (struct si_context *)ctx;
2740 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2741 int i;
2742
2743 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2744
2745 if (buffers) {
2746 for (i = 0; i < count; i++) {
2747 const struct pipe_vertex_buffer *src = buffers + i;
2748 struct pipe_vertex_buffer *dsti = dst + i;
2749
2750 pipe_resource_reference(&dsti->buffer, src->buffer);
2751 dsti->buffer_offset = src->buffer_offset;
2752 dsti->stride = src->stride;
2753 }
2754 } else {
2755 for (i = 0; i < count; i++) {
2756 pipe_resource_reference(&dst[i].buffer, NULL);
2757 }
2758 }
2759 sctx->vertex_buffers_dirty = true;
2760 }
2761
2762 static void si_set_index_buffer(struct pipe_context *ctx,
2763 const struct pipe_index_buffer *ib)
2764 {
2765 struct si_context *sctx = (struct si_context *)ctx;
2766
2767 if (ib) {
2768 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2769 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2770 } else {
2771 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2772 }
2773 }
2774
2775 /*
2776 * Misc
2777 */
2778 static void si_set_polygon_stipple(struct pipe_context *ctx,
2779 const struct pipe_poly_stipple *state)
2780 {
2781 struct si_context *sctx = (struct si_context *)ctx;
2782 struct pipe_resource *tex;
2783 struct pipe_sampler_view *view;
2784 bool is_zero = true;
2785 bool is_one = true;
2786 int i;
2787
2788 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2789 * the resource is NULL/invalid. Take advantage of this fact and skip
2790 * texture allocation if the stipple pattern is constant.
2791 *
2792 * This is an optimization for the common case when stippling isn't
2793 * used but set_polygon_stipple is still called by st/mesa.
2794 */
2795 for (i = 0; i < Elements(state->stipple); i++) {
2796 is_zero = is_zero && state->stipple[i] == 0;
2797 is_one = is_one && state->stipple[i] == 0xffffffff;
2798 }
2799
2800 if (is_zero || is_one) {
2801 struct pipe_sampler_view templ = {{0}};
2802
2803 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2804 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2805 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2806 /* The pattern should be inverted in the texture. */
2807 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2808
2809 view = ctx->create_sampler_view(ctx, NULL, &templ);
2810 } else {
2811 /* Create a new texture. */
2812 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2813 if (!tex)
2814 return;
2815
2816 view = util_pstipple_create_sampler_view(ctx, tex);
2817 pipe_resource_reference(&tex, NULL);
2818 }
2819
2820 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2821 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2822 pipe_sampler_view_reference(&view, NULL);
2823
2824 /* Bind the sampler state if needed. */
2825 if (!sctx->pstipple_sampler_state) {
2826 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2827 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2828 SI_POLY_STIPPLE_SAMPLER, 1,
2829 &sctx->pstipple_sampler_state);
2830 }
2831 }
2832
2833 static void si_texture_barrier(struct pipe_context *ctx)
2834 {
2835 struct si_context *sctx = (struct si_context *)ctx;
2836
2837 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2838 SI_CONTEXT_INV_TC_L2 |
2839 SI_CONTEXT_FLUSH_AND_INV_CB;
2840 }
2841
2842 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2843 {
2844 struct pipe_blend_state blend;
2845
2846 memset(&blend, 0, sizeof(blend));
2847 blend.independent_blend_enable = true;
2848 blend.rt[0].colormask = 0xf;
2849 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2850 }
2851
2852 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2853 bool include_draw_vbo)
2854 {
2855 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2856 }
2857
2858 void si_init_state_functions(struct si_context *sctx)
2859 {
2860 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2861 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2862 si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
2863
2864 sctx->b.b.create_blend_state = si_create_blend_state;
2865 sctx->b.b.bind_blend_state = si_bind_blend_state;
2866 sctx->b.b.delete_blend_state = si_delete_blend_state;
2867 sctx->b.b.set_blend_color = si_set_blend_color;
2868
2869 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2870 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2871 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2872
2873 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2874 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2875 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2876
2877 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2878 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2879 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2880 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2881
2882 sctx->b.b.set_clip_state = si_set_clip_state;
2883 sctx->b.b.set_scissor_states = si_set_scissor_states;
2884 sctx->b.b.set_viewport_states = si_set_viewport_states;
2885 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2886
2887 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2888 sctx->b.b.get_sample_position = cayman_get_sample_position;
2889
2890 sctx->b.b.create_sampler_state = si_create_sampler_state;
2891 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2892 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2893
2894 sctx->b.b.create_sampler_view = si_create_sampler_view;
2895 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2896
2897 sctx->b.b.set_sample_mask = si_set_sample_mask;
2898
2899 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2900 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2901 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2902 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2903 sctx->b.b.set_index_buffer = si_set_index_buffer;
2904
2905 sctx->b.b.texture_barrier = si_texture_barrier;
2906 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2907 sctx->b.b.set_min_samples = si_set_min_samples;
2908
2909 sctx->b.dma_copy = si_dma_copy;
2910 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2911 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2912
2913 sctx->b.b.draw_vbo = si_draw_vbo;
2914 }
2915
2916 static void
2917 si_write_harvested_raster_configs(struct si_context *sctx,
2918 struct si_pm4_state *pm4,
2919 unsigned raster_config)
2920 {
2921 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
2922 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
2923 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2924 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2925 unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
2926 unsigned rb_per_se = num_rb / num_se;
2927 unsigned se0_mask = (1 << rb_per_se) - 1;
2928 unsigned se1_mask = se0_mask << rb_per_se;
2929 unsigned se;
2930
2931 assert(num_se == 1 || num_se == 2);
2932 assert(sh_per_se == 1 || sh_per_se == 2);
2933 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
2934
2935 /* XXX: I can't figure out what the *_XSEL and *_YSEL
2936 * fields are for, so I'm leaving them as their default
2937 * values. */
2938
2939 se0_mask &= rb_mask;
2940 se1_mask &= rb_mask;
2941 if (num_se == 2 && (!se0_mask || !se1_mask)) {
2942 raster_config &= C_028350_SE_MAP;
2943
2944 if (!se0_mask) {
2945 raster_config |=
2946 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
2947 } else {
2948 raster_config |=
2949 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
2950 }
2951 }
2952
2953 for (se = 0; se < num_se; se++) {
2954 unsigned raster_config_se = raster_config;
2955 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
2956 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
2957
2958 pkr0_mask &= rb_mask;
2959 pkr1_mask &= rb_mask;
2960 if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
2961 raster_config_se &= C_028350_PKR_MAP;
2962
2963 if (!pkr0_mask) {
2964 raster_config_se |=
2965 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
2966 } else {
2967 raster_config_se |=
2968 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
2969 }
2970 }
2971
2972 if (rb_per_pkr == 2) {
2973 unsigned rb0_mask = 1 << (se * rb_per_se);
2974 unsigned rb1_mask = rb0_mask << 1;
2975
2976 rb0_mask &= rb_mask;
2977 rb1_mask &= rb_mask;
2978 if (!rb0_mask || !rb1_mask) {
2979 raster_config_se &= C_028350_RB_MAP_PKR0;
2980
2981 if (!rb0_mask) {
2982 raster_config_se |=
2983 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
2984 } else {
2985 raster_config_se |=
2986 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
2987 }
2988 }
2989
2990 if (sh_per_se == 2) {
2991 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
2992 rb1_mask = rb0_mask << 1;
2993 rb0_mask &= rb_mask;
2994 rb1_mask &= rb_mask;
2995 if (!rb0_mask || !rb1_mask) {
2996 raster_config_se &= C_028350_RB_MAP_PKR1;
2997
2998 if (!rb0_mask) {
2999 raster_config_se |=
3000 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3001 } else {
3002 raster_config_se |=
3003 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3004 }
3005 }
3006 }
3007 }
3008
3009 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3010 SE_INDEX(se) | SH_BROADCAST_WRITES |
3011 INSTANCE_BROADCAST_WRITES);
3012 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3013 }
3014
3015 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3016 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3017 INSTANCE_BROADCAST_WRITES);
3018 }
3019
3020 void si_init_config(struct si_context *sctx)
3021 {
3022 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3023
3024 if (pm4 == NULL)
3025 return;
3026
3027 si_cmd_context_control(pm4);
3028
3029 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3030 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3031
3032 /* FIXME calculate these values somehow ??? */
3033 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3034 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3035 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3036
3037 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3038 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3039 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3040 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3041
3042 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3043 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3044 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3045 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
3046
3047 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3048 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3049 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3050 if (sctx->b.chip_class < CIK)
3051 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3052 S_008A14_CLIP_VTX_REORDER_ENA(1));
3053
3054 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3055 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3056
3057 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3058
3059 if (sctx->b.chip_class >= CIK) {
3060 switch (sctx->screen->b.family) {
3061 case CHIP_BONAIRE:
3062 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3063 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3064 break;
3065 case CHIP_HAWAII:
3066 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3067 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3068 break;
3069 case CHIP_KAVERI:
3070 /* XXX todo */
3071 case CHIP_KABINI:
3072 /* XXX todo */
3073 case CHIP_MULLINS:
3074 /* XXX todo */
3075 default:
3076 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
3077 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3078 break;
3079 }
3080 } else {
3081 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3082 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
3083 unsigned raster_config;
3084
3085 switch (sctx->screen->b.family) {
3086 case CHIP_TAHITI:
3087 case CHIP_PITCAIRN:
3088 raster_config = 0x2a00126a;
3089 break;
3090 case CHIP_VERDE:
3091 raster_config = 0x0000124a;
3092 break;
3093 case CHIP_OLAND:
3094 raster_config = 0x00000082;
3095 break;
3096 case CHIP_HAINAN:
3097 raster_config = 0;
3098 break;
3099 default:
3100 fprintf(stderr,
3101 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3102 raster_config = 0;
3103 break;
3104 }
3105
3106 /* Always use the default config when all backends are enabled
3107 * (or when we failed to determine the enabled backends).
3108 */
3109 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3110 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3111 raster_config);
3112 } else {
3113 si_write_harvested_raster_configs(sctx, pm4, raster_config);
3114 }
3115 }
3116
3117 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3118 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3119 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3120 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3121 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3122 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3123 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3124
3125 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3126 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3127 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3128 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3129 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0);
3130 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, fui(1.0));
3131 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3132 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3133 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3134 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3135 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3136 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0);
3137 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0);
3138 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3139 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3140 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3141 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3142
3143 /* There is a hang if stencil is used and fast stencil is enabled
3144 * regardless of whether HTILE is depth-only or not.
3145 */
3146 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3147 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3148 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3149 S_02800C_FAST_STENCIL_DISABLE(1));
3150
3151 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3152 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3153 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3154
3155 if (sctx->b.chip_class >= CIK) {
3156 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3157 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3158 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3159 }
3160
3161 sctx->init_config = pm4;
3162 }