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[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_math.h"
31 #include "util/u_pack_color.h"
32 #include "tgsi/tgsi_parse.h"
33 #include "radeonsi_pipe.h"
34 #include "radeonsi_shader.h"
35 #include "si_state.h"
36 #include "sid.h"
37
38 /*
39 * inferred framebuffer and blender state
40 */
41 static void si_update_fb_blend_state(struct r600_context *rctx)
42 {
43 struct si_pm4_state *pm4;
44 struct si_state_blend *blend = rctx->queued.named.blend;
45 uint32_t mask;
46
47 if (blend == NULL)
48 return;
49
50 pm4 = CALLOC_STRUCT(si_pm4_state);
51 if (pm4 == NULL)
52 return;
53
54 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
55 mask &= blend->cb_target_mask;
56 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
57
58 si_pm4_set_state(rctx, fb_blend, pm4);
59 }
60
61 /*
62 * Blender functions
63 */
64
65 static uint32_t si_translate_blend_function(int blend_func)
66 {
67 switch (blend_func) {
68 case PIPE_BLEND_ADD:
69 return V_028780_COMB_DST_PLUS_SRC;
70 case PIPE_BLEND_SUBTRACT:
71 return V_028780_COMB_SRC_MINUS_DST;
72 case PIPE_BLEND_REVERSE_SUBTRACT:
73 return V_028780_COMB_DST_MINUS_SRC;
74 case PIPE_BLEND_MIN:
75 return V_028780_COMB_MIN_DST_SRC;
76 case PIPE_BLEND_MAX:
77 return V_028780_COMB_MAX_DST_SRC;
78 default:
79 R600_ERR("Unknown blend function %d\n", blend_func);
80 assert(0);
81 break;
82 }
83 return 0;
84 }
85
86 static uint32_t si_translate_blend_factor(int blend_fact)
87 {
88 switch (blend_fact) {
89 case PIPE_BLENDFACTOR_ONE:
90 return V_028780_BLEND_ONE;
91 case PIPE_BLENDFACTOR_SRC_COLOR:
92 return V_028780_BLEND_SRC_COLOR;
93 case PIPE_BLENDFACTOR_SRC_ALPHA:
94 return V_028780_BLEND_SRC_ALPHA;
95 case PIPE_BLENDFACTOR_DST_ALPHA:
96 return V_028780_BLEND_DST_ALPHA;
97 case PIPE_BLENDFACTOR_DST_COLOR:
98 return V_028780_BLEND_DST_COLOR;
99 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
100 return V_028780_BLEND_SRC_ALPHA_SATURATE;
101 case PIPE_BLENDFACTOR_CONST_COLOR:
102 return V_028780_BLEND_CONSTANT_COLOR;
103 case PIPE_BLENDFACTOR_CONST_ALPHA:
104 return V_028780_BLEND_CONSTANT_ALPHA;
105 case PIPE_BLENDFACTOR_ZERO:
106 return V_028780_BLEND_ZERO;
107 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
108 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
109 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
110 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
111 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
112 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
113 case PIPE_BLENDFACTOR_INV_DST_COLOR:
114 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
115 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
116 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
117 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
118 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
119 case PIPE_BLENDFACTOR_SRC1_COLOR:
120 return V_028780_BLEND_SRC1_COLOR;
121 case PIPE_BLENDFACTOR_SRC1_ALPHA:
122 return V_028780_BLEND_SRC1_ALPHA;
123 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
124 return V_028780_BLEND_INV_SRC1_COLOR;
125 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
126 return V_028780_BLEND_INV_SRC1_ALPHA;
127 default:
128 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
129 assert(0);
130 break;
131 }
132 return 0;
133 }
134
135 static void *si_create_blend_state(struct pipe_context *ctx,
136 const struct pipe_blend_state *state)
137 {
138 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
139 struct si_pm4_state *pm4 = &blend->pm4;
140
141 uint32_t color_control;
142
143 if (blend == NULL)
144 return NULL;
145
146 color_control = S_028808_MODE(V_028808_CB_NORMAL);
147 if (state->logicop_enable) {
148 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
149 } else {
150 color_control |= S_028808_ROP3(0xcc);
151 }
152 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
153
154 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
155 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
156
157 blend->cb_target_mask = 0;
158 for (int i = 0; i < 8; i++) {
159 /* state->rt entries > 0 only written if independent blending */
160 const int j = state->independent_blend_enable ? i : 0;
161
162 unsigned eqRGB = state->rt[j].rgb_func;
163 unsigned srcRGB = state->rt[j].rgb_src_factor;
164 unsigned dstRGB = state->rt[j].rgb_dst_factor;
165 unsigned eqA = state->rt[j].alpha_func;
166 unsigned srcA = state->rt[j].alpha_src_factor;
167 unsigned dstA = state->rt[j].alpha_dst_factor;
168
169 unsigned blend_cntl = 0;
170
171 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
172 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
173
174 if (!state->rt[j].blend_enable) {
175 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
176 continue;
177 }
178
179 blend_cntl |= S_028780_ENABLE(1);
180 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
181 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
182 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
183
184 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
185 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
186 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
187 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
188 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
189 }
190 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
191 }
192
193 return blend;
194 }
195
196 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
197 {
198 struct r600_context *rctx = (struct r600_context *)ctx;
199 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
200 si_update_fb_blend_state(rctx);
201 }
202
203 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
204 {
205 struct r600_context *rctx = (struct r600_context *)ctx;
206 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
207 }
208
209 static void si_set_blend_color(struct pipe_context *ctx,
210 const struct pipe_blend_color *state)
211 {
212 struct r600_context *rctx = (struct r600_context *)ctx;
213 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
214
215 if (pm4 == NULL)
216 return;
217
218 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
219 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
220 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
221 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
222
223 si_pm4_set_state(rctx, blend_color, pm4);
224 }
225
226 /*
227 * Clipping, scissors and viewport
228 */
229
230 static void si_set_clip_state(struct pipe_context *ctx,
231 const struct pipe_clip_state *state)
232 {
233 struct r600_context *rctx = (struct r600_context *)ctx;
234 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
235
236 if (pm4 == NULL)
237 return;
238
239 for (int i = 0; i < 6; i++) {
240 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
241 fui(state->ucp[i][0]));
242 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
243 fui(state->ucp[i][1]));
244 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
245 fui(state->ucp[i][2]));
246 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
247 fui(state->ucp[i][3]));
248 }
249
250 si_pm4_set_state(rctx, clip, pm4);
251 }
252
253 static void si_set_scissor_state(struct pipe_context *ctx,
254 const struct pipe_scissor_state *state)
255 {
256 struct r600_context *rctx = (struct r600_context *)ctx;
257 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
258 uint32_t tl, br;
259
260 if (pm4 == NULL)
261 return;
262
263 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
264 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
265 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
266 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
267 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
268 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
269 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
270 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
271 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
272 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
273
274 si_pm4_set_state(rctx, scissor, pm4);
275 }
276
277 static void si_set_viewport_state(struct pipe_context *ctx,
278 const struct pipe_viewport_state *state)
279 {
280 struct r600_context *rctx = (struct r600_context *)ctx;
281 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
282 struct si_pm4_state *pm4 = &viewport->pm4;
283
284 if (viewport == NULL)
285 return;
286
287 viewport->viewport = *state;
288 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
289 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
290 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
291 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
292 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
293 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
294 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
295 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
296 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
297
298 si_pm4_set_state(rctx, viewport, viewport);
299 }
300
301 /*
302 * inferred state between framebuffer and rasterizer
303 */
304 static void si_update_fb_rs_state(struct r600_context *rctx)
305 {
306 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
307 struct si_pm4_state *pm4;
308 unsigned offset_db_fmt_cntl = 0, depth;
309 float offset_units;
310
311 if (!rs || !rctx->framebuffer.zsbuf)
312 return;
313
314 offset_units = rctx->queued.named.rasterizer->offset_units;
315 switch (rctx->framebuffer.zsbuf->texture->format) {
316 case PIPE_FORMAT_Z24X8_UNORM:
317 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
318 depth = -24;
319 offset_units *= 2.0f;
320 break;
321 case PIPE_FORMAT_Z32_FLOAT:
322 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
323 depth = -23;
324 offset_units *= 1.0f;
325 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
326 break;
327 case PIPE_FORMAT_Z16_UNORM:
328 depth = -16;
329 offset_units *= 4.0f;
330 break;
331 default:
332 return;
333 }
334
335 pm4 = CALLOC_STRUCT(si_pm4_state);
336 /* FIXME some of those reg can be computed with cso */
337 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
338 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
339 fui(rctx->queued.named.rasterizer->offset_scale));
340 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
341 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
342 fui(rctx->queued.named.rasterizer->offset_scale));
343 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
344 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
345
346 si_pm4_set_state(rctx, fb_rs, pm4);
347 }
348
349 /*
350 * Rasterizer
351 */
352
353 static uint32_t si_translate_fill(uint32_t func)
354 {
355 switch(func) {
356 case PIPE_POLYGON_MODE_FILL:
357 return V_028814_X_DRAW_TRIANGLES;
358 case PIPE_POLYGON_MODE_LINE:
359 return V_028814_X_DRAW_LINES;
360 case PIPE_POLYGON_MODE_POINT:
361 return V_028814_X_DRAW_POINTS;
362 default:
363 assert(0);
364 return V_028814_X_DRAW_POINTS;
365 }
366 }
367
368 static void *si_create_rs_state(struct pipe_context *ctx,
369 const struct pipe_rasterizer_state *state)
370 {
371 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
372 struct si_pm4_state *pm4 = &rs->pm4;
373 unsigned tmp;
374 unsigned prov_vtx = 1, polygon_dual_mode;
375 unsigned clip_rule;
376 float psize_min, psize_max;
377
378 if (rs == NULL) {
379 return NULL;
380 }
381
382 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
383 state->fill_back != PIPE_POLYGON_MODE_FILL);
384
385 if (state->flatshade_first)
386 prov_vtx = 0;
387
388 rs->flatshade = state->flatshade;
389 rs->sprite_coord_enable = state->sprite_coord_enable;
390 rs->pa_sc_line_stipple = state->line_stipple_enable ?
391 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
392 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
393 rs->pa_su_sc_mode_cntl =
394 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
395 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
396 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
397 S_028814_FACE(!state->front_ccw) |
398 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
399 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
400 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
401 S_028814_POLY_MODE(polygon_dual_mode) |
402 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
403 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
404 rs->pa_cl_clip_cntl =
405 S_028810_PS_UCP_MODE(3) |
406 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
407 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
408 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
409 rs->pa_cl_vs_out_cntl =
410 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
411 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
412
413 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
414
415 /* offset */
416 rs->offset_units = state->offset_units;
417 rs->offset_scale = state->offset_scale * 12.0f;
418
419 /* XXX: Flat shading hangs the GPU */
420 tmp = S_0286D4_FLAT_SHADE_ENA(0);
421 if (state->sprite_coord_enable) {
422 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
423 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
424 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
425 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
426 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
427 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
428 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
429 }
430 }
431 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
432
433 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
434 /* point size 12.4 fixed point */
435 tmp = (unsigned)(state->point_size * 8.0);
436 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
437
438 if (state->point_size_per_vertex) {
439 psize_min = util_get_min_point_size(state);
440 psize_max = 8192;
441 } else {
442 /* Force the point size to be as if the vertex output was disabled. */
443 psize_min = state->point_size;
444 psize_max = state->point_size;
445 }
446 /* Divide by two, because 0.5 = 1 pixel. */
447 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
448 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
449 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
450
451 tmp = (unsigned)state->line_width * 8;
452 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
453 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
454 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
455
456 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
457 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
458 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
459 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
460 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
461 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
462 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
463
464 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
465 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
466
467 return rs;
468 }
469
470 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
471 {
472 struct r600_context *rctx = (struct r600_context *)ctx;
473 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
474
475 if (state == NULL)
476 return;
477
478 // TODO
479 rctx->sprite_coord_enable = rs->sprite_coord_enable;
480 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
481 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
482 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
483 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
484
485 si_pm4_bind_state(rctx, rasterizer, rs);
486 si_update_fb_rs_state(rctx);
487 }
488
489 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
490 {
491 struct r600_context *rctx = (struct r600_context *)ctx;
492 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
493 }
494
495 /*
496 * infeered state between dsa and stencil ref
497 */
498 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
499 {
500 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
501 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
502 struct si_state_dsa *dsa = rctx->queued.named.dsa;
503
504 if (pm4 == NULL)
505 return;
506
507 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
508 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
509 S_028430_STENCILMASK(dsa->valuemask[0]) |
510 S_028430_STENCILWRITEMASK(dsa->writemask[0]));
511 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
512 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
513 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
514 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]));
515
516 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
517 }
518
519 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
520 const struct pipe_stencil_ref *state)
521 {
522 struct r600_context *rctx = (struct r600_context *)ctx;
523 rctx->stencil_ref = *state;
524 si_update_dsa_stencil_ref(rctx);
525 }
526
527
528 /*
529 * DSA
530 */
531
532 static uint32_t si_translate_stencil_op(int s_op)
533 {
534 switch (s_op) {
535 case PIPE_STENCIL_OP_KEEP:
536 return V_02842C_STENCIL_KEEP;
537 case PIPE_STENCIL_OP_ZERO:
538 return V_02842C_STENCIL_ZERO;
539 case PIPE_STENCIL_OP_REPLACE:
540 return V_02842C_STENCIL_REPLACE_TEST;
541 case PIPE_STENCIL_OP_INCR:
542 return V_02842C_STENCIL_ADD_CLAMP;
543 case PIPE_STENCIL_OP_DECR:
544 return V_02842C_STENCIL_SUB_CLAMP;
545 case PIPE_STENCIL_OP_INCR_WRAP:
546 return V_02842C_STENCIL_ADD_WRAP;
547 case PIPE_STENCIL_OP_DECR_WRAP:
548 return V_02842C_STENCIL_SUB_WRAP;
549 case PIPE_STENCIL_OP_INVERT:
550 return V_02842C_STENCIL_INVERT;
551 default:
552 R600_ERR("Unknown stencil op %d", s_op);
553 assert(0);
554 break;
555 }
556 return 0;
557 }
558
559 static void *si_create_dsa_state(struct pipe_context *ctx,
560 const struct pipe_depth_stencil_alpha_state *state)
561 {
562 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
563 struct si_pm4_state *pm4 = &dsa->pm4;
564 unsigned db_depth_control, /* alpha_test_control, */ alpha_ref;
565 unsigned db_render_override, db_render_control;
566 uint32_t db_stencil_control = 0;
567
568 if (dsa == NULL) {
569 return NULL;
570 }
571
572 dsa->valuemask[0] = state->stencil[0].valuemask;
573 dsa->valuemask[1] = state->stencil[1].valuemask;
574 dsa->writemask[0] = state->stencil[0].writemask;
575 dsa->writemask[1] = state->stencil[1].writemask;
576
577 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
578 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
579 S_028800_ZFUNC(state->depth.func);
580
581 /* stencil */
582 if (state->stencil[0].enabled) {
583 db_depth_control |= S_028800_STENCIL_ENABLE(1);
584 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
585 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
586 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
587 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
588
589 if (state->stencil[1].enabled) {
590 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
591 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
592 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
593 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
594 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
595 }
596 }
597
598 /* alpha */
599 //alpha_test_control = 0;
600 alpha_ref = 0;
601 if (state->alpha.enabled) {
602 //alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
603 //alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
604 alpha_ref = fui(state->alpha.ref_value);
605 }
606 dsa->alpha_ref = alpha_ref;
607
608 /* misc */
609 db_render_control = 0;
610 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
611 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
612 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
613 /* TODO db_render_override depends on query */
614 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
615 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
616 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
617 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
618 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
619 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
620 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
621 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
622 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
623 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
624 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
625 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
626 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
627 dsa->db_render_override = db_render_override;
628
629 return dsa;
630 }
631
632 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
633 {
634 struct r600_context *rctx = (struct r600_context *)ctx;
635 struct si_state_dsa *dsa = state;
636
637 if (state == NULL)
638 return;
639
640 si_pm4_bind_state(rctx, dsa, dsa);
641 si_update_dsa_stencil_ref(rctx);
642
643 // TODO
644 rctx->alpha_ref = dsa->alpha_ref;
645 rctx->alpha_ref_dirty = true;
646 }
647
648 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
649 {
650 struct r600_context *rctx = (struct r600_context *)ctx;
651 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
652 }
653
654 static void *si_create_db_flush_dsa(struct r600_context *rctx)
655 {
656 struct pipe_depth_stencil_alpha_state dsa;
657 struct si_state_dsa *state;
658
659 memset(&dsa, 0, sizeof(dsa));
660
661 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
662 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
663 S_028000_DEPTH_COPY(1) |
664 S_028000_STENCIL_COPY(1) |
665 S_028000_COPY_CENTROID(1));
666 return state;
667 }
668
669 /*
670 * format translation
671 */
672 static uint32_t si_translate_colorformat(enum pipe_format format)
673 {
674 switch (format) {
675 /* 8-bit buffers. */
676 case PIPE_FORMAT_A8_UNORM:
677 case PIPE_FORMAT_A8_SNORM:
678 case PIPE_FORMAT_A8_UINT:
679 case PIPE_FORMAT_A8_SINT:
680 case PIPE_FORMAT_I8_UNORM:
681 case PIPE_FORMAT_I8_SNORM:
682 case PIPE_FORMAT_I8_UINT:
683 case PIPE_FORMAT_I8_SINT:
684 case PIPE_FORMAT_L8_UNORM:
685 case PIPE_FORMAT_L8_SNORM:
686 case PIPE_FORMAT_L8_UINT:
687 case PIPE_FORMAT_L8_SINT:
688 case PIPE_FORMAT_L8_SRGB:
689 case PIPE_FORMAT_R8_UNORM:
690 case PIPE_FORMAT_R8_SNORM:
691 case PIPE_FORMAT_R8_UINT:
692 case PIPE_FORMAT_R8_SINT:
693 return V_028C70_COLOR_8;
694
695 /* 16-bit buffers. */
696 case PIPE_FORMAT_B5G6R5_UNORM:
697 return V_028C70_COLOR_5_6_5;
698
699 case PIPE_FORMAT_B5G5R5A1_UNORM:
700 case PIPE_FORMAT_B5G5R5X1_UNORM:
701 return V_028C70_COLOR_1_5_5_5;
702
703 case PIPE_FORMAT_B4G4R4A4_UNORM:
704 case PIPE_FORMAT_B4G4R4X4_UNORM:
705 return V_028C70_COLOR_4_4_4_4;
706
707 case PIPE_FORMAT_L8A8_UNORM:
708 case PIPE_FORMAT_L8A8_SNORM:
709 case PIPE_FORMAT_L8A8_UINT:
710 case PIPE_FORMAT_L8A8_SINT:
711 case PIPE_FORMAT_L8A8_SRGB:
712 case PIPE_FORMAT_R8G8_SNORM:
713 case PIPE_FORMAT_R8G8_UNORM:
714 case PIPE_FORMAT_R8G8_UINT:
715 case PIPE_FORMAT_R8G8_SINT:
716 return V_028C70_COLOR_8_8;
717
718 case PIPE_FORMAT_Z16_UNORM:
719 case PIPE_FORMAT_R16_UNORM:
720 case PIPE_FORMAT_R16_SNORM:
721 case PIPE_FORMAT_R16_UINT:
722 case PIPE_FORMAT_R16_SINT:
723 case PIPE_FORMAT_R16_FLOAT:
724 case PIPE_FORMAT_L16_UNORM:
725 case PIPE_FORMAT_L16_SNORM:
726 case PIPE_FORMAT_L16_FLOAT:
727 case PIPE_FORMAT_I16_UNORM:
728 case PIPE_FORMAT_I16_SNORM:
729 case PIPE_FORMAT_I16_FLOAT:
730 case PIPE_FORMAT_A16_UNORM:
731 case PIPE_FORMAT_A16_SNORM:
732 case PIPE_FORMAT_A16_FLOAT:
733 return V_028C70_COLOR_16;
734
735 /* 32-bit buffers. */
736 case PIPE_FORMAT_A8B8G8R8_SRGB:
737 case PIPE_FORMAT_A8B8G8R8_UNORM:
738 case PIPE_FORMAT_A8R8G8B8_UNORM:
739 case PIPE_FORMAT_B8G8R8A8_SRGB:
740 case PIPE_FORMAT_B8G8R8A8_UNORM:
741 case PIPE_FORMAT_B8G8R8X8_UNORM:
742 case PIPE_FORMAT_R8G8B8A8_SNORM:
743 case PIPE_FORMAT_R8G8B8A8_UNORM:
744 case PIPE_FORMAT_R8G8B8X8_UNORM:
745 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
746 case PIPE_FORMAT_X8B8G8R8_UNORM:
747 case PIPE_FORMAT_X8R8G8B8_UNORM:
748 case PIPE_FORMAT_R8G8B8_UNORM:
749 case PIPE_FORMAT_R8G8B8A8_SSCALED:
750 case PIPE_FORMAT_R8G8B8A8_USCALED:
751 case PIPE_FORMAT_R8G8B8A8_SINT:
752 case PIPE_FORMAT_R8G8B8A8_UINT:
753 return V_028C70_COLOR_8_8_8_8;
754
755 case PIPE_FORMAT_R10G10B10A2_UNORM:
756 case PIPE_FORMAT_R10G10B10X2_SNORM:
757 case PIPE_FORMAT_B10G10R10A2_UNORM:
758 case PIPE_FORMAT_B10G10R10A2_UINT:
759 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
760 return V_028C70_COLOR_2_10_10_10;
761
762 case PIPE_FORMAT_Z24X8_UNORM:
763 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
764 return V_028C70_COLOR_8_24;
765
766 case PIPE_FORMAT_X8Z24_UNORM:
767 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
768 return V_028C70_COLOR_24_8;
769
770 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
771 return V_028C70_COLOR_X24_8_32_FLOAT;
772
773 case PIPE_FORMAT_I32_FLOAT:
774 case PIPE_FORMAT_L32_FLOAT:
775 case PIPE_FORMAT_R32_FLOAT:
776 case PIPE_FORMAT_A32_FLOAT:
777 case PIPE_FORMAT_Z32_FLOAT:
778 return V_028C70_COLOR_32;
779
780 case PIPE_FORMAT_L16A16_UNORM:
781 case PIPE_FORMAT_L16A16_SNORM:
782 case PIPE_FORMAT_L16A16_FLOAT:
783 case PIPE_FORMAT_R16G16_SSCALED:
784 case PIPE_FORMAT_R16G16_UNORM:
785 case PIPE_FORMAT_R16G16_SNORM:
786 case PIPE_FORMAT_R16G16_UINT:
787 case PIPE_FORMAT_R16G16_SINT:
788 case PIPE_FORMAT_R16G16_FLOAT:
789 return V_028C70_COLOR_16_16;
790
791 case PIPE_FORMAT_R11G11B10_FLOAT:
792 return V_028C70_COLOR_10_11_11;
793
794 /* 64-bit buffers. */
795 case PIPE_FORMAT_R16G16B16_USCALED:
796 case PIPE_FORMAT_R16G16B16_SSCALED:
797 case PIPE_FORMAT_R16G16B16A16_UINT:
798 case PIPE_FORMAT_R16G16B16A16_SINT:
799 case PIPE_FORMAT_R16G16B16A16_USCALED:
800 case PIPE_FORMAT_R16G16B16A16_SSCALED:
801 case PIPE_FORMAT_R16G16B16A16_UNORM:
802 case PIPE_FORMAT_R16G16B16A16_SNORM:
803 case PIPE_FORMAT_R16G16B16_FLOAT:
804 case PIPE_FORMAT_R16G16B16A16_FLOAT:
805 return V_028C70_COLOR_16_16_16_16;
806
807 case PIPE_FORMAT_L32A32_FLOAT:
808 case PIPE_FORMAT_R32G32_FLOAT:
809 case PIPE_FORMAT_R32G32_USCALED:
810 case PIPE_FORMAT_R32G32_SSCALED:
811 case PIPE_FORMAT_R32G32_SINT:
812 case PIPE_FORMAT_R32G32_UINT:
813 return V_028C70_COLOR_32_32;
814
815 /* 128-bit buffers. */
816 case PIPE_FORMAT_R32G32B32A32_SNORM:
817 case PIPE_FORMAT_R32G32B32A32_UNORM:
818 case PIPE_FORMAT_R32G32B32A32_SSCALED:
819 case PIPE_FORMAT_R32G32B32A32_USCALED:
820 case PIPE_FORMAT_R32G32B32A32_SINT:
821 case PIPE_FORMAT_R32G32B32A32_UINT:
822 case PIPE_FORMAT_R32G32B32A32_FLOAT:
823 return V_028C70_COLOR_32_32_32_32;
824
825 /* YUV buffers. */
826 case PIPE_FORMAT_UYVY:
827 case PIPE_FORMAT_YUYV:
828 /* 96-bit buffers. */
829 case PIPE_FORMAT_R32G32B32_FLOAT:
830 /* 8-bit buffers. */
831 case PIPE_FORMAT_L4A4_UNORM:
832 case PIPE_FORMAT_R4A4_UNORM:
833 case PIPE_FORMAT_A4R4_UNORM:
834 default:
835 return ~0U; /* Unsupported. */
836 }
837 }
838
839 static uint32_t si_translate_colorswap(enum pipe_format format)
840 {
841 switch (format) {
842 /* 8-bit buffers. */
843 case PIPE_FORMAT_L4A4_UNORM:
844 case PIPE_FORMAT_A4R4_UNORM:
845 return V_028C70_SWAP_ALT;
846
847 case PIPE_FORMAT_A8_UNORM:
848 case PIPE_FORMAT_A8_SNORM:
849 case PIPE_FORMAT_A8_UINT:
850 case PIPE_FORMAT_A8_SINT:
851 case PIPE_FORMAT_R4A4_UNORM:
852 return V_028C70_SWAP_ALT_REV;
853 case PIPE_FORMAT_I8_UNORM:
854 case PIPE_FORMAT_I8_SNORM:
855 case PIPE_FORMAT_L8_UNORM:
856 case PIPE_FORMAT_L8_SNORM:
857 case PIPE_FORMAT_I8_UINT:
858 case PIPE_FORMAT_I8_SINT:
859 case PIPE_FORMAT_L8_UINT:
860 case PIPE_FORMAT_L8_SINT:
861 case PIPE_FORMAT_L8_SRGB:
862 case PIPE_FORMAT_R8_UNORM:
863 case PIPE_FORMAT_R8_SNORM:
864 case PIPE_FORMAT_R8_UINT:
865 case PIPE_FORMAT_R8_SINT:
866 return V_028C70_SWAP_STD;
867
868 /* 16-bit buffers. */
869 case PIPE_FORMAT_B5G6R5_UNORM:
870 return V_028C70_SWAP_STD_REV;
871
872 case PIPE_FORMAT_B5G5R5A1_UNORM:
873 case PIPE_FORMAT_B5G5R5X1_UNORM:
874 return V_028C70_SWAP_ALT;
875
876 case PIPE_FORMAT_B4G4R4A4_UNORM:
877 case PIPE_FORMAT_B4G4R4X4_UNORM:
878 return V_028C70_SWAP_ALT;
879
880 case PIPE_FORMAT_Z16_UNORM:
881 return V_028C70_SWAP_STD;
882
883 case PIPE_FORMAT_L8A8_UNORM:
884 case PIPE_FORMAT_L8A8_SNORM:
885 case PIPE_FORMAT_L8A8_UINT:
886 case PIPE_FORMAT_L8A8_SINT:
887 case PIPE_FORMAT_L8A8_SRGB:
888 return V_028C70_SWAP_ALT;
889 case PIPE_FORMAT_R8G8_SNORM:
890 case PIPE_FORMAT_R8G8_UNORM:
891 case PIPE_FORMAT_R8G8_UINT:
892 case PIPE_FORMAT_R8G8_SINT:
893 return V_028C70_SWAP_STD;
894
895 case PIPE_FORMAT_I16_UNORM:
896 case PIPE_FORMAT_I16_SNORM:
897 case PIPE_FORMAT_I16_FLOAT:
898 case PIPE_FORMAT_L16_UNORM:
899 case PIPE_FORMAT_L16_SNORM:
900 case PIPE_FORMAT_L16_FLOAT:
901 case PIPE_FORMAT_R16_UNORM:
902 case PIPE_FORMAT_R16_SNORM:
903 case PIPE_FORMAT_R16_UINT:
904 case PIPE_FORMAT_R16_SINT:
905 case PIPE_FORMAT_R16_FLOAT:
906 return V_028C70_SWAP_STD;
907
908 case PIPE_FORMAT_A16_UNORM:
909 case PIPE_FORMAT_A16_SNORM:
910 case PIPE_FORMAT_A16_FLOAT:
911 return V_028C70_SWAP_ALT_REV;
912
913 /* 32-bit buffers. */
914 case PIPE_FORMAT_A8B8G8R8_SRGB:
915 return V_028C70_SWAP_STD_REV;
916 case PIPE_FORMAT_B8G8R8A8_SRGB:
917 return V_028C70_SWAP_ALT;
918
919 case PIPE_FORMAT_B8G8R8A8_UNORM:
920 case PIPE_FORMAT_B8G8R8X8_UNORM:
921 return V_028C70_SWAP_ALT;
922
923 case PIPE_FORMAT_A8R8G8B8_UNORM:
924 case PIPE_FORMAT_X8R8G8B8_UNORM:
925 return V_028C70_SWAP_ALT_REV;
926 case PIPE_FORMAT_R8G8B8A8_SNORM:
927 case PIPE_FORMAT_R8G8B8A8_UNORM:
928 case PIPE_FORMAT_R8G8B8A8_SSCALED:
929 case PIPE_FORMAT_R8G8B8A8_USCALED:
930 case PIPE_FORMAT_R8G8B8A8_SINT:
931 case PIPE_FORMAT_R8G8B8A8_UINT:
932 case PIPE_FORMAT_R8G8B8X8_UNORM:
933 return V_028C70_SWAP_STD;
934
935 case PIPE_FORMAT_A8B8G8R8_UNORM:
936 case PIPE_FORMAT_X8B8G8R8_UNORM:
937 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
938 return V_028C70_SWAP_STD_REV;
939
940 case PIPE_FORMAT_Z24X8_UNORM:
941 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
942 return V_028C70_SWAP_STD;
943
944 case PIPE_FORMAT_X8Z24_UNORM:
945 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
946 return V_028C70_SWAP_STD;
947
948 case PIPE_FORMAT_R10G10B10A2_UNORM:
949 case PIPE_FORMAT_R10G10B10X2_SNORM:
950 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
951 return V_028C70_SWAP_STD;
952
953 case PIPE_FORMAT_B10G10R10A2_UNORM:
954 case PIPE_FORMAT_B10G10R10A2_UINT:
955 return V_028C70_SWAP_ALT;
956
957 case PIPE_FORMAT_R11G11B10_FLOAT:
958 case PIPE_FORMAT_I32_FLOAT:
959 case PIPE_FORMAT_L32_FLOAT:
960 case PIPE_FORMAT_R32_FLOAT:
961 case PIPE_FORMAT_R32_UINT:
962 case PIPE_FORMAT_R32_SINT:
963 case PIPE_FORMAT_Z32_FLOAT:
964 case PIPE_FORMAT_R16G16_FLOAT:
965 case PIPE_FORMAT_R16G16_UNORM:
966 case PIPE_FORMAT_R16G16_SNORM:
967 case PIPE_FORMAT_R16G16_UINT:
968 case PIPE_FORMAT_R16G16_SINT:
969 return V_028C70_SWAP_STD;
970
971 case PIPE_FORMAT_L16A16_UNORM:
972 case PIPE_FORMAT_L16A16_SNORM:
973 case PIPE_FORMAT_L16A16_FLOAT:
974 return V_028C70_SWAP_ALT;
975
976 case PIPE_FORMAT_A32_FLOAT:
977 return V_028C70_SWAP_ALT_REV;
978
979 /* 64-bit buffers. */
980 case PIPE_FORMAT_R32G32_FLOAT:
981 case PIPE_FORMAT_R32G32_UINT:
982 case PIPE_FORMAT_R32G32_SINT:
983 case PIPE_FORMAT_R16G16B16A16_UNORM:
984 case PIPE_FORMAT_R16G16B16A16_SNORM:
985 case PIPE_FORMAT_R16G16B16A16_USCALED:
986 case PIPE_FORMAT_R16G16B16A16_SSCALED:
987 case PIPE_FORMAT_R16G16B16A16_UINT:
988 case PIPE_FORMAT_R16G16B16A16_SINT:
989 case PIPE_FORMAT_R16G16B16A16_FLOAT:
990 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
991 return V_028C70_SWAP_STD;
992
993 case PIPE_FORMAT_L32A32_FLOAT:
994 return V_028C70_SWAP_ALT;
995
996 /* 128-bit buffers. */
997 case PIPE_FORMAT_R32G32B32A32_FLOAT:
998 case PIPE_FORMAT_R32G32B32A32_SNORM:
999 case PIPE_FORMAT_R32G32B32A32_UNORM:
1000 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1001 case PIPE_FORMAT_R32G32B32A32_USCALED:
1002 case PIPE_FORMAT_R32G32B32A32_SINT:
1003 case PIPE_FORMAT_R32G32B32A32_UINT:
1004 return V_028C70_SWAP_STD;
1005 default:
1006 R600_ERR("unsupported colorswap format %d\n", format);
1007 return ~0U;
1008 }
1009 return ~0U;
1010 }
1011
1012 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1013 {
1014 if (R600_BIG_ENDIAN) {
1015 switch(colorformat) {
1016 /* 8-bit buffers. */
1017 case V_028C70_COLOR_8:
1018 return V_028C70_ENDIAN_NONE;
1019
1020 /* 16-bit buffers. */
1021 case V_028C70_COLOR_5_6_5:
1022 case V_028C70_COLOR_1_5_5_5:
1023 case V_028C70_COLOR_4_4_4_4:
1024 case V_028C70_COLOR_16:
1025 case V_028C70_COLOR_8_8:
1026 return V_028C70_ENDIAN_8IN16;
1027
1028 /* 32-bit buffers. */
1029 case V_028C70_COLOR_8_8_8_8:
1030 case V_028C70_COLOR_2_10_10_10:
1031 case V_028C70_COLOR_8_24:
1032 case V_028C70_COLOR_24_8:
1033 case V_028C70_COLOR_16_16:
1034 return V_028C70_ENDIAN_8IN32;
1035
1036 /* 64-bit buffers. */
1037 case V_028C70_COLOR_16_16_16_16:
1038 return V_028C70_ENDIAN_8IN16;
1039
1040 case V_028C70_COLOR_32_32:
1041 return V_028C70_ENDIAN_8IN32;
1042
1043 /* 128-bit buffers. */
1044 case V_028C70_COLOR_32_32_32_32:
1045 return V_028C70_ENDIAN_8IN32;
1046 default:
1047 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1048 }
1049 } else {
1050 return V_028C70_ENDIAN_NONE;
1051 }
1052 }
1053
1054 /* Returns the size in bits of the widest component of a CB format */
1055 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1056 {
1057 switch(colorformat) {
1058 case V_028C70_COLOR_4_4_4_4:
1059 return 4;
1060
1061 case V_028C70_COLOR_1_5_5_5:
1062 case V_028C70_COLOR_5_5_5_1:
1063 return 5;
1064
1065 case V_028C70_COLOR_5_6_5:
1066 return 6;
1067
1068 case V_028C70_COLOR_8:
1069 case V_028C70_COLOR_8_8:
1070 case V_028C70_COLOR_8_8_8_8:
1071 return 8;
1072
1073 case V_028C70_COLOR_10_10_10_2:
1074 case V_028C70_COLOR_2_10_10_10:
1075 return 10;
1076
1077 case V_028C70_COLOR_10_11_11:
1078 case V_028C70_COLOR_11_11_10:
1079 return 11;
1080
1081 case V_028C70_COLOR_16:
1082 case V_028C70_COLOR_16_16:
1083 case V_028C70_COLOR_16_16_16_16:
1084 return 16;
1085
1086 case V_028C70_COLOR_8_24:
1087 case V_028C70_COLOR_24_8:
1088 return 24;
1089
1090 case V_028C70_COLOR_32:
1091 case V_028C70_COLOR_32_32:
1092 case V_028C70_COLOR_32_32_32_32:
1093 case V_028C70_COLOR_X24_8_32_FLOAT:
1094 return 32;
1095 }
1096
1097 assert(!"Unknown maximum component size");
1098 return 0;
1099 }
1100
1101 static uint32_t si_translate_dbformat(enum pipe_format format)
1102 {
1103 switch (format) {
1104 //case PIPE_FORMAT_Z16_UNORM:
1105 // return V_028040_Z_16;
1106 case PIPE_FORMAT_Z24X8_UNORM:
1107 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1108 return V_028040_Z_24; /* XXX no longer supported on SI */
1109 case PIPE_FORMAT_Z32_FLOAT:
1110 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1111 return V_028040_Z_32_FLOAT;
1112 default:
1113 return ~0U;
1114 }
1115 }
1116
1117 /*
1118 * Texture translation
1119 */
1120
1121 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1122 enum pipe_format format,
1123 const struct util_format_description *desc,
1124 int first_non_void)
1125 {
1126 boolean uniform = TRUE;
1127 int i;
1128
1129 /* Colorspace (return non-RGB formats directly). */
1130 switch (desc->colorspace) {
1131 /* Depth stencil formats */
1132 case UTIL_FORMAT_COLORSPACE_ZS:
1133 switch (format) {
1134 case PIPE_FORMAT_Z16_UNORM:
1135 return V_008F14_IMG_DATA_FORMAT_16;
1136 case PIPE_FORMAT_X24S8_UINT:
1137 case PIPE_FORMAT_Z24X8_UNORM:
1138 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1139 return V_008F14_IMG_DATA_FORMAT_24_8;
1140 case PIPE_FORMAT_S8X24_UINT:
1141 case PIPE_FORMAT_X8Z24_UNORM:
1142 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1143 return V_008F14_IMG_DATA_FORMAT_8_24;
1144 case PIPE_FORMAT_S8_UINT:
1145 return V_008F14_IMG_DATA_FORMAT_8;
1146 case PIPE_FORMAT_Z32_FLOAT:
1147 return V_008F14_IMG_DATA_FORMAT_32;
1148 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1149 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1150 default:
1151 goto out_unknown;
1152 }
1153
1154 case UTIL_FORMAT_COLORSPACE_YUV:
1155 goto out_unknown; /* TODO */
1156
1157 case UTIL_FORMAT_COLORSPACE_SRGB:
1158 break;
1159
1160 default:
1161 break;
1162 }
1163
1164 /* TODO compressed formats */
1165
1166 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1167 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1168 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1169 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1170 }
1171
1172 /* R8G8Bx_SNORM - TODO CxV8U8 */
1173
1174 /* See whether the components are of the same size. */
1175 for (i = 1; i < desc->nr_channels; i++) {
1176 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1177 }
1178
1179 /* Non-uniform formats. */
1180 if (!uniform) {
1181 switch(desc->nr_channels) {
1182 case 3:
1183 if (desc->channel[0].size == 5 &&
1184 desc->channel[1].size == 6 &&
1185 desc->channel[2].size == 5) {
1186 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1187 }
1188 goto out_unknown;
1189 case 4:
1190 if (desc->channel[0].size == 5 &&
1191 desc->channel[1].size == 5 &&
1192 desc->channel[2].size == 5 &&
1193 desc->channel[3].size == 1) {
1194 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1195 }
1196 if (desc->channel[0].size == 10 &&
1197 desc->channel[1].size == 10 &&
1198 desc->channel[2].size == 10 &&
1199 desc->channel[3].size == 2) {
1200 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1201 }
1202 goto out_unknown;
1203 }
1204 goto out_unknown;
1205 }
1206
1207 if (first_non_void < 0 || first_non_void > 3)
1208 goto out_unknown;
1209
1210 /* uniform formats */
1211 switch (desc->channel[first_non_void].size) {
1212 case 4:
1213 switch (desc->nr_channels) {
1214 #if 0 /* Not supported for render targets */
1215 case 2:
1216 return V_008F14_IMG_DATA_FORMAT_4_4;
1217 #endif
1218 case 4:
1219 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1220 }
1221 break;
1222 case 8:
1223 switch (desc->nr_channels) {
1224 case 1:
1225 return V_008F14_IMG_DATA_FORMAT_8;
1226 case 2:
1227 return V_008F14_IMG_DATA_FORMAT_8_8;
1228 case 4:
1229 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1230 }
1231 break;
1232 case 16:
1233 switch (desc->nr_channels) {
1234 case 1:
1235 return V_008F14_IMG_DATA_FORMAT_16;
1236 case 2:
1237 return V_008F14_IMG_DATA_FORMAT_16_16;
1238 case 4:
1239 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1240 }
1241 break;
1242 case 32:
1243 switch (desc->nr_channels) {
1244 case 1:
1245 return V_008F14_IMG_DATA_FORMAT_32;
1246 case 2:
1247 return V_008F14_IMG_DATA_FORMAT_32_32;
1248 #if 0 /* Not supported for render targets */
1249 case 3:
1250 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1251 #endif
1252 case 4:
1253 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1254 }
1255 }
1256
1257 out_unknown:
1258 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1259 return ~0;
1260 }
1261
1262 static unsigned si_tex_wrap(unsigned wrap)
1263 {
1264 switch (wrap) {
1265 default:
1266 case PIPE_TEX_WRAP_REPEAT:
1267 return V_008F30_SQ_TEX_WRAP;
1268 case PIPE_TEX_WRAP_CLAMP:
1269 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1270 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1271 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1272 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1273 return V_008F30_SQ_TEX_CLAMP_BORDER;
1274 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1275 return V_008F30_SQ_TEX_MIRROR;
1276 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1277 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1278 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1279 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1280 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1281 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1282 }
1283 }
1284
1285 static unsigned si_tex_filter(unsigned filter)
1286 {
1287 switch (filter) {
1288 default:
1289 case PIPE_TEX_FILTER_NEAREST:
1290 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1291 case PIPE_TEX_FILTER_LINEAR:
1292 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1293 }
1294 }
1295
1296 static unsigned si_tex_mipfilter(unsigned filter)
1297 {
1298 switch (filter) {
1299 case PIPE_TEX_MIPFILTER_NEAREST:
1300 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1301 case PIPE_TEX_MIPFILTER_LINEAR:
1302 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1303 default:
1304 case PIPE_TEX_MIPFILTER_NONE:
1305 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1306 }
1307 }
1308
1309 static unsigned si_tex_compare(unsigned compare)
1310 {
1311 switch (compare) {
1312 default:
1313 case PIPE_FUNC_NEVER:
1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1315 case PIPE_FUNC_LESS:
1316 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1317 case PIPE_FUNC_EQUAL:
1318 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1319 case PIPE_FUNC_LEQUAL:
1320 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1321 case PIPE_FUNC_GREATER:
1322 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1323 case PIPE_FUNC_NOTEQUAL:
1324 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1325 case PIPE_FUNC_GEQUAL:
1326 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1327 case PIPE_FUNC_ALWAYS:
1328 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1329 }
1330 }
1331
1332 static unsigned si_tex_dim(unsigned dim)
1333 {
1334 switch (dim) {
1335 default:
1336 case PIPE_TEXTURE_1D:
1337 return V_008F1C_SQ_RSRC_IMG_1D;
1338 case PIPE_TEXTURE_1D_ARRAY:
1339 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1340 case PIPE_TEXTURE_2D:
1341 case PIPE_TEXTURE_RECT:
1342 return V_008F1C_SQ_RSRC_IMG_2D;
1343 case PIPE_TEXTURE_2D_ARRAY:
1344 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1345 case PIPE_TEXTURE_3D:
1346 return V_008F1C_SQ_RSRC_IMG_3D;
1347 case PIPE_TEXTURE_CUBE:
1348 return V_008F1C_SQ_RSRC_IMG_CUBE;
1349 }
1350 }
1351
1352 /*
1353 * Format support testing
1354 */
1355
1356 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1357 {
1358 return si_translate_texformat(screen, format, util_format_description(format),
1359 util_format_get_first_non_void_channel(format)) != ~0U;
1360 }
1361
1362 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1363 enum pipe_format format,
1364 const struct util_format_description *desc,
1365 int first_non_void)
1366 {
1367 unsigned type = desc->channel[first_non_void].type;
1368 int i;
1369
1370 if (type == UTIL_FORMAT_TYPE_FIXED)
1371 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1372
1373 /* See whether the components are of the same size. */
1374 for (i = 0; i < desc->nr_channels; i++) {
1375 if (desc->channel[first_non_void].size != desc->channel[i].size)
1376 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1377 }
1378
1379 switch (desc->channel[first_non_void].size) {
1380 case 8:
1381 switch (desc->nr_channels) {
1382 case 1:
1383 return V_008F0C_BUF_DATA_FORMAT_8;
1384 case 2:
1385 return V_008F0C_BUF_DATA_FORMAT_8_8;
1386 case 3:
1387 case 4:
1388 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1389 }
1390 break;
1391 case 16:
1392 switch (desc->nr_channels) {
1393 case 1:
1394 return V_008F0C_BUF_DATA_FORMAT_16;
1395 case 2:
1396 return V_008F0C_BUF_DATA_FORMAT_16_16;
1397 case 3:
1398 case 4:
1399 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1400 }
1401 break;
1402 case 32:
1403 if (type != UTIL_FORMAT_TYPE_FLOAT)
1404 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1405
1406 switch (desc->nr_channels) {
1407 case 1:
1408 return V_008F0C_BUF_DATA_FORMAT_32;
1409 case 2:
1410 return V_008F0C_BUF_DATA_FORMAT_32_32;
1411 case 3:
1412 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1413 case 4:
1414 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1415 }
1416 break;
1417 }
1418
1419 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1420 }
1421
1422 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1423 {
1424 const struct util_format_description *desc;
1425 int first_non_void;
1426 unsigned data_format;
1427
1428 desc = util_format_description(format);
1429 first_non_void = util_format_get_first_non_void_channel(format);
1430 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1431 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1432 }
1433
1434 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1435 {
1436 return si_translate_colorformat(format) != ~0U &&
1437 si_translate_colorswap(format) != ~0U;
1438 }
1439
1440 static bool si_is_zs_format_supported(enum pipe_format format)
1441 {
1442 return si_translate_dbformat(format) != ~0U;
1443 }
1444
1445 bool si_is_format_supported(struct pipe_screen *screen,
1446 enum pipe_format format,
1447 enum pipe_texture_target target,
1448 unsigned sample_count,
1449 unsigned usage)
1450 {
1451 unsigned retval = 0;
1452
1453 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1454 R600_ERR("r600: unsupported texture type %d\n", target);
1455 return FALSE;
1456 }
1457
1458 if (!util_format_is_supported(format, usage))
1459 return FALSE;
1460
1461 /* Multisample */
1462 if (sample_count > 1)
1463 return FALSE;
1464
1465 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1466 si_is_sampler_format_supported(screen, format)) {
1467 retval |= PIPE_BIND_SAMPLER_VIEW;
1468 }
1469
1470 if ((usage & (PIPE_BIND_RENDER_TARGET |
1471 PIPE_BIND_DISPLAY_TARGET |
1472 PIPE_BIND_SCANOUT |
1473 PIPE_BIND_SHARED)) &&
1474 si_is_colorbuffer_format_supported(format)) {
1475 retval |= usage &
1476 (PIPE_BIND_RENDER_TARGET |
1477 PIPE_BIND_DISPLAY_TARGET |
1478 PIPE_BIND_SCANOUT |
1479 PIPE_BIND_SHARED);
1480 }
1481
1482 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1483 si_is_zs_format_supported(format)) {
1484 retval |= PIPE_BIND_DEPTH_STENCIL;
1485 }
1486
1487 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1488 si_is_vertex_format_supported(screen, format)) {
1489 retval |= PIPE_BIND_VERTEX_BUFFER;
1490 }
1491
1492 if (usage & PIPE_BIND_TRANSFER_READ)
1493 retval |= PIPE_BIND_TRANSFER_READ;
1494 if (usage & PIPE_BIND_TRANSFER_WRITE)
1495 retval |= PIPE_BIND_TRANSFER_WRITE;
1496
1497 return retval == usage;
1498 }
1499
1500 /*
1501 * framebuffer handling
1502 */
1503
1504 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1505 const struct pipe_framebuffer_state *state, int cb)
1506 {
1507 struct r600_resource_texture *rtex;
1508 struct r600_surface *surf;
1509 unsigned level = state->cbufs[cb]->u.tex.level;
1510 unsigned pitch, slice;
1511 unsigned color_info, color_attrib;
1512 unsigned format, swap, ntype, endian;
1513 uint64_t offset;
1514 unsigned blocksize;
1515 const struct util_format_description *desc;
1516 int i;
1517 unsigned blend_clamp = 0, blend_bypass = 0;
1518 unsigned max_comp_size;
1519
1520 surf = (struct r600_surface *)state->cbufs[cb];
1521 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1522 blocksize = util_format_get_blocksize(rtex->real_format);
1523
1524 if (rtex->depth)
1525 rctx->have_depth_fb = TRUE;
1526
1527 if (rtex->depth && !rtex->is_flushing_texture) {
1528 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1529 rtex = rtex->flushed_depth_texture;
1530 }
1531
1532 offset = rtex->surface.level[level].offset;
1533 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1534 offset += rtex->surface.level[level].slice_size *
1535 state->cbufs[cb]->u.tex.first_layer;
1536 }
1537 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1538 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1539 if (slice) {
1540 slice = slice - 1;
1541 }
1542
1543 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1544 switch (rtex->surface.level[level].mode) {
1545 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1546 color_attrib = S_028C74_TILE_MODE_INDEX(8);
1547 break;
1548 case RADEON_SURF_MODE_1D:
1549 color_attrib = S_028C74_TILE_MODE_INDEX(9);
1550 break;
1551 case RADEON_SURF_MODE_2D:
1552 if (rtex->resource.b.b.bind & PIPE_BIND_SCANOUT) {
1553 switch (blocksize) {
1554 case 1:
1555 color_attrib = S_028C74_TILE_MODE_INDEX(10);
1556 break;
1557 case 2:
1558 color_attrib = S_028C74_TILE_MODE_INDEX(11);
1559 break;
1560 case 4:
1561 color_attrib = S_028C74_TILE_MODE_INDEX(12);
1562 break;
1563 }
1564 break;
1565 } else switch (blocksize) {
1566 case 1:
1567 color_attrib = S_028C74_TILE_MODE_INDEX(14);
1568 break;
1569 case 2:
1570 color_attrib = S_028C74_TILE_MODE_INDEX(15);
1571 break;
1572 case 4:
1573 color_attrib = S_028C74_TILE_MODE_INDEX(16);
1574 break;
1575 case 8:
1576 color_attrib = S_028C74_TILE_MODE_INDEX(17);
1577 break;
1578 default:
1579 color_attrib = S_028C74_TILE_MODE_INDEX(13);
1580 }
1581 break;
1582 }
1583
1584 desc = util_format_description(surf->base.format);
1585 for (i = 0; i < 4; i++) {
1586 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1587 break;
1588 }
1589 }
1590 if (desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1591 ntype = V_028C70_NUMBER_FLOAT;
1592 } else {
1593 ntype = V_028C70_NUMBER_UNORM;
1594 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1595 ntype = V_028C70_NUMBER_SRGB;
1596 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1597 if (desc->channel[i].normalized)
1598 ntype = V_028C70_NUMBER_SNORM;
1599 else if (desc->channel[i].pure_integer)
1600 ntype = V_028C70_NUMBER_SINT;
1601 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1602 if (desc->channel[i].normalized)
1603 ntype = V_028C70_NUMBER_UNORM;
1604 else if (desc->channel[i].pure_integer)
1605 ntype = V_028C70_NUMBER_UINT;
1606 }
1607 }
1608
1609 format = si_translate_colorformat(surf->base.format);
1610 swap = si_translate_colorswap(surf->base.format);
1611 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1612 endian = V_028C70_ENDIAN_NONE;
1613 } else {
1614 endian = si_colorformat_endian_swap(format);
1615 }
1616
1617 /* blend clamp should be set for all NORM/SRGB types */
1618 if (ntype == V_028C70_NUMBER_UNORM ||
1619 ntype == V_028C70_NUMBER_SNORM ||
1620 ntype == V_028C70_NUMBER_SRGB)
1621 blend_clamp = 1;
1622
1623 /* set blend bypass according to docs if SINT/UINT or
1624 8/24 COLOR variants */
1625 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1626 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1627 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1628 blend_clamp = 0;
1629 blend_bypass = 1;
1630 }
1631
1632 color_info = S_028C70_FORMAT(format) |
1633 S_028C70_COMP_SWAP(swap) |
1634 S_028C70_BLEND_CLAMP(blend_clamp) |
1635 S_028C70_BLEND_BYPASS(blend_bypass) |
1636 S_028C70_NUMBER_TYPE(ntype) |
1637 S_028C70_ENDIAN(endian);
1638
1639 rctx->alpha_ref_dirty = true;
1640
1641 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1642 offset >>= 8;
1643
1644 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1645 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1646 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1647 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1648 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1649
1650 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1651 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1652 } else {
1653 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1654 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1655 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1656 }
1657 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1658 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1659
1660 /* Determine pixel shader export format */
1661 max_comp_size = si_colorformat_max_comp_size(format);
1662 if (ntype == V_028C70_NUMBER_SRGB ||
1663 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1664 max_comp_size <= 10) ||
1665 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1666 rctx->export_16bpc |= 1 << cb;
1667 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_FP16_ABGR << (4 * cb);
1668 } else
1669 rctx->spi_shader_col_format |= V_028714_SPI_SHADER_32_ABGR << (4 * cb);
1670 }
1671
1672 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1673 const struct pipe_framebuffer_state *state)
1674 {
1675 struct r600_resource_texture *rtex;
1676 struct r600_surface *surf;
1677 unsigned level, pitch, slice, format;
1678 uint32_t z_info, s_info;
1679 uint64_t z_offs, s_offs;
1680
1681 if (state->zsbuf == NULL) {
1682 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1683 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1684 return;
1685 }
1686
1687 surf = (struct r600_surface *)state->zsbuf;
1688 level = surf->base.u.tex.level;
1689 rtex = (struct r600_resource_texture*)surf->base.texture;
1690
1691 format = si_translate_dbformat(rtex->real_format);
1692
1693 z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1694 z_offs += rtex->surface.level[level].offset;
1695
1696 s_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1697 s_offs += rtex->surface.stencil_offset;
1698 z_offs += rtex->surface.level[level].offset / 4;
1699
1700 z_offs >>= 8;
1701 s_offs >>= 8;
1702
1703 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1704 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1705 if (slice) {
1706 slice = slice - 1;
1707 }
1708
1709 z_info = S_028040_FORMAT(format);
1710 s_info = S_028044_FORMAT(1);
1711
1712 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1713 z_info |= S_028040_TILE_MODE_INDEX(4);
1714 s_info |= S_028044_TILE_MODE_INDEX(4);
1715
1716 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1717 switch (format) {
1718 case V_028040_Z_16:
1719 z_info |= S_028040_TILE_MODE_INDEX(5);
1720 s_info |= S_028044_TILE_MODE_INDEX(5);
1721 break;
1722 case V_028040_Z_24:
1723 case V_028040_Z_32_FLOAT:
1724 z_info |= S_028040_TILE_MODE_INDEX(6);
1725 s_info |= S_028044_TILE_MODE_INDEX(6);
1726 break;
1727 default:
1728 z_info |= S_028040_TILE_MODE_INDEX(7);
1729 s_info |= S_028044_TILE_MODE_INDEX(7);
1730 }
1731
1732 } else {
1733 R600_ERR("Invalid DB tiling mode %d!\n",
1734 rtex->surface.level[level].mode);
1735 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1736 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1737 return;
1738 }
1739
1740 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1741 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1742 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1743
1744 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, 0x1);
1745 if (format != ~0U) {
1746 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1747
1748 } else {
1749 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, 0);
1750 }
1751
1752 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
1753 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1754 } else {
1755 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, 0);
1756 }
1757
1758 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1759 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1760 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1761 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1762 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1763
1764 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1765 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1766 }
1767
1768 static void si_set_framebuffer_state(struct pipe_context *ctx,
1769 const struct pipe_framebuffer_state *state)
1770 {
1771 struct r600_context *rctx = (struct r600_context *)ctx;
1772 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1773 uint32_t shader_mask, tl, br;
1774 int tl_x, tl_y, br_x, br_y;
1775
1776 if (pm4 == NULL)
1777 return;
1778
1779 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1780
1781 if (state->zsbuf)
1782 si_pm4_inval_zsbuf_cache(pm4);
1783
1784 util_copy_framebuffer_state(&rctx->framebuffer, state);
1785
1786 /* build states */
1787 rctx->have_depth_fb = 0;
1788 rctx->export_16bpc = 0;
1789 rctx->spi_shader_col_format = 0;
1790 for (int i = 0; i < state->nr_cbufs; i++) {
1791 si_cb(rctx, pm4, state, i);
1792 }
1793 assert(!(rctx->export_16bpc & ~0xff));
1794 si_db(rctx, pm4, state);
1795
1796 shader_mask = 0;
1797 for (int i = 0; i < state->nr_cbufs; i++) {
1798 shader_mask |= 0xf << (i * 4);
1799 }
1800 tl_x = 0;
1801 tl_y = 0;
1802 br_x = state->width;
1803 br_y = state->height;
1804
1805 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1806 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1807
1808 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1809 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1810 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1811 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1812 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1813 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1814 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1815 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1816 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1817 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1818 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1819 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
1820 rctx->spi_shader_col_format);
1821 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1822
1823 si_pm4_set_state(rctx, framebuffer, pm4);
1824 si_update_fb_rs_state(rctx);
1825 si_update_fb_blend_state(rctx);
1826 }
1827
1828 /*
1829 * shaders
1830 */
1831
1832 /* Compute the key for the hw shader variant */
1833 static INLINE unsigned si_shader_selector_key(struct pipe_context *ctx,
1834 struct si_pipe_shader_selector *sel)
1835 {
1836 struct r600_context *rctx = (struct r600_context *)ctx;
1837 unsigned key = 0;
1838
1839 if (sel->type == PIPE_SHADER_FRAGMENT) {
1840 if (sel->fs_write_all)
1841 key |= rctx->framebuffer.nr_cbufs;
1842 key |= rctx->export_16bpc << 4;
1843 /*if (rctx->queued.named.rasterizer)
1844 key |= rctx->queued.named.rasterizer->flatshade << 12;*/
1845 /*key |== rctx->two_side << 13;*/
1846 }
1847
1848 return key;
1849 }
1850
1851 /* Select the hw shader variant depending on the current state.
1852 * (*dirty) is set to 1 if current variant was changed */
1853 int si_shader_select(struct pipe_context *ctx,
1854 struct si_pipe_shader_selector *sel,
1855 unsigned *dirty)
1856 {
1857 unsigned key;
1858 struct si_pipe_shader * shader = NULL;
1859 int r;
1860
1861 key = si_shader_selector_key(ctx, sel);
1862
1863 /* Check if we don't need to change anything.
1864 * This path is also used for most shaders that don't need multiple
1865 * variants, it will cost just a computation of the key and this
1866 * test. */
1867 if (likely(sel->current && sel->current->key == key)) {
1868 return 0;
1869 }
1870
1871 /* lookup if we have other variants in the list */
1872 if (sel->num_shaders > 1) {
1873 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1874
1875 while (c && c->key != key) {
1876 p = c;
1877 c = c->next_variant;
1878 }
1879
1880 if (c) {
1881 p->next_variant = c->next_variant;
1882 shader = c;
1883 }
1884 }
1885
1886 if (unlikely(!shader)) {
1887 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1888 shader->selector = sel;
1889
1890 r = si_pipe_shader_create(ctx, shader);
1891 if (unlikely(r)) {
1892 R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
1893 sel->type, key, r);
1894 sel->current = NULL;
1895 return r;
1896 }
1897
1898 /* We don't know the value of fs_write_all property until we built
1899 * at least one variant, so we may need to recompute the key (include
1900 * rctx->framebuffer.nr_cbufs) after building first variant. */
1901 if (sel->type == PIPE_SHADER_FRAGMENT &&
1902 sel->num_shaders == 0 &&
1903 shader->shader.fs_write_all) {
1904 sel->fs_write_all = 1;
1905 key = si_shader_selector_key(ctx, sel);
1906 }
1907
1908 shader->key = key;
1909 sel->num_shaders++;
1910 }
1911
1912 if (dirty)
1913 *dirty = 1;
1914
1915 shader->next_variant = sel->current;
1916 sel->current = shader;
1917
1918 return 0;
1919 }
1920
1921 static void *si_create_shader_state(struct pipe_context *ctx,
1922 const struct pipe_shader_state *state,
1923 unsigned pipe_shader_type)
1924 {
1925 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1926 int r;
1927
1928 sel->type = pipe_shader_type;
1929 sel->tokens = tgsi_dup_tokens(state->tokens);
1930 sel->so = state->stream_output;
1931
1932 r = si_shader_select(ctx, sel, NULL);
1933 if (r) {
1934 free(sel);
1935 return NULL;
1936 }
1937
1938 return sel;
1939 }
1940
1941 static void *si_create_fs_state(struct pipe_context *ctx,
1942 const struct pipe_shader_state *state)
1943 {
1944 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1945 }
1946
1947 static void *si_create_vs_state(struct pipe_context *ctx,
1948 const struct pipe_shader_state *state)
1949 {
1950 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
1951 }
1952
1953 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1954 {
1955 struct r600_context *rctx = (struct r600_context *)ctx;
1956 struct si_pipe_shader_selector *sel = state;
1957
1958 if (rctx->vs_shader == sel)
1959 return;
1960
1961 rctx->vs_shader = sel;
1962
1963 if (sel && sel->current)
1964 si_pm4_bind_state(rctx, vs, sel->current->pm4);
1965 else
1966 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
1967 }
1968
1969 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1970 {
1971 struct r600_context *rctx = (struct r600_context *)ctx;
1972 struct si_pipe_shader_selector *sel = state;
1973
1974 if (rctx->ps_shader == sel)
1975 return;
1976
1977 rctx->ps_shader = sel;
1978
1979 if (sel && sel->current)
1980 si_pm4_bind_state(rctx, ps, sel->current->pm4);
1981 else
1982 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
1983 }
1984
1985 static void si_delete_shader_selector(struct pipe_context *ctx,
1986 struct si_pipe_shader_selector *sel)
1987 {
1988 struct r600_context *rctx = (struct r600_context *)ctx;
1989 struct si_pipe_shader *p = sel->current, *c;
1990
1991 while (p) {
1992 c = p->next_variant;
1993 si_pm4_delete_state(rctx, vs, p->pm4);
1994 si_pipe_shader_destroy(ctx, p);
1995 free(p);
1996 p = c;
1997 }
1998
1999 free(sel->tokens);
2000 free(sel);
2001 }
2002
2003 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2004 {
2005 struct r600_context *rctx = (struct r600_context *)ctx;
2006 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2007
2008 if (rctx->vs_shader == sel) {
2009 rctx->vs_shader = NULL;
2010 }
2011
2012 si_delete_shader_selector(ctx, sel);
2013 }
2014
2015 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2016 {
2017 struct r600_context *rctx = (struct r600_context *)ctx;
2018 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2019
2020 if (rctx->ps_shader == sel) {
2021 rctx->ps_shader = NULL;
2022 }
2023
2024 si_delete_shader_selector(ctx, sel);
2025 }
2026
2027 /*
2028 * Samplers
2029 */
2030
2031 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2032 struct pipe_resource *texture,
2033 const struct pipe_sampler_view *state)
2034 {
2035 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2036 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2037 const struct util_format_description *desc = util_format_description(state->format);
2038 unsigned blocksize = util_format_get_blocksize(tmp->real_format);
2039 unsigned format, num_format, /*endian,*/ tiling_index;
2040 uint32_t pitch = 0;
2041 unsigned char state_swizzle[4], swizzle[4];
2042 unsigned height, depth, width;
2043 int first_non_void;
2044 uint64_t va;
2045
2046 if (view == NULL)
2047 return NULL;
2048
2049 /* initialize base object */
2050 view->base = *state;
2051 view->base.texture = NULL;
2052 pipe_reference(NULL, &texture->reference);
2053 view->base.texture = texture;
2054 view->base.reference.count = 1;
2055 view->base.context = ctx;
2056
2057 state_swizzle[0] = state->swizzle_r;
2058 state_swizzle[1] = state->swizzle_g;
2059 state_swizzle[2] = state->swizzle_b;
2060 state_swizzle[3] = state->swizzle_a;
2061 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2062
2063 first_non_void = util_format_get_first_non_void_channel(state->format);
2064 switch (desc->channel[first_non_void].type) {
2065 case UTIL_FORMAT_TYPE_FLOAT:
2066 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2067 break;
2068 case UTIL_FORMAT_TYPE_SIGNED:
2069 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2070 break;
2071 case UTIL_FORMAT_TYPE_UNSIGNED:
2072 default:
2073 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2074 }
2075
2076 format = si_translate_texformat(ctx->screen, state->format, desc, first_non_void);
2077 if (format == ~0) {
2078 format = 0;
2079 }
2080
2081 if (tmp->depth && !tmp->is_flushing_texture) {
2082 r600_texture_depth_flush(ctx, texture, TRUE);
2083 tmp = tmp->flushed_depth_texture;
2084 }
2085
2086 /* not supported any more */
2087 //endian = si_colorformat_endian_swap(format);
2088
2089 width = tmp->surface.level[0].npix_x;
2090 height = tmp->surface.level[0].npix_y;
2091 depth = tmp->surface.level[0].npix_z;
2092 pitch = tmp->surface.level[0].nblk_x * util_format_get_blockwidth(state->format);
2093
2094 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2095 height = 1;
2096 depth = texture->array_size;
2097 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2098 depth = texture->array_size;
2099 }
2100
2101 tiling_index = 8;
2102 switch (tmp->surface.level[0].mode) {
2103 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2104 tiling_index = 8;
2105 break;
2106 case RADEON_SURF_MODE_1D:
2107 tiling_index = 9;
2108 break;
2109 case RADEON_SURF_MODE_2D:
2110 if (tmp->resource.b.b.bind & PIPE_BIND_SCANOUT) {
2111 switch (blocksize) {
2112 case 1:
2113 tiling_index = 10;
2114 break;
2115 case 2:
2116 tiling_index = 11;
2117 break;
2118 case 4:
2119 tiling_index = 12;
2120 break;
2121 }
2122 break;
2123 } else switch (blocksize) {
2124 case 1:
2125 tiling_index = 14;
2126 break;
2127 case 2:
2128 tiling_index = 15;
2129 break;
2130 case 4:
2131 tiling_index = 16;
2132 break;
2133 case 8:
2134 tiling_index = 17;
2135 break;
2136 default:
2137 tiling_index = 13;
2138 }
2139 break;
2140 }
2141
2142 va = r600_resource_va(ctx->screen, texture);
2143 va += tmp->surface.level[0].offset;
2144 view->state[0] = va >> 8;
2145 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2146 S_008F14_DATA_FORMAT(format) |
2147 S_008F14_NUM_FORMAT(num_format));
2148 view->state[2] = (S_008F18_WIDTH(width - 1) |
2149 S_008F18_HEIGHT(height - 1));
2150 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2151 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2152 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2153 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2154 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2155 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2156 S_008F1C_TILING_INDEX(tiling_index) |
2157 S_008F1C_POW2_PAD(texture->last_level > 0) |
2158 S_008F1C_TYPE(si_tex_dim(texture->target)));
2159 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2160 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2161 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2162 view->state[6] = 0;
2163 view->state[7] = 0;
2164
2165 return &view->base;
2166 }
2167
2168 static void si_sampler_view_destroy(struct pipe_context *ctx,
2169 struct pipe_sampler_view *state)
2170 {
2171 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2172
2173 pipe_resource_reference(&state->texture, NULL);
2174 FREE(resource);
2175 }
2176
2177 static void *si_create_sampler_state(struct pipe_context *ctx,
2178 const struct pipe_sampler_state *state)
2179 {
2180 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2181 union util_color uc;
2182 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2183 unsigned border_color_type;
2184
2185 if (rstate == NULL) {
2186 return NULL;
2187 }
2188
2189 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2190 switch (uc.ui) {
2191 case 0x000000FF:
2192 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2193 break;
2194 case 0x00000000:
2195 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2196 break;
2197 case 0xFFFFFFFF:
2198 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2199 break;
2200 default: /* Use border color pointer */
2201 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2202 }
2203
2204 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2205 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2206 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2207 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2208 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2209 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2210 aniso_flag_offset << 16 | /* XXX */
2211 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2212 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2213 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2214 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2215 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2216 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2217 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2218 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2219
2220 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2221 memcpy(rstate->border_color, state->border_color.f,
2222 sizeof(rstate->border_color));
2223 }
2224
2225 return rstate;
2226 }
2227
2228 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2229 struct pipe_sampler_view **views)
2230 {
2231 assert(count == 0);
2232 }
2233
2234 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2235 struct pipe_sampler_view **views)
2236 {
2237 struct r600_context *rctx = (struct r600_context *)ctx;
2238 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2239 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2240 int i, j;
2241 int has_depth = 0;
2242
2243 if (!count)
2244 goto out;
2245
2246 si_pm4_inval_texture_cache(pm4);
2247
2248 si_pm4_sh_data_begin(pm4);
2249 for (i = 0; i < count; i++) {
2250 pipe_sampler_view_reference(
2251 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
2252 views[i]);
2253
2254 if (views[i]) {
2255 struct r600_resource_texture *tex = (void *)resource[i]->base.texture;
2256
2257 si_pm4_add_bo(pm4, &tex->resource, RADEON_USAGE_READ);
2258 }
2259
2260 for (j = 0; j < Elements(resource[i]->state); ++j) {
2261 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2262 }
2263 }
2264
2265 for (i = count; i < NUM_TEX_UNITS; i++) {
2266 if (rctx->ps_samplers.views[i])
2267 pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
2268 }
2269
2270 si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_RESOURCE);
2271
2272 out:
2273 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2274 rctx->have_depth_texture = has_depth;
2275 rctx->ps_samplers.n_views = count;
2276 }
2277
2278 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2279 {
2280 assert(count == 0);
2281 }
2282
2283 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2284 {
2285 struct r600_context *rctx = (struct r600_context *)ctx;
2286 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2287 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2288 uint32_t *border_color_table = NULL;
2289 int i, j;
2290
2291 if (!count)
2292 goto out;
2293
2294 si_pm4_inval_texture_cache(pm4);
2295
2296 si_pm4_sh_data_begin(pm4);
2297 for (i = 0; i < count; i++) {
2298 if (rstates[i] &&
2299 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2300 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2301 if (!rctx->border_color_table ||
2302 ((rctx->border_color_offset + count - i) &
2303 C_008F3C_BORDER_COLOR_PTR)) {
2304 si_resource_reference(&rctx->border_color_table, NULL);
2305 rctx->border_color_offset = 0;
2306
2307 rctx->border_color_table =
2308 si_resource_create_custom(ctx->screen,
2309 PIPE_USAGE_STAGING,
2310 4096 * 4 * 4);
2311 }
2312
2313 if (!border_color_table) {
2314 border_color_table =
2315 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2316 rctx->cs,
2317 PIPE_TRANSFER_WRITE |
2318 PIPE_TRANSFER_UNSYNCHRONIZED);
2319 }
2320
2321 for (j = 0; j < 4; j++) {
2322 union fi border_color;
2323
2324 border_color.f = rstates[i]->border_color[j];
2325 border_color_table[4 * rctx->border_color_offset + j] =
2326 util_le32_to_cpu(border_color.i);
2327 }
2328
2329 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2330 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2331 }
2332
2333 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2334 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2335 }
2336 }
2337 si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_SAMPLER);
2338
2339 if (border_color_table) {
2340 uint64_t va_offset =
2341 r600_resource_va(ctx->screen, (void*)rctx->border_color_table);
2342
2343 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2344 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2345 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2346 }
2347
2348 memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
2349
2350 out:
2351 si_pm4_set_state(rctx, ps_sampler, pm4);
2352 rctx->ps_samplers.n_samplers = count;
2353 }
2354
2355 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2356 {
2357 }
2358
2359 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2360 {
2361 free(state);
2362 }
2363
2364 /*
2365 * Constants
2366 */
2367 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2368 struct pipe_constant_buffer *cb)
2369 {
2370 struct r600_context *rctx = (struct r600_context *)ctx;
2371 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2372 struct si_pm4_state *pm4;
2373 uint64_t va_offset;
2374 uint32_t reg, offset;
2375
2376 /* Note that the state tracker can unbind constant buffers by
2377 * passing NULL here.
2378 */
2379 if (cb == NULL)
2380 return;
2381
2382 pm4 = CALLOC_STRUCT(si_pm4_state);
2383 si_pm4_inval_shader_cache(pm4);
2384
2385 if (cb->user_buffer)
2386 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2387 else
2388 offset = 0;
2389 va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
2390 va_offset += offset;
2391
2392 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2393
2394 switch (shader) {
2395 case PIPE_SHADER_VERTEX:
2396 reg = R_00B130_SPI_SHADER_USER_DATA_VS_0 + SI_SGPR_CONST * 4;
2397 si_pm4_set_reg(pm4, reg, va_offset);
2398 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2399 si_pm4_set_state(rctx, vs_const, pm4);
2400 break;
2401
2402 case PIPE_SHADER_FRAGMENT:
2403 reg = R_00B030_SPI_SHADER_USER_DATA_PS_0 + SI_SGPR_CONST * 4;
2404 si_pm4_set_reg(pm4, reg, va_offset);
2405 si_pm4_set_reg(pm4, reg + 4, va_offset >> 32);
2406 si_pm4_set_state(rctx, ps_const, pm4);
2407 break;
2408
2409 default:
2410 R600_ERR("unsupported %d\n", shader);
2411 }
2412
2413 if (cb->buffer != &rbuffer->b.b)
2414 si_resource_reference(&rbuffer, NULL);
2415 }
2416
2417 /*
2418 * Vertex elements & buffers
2419 */
2420
2421 static void *si_create_vertex_elements(struct pipe_context *ctx,
2422 unsigned count,
2423 const struct pipe_vertex_element *elements)
2424 {
2425 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2426 int i;
2427
2428 assert(count < PIPE_MAX_ATTRIBS);
2429 if (!v)
2430 return NULL;
2431
2432 v->count = count;
2433 for (i = 0; i < count; ++i) {
2434 const struct util_format_description *desc;
2435 unsigned data_format, num_format;
2436 int first_non_void;
2437
2438 desc = util_format_description(elements[i].src_format);
2439 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2440 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2441 desc, first_non_void);
2442
2443 switch (desc->channel[first_non_void].type) {
2444 case UTIL_FORMAT_TYPE_FIXED:
2445 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2446 break;
2447 case UTIL_FORMAT_TYPE_SIGNED:
2448 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2449 break;
2450 case UTIL_FORMAT_TYPE_UNSIGNED:
2451 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2452 break;
2453 case UTIL_FORMAT_TYPE_FLOAT:
2454 default:
2455 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2456 }
2457
2458 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2459 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2460 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2461 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2462 S_008F0C_NUM_FORMAT(num_format) |
2463 S_008F0C_DATA_FORMAT(data_format);
2464 }
2465 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2466
2467 return v;
2468 }
2469
2470 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2471 {
2472 struct r600_context *rctx = (struct r600_context *)ctx;
2473 struct si_vertex_element *v = (struct si_vertex_element*)state;
2474
2475 rctx->vertex_elements = v;
2476 }
2477
2478 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2479 {
2480 struct r600_context *rctx = (struct r600_context *)ctx;
2481
2482 if (rctx->vertex_elements == state)
2483 rctx->vertex_elements = NULL;
2484 FREE(state);
2485 }
2486
2487 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
2488 const struct pipe_vertex_buffer *buffers)
2489 {
2490 struct r600_context *rctx = (struct r600_context *)ctx;
2491
2492 util_copy_vertex_buffers(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, count);
2493 }
2494
2495 static void si_set_index_buffer(struct pipe_context *ctx,
2496 const struct pipe_index_buffer *ib)
2497 {
2498 struct r600_context *rctx = (struct r600_context *)ctx;
2499
2500 if (ib) {
2501 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2502 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2503 } else {
2504 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2505 }
2506 }
2507
2508 /*
2509 * Misc
2510 */
2511 static void si_set_polygon_stipple(struct pipe_context *ctx,
2512 const struct pipe_poly_stipple *state)
2513 {
2514 }
2515
2516 static void si_texture_barrier(struct pipe_context *ctx)
2517 {
2518 struct r600_context *rctx = (struct r600_context *)ctx;
2519 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2520
2521 si_pm4_inval_texture_cache(pm4);
2522 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2523 si_pm4_set_state(rctx, texture_barrier, pm4);
2524 }
2525
2526 void si_init_state_functions(struct r600_context *rctx)
2527 {
2528 rctx->context.create_blend_state = si_create_blend_state;
2529 rctx->context.bind_blend_state = si_bind_blend_state;
2530 rctx->context.delete_blend_state = si_delete_blend_state;
2531 rctx->context.set_blend_color = si_set_blend_color;
2532
2533 rctx->context.create_rasterizer_state = si_create_rs_state;
2534 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2535 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2536
2537 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2538 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2539 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2540 rctx->custom_dsa_flush = si_create_db_flush_dsa(rctx);
2541
2542 rctx->context.set_clip_state = si_set_clip_state;
2543 rctx->context.set_scissor_state = si_set_scissor_state;
2544 rctx->context.set_viewport_state = si_set_viewport_state;
2545 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2546
2547 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2548
2549 rctx->context.create_vs_state = si_create_vs_state;
2550 rctx->context.create_fs_state = si_create_fs_state;
2551 rctx->context.bind_vs_state = si_bind_vs_shader;
2552 rctx->context.bind_fs_state = si_bind_ps_shader;
2553 rctx->context.delete_vs_state = si_delete_vs_shader;
2554 rctx->context.delete_fs_state = si_delete_ps_shader;
2555
2556 rctx->context.create_sampler_state = si_create_sampler_state;
2557 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2558 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2559 rctx->context.delete_sampler_state = si_delete_sampler_state;
2560
2561 rctx->context.create_sampler_view = si_create_sampler_view;
2562 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2563 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2564 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2565
2566 rctx->context.set_sample_mask = si_set_sample_mask;
2567
2568 rctx->context.set_constant_buffer = si_set_constant_buffer;
2569
2570 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2571 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2572 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2573 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2574 rctx->context.set_index_buffer = si_set_index_buffer;
2575
2576 rctx->context.create_stream_output_target = si_create_so_target;
2577 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2578 rctx->context.set_stream_output_targets = si_set_so_targets;
2579
2580 rctx->context.texture_barrier = si_texture_barrier;
2581 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2582
2583 rctx->context.draw_vbo = si_draw_vbo;
2584 }
2585
2586 void si_init_config(struct r600_context *rctx)
2587 {
2588 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2589
2590 si_cmd_context_control(pm4);
2591
2592 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2593
2594 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2595 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2596 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2597 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2598 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2599 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2600 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2601 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2602 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2603 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2604 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2605 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2606 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2607 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2608 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2609 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2610 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2611 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2612 S_028AA8_SWITCH_ON_EOP(1) |
2613 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2614 S_028AA8_PRIMGROUP_SIZE(63));
2615 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2616 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2617 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, (3 << 1) | 1);
2618
2619 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2620 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2621 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2622
2623 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2624
2625 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2626
2627 si_pm4_set_state(rctx, init, pm4);
2628 }