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r600g,radeonsi: fix initialized buffer range tracking for DMA, add comments
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "tgsi/tgsi_scan.h"
37 #include "radeonsi_pipe.h"
38 #include "radeonsi_shader.h"
39 #include "si_state.h"
40 #include "../radeon/r600_cs.h"
41 #include "sid.h"
42
43 static uint32_t cik_num_banks(uint32_t nbanks)
44 {
45 switch (nbanks) {
46 case 2:
47 return V_02803C_ADDR_SURF_2_BANK;
48 case 4:
49 return V_02803C_ADDR_SURF_4_BANK;
50 case 8:
51 default:
52 return V_02803C_ADDR_SURF_8_BANK;
53 case 16:
54 return V_02803C_ADDR_SURF_16_BANK;
55 }
56 }
57
58
59 static unsigned cik_tile_split(unsigned tile_split)
60 {
61 switch (tile_split) {
62 case 64:
63 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
64 break;
65 case 128:
66 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
67 break;
68 case 256:
69 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
70 break;
71 case 512:
72 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
73 break;
74 default:
75 case 1024:
76 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
77 break;
78 case 2048:
79 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
80 break;
81 case 4096:
82 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
83 break;
84 }
85 return tile_split;
86 }
87
88 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
89 {
90 switch (macro_tile_aspect) {
91 default:
92 case 1:
93 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
94 break;
95 case 2:
96 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
97 break;
98 case 4:
99 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
100 break;
101 case 8:
102 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
103 break;
104 }
105 return macro_tile_aspect;
106 }
107
108 static unsigned cik_bank_wh(unsigned bankwh)
109 {
110 switch (bankwh) {
111 default:
112 case 1:
113 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
114 break;
115 case 2:
116 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
117 break;
118 case 4:
119 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
120 break;
121 case 8:
122 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
123 break;
124 }
125 return bankwh;
126 }
127
128 static unsigned cik_db_pipe_config(unsigned tile_pipes,
129 unsigned num_rbs)
130 {
131 unsigned pipe_config;
132
133 switch (tile_pipes) {
134 case 8:
135 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
136 break;
137 case 4:
138 default:
139 if (num_rbs == 4)
140 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
141 else
142 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
143 break;
144 case 2:
145 pipe_config = V_02803C_ADDR_SURF_P2;
146 break;
147 }
148 return pipe_config;
149 }
150
151 /*
152 * inferred framebuffer and blender state
153 */
154 static void si_update_fb_blend_state(struct r600_context *rctx)
155 {
156 struct si_pm4_state *pm4;
157 struct si_state_blend *blend = rctx->queued.named.blend;
158 uint32_t mask;
159
160 if (blend == NULL)
161 return;
162
163 pm4 = si_pm4_alloc_state(rctx);
164 if (pm4 == NULL)
165 return;
166
167 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
168 mask &= blend->cb_target_mask;
169 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
170
171 si_pm4_set_state(rctx, fb_blend, pm4);
172 }
173
174 /*
175 * Blender functions
176 */
177
178 static uint32_t si_translate_blend_function(int blend_func)
179 {
180 switch (blend_func) {
181 case PIPE_BLEND_ADD:
182 return V_028780_COMB_DST_PLUS_SRC;
183 case PIPE_BLEND_SUBTRACT:
184 return V_028780_COMB_SRC_MINUS_DST;
185 case PIPE_BLEND_REVERSE_SUBTRACT:
186 return V_028780_COMB_DST_MINUS_SRC;
187 case PIPE_BLEND_MIN:
188 return V_028780_COMB_MIN_DST_SRC;
189 case PIPE_BLEND_MAX:
190 return V_028780_COMB_MAX_DST_SRC;
191 default:
192 R600_ERR("Unknown blend function %d\n", blend_func);
193 assert(0);
194 break;
195 }
196 return 0;
197 }
198
199 static uint32_t si_translate_blend_factor(int blend_fact)
200 {
201 switch (blend_fact) {
202 case PIPE_BLENDFACTOR_ONE:
203 return V_028780_BLEND_ONE;
204 case PIPE_BLENDFACTOR_SRC_COLOR:
205 return V_028780_BLEND_SRC_COLOR;
206 case PIPE_BLENDFACTOR_SRC_ALPHA:
207 return V_028780_BLEND_SRC_ALPHA;
208 case PIPE_BLENDFACTOR_DST_ALPHA:
209 return V_028780_BLEND_DST_ALPHA;
210 case PIPE_BLENDFACTOR_DST_COLOR:
211 return V_028780_BLEND_DST_COLOR;
212 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
213 return V_028780_BLEND_SRC_ALPHA_SATURATE;
214 case PIPE_BLENDFACTOR_CONST_COLOR:
215 return V_028780_BLEND_CONSTANT_COLOR;
216 case PIPE_BLENDFACTOR_CONST_ALPHA:
217 return V_028780_BLEND_CONSTANT_ALPHA;
218 case PIPE_BLENDFACTOR_ZERO:
219 return V_028780_BLEND_ZERO;
220 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
221 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
222 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
223 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
224 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
225 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
226 case PIPE_BLENDFACTOR_INV_DST_COLOR:
227 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
228 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
229 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
230 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
231 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
232 case PIPE_BLENDFACTOR_SRC1_COLOR:
233 return V_028780_BLEND_SRC1_COLOR;
234 case PIPE_BLENDFACTOR_SRC1_ALPHA:
235 return V_028780_BLEND_SRC1_ALPHA;
236 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
237 return V_028780_BLEND_INV_SRC1_COLOR;
238 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
239 return V_028780_BLEND_INV_SRC1_ALPHA;
240 default:
241 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
242 assert(0);
243 break;
244 }
245 return 0;
246 }
247
248 static void *si_create_blend_state_mode(struct pipe_context *ctx,
249 const struct pipe_blend_state *state,
250 unsigned mode)
251 {
252 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
253 struct si_pm4_state *pm4 = &blend->pm4;
254
255 uint32_t color_control;
256
257 if (blend == NULL)
258 return NULL;
259
260 blend->alpha_to_one = state->alpha_to_one;
261
262 color_control = S_028808_MODE(mode);
263 if (state->logicop_enable) {
264 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
265 } else {
266 color_control |= S_028808_ROP3(0xcc);
267 }
268 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
269
270 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
271 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
272 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
273 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
274 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
275 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
276
277 blend->cb_target_mask = 0;
278 for (int i = 0; i < 8; i++) {
279 /* state->rt entries > 0 only written if independent blending */
280 const int j = state->independent_blend_enable ? i : 0;
281
282 unsigned eqRGB = state->rt[j].rgb_func;
283 unsigned srcRGB = state->rt[j].rgb_src_factor;
284 unsigned dstRGB = state->rt[j].rgb_dst_factor;
285 unsigned eqA = state->rt[j].alpha_func;
286 unsigned srcA = state->rt[j].alpha_src_factor;
287 unsigned dstA = state->rt[j].alpha_dst_factor;
288
289 unsigned blend_cntl = 0;
290
291 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
292 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
293
294 if (!state->rt[j].blend_enable) {
295 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
296 continue;
297 }
298
299 blend_cntl |= S_028780_ENABLE(1);
300 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
301 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
302 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
303
304 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
305 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
306 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
307 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
308 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
309 }
310 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
311 }
312
313 return blend;
314 }
315
316 static void *si_create_blend_state(struct pipe_context *ctx,
317 const struct pipe_blend_state *state)
318 {
319 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
320 }
321
322 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
323 {
324 struct r600_context *rctx = (struct r600_context *)ctx;
325 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
326 si_update_fb_blend_state(rctx);
327 }
328
329 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
330 {
331 struct r600_context *rctx = (struct r600_context *)ctx;
332 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
333 }
334
335 static void si_set_blend_color(struct pipe_context *ctx,
336 const struct pipe_blend_color *state)
337 {
338 struct r600_context *rctx = (struct r600_context *)ctx;
339 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
340
341 if (pm4 == NULL)
342 return;
343
344 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
345 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
346 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
347 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
348
349 si_pm4_set_state(rctx, blend_color, pm4);
350 }
351
352 /*
353 * Clipping, scissors and viewport
354 */
355
356 static void si_set_clip_state(struct pipe_context *ctx,
357 const struct pipe_clip_state *state)
358 {
359 struct r600_context *rctx = (struct r600_context *)ctx;
360 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
361 struct pipe_constant_buffer cb;
362
363 if (pm4 == NULL)
364 return;
365
366 for (int i = 0; i < 6; i++) {
367 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
368 fui(state->ucp[i][0]));
369 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
370 fui(state->ucp[i][1]));
371 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
372 fui(state->ucp[i][2]));
373 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
374 fui(state->ucp[i][3]));
375 }
376
377 cb.buffer = NULL;
378 cb.user_buffer = state->ucp;
379 cb.buffer_offset = 0;
380 cb.buffer_size = 4*4*8;
381 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, NUM_PIPE_CONST_BUFFERS, &cb);
382 pipe_resource_reference(&cb.buffer, NULL);
383
384 si_pm4_set_state(rctx, clip, pm4);
385 }
386
387 static void si_set_scissor_states(struct pipe_context *ctx,
388 unsigned start_slot,
389 unsigned num_scissors,
390 const struct pipe_scissor_state *state)
391 {
392 struct r600_context *rctx = (struct r600_context *)ctx;
393 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
394 uint32_t tl, br;
395
396 if (pm4 == NULL)
397 return;
398
399 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
400 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
401 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
402 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
403 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
404 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
405 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
406 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
407 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
408 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
409
410 si_pm4_set_state(rctx, scissor, pm4);
411 }
412
413 static void si_set_viewport_states(struct pipe_context *ctx,
414 unsigned start_slot,
415 unsigned num_viewports,
416 const struct pipe_viewport_state *state)
417 {
418 struct r600_context *rctx = (struct r600_context *)ctx;
419 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
420 struct si_pm4_state *pm4 = &viewport->pm4;
421
422 if (viewport == NULL)
423 return;
424
425 viewport->viewport = *state;
426 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
427 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
428 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
429 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
430 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
431 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
432 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
433 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
434 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
435
436 si_pm4_set_state(rctx, viewport, viewport);
437 }
438
439 /*
440 * inferred state between framebuffer and rasterizer
441 */
442 static void si_update_fb_rs_state(struct r600_context *rctx)
443 {
444 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
445 struct si_pm4_state *pm4;
446 unsigned offset_db_fmt_cntl = 0, depth;
447 float offset_units;
448
449 if (!rs || !rctx->framebuffer.zsbuf)
450 return;
451
452 offset_units = rctx->queued.named.rasterizer->offset_units;
453 switch (rctx->framebuffer.zsbuf->texture->format) {
454 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
455 case PIPE_FORMAT_X8Z24_UNORM:
456 case PIPE_FORMAT_Z24X8_UNORM:
457 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
458 depth = -24;
459 offset_units *= 2.0f;
460 break;
461 case PIPE_FORMAT_Z32_FLOAT:
462 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
463 depth = -23;
464 offset_units *= 1.0f;
465 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
466 break;
467 case PIPE_FORMAT_Z16_UNORM:
468 depth = -16;
469 offset_units *= 4.0f;
470 break;
471 default:
472 return;
473 }
474
475 pm4 = si_pm4_alloc_state(rctx);
476
477 if (pm4 == NULL)
478 return;
479
480 /* FIXME some of those reg can be computed with cso */
481 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
482 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
483 fui(rctx->queued.named.rasterizer->offset_scale));
484 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
485 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
486 fui(rctx->queued.named.rasterizer->offset_scale));
487 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
488 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
489
490 si_pm4_set_state(rctx, fb_rs, pm4);
491 }
492
493 /*
494 * Rasterizer
495 */
496
497 static uint32_t si_translate_fill(uint32_t func)
498 {
499 switch(func) {
500 case PIPE_POLYGON_MODE_FILL:
501 return V_028814_X_DRAW_TRIANGLES;
502 case PIPE_POLYGON_MODE_LINE:
503 return V_028814_X_DRAW_LINES;
504 case PIPE_POLYGON_MODE_POINT:
505 return V_028814_X_DRAW_POINTS;
506 default:
507 assert(0);
508 return V_028814_X_DRAW_POINTS;
509 }
510 }
511
512 static void *si_create_rs_state(struct pipe_context *ctx,
513 const struct pipe_rasterizer_state *state)
514 {
515 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
516 struct si_pm4_state *pm4 = &rs->pm4;
517 unsigned tmp;
518 unsigned prov_vtx = 1, polygon_dual_mode;
519 unsigned clip_rule;
520 float psize_min, psize_max;
521
522 if (rs == NULL) {
523 return NULL;
524 }
525
526 rs->two_side = state->light_twoside;
527 rs->multisample_enable = state->multisample;
528 rs->clip_plane_enable = state->clip_plane_enable;
529 rs->line_stipple_enable = state->line_stipple_enable;
530
531 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
532 state->fill_back != PIPE_POLYGON_MODE_FILL);
533
534 if (state->flatshade_first)
535 prov_vtx = 0;
536
537 rs->flatshade = state->flatshade;
538 rs->sprite_coord_enable = state->sprite_coord_enable;
539 rs->pa_sc_line_stipple = state->line_stipple_enable ?
540 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
541 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
542 rs->pa_su_sc_mode_cntl =
543 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
544 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
545 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
546 S_028814_FACE(!state->front_ccw) |
547 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
548 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
549 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
550 S_028814_POLY_MODE(polygon_dual_mode) |
551 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
552 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
553 rs->pa_cl_clip_cntl =
554 S_028810_PS_UCP_MODE(3) |
555 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
556 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
557 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
558 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
559
560 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
561
562 /* offset */
563 rs->offset_units = state->offset_units;
564 rs->offset_scale = state->offset_scale * 12.0f;
565
566 tmp = S_0286D4_FLAT_SHADE_ENA(1);
567 if (state->sprite_coord_enable) {
568 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
569 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
570 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
571 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
572 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
573 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
574 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
575 }
576 }
577 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
578
579 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
580 /* point size 12.4 fixed point */
581 tmp = (unsigned)(state->point_size * 8.0);
582 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
583
584 if (state->point_size_per_vertex) {
585 psize_min = util_get_min_point_size(state);
586 psize_max = 8192;
587 } else {
588 /* Force the point size to be as if the vertex output was disabled. */
589 psize_min = state->point_size;
590 psize_max = state->point_size;
591 }
592 /* Divide by two, because 0.5 = 1 pixel. */
593 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
594 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
595 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
596
597 tmp = (unsigned)state->line_width * 8;
598 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
599 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
600 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
601 S_028A48_MSAA_ENABLE(state->multisample));
602
603 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
604 S_028BE4_PIX_CENTER(state->half_pixel_center) |
605 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
606 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
607 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
608 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
609 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
610
611 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
612 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
613
614 return rs;
615 }
616
617 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
618 {
619 struct r600_context *rctx = (struct r600_context *)ctx;
620 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
621
622 if (state == NULL)
623 return;
624
625 // TODO
626 rctx->sprite_coord_enable = rs->sprite_coord_enable;
627 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
628 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
629
630 si_pm4_bind_state(rctx, rasterizer, rs);
631 si_update_fb_rs_state(rctx);
632 }
633
634 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
635 {
636 struct r600_context *rctx = (struct r600_context *)ctx;
637 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
638 }
639
640 /*
641 * infeered state between dsa and stencil ref
642 */
643 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
644 {
645 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
646 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
647 struct si_state_dsa *dsa = rctx->queued.named.dsa;
648
649 if (pm4 == NULL)
650 return;
651
652 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
653 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
654 S_028430_STENCILMASK(dsa->valuemask[0]) |
655 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
656 S_028430_STENCILOPVAL(1));
657 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
658 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
659 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
660 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
661 S_028434_STENCILOPVAL_BF(1));
662
663 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
664 }
665
666 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
667 const struct pipe_stencil_ref *state)
668 {
669 struct r600_context *rctx = (struct r600_context *)ctx;
670 rctx->stencil_ref = *state;
671 si_update_dsa_stencil_ref(rctx);
672 }
673
674
675 /*
676 * DSA
677 */
678
679 static uint32_t si_translate_stencil_op(int s_op)
680 {
681 switch (s_op) {
682 case PIPE_STENCIL_OP_KEEP:
683 return V_02842C_STENCIL_KEEP;
684 case PIPE_STENCIL_OP_ZERO:
685 return V_02842C_STENCIL_ZERO;
686 case PIPE_STENCIL_OP_REPLACE:
687 return V_02842C_STENCIL_REPLACE_TEST;
688 case PIPE_STENCIL_OP_INCR:
689 return V_02842C_STENCIL_ADD_CLAMP;
690 case PIPE_STENCIL_OP_DECR:
691 return V_02842C_STENCIL_SUB_CLAMP;
692 case PIPE_STENCIL_OP_INCR_WRAP:
693 return V_02842C_STENCIL_ADD_WRAP;
694 case PIPE_STENCIL_OP_DECR_WRAP:
695 return V_02842C_STENCIL_SUB_WRAP;
696 case PIPE_STENCIL_OP_INVERT:
697 return V_02842C_STENCIL_INVERT;
698 default:
699 R600_ERR("Unknown stencil op %d", s_op);
700 assert(0);
701 break;
702 }
703 return 0;
704 }
705
706 static void *si_create_dsa_state(struct pipe_context *ctx,
707 const struct pipe_depth_stencil_alpha_state *state)
708 {
709 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
710 struct si_pm4_state *pm4 = &dsa->pm4;
711 unsigned db_depth_control;
712 unsigned db_render_control;
713 uint32_t db_stencil_control = 0;
714
715 if (dsa == NULL) {
716 return NULL;
717 }
718
719 dsa->valuemask[0] = state->stencil[0].valuemask;
720 dsa->valuemask[1] = state->stencil[1].valuemask;
721 dsa->writemask[0] = state->stencil[0].writemask;
722 dsa->writemask[1] = state->stencil[1].writemask;
723
724 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
725 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
726 S_028800_ZFUNC(state->depth.func);
727
728 /* stencil */
729 if (state->stencil[0].enabled) {
730 db_depth_control |= S_028800_STENCIL_ENABLE(1);
731 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
732 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
733 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
734 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
735
736 if (state->stencil[1].enabled) {
737 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
738 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
739 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
740 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
741 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
742 }
743 }
744
745 /* alpha */
746 if (state->alpha.enabled) {
747 dsa->alpha_func = state->alpha.func;
748 dsa->alpha_ref = state->alpha.ref_value;
749
750 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
751 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
752 } else {
753 dsa->alpha_func = PIPE_FUNC_ALWAYS;
754 }
755
756 /* misc */
757 db_render_control = 0;
758 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
759 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
760 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
761 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
762 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
763 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
764 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
765 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
766 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
767 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
768 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
769
770 return dsa;
771 }
772
773 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
774 {
775 struct r600_context *rctx = (struct r600_context *)ctx;
776 struct si_state_dsa *dsa = state;
777
778 if (state == NULL)
779 return;
780
781 si_pm4_bind_state(rctx, dsa, dsa);
782 si_update_dsa_stencil_ref(rctx);
783 }
784
785 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
786 {
787 struct r600_context *rctx = (struct r600_context *)ctx;
788 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
789 }
790
791 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
792 bool copy_stencil, int sample)
793 {
794 struct pipe_depth_stencil_alpha_state dsa;
795 struct si_state_dsa *state;
796
797 memset(&dsa, 0, sizeof(dsa));
798
799 state = rctx->b.b.create_depth_stencil_alpha_state(&rctx->b.b, &dsa);
800 if (copy_depth || copy_stencil) {
801 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
802 S_028000_DEPTH_COPY(copy_depth) |
803 S_028000_STENCIL_COPY(copy_stencil) |
804 S_028000_COPY_CENTROID(1) |
805 S_028000_COPY_SAMPLE(sample));
806 } else {
807 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
808 S_028000_DEPTH_COMPRESS_DISABLE(1) |
809 S_028000_STENCIL_COMPRESS_DISABLE(1));
810 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
811 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
812 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
813 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
814 S_02800C_DISABLE_TILE_RATE_TILES(1));
815 }
816
817 return state;
818 }
819
820 /*
821 * format translation
822 */
823 static uint32_t si_translate_colorformat(enum pipe_format format)
824 {
825 const struct util_format_description *desc = util_format_description(format);
826
827 #define HAS_SIZE(x,y,z,w) \
828 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
829 desc->channel[2].size == (z) && desc->channel[3].size == (w))
830
831 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
832 return V_028C70_COLOR_10_11_11;
833
834 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
835 return V_028C70_COLOR_INVALID;
836
837 switch (desc->nr_channels) {
838 case 1:
839 switch (desc->channel[0].size) {
840 case 8:
841 return V_028C70_COLOR_8;
842 case 16:
843 return V_028C70_COLOR_16;
844 case 32:
845 return V_028C70_COLOR_32;
846 }
847 break;
848 case 2:
849 if (desc->channel[0].size == desc->channel[1].size) {
850 switch (desc->channel[0].size) {
851 case 8:
852 return V_028C70_COLOR_8_8;
853 case 16:
854 return V_028C70_COLOR_16_16;
855 case 32:
856 return V_028C70_COLOR_32_32;
857 }
858 } else if (HAS_SIZE(8,24,0,0)) {
859 return V_028C70_COLOR_24_8;
860 } else if (HAS_SIZE(24,8,0,0)) {
861 return V_028C70_COLOR_8_24;
862 }
863 break;
864 case 3:
865 if (HAS_SIZE(5,6,5,0)) {
866 return V_028C70_COLOR_5_6_5;
867 } else if (HAS_SIZE(32,8,24,0)) {
868 return V_028C70_COLOR_X24_8_32_FLOAT;
869 }
870 break;
871 case 4:
872 if (desc->channel[0].size == desc->channel[1].size &&
873 desc->channel[0].size == desc->channel[2].size &&
874 desc->channel[0].size == desc->channel[3].size) {
875 switch (desc->channel[0].size) {
876 case 4:
877 return V_028C70_COLOR_4_4_4_4;
878 case 8:
879 return V_028C70_COLOR_8_8_8_8;
880 case 16:
881 return V_028C70_COLOR_16_16_16_16;
882 case 32:
883 return V_028C70_COLOR_32_32_32_32;
884 }
885 } else if (HAS_SIZE(5,5,5,1)) {
886 return V_028C70_COLOR_1_5_5_5;
887 } else if (HAS_SIZE(10,10,10,2)) {
888 return V_028C70_COLOR_2_10_10_10;
889 }
890 break;
891 }
892 return V_028C70_COLOR_INVALID;
893 }
894
895 static uint32_t si_translate_colorswap(enum pipe_format format)
896 {
897 const struct util_format_description *desc = util_format_description(format);
898
899 #define HAS_SWIZZLE(chan,swz) (desc->swizzle[chan] == UTIL_FORMAT_SWIZZLE_##swz)
900
901 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
902 return V_028C70_SWAP_STD;
903
904 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
905 return ~0;
906
907 switch (desc->nr_channels) {
908 case 1:
909 if (HAS_SWIZZLE(0,X))
910 return V_028C70_SWAP_STD; /* X___ */
911 else if (HAS_SWIZZLE(3,X))
912 return V_028C70_SWAP_ALT_REV; /* ___X */
913 break;
914 case 2:
915 if ((HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,Y)) ||
916 (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(1,NONE)) ||
917 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,Y)))
918 return V_028C70_SWAP_STD; /* XY__ */
919 else if ((HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,X)) ||
920 (HAS_SWIZZLE(0,Y) && HAS_SWIZZLE(1,NONE)) ||
921 (HAS_SWIZZLE(0,NONE) && HAS_SWIZZLE(1,X)))
922 return V_028C70_SWAP_STD_REV; /* YX__ */
923 else if (HAS_SWIZZLE(0,X) && HAS_SWIZZLE(3,Y))
924 return V_028C70_SWAP_ALT; /* X__Y */
925 break;
926 case 3:
927 if (HAS_SWIZZLE(0,X))
928 return V_028C70_SWAP_STD; /* XYZ */
929 else if (HAS_SWIZZLE(0,Z))
930 return V_028C70_SWAP_STD_REV; /* ZYX */
931 break;
932 case 4:
933 /* check the middle channels, the 1st and 4th channel can be NONE */
934 if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,Z))
935 return V_028C70_SWAP_STD; /* XYZW */
936 else if (HAS_SWIZZLE(1,Z) && HAS_SWIZZLE(2,Y))
937 return V_028C70_SWAP_STD_REV; /* WZYX */
938 else if (HAS_SWIZZLE(1,Y) && HAS_SWIZZLE(2,X))
939 return V_028C70_SWAP_ALT; /* ZYXW */
940 else if (HAS_SWIZZLE(1,X) && HAS_SWIZZLE(2,Y))
941 return V_028C70_SWAP_ALT_REV; /* WXYZ */
942 break;
943 }
944 return ~0U;
945 }
946
947 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
948 {
949 if (R600_BIG_ENDIAN) {
950 switch(colorformat) {
951 /* 8-bit buffers. */
952 case V_028C70_COLOR_8:
953 return V_028C70_ENDIAN_NONE;
954
955 /* 16-bit buffers. */
956 case V_028C70_COLOR_5_6_5:
957 case V_028C70_COLOR_1_5_5_5:
958 case V_028C70_COLOR_4_4_4_4:
959 case V_028C70_COLOR_16:
960 case V_028C70_COLOR_8_8:
961 return V_028C70_ENDIAN_8IN16;
962
963 /* 32-bit buffers. */
964 case V_028C70_COLOR_8_8_8_8:
965 case V_028C70_COLOR_2_10_10_10:
966 case V_028C70_COLOR_8_24:
967 case V_028C70_COLOR_24_8:
968 case V_028C70_COLOR_16_16:
969 return V_028C70_ENDIAN_8IN32;
970
971 /* 64-bit buffers. */
972 case V_028C70_COLOR_16_16_16_16:
973 return V_028C70_ENDIAN_8IN16;
974
975 case V_028C70_COLOR_32_32:
976 return V_028C70_ENDIAN_8IN32;
977
978 /* 128-bit buffers. */
979 case V_028C70_COLOR_32_32_32_32:
980 return V_028C70_ENDIAN_8IN32;
981 default:
982 return V_028C70_ENDIAN_NONE; /* Unsupported. */
983 }
984 } else {
985 return V_028C70_ENDIAN_NONE;
986 }
987 }
988
989 /* Returns the size in bits of the widest component of a CB format */
990 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
991 {
992 switch(colorformat) {
993 case V_028C70_COLOR_4_4_4_4:
994 return 4;
995
996 case V_028C70_COLOR_1_5_5_5:
997 case V_028C70_COLOR_5_5_5_1:
998 return 5;
999
1000 case V_028C70_COLOR_5_6_5:
1001 return 6;
1002
1003 case V_028C70_COLOR_8:
1004 case V_028C70_COLOR_8_8:
1005 case V_028C70_COLOR_8_8_8_8:
1006 return 8;
1007
1008 case V_028C70_COLOR_10_10_10_2:
1009 case V_028C70_COLOR_2_10_10_10:
1010 return 10;
1011
1012 case V_028C70_COLOR_10_11_11:
1013 case V_028C70_COLOR_11_11_10:
1014 return 11;
1015
1016 case V_028C70_COLOR_16:
1017 case V_028C70_COLOR_16_16:
1018 case V_028C70_COLOR_16_16_16_16:
1019 return 16;
1020
1021 case V_028C70_COLOR_8_24:
1022 case V_028C70_COLOR_24_8:
1023 return 24;
1024
1025 case V_028C70_COLOR_32:
1026 case V_028C70_COLOR_32_32:
1027 case V_028C70_COLOR_32_32_32_32:
1028 case V_028C70_COLOR_X24_8_32_FLOAT:
1029 return 32;
1030 }
1031
1032 assert(!"Unknown maximum component size");
1033 return 0;
1034 }
1035
1036 static uint32_t si_translate_dbformat(enum pipe_format format)
1037 {
1038 switch (format) {
1039 case PIPE_FORMAT_Z16_UNORM:
1040 return V_028040_Z_16;
1041 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1042 case PIPE_FORMAT_X8Z24_UNORM:
1043 case PIPE_FORMAT_Z24X8_UNORM:
1044 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1045 return V_028040_Z_24; /* deprecated on SI */
1046 case PIPE_FORMAT_Z32_FLOAT:
1047 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1048 return V_028040_Z_32_FLOAT;
1049 default:
1050 return V_028040_Z_INVALID;
1051 }
1052 }
1053
1054 /*
1055 * Texture translation
1056 */
1057
1058 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1059 enum pipe_format format,
1060 const struct util_format_description *desc,
1061 int first_non_void)
1062 {
1063 struct r600_screen *rscreen = (struct r600_screen*)screen;
1064 bool enable_s3tc = rscreen->b.info.drm_minor >= 31;
1065 boolean uniform = TRUE;
1066 int i;
1067
1068 /* Colorspace (return non-RGB formats directly). */
1069 switch (desc->colorspace) {
1070 /* Depth stencil formats */
1071 case UTIL_FORMAT_COLORSPACE_ZS:
1072 switch (format) {
1073 case PIPE_FORMAT_Z16_UNORM:
1074 return V_008F14_IMG_DATA_FORMAT_16;
1075 case PIPE_FORMAT_X24S8_UINT:
1076 case PIPE_FORMAT_Z24X8_UNORM:
1077 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1078 return V_008F14_IMG_DATA_FORMAT_8_24;
1079 case PIPE_FORMAT_X8Z24_UNORM:
1080 case PIPE_FORMAT_S8X24_UINT:
1081 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1082 return V_008F14_IMG_DATA_FORMAT_24_8;
1083 case PIPE_FORMAT_S8_UINT:
1084 return V_008F14_IMG_DATA_FORMAT_8;
1085 case PIPE_FORMAT_Z32_FLOAT:
1086 return V_008F14_IMG_DATA_FORMAT_32;
1087 case PIPE_FORMAT_X32_S8X24_UINT:
1088 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1089 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1090 default:
1091 goto out_unknown;
1092 }
1093
1094 case UTIL_FORMAT_COLORSPACE_YUV:
1095 goto out_unknown; /* TODO */
1096
1097 case UTIL_FORMAT_COLORSPACE_SRGB:
1098 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1099 goto out_unknown;
1100 break;
1101
1102 default:
1103 break;
1104 }
1105
1106 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1107 if (!enable_s3tc)
1108 goto out_unknown;
1109
1110 switch (format) {
1111 case PIPE_FORMAT_RGTC1_SNORM:
1112 case PIPE_FORMAT_LATC1_SNORM:
1113 case PIPE_FORMAT_RGTC1_UNORM:
1114 case PIPE_FORMAT_LATC1_UNORM:
1115 return V_008F14_IMG_DATA_FORMAT_BC4;
1116 case PIPE_FORMAT_RGTC2_SNORM:
1117 case PIPE_FORMAT_LATC2_SNORM:
1118 case PIPE_FORMAT_RGTC2_UNORM:
1119 case PIPE_FORMAT_LATC2_UNORM:
1120 return V_008F14_IMG_DATA_FORMAT_BC5;
1121 default:
1122 goto out_unknown;
1123 }
1124 }
1125
1126 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1127
1128 if (!enable_s3tc)
1129 goto out_unknown;
1130
1131 if (!util_format_s3tc_enabled) {
1132 goto out_unknown;
1133 }
1134
1135 switch (format) {
1136 case PIPE_FORMAT_DXT1_RGB:
1137 case PIPE_FORMAT_DXT1_RGBA:
1138 case PIPE_FORMAT_DXT1_SRGB:
1139 case PIPE_FORMAT_DXT1_SRGBA:
1140 return V_008F14_IMG_DATA_FORMAT_BC1;
1141 case PIPE_FORMAT_DXT3_RGBA:
1142 case PIPE_FORMAT_DXT3_SRGBA:
1143 return V_008F14_IMG_DATA_FORMAT_BC2;
1144 case PIPE_FORMAT_DXT5_RGBA:
1145 case PIPE_FORMAT_DXT5_SRGBA:
1146 return V_008F14_IMG_DATA_FORMAT_BC3;
1147 default:
1148 goto out_unknown;
1149 }
1150 }
1151
1152 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1153 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1154 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1155 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1156 }
1157
1158 /* R8G8Bx_SNORM - TODO CxV8U8 */
1159
1160 /* See whether the components are of the same size. */
1161 for (i = 1; i < desc->nr_channels; i++) {
1162 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1163 }
1164
1165 /* Non-uniform formats. */
1166 if (!uniform) {
1167 switch(desc->nr_channels) {
1168 case 3:
1169 if (desc->channel[0].size == 5 &&
1170 desc->channel[1].size == 6 &&
1171 desc->channel[2].size == 5) {
1172 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1173 }
1174 goto out_unknown;
1175 case 4:
1176 if (desc->channel[0].size == 5 &&
1177 desc->channel[1].size == 5 &&
1178 desc->channel[2].size == 5 &&
1179 desc->channel[3].size == 1) {
1180 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1181 }
1182 if (desc->channel[0].size == 10 &&
1183 desc->channel[1].size == 10 &&
1184 desc->channel[2].size == 10 &&
1185 desc->channel[3].size == 2) {
1186 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1187 }
1188 goto out_unknown;
1189 }
1190 goto out_unknown;
1191 }
1192
1193 if (first_non_void < 0 || first_non_void > 3)
1194 goto out_unknown;
1195
1196 /* uniform formats */
1197 switch (desc->channel[first_non_void].size) {
1198 case 4:
1199 switch (desc->nr_channels) {
1200 #if 0 /* Not supported for render targets */
1201 case 2:
1202 return V_008F14_IMG_DATA_FORMAT_4_4;
1203 #endif
1204 case 4:
1205 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1206 }
1207 break;
1208 case 8:
1209 switch (desc->nr_channels) {
1210 case 1:
1211 return V_008F14_IMG_DATA_FORMAT_8;
1212 case 2:
1213 return V_008F14_IMG_DATA_FORMAT_8_8;
1214 case 4:
1215 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1216 }
1217 break;
1218 case 16:
1219 switch (desc->nr_channels) {
1220 case 1:
1221 return V_008F14_IMG_DATA_FORMAT_16;
1222 case 2:
1223 return V_008F14_IMG_DATA_FORMAT_16_16;
1224 case 4:
1225 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1226 }
1227 break;
1228 case 32:
1229 switch (desc->nr_channels) {
1230 case 1:
1231 return V_008F14_IMG_DATA_FORMAT_32;
1232 case 2:
1233 return V_008F14_IMG_DATA_FORMAT_32_32;
1234 #if 0 /* Not supported for render targets */
1235 case 3:
1236 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1237 #endif
1238 case 4:
1239 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1240 }
1241 }
1242
1243 out_unknown:
1244 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1245 return ~0;
1246 }
1247
1248 static unsigned si_tex_wrap(unsigned wrap)
1249 {
1250 switch (wrap) {
1251 default:
1252 case PIPE_TEX_WRAP_REPEAT:
1253 return V_008F30_SQ_TEX_WRAP;
1254 case PIPE_TEX_WRAP_CLAMP:
1255 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1256 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1257 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1258 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1259 return V_008F30_SQ_TEX_CLAMP_BORDER;
1260 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1261 return V_008F30_SQ_TEX_MIRROR;
1262 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1263 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1264 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1265 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1266 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1267 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1268 }
1269 }
1270
1271 static unsigned si_tex_filter(unsigned filter)
1272 {
1273 switch (filter) {
1274 default:
1275 case PIPE_TEX_FILTER_NEAREST:
1276 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1277 case PIPE_TEX_FILTER_LINEAR:
1278 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1279 }
1280 }
1281
1282 static unsigned si_tex_mipfilter(unsigned filter)
1283 {
1284 switch (filter) {
1285 case PIPE_TEX_MIPFILTER_NEAREST:
1286 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1287 case PIPE_TEX_MIPFILTER_LINEAR:
1288 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1289 default:
1290 case PIPE_TEX_MIPFILTER_NONE:
1291 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1292 }
1293 }
1294
1295 static unsigned si_tex_compare(unsigned compare)
1296 {
1297 switch (compare) {
1298 default:
1299 case PIPE_FUNC_NEVER:
1300 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1301 case PIPE_FUNC_LESS:
1302 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1303 case PIPE_FUNC_EQUAL:
1304 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1305 case PIPE_FUNC_LEQUAL:
1306 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1307 case PIPE_FUNC_GREATER:
1308 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1309 case PIPE_FUNC_NOTEQUAL:
1310 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1311 case PIPE_FUNC_GEQUAL:
1312 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1313 case PIPE_FUNC_ALWAYS:
1314 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1315 }
1316 }
1317
1318 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1319 {
1320 switch (dim) {
1321 default:
1322 case PIPE_TEXTURE_1D:
1323 return V_008F1C_SQ_RSRC_IMG_1D;
1324 case PIPE_TEXTURE_1D_ARRAY:
1325 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1326 case PIPE_TEXTURE_2D:
1327 case PIPE_TEXTURE_RECT:
1328 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1329 V_008F1C_SQ_RSRC_IMG_2D;
1330 case PIPE_TEXTURE_2D_ARRAY:
1331 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1332 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1333 case PIPE_TEXTURE_3D:
1334 return V_008F1C_SQ_RSRC_IMG_3D;
1335 case PIPE_TEXTURE_CUBE:
1336 return V_008F1C_SQ_RSRC_IMG_CUBE;
1337 }
1338 }
1339
1340 /*
1341 * Format support testing
1342 */
1343
1344 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1345 {
1346 return si_translate_texformat(screen, format, util_format_description(format),
1347 util_format_get_first_non_void_channel(format)) != ~0U;
1348 }
1349
1350 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1351 const struct util_format_description *desc,
1352 int first_non_void)
1353 {
1354 unsigned type = desc->channel[first_non_void].type;
1355 int i;
1356
1357 if (type == UTIL_FORMAT_TYPE_FIXED)
1358 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1359
1360 if (desc->nr_channels == 4 &&
1361 desc->channel[0].size == 10 &&
1362 desc->channel[1].size == 10 &&
1363 desc->channel[2].size == 10 &&
1364 desc->channel[3].size == 2)
1365 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1366
1367 /* See whether the components are of the same size. */
1368 for (i = 0; i < desc->nr_channels; i++) {
1369 if (desc->channel[first_non_void].size != desc->channel[i].size)
1370 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1371 }
1372
1373 switch (desc->channel[first_non_void].size) {
1374 case 8:
1375 switch (desc->nr_channels) {
1376 case 1:
1377 return V_008F0C_BUF_DATA_FORMAT_8;
1378 case 2:
1379 return V_008F0C_BUF_DATA_FORMAT_8_8;
1380 case 3:
1381 case 4:
1382 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1383 }
1384 break;
1385 case 16:
1386 switch (desc->nr_channels) {
1387 case 1:
1388 return V_008F0C_BUF_DATA_FORMAT_16;
1389 case 2:
1390 return V_008F0C_BUF_DATA_FORMAT_16_16;
1391 case 3:
1392 case 4:
1393 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1394 }
1395 break;
1396 case 32:
1397 /* From the Southern Islands ISA documentation about MTBUF:
1398 * 'Memory reads of data in memory that is 32 or 64 bits do not
1399 * undergo any format conversion.'
1400 */
1401 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1402 !desc->channel[first_non_void].pure_integer)
1403 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1404
1405 switch (desc->nr_channels) {
1406 case 1:
1407 return V_008F0C_BUF_DATA_FORMAT_32;
1408 case 2:
1409 return V_008F0C_BUF_DATA_FORMAT_32_32;
1410 case 3:
1411 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1412 case 4:
1413 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1414 }
1415 break;
1416 }
1417
1418 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1419 }
1420
1421 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1422 const struct util_format_description *desc,
1423 int first_non_void)
1424 {
1425 switch (desc->channel[first_non_void].type) {
1426 case UTIL_FORMAT_TYPE_SIGNED:
1427 if (desc->channel[first_non_void].normalized)
1428 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1429 else if (desc->channel[first_non_void].pure_integer)
1430 return V_008F0C_BUF_NUM_FORMAT_SINT;
1431 else
1432 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1433 break;
1434 case UTIL_FORMAT_TYPE_UNSIGNED:
1435 if (desc->channel[first_non_void].normalized)
1436 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1437 else if (desc->channel[first_non_void].pure_integer)
1438 return V_008F0C_BUF_NUM_FORMAT_UINT;
1439 else
1440 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1441 break;
1442 case UTIL_FORMAT_TYPE_FLOAT:
1443 default:
1444 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1445 }
1446 }
1447
1448 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1449 {
1450 const struct util_format_description *desc;
1451 int first_non_void;
1452 unsigned data_format;
1453
1454 desc = util_format_description(format);
1455 first_non_void = util_format_get_first_non_void_channel(format);
1456 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1457 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1458 }
1459
1460 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1461 {
1462 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1463 si_translate_colorswap(format) != ~0U;
1464 }
1465
1466 static bool si_is_zs_format_supported(enum pipe_format format)
1467 {
1468 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1469 }
1470
1471 boolean si_is_format_supported(struct pipe_screen *screen,
1472 enum pipe_format format,
1473 enum pipe_texture_target target,
1474 unsigned sample_count,
1475 unsigned usage)
1476 {
1477 struct r600_screen *rscreen = (struct r600_screen *)screen;
1478 unsigned retval = 0;
1479
1480 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1481 R600_ERR("r600: unsupported texture type %d\n", target);
1482 return FALSE;
1483 }
1484
1485 if (!util_format_is_supported(format, usage))
1486 return FALSE;
1487
1488 if (sample_count > 1) {
1489 if (HAVE_LLVM < 0x0304)
1490 return FALSE;
1491
1492 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1493 if (rscreen->b.chip_class >= CIK && rscreen->b.info.drm_minor < 35)
1494 return FALSE;
1495
1496 switch (sample_count) {
1497 case 2:
1498 case 4:
1499 case 8:
1500 break;
1501 default:
1502 return FALSE;
1503 }
1504 }
1505
1506 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1507 if (target == PIPE_BUFFER) {
1508 if (si_is_vertex_format_supported(screen, format))
1509 retval |= PIPE_BIND_SAMPLER_VIEW;
1510 } else {
1511 if (si_is_sampler_format_supported(screen, format))
1512 retval |= PIPE_BIND_SAMPLER_VIEW;
1513 }
1514 }
1515
1516 if ((usage & (PIPE_BIND_RENDER_TARGET |
1517 PIPE_BIND_DISPLAY_TARGET |
1518 PIPE_BIND_SCANOUT |
1519 PIPE_BIND_SHARED)) &&
1520 si_is_colorbuffer_format_supported(format)) {
1521 retval |= usage &
1522 (PIPE_BIND_RENDER_TARGET |
1523 PIPE_BIND_DISPLAY_TARGET |
1524 PIPE_BIND_SCANOUT |
1525 PIPE_BIND_SHARED);
1526 }
1527
1528 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1529 si_is_zs_format_supported(format)) {
1530 retval |= PIPE_BIND_DEPTH_STENCIL;
1531 }
1532
1533 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1534 si_is_vertex_format_supported(screen, format)) {
1535 retval |= PIPE_BIND_VERTEX_BUFFER;
1536 }
1537
1538 if (usage & PIPE_BIND_TRANSFER_READ)
1539 retval |= PIPE_BIND_TRANSFER_READ;
1540 if (usage & PIPE_BIND_TRANSFER_WRITE)
1541 retval |= PIPE_BIND_TRANSFER_WRITE;
1542
1543 return retval == usage;
1544 }
1545
1546 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1547 {
1548 unsigned tile_mode_index = 0;
1549
1550 if (stencil) {
1551 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1552 } else {
1553 tile_mode_index = rtex->surface.tiling_index[level];
1554 }
1555 return tile_mode_index;
1556 }
1557
1558 /*
1559 * framebuffer handling
1560 */
1561
1562 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1563 const struct pipe_framebuffer_state *state, int cb)
1564 {
1565 struct r600_texture *rtex;
1566 struct r600_surface *surf;
1567 unsigned level = state->cbufs[cb]->u.tex.level;
1568 unsigned pitch, slice;
1569 unsigned color_info, color_attrib, color_pitch, color_view;
1570 unsigned tile_mode_index;
1571 unsigned format, swap, ntype, endian;
1572 uint64_t offset;
1573 const struct util_format_description *desc;
1574 int i;
1575 unsigned blend_clamp = 0, blend_bypass = 0;
1576 unsigned max_comp_size;
1577
1578 surf = (struct r600_surface *)state->cbufs[cb];
1579 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1580
1581 offset = rtex->surface.level[level].offset;
1582
1583 /* Layered rendering doesn't work with LINEAR_GENERAL.
1584 * (LINEAR_ALIGNED and others work) */
1585 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1586 assert(state->cbufs[cb]->u.tex.first_layer == state->cbufs[cb]->u.tex.last_layer);
1587 offset += rtex->surface.level[level].slice_size *
1588 state->cbufs[cb]->u.tex.first_layer;
1589 color_view = 0;
1590 } else {
1591 color_view = S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1592 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer);
1593 }
1594
1595 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1596 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1597 if (slice) {
1598 slice = slice - 1;
1599 }
1600
1601 tile_mode_index = si_tile_mode_index(rtex, level, false);
1602
1603 desc = util_format_description(surf->base.format);
1604 for (i = 0; i < 4; i++) {
1605 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1606 break;
1607 }
1608 }
1609 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1610 ntype = V_028C70_NUMBER_FLOAT;
1611 } else {
1612 ntype = V_028C70_NUMBER_UNORM;
1613 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1614 ntype = V_028C70_NUMBER_SRGB;
1615 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1616 if (desc->channel[i].pure_integer) {
1617 ntype = V_028C70_NUMBER_SINT;
1618 } else {
1619 assert(desc->channel[i].normalized);
1620 ntype = V_028C70_NUMBER_SNORM;
1621 }
1622 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1623 if (desc->channel[i].pure_integer) {
1624 ntype = V_028C70_NUMBER_UINT;
1625 } else {
1626 assert(desc->channel[i].normalized);
1627 ntype = V_028C70_NUMBER_UNORM;
1628 }
1629 }
1630 }
1631
1632 format = si_translate_colorformat(surf->base.format);
1633 if (format == V_028C70_COLOR_INVALID) {
1634 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1635 }
1636 assert(format != V_028C70_COLOR_INVALID);
1637 swap = si_translate_colorswap(surf->base.format);
1638 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1639 endian = V_028C70_ENDIAN_NONE;
1640 } else {
1641 endian = si_colorformat_endian_swap(format);
1642 }
1643
1644 /* blend clamp should be set for all NORM/SRGB types */
1645 if (ntype == V_028C70_NUMBER_UNORM ||
1646 ntype == V_028C70_NUMBER_SNORM ||
1647 ntype == V_028C70_NUMBER_SRGB)
1648 blend_clamp = 1;
1649
1650 /* set blend bypass according to docs if SINT/UINT or
1651 8/24 COLOR variants */
1652 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1653 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1654 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1655 blend_clamp = 0;
1656 blend_bypass = 1;
1657 }
1658
1659 color_info = S_028C70_FORMAT(format) |
1660 S_028C70_COMP_SWAP(swap) |
1661 S_028C70_BLEND_CLAMP(blend_clamp) |
1662 S_028C70_BLEND_BYPASS(blend_bypass) |
1663 S_028C70_NUMBER_TYPE(ntype) |
1664 S_028C70_ENDIAN(endian);
1665
1666 color_pitch = S_028C64_TILE_MAX(pitch);
1667
1668 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1669 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1670
1671 if (rtex->resource.b.b.nr_samples > 1) {
1672 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1673
1674 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1675 S_028C74_NUM_FRAGMENTS(log_samples);
1676
1677 if (rtex->fmask.size) {
1678 color_info |= S_028C70_COMPRESSION(1);
1679 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1680
1681 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1682
1683 if (rctx->b.chip_class == SI) {
1684 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1685 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1686 }
1687 if (rctx->b.chip_class >= CIK) {
1688 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1689 }
1690 }
1691 }
1692
1693 if (rtex->cmask.size) {
1694 color_info |= S_028C70_FAST_CLEAR(1);
1695 }
1696
1697 offset += r600_resource_va(rctx->b.b.screen, state->cbufs[cb]->texture);
1698 offset >>= 8;
1699
1700 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1701 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1702 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, color_pitch);
1703 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1704 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, color_view);
1705 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1706 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1707
1708 if (rtex->cmask.size) {
1709 si_pm4_set_reg(pm4, R_028C7C_CB_COLOR0_CMASK + cb * 0x3C,
1710 offset + (rtex->cmask.offset >> 8));
1711 si_pm4_set_reg(pm4, R_028C80_CB_COLOR0_CMASK_SLICE + cb * 0x3C,
1712 S_028C80_TILE_MAX(rtex->cmask.slice_tile_max));
1713 }
1714 if (rtex->fmask.size) {
1715 si_pm4_set_reg(pm4, R_028C84_CB_COLOR0_FMASK + cb * 0x3C,
1716 offset + (rtex->fmask.offset >> 8));
1717 si_pm4_set_reg(pm4, R_028C88_CB_COLOR0_FMASK_SLICE + cb * 0x3C,
1718 S_028C88_TILE_MAX(rtex->fmask.slice_tile_max));
1719 }
1720
1721 /* set CB_COLOR1_INFO for possible dual-src blending */
1722 if (state->nr_cbufs == 1) {
1723 assert(cb == 0);
1724 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1725 }
1726
1727 /* Determine pixel shader export format */
1728 max_comp_size = si_colorformat_max_comp_size(format);
1729 if (ntype == V_028C70_NUMBER_SRGB ||
1730 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1731 max_comp_size <= 10) ||
1732 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1733 rctx->export_16bpc |= 1 << cb;
1734 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1735 if (state->nr_cbufs == 1)
1736 rctx->export_16bpc |= 1 << 1;
1737 }
1738 }
1739
1740 /* Update register(s) containing depth buffer and draw state. */
1741 void si_update_db_draw_state(struct r600_context *rctx, struct r600_surface *zsbuf)
1742 {
1743 struct si_pm4_state *pm4;
1744 uint32_t db_render_override;
1745 boolean hiz_enable = false;
1746
1747 pm4 = si_pm4_alloc_state(rctx);
1748 if (pm4 == NULL) {
1749 return;
1750 }
1751
1752 /* db */
1753
1754 /* TODO HiS aka stencil buffer htile goes here */
1755 db_render_override = S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
1756 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
1757
1758 /* HiZ aka depth buffer htile */
1759 if (zsbuf && zsbuf->base.texture) {
1760 struct r600_texture *rtex = (struct r600_texture*)zsbuf->base.texture;
1761 uint level = zsbuf->base.u.tex.level;
1762 /* use htile only for first level */
1763 hiz_enable = rtex->htile_buffer && !level;
1764 }
1765 if (hiz_enable) {
1766 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
1767 } else {
1768 db_render_override |= S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
1769 }
1770
1771 /* draw */
1772
1773 if (rctx->num_cs_dw_nontimer_queries_suspend) {
1774 db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
1775 }
1776
1777 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
1778 si_pm4_set_state(rctx, db_draw, pm4);
1779 }
1780
1781 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1782 const struct pipe_framebuffer_state *state)
1783 {
1784 struct r600_screen *rscreen = rctx->screen;
1785 struct r600_texture *rtex;
1786 struct r600_surface *surf;
1787 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1788 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1789 uint32_t z_info, s_info, db_depth_info;
1790 uint64_t z_offs, s_offs;
1791 uint32_t db_htile_data_base, db_htile_surface;
1792
1793 if (state->zsbuf == NULL) {
1794 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1795 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1796 return;
1797 }
1798
1799 surf = (struct r600_surface *)state->zsbuf;
1800 level = surf->base.u.tex.level;
1801 rtex = (struct r600_texture*)surf->base.texture;
1802
1803 format = si_translate_dbformat(rtex->resource.b.b.format);
1804
1805 if (format == V_028040_Z_INVALID) {
1806 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1807 }
1808 assert(format != V_028040_Z_INVALID);
1809
1810 s_offs = z_offs = r600_resource_va(rctx->b.b.screen, surf->base.texture);
1811 z_offs += rtex->surface.level[level].offset;
1812 s_offs += rtex->surface.stencil_level[level].offset;
1813
1814 z_offs >>= 8;
1815 s_offs >>= 8;
1816
1817 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1818 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1819 if (slice) {
1820 slice = slice - 1;
1821 }
1822
1823 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1824
1825 z_info = S_028040_FORMAT(format);
1826 if (rtex->resource.b.b.nr_samples > 1) {
1827 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1828 }
1829
1830 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1831 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1832 else
1833 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1834
1835 if (rctx->b.chip_class >= CIK) {
1836 switch (rtex->surface.level[level].mode) {
1837 case RADEON_SURF_MODE_2D:
1838 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1839 break;
1840 case RADEON_SURF_MODE_1D:
1841 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1842 case RADEON_SURF_MODE_LINEAR:
1843 default:
1844 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1845 break;
1846 }
1847 tile_split = rtex->surface.tile_split;
1848 stile_split = rtex->surface.stencil_tile_split;
1849 macro_aspect = rtex->surface.mtilea;
1850 bankw = rtex->surface.bankw;
1851 bankh = rtex->surface.bankh;
1852 tile_split = cik_tile_split(tile_split);
1853 stile_split = cik_tile_split(stile_split);
1854 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1855 bankw = cik_bank_wh(bankw);
1856 bankh = cik_bank_wh(bankh);
1857 nbanks = cik_num_banks(rscreen->b.tiling_info.num_banks);
1858 pipe_config = cik_db_pipe_config(rscreen->b.info.r600_num_tile_pipes,
1859 rscreen->b.info.r600_num_backends);
1860
1861 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1862 S_02803C_PIPE_CONFIG(pipe_config) |
1863 S_02803C_BANK_WIDTH(bankw) |
1864 S_02803C_BANK_HEIGHT(bankh) |
1865 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1866 S_02803C_NUM_BANKS(nbanks);
1867 z_info |= S_028040_TILE_SPLIT(tile_split);
1868 s_info |= S_028044_TILE_SPLIT(stile_split);
1869 } else {
1870 tile_mode_index = si_tile_mode_index(rtex, level, false);
1871 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1872 tile_mode_index = si_tile_mode_index(rtex, level, true);
1873 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1874 }
1875
1876 /* HiZ aka depth buffer htile */
1877 /* use htile only for first level */
1878 if (rtex->htile_buffer && !level) {
1879 z_info |= S_028040_TILE_SURFACE_ENABLE(1);
1880 /* Force off means no force, DB_SHADER_CONTROL decides */
1881 uint64_t va = r600_resource_va(&rctx->screen->b.b, &rtex->htile_buffer->b.b);
1882 db_htile_data_base = va >> 8;
1883 db_htile_surface = S_028ABC_FULL_CACHE(1);
1884 } else {
1885 db_htile_data_base = 0;
1886 db_htile_surface = 0;
1887 }
1888
1889 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1890 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1891 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1892 si_pm4_set_reg(pm4, R_028014_DB_HTILE_DATA_BASE, db_htile_data_base);
1893
1894 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1895 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1896 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1897
1898 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1899 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1900 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1901 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1902 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1903
1904 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1905 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1906
1907 si_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);
1908 }
1909
1910 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
1911 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
1912 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
1913 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
1914 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1915
1916 /* 2xMSAA
1917 * There are two locations (-4, 4), (4, -4). */
1918 static uint32_t sample_locs_2x[] = {
1919 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1920 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1921 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1922 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1923 };
1924 static unsigned max_dist_2x = 4;
1925 /* 4xMSAA
1926 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
1927 static uint32_t sample_locs_4x[] = {
1928 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1929 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1930 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1931 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1932 };
1933 static unsigned max_dist_4x = 6;
1934 /* Cayman/SI 8xMSAA */
1935 static uint32_t cm_sample_locs_8x[] = {
1936 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1937 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1938 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1939 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1940 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1941 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1942 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1943 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
1944 };
1945 static unsigned cm_max_dist_8x = 8;
1946 /* Cayman/SI 16xMSAA */
1947 static uint32_t cm_sample_locs_16x[] = {
1948 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1949 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1950 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1951 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
1952 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1953 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1954 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1955 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
1956 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1957 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1958 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1959 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
1960 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1961 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1962 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1963 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
1964 };
1965 static unsigned cm_max_dist_16x = 8;
1966
1967 static void si_get_sample_position(struct pipe_context *ctx,
1968 unsigned sample_count,
1969 unsigned sample_index,
1970 float *out_value)
1971 {
1972 int offset, index;
1973 struct {
1974 int idx:4;
1975 } val;
1976 switch (sample_count) {
1977 case 1:
1978 default:
1979 out_value[0] = out_value[1] = 0.5;
1980 break;
1981 case 2:
1982 offset = 4 * (sample_index * 2);
1983 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
1984 out_value[0] = (float)(val.idx + 8) / 16.0f;
1985 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
1986 out_value[1] = (float)(val.idx + 8) / 16.0f;
1987 break;
1988 case 4:
1989 offset = 4 * (sample_index * 2);
1990 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
1991 out_value[0] = (float)(val.idx + 8) / 16.0f;
1992 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
1993 out_value[1] = (float)(val.idx + 8) / 16.0f;
1994 break;
1995 case 8:
1996 offset = 4 * (sample_index % 4 * 2);
1997 index = (sample_index / 4) * 4;
1998 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
1999 out_value[0] = (float)(val.idx + 8) / 16.0f;
2000 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2001 out_value[1] = (float)(val.idx + 8) / 16.0f;
2002 break;
2003 case 16:
2004 offset = 4 * (sample_index % 4 * 2);
2005 index = (sample_index / 4) * 4;
2006 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2007 out_value[0] = (float)(val.idx + 8) / 16.0f;
2008 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2009 out_value[1] = (float)(val.idx + 8) / 16.0f;
2010 break;
2011 }
2012 }
2013
2014 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
2015 {
2016 unsigned max_dist = 0;
2017
2018 switch (nr_samples) {
2019 default:
2020 nr_samples = 0;
2021 break;
2022 case 2:
2023 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2024 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2025 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2026 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2027 max_dist = max_dist_2x;
2028 break;
2029 case 4:
2030 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2031 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2032 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2033 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2034 max_dist = max_dist_4x;
2035 break;
2036 case 8:
2037 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2038 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2039 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2040 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2041 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2042 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2043 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2044 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2045 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2046 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2047 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2048 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2049 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2050 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2051 max_dist = cm_max_dist_8x;
2052 break;
2053 case 16:
2054 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2055 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2056 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2057 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2058 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2059 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2060 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2061 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2062 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2063 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2064 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2065 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2066 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2067 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2068 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2069 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2070 max_dist = cm_max_dist_16x;
2071 break;
2072 }
2073
2074 if (nr_samples > 1) {
2075 unsigned log_samples = util_logbase2(nr_samples);
2076
2077 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2078 S_028BDC_LAST_PIXEL(1) |
2079 S_028BDC_EXPAND_LINE_WIDTH(1));
2080 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2081 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2082 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2083 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2084
2085 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2086 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2087 S_028804_PS_ITER_SAMPLES(log_samples) |
2088 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2089 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2090 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2091 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2092 } else {
2093 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2094 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2095
2096 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2097 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2098 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2099 }
2100 }
2101
2102 static void si_set_framebuffer_state(struct pipe_context *ctx,
2103 const struct pipe_framebuffer_state *state)
2104 {
2105 struct r600_context *rctx = (struct r600_context *)ctx;
2106 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2107 uint32_t tl, br;
2108 int tl_x, tl_y, br_x, br_y, nr_samples, i;
2109
2110 if (pm4 == NULL)
2111 return;
2112
2113 if (rctx->framebuffer.nr_cbufs) {
2114 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
2115 R600_CONTEXT_FLUSH_AND_INV_CB_META;
2116 }
2117 if (rctx->framebuffer.zsbuf) {
2118 rctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB;
2119 }
2120
2121 util_copy_framebuffer_state(&rctx->framebuffer, state);
2122
2123 /* build states */
2124 rctx->export_16bpc = 0;
2125 rctx->fb_compressed_cb_mask = 0;
2126 for (i = 0; i < state->nr_cbufs; i++) {
2127 struct r600_texture *rtex =
2128 (struct r600_texture*)state->cbufs[i]->texture;
2129
2130 si_cb(rctx, pm4, state, i);
2131
2132 if (rtex->fmask.size || rtex->cmask.size) {
2133 rctx->fb_compressed_cb_mask |= 1 << i;
2134 }
2135 }
2136 for (; i < 8; i++) {
2137 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2138 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2139 }
2140
2141 assert(!(rctx->export_16bpc & ~0xff));
2142 si_db(rctx, pm4, state);
2143
2144 tl_x = 0;
2145 tl_y = 0;
2146 br_x = state->width;
2147 br_y = state->height;
2148
2149 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2150 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2151
2152 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2153 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2154 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2155 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2156 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2157 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2158 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2159 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2160 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2161 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2162
2163 if (state->nr_cbufs)
2164 nr_samples = state->cbufs[0]->texture->nr_samples;
2165 else if (state->zsbuf)
2166 nr_samples = state->zsbuf->texture->nr_samples;
2167 else
2168 nr_samples = 0;
2169
2170 si_set_msaa_state(rctx, pm4, nr_samples);
2171 rctx->fb_log_samples = util_logbase2(nr_samples);
2172 rctx->fb_cb0_is_integer = state->nr_cbufs &&
2173 util_format_is_pure_integer(state->cbufs[0]->format);
2174
2175 si_pm4_set_state(rctx, framebuffer, pm4);
2176 si_update_fb_rs_state(rctx);
2177 si_update_fb_blend_state(rctx);
2178 si_update_db_draw_state(rctx, (struct r600_surface *)state->zsbuf);
2179 }
2180
2181 /*
2182 * shaders
2183 */
2184
2185 /* Compute the key for the hw shader variant */
2186 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2187 struct si_pipe_shader_selector *sel,
2188 union si_shader_key *key)
2189 {
2190 struct r600_context *rctx = (struct r600_context *)ctx;
2191 memset(key, 0, sizeof(*key));
2192
2193 if (sel->type == PIPE_SHADER_VERTEX) {
2194 unsigned i;
2195 if (!rctx->vertex_elements)
2196 return;
2197
2198 for (i = 0; i < rctx->vertex_elements->count; ++i)
2199 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2200
2201 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2202 key->vs.ucps_enabled |= 0x2;
2203 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2204 key->vs.ucps_enabled |= 0x1;
2205 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2206 if (sel->fs_write_all)
2207 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2208 key->ps.export_16bpc = rctx->export_16bpc;
2209
2210 if (rctx->queued.named.rasterizer) {
2211 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2212 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2213
2214 if (rctx->queued.named.blend) {
2215 key->ps.alpha_to_one = rctx->queued.named.blend->alpha_to_one &&
2216 rctx->queued.named.rasterizer->multisample_enable &&
2217 !rctx->fb_cb0_is_integer;
2218 }
2219 }
2220 if (rctx->queued.named.dsa) {
2221 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2222
2223 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
2224 if (rctx->framebuffer.nr_cbufs &&
2225 rctx->framebuffer.cbufs[0] &&
2226 util_format_is_pure_integer(rctx->framebuffer.cbufs[0]->texture->format))
2227 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2228 } else {
2229 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2230 }
2231 }
2232 }
2233
2234 /* Select the hw shader variant depending on the current state.
2235 * (*dirty) is set to 1 if current variant was changed */
2236 int si_shader_select(struct pipe_context *ctx,
2237 struct si_pipe_shader_selector *sel,
2238 unsigned *dirty)
2239 {
2240 union si_shader_key key;
2241 struct si_pipe_shader * shader = NULL;
2242 int r;
2243
2244 si_shader_selector_key(ctx, sel, &key);
2245
2246 /* Check if we don't need to change anything.
2247 * This path is also used for most shaders that don't need multiple
2248 * variants, it will cost just a computation of the key and this
2249 * test. */
2250 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2251 return 0;
2252 }
2253
2254 /* lookup if we have other variants in the list */
2255 if (sel->num_shaders > 1) {
2256 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2257
2258 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2259 p = c;
2260 c = c->next_variant;
2261 }
2262
2263 if (c) {
2264 p->next_variant = c->next_variant;
2265 shader = c;
2266 }
2267 }
2268
2269 if (unlikely(!shader)) {
2270 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2271 shader->selector = sel;
2272 shader->key = key;
2273
2274 r = si_pipe_shader_create(ctx, shader);
2275 if (unlikely(r)) {
2276 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2277 sel->type, r);
2278 sel->current = NULL;
2279 FREE(shader);
2280 return r;
2281 }
2282 sel->num_shaders++;
2283 }
2284
2285 if (dirty)
2286 *dirty = 1;
2287
2288 shader->next_variant = sel->current;
2289 sel->current = shader;
2290
2291 return 0;
2292 }
2293
2294 static void *si_create_shader_state(struct pipe_context *ctx,
2295 const struct pipe_shader_state *state,
2296 unsigned pipe_shader_type)
2297 {
2298 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2299 int r;
2300 struct tgsi_shader_info info;
2301
2302 tgsi_scan_shader(state->tokens, &info);
2303
2304 sel->type = pipe_shader_type;
2305 sel->tokens = tgsi_dup_tokens(state->tokens);
2306 sel->so = state->stream_output;
2307 sel->fs_write_all = info.color0_writes_all_cbufs;
2308
2309 r = si_shader_select(ctx, sel, NULL);
2310 if (r) {
2311 free(sel);
2312 return NULL;
2313 }
2314
2315 return sel;
2316 }
2317
2318 static void *si_create_fs_state(struct pipe_context *ctx,
2319 const struct pipe_shader_state *state)
2320 {
2321 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2322 }
2323
2324 static void *si_create_vs_state(struct pipe_context *ctx,
2325 const struct pipe_shader_state *state)
2326 {
2327 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2328 }
2329
2330 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2331 {
2332 struct r600_context *rctx = (struct r600_context *)ctx;
2333 struct si_pipe_shader_selector *sel = state;
2334
2335 if (rctx->vs_shader == sel)
2336 return;
2337
2338 if (!sel || !sel->current)
2339 return;
2340
2341 rctx->vs_shader = sel;
2342 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2343 rctx->b.streamout.stride_in_dw = sel->so.stride;
2344 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2345 }
2346
2347 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2348 {
2349 struct r600_context *rctx = (struct r600_context *)ctx;
2350 struct si_pipe_shader_selector *sel = state;
2351
2352 if (rctx->ps_shader == sel)
2353 return;
2354
2355 if (!sel || !sel->current)
2356 sel = rctx->dummy_pixel_shader;
2357
2358 rctx->ps_shader = sel;
2359 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2360 rctx->b.flags |= R600_CONTEXT_INV_SHADER_CACHE;
2361 }
2362
2363 static void si_delete_shader_selector(struct pipe_context *ctx,
2364 struct si_pipe_shader_selector *sel)
2365 {
2366 struct r600_context *rctx = (struct r600_context *)ctx;
2367 struct si_pipe_shader *p = sel->current, *c;
2368
2369 while (p) {
2370 c = p->next_variant;
2371 si_pm4_delete_state(rctx, vs, p->pm4);
2372 si_pipe_shader_destroy(ctx, p);
2373 free(p);
2374 p = c;
2375 }
2376
2377 free(sel->tokens);
2378 free(sel);
2379 }
2380
2381 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2382 {
2383 struct r600_context *rctx = (struct r600_context *)ctx;
2384 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2385
2386 if (rctx->vs_shader == sel) {
2387 rctx->vs_shader = NULL;
2388 }
2389
2390 si_delete_shader_selector(ctx, sel);
2391 }
2392
2393 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2394 {
2395 struct r600_context *rctx = (struct r600_context *)ctx;
2396 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2397
2398 if (rctx->ps_shader == sel) {
2399 rctx->ps_shader = NULL;
2400 }
2401
2402 si_delete_shader_selector(ctx, sel);
2403 }
2404
2405 /*
2406 * Samplers
2407 */
2408
2409 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2410 struct pipe_resource *texture,
2411 const struct pipe_sampler_view *state)
2412 {
2413 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2414 struct r600_texture *tmp = (struct r600_texture*)texture;
2415 const struct util_format_description *desc;
2416 unsigned format, num_format;
2417 uint32_t pitch = 0;
2418 unsigned char state_swizzle[4], swizzle[4];
2419 unsigned height, depth, width;
2420 enum pipe_format pipe_format = state->format;
2421 struct radeon_surface_level *surflevel;
2422 int first_non_void;
2423 uint64_t va;
2424
2425 if (view == NULL)
2426 return NULL;
2427
2428 /* initialize base object */
2429 view->base = *state;
2430 view->base.texture = NULL;
2431 pipe_resource_reference(&view->base.texture, texture);
2432 view->base.reference.count = 1;
2433 view->base.context = ctx;
2434 view->resource = &tmp->resource;
2435
2436 /* Buffer resource. */
2437 if (texture->target == PIPE_BUFFER) {
2438 unsigned stride;
2439
2440 desc = util_format_description(state->format);
2441 first_non_void = util_format_get_first_non_void_channel(state->format);
2442 stride = desc->block.bits / 8;
2443 va = r600_resource_va(ctx->screen, texture) + state->u.buf.first_element*stride;
2444 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2445 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2446
2447 view->state[0] = va;
2448 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2449 S_008F04_STRIDE(stride);
2450 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2451 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2452 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2453 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2454 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2455 S_008F0C_NUM_FORMAT(num_format) |
2456 S_008F0C_DATA_FORMAT(format);
2457 return &view->base;
2458 }
2459
2460 state_swizzle[0] = state->swizzle_r;
2461 state_swizzle[1] = state->swizzle_g;
2462 state_swizzle[2] = state->swizzle_b;
2463 state_swizzle[3] = state->swizzle_a;
2464
2465 surflevel = tmp->surface.level;
2466
2467 /* Texturing with separate depth and stencil. */
2468 if (tmp->is_depth && !tmp->is_flushing_texture) {
2469 switch (pipe_format) {
2470 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2471 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2472 break;
2473 case PIPE_FORMAT_X8Z24_UNORM:
2474 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2475 /* Z24 is always stored like this. */
2476 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2477 break;
2478 case PIPE_FORMAT_X24S8_UINT:
2479 case PIPE_FORMAT_S8X24_UINT:
2480 case PIPE_FORMAT_X32_S8X24_UINT:
2481 pipe_format = PIPE_FORMAT_S8_UINT;
2482 surflevel = tmp->surface.stencil_level;
2483 break;
2484 default:;
2485 }
2486 }
2487
2488 desc = util_format_description(pipe_format);
2489
2490 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2491 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2492 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2493
2494 switch (pipe_format) {
2495 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2496 case PIPE_FORMAT_X24S8_UINT:
2497 case PIPE_FORMAT_X32_S8X24_UINT:
2498 case PIPE_FORMAT_X8Z24_UNORM:
2499 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2500 break;
2501 default:
2502 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2503 }
2504 } else {
2505 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2506 }
2507
2508 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2509
2510 switch (pipe_format) {
2511 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2512 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2513 break;
2514 default:
2515 if (first_non_void < 0) {
2516 if (util_format_is_compressed(pipe_format)) {
2517 switch (pipe_format) {
2518 case PIPE_FORMAT_DXT1_SRGB:
2519 case PIPE_FORMAT_DXT1_SRGBA:
2520 case PIPE_FORMAT_DXT3_SRGBA:
2521 case PIPE_FORMAT_DXT5_SRGBA:
2522 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2523 break;
2524 case PIPE_FORMAT_RGTC1_SNORM:
2525 case PIPE_FORMAT_LATC1_SNORM:
2526 case PIPE_FORMAT_RGTC2_SNORM:
2527 case PIPE_FORMAT_LATC2_SNORM:
2528 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2529 break;
2530 default:
2531 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2532 break;
2533 }
2534 } else {
2535 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2536 }
2537 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2538 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2539 } else {
2540 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2541
2542 switch (desc->channel[first_non_void].type) {
2543 case UTIL_FORMAT_TYPE_FLOAT:
2544 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2545 break;
2546 case UTIL_FORMAT_TYPE_SIGNED:
2547 if (desc->channel[first_non_void].normalized)
2548 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2549 else if (desc->channel[first_non_void].pure_integer)
2550 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2551 else
2552 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2553 break;
2554 case UTIL_FORMAT_TYPE_UNSIGNED:
2555 if (desc->channel[first_non_void].normalized)
2556 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2557 else if (desc->channel[first_non_void].pure_integer)
2558 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2559 else
2560 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2561 }
2562 }
2563 }
2564
2565 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2566 if (format == ~0) {
2567 format = 0;
2568 }
2569
2570 /* not supported any more */
2571 //endian = si_colorformat_endian_swap(format);
2572
2573 width = surflevel[0].npix_x;
2574 height = surflevel[0].npix_y;
2575 depth = surflevel[0].npix_z;
2576 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2577
2578 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2579 height = 1;
2580 depth = texture->array_size;
2581 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2582 depth = texture->array_size;
2583 }
2584
2585 va = r600_resource_va(ctx->screen, texture);
2586 va += surflevel[0].offset;
2587 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size;
2588 view->state[0] = va >> 8;
2589 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2590 S_008F14_DATA_FORMAT(format) |
2591 S_008F14_NUM_FORMAT(num_format));
2592 view->state[2] = (S_008F18_WIDTH(width - 1) |
2593 S_008F18_HEIGHT(height - 1));
2594 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2595 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2596 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2597 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2598 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2599 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2600 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2601 util_logbase2(texture->nr_samples) :
2602 state->u.tex.last_level - tmp->mipmap_shift) |
2603 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2604 S_008F1C_POW2_PAD(texture->last_level > 0) |
2605 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2606 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2607 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2608 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2609 view->state[6] = 0;
2610 view->state[7] = 0;
2611
2612 /* Initialize the sampler view for FMASK. */
2613 if (tmp->fmask.size) {
2614 uint64_t va = r600_resource_va(ctx->screen, texture) + tmp->fmask.offset;
2615 uint32_t fmask_format;
2616
2617 switch (texture->nr_samples) {
2618 case 2:
2619 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2620 break;
2621 case 4:
2622 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2623 break;
2624 case 8:
2625 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2626 break;
2627 default:
2628 assert(0);
2629 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2630 }
2631
2632 view->fmask_state[0] = va >> 8;
2633 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2634 S_008F14_DATA_FORMAT(fmask_format) |
2635 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2636 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2637 S_008F18_HEIGHT(height - 1);
2638 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2639 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2640 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2641 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2642 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2643 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2644 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2645 S_008F20_PITCH(tmp->fmask.pitch - 1);
2646 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2647 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2648 view->fmask_state[6] = 0;
2649 view->fmask_state[7] = 0;
2650 }
2651
2652 return &view->base;
2653 }
2654
2655 static void si_sampler_view_destroy(struct pipe_context *ctx,
2656 struct pipe_sampler_view *state)
2657 {
2658 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2659
2660 pipe_resource_reference(&state->texture, NULL);
2661 FREE(resource);
2662 }
2663
2664 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2665 {
2666 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2667 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2668 (linear_filter &&
2669 (wrap == PIPE_TEX_WRAP_CLAMP ||
2670 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2671 }
2672
2673 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2674 {
2675 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2676 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2677
2678 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2679 state->border_color.ui[2] || state->border_color.ui[3]) &&
2680 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2681 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2682 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2683 }
2684
2685 static void *si_create_sampler_state(struct pipe_context *ctx,
2686 const struct pipe_sampler_state *state)
2687 {
2688 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2689 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2690 unsigned border_color_type;
2691
2692 if (rstate == NULL) {
2693 return NULL;
2694 }
2695
2696 if (sampler_state_needs_border_color(state))
2697 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2698 else
2699 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2700
2701 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2702 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2703 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2704 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2705 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2706 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2707 aniso_flag_offset << 16 | /* XXX */
2708 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2709 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2710 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2711 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2712 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2713 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2714 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2715 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2716
2717 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2718 memcpy(rstate->border_color, state->border_color.ui,
2719 sizeof(rstate->border_color));
2720 }
2721
2722 return rstate;
2723 }
2724
2725 /* XXX consider moving this function to si_descriptors.c for gcc to inline
2726 * the si_set_sampler_view calls. LTO might help too. */
2727 static void si_set_sampler_views(struct pipe_context *ctx,
2728 unsigned shader, unsigned start,
2729 unsigned count,
2730 struct pipe_sampler_view **views)
2731 {
2732 struct r600_context *rctx = (struct r600_context *)ctx;
2733 struct r600_textures_info *samplers = &rctx->samplers[shader];
2734 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2735 int i;
2736
2737 if (shader != PIPE_SHADER_VERTEX && shader != PIPE_SHADER_FRAGMENT)
2738 return;
2739
2740 assert(start == 0);
2741
2742 for (i = 0; i < count; i++) {
2743 if (!views[i]) {
2744 samplers->depth_texture_mask &= ~(1 << i);
2745 samplers->compressed_colortex_mask &= ~(1 << i);
2746 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2747 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2748 NULL, NULL);
2749 continue;
2750 }
2751
2752 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2753
2754 if (views[i]->texture->target != PIPE_BUFFER) {
2755 struct r600_texture *rtex =
2756 (struct r600_texture*)views[i]->texture;
2757
2758 if (rtex->is_depth && !rtex->is_flushing_texture) {
2759 samplers->depth_texture_mask |= 1 << i;
2760 } else {
2761 samplers->depth_texture_mask &= ~(1 << i);
2762 }
2763 if (rtex->cmask.size || rtex->fmask.size) {
2764 samplers->compressed_colortex_mask |= 1 << i;
2765 } else {
2766 samplers->compressed_colortex_mask &= ~(1 << i);
2767 }
2768
2769 if (rtex->fmask.size) {
2770 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2771 views[i], rviews[i]->fmask_state);
2772 } else {
2773 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2774 NULL, NULL);
2775 }
2776 }
2777 }
2778 for (; i < samplers->n_views; i++) {
2779 samplers->depth_texture_mask &= ~(1 << i);
2780 samplers->compressed_colortex_mask &= ~(1 << i);
2781 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2782 si_set_sampler_view(rctx, shader, FMASK_TEX_OFFSET + i,
2783 NULL, NULL);
2784 }
2785
2786 samplers->n_views = count;
2787 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2788 }
2789
2790 static struct si_pm4_state *si_set_sampler_states(struct r600_context *rctx, unsigned count,
2791 void **states,
2792 struct r600_textures_info *samplers,
2793 unsigned user_data_reg)
2794 {
2795 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2796 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2797 uint32_t *border_color_table = NULL;
2798 int i, j;
2799
2800 if (!count)
2801 goto out;
2802
2803 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE;
2804
2805 si_pm4_sh_data_begin(pm4);
2806 for (i = 0; i < count; i++) {
2807 if (rstates[i] &&
2808 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2809 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2810 if (!rctx->border_color_table ||
2811 ((rctx->border_color_offset + count - i) &
2812 C_008F3C_BORDER_COLOR_PTR)) {
2813 r600_resource_reference(&rctx->border_color_table, NULL);
2814 rctx->border_color_offset = 0;
2815
2816 rctx->border_color_table =
2817 r600_resource_create_custom(&rctx->screen->b.b,
2818 PIPE_USAGE_STAGING,
2819 4096 * 4 * 4);
2820 }
2821
2822 if (!border_color_table) {
2823 border_color_table =
2824 rctx->b.ws->buffer_map(rctx->border_color_table->cs_buf,
2825 rctx->b.rings.gfx.cs,
2826 PIPE_TRANSFER_WRITE |
2827 PIPE_TRANSFER_UNSYNCHRONIZED);
2828 }
2829
2830 for (j = 0; j < 4; j++) {
2831 border_color_table[4 * rctx->border_color_offset + j] =
2832 util_le32_to_cpu(rstates[i]->border_color[j]);
2833 }
2834
2835 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2836 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2837 }
2838
2839 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2840 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2841 }
2842 }
2843 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2844
2845 if (border_color_table) {
2846 uint64_t va_offset =
2847 r600_resource_va(&rctx->screen->b.b,
2848 (void*)rctx->border_color_table);
2849
2850 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2851 if (rctx->b.chip_class >= CIK)
2852 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2853 rctx->b.ws->buffer_unmap(rctx->border_color_table->cs_buf);
2854 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2855 }
2856
2857 memcpy(samplers->samplers, states, sizeof(void*) * count);
2858
2859 out:
2860 samplers->n_samplers = count;
2861 return pm4;
2862 }
2863
2864 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2865 {
2866 struct r600_context *rctx = (struct r600_context *)ctx;
2867 struct si_pm4_state *pm4;
2868
2869 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2870 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2871 si_pm4_set_state(rctx, vs_sampler, pm4);
2872 }
2873
2874 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2875 {
2876 struct r600_context *rctx = (struct r600_context *)ctx;
2877 struct si_pm4_state *pm4;
2878
2879 pm4 = si_set_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2880 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2881 si_pm4_set_state(rctx, ps_sampler, pm4);
2882 }
2883
2884
2885 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2886 unsigned start, unsigned count,
2887 void **states)
2888 {
2889 assert(start == 0);
2890
2891 switch (shader) {
2892 case PIPE_SHADER_VERTEX:
2893 si_bind_vs_sampler_states(ctx, count, states);
2894 break;
2895 case PIPE_SHADER_FRAGMENT:
2896 si_bind_ps_sampler_states(ctx, count, states);
2897 break;
2898 default:
2899 ;
2900 }
2901 }
2902
2903
2904
2905 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2906 {
2907 struct r600_context *rctx = (struct r600_context *)ctx;
2908 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2909 uint16_t mask = sample_mask;
2910
2911 if (pm4 == NULL)
2912 return;
2913
2914 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2915 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2916
2917 si_pm4_set_state(rctx, sample_mask, pm4);
2918 }
2919
2920 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2921 {
2922 free(state);
2923 }
2924
2925 /*
2926 * Vertex elements & buffers
2927 */
2928
2929 static void *si_create_vertex_elements(struct pipe_context *ctx,
2930 unsigned count,
2931 const struct pipe_vertex_element *elements)
2932 {
2933 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2934 int i;
2935
2936 assert(count < PIPE_MAX_ATTRIBS);
2937 if (!v)
2938 return NULL;
2939
2940 v->count = count;
2941 for (i = 0; i < count; ++i) {
2942 const struct util_format_description *desc;
2943 unsigned data_format, num_format;
2944 int first_non_void;
2945
2946 desc = util_format_description(elements[i].src_format);
2947 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2948 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2949 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2950
2951 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2952 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2953 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2954 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2955 S_008F0C_NUM_FORMAT(num_format) |
2956 S_008F0C_DATA_FORMAT(data_format);
2957 }
2958 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2959
2960 return v;
2961 }
2962
2963 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2964 {
2965 struct r600_context *rctx = (struct r600_context *)ctx;
2966 struct si_vertex_element *v = (struct si_vertex_element*)state;
2967
2968 rctx->vertex_elements = v;
2969 }
2970
2971 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2972 {
2973 struct r600_context *rctx = (struct r600_context *)ctx;
2974
2975 if (rctx->vertex_elements == state)
2976 rctx->vertex_elements = NULL;
2977 FREE(state);
2978 }
2979
2980 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2981 const struct pipe_vertex_buffer *buffers)
2982 {
2983 struct r600_context *rctx = (struct r600_context *)ctx;
2984
2985 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2986 }
2987
2988 static void si_set_index_buffer(struct pipe_context *ctx,
2989 const struct pipe_index_buffer *ib)
2990 {
2991 struct r600_context *rctx = (struct r600_context *)ctx;
2992
2993 if (ib) {
2994 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2995 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2996 } else {
2997 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2998 }
2999 }
3000
3001 /*
3002 * Misc
3003 */
3004 static void si_set_polygon_stipple(struct pipe_context *ctx,
3005 const struct pipe_poly_stipple *state)
3006 {
3007 }
3008
3009 static void si_texture_barrier(struct pipe_context *ctx)
3010 {
3011 struct r600_context *rctx = (struct r600_context *)ctx;
3012
3013 rctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
3014 R600_CONTEXT_FLUSH_AND_INV_CB;
3015 }
3016
3017 static void *si_create_blend_custom(struct r600_context *rctx, unsigned mode)
3018 {
3019 struct pipe_blend_state blend;
3020
3021 memset(&blend, 0, sizeof(blend));
3022 blend.independent_blend_enable = true;
3023 blend.rt[0].colormask = 0xf;
3024 return si_create_blend_state_mode(&rctx->b.b, &blend, mode);
3025 }
3026
3027 static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
3028 struct pipe_resource *texture,
3029 const struct pipe_surface *surf_tmpl)
3030 {
3031 struct r600_texture *rtex = (struct r600_texture*)texture;
3032 struct r600_surface *surface = CALLOC_STRUCT(r600_surface);
3033 unsigned level = surf_tmpl->u.tex.level;
3034
3035 if (surface == NULL)
3036 return NULL;
3037
3038 assert(surf_tmpl->u.tex.first_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3039 assert(surf_tmpl->u.tex.last_layer <= util_max_layer(texture, surf_tmpl->u.tex.level));
3040
3041 pipe_reference_init(&surface->base.reference, 1);
3042 pipe_resource_reference(&surface->base.texture, texture);
3043 surface->base.context = pipe;
3044 surface->base.format = surf_tmpl->format;
3045 surface->base.width = rtex->surface.level[level].npix_x;
3046 surface->base.height = rtex->surface.level[level].npix_y;
3047 surface->base.texture = texture;
3048 surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
3049 surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
3050 surface->base.u.tex.level = level;
3051
3052 return &surface->base;
3053 }
3054
3055 static void r600_surface_destroy(struct pipe_context *pipe,
3056 struct pipe_surface *surface)
3057 {
3058 pipe_resource_reference(&surface->texture, NULL);
3059 FREE(surface);
3060 }
3061
3062 static boolean si_dma_copy(struct pipe_context *ctx,
3063 struct pipe_resource *dst,
3064 unsigned dst_level,
3065 unsigned dst_x, unsigned dst_y, unsigned dst_z,
3066 struct pipe_resource *src,
3067 unsigned src_level,
3068 const struct pipe_box *src_box)
3069 {
3070 /* XXX implement this or share evergreen_dma_blit with r600g */
3071 return FALSE;
3072 }
3073
3074 void si_init_state_functions(struct r600_context *rctx)
3075 {
3076 int i;
3077
3078 rctx->b.b.create_blend_state = si_create_blend_state;
3079 rctx->b.b.bind_blend_state = si_bind_blend_state;
3080 rctx->b.b.delete_blend_state = si_delete_blend_state;
3081 rctx->b.b.set_blend_color = si_set_blend_color;
3082
3083 rctx->b.b.create_rasterizer_state = si_create_rs_state;
3084 rctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3085 rctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3086
3087 rctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3088 rctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3089 rctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3090
3091 for (i = 0; i < 8; i++) {
3092 rctx->custom_dsa_flush_depth_stencil[i] = si_create_db_flush_dsa(rctx, true, true, i);
3093 rctx->custom_dsa_flush_depth[i] = si_create_db_flush_dsa(rctx, true, false, i);
3094 rctx->custom_dsa_flush_stencil[i] = si_create_db_flush_dsa(rctx, false, true, i);
3095 }
3096 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false, 0);
3097 rctx->custom_blend_resolve = si_create_blend_custom(rctx, V_028808_CB_RESOLVE);
3098 rctx->custom_blend_decompress = si_create_blend_custom(rctx, V_028808_CB_FMASK_DECOMPRESS);
3099
3100 rctx->b.b.set_clip_state = si_set_clip_state;
3101 rctx->b.b.set_scissor_states = si_set_scissor_states;
3102 rctx->b.b.set_viewport_states = si_set_viewport_states;
3103 rctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3104
3105 rctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3106 rctx->b.b.get_sample_position = si_get_sample_position;
3107
3108 rctx->b.b.create_vs_state = si_create_vs_state;
3109 rctx->b.b.create_fs_state = si_create_fs_state;
3110 rctx->b.b.bind_vs_state = si_bind_vs_shader;
3111 rctx->b.b.bind_fs_state = si_bind_ps_shader;
3112 rctx->b.b.delete_vs_state = si_delete_vs_shader;
3113 rctx->b.b.delete_fs_state = si_delete_ps_shader;
3114
3115 rctx->b.b.create_sampler_state = si_create_sampler_state;
3116 rctx->b.b.bind_sampler_states = si_bind_sampler_states;
3117 rctx->b.b.delete_sampler_state = si_delete_sampler_state;
3118
3119 rctx->b.b.create_sampler_view = si_create_sampler_view;
3120 rctx->b.b.set_sampler_views = si_set_sampler_views;
3121 rctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3122
3123 rctx->b.b.set_sample_mask = si_set_sample_mask;
3124
3125 rctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3126 rctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3127 rctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3128 rctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3129 rctx->b.b.set_index_buffer = si_set_index_buffer;
3130
3131 rctx->b.b.texture_barrier = si_texture_barrier;
3132 rctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3133 rctx->b.b.create_surface = r600_create_surface;
3134 rctx->b.b.surface_destroy = r600_surface_destroy;
3135 rctx->b.dma_copy = si_dma_copy;
3136
3137 rctx->b.b.draw_vbo = si_draw_vbo;
3138 }
3139
3140 void si_init_config(struct r600_context *rctx)
3141 {
3142 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3143
3144 if (pm4 == NULL)
3145 return;
3146
3147 si_cmd_context_control(pm4);
3148
3149 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3150
3151 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3152 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3153 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3154 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3155 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3156 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3157 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3158 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3159 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3160 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3161 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3162 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3163 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3164 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3165 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3166 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3167 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3168 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3169 if (rctx->b.chip_class == SI) {
3170 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3171 S_028AA8_SWITCH_ON_EOP(1) |
3172 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3173 S_028AA8_PRIMGROUP_SIZE(63));
3174 }
3175 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3176 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3177 if (rctx->b.chip_class < CIK)
3178 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3179 S_008A14_CLIP_VTX_REORDER_ENA(1));
3180
3181 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3182 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3183 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3184
3185 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3186
3187 if (rctx->b.chip_class >= CIK) {
3188 switch (rctx->screen->b.family) {
3189 case CHIP_BONAIRE:
3190 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3191 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3192 break;
3193 case CHIP_HAWAII:
3194 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3195 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3196 break;
3197 case CHIP_KAVERI:
3198 /* XXX todo */
3199 case CHIP_KABINI:
3200 /* XXX todo */
3201 default:
3202 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3203 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3204 break;
3205 }
3206 } else {
3207 switch (rctx->screen->b.family) {
3208 case CHIP_TAHITI:
3209 case CHIP_PITCAIRN:
3210 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3211 break;
3212 case CHIP_VERDE:
3213 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3214 break;
3215 case CHIP_OLAND:
3216 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3217 break;
3218 case CHIP_HAINAN:
3219 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3220 break;
3221 default:
3222 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3223 break;
3224 }
3225 }
3226
3227 si_pm4_set_state(rctx, init, pm4);
3228 }