2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
37 unsigned img_format
: 9;
39 /* Various formats are only supported with workarounds for vertex fetch,
40 * and some 32_32_32 formats are supported natively, but only for buffers
41 * (possibly with some image support, actually, but no filtering). */
42 bool buffers_only
: 1;
45 #include "gfx10_format_table.h"
47 static unsigned si_map_swizzle(unsigned swizzle
)
51 return V_008F0C_SQ_SEL_Y
;
53 return V_008F0C_SQ_SEL_Z
;
55 return V_008F0C_SQ_SEL_W
;
57 return V_008F0C_SQ_SEL_0
;
59 return V_008F0C_SQ_SEL_1
;
60 default: /* PIPE_SWIZZLE_X */
61 return V_008F0C_SQ_SEL_X
;
65 /* 12.4 fixed-point */
66 static unsigned si_pack_float_12p4(float x
)
68 return x
<= 0 ? 0 : x
>= 4096 ? 0xffff : x
* 16;
72 * Inferred framebuffer and blender state.
74 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
75 * if there is not enough PS outputs.
77 static void si_emit_cb_render_state(struct si_context
*sctx
)
79 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
80 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
81 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
82 * but you never know. */
83 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
& blend
->cb_target_mask
;
86 /* Avoid a hang that happens when dual source blending is enabled
87 * but there is not enough color outputs. This is undefined behavior,
88 * so disable color writes completely.
90 * Reproducible with Unigine Heaven 4.0 and drirc missing.
92 if (blend
->dual_src_blend
&& sctx
->ps_shader
.cso
&&
93 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
96 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
97 * I think we don't have to do anything between IBs.
99 if (sctx
->screen
->dpbb_allowed
&& sctx
->last_cb_target_mask
!= cb_target_mask
) {
100 sctx
->last_cb_target_mask
= cb_target_mask
;
102 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
103 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
106 unsigned initial_cdw
= cs
->current
.cdw
;
107 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
, SI_TRACKED_CB_TARGET_MASK
,
110 if (sctx
->chip_class
>= GFX8
) {
111 /* DCC MSAA workaround.
112 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
113 * COMBINER_DISABLE, but that would be more complicated.
116 blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&& sctx
->framebuffer
.nr_samples
>= 2;
117 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
119 radeon_opt_set_context_reg(
120 sctx
, R_028424_CB_DCC_CONTROL
, SI_TRACKED_CB_DCC_CONTROL
,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
127 /* RB+ register settings. */
128 if (sctx
->screen
->info
.rbplus_allowed
) {
129 unsigned spi_shader_col_format
=
130 sctx
->ps_shader
.cso
? sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
132 unsigned sx_ps_downconvert
= 0;
133 unsigned sx_blend_opt_epsilon
= 0;
134 unsigned sx_blend_opt_control
= 0;
136 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
137 struct si_surface
*surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
138 unsigned format
, swap
, spi_format
, colormask
;
139 bool has_alpha
, has_rgb
;
142 /* If the color buffer is not set, the driver sets 32_R
143 * as the SPI color format, because the hw doesn't allow
144 * holes between color outputs, so also set this to
147 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
151 format
= G_028C70_FORMAT(surf
->cb_color_info
);
152 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
153 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
154 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
156 /* Set if RGB and A are present. */
157 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
159 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_16
||
160 format
== V_028C70_COLOR_32
)
161 has_rgb
= !has_alpha
;
165 /* Check the colormask and export format. */
166 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
168 if (!(colormask
& PIPE_MASK_A
))
171 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
176 /* Disable value checking for disabled channels. */
178 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
180 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
182 /* Enable down-conversion for 32bpp and smaller formats. */
184 case V_028C70_COLOR_8
:
185 case V_028C70_COLOR_8_8
:
186 case V_028C70_COLOR_8_8_8_8
:
187 /* For 1 and 2-channel formats, use the superset thereof. */
188 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
189 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
190 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
191 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
192 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
196 case V_028C70_COLOR_5_6_5
:
197 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
198 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
199 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
203 case V_028C70_COLOR_1_5_5_5
:
204 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
205 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
206 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
210 case V_028C70_COLOR_4_4_4_4
:
211 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
212 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
213 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
217 case V_028C70_COLOR_32
:
218 if (swap
== V_028C70_SWAP_STD
&& spi_format
== V_028714_SPI_SHADER_32_R
)
219 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
220 else if (swap
== V_028C70_SWAP_ALT_REV
&& spi_format
== V_028714_SPI_SHADER_32_AR
)
221 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
224 case V_028C70_COLOR_16
:
225 case V_028C70_COLOR_16_16
:
226 /* For 1-channel formats, use the superset thereof. */
227 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
228 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
229 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
230 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
231 if (swap
== V_028C70_SWAP_STD
|| swap
== V_028C70_SWAP_STD_REV
)
232 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
238 case V_028C70_COLOR_10_11_11
:
239 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
240 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
243 case V_028C70_COLOR_2_10_10_10
:
244 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
245 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
246 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
252 /* If there are no color outputs, the first color export is
253 * always enabled as 32_R, so also set this to enable RB+.
255 if (!sx_ps_downconvert
)
256 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
258 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
259 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
, SI_TRACKED_SX_PS_DOWNCONVERT
,
260 sx_ps_downconvert
, sx_blend_opt_epsilon
, sx_blend_opt_control
);
262 if (initial_cdw
!= cs
->current
.cdw
)
263 sctx
->context_roll
= true;
270 static uint32_t si_translate_blend_function(int blend_func
)
272 switch (blend_func
) {
274 return V_028780_COMB_DST_PLUS_SRC
;
275 case PIPE_BLEND_SUBTRACT
:
276 return V_028780_COMB_SRC_MINUS_DST
;
277 case PIPE_BLEND_REVERSE_SUBTRACT
:
278 return V_028780_COMB_DST_MINUS_SRC
;
280 return V_028780_COMB_MIN_DST_SRC
;
282 return V_028780_COMB_MAX_DST_SRC
;
284 PRINT_ERR("Unknown blend function %d\n", blend_func
);
291 static uint32_t si_translate_blend_factor(int blend_fact
)
293 switch (blend_fact
) {
294 case PIPE_BLENDFACTOR_ONE
:
295 return V_028780_BLEND_ONE
;
296 case PIPE_BLENDFACTOR_SRC_COLOR
:
297 return V_028780_BLEND_SRC_COLOR
;
298 case PIPE_BLENDFACTOR_SRC_ALPHA
:
299 return V_028780_BLEND_SRC_ALPHA
;
300 case PIPE_BLENDFACTOR_DST_ALPHA
:
301 return V_028780_BLEND_DST_ALPHA
;
302 case PIPE_BLENDFACTOR_DST_COLOR
:
303 return V_028780_BLEND_DST_COLOR
;
304 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
305 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
306 case PIPE_BLENDFACTOR_CONST_COLOR
:
307 return V_028780_BLEND_CONSTANT_COLOR
;
308 case PIPE_BLENDFACTOR_CONST_ALPHA
:
309 return V_028780_BLEND_CONSTANT_ALPHA
;
310 case PIPE_BLENDFACTOR_ZERO
:
311 return V_028780_BLEND_ZERO
;
312 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
313 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
314 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
315 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
316 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
317 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
318 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
319 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
320 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
322 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
324 case PIPE_BLENDFACTOR_SRC1_COLOR
:
325 return V_028780_BLEND_SRC1_COLOR
;
326 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
327 return V_028780_BLEND_SRC1_ALPHA
;
328 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
329 return V_028780_BLEND_INV_SRC1_COLOR
;
330 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
331 return V_028780_BLEND_INV_SRC1_ALPHA
;
333 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
340 static uint32_t si_translate_blend_opt_function(int blend_func
)
342 switch (blend_func
) {
344 return V_028760_OPT_COMB_ADD
;
345 case PIPE_BLEND_SUBTRACT
:
346 return V_028760_OPT_COMB_SUBTRACT
;
347 case PIPE_BLEND_REVERSE_SUBTRACT
:
348 return V_028760_OPT_COMB_REVSUBTRACT
;
350 return V_028760_OPT_COMB_MIN
;
352 return V_028760_OPT_COMB_MAX
;
354 return V_028760_OPT_COMB_BLEND_DISABLED
;
358 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
360 switch (blend_fact
) {
361 case PIPE_BLENDFACTOR_ZERO
:
362 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
363 case PIPE_BLENDFACTOR_ONE
:
364 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
365 case PIPE_BLENDFACTOR_SRC_COLOR
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
367 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
368 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
369 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
370 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
371 case PIPE_BLENDFACTOR_SRC_ALPHA
:
372 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
373 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
374 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
375 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
376 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
377 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
379 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
383 static void si_blend_check_commutativity(struct si_screen
*sscreen
, struct si_state_blend
*blend
,
384 enum pipe_blend_func func
, enum pipe_blendfactor src
,
385 enum pipe_blendfactor dst
, unsigned chanmask
)
387 /* Src factor is allowed when it does not depend on Dst */
388 static const uint32_t src_allowed
=
389 (1u << PIPE_BLENDFACTOR_ONE
) | (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
391 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
392 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
393 (1u << PIPE_BLENDFACTOR_ZERO
) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
394 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
395 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
398 if (dst
== PIPE_BLENDFACTOR_ONE
&& (src_allowed
& (1u << src
))) {
399 /* Addition is commutative, but floating point addition isn't
400 * associative: subtle changes can be introduced via different
403 * Out-of-order is also non-deterministic, which means that
404 * this breaks OpenGL invariance requirements. So only enable
405 * out-of-order additive blending if explicitly allowed by a
408 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
409 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
410 blend
->commutative_4bit
|= chanmask
;
415 * Get rid of DST in the blend factors by commuting the operands:
416 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
, unsigned *dst_factor
,
419 unsigned expected_dst
, unsigned replacement_src
)
421 if (*src_factor
== expected_dst
&& *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
422 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
423 *dst_factor
= replacement_src
;
425 /* Commuting the operands requires reversing subtractions. */
426 if (*func
== PIPE_BLEND_SUBTRACT
)
427 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
428 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
429 *func
= PIPE_BLEND_SUBTRACT
;
433 static bool si_blend_factor_uses_dst(unsigned factor
)
435 return factor
== PIPE_BLENDFACTOR_DST_COLOR
|| factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
436 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
437 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
|| factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
440 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
441 const struct pipe_blend_state
*state
, unsigned mode
)
443 struct si_context
*sctx
= (struct si_context
*)ctx
;
444 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
445 struct si_pm4_state
*pm4
= &blend
->pm4
;
446 uint32_t sx_mrt_blend_opt
[8] = {0};
447 uint32_t color_control
= 0;
448 bool logicop_enable
= state
->logicop_enable
&& state
->logicop_func
!= PIPE_LOGICOP_COPY
;
453 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
454 blend
->alpha_to_one
= state
->alpha_to_one
;
455 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
456 blend
->logicop_enable
= logicop_enable
;
458 if (logicop_enable
) {
459 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
461 color_control
|= S_028808_ROP3(0xcc);
464 if (state
->alpha_to_coverage
&& state
->alpha_to_coverage_dither
) {
465 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
468 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
469 S_028B70_OFFSET_ROUND(1));
471 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
472 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
473 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
475 S_028B70_OFFSET_ROUND(0));
478 if (state
->alpha_to_coverage
)
479 blend
->need_src_alpha_4bit
|= 0xf;
481 blend
->cb_target_mask
= 0;
482 blend
->cb_target_enabled_4bit
= 0;
484 for (int i
= 0; i
< 8; i
++) {
485 /* state->rt entries > 0 only written if independent blending */
486 const int j
= state
->independent_blend_enable
? i
: 0;
488 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
489 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
490 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
491 unsigned eqA
= state
->rt
[j
].alpha_func
;
492 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
493 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
495 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
496 unsigned blend_cntl
= 0;
498 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
499 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
501 /* Only set dual source blending for MRT0 to avoid a hang. */
502 if (i
>= 1 && blend
->dual_src_blend
) {
503 /* Vulkan does this for dual source blending. */
505 blend_cntl
|= S_028780_ENABLE(1);
507 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
511 /* Only addition and subtraction equations are supported with
512 * dual source blending.
514 if (blend
->dual_src_blend
&& (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
515 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
521 /* cb_render_state will disable unused ones */
522 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
523 if (state
->rt
[j
].colormask
)
524 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
526 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
527 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
531 si_blend_check_commutativity(sctx
->screen
, blend
, eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
532 si_blend_check_commutativity(sctx
->screen
, blend
, eqA
, srcA
, dstA
, 0x8 << (4 * i
));
534 /* Blending optimizations for RB+.
535 * These transformations don't change the behavior.
537 * First, get rid of DST in the blend factors:
538 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
540 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
, PIPE_BLENDFACTOR_DST_COLOR
,
541 PIPE_BLENDFACTOR_SRC_COLOR
);
542 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_COLOR
,
543 PIPE_BLENDFACTOR_SRC_COLOR
);
544 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_ALPHA
,
545 PIPE_BLENDFACTOR_SRC_ALPHA
);
547 /* Look up the ideal settings from tables. */
548 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
549 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
550 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
551 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
553 /* Handle interdependencies. */
554 if (si_blend_factor_uses_dst(srcRGB
))
555 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
556 if (si_blend_factor_uses_dst(srcA
))
557 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
559 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
560 (dstRGB
== PIPE_BLENDFACTOR_ZERO
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
561 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
562 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
564 /* Set the final value. */
565 sx_mrt_blend_opt
[i
] = S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
566 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
567 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
568 S_028760_ALPHA_SRC_OPT(srcA_opt
) | S_028760_ALPHA_DST_OPT(dstA_opt
) |
569 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
571 /* Set blend state. */
572 blend_cntl
|= S_028780_ENABLE(1);
573 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
574 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
575 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
577 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
578 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
579 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
580 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
581 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
583 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
585 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
587 if (sctx
->chip_class
>= GFX8
&& sctx
->family
<= CHIP_NAVI14
)
588 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
590 /* This is only important for formats without alpha. */
591 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
592 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
593 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
594 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
595 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
598 if (sctx
->chip_class
>= GFX8
&& sctx
->family
<= CHIP_NAVI14
&& logicop_enable
)
599 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
601 if (blend
->cb_target_mask
) {
602 color_control
|= S_028808_MODE(mode
);
604 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
607 if (sctx
->screen
->info
.rbplus_allowed
) {
608 /* Disable RB+ blend optimizations for dual source blending.
611 if (blend
->dual_src_blend
) {
612 for (int i
= 0; i
< 8; i
++) {
613 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
614 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
618 for (int i
= 0; i
< 8; i
++)
619 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4, sx_mrt_blend_opt
[i
]);
621 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
622 if (blend
->dual_src_blend
|| logicop_enable
|| mode
== V_028808_CB_RESOLVE
)
623 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
626 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
630 static void *si_create_blend_state(struct pipe_context
*ctx
, const struct pipe_blend_state
*state
)
632 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
635 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
637 struct si_context
*sctx
= (struct si_context
*)ctx
;
638 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
639 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
642 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
644 si_pm4_bind_state(sctx
, blend
, blend
);
646 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
647 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
648 (old_blend
->dcc_msaa_corruption_4bit
!= blend
->dcc_msaa_corruption_4bit
&&
649 sctx
->framebuffer
.nr_samples
>= 2 && sctx
->screen
->dcc_msaa_allowed
))
650 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
652 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
653 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
654 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
655 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
656 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
657 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
658 sctx
->do_update_shaders
= true;
660 if (sctx
->screen
->dpbb_allowed
&&
661 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
662 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
663 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
664 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
666 if (sctx
->screen
->has_out_of_order_rast
&&
667 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
668 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
669 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
670 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
671 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
674 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
676 struct si_context
*sctx
= (struct si_context
*)ctx
;
678 if (sctx
->queued
.named
.blend
== state
)
679 si_bind_blend_state(ctx
, sctx
->noop_blend
);
681 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
684 static void si_set_blend_color(struct pipe_context
*ctx
, const struct pipe_blend_color
*state
)
686 struct si_context
*sctx
= (struct si_context
*)ctx
;
687 static const struct pipe_blend_color zeros
;
689 sctx
->blend_color
.state
= *state
;
690 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
691 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
694 static void si_emit_blend_color(struct si_context
*sctx
)
696 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
698 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
699 radeon_emit_array(cs
, (uint32_t *)sctx
->blend_color
.state
.color
, 4);
706 static void si_set_clip_state(struct pipe_context
*ctx
, const struct pipe_clip_state
*state
)
708 struct si_context
*sctx
= (struct si_context
*)ctx
;
709 struct pipe_constant_buffer cb
;
710 static const struct pipe_clip_state zeros
;
712 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
715 sctx
->clip_state
.state
= *state
;
716 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
717 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
720 cb
.user_buffer
= state
->ucp
;
721 cb
.buffer_offset
= 0;
722 cb
.buffer_size
= 4 * 4 * 8;
723 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
724 pipe_resource_reference(&cb
.buffer
, NULL
);
727 static void si_emit_clip_state(struct si_context
*sctx
)
729 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
731 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6 * 4);
732 radeon_emit_array(cs
, (uint32_t *)sctx
->clip_state
.state
.ucp
, 6 * 4);
735 static void si_emit_clip_regs(struct si_context
*sctx
)
737 struct si_shader
*vs
= si_get_vs_state(sctx
);
738 struct si_shader_selector
*vs_sel
= vs
->selector
;
739 struct si_shader_info
*info
= &vs_sel
->info
;
740 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
741 unsigned window_space
= info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
742 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
743 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
744 unsigned culldist_mask
= vs_sel
->culldist_mask
;
747 if (vs
->key
.opt
.clip_disable
) {
748 assert(!info
->culldist_writemask
);
752 total_mask
= clipdist_mask
| culldist_mask
;
754 /* Clip distances on points have no effect, so need to be implemented
755 * as cull distances. This applies for the clipvertex case as well.
757 * Setting this for primitives other than points should have no adverse
760 clipdist_mask
&= rs
->clip_plane_enable
;
761 culldist_mask
|= clipdist_mask
;
763 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
764 unsigned pa_cl_cntl
= S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
765 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) | clipdist_mask
|
766 (culldist_mask
<< 8);
768 if (sctx
->chip_class
>= GFX10
) {
769 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
770 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
, pa_cl_cntl
,
771 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
773 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
774 vs_sel
->pa_cl_vs_out_cntl
| pa_cl_cntl
);
776 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
, SI_TRACKED_PA_CL_CLIP_CNTL
,
777 rs
->pa_cl_clip_cntl
| ucp_mask
| S_028810_CLIP_DISABLE(window_space
));
779 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
780 sctx
->context_roll
= true;
784 * inferred state between framebuffer and rasterizer
786 static void si_update_poly_offset_state(struct si_context
*sctx
)
788 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
790 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
791 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
795 /* Use the user format, not db_render_format, so that the polygon
796 * offset behaves as expected by applications.
798 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
799 case PIPE_FORMAT_Z16_UNORM
:
800 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
802 default: /* 24-bit */
803 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
805 case PIPE_FORMAT_Z32_FLOAT
:
806 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
807 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
816 static uint32_t si_translate_fill(uint32_t func
)
819 case PIPE_POLYGON_MODE_FILL
:
820 return V_028814_X_DRAW_TRIANGLES
;
821 case PIPE_POLYGON_MODE_LINE
:
822 return V_028814_X_DRAW_LINES
;
823 case PIPE_POLYGON_MODE_POINT
:
824 return V_028814_X_DRAW_POINTS
;
827 return V_028814_X_DRAW_POINTS
;
831 static void *si_create_rs_state(struct pipe_context
*ctx
, const struct pipe_rasterizer_state
*state
)
833 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
834 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
835 struct si_pm4_state
*pm4
= &rs
->pm4
;
837 float psize_min
, psize_max
;
843 if (!state
->front_ccw
) {
844 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
845 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
847 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
848 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
850 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
851 rs
->provoking_vertex_first
= state
->flatshade_first
;
852 rs
->scissor_enable
= state
->scissor
;
853 rs
->clip_halfz
= state
->clip_halfz
;
854 rs
->two_side
= state
->light_twoside
;
855 rs
->multisample_enable
= state
->multisample
;
856 rs
->force_persample_interp
= state
->force_persample_interp
;
857 rs
->clip_plane_enable
= state
->clip_plane_enable
;
858 rs
->half_pixel_center
= state
->half_pixel_center
;
859 rs
->line_stipple_enable
= state
->line_stipple_enable
;
860 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
861 rs
->line_smooth
= state
->line_smooth
;
862 rs
->line_width
= state
->line_width
;
863 rs
->poly_smooth
= state
->poly_smooth
;
864 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
865 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
866 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
867 rs
->flatshade
= state
->flatshade
;
868 rs
->flatshade_first
= state
->flatshade_first
;
869 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
870 rs
->rasterizer_discard
= state
->rasterizer_discard
;
871 rs
->polygon_mode_enabled
=
872 (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
873 (state
->fill_back
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_BACK
));
874 rs
->polygon_mode_is_lines
=
875 (state
->fill_front
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
876 (state
->fill_back
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_BACK
));
877 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
878 ? S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
879 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
)
881 rs
->pa_cl_clip_cntl
= S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
882 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
883 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
884 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
885 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
888 pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
889 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
890 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
891 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
892 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
893 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
894 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
896 /* point size 12.4 fixed point */
897 tmp
= (unsigned)(state
->point_size
* 8.0);
898 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
900 if (state
->point_size_per_vertex
) {
901 psize_min
= util_get_min_point_size(state
);
902 psize_max
= SI_MAX_POINT_SIZE
;
904 /* Force the point size to be as if the vertex output was disabled. */
905 psize_min
= state
->point_size
;
906 psize_max
= state
->point_size
;
908 rs
->max_point_size
= psize_max
;
910 /* Divide by two, because 0.5 = 1 pixel. */
911 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
912 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/ 2)) |
913 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/ 2)));
915 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
916 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/ 2)));
918 pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
919 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
920 S_028A48_MSAA_ENABLE(state
->multisample
|| state
->poly_smooth
|| state
->line_smooth
) |
921 S_028A48_VPORT_SCISSOR_ENABLE(1) |
922 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
924 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
925 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
926 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
927 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
928 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
929 S_028814_FACE(!state
->front_ccw
) |
930 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
931 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
932 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
933 S_028814_POLY_MODE(rs
->polygon_mode_enabled
) |
934 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
935 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
937 if (!rs
->uses_poly_offset
)
940 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
941 if (!rs
->pm4_poly_offset
) {
946 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
947 for (i
= 0; i
< 3; i
++) {
948 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
949 float offset_units
= state
->offset_units
;
950 float offset_scale
= state
->offset_scale
* 16.0f
;
951 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
953 if (!state
->offset_units_unscaled
) {
955 case 0: /* 16-bit zbuffer */
956 offset_units
*= 4.0f
;
957 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
959 case 1: /* 24-bit zbuffer */
960 offset_units
*= 2.0f
;
961 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
963 case 2: /* 32-bit zbuffer */
964 offset_units
*= 1.0f
;
965 pa_su_poly_offset_db_fmt_cntl
=
966 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
971 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, fui(offset_scale
));
972 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
973 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, fui(offset_scale
));
974 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
975 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, pa_su_poly_offset_db_fmt_cntl
);
981 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
983 struct si_context
*sctx
= (struct si_context
*)ctx
;
984 struct si_state_rasterizer
*old_rs
= (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
985 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
988 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
990 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
991 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
993 /* Update the small primitive filter workaround if necessary. */
994 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1)
995 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
998 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
999 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1001 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1002 si_update_poly_offset_state(sctx
);
1004 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1005 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1007 if (old_rs
->line_width
!= rs
->line_width
|| old_rs
->max_point_size
!= rs
->max_point_size
||
1008 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1009 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1011 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1012 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1014 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1015 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1016 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1018 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1019 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1020 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1021 old_rs
->flatshade
!= rs
->flatshade
|| old_rs
->two_side
!= rs
->two_side
||
1022 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1023 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1024 old_rs
->poly_smooth
!= rs
->poly_smooth
|| old_rs
->line_smooth
!= rs
->line_smooth
||
1025 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1026 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1027 sctx
->do_update_shaders
= true;
1030 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1032 struct si_context
*sctx
= (struct si_context
*)ctx
;
1033 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1035 if (sctx
->queued
.named
.rasterizer
== state
)
1036 si_bind_rs_state(ctx
, sctx
->discard_rasterizer_state
);
1038 FREE(rs
->pm4_poly_offset
);
1039 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1043 * infeered state between dsa and stencil ref
1045 static void si_emit_stencil_ref(struct si_context
*sctx
)
1047 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1048 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1049 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1051 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1052 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1053 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1054 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) | S_028430_STENCILOPVAL(1));
1055 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1056 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1057 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1058 S_028434_STENCILOPVAL_BF(1));
1061 static void si_set_stencil_ref(struct pipe_context
*ctx
, const struct pipe_stencil_ref
*state
)
1063 struct si_context
*sctx
= (struct si_context
*)ctx
;
1065 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1068 sctx
->stencil_ref
.state
= *state
;
1069 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1076 static uint32_t si_translate_stencil_op(int s_op
)
1079 case PIPE_STENCIL_OP_KEEP
:
1080 return V_02842C_STENCIL_KEEP
;
1081 case PIPE_STENCIL_OP_ZERO
:
1082 return V_02842C_STENCIL_ZERO
;
1083 case PIPE_STENCIL_OP_REPLACE
:
1084 return V_02842C_STENCIL_REPLACE_TEST
;
1085 case PIPE_STENCIL_OP_INCR
:
1086 return V_02842C_STENCIL_ADD_CLAMP
;
1087 case PIPE_STENCIL_OP_DECR
:
1088 return V_02842C_STENCIL_SUB_CLAMP
;
1089 case PIPE_STENCIL_OP_INCR_WRAP
:
1090 return V_02842C_STENCIL_ADD_WRAP
;
1091 case PIPE_STENCIL_OP_DECR_WRAP
:
1092 return V_02842C_STENCIL_SUB_WRAP
;
1093 case PIPE_STENCIL_OP_INVERT
:
1094 return V_02842C_STENCIL_INVERT
;
1096 PRINT_ERR("Unknown stencil op %d", s_op
);
1103 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1105 return s
->enabled
&& s
->writemask
&&
1106 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
|| s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1107 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1110 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1112 /* REPLACE is normally order invariant, except when the stencil
1113 * reference value is written by the fragment shader. Tracking this
1114 * interaction does not seem worth the effort, so be conservative. */
1115 return op
!= PIPE_STENCIL_OP_INCR
&& op
!= PIPE_STENCIL_OP_DECR
&& op
!= PIPE_STENCIL_OP_REPLACE
;
1118 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1119 * invariant in the sense that the set of passing fragments as well as the
1120 * final stencil buffer result does not depend on the order of fragments. */
1121 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1123 return !state
->enabled
|| !state
->writemask
||
1124 /* The following assumes that Z writes are disabled. */
1125 (state
->func
== PIPE_FUNC_ALWAYS
&& si_order_invariant_stencil_op(state
->zpass_op
) &&
1126 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1127 (state
->func
== PIPE_FUNC_NEVER
&& si_order_invariant_stencil_op(state
->fail_op
));
1130 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1131 const struct pipe_depth_stencil_alpha_state
*state
)
1133 struct si_context
*sctx
= (struct si_context
*)ctx
;
1134 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1135 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1136 unsigned db_depth_control
;
1137 uint32_t db_stencil_control
= 0;
1143 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1144 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1145 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1146 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1149 S_028800_Z_ENABLE(state
->depth
.enabled
) | S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1150 S_028800_ZFUNC(state
->depth
.func
) | S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1153 if (state
->stencil
[0].enabled
) {
1154 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1155 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1156 db_stencil_control
|=
1157 S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1158 db_stencil_control
|=
1159 S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1160 db_stencil_control
|=
1161 S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1163 if (state
->stencil
[1].enabled
) {
1164 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1165 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1166 db_stencil_control
|=
1167 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1168 db_stencil_control
|=
1169 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1170 db_stencil_control
|=
1171 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1176 if (state
->alpha
.enabled
) {
1177 dsa
->alpha_func
= state
->alpha
.func
;
1179 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+ SI_SGPR_ALPHA_REF
* 4,
1180 fui(state
->alpha
.ref_value
));
1182 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1185 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1186 if (state
->stencil
[0].enabled
)
1187 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1188 if (state
->depth
.bounds_test
) {
1189 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1190 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1193 dsa
->depth_enabled
= state
->depth
.enabled
;
1194 dsa
->depth_write_enabled
= state
->depth
.enabled
&& state
->depth
.writemask
;
1195 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1196 dsa
->stencil_write_enabled
=
1197 state
->stencil
[0].enabled
&&
1198 (si_dsa_writes_stencil(&state
->stencil
[0]) || si_dsa_writes_stencil(&state
->stencil
[1]));
1199 dsa
->db_can_write
= dsa
->depth_write_enabled
|| dsa
->stencil_write_enabled
;
1201 bool zfunc_is_ordered
=
1202 state
->depth
.func
== PIPE_FUNC_NEVER
|| state
->depth
.func
== PIPE_FUNC_LESS
||
1203 state
->depth
.func
== PIPE_FUNC_LEQUAL
|| state
->depth
.func
== PIPE_FUNC_GREATER
||
1204 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1206 bool nozwrite_and_order_invariant_stencil
=
1207 !dsa
->db_can_write
||
1208 (!dsa
->depth_write_enabled
&& si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1209 si_order_invariant_stencil_state(&state
->stencil
[1]));
1211 dsa
->order_invariance
[1].zs
=
1212 nozwrite_and_order_invariant_stencil
|| (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1213 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1215 dsa
->order_invariance
[1].pass_set
=
1216 nozwrite_and_order_invariant_stencil
||
1217 (!dsa
->stencil_write_enabled
&&
1218 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
));
1219 dsa
->order_invariance
[0].pass_set
=
1220 !dsa
->depth_write_enabled
||
1221 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
);
1223 dsa
->order_invariance
[1].pass_last
= sctx
->screen
->assume_no_z_fights
&&
1224 !dsa
->stencil_write_enabled
&& dsa
->depth_write_enabled
&&
1226 dsa
->order_invariance
[0].pass_last
=
1227 sctx
->screen
->assume_no_z_fights
&& dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1232 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1234 struct si_context
*sctx
= (struct si_context
*)ctx
;
1235 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1236 struct si_state_dsa
*dsa
= state
;
1239 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1241 si_pm4_bind_state(sctx
, dsa
, dsa
);
1243 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1244 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1245 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1246 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1249 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1250 sctx
->do_update_shaders
= true;
1252 if (sctx
->screen
->dpbb_allowed
&& ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1253 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1254 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1255 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1257 if (sctx
->screen
->has_out_of_order_rast
&&
1258 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1259 sizeof(old_dsa
->order_invariance
))))
1260 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1263 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1265 struct si_context
*sctx
= (struct si_context
*)ctx
;
1267 if (sctx
->queued
.named
.dsa
== state
)
1268 si_bind_dsa_state(ctx
, sctx
->noop_dsa
);
1270 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1273 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1275 struct pipe_depth_stencil_alpha_state dsa
= {};
1277 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1280 /* DB RENDER STATE */
1282 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1284 struct si_context
*sctx
= (struct si_context
*)ctx
;
1286 /* Pipeline stat & streamout queries. */
1288 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1289 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1291 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1292 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1295 /* Occlusion queries. */
1296 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1297 sctx
->occlusion_queries_disabled
= !enable
;
1298 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1302 void si_set_occlusion_query_state(struct si_context
*sctx
, bool old_perfect_enable
)
1304 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1306 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1308 if (perfect_enable
!= old_perfect_enable
)
1309 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1312 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1314 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1316 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1317 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1319 st
->saved_ssbo_writable_mask
= 0;
1321 for (unsigned i
= 0; i
< 3; i
++) {
1322 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1323 (1u << si_get_shaderbuf_slot(i
)))
1324 st
->saved_ssbo_writable_mask
|= 1 << i
;
1328 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1330 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1332 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1333 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1335 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1336 st
->saved_ssbo_writable_mask
);
1337 for (unsigned i
= 0; i
< 3; ++i
)
1338 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1341 static void si_emit_db_render_state(struct si_context
*sctx
)
1343 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1344 unsigned db_shader_control
, db_render_control
, db_count_control
;
1345 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1347 /* DB_RENDER_CONTROL */
1348 if (sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
) {
1349 db_render_control
= S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1350 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1351 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1352 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1353 db_render_control
= S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1354 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1356 db_render_control
= S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1357 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1360 /* DB_COUNT_CONTROL (occlusion queries) */
1361 if (sctx
->num_occlusion_queries
> 0 && !sctx
->occlusion_queries_disabled
) {
1362 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1363 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1365 if (sctx
->chip_class
>= GFX7
) {
1366 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1368 /* Stoney doesn't increment occlusion query counters
1369 * if the sample rate is 16x. Use 8x sample rate instead.
1371 if (sctx
->family
== CHIP_STONEY
)
1372 log_sample_rate
= MIN2(log_sample_rate
, 3);
1374 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1375 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1376 S_028004_SAMPLE_RATE(log_sample_rate
) | S_028004_ZPASS_ENABLE(1) |
1377 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1379 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1380 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1383 /* Disable occlusion queries. */
1384 if (sctx
->chip_class
>= GFX7
) {
1385 db_count_control
= 0;
1387 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1391 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
, SI_TRACKED_DB_RENDER_CONTROL
,
1392 db_render_control
, db_count_control
);
1394 /* DB_RENDER_OVERRIDE2 */
1395 radeon_opt_set_context_reg(
1396 sctx
, R_028010_DB_RENDER_OVERRIDE2
, SI_TRACKED_DB_RENDER_OVERRIDE2
,
1397 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1398 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1399 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1401 db_shader_control
= sctx
->ps_db_shader_control
;
1403 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1404 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1405 db_shader_control
&= C_02880C_Z_ORDER
;
1406 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1409 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1410 if (!rs
->multisample_enable
)
1411 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1413 if (sctx
->screen
->info
.has_rbplus
&& !sctx
->screen
->info
.rbplus_allowed
)
1414 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1416 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
, SI_TRACKED_DB_SHADER_CONTROL
,
1419 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1420 sctx
->context_roll
= true;
1424 * format translation
1426 static uint32_t si_translate_colorformat(enum pipe_format format
)
1428 const struct util_format_description
*desc
= util_format_description(format
);
1430 return V_028C70_COLOR_INVALID
;
1432 #define HAS_SIZE(x, y, z, w) \
1433 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1434 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1436 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1437 return V_028C70_COLOR_10_11_11
;
1439 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1440 return V_028C70_COLOR_INVALID
;
1442 /* hw cannot support mixed formats (except depth/stencil, since
1443 * stencil is not written to). */
1444 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1445 return V_028C70_COLOR_INVALID
;
1447 switch (desc
->nr_channels
) {
1449 switch (desc
->channel
[0].size
) {
1451 return V_028C70_COLOR_8
;
1453 return V_028C70_COLOR_16
;
1455 return V_028C70_COLOR_32
;
1459 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1460 switch (desc
->channel
[0].size
) {
1462 return V_028C70_COLOR_8_8
;
1464 return V_028C70_COLOR_16_16
;
1466 return V_028C70_COLOR_32_32
;
1468 } else if (HAS_SIZE(8, 24, 0, 0)) {
1469 return V_028C70_COLOR_24_8
;
1470 } else if (HAS_SIZE(24, 8, 0, 0)) {
1471 return V_028C70_COLOR_8_24
;
1475 if (HAS_SIZE(5, 6, 5, 0)) {
1476 return V_028C70_COLOR_5_6_5
;
1477 } else if (HAS_SIZE(32, 8, 24, 0)) {
1478 return V_028C70_COLOR_X24_8_32_FLOAT
;
1482 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1483 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1484 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1485 switch (desc
->channel
[0].size
) {
1487 return V_028C70_COLOR_4_4_4_4
;
1489 return V_028C70_COLOR_8_8_8_8
;
1491 return V_028C70_COLOR_16_16_16_16
;
1493 return V_028C70_COLOR_32_32_32_32
;
1495 } else if (HAS_SIZE(5, 5, 5, 1)) {
1496 return V_028C70_COLOR_1_5_5_5
;
1497 } else if (HAS_SIZE(1, 5, 5, 5)) {
1498 return V_028C70_COLOR_5_5_5_1
;
1499 } else if (HAS_SIZE(10, 10, 10, 2)) {
1500 return V_028C70_COLOR_2_10_10_10
;
1504 return V_028C70_COLOR_INVALID
;
1507 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1509 if (SI_BIG_ENDIAN
) {
1510 switch (colorformat
) {
1511 /* 8-bit buffers. */
1512 case V_028C70_COLOR_8
:
1513 return V_028C70_ENDIAN_NONE
;
1515 /* 16-bit buffers. */
1516 case V_028C70_COLOR_5_6_5
:
1517 case V_028C70_COLOR_1_5_5_5
:
1518 case V_028C70_COLOR_4_4_4_4
:
1519 case V_028C70_COLOR_16
:
1520 case V_028C70_COLOR_8_8
:
1521 return V_028C70_ENDIAN_8IN16
;
1523 /* 32-bit buffers. */
1524 case V_028C70_COLOR_8_8_8_8
:
1525 case V_028C70_COLOR_2_10_10_10
:
1526 case V_028C70_COLOR_8_24
:
1527 case V_028C70_COLOR_24_8
:
1528 case V_028C70_COLOR_16_16
:
1529 return V_028C70_ENDIAN_8IN32
;
1531 /* 64-bit buffers. */
1532 case V_028C70_COLOR_16_16_16_16
:
1533 return V_028C70_ENDIAN_8IN16
;
1535 case V_028C70_COLOR_32_32
:
1536 return V_028C70_ENDIAN_8IN32
;
1538 /* 128-bit buffers. */
1539 case V_028C70_COLOR_32_32_32_32
:
1540 return V_028C70_ENDIAN_8IN32
;
1542 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1545 return V_028C70_ENDIAN_NONE
;
1549 static uint32_t si_translate_dbformat(enum pipe_format format
)
1552 case PIPE_FORMAT_Z16_UNORM
:
1553 return V_028040_Z_16
;
1554 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1555 case PIPE_FORMAT_X8Z24_UNORM
:
1556 case PIPE_FORMAT_Z24X8_UNORM
:
1557 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1558 return V_028040_Z_24
; /* deprecated on AMD GCN */
1559 case PIPE_FORMAT_Z32_FLOAT
:
1560 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1561 return V_028040_Z_32_FLOAT
;
1563 return V_028040_Z_INVALID
;
1568 * Texture translation
1571 static uint32_t si_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
1572 const struct util_format_description
*desc
,
1575 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1576 bool uniform
= true;
1579 assert(sscreen
->info
.chip_class
<= GFX9
);
1581 /* Colorspace (return non-RGB formats directly). */
1582 switch (desc
->colorspace
) {
1583 /* Depth stencil formats */
1584 case UTIL_FORMAT_COLORSPACE_ZS
:
1586 case PIPE_FORMAT_Z16_UNORM
:
1587 return V_008F14_IMG_DATA_FORMAT_16
;
1588 case PIPE_FORMAT_X24S8_UINT
:
1589 case PIPE_FORMAT_S8X24_UINT
:
1591 * Implemented as an 8_8_8_8 data format to fix texture
1592 * gathers in stencil sampling. This affects at least
1593 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1595 if (sscreen
->info
.chip_class
<= GFX8
)
1596 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1598 if (format
== PIPE_FORMAT_X24S8_UINT
)
1599 return V_008F14_IMG_DATA_FORMAT_8_24
;
1601 return V_008F14_IMG_DATA_FORMAT_24_8
;
1602 case PIPE_FORMAT_Z24X8_UNORM
:
1603 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1604 return V_008F14_IMG_DATA_FORMAT_8_24
;
1605 case PIPE_FORMAT_X8Z24_UNORM
:
1606 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1607 return V_008F14_IMG_DATA_FORMAT_24_8
;
1608 case PIPE_FORMAT_S8_UINT
:
1609 return V_008F14_IMG_DATA_FORMAT_8
;
1610 case PIPE_FORMAT_Z32_FLOAT
:
1611 return V_008F14_IMG_DATA_FORMAT_32
;
1612 case PIPE_FORMAT_X32_S8X24_UINT
:
1613 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1614 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1619 case UTIL_FORMAT_COLORSPACE_YUV
:
1620 goto out_unknown
; /* TODO */
1622 case UTIL_FORMAT_COLORSPACE_SRGB
:
1623 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1631 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1632 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1636 case PIPE_FORMAT_RGTC1_SNORM
:
1637 case PIPE_FORMAT_LATC1_SNORM
:
1638 case PIPE_FORMAT_RGTC1_UNORM
:
1639 case PIPE_FORMAT_LATC1_UNORM
:
1640 return V_008F14_IMG_DATA_FORMAT_BC4
;
1641 case PIPE_FORMAT_RGTC2_SNORM
:
1642 case PIPE_FORMAT_LATC2_SNORM
:
1643 case PIPE_FORMAT_RGTC2_UNORM
:
1644 case PIPE_FORMAT_LATC2_UNORM
:
1645 return V_008F14_IMG_DATA_FORMAT_BC5
;
1651 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1652 (sscreen
->info
.family
== CHIP_STONEY
|| sscreen
->info
.family
== CHIP_VEGA10
||
1653 sscreen
->info
.family
== CHIP_RAVEN
)) {
1655 case PIPE_FORMAT_ETC1_RGB8
:
1656 case PIPE_FORMAT_ETC2_RGB8
:
1657 case PIPE_FORMAT_ETC2_SRGB8
:
1658 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1659 case PIPE_FORMAT_ETC2_RGB8A1
:
1660 case PIPE_FORMAT_ETC2_SRGB8A1
:
1661 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1662 case PIPE_FORMAT_ETC2_RGBA8
:
1663 case PIPE_FORMAT_ETC2_SRGBA8
:
1664 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1665 case PIPE_FORMAT_ETC2_R11_UNORM
:
1666 case PIPE_FORMAT_ETC2_R11_SNORM
:
1667 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1668 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1669 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1670 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1676 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1677 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1681 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1682 case PIPE_FORMAT_BPTC_SRGBA
:
1683 return V_008F14_IMG_DATA_FORMAT_BC7
;
1684 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1685 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1686 return V_008F14_IMG_DATA_FORMAT_BC6
;
1692 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1694 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1695 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1696 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1697 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1698 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1699 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1705 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1706 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1710 case PIPE_FORMAT_DXT1_RGB
:
1711 case PIPE_FORMAT_DXT1_RGBA
:
1712 case PIPE_FORMAT_DXT1_SRGB
:
1713 case PIPE_FORMAT_DXT1_SRGBA
:
1714 return V_008F14_IMG_DATA_FORMAT_BC1
;
1715 case PIPE_FORMAT_DXT3_RGBA
:
1716 case PIPE_FORMAT_DXT3_SRGBA
:
1717 return V_008F14_IMG_DATA_FORMAT_BC2
;
1718 case PIPE_FORMAT_DXT5_RGBA
:
1719 case PIPE_FORMAT_DXT5_SRGBA
:
1720 return V_008F14_IMG_DATA_FORMAT_BC3
;
1726 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1727 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1728 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1729 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1732 /* R8G8Bx_SNORM - TODO CxV8U8 */
1734 /* hw cannot support mixed formats (except depth/stencil, since only
1736 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1739 /* See whether the components are of the same size. */
1740 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1741 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1744 /* Non-uniform formats. */
1746 switch (desc
->nr_channels
) {
1748 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 6 &&
1749 desc
->channel
[2].size
== 5) {
1750 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1754 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 5 &&
1755 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 1) {
1756 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1758 if (desc
->channel
[0].size
== 1 && desc
->channel
[1].size
== 5 &&
1759 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 5) {
1760 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1762 if (desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1763 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2) {
1764 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1771 if (first_non_void
< 0 || first_non_void
> 3)
1774 /* uniform formats */
1775 switch (desc
->channel
[first_non_void
].size
) {
1777 switch (desc
->nr_channels
) {
1778 #if 0 /* Not supported for render targets */
1780 return V_008F14_IMG_DATA_FORMAT_4_4
;
1783 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1787 switch (desc
->nr_channels
) {
1789 return V_008F14_IMG_DATA_FORMAT_8
;
1791 return V_008F14_IMG_DATA_FORMAT_8_8
;
1793 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1797 switch (desc
->nr_channels
) {
1799 return V_008F14_IMG_DATA_FORMAT_16
;
1801 return V_008F14_IMG_DATA_FORMAT_16_16
;
1803 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1807 switch (desc
->nr_channels
) {
1809 return V_008F14_IMG_DATA_FORMAT_32
;
1811 return V_008F14_IMG_DATA_FORMAT_32_32
;
1812 #if 0 /* Not supported for render targets */
1814 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1817 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1825 static unsigned si_tex_wrap(unsigned wrap
)
1829 case PIPE_TEX_WRAP_REPEAT
:
1830 return V_008F30_SQ_TEX_WRAP
;
1831 case PIPE_TEX_WRAP_CLAMP
:
1832 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1833 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1834 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1835 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1836 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1837 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1838 return V_008F30_SQ_TEX_MIRROR
;
1839 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1840 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1841 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1842 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1843 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1844 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1848 static unsigned si_tex_mipfilter(unsigned filter
)
1851 case PIPE_TEX_MIPFILTER_NEAREST
:
1852 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1853 case PIPE_TEX_MIPFILTER_LINEAR
:
1854 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1856 case PIPE_TEX_MIPFILTER_NONE
:
1857 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1861 static unsigned si_tex_compare(unsigned compare
)
1865 case PIPE_FUNC_NEVER
:
1866 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1867 case PIPE_FUNC_LESS
:
1868 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1869 case PIPE_FUNC_EQUAL
:
1870 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1871 case PIPE_FUNC_LEQUAL
:
1872 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1873 case PIPE_FUNC_GREATER
:
1874 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1875 case PIPE_FUNC_NOTEQUAL
:
1876 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1877 case PIPE_FUNC_GEQUAL
:
1878 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1879 case PIPE_FUNC_ALWAYS
:
1880 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1884 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
, unsigned view_target
,
1885 unsigned nr_samples
)
1887 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1889 if (view_target
== PIPE_TEXTURE_CUBE
|| view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1890 res_target
= view_target
;
1891 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1892 else if (res_target
== PIPE_TEXTURE_CUBE
|| res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1893 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1895 /* GFX9 allocates 1D textures as 2D. */
1896 if ((res_target
== PIPE_TEXTURE_1D
|| res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1897 sscreen
->info
.chip_class
== GFX9
&&
1898 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1899 if (res_target
== PIPE_TEXTURE_1D
)
1900 res_target
= PIPE_TEXTURE_2D
;
1902 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1905 switch (res_target
) {
1907 case PIPE_TEXTURE_1D
:
1908 return V_008F1C_SQ_RSRC_IMG_1D
;
1909 case PIPE_TEXTURE_1D_ARRAY
:
1910 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1911 case PIPE_TEXTURE_2D
:
1912 case PIPE_TEXTURE_RECT
:
1913 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
: V_008F1C_SQ_RSRC_IMG_2D
;
1914 case PIPE_TEXTURE_2D_ARRAY
:
1915 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1916 case PIPE_TEXTURE_3D
:
1917 return V_008F1C_SQ_RSRC_IMG_3D
;
1918 case PIPE_TEXTURE_CUBE
:
1919 case PIPE_TEXTURE_CUBE_ARRAY
:
1920 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1925 * Format support testing
1928 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1930 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1932 if (sscreen
->info
.chip_class
>= GFX10
) {
1933 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
1934 if (!fmt
->img_format
|| fmt
->buffers_only
)
1939 const struct util_format_description
*desc
= util_format_description(format
);
1943 return si_translate_texformat(screen
, format
, desc
,
1944 util_format_get_first_non_void_channel(format
)) != ~0U;
1947 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1948 const struct util_format_description
*desc
,
1953 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
1955 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1956 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1958 assert(first_non_void
>= 0);
1960 if (desc
->nr_channels
== 4 && desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1961 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2)
1962 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1964 /* See whether the components are of the same size. */
1965 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1966 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1967 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1970 switch (desc
->channel
[first_non_void
].size
) {
1972 switch (desc
->nr_channels
) {
1974 case 3: /* 3 loads */
1975 return V_008F0C_BUF_DATA_FORMAT_8
;
1977 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1979 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1983 switch (desc
->nr_channels
) {
1985 case 3: /* 3 loads */
1986 return V_008F0C_BUF_DATA_FORMAT_16
;
1988 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1990 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1994 switch (desc
->nr_channels
) {
1996 return V_008F0C_BUF_DATA_FORMAT_32
;
1998 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2000 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2002 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2006 /* Legacy double formats. */
2007 switch (desc
->nr_channels
) {
2008 case 1: /* 1 load */
2009 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2010 case 2: /* 1 load */
2011 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2012 case 3: /* 3 loads */
2013 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2014 case 4: /* 2 loads */
2015 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2020 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2023 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2024 const struct util_format_description
*desc
,
2027 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2029 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2030 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2032 assert(first_non_void
>= 0);
2034 switch (desc
->channel
[first_non_void
].type
) {
2035 case UTIL_FORMAT_TYPE_SIGNED
:
2036 case UTIL_FORMAT_TYPE_FIXED
:
2037 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2038 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2039 else if (desc
->channel
[first_non_void
].normalized
)
2040 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2042 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2044 case UTIL_FORMAT_TYPE_UNSIGNED
:
2045 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2046 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2047 else if (desc
->channel
[first_non_void
].normalized
)
2048 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2050 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2052 case UTIL_FORMAT_TYPE_FLOAT
:
2054 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2058 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2061 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2062 const struct util_format_description
*desc
;
2064 unsigned data_format
;
2066 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_VERTEX_BUFFER
)) ==
2069 desc
= util_format_description(format
);
2073 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2074 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2075 * for read-only access (with caveats surrounding bounds checks), but
2076 * obviously fails for write access which we have to implement for
2077 * shader images. Luckily, OpenGL doesn't expect this to be supported
2078 * anyway, and so the only impact is on PBO uploads / downloads, which
2079 * shouldn't be expected to be fast for GL_RGB anyway.
2081 if (desc
->block
.bits
== 3 * 8 || desc
->block
.bits
== 3 * 16) {
2082 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2083 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2089 if (sscreen
->info
.chip_class
>= GFX10
) {
2090 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2091 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2096 first_non_void
= util_format_get_first_non_void_channel(format
);
2097 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2098 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2104 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2106 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2107 si_translate_colorswap(format
, false) != ~0U;
2110 static bool si_is_zs_format_supported(enum pipe_format format
)
2112 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2115 static bool si_is_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2116 enum pipe_texture_target target
, unsigned sample_count
,
2117 unsigned storage_sample_count
, unsigned usage
)
2119 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2120 unsigned retval
= 0;
2122 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2123 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2127 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2130 if (sample_count
> 1) {
2131 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2134 /* Only power-of-two sample counts are supported. */
2135 if (!util_is_power_of_two_or_zero(sample_count
) ||
2136 !util_is_power_of_two_or_zero(storage_sample_count
))
2139 /* MSAA support without framebuffer attachments. */
2140 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2143 if (!sscreen
->info
.has_eqaa_surface_allocator
|| util_format_is_depth_or_stencil(format
)) {
2144 /* Color without EQAA or depth/stencil. */
2145 if (sample_count
> 8 || sample_count
!= storage_sample_count
)
2148 /* Color with EQAA. */
2149 if (sample_count
> 16 || storage_sample_count
> 8)
2154 if (usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
)) {
2155 if (target
== PIPE_BUFFER
) {
2156 retval
|= si_is_vertex_format_supported(
2157 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
));
2159 if (si_is_sampler_format_supported(screen
, format
))
2160 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
);
2164 if ((usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2165 PIPE_BIND_SHARED
| PIPE_BIND_BLENDABLE
)) &&
2166 si_is_colorbuffer_format_supported(format
)) {
2167 retval
|= usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2169 if (!util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
))
2170 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2173 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) && si_is_zs_format_supported(format
)) {
2174 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2177 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2178 retval
|= si_is_vertex_format_supported(screen
, format
, PIPE_BIND_VERTEX_BUFFER
);
2181 if ((usage
& PIPE_BIND_LINEAR
) && !util_format_is_compressed(format
) &&
2182 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2183 retval
|= PIPE_BIND_LINEAR
;
2185 return retval
== usage
;
2189 * framebuffer handling
2192 static void si_choose_spi_color_formats(struct si_surface
*surf
, unsigned format
, unsigned swap
,
2193 unsigned ntype
, bool is_depth
)
2195 /* Alpha is needed for alpha-to-coverage.
2196 * Blending may be with or without alpha.
2198 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2199 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2200 unsigned blend
= 0; /* supports blending, but may not export alpha */
2201 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2203 /* Choose the SPI color formats. These are required values for RB+.
2204 * Other chips have multiple choices, though they are not necessarily better.
2207 case V_028C70_COLOR_5_6_5
:
2208 case V_028C70_COLOR_1_5_5_5
:
2209 case V_028C70_COLOR_5_5_5_1
:
2210 case V_028C70_COLOR_4_4_4_4
:
2211 case V_028C70_COLOR_10_11_11
:
2212 case V_028C70_COLOR_11_11_10
:
2213 case V_028C70_COLOR_8
:
2214 case V_028C70_COLOR_8_8
:
2215 case V_028C70_COLOR_8_8_8_8
:
2216 case V_028C70_COLOR_10_10_10_2
:
2217 case V_028C70_COLOR_2_10_10_10
:
2218 if (ntype
== V_028C70_NUMBER_UINT
)
2219 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2220 else if (ntype
== V_028C70_NUMBER_SINT
)
2221 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2223 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2226 case V_028C70_COLOR_16
:
2227 case V_028C70_COLOR_16_16
:
2228 case V_028C70_COLOR_16_16_16_16
:
2229 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
) {
2230 /* UNORM16 and SNORM16 don't support blending */
2231 if (ntype
== V_028C70_NUMBER_UNORM
)
2232 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2234 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2236 /* Use 32 bits per channel for blending. */
2237 if (format
== V_028C70_COLOR_16
) {
2238 if (swap
== V_028C70_SWAP_STD
) { /* R */
2239 blend
= V_028714_SPI_SHADER_32_R
;
2240 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2241 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2242 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2245 } else if (format
== V_028C70_COLOR_16_16
) {
2246 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2247 blend
= V_028714_SPI_SHADER_32_GR
;
2248 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2249 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2250 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2253 } else /* 16_16_16_16 */
2254 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2255 } else if (ntype
== V_028C70_NUMBER_UINT
)
2256 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2257 else if (ntype
== V_028C70_NUMBER_SINT
)
2258 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2259 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2260 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2265 case V_028C70_COLOR_32
:
2266 if (swap
== V_028C70_SWAP_STD
) { /* R */
2267 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2268 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2269 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2270 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2275 case V_028C70_COLOR_32_32
:
2276 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2277 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2278 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2279 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2280 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2285 case V_028C70_COLOR_32_32_32_32
:
2286 case V_028C70_COLOR_8_24
:
2287 case V_028C70_COLOR_24_8
:
2288 case V_028C70_COLOR_X24_8_32_FLOAT
:
2289 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2297 /* The DB->CB copy needs 32_ABGR. */
2299 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2301 surf
->spi_shader_col_format
= normal
;
2302 surf
->spi_shader_col_format_alpha
= alpha
;
2303 surf
->spi_shader_col_format_blend
= blend
;
2304 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2307 static void si_initialize_color_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2309 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2310 unsigned color_info
, color_attrib
;
2311 unsigned format
, swap
, ntype
, endian
;
2312 const struct util_format_description
*desc
;
2314 unsigned blend_clamp
= 0, blend_bypass
= 0;
2316 desc
= util_format_description(surf
->base
.format
);
2317 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2318 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2322 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2323 ntype
= V_028C70_NUMBER_FLOAT
;
2325 ntype
= V_028C70_NUMBER_UNORM
;
2326 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2327 ntype
= V_028C70_NUMBER_SRGB
;
2328 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2329 if (desc
->channel
[firstchan
].pure_integer
) {
2330 ntype
= V_028C70_NUMBER_SINT
;
2332 assert(desc
->channel
[firstchan
].normalized
);
2333 ntype
= V_028C70_NUMBER_SNORM
;
2335 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2336 if (desc
->channel
[firstchan
].pure_integer
) {
2337 ntype
= V_028C70_NUMBER_UINT
;
2339 assert(desc
->channel
[firstchan
].normalized
);
2340 ntype
= V_028C70_NUMBER_UNORM
;
2345 format
= si_translate_colorformat(surf
->base
.format
);
2346 if (format
== V_028C70_COLOR_INVALID
) {
2347 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2349 assert(format
!= V_028C70_COLOR_INVALID
);
2350 swap
= si_translate_colorswap(surf
->base
.format
, false);
2351 endian
= si_colorformat_endian_swap(format
);
2353 /* blend clamp should be set for all NORM/SRGB types */
2354 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
2355 ntype
== V_028C70_NUMBER_SRGB
)
2358 /* set blend bypass according to docs if SINT/UINT or
2359 8/24 COLOR variants */
2360 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2361 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2362 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2367 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2368 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_8_8
||
2369 format
== V_028C70_COLOR_8_8_8_8
)
2370 surf
->color_is_int8
= true;
2371 else if (format
== V_028C70_COLOR_10_10_10_2
|| format
== V_028C70_COLOR_2_10_10_10
)
2372 surf
->color_is_int10
= true;
2376 S_028C70_FORMAT(format
) | S_028C70_COMP_SWAP(swap
) | S_028C70_BLEND_CLAMP(blend_clamp
) |
2377 S_028C70_BLEND_BYPASS(blend_bypass
) | S_028C70_SIMPLE_FLOAT(1) |
2378 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&& ntype
!= V_028C70_NUMBER_SNORM
&&
2379 ntype
!= V_028C70_NUMBER_SRGB
&& format
!= V_028C70_COLOR_8_24
&&
2380 format
!= V_028C70_COLOR_24_8
) |
2381 S_028C70_NUMBER_TYPE(ntype
) | S_028C70_ENDIAN(endian
);
2383 /* Intensity is implemented as Red, so treat it that way. */
2384 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2385 util_format_is_intensity(surf
->base
.format
));
2387 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2388 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2389 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2391 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) | S_028C74_NUM_FRAGMENTS(log_fragments
);
2393 if (tex
->surface
.fmask_offset
) {
2394 color_info
|= S_028C70_COMPRESSION(1);
2395 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2397 if (sctx
->chip_class
== GFX6
) {
2398 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2399 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2404 if (sctx
->chip_class
>= GFX10
) {
2405 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2407 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2408 64 for APU because all of our APUs to date use DIMMs which have
2409 a request granularity size of 64B while all other chips have a
2411 if (!sctx
->screen
->info
.has_dedicated_vram
)
2412 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2414 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2415 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
2416 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2417 S_028C78_INDEPENDENT_64B_BLOCKS(0) |
2418 S_028C78_INDEPENDENT_128B_BLOCKS(1);
2419 } else if (sctx
->chip_class
>= GFX8
) {
2420 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2421 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2423 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2424 64 for APU because all of our APUs to date use DIMMs which have
2425 a request granularity size of 64B while all other chips have a
2427 if (!sctx
->screen
->info
.has_dedicated_vram
)
2428 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2430 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2431 if (tex
->surface
.bpe
== 1)
2432 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2433 else if (tex
->surface
.bpe
== 2)
2434 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2437 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2438 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2439 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2442 /* This must be set for fast clear to work without FMASK. */
2443 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2444 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2445 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2448 /* GFX10 field has the same base shift as the GFX6 field */
2449 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2450 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2451 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2453 if (sctx
->chip_class
>= GFX10
) {
2454 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2456 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2457 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2458 S_028EE0_RESOURCE_LEVEL(1);
2459 } else if (sctx
->chip_class
== GFX9
) {
2460 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2461 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2462 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2465 if (sctx
->chip_class
>= GFX9
) {
2466 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2467 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2468 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2471 surf
->cb_color_view
= color_view
;
2472 surf
->cb_color_info
= color_info
;
2473 surf
->cb_color_attrib
= color_attrib
;
2475 /* Determine pixel shader export format */
2476 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2478 surf
->color_initialized
= true;
2481 static void si_init_depth_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2483 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2484 unsigned level
= surf
->base
.u
.tex
.level
;
2485 unsigned format
, stencil_format
;
2486 uint32_t z_info
, s_info
;
2488 format
= si_translate_dbformat(tex
->db_render_format
);
2489 stencil_format
= tex
->surface
.has_stencil
? V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2491 assert(format
!= V_028040_Z_INVALID
);
2492 if (format
== V_028040_Z_INVALID
)
2493 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2495 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2496 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2497 surf
->db_htile_data_base
= 0;
2498 surf
->db_htile_surface
= 0;
2500 if (sctx
->chip_class
>= GFX10
) {
2501 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2502 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2505 if (sctx
->chip_class
>= GFX9
) {
2506 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2507 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2508 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2509 z_info
= S_028038_FORMAT(format
) |
2510 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2511 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2512 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2513 s_info
= S_02803C_FORMAT(stencil_format
) |
2514 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2516 if (sctx
->chip_class
== GFX9
) {
2517 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2518 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2520 surf
->db_depth_view
|= S_028008_MIPID(level
);
2521 surf
->db_depth_size
=
2522 S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) | S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2524 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2525 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2527 if (tex
->tc_compatible_htile
) {
2528 unsigned max_zplanes
= 4;
2530 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&& tex
->buffer
.b
.b
.nr_samples
> 1)
2533 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
2535 if (sctx
->chip_class
>= GFX10
) {
2536 z_info
|= S_028040_ITERATE_FLUSH(1);
2537 s_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
2539 z_info
|= S_028038_ITERATE_FLUSH(1);
2540 s_info
|= S_02803C_ITERATE_FLUSH(1);
2544 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2545 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2546 * See that for explanation.
2548 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2550 /* Use all HTILE for depth if there's no stencil. */
2551 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2554 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2555 surf
->db_htile_surface
=
2556 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
);
2557 if (sctx
->chip_class
== GFX9
) {
2558 surf
->db_htile_surface
|= S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2563 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2565 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2567 surf
->db_depth_base
=
2568 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2569 surf
->db_stencil_base
=
2570 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2573 S_028040_FORMAT(format
) | S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2574 s_info
= S_028044_FORMAT(stencil_format
);
2575 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2577 if (sctx
->chip_class
>= GFX7
) {
2578 struct radeon_info
*info
= &sctx
->screen
->info
;
2579 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2580 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2581 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2582 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2583 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2584 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2586 surf
->db_depth_info
|= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2587 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2588 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2589 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2590 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2591 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2592 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2593 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2595 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2596 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2597 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2598 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2601 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2602 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2603 surf
->db_depth_slice
=
2604 S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
* levelinfo
->nblk_y
) / 64 - 1);
2606 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2607 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2609 if (tex
->surface
.has_stencil
) {
2610 /* Workaround: For a not yet understood reason, the
2611 * combination of MSAA, fast stencil clear and stencil
2612 * decompress messes with subsequent stencil buffer
2613 * uses. Problem was reproduced on Verde, Bonaire,
2614 * Tonga, and Carrizo.
2616 * Disabling EXPCLEAR works around the problem.
2618 * Check piglit's arb_texture_multisample-stencil-clear
2619 * test if you want to try changing this.
2621 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2622 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2623 } else if (!tex
->tc_compatible_htile
) {
2624 /* Use all of the htile_buffer for depth if there's no stencil.
2625 * This must not be set when TC-compatible HTILE is enabled
2628 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2631 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2632 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2634 if (tex
->tc_compatible_htile
) {
2635 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2637 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2638 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2639 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2640 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2641 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2643 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2648 surf
->db_z_info
= z_info
;
2649 surf
->db_stencil_info
= s_info
;
2651 surf
->depth_initialized
= true;
2654 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2656 if (sctx
->decompression_enabled
)
2659 if (sctx
->framebuffer
.state
.zsbuf
) {
2660 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2661 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2663 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2665 if (tex
->surface
.has_stencil
)
2666 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2669 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2670 while (compressed_cb_mask
) {
2671 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2672 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2673 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2675 if (tex
->surface
.fmask_offset
) {
2676 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2677 tex
->fmask_is_identity
= false;
2679 if (tex
->dcc_gather_statistics
)
2680 tex
->separate_dcc_dirty
= true;
2684 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2686 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2687 struct si_surface
*surf
= NULL
;
2688 struct si_texture
*tex
;
2690 if (!state
->cbufs
[i
])
2692 surf
= (struct si_surface
*)state
->cbufs
[i
];
2693 tex
= (struct si_texture
*)surf
->base
.texture
;
2695 p_atomic_dec(&tex
->framebuffers_bound
);
2699 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2700 const struct pipe_framebuffer_state
*state
)
2702 struct si_context
*sctx
= (struct si_context
*)ctx
;
2703 struct si_surface
*surf
= NULL
;
2704 struct si_texture
*tex
;
2705 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2706 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2707 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2708 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2709 bool old_has_stencil
=
2711 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2712 bool unbound
= false;
2715 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2716 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2717 * We could implement the full workaround here, but it's a useless case.
2719 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2720 unreachable("the framebuffer shouldn't have zero area");
2724 si_update_fb_dirtiness_after_rendering(sctx
);
2726 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2727 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2730 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2731 if (tex
->dcc_gather_statistics
)
2732 vi_separate_dcc_stop_query(sctx
, tex
);
2735 /* Disable DCC if the formats are incompatible. */
2736 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2737 if (!state
->cbufs
[i
])
2740 surf
= (struct si_surface
*)state
->cbufs
[i
];
2741 tex
= (struct si_texture
*)surf
->base
.texture
;
2743 if (!surf
->dcc_incompatible
)
2746 /* Since the DCC decompression calls back into set_framebuffer-
2747 * _state, we need to unbind the framebuffer, so that
2748 * vi_separate_dcc_stop_query isn't called twice with the same
2752 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2756 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2757 if (!si_texture_disable_dcc(sctx
, tex
))
2758 si_decompress_dcc(sctx
, tex
);
2760 surf
->dcc_incompatible
= false;
2763 /* Only flush TC when changing the framebuffer state, because
2764 * the only client not using TC that can change textures is
2767 * Wait for compute shaders because of possible transitions:
2768 * - FB write -> shader read
2769 * - shader write -> FB read
2771 * DB caches are flushed on demand (using si_decompress_textures).
2773 * When MSAA is enabled, CB and TC caches are flushed on demand
2774 * (after FMASK decompression). Shader write -> FB read transitions
2775 * cannot happen for MSAA textures, because MSAA shader images are
2778 * Only flush and wait for CB if there is actually a bound color buffer.
2780 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2781 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2782 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2783 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2786 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2788 /* u_blitter doesn't invoke depth decompression when it does multiple
2789 * blits in a row, but the only case when it matters for DB is when
2790 * doing generate_mipmap. So here we flush DB manually between
2791 * individual generate_mipmap blits.
2792 * Note that lower mipmap levels aren't compressed.
2794 if (sctx
->generate_mipmap_for_depth
) {
2795 si_make_DB_shader_coherent(sctx
, 1, false, sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2796 } else if (sctx
->chip_class
== GFX9
) {
2797 /* It appears that DB metadata "leaks" in a sequence of:
2799 * - DCC decompress for shader image writes (with DB disabled)
2800 * - render with DEPTH_BEFORE_SHADER=1
2801 * Flushing DB metadata works around the problem.
2803 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2806 /* Take the maximum of the old and new count. If the new count is lower,
2807 * dirtying is needed to disable the unbound colorbuffers.
2809 sctx
->framebuffer
.dirty_cbufs
|=
2810 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2811 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2813 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2814 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2816 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2817 sctx
->framebuffer
.spi_shader_col_format
= 0;
2818 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2819 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2820 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2821 sctx
->framebuffer
.color_is_int8
= 0;
2822 sctx
->framebuffer
.color_is_int10
= 0;
2824 sctx
->framebuffer
.compressed_cb_mask
= 0;
2825 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2826 sctx
->framebuffer
.displayable_dcc_cb_mask
= 0;
2827 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2828 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2829 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2830 sctx
->framebuffer
.any_dst_linear
= false;
2831 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2832 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2833 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2834 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2836 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2837 if (!state
->cbufs
[i
])
2840 surf
= (struct si_surface
*)state
->cbufs
[i
];
2841 tex
= (struct si_texture
*)surf
->base
.texture
;
2843 if (!surf
->color_initialized
) {
2844 si_initialize_color_surface(sctx
, surf
);
2847 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2848 sctx
->framebuffer
.spi_shader_col_format
|= surf
->spi_shader_col_format
<< (i
* 4);
2849 sctx
->framebuffer
.spi_shader_col_format_alpha
|= surf
->spi_shader_col_format_alpha
<< (i
* 4);
2850 sctx
->framebuffer
.spi_shader_col_format_blend
|= surf
->spi_shader_col_format_blend
<< (i
* 4);
2851 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|= surf
->spi_shader_col_format_blend_alpha
2854 if (surf
->color_is_int8
)
2855 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2856 if (surf
->color_is_int10
)
2857 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2859 if (tex
->surface
.fmask_offset
)
2860 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2862 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2864 if (tex
->surface
.dcc_offset
)
2865 sctx
->framebuffer
.displayable_dcc_cb_mask
|= 1 << i
;
2867 /* Don't update nr_color_samples for non-AA buffers.
2868 * (e.g. destination of MSAA resolve)
2870 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2871 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2872 sctx
->framebuffer
.nr_color_samples
=
2873 MIN2(sctx
->framebuffer
.nr_color_samples
, tex
->buffer
.b
.b
.nr_storage_samples
);
2874 sctx
->framebuffer
.nr_color_samples
= MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2877 if (tex
->surface
.is_linear
)
2878 sctx
->framebuffer
.any_dst_linear
= true;
2880 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
2881 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2883 if (sctx
->chip_class
>= GFX9
&& !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
2884 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
2887 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2889 p_atomic_inc(&tex
->framebuffers_bound
);
2891 if (tex
->dcc_gather_statistics
) {
2892 /* Dirty tracking must be enabled for DCC usage analysis. */
2893 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2894 vi_separate_dcc_start_query(sctx
, tex
);
2897 /* Update the minimum but don't keep 0. */
2898 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2899 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2900 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
2903 /* For optimal DCC performance. */
2904 if (sctx
->chip_class
>= GFX10
)
2905 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2907 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2909 struct si_texture
*zstex
= NULL
;
2912 surf
= (struct si_surface
*)state
->zsbuf
;
2913 zstex
= (struct si_texture
*)surf
->base
.texture
;
2915 if (!surf
->depth_initialized
) {
2916 si_init_depth_surface(sctx
, surf
);
2919 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
, PIPE_MASK_ZS
))
2920 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2922 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2924 /* Update the minimum but don't keep 0. */
2925 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2926 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2927 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
2930 si_update_ps_colorbuf0_slot(sctx
);
2931 si_update_poly_offset_state(sctx
);
2932 si_update_ngg_small_prim_precision(sctx
);
2933 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2934 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2936 if (sctx
->screen
->dpbb_allowed
)
2937 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2939 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2940 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2942 if (sctx
->screen
->has_out_of_order_rast
&&
2943 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2944 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2945 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2946 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2948 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2949 struct pipe_constant_buffer constbuf
= {0};
2951 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2952 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2954 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2956 /* Set sample locations as fragment shader constants. */
2957 switch (sctx
->framebuffer
.nr_samples
) {
2959 constbuf
.buffer_offset
= 0;
2962 constbuf
.buffer_offset
=
2963 (ubyte
*)sctx
->sample_positions
.x2
- (ubyte
*)sctx
->sample_positions
.x1
;
2966 constbuf
.buffer_offset
=
2967 (ubyte
*)sctx
->sample_positions
.x4
- (ubyte
*)sctx
->sample_positions
.x1
;
2970 constbuf
.buffer_offset
=
2971 (ubyte
*)sctx
->sample_positions
.x8
- (ubyte
*)sctx
->sample_positions
.x1
;
2974 constbuf
.buffer_offset
=
2975 (ubyte
*)sctx
->sample_positions
.x16
- (ubyte
*)sctx
->sample_positions
.x1
;
2978 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx
->framebuffer
.nr_samples
);
2981 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2982 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2984 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2987 sctx
->do_update_shaders
= true;
2989 if (!sctx
->decompression_enabled
) {
2990 /* Prevent textures decompression when the framebuffer state
2991 * changes come from the decompression passes themselves.
2993 sctx
->need_check_render_feedback
= true;
2997 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2999 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3000 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
3001 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
3002 struct si_texture
*tex
= NULL
;
3003 struct si_surface
*cb
= NULL
;
3004 unsigned cb_color_info
= 0;
3007 for (i
= 0; i
< nr_cbufs
; i
++) {
3008 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3009 unsigned cb_color_attrib
;
3011 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3014 cb
= (struct si_surface
*)state
->cbufs
[i
];
3016 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3017 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3021 tex
= (struct si_texture
*)cb
->base
.texture
;
3022 radeon_add_to_buffer_list(
3023 sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3024 tex
->buffer
.b
.b
.nr_samples
> 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA
: RADEON_PRIO_COLOR_BUFFER
);
3026 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3027 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3028 RADEON_PRIO_SEPARATE_META
);
3031 if (tex
->dcc_separate_buffer
)
3032 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->dcc_separate_buffer
,
3033 RADEON_USAGE_READWRITE
, RADEON_PRIO_SEPARATE_META
);
3035 /* Compute mutable surface parameters. */
3036 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3038 cb_color_cmask
= tex
->cmask_base_address_reg
;
3040 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3041 cb_color_attrib
= cb
->cb_color_attrib
;
3043 if (cb
->base
.u
.tex
.level
> 0)
3044 cb_color_info
&= C_028C70_FAST_CLEAR
;
3046 if (tex
->surface
.fmask_offset
) {
3047 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
) >> 8;
3048 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3052 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3053 bool is_msaa_resolve_dst
= state
->cbufs
[0] && state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3054 state
->cbufs
[1] == &cb
->base
&&
3055 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3057 if (!is_msaa_resolve_dst
)
3058 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3061 ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
) >>
3064 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
3065 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
3066 cb_dcc_base
|= dcc_tile_swizzle
;
3069 if (sctx
->chip_class
>= GFX10
) {
3070 unsigned cb_color_attrib3
;
3072 /* Set mutable surface parameters. */
3073 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3074 cb_color_base
|= tex
->surface
.tile_swizzle
;
3075 if (!tex
->surface
.fmask_offset
)
3076 cb_color_fmask
= cb_color_base
;
3077 if (cb
->base
.u
.tex
.level
> 0)
3078 cb_color_cmask
= cb_color_base
;
3080 cb_color_attrib3
= cb
->cb_color_attrib3
|
3081 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3082 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3083 S_028EE0_CMASK_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3084 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
3086 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
3087 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3088 radeon_emit(cs
, 0); /* hole */
3089 radeon_emit(cs
, 0); /* hole */
3090 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3091 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3092 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3093 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3094 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3095 radeon_emit(cs
, 0); /* hole */
3096 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3097 radeon_emit(cs
, 0); /* hole */
3098 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3099 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3100 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3102 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4, cb_color_base
>> 32);
3103 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
3104 cb_color_cmask
>> 32);
3105 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
3106 cb_color_fmask
>> 32);
3107 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4, cb_dcc_base
>> 32);
3108 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4, cb
->cb_color_attrib2
);
3109 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4, cb_color_attrib3
);
3110 } else if (sctx
->chip_class
== GFX9
) {
3111 struct gfx9_surf_meta_flags meta
;
3113 if (tex
->surface
.dcc_offset
)
3114 meta
= tex
->surface
.u
.gfx9
.dcc
;
3116 meta
= tex
->surface
.u
.gfx9
.cmask
;
3118 /* Set mutable surface parameters. */
3119 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3120 cb_color_base
|= tex
->surface
.tile_swizzle
;
3121 if (!tex
->surface
.fmask_offset
)
3122 cb_color_fmask
= cb_color_base
;
3123 if (cb
->base
.u
.tex
.level
> 0)
3124 cb_color_cmask
= cb_color_base
;
3125 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3126 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3127 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3128 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3130 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3131 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3132 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3133 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3134 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3135 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3136 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3137 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3138 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3139 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3140 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3141 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3142 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3143 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3144 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3145 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3147 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3148 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3150 /* Compute mutable surface parameters (GFX6-GFX8). */
3151 const struct legacy_surf_level
*level_info
=
3152 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3153 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3154 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3156 cb_color_base
+= level_info
->offset
>> 8;
3157 /* Only macrotiled modes can set tile swizzle. */
3158 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3159 cb_color_base
|= tex
->surface
.tile_swizzle
;
3161 if (!tex
->surface
.fmask_offset
)
3162 cb_color_fmask
= cb_color_base
;
3163 if (cb
->base
.u
.tex
.level
> 0)
3164 cb_color_cmask
= cb_color_base
;
3166 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3168 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3169 slice_tile_max
= level_info
->nblk_x
* level_info
->nblk_y
/ 64 - 1;
3170 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3172 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3173 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3174 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3176 if (tex
->surface
.fmask_offset
) {
3177 if (sctx
->chip_class
>= GFX7
)
3179 S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3181 S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3182 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3184 /* This must be set for fast clear to work without FMASK. */
3185 if (sctx
->chip_class
>= GFX7
)
3186 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3187 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3188 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3191 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3192 sctx
->chip_class
>= GFX8
? 14 : 13);
3193 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3194 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3195 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3196 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3197 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3198 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3199 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3200 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3201 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3202 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3203 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3204 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3205 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3207 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3208 radeon_emit(cs
, cb_dcc_base
);
3212 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3213 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3216 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3217 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3218 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3220 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3221 zb
->base
.texture
->nr_samples
> 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3222 : RADEON_PRIO_DEPTH_BUFFER
);
3224 if (sctx
->chip_class
>= GFX10
) {
3225 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3226 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3228 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3229 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3230 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3231 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3232 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3233 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3234 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3235 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3236 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3238 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 5);
3239 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3240 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3241 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3242 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3243 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3244 } else if (sctx
->chip_class
== GFX9
) {
3245 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3246 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3248 S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3249 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3251 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3252 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3253 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3254 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3255 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3256 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3257 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3258 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3259 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3260 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3261 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3263 S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3265 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3266 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3267 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3269 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3271 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3272 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3273 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3274 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3275 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3276 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3277 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3278 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3279 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3280 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3281 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3284 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3285 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3286 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3288 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3289 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3290 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3291 if (sctx
->chip_class
== GFX9
)
3292 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3294 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3296 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3297 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3300 /* Framebuffer dimensions. */
3301 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3302 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3303 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3305 if (sctx
->screen
->dfsm_allowed
) {
3306 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3307 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3310 sctx
->framebuffer
.dirty_cbufs
= 0;
3311 sctx
->framebuffer
.dirty_zsbuf
= false;
3314 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3316 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3317 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3318 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3319 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3321 /* Smoothing (only possible with nr_samples == 1) uses the same
3322 * sample locations as the MSAA it simulates.
3324 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3325 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3327 /* On Polaris, the small primitive filter uses the sample locations
3328 * even when MSAA is off, so we need to make sure they're set to 0.
3330 * GFX10 uses sample locations unconditionally, so they always need
3333 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
|| sctx
->chip_class
>= GFX10
) &&
3334 nr_samples
!= sctx
->sample_locs_num_samples
) {
3335 sctx
->sample_locs_num_samples
= nr_samples
;
3336 si_emit_sample_locations(cs
, nr_samples
);
3339 if (sctx
->family
>= CHIP_POLARIS10
) {
3340 unsigned small_prim_filter_cntl
=
3341 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3343 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3345 /* The alternative of setting sample locations to 0 would
3346 * require a DB flush to avoid Z errors, see
3347 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3349 if (has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1 && !rs
->multisample_enable
)
3350 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3352 radeon_opt_set_context_reg(sctx
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3353 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
, small_prim_filter_cntl
);
3356 /* The exclusion bits can be set to improve rasterization efficiency
3357 * if no sample lies on the pixel boundary (-8 sample offset).
3359 bool exclusion
= sctx
->chip_class
>= GFX7
&& (!rs
->multisample_enable
|| nr_samples
!= 16);
3360 radeon_opt_set_context_reg(
3361 sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3362 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3365 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3367 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3368 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3370 if (!sctx
->screen
->has_out_of_order_rast
)
3373 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3375 colormask
&= blend
->cb_target_enabled_4bit
;
3377 /* Conservative: No logic op. */
3378 if (colormask
&& blend
->logicop_enable
)
3381 struct si_dsa_order_invariance dsa_order_invariant
= {.zs
= true,
3383 .pass_last
= false};
3385 if (sctx
->framebuffer
.state
.zsbuf
) {
3386 struct si_texture
*zstex
= (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3387 bool has_stencil
= zstex
->surface
.has_stencil
;
3388 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3389 if (!dsa_order_invariant
.zs
)
3392 /* The set of PS invocations is always order invariant,
3393 * except when early Z/S tests are requested. */
3394 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.writes_memory
&&
3395 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3396 !dsa_order_invariant
.pass_set
)
3399 if (sctx
->num_perfect_occlusion_queries
!= 0 && !dsa_order_invariant
.pass_set
)
3406 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3409 /* Only commutative blending. */
3410 if (blendmask
& ~blend
->commutative_4bit
)
3413 if (!dsa_order_invariant
.pass_set
)
3417 if (colormask
& ~blendmask
) {
3418 if (!dsa_order_invariant
.pass_last
)
3425 static void si_emit_msaa_config(struct si_context
*sctx
)
3427 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3428 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3429 /* 33% faster rendering to linear color buffers */
3430 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3431 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3432 unsigned sc_mode_cntl_1
=
3433 S_028A4C_WALK_SIZE(dst_is_linear
) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3434 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3435 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3436 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3438 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3439 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3440 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3441 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) |
3442 S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3443 unsigned coverage_samples
, color_samples
, z_samples
;
3444 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3446 /* S: Coverage samples (up to 16x):
3447 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3448 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3450 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3451 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3452 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3453 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3454 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3457 * F: Color samples (up to 8x, must be <= coverage samples):
3458 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3459 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3461 * Can be anything between coverage and color samples:
3462 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3463 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3464 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3465 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3466 * # All are currently set the same as coverage samples.
3468 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3469 * flag for undefined color samples. A shader-based resolve must handle unknowns
3470 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3471 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3472 * useful. The CB resolve always drops unknowns.
3474 * Sensible AA configurations:
3475 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3476 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3477 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3478 * EQAA 8s 8z 8f = 8x MSAA
3479 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3480 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3481 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3482 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3483 * EQAA 4s 4z 4f = 4x MSAA
3484 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3485 * EQAA 2s 2z 2f = 2x MSAA
3487 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3488 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3489 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3491 if (sctx
->framebuffer
.state
.zsbuf
) {
3492 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3493 z_samples
= MAX2(1, z_samples
);
3495 z_samples
= coverage_samples
;
3497 } else if (sctx
->smoothing_enabled
) {
3498 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3500 coverage_samples
= color_samples
= z_samples
= 1;
3503 /* Required by OpenGL line rasterization.
3505 * TODO: We should also enable perpendicular endcaps for AA lines,
3506 * but that requires implementing line stippling in the pixel
3507 * shader. SC can only do line stippling with axis-aligned
3510 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3511 unsigned sc_aa_config
= 0;
3513 if (coverage_samples
> 1) {
3514 /* distance from the pixel center, indexed by log2(nr_samples) */
3515 static unsigned max_dist
[] = {
3522 unsigned log_samples
= util_logbase2(coverage_samples
);
3523 unsigned log_z_samples
= util_logbase2(z_samples
);
3524 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3525 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3527 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3528 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3529 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3530 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3532 if (sctx
->framebuffer
.nr_samples
> 1) {
3533 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3534 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3535 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3536 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3537 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3538 } else if (sctx
->smoothing_enabled
) {
3539 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3543 unsigned initial_cdw
= cs
->current
.cdw
;
3545 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3546 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
, SI_TRACKED_PA_SC_LINE_CNTL
,
3547 sc_line_cntl
, sc_aa_config
);
3548 /* R_028804_DB_EQAA */
3549 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
, db_eqaa
);
3550 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3551 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
, SI_TRACKED_PA_SC_MODE_CNTL_1
,
3554 if (initial_cdw
!= cs
->current
.cdw
) {
3555 sctx
->context_roll
= true;
3557 /* GFX9: Flush DFSM when the AA mode changes. */
3558 if (sctx
->screen
->dfsm_allowed
) {
3559 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3560 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3565 void si_update_ps_iter_samples(struct si_context
*sctx
)
3567 if (sctx
->framebuffer
.nr_samples
> 1)
3568 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3569 if (sctx
->screen
->dpbb_allowed
)
3570 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3573 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3575 struct si_context
*sctx
= (struct si_context
*)ctx
;
3577 /* The hardware can only do sample shading with 2^n samples. */
3578 min_samples
= util_next_power_of_two(min_samples
);
3580 if (sctx
->ps_iter_samples
== min_samples
)
3583 sctx
->ps_iter_samples
= min_samples
;
3584 sctx
->do_update_shaders
= true;
3586 si_update_ps_iter_samples(sctx
);
3594 * Build the sampler view descriptor for a buffer texture.
3595 * @param state 256-bit descriptor; only the high 128 bits are filled in
3597 void si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3598 enum pipe_format format
, unsigned offset
, unsigned size
,
3601 const struct util_format_description
*desc
;
3603 unsigned num_records
;
3605 desc
= util_format_description(format
);
3606 stride
= desc
->block
.bits
/ 8;
3608 num_records
= size
/ stride
;
3609 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3611 /* The NUM_RECORDS field has a different meaning depending on the chip,
3612 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3615 * - If STRIDE == 0, it's in byte units.
3616 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3619 * - For SMEM and STRIDE == 0, it's in byte units.
3620 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3621 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3622 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3623 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3624 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3625 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3626 * That way the same descriptor can be used by both SMEM and VMEM.
3629 * - For SMEM and STRIDE == 0, it's in byte units.
3630 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3631 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3632 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3634 if (screen
->info
.chip_class
== GFX8
)
3635 num_records
*= stride
;
3638 state
[5] = S_008F04_STRIDE(stride
);
3639 state
[6] = num_records
;
3640 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3641 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3642 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3643 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3645 if (screen
->info
.chip_class
>= GFX10
) {
3646 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3648 /* OOB_SELECT chooses the out-of-bounds check:
3649 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3650 * - 1: index >= NUM_RECORDS
3651 * - 2: NUM_RECORDS == 0
3652 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3653 * else: swizzle_address >= NUM_RECORDS
3655 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3656 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET
) |
3657 S_008F0C_RESOURCE_LEVEL(1);
3660 unsigned num_format
, data_format
;
3662 first_non_void
= util_format_get_first_non_void_channel(format
);
3663 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3664 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3666 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
3670 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3672 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3674 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3675 /* For the pre-defined border color values (white, opaque
3676 * black, transparent black), the only thing that matters is
3677 * that the alpha channel winds up in the correct place
3678 * (because the RGB channels are all the same) so either of
3679 * these enumerations will work.
3681 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3682 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3684 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3685 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3686 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3687 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3689 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3690 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3691 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3692 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3693 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3700 * Build the sampler view descriptor for a texture.
3702 static void gfx10_make_texture_descriptor(
3703 struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
, enum pipe_texture_target target
,
3704 enum pipe_format pipe_format
, const unsigned char state_swizzle
[4], unsigned first_level
,
3705 unsigned last_level
, unsigned first_layer
, unsigned last_layer
, unsigned width
, unsigned height
,
3706 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3708 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3709 const struct util_format_description
*desc
;
3710 unsigned img_format
;
3711 unsigned char swizzle
[4];
3715 desc
= util_format_description(pipe_format
);
3716 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3718 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3719 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3720 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3721 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3722 bool is_stencil
= false;
3724 switch (pipe_format
) {
3725 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3726 case PIPE_FORMAT_X32_S8X24_UINT
:
3727 case PIPE_FORMAT_X8Z24_UNORM
:
3728 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3731 case PIPE_FORMAT_X24S8_UINT
:
3733 * X24S8 is implemented as an 8_8_8_8 data format, to
3734 * fix texture gathers. This affects at least
3735 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3737 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3741 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3742 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3745 if (tex
->upgraded_depth
&& !is_stencil
) {
3746 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3747 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3750 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3753 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3754 /* For the purpose of shader images, treat cube maps as 2D
3757 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3759 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3762 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3764 depth
= res
->array_size
;
3765 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3766 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3767 depth
= res
->array_size
;
3768 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3769 depth
= res
->array_size
/ 6;
3772 state
[1] = S_00A004_FORMAT(img_format
) | S_00A004_WIDTH_LO(width
- 1);
3773 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3774 S_00A008_RESOURCE_LEVEL(1);
3776 S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3777 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3778 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3779 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3780 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ? 0 : first_level
) |
3781 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
) : last_level
) |
3782 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) | S_00A00C_TYPE(type
);
3783 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3784 * to know the total number of layers.
3787 S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
) ? depth
- 1 : last_layer
) |
3788 S_00A010_BASE_ARRAY(first_layer
);
3789 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3790 S_00A014_MAX_MIP(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
)
3791 : tex
->buffer
.b
.b
.last_level
) |
3792 S_00A014_PERF_MOD(4);
3796 if (tex
->surface
.dcc_offset
) {
3797 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3798 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B
) |
3799 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
3802 /* Initialize the sampler view for FMASK. */
3803 if (tex
->surface
.fmask_offset
) {
3806 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
3808 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3809 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3811 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
3814 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
3817 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
3820 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
3823 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
3826 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
3829 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
3832 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
3835 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
3838 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
3841 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
3844 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
3847 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
3850 unreachable("invalid nr_samples");
3853 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3854 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) | S_00A004_FORMAT(format
) |
3855 S_00A004_WIDTH_LO(width
- 1);
3856 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3857 S_00A008_RESOURCE_LEVEL(1);
3859 S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3860 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3861 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3862 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3863 fmask_state
[4] = S_00A010_DEPTH(last_layer
) | S_00A010_BASE_ARRAY(first_layer
);
3865 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
);
3871 * Build the sampler view descriptor for a texture (SI-GFX9).
3873 static void si_make_texture_descriptor(struct si_screen
*screen
, struct si_texture
*tex
,
3874 bool sampler
, enum pipe_texture_target target
,
3875 enum pipe_format pipe_format
,
3876 const unsigned char state_swizzle
[4], unsigned first_level
,
3877 unsigned last_level
, unsigned first_layer
,
3878 unsigned last_layer
, unsigned width
, unsigned height
,
3879 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3881 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3882 const struct util_format_description
*desc
;
3883 unsigned char swizzle
[4];
3885 unsigned num_format
, data_format
, type
, num_samples
;
3888 desc
= util_format_description(pipe_format
);
3890 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
? MAX2(1, res
->nr_samples
)
3891 : MAX2(1, res
->nr_storage_samples
);
3893 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3894 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3895 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3896 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3898 switch (pipe_format
) {
3899 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3900 case PIPE_FORMAT_X32_S8X24_UINT
:
3901 case PIPE_FORMAT_X8Z24_UNORM
:
3902 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3904 case PIPE_FORMAT_X24S8_UINT
:
3906 * X24S8 is implemented as an 8_8_8_8 data format, to
3907 * fix texture gathers. This affects at least
3908 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3910 if (screen
->info
.chip_class
<= GFX8
)
3911 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3913 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3916 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3919 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3922 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3924 switch (pipe_format
) {
3925 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3926 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3929 if (first_non_void
< 0) {
3930 if (util_format_is_compressed(pipe_format
)) {
3931 switch (pipe_format
) {
3932 case PIPE_FORMAT_DXT1_SRGB
:
3933 case PIPE_FORMAT_DXT1_SRGBA
:
3934 case PIPE_FORMAT_DXT3_SRGBA
:
3935 case PIPE_FORMAT_DXT5_SRGBA
:
3936 case PIPE_FORMAT_BPTC_SRGBA
:
3937 case PIPE_FORMAT_ETC2_SRGB8
:
3938 case PIPE_FORMAT_ETC2_SRGB8A1
:
3939 case PIPE_FORMAT_ETC2_SRGBA8
:
3940 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3942 case PIPE_FORMAT_RGTC1_SNORM
:
3943 case PIPE_FORMAT_LATC1_SNORM
:
3944 case PIPE_FORMAT_RGTC2_SNORM
:
3945 case PIPE_FORMAT_LATC2_SNORM
:
3946 case PIPE_FORMAT_ETC2_R11_SNORM
:
3947 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3948 /* implies float, so use SNORM/UNORM to determine
3949 whether data is signed or not */
3950 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3951 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3954 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3957 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3958 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3960 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3962 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3963 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3965 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3967 switch (desc
->channel
[first_non_void
].type
) {
3968 case UTIL_FORMAT_TYPE_FLOAT
:
3969 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3971 case UTIL_FORMAT_TYPE_SIGNED
:
3972 if (desc
->channel
[first_non_void
].normalized
)
3973 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3974 else if (desc
->channel
[first_non_void
].pure_integer
)
3975 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3977 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3979 case UTIL_FORMAT_TYPE_UNSIGNED
:
3980 if (desc
->channel
[first_non_void
].normalized
)
3981 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3982 else if (desc
->channel
[first_non_void
].pure_integer
)
3983 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3985 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3990 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3991 if (data_format
== ~0) {
3995 /* S8 with Z32 HTILE needs a special format. */
3996 if (screen
->info
.chip_class
== GFX9
&& pipe_format
== PIPE_FORMAT_S8_UINT
&&
3997 tex
->tc_compatible_htile
)
3998 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
4000 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
4001 (screen
->info
.chip_class
<= GFX8
&& res
->target
== PIPE_TEXTURE_3D
))) {
4002 /* For the purpose of shader images, treat cube maps and 3D
4003 * textures as 2D arrays. For 3D textures, the address
4004 * calculations for mipmaps are different, so we rely on the
4005 * caller to effectively disable mipmaps.
4007 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
4009 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
4011 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
4014 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
4016 depth
= res
->array_size
;
4017 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
4018 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
4019 depth
= res
->array_size
;
4020 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
4021 depth
= res
->array_size
/ 6;
4024 state
[1] = (S_008F14_DATA_FORMAT(data_format
) | S_008F14_NUM_FORMAT(num_format
));
4025 state
[2] = (S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1) | S_008F18_PERF_MOD(4));
4026 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4027 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4028 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4029 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4030 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
4031 S_008F1C_LAST_LEVEL(num_samples
> 1 ? util_logbase2(num_samples
) : last_level
) |
4032 S_008F1C_TYPE(type
));
4034 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4038 if (screen
->info
.chip_class
== GFX9
) {
4039 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4041 /* Depth is the the last accessible layer on Gfx9.
4042 * The hw doesn't need to know the total number of layers.
4044 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4045 state
[4] |= S_008F20_DEPTH(depth
- 1);
4047 state
[4] |= S_008F20_DEPTH(last_layer
);
4049 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4050 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ? util_logbase2(num_samples
)
4051 : tex
->buffer
.b
.b
.last_level
);
4053 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4054 state
[4] |= S_008F20_DEPTH(depth
- 1);
4055 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4058 if (tex
->surface
.dcc_offset
) {
4059 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4061 /* The last dword is unused by hw. The shader uses it to clear
4062 * bits in the first dword of sampler state.
4064 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4065 if (first_level
== last_level
)
4066 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4068 state
[7] = 0xffffffff;
4072 /* Initialize the sampler view for FMASK. */
4073 if (tex
->surface
.fmask_offset
) {
4074 uint32_t data_format
, num_format
;
4076 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4078 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4079 if (screen
->info
.chip_class
== GFX9
) {
4080 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4081 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4083 num_format
= V_008F14_IMG_FMASK_8_2_1
;
4086 num_format
= V_008F14_IMG_FMASK_8_2_2
;
4089 num_format
= V_008F14_IMG_FMASK_8_4_1
;
4092 num_format
= V_008F14_IMG_FMASK_8_4_2
;
4095 num_format
= V_008F14_IMG_FMASK_8_4_4
;
4098 num_format
= V_008F14_IMG_FMASK_8_8_1
;
4101 num_format
= V_008F14_IMG_FMASK_16_8_2
;
4104 num_format
= V_008F14_IMG_FMASK_32_8_4
;
4107 num_format
= V_008F14_IMG_FMASK_32_8_8
;
4110 num_format
= V_008F14_IMG_FMASK_16_16_1
;
4113 num_format
= V_008F14_IMG_FMASK_32_16_2
;
4116 num_format
= V_008F14_IMG_FMASK_64_16_4
;
4119 num_format
= V_008F14_IMG_FMASK_64_16_8
;
4122 unreachable("invalid nr_samples");
4125 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4127 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4130 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4133 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4136 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4139 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4142 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4145 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4148 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4151 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4154 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4157 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4160 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4163 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4166 unreachable("invalid nr_samples");
4168 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4172 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4173 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) | S_008F14_DATA_FORMAT(data_format
) |
4174 S_008F14_NUM_FORMAT(num_format
);
4175 fmask_state
[2] = S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1);
4177 S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4178 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4179 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4181 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4185 if (screen
->info
.chip_class
== GFX9
) {
4186 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4188 S_008F20_DEPTH(last_layer
) | S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4189 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
4190 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
4192 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4193 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4194 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4195 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4201 * Create a sampler view.
4203 * @param ctx context
4204 * @param texture texture
4205 * @param state sampler view template
4206 * @param width0 width0 override (for compressed textures as int)
4207 * @param height0 height0 override (for compressed textures as int)
4208 * @param force_level set the base address to the level (for compressed textures)
4210 struct pipe_sampler_view
*si_create_sampler_view_custom(struct pipe_context
*ctx
,
4211 struct pipe_resource
*texture
,
4212 const struct pipe_sampler_view
*state
,
4213 unsigned width0
, unsigned height0
,
4214 unsigned force_level
)
4216 struct si_context
*sctx
= (struct si_context
*)ctx
;
4217 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4218 struct si_texture
*tex
= (struct si_texture
*)texture
;
4219 unsigned base_level
, first_level
, last_level
;
4220 unsigned char state_swizzle
[4];
4221 unsigned height
, depth
, width
;
4222 unsigned last_layer
= state
->u
.tex
.last_layer
;
4223 enum pipe_format pipe_format
;
4224 const struct legacy_surf_level
*surflevel
;
4229 /* initialize base object */
4230 view
->base
= *state
;
4231 view
->base
.texture
= NULL
;
4232 view
->base
.reference
.count
= 1;
4233 view
->base
.context
= ctx
;
4236 pipe_resource_reference(&view
->base
.texture
, texture
);
4238 if (state
->format
== PIPE_FORMAT_X24S8_UINT
|| state
->format
== PIPE_FORMAT_S8X24_UINT
||
4239 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
|| state
->format
== PIPE_FORMAT_S8_UINT
)
4240 view
->is_stencil_sampler
= true;
4242 /* Buffer resource. */
4243 if (texture
->target
== PIPE_BUFFER
) {
4244 si_make_buffer_descriptor(sctx
->screen
, si_resource(texture
), state
->format
,
4245 state
->u
.buf
.offset
, state
->u
.buf
.size
, view
->state
);
4249 state_swizzle
[0] = state
->swizzle_r
;
4250 state_swizzle
[1] = state
->swizzle_g
;
4251 state_swizzle
[2] = state
->swizzle_b
;
4252 state_swizzle
[3] = state
->swizzle_a
;
4255 first_level
= state
->u
.tex
.first_level
;
4256 last_level
= state
->u
.tex
.last_level
;
4259 depth
= texture
->depth0
;
4261 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4262 assert(force_level
== first_level
&& force_level
== last_level
);
4263 base_level
= force_level
;
4266 width
= u_minify(width
, force_level
);
4267 height
= u_minify(height
, force_level
);
4268 depth
= u_minify(depth
, force_level
);
4271 /* This is not needed if state trackers set last_layer correctly. */
4272 if (state
->target
== PIPE_TEXTURE_1D
|| state
->target
== PIPE_TEXTURE_2D
||
4273 state
->target
== PIPE_TEXTURE_RECT
|| state
->target
== PIPE_TEXTURE_CUBE
)
4274 last_layer
= state
->u
.tex
.first_layer
;
4276 /* Texturing with separate depth and stencil. */
4277 pipe_format
= state
->format
;
4279 /* Depth/stencil texturing sometimes needs separate texture. */
4280 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4281 if (!tex
->flushed_depth_texture
&& !si_init_flushed_depth_texture(ctx
, texture
)) {
4282 pipe_resource_reference(&view
->base
.texture
, NULL
);
4287 assert(tex
->flushed_depth_texture
);
4289 /* Override format for the case where the flushed texture
4290 * contains only Z or only S.
4292 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4293 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4295 tex
= tex
->flushed_depth_texture
;
4298 surflevel
= tex
->surface
.u
.legacy
.level
;
4300 if (tex
->db_compatible
) {
4301 if (!view
->is_stencil_sampler
)
4302 pipe_format
= tex
->db_render_format
;
4304 switch (pipe_format
) {
4305 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4306 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4308 case PIPE_FORMAT_X8Z24_UNORM
:
4309 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4310 /* Z24 is always stored like this for DB
4313 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4315 case PIPE_FORMAT_X24S8_UINT
:
4316 case PIPE_FORMAT_S8X24_UINT
:
4317 case PIPE_FORMAT_X32_S8X24_UINT
:
4318 pipe_format
= PIPE_FORMAT_S8_UINT
;
4319 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4325 view
->dcc_incompatible
=
4326 vi_dcc_formats_are_incompatible(texture
, state
->u
.tex
.first_level
, state
->format
);
4328 sctx
->screen
->make_texture_descriptor(
4329 sctx
->screen
, tex
, true, state
->target
, pipe_format
, state_swizzle
, first_level
, last_level
,
4330 state
->u
.tex
.first_layer
, last_layer
, width
, height
, depth
, view
->state
, view
->fmask_state
);
4332 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4333 view
->is_integer
= false;
4335 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4336 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4339 /* Whether the number format is {U,S}{SCALED,INT} */
4340 view
->is_integer
= (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4341 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4342 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4346 view
->base_level_info
= &surflevel
[base_level
];
4347 view
->base_level
= base_level
;
4348 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4352 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
4353 struct pipe_resource
*texture
,
4354 const struct pipe_sampler_view
*state
)
4356 return si_create_sampler_view_custom(ctx
, texture
, state
, texture
? texture
->width0
: 0,
4357 texture
? texture
->height0
: 0, 0);
4360 static void si_sampler_view_destroy(struct pipe_context
*ctx
, struct pipe_sampler_view
*state
)
4362 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4364 pipe_resource_reference(&state
->texture
, NULL
);
4368 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4370 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4371 (linear_filter
&& (wrap
== PIPE_TEX_WRAP_CLAMP
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4374 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4375 const struct pipe_sampler_state
*state
,
4376 const union pipe_color_union
*color
, bool is_integer
)
4378 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4379 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4381 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4382 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4383 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4384 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4386 #define simple_border_types(elt) \
4388 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4389 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4390 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4391 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4392 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4393 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4397 simple_border_types(ui
);
4399 simple_border_types(f
);
4401 #undef simple_border_types
4405 /* Check if the border has been uploaded already. */
4406 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4407 if (memcmp(&sctx
->border_color_table
[i
], color
, sizeof(*color
)) == 0)
4410 if (i
>= SI_MAX_BORDER_COLORS
) {
4411 /* Getting 4096 unique border colors is very unlikely. */
4412 fprintf(stderr
, "radeonsi: The border color table is full. "
4413 "Any new border colors will be just black. "
4414 "Please file a bug.\n");
4415 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4418 if (i
== sctx
->border_color_count
) {
4419 /* Upload a new border color. */
4420 memcpy(&sctx
->border_color_table
[i
], color
, sizeof(*color
));
4421 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
], color
, sizeof(*color
));
4422 sctx
->border_color_count
++;
4425 return S_008F3C_BORDER_COLOR_PTR(i
) |
4426 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4429 static inline int S_FIXED(float value
, unsigned frac_bits
)
4431 return value
* (1 << frac_bits
);
4434 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4436 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4437 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4438 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4440 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4441 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4444 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4457 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4458 const struct pipe_sampler_state
*state
)
4460 struct si_context
*sctx
= (struct si_context
*)ctx
;
4461 struct si_screen
*sscreen
= sctx
->screen
;
4462 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4463 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
: state
->max_anisotropy
;
4464 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4465 union pipe_color_union clamped_border_color
;
4472 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4475 (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) | S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4476 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4477 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4478 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4479 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4480 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4481 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4482 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4483 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4484 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4485 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4486 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4487 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4488 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4489 S_008F38_MIP_POINT_PRECLAMP(0));
4490 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4492 if (sscreen
->info
.chip_class
>= GFX10
) {
4493 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4495 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4496 S_008F38_FILTER_PREC_FIX(1) |
4497 S_008F38_ANISO_OVERRIDE_GFX6(sctx
->chip_class
>= GFX8
);
4500 /* Create sampler resource for integer textures. */
4501 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4502 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4504 /* Create sampler resource for upgraded depth textures. */
4505 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4507 for (unsigned i
= 0; i
< 4; ++i
) {
4508 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4509 * when the border color is 1.0. */
4510 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4513 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4514 if (sscreen
->info
.chip_class
<= GFX9
)
4515 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4517 rstate
->upgraded_depth_val
[3] =
4518 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4524 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4526 struct si_context
*sctx
= (struct si_context
*)ctx
;
4528 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4531 sctx
->sample_mask
= sample_mask
;
4532 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4535 static void si_emit_sample_mask(struct si_context
*sctx
)
4537 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4538 unsigned mask
= sctx
->sample_mask
;
4540 /* Needed for line and polygon smoothing as well as for the Polaris
4541 * small primitive filter. We expect the state tracker to take care of
4544 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4545 (mask
& 1 && sctx
->blitter
->running
));
4547 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4548 radeon_emit(cs
, mask
| (mask
<< 16));
4549 radeon_emit(cs
, mask
| (mask
<< 16));
4552 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4555 struct si_sampler_state
*s
= state
;
4557 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4564 * Vertex elements & buffers
4567 struct si_fast_udiv_info32
si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4569 struct util_fast_udiv_info info
= util_compute_fast_udiv_info(D
, num_bits
, 32);
4571 struct si_fast_udiv_info32 result
= {
4580 static void *si_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
4581 const struct pipe_vertex_element
*elements
)
4583 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4584 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4585 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4586 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4587 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4588 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4589 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4590 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4591 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4594 assert(count
<= SI_MAX_ATTRIBS
);
4600 unsigned alloc_count
=
4601 count
> sscreen
->num_vbos_in_user_sgprs
? count
- sscreen
->num_vbos_in_user_sgprs
: 0;
4602 v
->vb_desc_list_alloc_size
= align(alloc_count
* 16, SI_CPDMA_ALIGNMENT
);
4604 for (i
= 0; i
< count
; ++i
) {
4605 const struct util_format_description
*desc
;
4606 const struct util_format_channel_description
*channel
;
4608 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4610 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4615 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4616 if (instance_divisor
) {
4617 v
->uses_instance_divisors
= true;
4619 if (instance_divisor
== 1) {
4620 v
->instance_divisor_is_one
|= 1u << i
;
4622 v
->instance_divisor_is_fetched
|= 1u << i
;
4623 divisor_factors
[i
] = si_compute_fast_udiv_info32(instance_divisor
, 32);
4627 if (!used
[vbo_index
]) {
4628 v
->first_vb_use_mask
|= 1 << i
;
4629 used
[vbo_index
] = true;
4632 desc
= util_format_description(elements
[i
].src_format
);
4633 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4634 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4636 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4637 v
->src_offset
[i
] = elements
[i
].src_offset
;
4638 v
->vertex_buffer_index
[i
] = vbo_index
;
4640 bool always_fix
= false;
4641 union si_vs_fix_fetch fix_fetch
;
4642 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4645 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4648 switch (channel
->type
) {
4649 case UTIL_FORMAT_TYPE_FLOAT
:
4650 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4652 case UTIL_FORMAT_TYPE_FIXED
:
4653 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4655 case UTIL_FORMAT_TYPE_SIGNED
: {
4656 if (channel
->pure_integer
)
4657 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4658 else if (channel
->normalized
)
4659 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4661 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4664 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4665 if (channel
->pure_integer
)
4666 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4667 else if (channel
->normalized
)
4668 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4670 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4674 unreachable("bad format type");
4677 switch (elements
[i
].src_format
) {
4678 case PIPE_FORMAT_R11G11B10_FLOAT
:
4679 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4682 unreachable("bad other format");
4686 if (desc
->channel
[0].size
== 10) {
4687 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4688 log_hw_load_size
= 2;
4690 /* The hardware always treats the 2-bit alpha channel as
4691 * unsigned, so a shader workaround is needed. The affected
4692 * chips are GFX8 and older except Stoney (GFX8.1).
4694 always_fix
= sscreen
->info
.chip_class
<= GFX8
&& sscreen
->info
.family
!= CHIP_STONEY
&&
4695 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4696 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4697 fix_fetch
.u
.log_size
= 3; /* special encoding */
4698 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4699 log_hw_load_size
= 2;
4701 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4702 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4705 * - doubles (multiple loads + truncate to float)
4706 * - 32-bit requiring a conversion
4708 always_fix
= (fix_fetch
.u
.log_size
== 3) ||
4709 (fix_fetch
.u
.log_size
== 2 && fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4710 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4711 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4713 /* Also fixup 8_8_8 and 16_16_16. */
4714 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4716 log_hw_load_size
= fix_fetch
.u
.log_size
;
4720 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4721 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4722 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4723 fix_fetch
.u
.reverse
= 1;
4726 /* Force the workaround for unaligned access here already if the
4727 * offset relative to the vertex buffer base is unaligned.
4729 * There is a theoretical case in which this is too conservative:
4730 * if the vertex buffer's offset is also unaligned in just the
4731 * right way, we end up with an aligned address after all.
4732 * However, this case should be extremely rare in practice (it
4733 * won't happen in well-behaved applications), and taking it
4734 * into account would complicate the fast path (where everything
4735 * is nicely aligned).
4737 bool check_alignment
= log_hw_load_size
>= 1 && (sscreen
->info
.chip_class
== GFX6
||
4738 sscreen
->info
.chip_class
== GFX10
);
4739 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4741 if (check_alignment
&& (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4744 if (always_fix
|| check_alignment
|| opencode
)
4745 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4748 v
->fix_fetch_opencode
|= 1 << i
;
4749 if (opencode
|| always_fix
)
4750 v
->fix_fetch_always
|= 1 << i
;
4752 if (check_alignment
&& !opencode
) {
4753 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4755 v
->fix_fetch_unaligned
|= 1 << i
;
4756 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4757 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
4760 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
4761 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
4762 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
4763 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
4765 if (sscreen
->info
.chip_class
>= GFX10
) {
4766 const struct gfx10_format
*fmt
= &gfx10_format_table
[elements
[i
].src_format
];
4767 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
4768 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) | S_008F0C_RESOURCE_LEVEL(1);
4770 unsigned data_format
, num_format
;
4771 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4772 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4773 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
4777 if (v
->instance_divisor_is_fetched
) {
4778 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4780 v
->instance_divisor_factor_buffer
= (struct si_resource
*)pipe_buffer_create(
4781 &sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, num_divisors
* sizeof(divisor_factors
[0]));
4782 if (!v
->instance_divisor_factor_buffer
) {
4787 sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
4788 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4793 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4795 struct si_context
*sctx
= (struct si_context
*)ctx
;
4796 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4797 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4799 sctx
->vertex_elements
= v
;
4800 sctx
->num_vertex_elements
= v
? v
->count
: 0;
4802 if (sctx
->num_vertex_elements
) {
4803 sctx
->vertex_buffers_dirty
= true;
4805 sctx
->vertex_buffer_pointer_dirty
= false;
4806 sctx
->vertex_buffer_user_sgprs_dirty
= false;
4809 if (v
&& (!old
|| old
->count
!= v
->count
||
4810 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4811 /* we don't check which divisors changed */
4812 v
->uses_instance_divisors
||
4813 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) &
4814 sctx
->vertex_buffer_unaligned
||
4815 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
4816 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
4817 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
4818 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4819 * functions of fix_fetch and the src_offset alignment.
4820 * If they change and fix_fetch doesn't, it must be due to different
4821 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4822 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
4823 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4824 sctx
->do_update_shaders
= true;
4826 if (v
&& v
->instance_divisor_is_fetched
) {
4827 struct pipe_constant_buffer cb
;
4829 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4830 cb
.user_buffer
= NULL
;
4831 cb
.buffer_offset
= 0;
4832 cb
.buffer_size
= 0xffffffff;
4833 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4837 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4839 struct si_context
*sctx
= (struct si_context
*)ctx
;
4840 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4842 if (sctx
->vertex_elements
== state
) {
4843 sctx
->vertex_elements
= NULL
;
4844 sctx
->num_vertex_elements
= 0;
4846 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4850 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
4851 const struct pipe_vertex_buffer
*buffers
)
4853 struct si_context
*sctx
= (struct si_context
*)ctx
;
4854 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4855 unsigned updated_mask
= u_bit_consecutive(start_slot
, count
);
4856 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
4857 uint32_t unaligned
= 0;
4860 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4863 for (i
= 0; i
< count
; i
++) {
4864 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4865 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4866 struct pipe_resource
*buf
= src
->buffer
.resource
;
4867 unsigned slot_bit
= 1 << (start_slot
+ i
);
4869 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4870 dsti
->buffer_offset
= src
->buffer_offset
;
4871 dsti
->stride
= src
->stride
;
4873 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
4874 unaligned
|= slot_bit
;
4876 si_context_add_resource_size(sctx
, buf
);
4878 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4881 for (i
= 0; i
< count
; i
++) {
4882 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4884 unaligned
&= ~updated_mask
;
4886 sctx
->vertex_buffers_dirty
= true;
4887 sctx
->vertex_buffer_unaligned
= (orig_unaligned
& ~updated_mask
) | unaligned
;
4889 /* Check whether alignment may have changed in a way that requires
4890 * shader changes. This check is conservative: a vertex buffer can only
4891 * trigger a shader change if the misalignment amount changes (e.g.
4892 * from byte-aligned to short-aligned), but we only keep track of
4893 * whether buffers are at least dword-aligned, since that should always
4894 * be the case in well-behaved applications anyway.
4896 if (sctx
->vertex_elements
&& (sctx
->vertex_elements
->vb_alignment_check_mask
&
4897 (unaligned
| orig_unaligned
) & updated_mask
))
4898 sctx
->do_update_shaders
= true;
4905 static void si_set_tess_state(struct pipe_context
*ctx
, const float default_outer_level
[4],
4906 const float default_inner_level
[2])
4908 struct si_context
*sctx
= (struct si_context
*)ctx
;
4909 struct pipe_constant_buffer cb
;
4912 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4913 memcpy(array
+ 4, default_inner_level
, sizeof(float) * 2);
4916 cb
.user_buffer
= NULL
;
4917 cb
.buffer_size
= sizeof(array
);
4919 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
, (void *)array
, sizeof(array
),
4922 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4923 pipe_resource_reference(&cb
.buffer
, NULL
);
4926 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4928 struct si_context
*sctx
= (struct si_context
*)ctx
;
4930 si_update_fb_dirtiness_after_rendering(sctx
);
4932 /* Multisample surfaces are flushed in si_decompress_textures. */
4933 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
4934 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4935 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
4936 sctx
->framebuffer
.all_DCC_pipe_aligned
);
4940 /* This only ensures coherency for shader image/buffer stores. */
4941 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4943 struct si_context
*sctx
= (struct si_context
*)ctx
;
4945 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
4948 /* Subsequent commands must wait for all shader invocations to
4950 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
4952 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4953 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
;
4955 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
| PIPE_BARRIER_SHADER_BUFFER
| PIPE_BARRIER_TEXTURE
|
4956 PIPE_BARRIER_IMAGE
| PIPE_BARRIER_STREAMOUT_BUFFER
| PIPE_BARRIER_GLOBAL_BUFFER
)) {
4957 /* As far as I can tell, L1 contents are written back to L2
4958 * automatically at end of shader, but the contents of other
4959 * L1 caches might still be stale. */
4960 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
4963 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4964 /* Indices are read through TC L2 since GFX8.
4967 if (sctx
->screen
->info
.chip_class
<= GFX7
)
4968 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4971 /* MSAA color, any depth and any stencil are flushed in
4972 * si_decompress_textures when needed.
4974 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&& sctx
->framebuffer
.uncompressed_cb_mask
) {
4975 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4977 if (sctx
->chip_class
<= GFX8
)
4978 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4981 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4982 if (sctx
->screen
->info
.chip_class
<= GFX8
&& flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4983 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4986 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4988 struct pipe_blend_state blend
;
4990 memset(&blend
, 0, sizeof(blend
));
4991 blend
.independent_blend_enable
= true;
4992 blend
.rt
[0].colormask
= 0xf;
4993 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4996 static void si_init_config(struct si_context
*sctx
);
4998 void si_init_state_compute_functions(struct si_context
*sctx
)
5000 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
5001 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
5002 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
5003 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
5004 sctx
->b
.memory_barrier
= si_memory_barrier
;
5007 void si_init_state_functions(struct si_context
*sctx
)
5009 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
5010 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
5011 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
5012 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
5013 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
5014 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
5015 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
5016 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
5017 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
5018 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
5019 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
5021 sctx
->b
.create_blend_state
= si_create_blend_state
;
5022 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
5023 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
5024 sctx
->b
.set_blend_color
= si_set_blend_color
;
5026 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
5027 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
5028 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
5030 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
5031 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
5032 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5034 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5035 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5036 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5037 sctx
->custom_blend_eliminate_fastclear
=
5038 si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5039 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5041 sctx
->b
.set_clip_state
= si_set_clip_state
;
5042 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5044 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5046 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5048 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5049 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5050 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5051 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5053 sctx
->b
.texture_barrier
= si_texture_barrier
;
5054 sctx
->b
.set_min_samples
= si_set_min_samples
;
5055 sctx
->b
.set_tess_state
= si_set_tess_state
;
5057 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5059 si_init_config(sctx
);
5062 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5064 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5066 if (sscreen
->info
.chip_class
>= GFX10
) {
5067 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5069 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5073 static void si_set_grbm_gfx_index(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned value
)
5075 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
: R_00802C_GRBM_GFX_INDEX
;
5076 si_pm4_set_reg(pm4
, reg
, value
);
5079 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned se
)
5081 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5082 si_set_grbm_gfx_index(sctx
, pm4
,
5083 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se
)) |
5084 S_030800_SH_BROADCAST_WRITES(1) |
5085 S_030800_INSTANCE_BROADCAST_WRITES(1));
5088 static void si_write_harvested_raster_configs(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
5089 unsigned raster_config
, unsigned raster_config_1
)
5091 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5092 unsigned raster_config_se
[4];
5095 ac_get_harvested_configs(&sctx
->screen
->info
, raster_config
, &raster_config_1
, raster_config_se
);
5097 for (se
= 0; se
< num_se
; se
++) {
5098 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5099 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5101 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5103 if (sctx
->chip_class
>= GFX7
) {
5104 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5108 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5110 struct si_screen
*sscreen
= sctx
->screen
;
5111 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5112 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5113 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5114 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5116 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5117 /* Always use the default config when all backends are enabled
5118 * (or when we failed to determine the enabled backends).
5120 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config
);
5121 if (sctx
->chip_class
>= GFX7
)
5122 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5124 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5128 static void si_init_config(struct si_context
*sctx
)
5130 struct si_screen
*sscreen
= sctx
->screen
;
5131 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5132 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5133 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5138 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
5139 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
5140 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5141 si_pm4_cmd_end(pm4
, false);
5143 if (has_clear_state
) {
5144 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
5145 si_pm4_cmd_add(pm4
, 0);
5146 si_pm4_cmd_end(pm4
, false);
5149 if (sctx
->chip_class
<= GFX8
)
5150 si_set_raster_config(sctx
, pm4
);
5152 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5153 if (!has_clear_state
)
5154 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5156 /* FIXME calculate these values somehow ??? */
5157 if (sctx
->chip_class
<= GFX8
) {
5158 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5159 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5162 if (!has_clear_state
) {
5163 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5164 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5165 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5168 if (sscreen
->info
.chip_class
<= GFX9
)
5169 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5170 if (!has_clear_state
)
5171 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5172 if (sctx
->chip_class
< GFX7
)
5173 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
,
5174 S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
5176 /* CLEAR_STATE doesn't restore these correctly. */
5177 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5178 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5179 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5181 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5182 * I don't know why. Deduced by trial and error.
5184 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5185 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5186 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5187 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5188 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5189 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5192 if (!has_clear_state
) {
5193 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5194 S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
5195 /* Required by DX10_DIAMOND_TEST_ENA: */
5196 S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
5197 S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
5198 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5199 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5200 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5201 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5202 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5205 if (sctx
->chip_class
>= GFX10
) {
5206 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5207 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5208 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5209 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5210 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5211 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5212 } else if (sctx
->chip_class
== GFX9
) {
5213 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5214 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5215 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5217 /* These registers, when written, also overwrite the CLEAR_STATE
5218 * context, so we can't rely on CLEAR_STATE setting them.
5219 * It would be an issue if there was another UMD changing them.
5221 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5222 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5223 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5226 if (sctx
->chip_class
>= GFX7
) {
5227 if (sctx
->chip_class
>= GFX10
) {
5228 /* Logical CUs 16 - 31 */
5229 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
, S_00B404_CU_EN(0xffff));
5230 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
, S_00B104_CU_EN(0xffff));
5231 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
, S_00B004_CU_EN(0xffff));
5234 if (sctx
->chip_class
>= GFX9
) {
5235 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5236 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5238 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5239 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5240 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_WAVE_LIMIT(0x3F));
5241 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5242 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5244 /* If this is 0, Bonaire can hang even if GS isn't being used.
5245 * Other chips are unaffected. These are suboptimal values,
5246 * but we don't use on-chip GS.
5248 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5249 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
5252 /* Compute LATE_ALLOC_VS.LIMIT. */
5253 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
5254 unsigned late_alloc_wave64
= 0; /* The limit is per SH. */
5255 unsigned cu_mask_vs
= 0xffff;
5256 unsigned cu_mask_gs
= 0xffff;
5258 if (sctx
->chip_class
>= GFX10
) {
5259 /* For Wave32, the hw will launch twice the number of late
5260 * alloc waves, so 1 == 2x wave32.
5262 if (!sscreen
->info
.use_late_alloc
) {
5263 late_alloc_wave64
= 0;
5264 } else if (num_cu_per_sh
<= 6) {
5265 late_alloc_wave64
= num_cu_per_sh
- 2;
5267 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5269 /* CU2 & CU3 disabled because of the dual CU design */
5270 /* Late alloc is not used for NGG on Navi14 due to a hw bug. */
5271 cu_mask_vs
= 0xfff3;
5272 cu_mask_gs
= sscreen
->use_ngg
&& sctx
->family
!= CHIP_NAVI14
? 0xfff3 : 0xffff;
5275 if (!sscreen
->info
.use_late_alloc
) {
5276 late_alloc_wave64
= 0;
5277 } else if (num_cu_per_sh
<= 4) {
5278 /* Too few available compute units per SH. Disallowing
5279 * VS to run on one CU could hurt us more than late VS
5280 * allocation would help.
5282 * 2 is the highest safe number that allows us to keep
5285 late_alloc_wave64
= 2;
5287 /* This is a good initial value, allowing 1 late_alloc
5288 * wave per SIMD on num_cu - 2.
5290 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5293 if (late_alloc_wave64
> 2)
5294 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5297 /* VS can't execute on one CU if the limit is > 2. */
5298 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5299 S_00B118_CU_EN(cu_mask_vs
) | S_00B118_WAVE_LIMIT(0x3F));
5300 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(late_alloc_wave64
));
5302 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5303 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5305 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5306 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5309 if (sctx
->chip_class
>= GFX10
) {
5310 /* Break up a pixel wave if it contains deallocs for more than
5311 * half the parameter cache.
5313 * To avoid a deadlock where pixel waves aren't launched
5314 * because they're waiting for more pixels while the frontend
5315 * is stuck waiting for PC space, the maximum allowed value is
5316 * the size of the PC minus the largest possible allocation for
5317 * a single primitive shader subgroup.
5319 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5320 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5322 if (!has_clear_state
) {
5323 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5324 sscreen
->info
.pa_sc_tile_steering_override
);
5327 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
5328 unsigned meta_write_policy
, meta_read_policy
;
5329 /* TODO: investigate whether LRU improves performance on other chips too */
5330 if (sscreen
->info
.num_render_backends
<= 4) {
5331 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
5332 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
5334 meta_write_policy
= V_02807C_CACHE_STREAM_WR
; /* write combine */
5335 meta_read_policy
= V_02807C_CACHE_NOA_RD
; /* don't cache reads */
5338 si_pm4_set_reg(pm4
, R_02807C_DB_RMI_L2_CACHE_CONTROL
,
5339 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5340 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5341 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
5342 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM_WR
) |
5343 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5344 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA_RD
) |
5345 S_02807C_HTILE_RD_POLICY(meta_read_policy
));
5348 pm4
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
5349 S_028410_CMASK_WR_POLICY(meta_write_policy
) | S_028410_FMASK_WR_POLICY(meta_write_policy
) |
5350 S_028410_DCC_WR_POLICY(meta_write_policy
) |
5351 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM_WR
) |
5352 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
5353 S_028410_FMASK_RD_POLICY(meta_read_policy
) | S_028410_DCC_RD_POLICY(meta_read_policy
) |
5354 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA_RD
));
5355 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5357 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5358 S_00B0C0_SOFT_GROUPING_EN(1) | S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5359 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5362 if (sctx
->chip_class
>= GFX9
) {
5363 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
,
5364 S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
5365 S_028B50_DONUT_SPLIT(24) | S_028B50_TRAP_SPLIT(6));
5366 } else if (sctx
->chip_class
>= GFX8
) {
5367 unsigned vgt_tess_distribution
;
5369 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
5370 S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT(16);
5372 /* Testing with Unigine Heaven extreme tesselation yielded best results
5373 * with TRAP_SPLIT = 3.
5375 if (sctx
->family
== CHIP_FIJI
|| sctx
->family
>= CHIP_POLARIS10
)
5376 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5378 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5379 } else if (!has_clear_state
) {
5380 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5381 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5384 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5385 if (sctx
->chip_class
>= GFX7
) {
5386 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, S_028084_ADDRESS(border_color_va
>> 40));
5388 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
, RADEON_PRIO_BORDER_COLORS
);
5390 if (sctx
->chip_class
>= GFX9
) {
5391 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5392 S_028C48_MAX_ALLOC_COUNT(sscreen
->info
.pbb_max_alloc_count
- 1) |
5393 S_028C48_MAX_PRIM_PER_BATCH(1023));
5394 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5395 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5396 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5399 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5400 sctx
->init_config
= pm4
;