2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "util/fast_idiv_by_const.h"
29 #include "util/format/u_format.h"
30 #include "util/format/u_format_s3tc.h"
31 #include "util/u_dual_blend.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/u_blend.h"
37 #include "gfx10_format_table.h"
39 static unsigned si_map_swizzle(unsigned swizzle
)
43 return V_008F0C_SQ_SEL_Y
;
45 return V_008F0C_SQ_SEL_Z
;
47 return V_008F0C_SQ_SEL_W
;
49 return V_008F0C_SQ_SEL_0
;
51 return V_008F0C_SQ_SEL_1
;
52 default: /* PIPE_SWIZZLE_X */
53 return V_008F0C_SQ_SEL_X
;
57 /* 12.4 fixed-point */
58 static unsigned si_pack_float_12p4(float x
)
60 return x
<= 0 ? 0 : x
>= 4096 ? 0xffff : x
* 16;
64 * Inferred framebuffer and blender state.
66 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
67 * if there is not enough PS outputs.
69 static void si_emit_cb_render_state(struct si_context
*sctx
)
71 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
72 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
73 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
74 * but you never know. */
75 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
& blend
->cb_target_mask
;
78 /* Avoid a hang that happens when dual source blending is enabled
79 * but there is not enough color outputs. This is undefined behavior,
80 * so disable color writes completely.
82 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 if (blend
->dual_src_blend
&& sctx
->ps_shader
.cso
&&
85 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
88 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
89 * I think we don't have to do anything between IBs.
91 if (sctx
->screen
->dpbb_allowed
&& sctx
->last_cb_target_mask
!= cb_target_mask
) {
92 sctx
->last_cb_target_mask
= cb_target_mask
;
94 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
95 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
98 unsigned initial_cdw
= cs
->current
.cdw
;
99 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
, SI_TRACKED_CB_TARGET_MASK
,
102 if (sctx
->chip_class
>= GFX8
) {
103 /* DCC MSAA workaround.
104 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
105 * COMBINER_DISABLE, but that would be more complicated.
108 blend
->dcc_msaa_corruption_4bit
& cb_target_mask
&& sctx
->framebuffer
.nr_samples
>= 2;
109 unsigned watermark
= sctx
->framebuffer
.dcc_overwrite_combiner_watermark
;
111 radeon_opt_set_context_reg(
112 sctx
, R_028424_CB_DCC_CONTROL
, SI_TRACKED_CB_DCC_CONTROL
,
113 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(sctx
->chip_class
<= GFX9
) |
114 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark
) |
115 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
) |
116 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx
->screen
->info
.has_dcc_constant_encode
));
119 /* RB+ register settings. */
120 if (sctx
->screen
->info
.rbplus_allowed
) {
121 unsigned spi_shader_col_format
=
122 sctx
->ps_shader
.cso
? sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
124 unsigned sx_ps_downconvert
= 0;
125 unsigned sx_blend_opt_epsilon
= 0;
126 unsigned sx_blend_opt_control
= 0;
128 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
129 struct si_surface
*surf
= (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
130 unsigned format
, swap
, spi_format
, colormask
;
131 bool has_alpha
, has_rgb
;
134 /* If the color buffer is not set, the driver sets 32_R
135 * as the SPI color format, because the hw doesn't allow
136 * holes between color outputs, so also set this to
139 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
143 format
= G_028C70_FORMAT(surf
->cb_color_info
);
144 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
145 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
146 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
148 /* Set if RGB and A are present. */
149 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
151 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_16
||
152 format
== V_028C70_COLOR_32
)
153 has_rgb
= !has_alpha
;
157 /* Check the colormask and export format. */
158 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
160 if (!(colormask
& PIPE_MASK_A
))
163 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
168 /* Disable value checking for disabled channels. */
170 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
172 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
174 /* Enable down-conversion for 32bpp and smaller formats. */
176 case V_028C70_COLOR_8
:
177 case V_028C70_COLOR_8_8
:
178 case V_028C70_COLOR_8_8_8_8
:
179 /* For 1 and 2-channel formats, use the superset thereof. */
180 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
181 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
182 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
183 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
184 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
188 case V_028C70_COLOR_5_6_5
:
189 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
190 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
191 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
195 case V_028C70_COLOR_1_5_5_5
:
196 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
197 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
198 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
202 case V_028C70_COLOR_4_4_4_4
:
203 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
204 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
205 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
209 case V_028C70_COLOR_32
:
210 if (swap
== V_028C70_SWAP_STD
&& spi_format
== V_028714_SPI_SHADER_32_R
)
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
212 else if (swap
== V_028C70_SWAP_ALT_REV
&& spi_format
== V_028714_SPI_SHADER_32_AR
)
213 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
216 case V_028C70_COLOR_16
:
217 case V_028C70_COLOR_16_16
:
218 /* For 1-channel formats, use the superset thereof. */
219 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
220 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
221 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
222 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
223 if (swap
== V_028C70_SWAP_STD
|| swap
== V_028C70_SWAP_STD_REV
)
224 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
226 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
230 case V_028C70_COLOR_10_11_11
:
231 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
232 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
235 case V_028C70_COLOR_2_10_10_10
:
236 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
237 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
238 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
242 case V_028C70_COLOR_5_9_9_9
:
243 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
)
244 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_9_9_9_E5
<< (i
* 4);
249 /* If there are no color outputs, the first color export is
250 * always enabled as 32_R, so also set this to enable RB+.
252 if (!sx_ps_downconvert
)
253 sx_ps_downconvert
= V_028754_SX_RT_EXPORT_32_R
;
255 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
256 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
, SI_TRACKED_SX_PS_DOWNCONVERT
,
257 sx_ps_downconvert
, sx_blend_opt_epsilon
, sx_blend_opt_control
);
259 if (initial_cdw
!= cs
->current
.cdw
)
260 sctx
->context_roll
= true;
267 static uint32_t si_translate_blend_function(int blend_func
)
269 switch (blend_func
) {
271 return V_028780_COMB_DST_PLUS_SRC
;
272 case PIPE_BLEND_SUBTRACT
:
273 return V_028780_COMB_SRC_MINUS_DST
;
274 case PIPE_BLEND_REVERSE_SUBTRACT
:
275 return V_028780_COMB_DST_MINUS_SRC
;
277 return V_028780_COMB_MIN_DST_SRC
;
279 return V_028780_COMB_MAX_DST_SRC
;
281 PRINT_ERR("Unknown blend function %d\n", blend_func
);
288 static uint32_t si_translate_blend_factor(int blend_fact
)
290 switch (blend_fact
) {
291 case PIPE_BLENDFACTOR_ONE
:
292 return V_028780_BLEND_ONE
;
293 case PIPE_BLENDFACTOR_SRC_COLOR
:
294 return V_028780_BLEND_SRC_COLOR
;
295 case PIPE_BLENDFACTOR_SRC_ALPHA
:
296 return V_028780_BLEND_SRC_ALPHA
;
297 case PIPE_BLENDFACTOR_DST_ALPHA
:
298 return V_028780_BLEND_DST_ALPHA
;
299 case PIPE_BLENDFACTOR_DST_COLOR
:
300 return V_028780_BLEND_DST_COLOR
;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
303 case PIPE_BLENDFACTOR_CONST_COLOR
:
304 return V_028780_BLEND_CONSTANT_COLOR
;
305 case PIPE_BLENDFACTOR_CONST_ALPHA
:
306 return V_028780_BLEND_CONSTANT_ALPHA
;
307 case PIPE_BLENDFACTOR_ZERO
:
308 return V_028780_BLEND_ZERO
;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
321 case PIPE_BLENDFACTOR_SRC1_COLOR
:
322 return V_028780_BLEND_SRC1_COLOR
;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
324 return V_028780_BLEND_SRC1_ALPHA
;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
326 return V_028780_BLEND_INV_SRC1_COLOR
;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
328 return V_028780_BLEND_INV_SRC1_ALPHA
;
330 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
337 static uint32_t si_translate_blend_opt_function(int blend_func
)
339 switch (blend_func
) {
341 return V_028760_OPT_COMB_ADD
;
342 case PIPE_BLEND_SUBTRACT
:
343 return V_028760_OPT_COMB_SUBTRACT
;
344 case PIPE_BLEND_REVERSE_SUBTRACT
:
345 return V_028760_OPT_COMB_REVSUBTRACT
;
347 return V_028760_OPT_COMB_MIN
;
349 return V_028760_OPT_COMB_MAX
;
351 return V_028760_OPT_COMB_BLEND_DISABLED
;
355 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
357 switch (blend_fact
) {
358 case PIPE_BLENDFACTOR_ZERO
:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
360 case PIPE_BLENDFACTOR_ONE
:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
362 case PIPE_BLENDFACTOR_SRC_COLOR
:
363 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
368 case PIPE_BLENDFACTOR_SRC_ALPHA
:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
373 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
380 static void si_blend_check_commutativity(struct si_screen
*sscreen
, struct si_state_blend
*blend
,
381 enum pipe_blend_func func
, enum pipe_blendfactor src
,
382 enum pipe_blendfactor dst
, unsigned chanmask
)
384 /* Src factor is allowed when it does not depend on Dst */
385 static const uint32_t src_allowed
=
386 (1u << PIPE_BLENDFACTOR_ONE
) | (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
387 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
388 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) | (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
389 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) | (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
390 (1u << PIPE_BLENDFACTOR_ZERO
) | (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
392 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) | (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
393 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
395 if (dst
== PIPE_BLENDFACTOR_ONE
&& (src_allowed
& (1u << src
))) {
396 /* Addition is commutative, but floating point addition isn't
397 * associative: subtle changes can be introduced via different
400 * Out-of-order is also non-deterministic, which means that
401 * this breaks OpenGL invariance requirements. So only enable
402 * out-of-order additive blending if explicitly allowed by a
405 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
406 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
407 blend
->commutative_4bit
|= chanmask
;
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
415 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
, unsigned *dst_factor
,
416 unsigned expected_dst
, unsigned replacement_src
)
418 if (*src_factor
== expected_dst
&& *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
419 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
420 *dst_factor
= replacement_src
;
422 /* Commuting the operands requires reversing subtractions. */
423 if (*func
== PIPE_BLEND_SUBTRACT
)
424 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
425 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
426 *func
= PIPE_BLEND_SUBTRACT
;
430 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
431 const struct pipe_blend_state
*state
, unsigned mode
)
433 struct si_context
*sctx
= (struct si_context
*)ctx
;
434 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
435 struct si_pm4_state
*pm4
= &blend
->pm4
;
436 uint32_t sx_mrt_blend_opt
[8] = {0};
437 uint32_t color_control
= 0;
438 bool logicop_enable
= state
->logicop_enable
&& state
->logicop_func
!= PIPE_LOGICOP_COPY
;
443 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
444 blend
->alpha_to_one
= state
->alpha_to_one
;
445 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
446 blend
->logicop_enable
= logicop_enable
;
448 unsigned num_shader_outputs
= state
->max_rt
+ 1; /* estimate */
449 if (blend
->dual_src_blend
)
450 num_shader_outputs
= MAX2(num_shader_outputs
, 2);
452 if (logicop_enable
) {
453 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
455 color_control
|= S_028808_ROP3(0xcc);
458 if (state
->alpha_to_coverage
&& state
->alpha_to_coverage_dither
) {
459 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
460 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
461 S_028B70_ALPHA_TO_MASK_OFFSET0(3) | S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
462 S_028B70_ALPHA_TO_MASK_OFFSET2(0) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
463 S_028B70_OFFSET_ROUND(1));
465 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(2) | S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
468 S_028B70_ALPHA_TO_MASK_OFFSET2(2) | S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
469 S_028B70_OFFSET_ROUND(0));
472 if (state
->alpha_to_coverage
)
473 blend
->need_src_alpha_4bit
|= 0xf;
475 blend
->cb_target_mask
= 0;
476 blend
->cb_target_enabled_4bit
= 0;
478 for (int i
= 0; i
< num_shader_outputs
; i
++) {
479 /* state->rt entries > 0 only written if independent blending */
480 const int j
= state
->independent_blend_enable
? i
: 0;
482 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
483 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
484 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
485 unsigned eqA
= state
->rt
[j
].alpha_func
;
486 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
487 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
489 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
490 unsigned blend_cntl
= 0;
492 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
493 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
495 /* Only set dual source blending for MRT0 to avoid a hang. */
496 if (i
>= 1 && blend
->dual_src_blend
) {
497 /* Vulkan does this for dual source blending. */
499 blend_cntl
|= S_028780_ENABLE(1);
501 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
505 /* Only addition and subtraction equations are supported with
506 * dual source blending.
508 if (blend
->dual_src_blend
&& (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
509 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
510 assert(!"Unsupported equation for dual source blending");
511 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
515 /* cb_render_state will disable unused ones */
516 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
517 if (state
->rt
[j
].colormask
)
518 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
520 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
521 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
525 si_blend_check_commutativity(sctx
->screen
, blend
, eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
526 si_blend_check_commutativity(sctx
->screen
, blend
, eqA
, srcA
, dstA
, 0x8 << (4 * i
));
528 /* Blending optimizations for RB+.
529 * These transformations don't change the behavior.
531 * First, get rid of DST in the blend factors:
532 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
534 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
, PIPE_BLENDFACTOR_DST_COLOR
,
535 PIPE_BLENDFACTOR_SRC_COLOR
);
536 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_COLOR
,
537 PIPE_BLENDFACTOR_SRC_COLOR
);
538 si_blend_remove_dst(&eqA
, &srcA
, &dstA
, PIPE_BLENDFACTOR_DST_ALPHA
,
539 PIPE_BLENDFACTOR_SRC_ALPHA
);
541 /* Look up the ideal settings from tables. */
542 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
543 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
544 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
545 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
547 /* Handle interdependencies. */
548 if (util_blend_factor_uses_dest(srcRGB
, false))
549 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
550 if (util_blend_factor_uses_dest(srcA
, false))
551 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
553 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
554 (dstRGB
== PIPE_BLENDFACTOR_ZERO
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
555 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
556 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
558 /* Set the final value. */
559 sx_mrt_blend_opt
[i
] = S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
560 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
561 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
562 S_028760_ALPHA_SRC_OPT(srcA_opt
) | S_028760_ALPHA_DST_OPT(dstA_opt
) |
563 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
565 /* Set blend state. */
566 blend_cntl
|= S_028780_ENABLE(1);
567 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
568 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
569 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
571 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
572 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
573 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
574 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
575 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
577 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
579 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
581 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
)
582 blend
->dcc_msaa_corruption_4bit
|= 0xfu
<< (i
* 4);
584 /* This is only important for formats without alpha. */
585 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
586 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
587 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
588 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
|| dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
589 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
592 if (sctx
->chip_class
>= GFX8
&& sctx
->chip_class
<= GFX10
&& logicop_enable
)
593 blend
->dcc_msaa_corruption_4bit
|= blend
->cb_target_enabled_4bit
;
595 if (blend
->cb_target_mask
) {
596 color_control
|= S_028808_MODE(mode
);
598 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
601 if (sctx
->screen
->info
.rbplus_allowed
) {
602 /* Disable RB+ blend optimizations for dual source blending.
605 if (blend
->dual_src_blend
) {
606 for (int i
= 0; i
< num_shader_outputs
; i
++) {
607 sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
608 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
612 for (int i
= 0; i
< num_shader_outputs
; i
++)
613 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4, sx_mrt_blend_opt
[i
]);
615 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
616 if (blend
->dual_src_blend
|| logicop_enable
|| mode
== V_028808_CB_RESOLVE
)
617 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
620 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
624 static void *si_create_blend_state(struct pipe_context
*ctx
, const struct pipe_blend_state
*state
)
626 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
629 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
631 struct si_context
*sctx
= (struct si_context
*)ctx
;
632 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
633 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
636 blend
= (struct si_state_blend
*)sctx
->noop_blend
;
638 si_pm4_bind_state(sctx
, blend
, blend
);
640 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
641 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
642 (old_blend
->dcc_msaa_corruption_4bit
!= blend
->dcc_msaa_corruption_4bit
&&
643 sctx
->framebuffer
.nr_samples
>= 2 && sctx
->screen
->dcc_msaa_allowed
))
644 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
646 if (old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
647 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
648 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
649 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
650 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
651 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
652 sctx
->do_update_shaders
= true;
654 if (sctx
->screen
->dpbb_allowed
&&
655 (old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
656 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
657 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
658 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
660 if (sctx
->screen
->has_out_of_order_rast
&&
661 ((old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
662 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
663 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
664 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
665 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
668 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
670 struct si_context
*sctx
= (struct si_context
*)ctx
;
672 if (sctx
->queued
.named
.blend
== state
)
673 si_bind_blend_state(ctx
, sctx
->noop_blend
);
675 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
678 static void si_set_blend_color(struct pipe_context
*ctx
, const struct pipe_blend_color
*state
)
680 struct si_context
*sctx
= (struct si_context
*)ctx
;
681 static const struct pipe_blend_color zeros
;
683 sctx
->blend_color
.state
= *state
;
684 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
685 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
688 static void si_emit_blend_color(struct si_context
*sctx
)
690 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
692 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
693 radeon_emit_array(cs
, (uint32_t *)sctx
->blend_color
.state
.color
, 4);
700 static void si_set_clip_state(struct pipe_context
*ctx
, const struct pipe_clip_state
*state
)
702 struct si_context
*sctx
= (struct si_context
*)ctx
;
703 struct pipe_constant_buffer cb
;
704 static const struct pipe_clip_state zeros
;
706 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
709 sctx
->clip_state
.state
= *state
;
710 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
711 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
714 cb
.user_buffer
= state
->ucp
;
715 cb
.buffer_offset
= 0;
716 cb
.buffer_size
= 4 * 4 * 8;
717 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
718 pipe_resource_reference(&cb
.buffer
, NULL
);
721 static void si_emit_clip_state(struct si_context
*sctx
)
723 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
725 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6 * 4);
726 radeon_emit_array(cs
, (uint32_t *)sctx
->clip_state
.state
.ucp
, 6 * 4);
729 static void si_emit_clip_regs(struct si_context
*sctx
)
731 struct si_shader
*vs
= si_get_vs_state(sctx
);
732 struct si_shader_selector
*vs_sel
= vs
->selector
;
733 struct si_shader_info
*info
= &vs_sel
->info
;
734 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
735 unsigned window_space
= info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
736 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
737 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
738 unsigned culldist_mask
= vs_sel
->culldist_mask
;
741 if (vs
->key
.opt
.clip_disable
) {
742 assert(!info
->culldist_writemask
);
746 total_mask
= clipdist_mask
| culldist_mask
;
748 /* Clip distances on points have no effect, so need to be implemented
749 * as cull distances. This applies for the clipvertex case as well.
751 * Setting this for primitives other than points should have no adverse
754 clipdist_mask
&= rs
->clip_plane_enable
;
755 culldist_mask
|= clipdist_mask
;
757 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
758 unsigned pa_cl_cntl
= S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
759 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
760 S_02881C_BYPASS_VTX_RATE_COMBINER(sctx
->chip_class
>= GFX10_3
) |
761 S_02881C_BYPASS_PRIM_RATE_COMBINER(sctx
->chip_class
>= GFX10_3
) |
762 clipdist_mask
| (culldist_mask
<< 8);
764 if (sctx
->chip_class
>= GFX10
) {
765 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
766 SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
, pa_cl_cntl
,
767 ~SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
769 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
, SI_TRACKED_PA_CL_VS_OUT_CNTL__CL
,
770 vs_sel
->pa_cl_vs_out_cntl
| pa_cl_cntl
);
772 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
, SI_TRACKED_PA_CL_CLIP_CNTL
,
773 rs
->pa_cl_clip_cntl
| ucp_mask
| S_028810_CLIP_DISABLE(window_space
));
775 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
776 sctx
->context_roll
= true;
780 * inferred state between framebuffer and rasterizer
782 static void si_update_poly_offset_state(struct si_context
*sctx
)
784 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
786 if (!rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
787 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
791 /* Use the user format, not db_render_format, so that the polygon
792 * offset behaves as expected by applications.
794 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
795 case PIPE_FORMAT_Z16_UNORM
:
796 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
798 default: /* 24-bit */
799 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
801 case PIPE_FORMAT_Z32_FLOAT
:
802 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
803 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
812 static uint32_t si_translate_fill(uint32_t func
)
815 case PIPE_POLYGON_MODE_FILL
:
816 return V_028814_X_DRAW_TRIANGLES
;
817 case PIPE_POLYGON_MODE_LINE
:
818 return V_028814_X_DRAW_LINES
;
819 case PIPE_POLYGON_MODE_POINT
:
820 return V_028814_X_DRAW_POINTS
;
823 return V_028814_X_DRAW_POINTS
;
827 static void *si_create_rs_state(struct pipe_context
*ctx
, const struct pipe_rasterizer_state
*state
)
829 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
830 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
831 struct si_pm4_state
*pm4
= &rs
->pm4
;
833 float psize_min
, psize_max
;
839 if (!state
->front_ccw
) {
840 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
841 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_BACK
);
843 rs
->cull_back
= !!(state
->cull_face
& PIPE_FACE_FRONT
);
844 rs
->cull_front
= !!(state
->cull_face
& PIPE_FACE_BACK
);
846 rs
->depth_clamp_any
= !state
->depth_clip_near
|| !state
->depth_clip_far
;
847 rs
->provoking_vertex_first
= state
->flatshade_first
;
848 rs
->scissor_enable
= state
->scissor
;
849 rs
->clip_halfz
= state
->clip_halfz
;
850 rs
->two_side
= state
->light_twoside
;
851 rs
->multisample_enable
= state
->multisample
;
852 rs
->force_persample_interp
= state
->force_persample_interp
;
853 rs
->clip_plane_enable
= state
->clip_plane_enable
;
854 rs
->half_pixel_center
= state
->half_pixel_center
;
855 rs
->line_stipple_enable
= state
->line_stipple_enable
;
856 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
857 rs
->line_smooth
= state
->line_smooth
;
858 rs
->line_width
= state
->line_width
;
859 rs
->poly_smooth
= state
->poly_smooth
;
860 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
|| state
->offset_tri
;
861 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
862 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
863 rs
->flatshade
= state
->flatshade
;
864 rs
->flatshade_first
= state
->flatshade_first
;
865 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
866 rs
->rasterizer_discard
= state
->rasterizer_discard
;
867 rs
->polygon_mode_enabled
=
868 (state
->fill_front
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
869 (state
->fill_back
!= PIPE_POLYGON_MODE_FILL
&& !(state
->cull_face
& PIPE_FACE_BACK
));
870 rs
->polygon_mode_is_lines
=
871 (state
->fill_front
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_FRONT
)) ||
872 (state
->fill_back
== PIPE_POLYGON_MODE_LINE
&& !(state
->cull_face
& PIPE_FACE_BACK
));
873 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
874 ? S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
875 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
)
877 rs
->pa_cl_clip_cntl
= S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
878 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
879 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
880 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
881 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
884 pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
885 S_0286D4_FLAT_SHADE_ENA(1) | S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
886 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
887 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
888 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
889 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
890 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
892 /* point size 12.4 fixed point */
893 tmp
= (unsigned)(state
->point_size
* 8.0);
894 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
896 if (state
->point_size_per_vertex
) {
897 psize_min
= util_get_min_point_size(state
);
898 psize_max
= SI_MAX_POINT_SIZE
;
900 /* Force the point size to be as if the vertex output was disabled. */
901 psize_min
= state
->point_size
;
902 psize_max
= state
->point_size
;
904 rs
->max_point_size
= psize_max
;
906 /* Divide by two, because 0.5 = 1 pixel. */
907 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
908 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/ 2)) |
909 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/ 2)));
911 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
912 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/ 2)));
914 pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
915 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
916 S_028A48_MSAA_ENABLE(state
->multisample
|| state
->poly_smooth
|| state
->line_smooth
) |
917 S_028A48_VPORT_SCISSOR_ENABLE(1) |
918 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
920 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
921 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
922 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
923 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
924 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
925 S_028814_FACE(!state
->front_ccw
) |
926 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
927 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
928 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
929 S_028814_POLY_MODE(rs
->polygon_mode_enabled
) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
933 if (!rs
->uses_poly_offset
)
936 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
937 if (!rs
->pm4_poly_offset
) {
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i
= 0; i
< 3; i
++) {
944 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
945 float offset_units
= state
->offset_units
;
946 float offset_scale
= state
->offset_scale
* 16.0f
;
947 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
949 if (!state
->offset_units_unscaled
) {
951 case 0: /* 16-bit zbuffer */
952 offset_units
*= 4.0f
;
953 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
955 case 1: /* 24-bit zbuffer */
956 offset_units
*= 2.0f
;
957 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
959 case 2: /* 32-bit zbuffer */
960 offset_units
*= 1.0f
;
961 pa_su_poly_offset_db_fmt_cntl
=
962 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) | S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
967 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
, fui(offset_scale
));
968 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
, fui(offset_units
));
969 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
, fui(offset_scale
));
970 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
, fui(offset_units
));
971 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
, pa_su_poly_offset_db_fmt_cntl
);
977 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
979 struct si_context
*sctx
= (struct si_context
*)ctx
;
980 struct si_state_rasterizer
*old_rs
= (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
981 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
984 rs
= (struct si_state_rasterizer
*)sctx
->discard_rasterizer_state
;
986 if (old_rs
->multisample_enable
!= rs
->multisample_enable
) {
987 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
989 /* Update the small primitive filter workaround if necessary. */
990 if (sctx
->screen
->info
.has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1)
991 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
994 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
995 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
997 si_pm4_bind_state(sctx
, rasterizer
, rs
);
998 si_update_poly_offset_state(sctx
);
1000 if (old_rs
->scissor_enable
!= rs
->scissor_enable
)
1001 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1003 if (old_rs
->line_width
!= rs
->line_width
|| old_rs
->max_point_size
!= rs
->max_point_size
||
1004 old_rs
->half_pixel_center
!= rs
->half_pixel_center
)
1005 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1007 if (old_rs
->clip_halfz
!= rs
->clip_halfz
)
1008 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1010 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1011 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1012 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1014 if (old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1015 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1016 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1017 old_rs
->flatshade
!= rs
->flatshade
|| old_rs
->two_side
!= rs
->two_side
||
1018 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1019 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1020 old_rs
->poly_smooth
!= rs
->poly_smooth
|| old_rs
->line_smooth
!= rs
->line_smooth
||
1021 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1022 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1023 sctx
->do_update_shaders
= true;
1026 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1028 struct si_context
*sctx
= (struct si_context
*)ctx
;
1029 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1031 if (sctx
->queued
.named
.rasterizer
== state
)
1032 si_bind_rs_state(ctx
, sctx
->discard_rasterizer_state
);
1034 FREE(rs
->pm4_poly_offset
);
1035 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1039 * infeered state between dsa and stencil ref
1041 static void si_emit_stencil_ref(struct si_context
*sctx
)
1043 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1044 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1045 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1047 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1048 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1049 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1050 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) | S_028430_STENCILOPVAL(1));
1051 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1052 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1053 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1054 S_028434_STENCILOPVAL_BF(1));
1057 static void si_set_stencil_ref(struct pipe_context
*ctx
, const struct pipe_stencil_ref
*state
)
1059 struct si_context
*sctx
= (struct si_context
*)ctx
;
1061 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1064 sctx
->stencil_ref
.state
= *state
;
1065 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1072 static uint32_t si_translate_stencil_op(int s_op
)
1075 case PIPE_STENCIL_OP_KEEP
:
1076 return V_02842C_STENCIL_KEEP
;
1077 case PIPE_STENCIL_OP_ZERO
:
1078 return V_02842C_STENCIL_ZERO
;
1079 case PIPE_STENCIL_OP_REPLACE
:
1080 return V_02842C_STENCIL_REPLACE_TEST
;
1081 case PIPE_STENCIL_OP_INCR
:
1082 return V_02842C_STENCIL_ADD_CLAMP
;
1083 case PIPE_STENCIL_OP_DECR
:
1084 return V_02842C_STENCIL_SUB_CLAMP
;
1085 case PIPE_STENCIL_OP_INCR_WRAP
:
1086 return V_02842C_STENCIL_ADD_WRAP
;
1087 case PIPE_STENCIL_OP_DECR_WRAP
:
1088 return V_02842C_STENCIL_SUB_WRAP
;
1089 case PIPE_STENCIL_OP_INVERT
:
1090 return V_02842C_STENCIL_INVERT
;
1092 PRINT_ERR("Unknown stencil op %d", s_op
);
1099 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1101 return s
->enabled
&& s
->writemask
&&
1102 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
|| s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1103 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1106 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1108 /* REPLACE is normally order invariant, except when the stencil
1109 * reference value is written by the fragment shader. Tracking this
1110 * interaction does not seem worth the effort, so be conservative. */
1111 return op
!= PIPE_STENCIL_OP_INCR
&& op
!= PIPE_STENCIL_OP_DECR
&& op
!= PIPE_STENCIL_OP_REPLACE
;
1114 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1115 * invariant in the sense that the set of passing fragments as well as the
1116 * final stencil buffer result does not depend on the order of fragments. */
1117 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1119 return !state
->enabled
|| !state
->writemask
||
1120 /* The following assumes that Z writes are disabled. */
1121 (state
->func
== PIPE_FUNC_ALWAYS
&& si_order_invariant_stencil_op(state
->zpass_op
) &&
1122 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1123 (state
->func
== PIPE_FUNC_NEVER
&& si_order_invariant_stencil_op(state
->fail_op
));
1126 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1127 const struct pipe_depth_stencil_alpha_state
*state
)
1129 struct si_context
*sctx
= (struct si_context
*)ctx
;
1130 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1131 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1132 unsigned db_depth_control
;
1133 uint32_t db_stencil_control
= 0;
1139 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1140 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1141 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1142 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1145 S_028800_Z_ENABLE(state
->depth
.enabled
) | S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1146 S_028800_ZFUNC(state
->depth
.func
) | S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1149 if (state
->stencil
[0].enabled
) {
1150 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1151 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1152 db_stencil_control
|=
1153 S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1154 db_stencil_control
|=
1155 S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1156 db_stencil_control
|=
1157 S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1159 if (state
->stencil
[1].enabled
) {
1160 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1161 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1162 db_stencil_control
|=
1163 S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1164 db_stencil_control
|=
1165 S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1166 db_stencil_control
|=
1167 S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1172 if (state
->alpha
.enabled
) {
1173 dsa
->alpha_func
= state
->alpha
.func
;
1175 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+ SI_SGPR_ALPHA_REF
* 4,
1176 fui(state
->alpha
.ref_value
));
1178 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1181 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1182 if (state
->stencil
[0].enabled
)
1183 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1184 if (state
->depth
.bounds_test
) {
1185 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1186 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1189 dsa
->depth_enabled
= state
->depth
.enabled
;
1190 dsa
->depth_write_enabled
= state
->depth
.enabled
&& state
->depth
.writemask
;
1191 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1192 dsa
->stencil_write_enabled
=
1193 state
->stencil
[0].enabled
&&
1194 (si_dsa_writes_stencil(&state
->stencil
[0]) || si_dsa_writes_stencil(&state
->stencil
[1]));
1195 dsa
->db_can_write
= dsa
->depth_write_enabled
|| dsa
->stencil_write_enabled
;
1197 bool zfunc_is_ordered
=
1198 state
->depth
.func
== PIPE_FUNC_NEVER
|| state
->depth
.func
== PIPE_FUNC_LESS
||
1199 state
->depth
.func
== PIPE_FUNC_LEQUAL
|| state
->depth
.func
== PIPE_FUNC_GREATER
||
1200 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1202 bool nozwrite_and_order_invariant_stencil
=
1203 !dsa
->db_can_write
||
1204 (!dsa
->depth_write_enabled
&& si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1205 si_order_invariant_stencil_state(&state
->stencil
[1]));
1207 dsa
->order_invariance
[1].zs
=
1208 nozwrite_and_order_invariant_stencil
|| (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1209 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1211 dsa
->order_invariance
[1].pass_set
=
1212 nozwrite_and_order_invariant_stencil
||
1213 (!dsa
->stencil_write_enabled
&&
1214 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
));
1215 dsa
->order_invariance
[0].pass_set
=
1216 !dsa
->depth_write_enabled
||
1217 (state
->depth
.func
== PIPE_FUNC_ALWAYS
|| state
->depth
.func
== PIPE_FUNC_NEVER
);
1219 dsa
->order_invariance
[1].pass_last
= sctx
->screen
->assume_no_z_fights
&&
1220 !dsa
->stencil_write_enabled
&& dsa
->depth_write_enabled
&&
1222 dsa
->order_invariance
[0].pass_last
=
1223 sctx
->screen
->assume_no_z_fights
&& dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1228 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1230 struct si_context
*sctx
= (struct si_context
*)ctx
;
1231 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1232 struct si_state_dsa
*dsa
= state
;
1235 dsa
= (struct si_state_dsa
*)sctx
->noop_dsa
;
1237 si_pm4_bind_state(sctx
, dsa
, dsa
);
1239 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1240 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1241 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1242 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1245 if (old_dsa
->alpha_func
!= dsa
->alpha_func
)
1246 sctx
->do_update_shaders
= true;
1248 if (sctx
->screen
->dpbb_allowed
&& ((old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1249 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1250 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1251 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1253 if (sctx
->screen
->has_out_of_order_rast
&&
1254 (memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1255 sizeof(old_dsa
->order_invariance
))))
1256 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1259 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1261 struct si_context
*sctx
= (struct si_context
*)ctx
;
1263 if (sctx
->queued
.named
.dsa
== state
)
1264 si_bind_dsa_state(ctx
, sctx
->noop_dsa
);
1266 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1269 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1271 struct pipe_depth_stencil_alpha_state dsa
= {};
1273 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1276 /* DB RENDER STATE */
1278 static void si_set_active_query_state(struct pipe_context
*ctx
, bool enable
)
1280 struct si_context
*sctx
= (struct si_context
*)ctx
;
1282 /* Pipeline stat & streamout queries. */
1284 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1285 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1287 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1288 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1291 /* Occlusion queries. */
1292 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1293 sctx
->occlusion_queries_disabled
= !enable
;
1294 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1298 void si_set_occlusion_query_state(struct si_context
*sctx
, bool old_perfect_enable
)
1300 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1302 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1304 if (perfect_enable
!= old_perfect_enable
)
1305 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1308 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1310 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1312 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1313 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1315 st
->saved_ssbo_writable_mask
= 0;
1317 for (unsigned i
= 0; i
< 3; i
++) {
1318 if (sctx
->const_and_shader_buffers
[PIPE_SHADER_COMPUTE
].writable_mask
&
1319 (1u << si_get_shaderbuf_slot(i
)))
1320 st
->saved_ssbo_writable_mask
|= 1 << i
;
1324 void si_restore_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1326 sctx
->b
.bind_compute_state(&sctx
->b
, st
->saved_compute
);
1328 sctx
->b
.set_constant_buffer(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1329 pipe_resource_reference(&st
->saved_const0
.buffer
, NULL
);
1331 sctx
->b
.set_shader_buffers(&sctx
->b
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
,
1332 st
->saved_ssbo_writable_mask
);
1333 for (unsigned i
= 0; i
< 3; ++i
)
1334 pipe_resource_reference(&st
->saved_ssbo
[i
].buffer
, NULL
);
1337 static void si_emit_db_render_state(struct si_context
*sctx
)
1339 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1340 unsigned db_shader_control
, db_render_control
, db_count_control
;
1341 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1343 /* DB_RENDER_CONTROL */
1344 if (sctx
->dbcb_depth_copy_enabled
|| sctx
->dbcb_stencil_copy_enabled
) {
1345 db_render_control
= S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1346 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1347 S_028000_COPY_CENTROID(1) | S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1348 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1349 db_render_control
= S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1350 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1352 db_render_control
= S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1353 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1356 /* DB_COUNT_CONTROL (occlusion queries) */
1357 if (sctx
->num_occlusion_queries
> 0 && !sctx
->occlusion_queries_disabled
) {
1358 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1359 bool gfx10_perfect
= sctx
->chip_class
>= GFX10
&& perfect
;
1361 if (sctx
->chip_class
>= GFX7
) {
1362 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1364 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1365 S_028004_DISABLE_CONSERVATIVE_ZPASS_COUNTS(gfx10_perfect
) |
1366 S_028004_SAMPLE_RATE(log_sample_rate
) | S_028004_ZPASS_ENABLE(1) |
1367 S_028004_SLICE_EVEN_ENABLE(1) | S_028004_SLICE_ODD_ENABLE(1);
1369 db_count_control
= S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1370 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1373 /* Disable occlusion queries. */
1374 if (sctx
->chip_class
>= GFX7
) {
1375 db_count_control
= 0;
1377 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1381 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
, SI_TRACKED_DB_RENDER_CONTROL
,
1382 db_render_control
, db_count_control
);
1384 /* DB_RENDER_OVERRIDE2 */
1385 radeon_opt_set_context_reg(
1386 sctx
, R_028010_DB_RENDER_OVERRIDE2
, SI_TRACKED_DB_RENDER_OVERRIDE2
,
1387 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1388 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1389 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4) |
1390 S_028010_CENTROID_COMPUTATION_MODE(sctx
->chip_class
>= GFX10_3
? 2 : 0));
1392 db_shader_control
= sctx
->ps_db_shader_control
;
1394 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1395 if (sctx
->chip_class
== GFX6
&& sctx
->smoothing_enabled
) {
1396 db_shader_control
&= C_02880C_Z_ORDER
;
1397 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1400 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1401 if (!rs
->multisample_enable
)
1402 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1404 if (sctx
->screen
->info
.has_rbplus
&& !sctx
->screen
->info
.rbplus_allowed
)
1405 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1407 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
, SI_TRACKED_DB_SHADER_CONTROL
,
1410 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1411 sctx
->context_roll
= true;
1415 * format translation
1417 static uint32_t si_translate_colorformat(enum chip_class chip_class
,
1418 enum pipe_format format
)
1420 const struct util_format_description
*desc
= util_format_description(format
);
1422 return V_028C70_COLOR_INVALID
;
1424 #define HAS_SIZE(x, y, z, w) \
1425 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1426 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1428 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1429 return V_028C70_COLOR_10_11_11
;
1431 if (chip_class
>= GFX10_3
&&
1432 format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) /* isn't plain */
1433 return V_028C70_COLOR_5_9_9_9
;
1435 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1436 return V_028C70_COLOR_INVALID
;
1438 /* hw cannot support mixed formats (except depth/stencil, since
1439 * stencil is not written to). */
1440 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1441 return V_028C70_COLOR_INVALID
;
1443 switch (desc
->nr_channels
) {
1445 switch (desc
->channel
[0].size
) {
1447 return V_028C70_COLOR_8
;
1449 return V_028C70_COLOR_16
;
1451 return V_028C70_COLOR_32
;
1455 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1456 switch (desc
->channel
[0].size
) {
1458 return V_028C70_COLOR_8_8
;
1460 return V_028C70_COLOR_16_16
;
1462 return V_028C70_COLOR_32_32
;
1464 } else if (HAS_SIZE(8, 24, 0, 0)) {
1465 return V_028C70_COLOR_24_8
;
1466 } else if (HAS_SIZE(24, 8, 0, 0)) {
1467 return V_028C70_COLOR_8_24
;
1471 if (HAS_SIZE(5, 6, 5, 0)) {
1472 return V_028C70_COLOR_5_6_5
;
1473 } else if (HAS_SIZE(32, 8, 24, 0)) {
1474 return V_028C70_COLOR_X24_8_32_FLOAT
;
1478 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1479 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1480 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1481 switch (desc
->channel
[0].size
) {
1483 return V_028C70_COLOR_4_4_4_4
;
1485 return V_028C70_COLOR_8_8_8_8
;
1487 return V_028C70_COLOR_16_16_16_16
;
1489 return V_028C70_COLOR_32_32_32_32
;
1491 } else if (HAS_SIZE(5, 5, 5, 1)) {
1492 return V_028C70_COLOR_1_5_5_5
;
1493 } else if (HAS_SIZE(1, 5, 5, 5)) {
1494 return V_028C70_COLOR_5_5_5_1
;
1495 } else if (HAS_SIZE(10, 10, 10, 2)) {
1496 return V_028C70_COLOR_2_10_10_10
;
1500 return V_028C70_COLOR_INVALID
;
1503 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1505 if (SI_BIG_ENDIAN
) {
1506 switch (colorformat
) {
1507 /* 8-bit buffers. */
1508 case V_028C70_COLOR_8
:
1509 return V_028C70_ENDIAN_NONE
;
1511 /* 16-bit buffers. */
1512 case V_028C70_COLOR_5_6_5
:
1513 case V_028C70_COLOR_1_5_5_5
:
1514 case V_028C70_COLOR_4_4_4_4
:
1515 case V_028C70_COLOR_16
:
1516 case V_028C70_COLOR_8_8
:
1517 return V_028C70_ENDIAN_8IN16
;
1519 /* 32-bit buffers. */
1520 case V_028C70_COLOR_8_8_8_8
:
1521 case V_028C70_COLOR_2_10_10_10
:
1522 case V_028C70_COLOR_8_24
:
1523 case V_028C70_COLOR_24_8
:
1524 case V_028C70_COLOR_16_16
:
1525 return V_028C70_ENDIAN_8IN32
;
1527 /* 64-bit buffers. */
1528 case V_028C70_COLOR_16_16_16_16
:
1529 return V_028C70_ENDIAN_8IN16
;
1531 case V_028C70_COLOR_32_32
:
1532 return V_028C70_ENDIAN_8IN32
;
1534 /* 128-bit buffers. */
1535 case V_028C70_COLOR_32_32_32_32
:
1536 return V_028C70_ENDIAN_8IN32
;
1538 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1541 return V_028C70_ENDIAN_NONE
;
1545 static uint32_t si_translate_dbformat(enum pipe_format format
)
1548 case PIPE_FORMAT_Z16_UNORM
:
1549 return V_028040_Z_16
;
1550 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1551 case PIPE_FORMAT_X8Z24_UNORM
:
1552 case PIPE_FORMAT_Z24X8_UNORM
:
1553 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1554 return V_028040_Z_24
; /* deprecated on AMD GCN */
1555 case PIPE_FORMAT_Z32_FLOAT
:
1556 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1557 return V_028040_Z_32_FLOAT
;
1559 return V_028040_Z_INVALID
;
1564 * Texture translation
1567 static uint32_t si_translate_texformat(struct pipe_screen
*screen
, enum pipe_format format
,
1568 const struct util_format_description
*desc
,
1571 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1572 bool uniform
= true;
1575 assert(sscreen
->info
.chip_class
<= GFX9
);
1577 /* Colorspace (return non-RGB formats directly). */
1578 switch (desc
->colorspace
) {
1579 /* Depth stencil formats */
1580 case UTIL_FORMAT_COLORSPACE_ZS
:
1582 case PIPE_FORMAT_Z16_UNORM
:
1583 return V_008F14_IMG_DATA_FORMAT_16
;
1584 case PIPE_FORMAT_X24S8_UINT
:
1585 case PIPE_FORMAT_S8X24_UINT
:
1587 * Implemented as an 8_8_8_8 data format to fix texture
1588 * gathers in stencil sampling. This affects at least
1589 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1591 if (sscreen
->info
.chip_class
<= GFX8
)
1592 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1594 if (format
== PIPE_FORMAT_X24S8_UINT
)
1595 return V_008F14_IMG_DATA_FORMAT_8_24
;
1597 return V_008F14_IMG_DATA_FORMAT_24_8
;
1598 case PIPE_FORMAT_Z24X8_UNORM
:
1599 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1600 return V_008F14_IMG_DATA_FORMAT_8_24
;
1601 case PIPE_FORMAT_X8Z24_UNORM
:
1602 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1603 return V_008F14_IMG_DATA_FORMAT_24_8
;
1604 case PIPE_FORMAT_S8_UINT
:
1605 return V_008F14_IMG_DATA_FORMAT_8
;
1606 case PIPE_FORMAT_Z32_FLOAT
:
1607 return V_008F14_IMG_DATA_FORMAT_32
;
1608 case PIPE_FORMAT_X32_S8X24_UINT
:
1609 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1610 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1615 case UTIL_FORMAT_COLORSPACE_YUV
:
1616 goto out_unknown
; /* TODO */
1618 case UTIL_FORMAT_COLORSPACE_SRGB
:
1619 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1627 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1628 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1632 case PIPE_FORMAT_RGTC1_SNORM
:
1633 case PIPE_FORMAT_LATC1_SNORM
:
1634 case PIPE_FORMAT_RGTC1_UNORM
:
1635 case PIPE_FORMAT_LATC1_UNORM
:
1636 return V_008F14_IMG_DATA_FORMAT_BC4
;
1637 case PIPE_FORMAT_RGTC2_SNORM
:
1638 case PIPE_FORMAT_LATC2_SNORM
:
1639 case PIPE_FORMAT_RGTC2_UNORM
:
1640 case PIPE_FORMAT_LATC2_UNORM
:
1641 return V_008F14_IMG_DATA_FORMAT_BC5
;
1647 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1648 (sscreen
->info
.family
== CHIP_STONEY
|| sscreen
->info
.family
== CHIP_VEGA10
||
1649 sscreen
->info
.family
== CHIP_RAVEN
|| sscreen
->info
.family
== CHIP_RAVEN2
)) {
1651 case PIPE_FORMAT_ETC1_RGB8
:
1652 case PIPE_FORMAT_ETC2_RGB8
:
1653 case PIPE_FORMAT_ETC2_SRGB8
:
1654 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1655 case PIPE_FORMAT_ETC2_RGB8A1
:
1656 case PIPE_FORMAT_ETC2_SRGB8A1
:
1657 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1658 case PIPE_FORMAT_ETC2_RGBA8
:
1659 case PIPE_FORMAT_ETC2_SRGBA8
:
1660 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1661 case PIPE_FORMAT_ETC2_R11_UNORM
:
1662 case PIPE_FORMAT_ETC2_R11_SNORM
:
1663 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1664 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1665 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1672 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1673 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1677 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1678 case PIPE_FORMAT_BPTC_SRGBA
:
1679 return V_008F14_IMG_DATA_FORMAT_BC7
;
1680 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1681 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1682 return V_008F14_IMG_DATA_FORMAT_BC6
;
1688 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1690 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1691 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1692 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1693 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1694 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1695 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1701 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1702 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1706 case PIPE_FORMAT_DXT1_RGB
:
1707 case PIPE_FORMAT_DXT1_RGBA
:
1708 case PIPE_FORMAT_DXT1_SRGB
:
1709 case PIPE_FORMAT_DXT1_SRGBA
:
1710 return V_008F14_IMG_DATA_FORMAT_BC1
;
1711 case PIPE_FORMAT_DXT3_RGBA
:
1712 case PIPE_FORMAT_DXT3_SRGBA
:
1713 return V_008F14_IMG_DATA_FORMAT_BC2
;
1714 case PIPE_FORMAT_DXT5_RGBA
:
1715 case PIPE_FORMAT_DXT5_SRGBA
:
1716 return V_008F14_IMG_DATA_FORMAT_BC3
;
1722 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1723 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1724 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1725 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1728 /* R8G8Bx_SNORM - TODO CxV8U8 */
1730 /* hw cannot support mixed formats (except depth/stencil, since only
1732 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1735 /* See whether the components are of the same size. */
1736 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1737 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1740 /* Non-uniform formats. */
1742 switch (desc
->nr_channels
) {
1744 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 6 &&
1745 desc
->channel
[2].size
== 5) {
1746 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1750 if (desc
->channel
[0].size
== 5 && desc
->channel
[1].size
== 5 &&
1751 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 1) {
1752 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1754 if (desc
->channel
[0].size
== 1 && desc
->channel
[1].size
== 5 &&
1755 desc
->channel
[2].size
== 5 && desc
->channel
[3].size
== 5) {
1756 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1758 if (desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1759 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2) {
1760 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1767 if (first_non_void
< 0 || first_non_void
> 3)
1770 /* uniform formats */
1771 switch (desc
->channel
[first_non_void
].size
) {
1773 switch (desc
->nr_channels
) {
1774 #if 0 /* Not supported for render targets */
1776 return V_008F14_IMG_DATA_FORMAT_4_4
;
1779 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1783 switch (desc
->nr_channels
) {
1785 return V_008F14_IMG_DATA_FORMAT_8
;
1787 return V_008F14_IMG_DATA_FORMAT_8_8
;
1789 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1793 switch (desc
->nr_channels
) {
1795 return V_008F14_IMG_DATA_FORMAT_16
;
1797 return V_008F14_IMG_DATA_FORMAT_16_16
;
1799 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1803 switch (desc
->nr_channels
) {
1805 return V_008F14_IMG_DATA_FORMAT_32
;
1807 return V_008F14_IMG_DATA_FORMAT_32_32
;
1808 #if 0 /* Not supported for render targets */
1810 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1813 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1821 static unsigned si_tex_wrap(unsigned wrap
)
1825 case PIPE_TEX_WRAP_REPEAT
:
1826 return V_008F30_SQ_TEX_WRAP
;
1827 case PIPE_TEX_WRAP_CLAMP
:
1828 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1829 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1830 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1831 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1832 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1833 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1834 return V_008F30_SQ_TEX_MIRROR
;
1835 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1836 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1837 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1838 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1839 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1840 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1844 static unsigned si_tex_mipfilter(unsigned filter
)
1847 case PIPE_TEX_MIPFILTER_NEAREST
:
1848 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1849 case PIPE_TEX_MIPFILTER_LINEAR
:
1850 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1852 case PIPE_TEX_MIPFILTER_NONE
:
1853 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1857 static unsigned si_tex_compare(unsigned compare
)
1861 case PIPE_FUNC_NEVER
:
1862 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1863 case PIPE_FUNC_LESS
:
1864 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1865 case PIPE_FUNC_EQUAL
:
1866 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1867 case PIPE_FUNC_LEQUAL
:
1868 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1869 case PIPE_FUNC_GREATER
:
1870 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1871 case PIPE_FUNC_NOTEQUAL
:
1872 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1873 case PIPE_FUNC_GEQUAL
:
1874 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1875 case PIPE_FUNC_ALWAYS
:
1876 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1880 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
, unsigned view_target
,
1881 unsigned nr_samples
)
1883 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1885 if (view_target
== PIPE_TEXTURE_CUBE
|| view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1886 res_target
= view_target
;
1887 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1888 else if (res_target
== PIPE_TEXTURE_CUBE
|| res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1889 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1891 /* GFX9 allocates 1D textures as 2D. */
1892 if ((res_target
== PIPE_TEXTURE_1D
|| res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1893 sscreen
->info
.chip_class
== GFX9
&&
1894 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1895 if (res_target
== PIPE_TEXTURE_1D
)
1896 res_target
= PIPE_TEXTURE_2D
;
1898 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1901 switch (res_target
) {
1903 case PIPE_TEXTURE_1D
:
1904 return V_008F1C_SQ_RSRC_IMG_1D
;
1905 case PIPE_TEXTURE_1D_ARRAY
:
1906 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1907 case PIPE_TEXTURE_2D
:
1908 case PIPE_TEXTURE_RECT
:
1909 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
: V_008F1C_SQ_RSRC_IMG_2D
;
1910 case PIPE_TEXTURE_2D_ARRAY
:
1911 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1912 case PIPE_TEXTURE_3D
:
1913 return V_008F1C_SQ_RSRC_IMG_3D
;
1914 case PIPE_TEXTURE_CUBE
:
1915 case PIPE_TEXTURE_CUBE_ARRAY
:
1916 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1921 * Format support testing
1924 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1926 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1928 if (sscreen
->info
.chip_class
>= GFX10
) {
1929 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
1930 if (!fmt
->img_format
|| fmt
->buffers_only
)
1935 const struct util_format_description
*desc
= util_format_description(format
);
1939 return si_translate_texformat(screen
, format
, desc
,
1940 util_format_get_first_non_void_channel(format
)) != ~0U;
1943 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1944 const struct util_format_description
*desc
,
1949 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
1951 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1952 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1954 assert(first_non_void
>= 0);
1956 if (desc
->nr_channels
== 4 && desc
->channel
[0].size
== 10 && desc
->channel
[1].size
== 10 &&
1957 desc
->channel
[2].size
== 10 && desc
->channel
[3].size
== 2)
1958 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1960 /* See whether the components are of the same size. */
1961 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1962 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1963 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1966 switch (desc
->channel
[first_non_void
].size
) {
1968 switch (desc
->nr_channels
) {
1970 case 3: /* 3 loads */
1971 return V_008F0C_BUF_DATA_FORMAT_8
;
1973 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1975 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1979 switch (desc
->nr_channels
) {
1981 case 3: /* 3 loads */
1982 return V_008F0C_BUF_DATA_FORMAT_16
;
1984 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1986 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1990 switch (desc
->nr_channels
) {
1992 return V_008F0C_BUF_DATA_FORMAT_32
;
1994 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1996 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1998 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2002 /* Legacy double formats. */
2003 switch (desc
->nr_channels
) {
2004 case 1: /* 1 load */
2005 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2006 case 2: /* 1 load */
2007 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2008 case 3: /* 3 loads */
2009 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2010 case 4: /* 2 loads */
2011 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2016 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2019 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2020 const struct util_format_description
*desc
,
2023 assert(((struct si_screen
*)screen
)->info
.chip_class
<= GFX9
);
2025 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2026 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2028 assert(first_non_void
>= 0);
2030 switch (desc
->channel
[first_non_void
].type
) {
2031 case UTIL_FORMAT_TYPE_SIGNED
:
2032 case UTIL_FORMAT_TYPE_FIXED
:
2033 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2034 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2035 else if (desc
->channel
[first_non_void
].normalized
)
2036 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2038 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2040 case UTIL_FORMAT_TYPE_UNSIGNED
:
2041 if (desc
->channel
[first_non_void
].size
>= 32 || desc
->channel
[first_non_void
].pure_integer
)
2042 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2043 else if (desc
->channel
[first_non_void
].normalized
)
2044 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2046 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2048 case UTIL_FORMAT_TYPE_FLOAT
:
2050 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2054 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2057 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2058 const struct util_format_description
*desc
;
2060 unsigned data_format
;
2062 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_VERTEX_BUFFER
)) ==
2065 desc
= util_format_description(format
);
2069 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2070 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2071 * for read-only access (with caveats surrounding bounds checks), but
2072 * obviously fails for write access which we have to implement for
2073 * shader images. Luckily, OpenGL doesn't expect this to be supported
2074 * anyway, and so the only impact is on PBO uploads / downloads, which
2075 * shouldn't be expected to be fast for GL_RGB anyway.
2077 if (desc
->block
.bits
== 3 * 8 || desc
->block
.bits
== 3 * 16) {
2078 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2079 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2085 if (sscreen
->info
.chip_class
>= GFX10
) {
2086 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
2087 if (!fmt
->img_format
|| fmt
->img_format
>= 128)
2092 first_non_void
= util_format_get_first_non_void_channel(format
);
2093 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2094 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2100 static bool si_is_colorbuffer_format_supported(enum chip_class chip_class
,
2101 enum pipe_format format
)
2103 return si_translate_colorformat(chip_class
, format
) != V_028C70_COLOR_INVALID
&&
2104 si_translate_colorswap(format
, false) != ~0U;
2107 static bool si_is_zs_format_supported(enum pipe_format format
)
2109 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2112 static bool si_is_format_supported(struct pipe_screen
*screen
, enum pipe_format format
,
2113 enum pipe_texture_target target
, unsigned sample_count
,
2114 unsigned storage_sample_count
, unsigned usage
)
2116 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2117 unsigned retval
= 0;
2119 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2120 PRINT_ERR("radeonsi: unsupported texture type %d\n", target
);
2124 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2127 if (sample_count
> 1) {
2128 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2131 /* Only power-of-two sample counts are supported. */
2132 if (!util_is_power_of_two_or_zero(sample_count
) ||
2133 !util_is_power_of_two_or_zero(storage_sample_count
))
2136 /* Chips with 1 RB don't increment occlusion queries at 16x MSAA sample rate,
2137 * so don't expose 16 samples there.
2139 const unsigned max_eqaa_samples
= sscreen
->info
.num_render_backends
== 1 ? 8 : 16;
2140 const unsigned max_samples
= 8;
2142 /* MSAA support without framebuffer attachments. */
2143 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= max_eqaa_samples
)
2146 if (!sscreen
->info
.has_eqaa_surface_allocator
|| util_format_is_depth_or_stencil(format
)) {
2147 /* Color without EQAA or depth/stencil. */
2148 if (sample_count
> max_samples
|| sample_count
!= storage_sample_count
)
2151 /* Color with EQAA. */
2152 if (sample_count
> max_eqaa_samples
|| storage_sample_count
> max_samples
)
2157 if (usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
)) {
2158 if (target
== PIPE_BUFFER
) {
2159 retval
|= si_is_vertex_format_supported(
2160 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
));
2162 if (si_is_sampler_format_supported(screen
, format
))
2163 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
| PIPE_BIND_SHADER_IMAGE
);
2167 if ((usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2168 PIPE_BIND_SHARED
| PIPE_BIND_BLENDABLE
)) &&
2169 si_is_colorbuffer_format_supported(sscreen
->info
.chip_class
, format
)) {
2170 retval
|= usage
& (PIPE_BIND_RENDER_TARGET
| PIPE_BIND_DISPLAY_TARGET
| PIPE_BIND_SCANOUT
|
2172 if (!util_format_is_pure_integer(format
) && !util_format_is_depth_or_stencil(format
))
2173 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2176 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) && si_is_zs_format_supported(format
)) {
2177 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2180 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2181 retval
|= si_is_vertex_format_supported(screen
, format
, PIPE_BIND_VERTEX_BUFFER
);
2184 if ((usage
& PIPE_BIND_LINEAR
) && !util_format_is_compressed(format
) &&
2185 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2186 retval
|= PIPE_BIND_LINEAR
;
2188 return retval
== usage
;
2192 * framebuffer handling
2195 static void si_choose_spi_color_formats(struct si_surface
*surf
, unsigned format
, unsigned swap
,
2196 unsigned ntype
, bool is_depth
)
2198 struct ac_spi_color_formats formats
= {};
2200 ac_choose_spi_color_formats(format
, swap
, ntype
, is_depth
, &formats
);
2202 surf
->spi_shader_col_format
= formats
.normal
;
2203 surf
->spi_shader_col_format_alpha
= formats
.alpha
;
2204 surf
->spi_shader_col_format_blend
= formats
.blend
;
2205 surf
->spi_shader_col_format_blend_alpha
= formats
.blend_alpha
;
2208 static void si_initialize_color_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2210 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2211 unsigned color_info
, color_attrib
;
2212 unsigned format
, swap
, ntype
, endian
;
2213 const struct util_format_description
*desc
;
2215 unsigned blend_clamp
= 0, blend_bypass
= 0;
2217 desc
= util_format_description(surf
->base
.format
);
2218 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2219 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2223 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2224 ntype
= V_028C70_NUMBER_FLOAT
;
2226 ntype
= V_028C70_NUMBER_UNORM
;
2227 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2228 ntype
= V_028C70_NUMBER_SRGB
;
2229 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2230 if (desc
->channel
[firstchan
].pure_integer
) {
2231 ntype
= V_028C70_NUMBER_SINT
;
2233 assert(desc
->channel
[firstchan
].normalized
);
2234 ntype
= V_028C70_NUMBER_SNORM
;
2236 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2237 if (desc
->channel
[firstchan
].pure_integer
) {
2238 ntype
= V_028C70_NUMBER_UINT
;
2240 assert(desc
->channel
[firstchan
].normalized
);
2241 ntype
= V_028C70_NUMBER_UNORM
;
2246 format
= si_translate_colorformat(sctx
->chip_class
, surf
->base
.format
);
2247 if (format
== V_028C70_COLOR_INVALID
) {
2248 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2250 assert(format
!= V_028C70_COLOR_INVALID
);
2251 swap
= si_translate_colorswap(surf
->base
.format
, false);
2252 endian
= si_colorformat_endian_swap(format
);
2254 /* blend clamp should be set for all NORM/SRGB types */
2255 if (ntype
== V_028C70_NUMBER_UNORM
|| ntype
== V_028C70_NUMBER_SNORM
||
2256 ntype
== V_028C70_NUMBER_SRGB
)
2259 /* set blend bypass according to docs if SINT/UINT or
2260 8/24 COLOR variants */
2261 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2262 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2263 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2268 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2269 if (format
== V_028C70_COLOR_8
|| format
== V_028C70_COLOR_8_8
||
2270 format
== V_028C70_COLOR_8_8_8_8
)
2271 surf
->color_is_int8
= true;
2272 else if (format
== V_028C70_COLOR_10_10_10_2
|| format
== V_028C70_COLOR_2_10_10_10
)
2273 surf
->color_is_int10
= true;
2277 S_028C70_FORMAT(format
) | S_028C70_COMP_SWAP(swap
) | S_028C70_BLEND_CLAMP(blend_clamp
) |
2278 S_028C70_BLEND_BYPASS(blend_bypass
) | S_028C70_SIMPLE_FLOAT(1) |
2279 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&& ntype
!= V_028C70_NUMBER_SNORM
&&
2280 ntype
!= V_028C70_NUMBER_SRGB
&& format
!= V_028C70_COLOR_8_24
&&
2281 format
!= V_028C70_COLOR_24_8
) |
2282 S_028C70_NUMBER_TYPE(ntype
) | S_028C70_ENDIAN(endian
);
2284 /* Intensity is implemented as Red, so treat it that way. */
2285 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2286 util_format_is_intensity(surf
->base
.format
));
2288 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2289 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2290 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2292 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) | S_028C74_NUM_FRAGMENTS(log_fragments
);
2294 if (tex
->surface
.fmask_offset
) {
2295 color_info
|= S_028C70_COMPRESSION(1);
2296 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2298 if (sctx
->chip_class
== GFX6
) {
2299 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2300 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2305 if (sctx
->chip_class
>= GFX10
) {
2306 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2308 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2309 64 for APU because all of our APUs to date use DIMMs which have
2310 a request granularity size of 64B while all other chips have a
2312 if (!sctx
->screen
->info
.has_dedicated_vram
)
2313 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2315 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
2316 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
2317 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2318 S_028C78_INDEPENDENT_64B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_64B_blocks
) |
2319 S_028C78_INDEPENDENT_128B_BLOCKS(tex
->surface
.u
.gfx9
.dcc
.independent_128B_blocks
);
2320 } else if (sctx
->chip_class
>= GFX8
) {
2321 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2322 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2324 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2325 64 for APU because all of our APUs to date use DIMMs which have
2326 a request granularity size of 64B while all other chips have a
2328 if (!sctx
->screen
->info
.has_dedicated_vram
)
2329 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2331 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2332 if (tex
->surface
.bpe
== 1)
2333 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2334 else if (tex
->surface
.bpe
== 2)
2335 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2338 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2339 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2340 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2343 /* This must be set for fast clear to work without FMASK. */
2344 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== GFX6
) {
2345 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2346 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2349 /* GFX10 field has the same base shift as the GFX6 field */
2350 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2351 S_028C6C_SLICE_MAX_GFX10(surf
->base
.u
.tex
.last_layer
);
2352 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2354 if (sctx
->chip_class
>= GFX10
) {
2355 color_view
|= S_028C6C_MIP_LEVEL_GFX10(surf
->base
.u
.tex
.level
);
2357 surf
->cb_color_attrib3
= S_028EE0_MIP0_DEPTH(mip0_depth
) |
2358 S_028EE0_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
) |
2359 S_028EE0_RESOURCE_LEVEL(1);
2360 } else if (sctx
->chip_class
== GFX9
) {
2361 color_view
|= S_028C6C_MIP_LEVEL_GFX9(surf
->base
.u
.tex
.level
);
2362 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2363 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2366 if (sctx
->chip_class
>= GFX9
) {
2367 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2368 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2369 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2372 surf
->cb_color_view
= color_view
;
2373 surf
->cb_color_info
= color_info
;
2374 surf
->cb_color_attrib
= color_attrib
;
2376 /* Determine pixel shader export format */
2377 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2379 surf
->color_initialized
= true;
2382 static void si_init_depth_surface(struct si_context
*sctx
, struct si_surface
*surf
)
2384 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2385 unsigned level
= surf
->base
.u
.tex
.level
;
2386 unsigned format
, stencil_format
;
2387 uint32_t z_info
, s_info
;
2389 format
= si_translate_dbformat(tex
->db_render_format
);
2390 stencil_format
= tex
->surface
.has_stencil
? V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2392 assert(format
!= V_028040_Z_INVALID
);
2393 if (format
== V_028040_Z_INVALID
)
2394 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2396 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2397 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2398 surf
->db_htile_data_base
= 0;
2399 surf
->db_htile_surface
= 0;
2401 if (sctx
->chip_class
>= GFX10
) {
2402 surf
->db_depth_view
|= S_028008_SLICE_START_HI(surf
->base
.u
.tex
.first_layer
>> 11) |
2403 S_028008_SLICE_MAX_HI(surf
->base
.u
.tex
.last_layer
>> 11);
2406 if (sctx
->chip_class
>= GFX9
) {
2407 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2408 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2409 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2410 z_info
= S_028038_FORMAT(format
) |
2411 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2412 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2413 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2414 s_info
= S_02803C_FORMAT(stencil_format
) |
2415 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2417 if (sctx
->chip_class
== GFX9
) {
2418 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2419 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2421 surf
->db_depth_view
|= S_028008_MIPID(level
);
2422 surf
->db_depth_size
=
2423 S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) | S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2425 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2426 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) | S_028038_ALLOW_EXPCLEAR(1);
2428 if (tex
->surface
.has_stencil
&& !tex
->htile_stencil_disabled
) {
2429 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2430 * See that for explanation.
2432 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2434 /* Use all HTILE for depth if there's no stencil. */
2435 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2438 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2439 surf
->db_htile_surface
=
2440 S_028ABC_FULL_CACHE(1) | S_028ABC_PIPE_ALIGNED(1);
2441 if (sctx
->chip_class
== GFX9
) {
2442 surf
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
2447 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2449 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2451 surf
->db_depth_base
=
2452 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2453 surf
->db_stencil_base
=
2454 (tex
->buffer
.gpu_address
+ tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2457 S_028040_FORMAT(format
) | S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2458 s_info
= S_028044_FORMAT(stencil_format
);
2459 surf
->db_depth_info
= 0;
2461 if (sctx
->chip_class
>= GFX7
) {
2462 struct radeon_info
*info
= &sctx
->screen
->info
;
2463 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2464 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2465 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2466 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2467 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2468 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2470 surf
->db_depth_info
|= S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2471 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2472 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2473 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2474 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2475 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2476 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2477 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2479 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2480 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2481 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2482 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2485 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2486 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2487 surf
->db_depth_slice
=
2488 S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
* levelinfo
->nblk_y
) / 64 - 1);
2490 if (si_htile_enabled(tex
, level
, PIPE_MASK_ZS
)) {
2491 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) | S_028040_ALLOW_EXPCLEAR(1);
2493 if (tex
->surface
.has_stencil
) {
2494 /* Workaround: For a not yet understood reason, the
2495 * combination of MSAA, fast stencil clear and stencil
2496 * decompress messes with subsequent stencil buffer
2497 * uses. Problem was reproduced on Verde, Bonaire,
2498 * Tonga, and Carrizo.
2500 * Disabling EXPCLEAR works around the problem.
2502 * Check piglit's arb_texture_multisample-stencil-clear
2503 * test if you want to try changing this.
2505 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2506 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2509 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+ tex
->surface
.htile_offset
) >> 8;
2510 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2514 surf
->db_z_info
= z_info
;
2515 surf
->db_stencil_info
= s_info
;
2517 surf
->depth_initialized
= true;
2520 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2522 if (sctx
->decompression_enabled
)
2525 if (sctx
->framebuffer
.state
.zsbuf
) {
2526 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2527 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2529 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2531 if (tex
->surface
.has_stencil
)
2532 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2535 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2536 while (compressed_cb_mask
) {
2537 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2538 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2539 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2541 if (tex
->surface
.fmask_offset
) {
2542 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2543 tex
->fmask_is_identity
= false;
2545 if (tex
->dcc_gather_statistics
)
2546 tex
->separate_dcc_dirty
= true;
2550 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2552 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2553 struct si_surface
*surf
= NULL
;
2554 struct si_texture
*tex
;
2556 if (!state
->cbufs
[i
])
2558 surf
= (struct si_surface
*)state
->cbufs
[i
];
2559 tex
= (struct si_texture
*)surf
->base
.texture
;
2561 p_atomic_dec(&tex
->framebuffers_bound
);
2565 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2566 const struct pipe_framebuffer_state
*state
)
2568 struct si_context
*sctx
= (struct si_context
*)ctx
;
2569 struct si_surface
*surf
= NULL
;
2570 struct si_texture
*tex
;
2571 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2572 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2573 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2574 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2575 bool old_has_stencil
=
2577 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2578 bool unbound
= false;
2581 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2582 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2583 * We could implement the full workaround here, but it's a useless case.
2585 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2586 unreachable("the framebuffer shouldn't have zero area");
2590 si_update_fb_dirtiness_after_rendering(sctx
);
2592 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2593 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2596 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2597 if (tex
->dcc_gather_statistics
)
2598 vi_separate_dcc_stop_query(sctx
, tex
);
2601 /* Disable DCC if the formats are incompatible. */
2602 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2603 if (!state
->cbufs
[i
])
2606 surf
= (struct si_surface
*)state
->cbufs
[i
];
2607 tex
= (struct si_texture
*)surf
->base
.texture
;
2609 if (!surf
->dcc_incompatible
)
2612 /* Since the DCC decompression calls back into set_framebuffer-
2613 * _state, we need to unbind the framebuffer, so that
2614 * vi_separate_dcc_stop_query isn't called twice with the same
2618 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2622 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2623 if (!si_texture_disable_dcc(sctx
, tex
))
2624 si_decompress_dcc(sctx
, tex
);
2626 surf
->dcc_incompatible
= false;
2629 /* Only flush TC when changing the framebuffer state, because
2630 * the only client not using TC that can change textures is
2633 * Wait for compute shaders because of possible transitions:
2634 * - FB write -> shader read
2635 * - shader write -> FB read
2637 * DB caches are flushed on demand (using si_decompress_textures).
2639 * When MSAA is enabled, CB and TC caches are flushed on demand
2640 * (after FMASK decompression). Shader write -> FB read transitions
2641 * cannot happen for MSAA textures, because MSAA shader images are
2644 * Only flush and wait for CB if there is actually a bound color buffer.
2646 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
2647 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2648 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
2649 sctx
->framebuffer
.all_DCC_pipe_aligned
);
2652 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2654 /* u_blitter doesn't invoke depth decompression when it does multiple
2655 * blits in a row, but the only case when it matters for DB is when
2656 * doing generate_mipmap. So here we flush DB manually between
2657 * individual generate_mipmap blits.
2658 * Note that lower mipmap levels aren't compressed.
2660 if (sctx
->generate_mipmap_for_depth
) {
2661 si_make_DB_shader_coherent(sctx
, 1, false, sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2662 } else if (sctx
->chip_class
== GFX9
) {
2663 /* It appears that DB metadata "leaks" in a sequence of:
2665 * - DCC decompress for shader image writes (with DB disabled)
2666 * - render with DEPTH_BEFORE_SHADER=1
2667 * Flushing DB metadata works around the problem.
2669 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2672 /* Take the maximum of the old and new count. If the new count is lower,
2673 * dirtying is needed to disable the unbound colorbuffers.
2675 sctx
->framebuffer
.dirty_cbufs
|=
2676 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2677 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2679 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2680 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2682 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2683 sctx
->framebuffer
.spi_shader_col_format
= 0;
2684 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2685 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2686 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2687 sctx
->framebuffer
.color_is_int8
= 0;
2688 sctx
->framebuffer
.color_is_int10
= 0;
2690 sctx
->framebuffer
.compressed_cb_mask
= 0;
2691 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2692 sctx
->framebuffer
.displayable_dcc_cb_mask
= 0;
2693 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2694 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2695 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2696 sctx
->framebuffer
.any_dst_linear
= false;
2697 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2698 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2699 sctx
->framebuffer
.all_DCC_pipe_aligned
= true;
2700 sctx
->framebuffer
.min_bytes_per_pixel
= 0;
2701 sctx
->framebuffer
.color_big_page
= true;
2702 sctx
->framebuffer
.zs_big_page
= true;
2704 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2705 if (!state
->cbufs
[i
])
2708 surf
= (struct si_surface
*)state
->cbufs
[i
];
2709 tex
= (struct si_texture
*)surf
->base
.texture
;
2711 if (!surf
->color_initialized
) {
2712 si_initialize_color_surface(sctx
, surf
);
2715 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2716 sctx
->framebuffer
.spi_shader_col_format
|= surf
->spi_shader_col_format
<< (i
* 4);
2717 sctx
->framebuffer
.spi_shader_col_format_alpha
|= surf
->spi_shader_col_format_alpha
<< (i
* 4);
2718 sctx
->framebuffer
.spi_shader_col_format_blend
|= surf
->spi_shader_col_format_blend
<< (i
* 4);
2719 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|= surf
->spi_shader_col_format_blend_alpha
2722 sctx
->framebuffer
.color_big_page
&=
2723 tex
->buffer
.bo_alignment
% (64 * 1024) == 0;
2725 if (surf
->color_is_int8
)
2726 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2727 if (surf
->color_is_int10
)
2728 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2730 if (tex
->surface
.fmask_offset
)
2731 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2733 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2735 if (tex
->surface
.display_dcc_offset
)
2736 sctx
->framebuffer
.displayable_dcc_cb_mask
|= 1 << i
;
2738 /* Don't update nr_color_samples for non-AA buffers.
2739 * (e.g. destination of MSAA resolve)
2741 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2742 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2743 sctx
->framebuffer
.nr_color_samples
=
2744 MIN2(sctx
->framebuffer
.nr_color_samples
, tex
->buffer
.b
.b
.nr_storage_samples
);
2745 sctx
->framebuffer
.nr_color_samples
= MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2748 if (tex
->surface
.is_linear
)
2749 sctx
->framebuffer
.any_dst_linear
= true;
2751 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
)) {
2752 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2754 if (sctx
->chip_class
>= GFX9
&& !tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
)
2755 sctx
->framebuffer
.all_DCC_pipe_aligned
= false;
2758 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2760 p_atomic_inc(&tex
->framebuffers_bound
);
2762 if (tex
->dcc_gather_statistics
) {
2763 /* Dirty tracking must be enabled for DCC usage analysis. */
2764 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2765 vi_separate_dcc_start_query(sctx
, tex
);
2768 /* Update the minimum but don't keep 0. */
2769 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2770 tex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2771 sctx
->framebuffer
.min_bytes_per_pixel
= tex
->surface
.bpe
;
2774 /* For optimal DCC performance. */
2775 if (sctx
->chip_class
>= GFX10
)
2776 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 6;
2778 sctx
->framebuffer
.dcc_overwrite_combiner_watermark
= 4;
2780 struct si_texture
*zstex
= NULL
;
2783 surf
= (struct si_surface
*)state
->zsbuf
;
2784 zstex
= (struct si_texture
*)surf
->base
.texture
;
2786 if (!surf
->depth_initialized
) {
2787 si_init_depth_surface(sctx
, surf
);
2790 sctx
->framebuffer
.zs_big_page
= zstex
->buffer
.bo_alignment
% (64 * 1024) == 0;
2792 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
, PIPE_MASK_ZS
))
2793 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2795 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2797 /* Update the minimum but don't keep 0. */
2798 if (!sctx
->framebuffer
.min_bytes_per_pixel
||
2799 zstex
->surface
.bpe
< sctx
->framebuffer
.min_bytes_per_pixel
)
2800 sctx
->framebuffer
.min_bytes_per_pixel
= zstex
->surface
.bpe
;
2803 si_update_ps_colorbuf0_slot(sctx
);
2804 si_update_poly_offset_state(sctx
);
2805 si_update_ngg_small_prim_precision(sctx
);
2806 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2807 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2809 if (sctx
->screen
->dpbb_allowed
)
2810 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2812 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2813 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2815 if (sctx
->screen
->has_out_of_order_rast
&&
2816 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2817 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2818 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2819 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2821 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2822 struct pipe_constant_buffer constbuf
= {0};
2824 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2825 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2827 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2829 /* Set sample locations as fragment shader constants. */
2830 switch (sctx
->framebuffer
.nr_samples
) {
2832 constbuf
.buffer_offset
= 0;
2835 constbuf
.buffer_offset
=
2836 (ubyte
*)sctx
->sample_positions
.x2
- (ubyte
*)sctx
->sample_positions
.x1
;
2839 constbuf
.buffer_offset
=
2840 (ubyte
*)sctx
->sample_positions
.x4
- (ubyte
*)sctx
->sample_positions
.x1
;
2843 constbuf
.buffer_offset
=
2844 (ubyte
*)sctx
->sample_positions
.x8
- (ubyte
*)sctx
->sample_positions
.x1
;
2847 constbuf
.buffer_offset
=
2848 (ubyte
*)sctx
->sample_positions
.x16
- (ubyte
*)sctx
->sample_positions
.x1
;
2851 PRINT_ERR("Requested an invalid number of samples %i.\n", sctx
->framebuffer
.nr_samples
);
2854 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2855 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2857 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2860 sctx
->do_update_shaders
= true;
2862 if (!sctx
->decompression_enabled
) {
2863 /* Prevent textures decompression when the framebuffer state
2864 * changes come from the decompression passes themselves.
2866 sctx
->need_check_render_feedback
= true;
2870 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2872 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2873 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2874 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2875 struct si_texture
*tex
= NULL
;
2876 struct si_surface
*cb
= NULL
;
2877 unsigned cb_color_info
= 0;
2879 /* Enable CMASK/FMASK/HTILE/DCC caching in L2 for small chips. */
2880 unsigned meta_write_policy
, meta_read_policy
;
2881 /* TODO: investigate whether LRU improves performance on other chips too */
2882 if (sctx
->screen
->info
.num_render_backends
<= 4) {
2883 meta_write_policy
= V_02807C_CACHE_LRU_WR
; /* cache writes */
2884 meta_read_policy
= V_02807C_CACHE_LRU_RD
; /* cache reads */
2886 meta_write_policy
= V_02807C_CACHE_STREAM
; /* write combine */
2887 meta_read_policy
= V_02807C_CACHE_NOA
; /* don't cache reads */
2891 for (i
= 0; i
< nr_cbufs
; i
++) {
2892 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
2893 unsigned cb_color_attrib
;
2895 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2898 cb
= (struct si_surface
*)state
->cbufs
[i
];
2900 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2901 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2905 tex
= (struct si_texture
*)cb
->base
.texture
;
2906 radeon_add_to_buffer_list(
2907 sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
2908 tex
->buffer
.b
.b
.nr_samples
> 1 ? RADEON_PRIO_COLOR_BUFFER_MSAA
: RADEON_PRIO_COLOR_BUFFER
);
2910 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
2911 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2912 RADEON_PRIO_SEPARATE_META
);
2915 if (tex
->dcc_separate_buffer
)
2916 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, tex
->dcc_separate_buffer
,
2917 RADEON_USAGE_READWRITE
, RADEON_PRIO_SEPARATE_META
);
2919 /* Compute mutable surface parameters. */
2920 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
2922 cb_color_cmask
= tex
->cmask_base_address_reg
;
2924 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2925 cb_color_attrib
= cb
->cb_color_attrib
;
2927 if (cb
->base
.u
.tex
.level
> 0)
2928 cb_color_info
&= C_028C70_FAST_CLEAR
;
2930 if (tex
->surface
.fmask_offset
) {
2931 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
) >> 8;
2932 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
2936 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
2937 bool is_msaa_resolve_dst
= state
->cbufs
[0] && state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2938 state
->cbufs
[1] == &cb
->base
&&
2939 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2941 if (!is_msaa_resolve_dst
)
2942 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2945 ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) + tex
->surface
.dcc_offset
) >>
2948 unsigned dcc_tile_swizzle
= tex
->surface
.tile_swizzle
;
2949 dcc_tile_swizzle
&= (tex
->surface
.dcc_alignment
- 1) >> 8;
2950 cb_dcc_base
|= dcc_tile_swizzle
;
2953 if (sctx
->chip_class
>= GFX10
) {
2954 unsigned cb_color_attrib3
;
2956 /* Set mutable surface parameters. */
2957 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
2958 cb_color_base
|= tex
->surface
.tile_swizzle
;
2959 if (!tex
->surface
.fmask_offset
)
2960 cb_color_fmask
= cb_color_base
;
2961 if (cb
->base
.u
.tex
.level
> 0)
2962 cb_color_cmask
= cb_color_base
;
2964 cb_color_attrib3
= cb
->cb_color_attrib3
|
2965 S_028EE0_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2966 S_028EE0_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2967 S_028EE0_CMASK_PIPE_ALIGNED(1) |
2968 S_028EE0_DCC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.dcc
.pipe_aligned
);
2970 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 14);
2971 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
2972 radeon_emit(cs
, 0); /* hole */
2973 radeon_emit(cs
, 0); /* hole */
2974 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
2975 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
2976 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
2977 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
2978 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
2979 radeon_emit(cs
, 0); /* hole */
2980 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
2981 radeon_emit(cs
, 0); /* hole */
2982 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
2983 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
2984 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
2986 radeon_set_context_reg(cs
, R_028E40_CB_COLOR0_BASE_EXT
+ i
* 4, cb_color_base
>> 32);
2987 radeon_set_context_reg(cs
, R_028E60_CB_COLOR0_CMASK_BASE_EXT
+ i
* 4,
2988 cb_color_cmask
>> 32);
2989 radeon_set_context_reg(cs
, R_028E80_CB_COLOR0_FMASK_BASE_EXT
+ i
* 4,
2990 cb_color_fmask
>> 32);
2991 radeon_set_context_reg(cs
, R_028EA0_CB_COLOR0_DCC_BASE_EXT
+ i
* 4, cb_dcc_base
>> 32);
2992 radeon_set_context_reg(cs
, R_028EC0_CB_COLOR0_ATTRIB2
+ i
* 4, cb
->cb_color_attrib2
);
2993 radeon_set_context_reg(cs
, R_028EE0_CB_COLOR0_ATTRIB3
+ i
* 4, cb_color_attrib3
);
2994 } else if (sctx
->chip_class
== GFX9
) {
2995 struct gfx9_surf_meta_flags meta
= {
3000 if (tex
->surface
.dcc_offset
)
3001 meta
= tex
->surface
.u
.gfx9
.dcc
;
3003 /* Set mutable surface parameters. */
3004 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3005 cb_color_base
|= tex
->surface
.tile_swizzle
;
3006 if (!tex
->surface
.fmask_offset
)
3007 cb_color_fmask
= cb_color_base
;
3008 if (cb
->base
.u
.tex
.level
> 0)
3009 cb_color_cmask
= cb_color_base
;
3010 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3011 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3012 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3013 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3015 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3016 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3017 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3018 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3019 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3020 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3021 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3022 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3023 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3024 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3025 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3026 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3027 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3028 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3029 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3030 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3032 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3033 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3035 /* Compute mutable surface parameters (GFX6-GFX8). */
3036 const struct legacy_surf_level
*level_info
=
3037 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3038 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3039 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3041 cb_color_base
+= level_info
->offset
>> 8;
3042 /* Only macrotiled modes can set tile swizzle. */
3043 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3044 cb_color_base
|= tex
->surface
.tile_swizzle
;
3046 if (!tex
->surface
.fmask_offset
)
3047 cb_color_fmask
= cb_color_base
;
3048 if (cb
->base
.u
.tex
.level
> 0)
3049 cb_color_cmask
= cb_color_base
;
3051 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3053 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3054 slice_tile_max
= level_info
->nblk_x
* level_info
->nblk_y
/ 64 - 1;
3055 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3057 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3058 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3059 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3061 if (tex
->surface
.fmask_offset
) {
3062 if (sctx
->chip_class
>= GFX7
)
3064 S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3066 S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3067 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3069 /* This must be set for fast clear to work without FMASK. */
3070 if (sctx
->chip_class
>= GFX7
)
3071 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3072 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3073 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3076 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3077 sctx
->chip_class
>= GFX8
? 14 : 13);
3078 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3079 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3080 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3081 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3082 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3083 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3084 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3085 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3086 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3087 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3088 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3089 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3090 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3092 if (sctx
->chip_class
>= GFX8
) /* R_028C94_CB_COLOR0_DCC_BASE */
3093 radeon_emit(cs
, cb_dcc_base
);
3097 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3098 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3101 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3102 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3103 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3104 unsigned db_z_info
= zb
->db_z_info
;
3105 unsigned db_stencil_info
= zb
->db_stencil_info
;
3106 unsigned db_htile_surface
= zb
->db_htile_surface
;
3108 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, &tex
->buffer
, RADEON_USAGE_READWRITE
,
3109 zb
->base
.texture
->nr_samples
> 1 ? RADEON_PRIO_DEPTH_BUFFER_MSAA
3110 : RADEON_PRIO_DEPTH_BUFFER
);
3112 /* Set fields dependent on tc_compatile_htile. */
3113 if (sctx
->chip_class
>= GFX9
&&
3114 vi_tc_compat_htile_enabled(tex
, zb
->base
.u
.tex
.level
, PIPE_MASK_ZS
)) {
3115 unsigned max_zplanes
= 4;
3117 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&& tex
->buffer
.b
.b
.nr_samples
> 1)
3120 db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1);
3122 if (sctx
->chip_class
>= GFX10
) {
3123 db_z_info
|= S_028040_ITERATE_FLUSH(1);
3124 db_stencil_info
|= S_028044_ITERATE_FLUSH(!tex
->htile_stencil_disabled
);
3126 db_z_info
|= S_028038_ITERATE_FLUSH(1);
3127 db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
3131 if (sctx
->chip_class
>= GFX10
) {
3132 bool zs_big_page
= sctx
->chip_class
>= GFX10_3
&&
3133 sctx
->framebuffer
.zs_big_page
;
3135 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3136 radeon_set_context_reg(cs
, R_02801C_DB_DEPTH_SIZE_XY
, zb
->db_depth_size
);
3138 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 7);
3139 radeon_emit(cs
, S_02803C_RESOURCE_LEVEL(1)); /* DB_DEPTH_INFO */
3140 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3141 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3142 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3143 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3144 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3145 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3146 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3148 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_READ_BASE_HI
, 6);
3149 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3150 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3151 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3152 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3153 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3154 radeon_emit(cs
, /* DB_RMI_L2_CACHE_CONTROL */
3155 S_02807C_Z_WR_POLICY(V_02807C_CACHE_STREAM
) |
3156 S_02807C_S_WR_POLICY(V_02807C_CACHE_STREAM
) |
3157 S_02807C_HTILE_WR_POLICY(meta_write_policy
) |
3158 S_02807C_ZPCPSD_WR_POLICY(V_02807C_CACHE_STREAM
) |
3159 S_02807C_Z_RD_POLICY(V_02807C_CACHE_NOA
) |
3160 S_02807C_S_RD_POLICY(V_02807C_CACHE_NOA
) |
3161 S_02807C_HTILE_RD_POLICY(meta_read_policy
) |
3162 S_02807C_Z_BIG_PAGE(zs_big_page
) |
3163 S_02807C_S_BIG_PAGE(zs_big_page
));
3164 } else if (sctx
->chip_class
== GFX9
) {
3165 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3166 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3168 S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3169 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3171 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3172 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3173 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3174 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3175 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3176 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3177 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3178 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3179 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3180 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3181 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3183 S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3185 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3186 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3187 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3190 /* Set fields dependent on tc_compatile_htile. */
3191 if (si_htile_enabled(tex
, zb
->base
.u
.tex
.level
, PIPE_MASK_ZS
)) {
3192 if (!tex
->surface
.has_stencil
&& !tex
->tc_compatible_htile
) {
3193 /* Use all of the htile_buffer for depth if there's no stencil.
3194 * This must not be set when TC-compatible HTILE is enabled
3197 db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3200 if (tex
->tc_compatible_htile
) {
3201 db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
3203 /* 0 = full compression. N = only compress up to N-1 Z planes. */
3204 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
3205 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3206 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
3207 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3209 db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3213 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3215 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3216 radeon_emit(cs
, zb
->db_depth_info
| /* DB_DEPTH_INFO */
3217 S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
));
3218 radeon_emit(cs
, db_z_info
| /* DB_Z_INFO */
3219 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3220 radeon_emit(cs
, db_stencil_info
); /* DB_STENCIL_INFO */
3221 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3222 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3223 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3224 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3225 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3226 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3229 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3230 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3231 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3233 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3234 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, db_htile_surface
);
3235 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3236 if (sctx
->chip_class
== GFX9
)
3237 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3239 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3241 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3242 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3245 /* Framebuffer dimensions. */
3246 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_cs_preamble_state */
3247 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3248 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3251 bool color_big_page
= sctx
->chip_class
>= GFX10_3
&&
3252 sctx
->framebuffer
.color_big_page
;
3253 radeon_set_context_reg(cs
, R_028410_CB_RMI_GL2_CACHE_CONTROL
,
3254 S_028410_CMASK_WR_POLICY(meta_write_policy
) |
3255 S_028410_FMASK_WR_POLICY(meta_write_policy
) |
3256 S_028410_DCC_WR_POLICY(meta_write_policy
) |
3257 S_028410_COLOR_WR_POLICY(V_028410_CACHE_STREAM
) |
3258 S_028410_CMASK_RD_POLICY(meta_read_policy
) |
3259 S_028410_FMASK_RD_POLICY(meta_read_policy
) |
3260 S_028410_DCC_RD_POLICY(meta_read_policy
) |
3261 S_028410_COLOR_RD_POLICY(V_028410_CACHE_NOA
) |
3262 S_028410_FMASK_BIG_PAGE(color_big_page
) |
3263 S_028410_COLOR_BIG_PAGE(color_big_page
));
3266 if (sctx
->screen
->dfsm_allowed
) {
3267 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3268 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3271 sctx
->framebuffer
.dirty_cbufs
= 0;
3272 sctx
->framebuffer
.dirty_zsbuf
= false;
3275 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3277 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3278 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3279 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3280 bool has_msaa_sample_loc_bug
= sctx
->screen
->info
.has_msaa_sample_loc_bug
;
3282 /* Smoothing (only possible with nr_samples == 1) uses the same
3283 * sample locations as the MSAA it simulates.
3285 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3286 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3288 /* On Polaris, the small primitive filter uses the sample locations
3289 * even when MSAA is off, so we need to make sure they're set to 0.
3291 * GFX10 uses sample locations unconditionally, so they always need
3294 if ((nr_samples
>= 2 || has_msaa_sample_loc_bug
|| sctx
->chip_class
>= GFX10
) &&
3295 nr_samples
!= sctx
->sample_locs_num_samples
) {
3296 sctx
->sample_locs_num_samples
= nr_samples
;
3297 si_emit_sample_locations(cs
, nr_samples
);
3300 if (sctx
->family
>= CHIP_POLARIS10
) {
3301 unsigned small_prim_filter_cntl
=
3302 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3304 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3306 /* The alternative of setting sample locations to 0 would
3307 * require a DB flush to avoid Z errors, see
3308 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3310 if (has_msaa_sample_loc_bug
&& sctx
->framebuffer
.nr_samples
> 1 && !rs
->multisample_enable
)
3311 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3313 radeon_opt_set_context_reg(sctx
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3314 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
, small_prim_filter_cntl
);
3317 /* The exclusion bits can be set to improve rasterization efficiency
3318 * if no sample lies on the pixel boundary (-8 sample offset).
3320 bool exclusion
= sctx
->chip_class
>= GFX7
&& (!rs
->multisample_enable
|| nr_samples
!= 16);
3321 radeon_opt_set_context_reg(
3322 sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3323 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) | S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3326 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3328 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3329 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3331 if (!sctx
->screen
->has_out_of_order_rast
)
3334 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3336 colormask
&= blend
->cb_target_enabled_4bit
;
3338 /* Conservative: No logic op. */
3339 if (colormask
&& blend
->logicop_enable
)
3342 struct si_dsa_order_invariance dsa_order_invariant
= {.zs
= true,
3344 .pass_last
= false};
3346 if (sctx
->framebuffer
.state
.zsbuf
) {
3347 struct si_texture
*zstex
= (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3348 bool has_stencil
= zstex
->surface
.has_stencil
;
3349 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3350 if (!dsa_order_invariant
.zs
)
3353 /* The set of PS invocations is always order invariant,
3354 * except when early Z/S tests are requested. */
3355 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.writes_memory
&&
3356 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3357 !dsa_order_invariant
.pass_set
)
3360 if (sctx
->num_perfect_occlusion_queries
!= 0 && !dsa_order_invariant
.pass_set
)
3367 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3370 /* Only commutative blending. */
3371 if (blendmask
& ~blend
->commutative_4bit
)
3374 if (!dsa_order_invariant
.pass_set
)
3378 if (colormask
& ~blendmask
) {
3379 if (!dsa_order_invariant
.pass_last
)
3386 static void si_emit_msaa_config(struct si_context
*sctx
)
3388 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3389 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3390 /* 33% faster rendering to linear color buffers */
3391 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3392 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3393 unsigned sc_mode_cntl_1
=
3394 S_028A4C_WALK_SIZE(dst_is_linear
) | S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3395 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3396 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3397 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3399 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) | S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3400 S_028A4C_TILE_WALK_ORDER_ENABLE(1) | S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3401 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3402 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) | S_028804_INCOHERENT_EQAA_READS(1) |
3403 S_028804_INTERPOLATE_COMP_Z(1) | S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3404 unsigned coverage_samples
, color_samples
, z_samples
;
3405 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3407 /* S: Coverage samples (up to 16x):
3408 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3409 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3411 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3412 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3413 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3414 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3415 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3418 * F: Color samples (up to 8x, must be <= coverage samples):
3419 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3420 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3422 * Can be anything between coverage and color samples:
3423 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3424 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3425 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3426 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3427 * # All are currently set the same as coverage samples.
3429 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3430 * flag for undefined color samples. A shader-based resolve must handle unknowns
3431 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3432 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3433 * useful. The CB resolve always drops unknowns.
3435 * Sensible AA configurations:
3436 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3437 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3438 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3439 * EQAA 8s 8z 8f = 8x MSAA
3440 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3441 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3442 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3443 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3444 * EQAA 4s 4z 4f = 4x MSAA
3445 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3446 * EQAA 2s 2z 2f = 2x MSAA
3448 if (sctx
->framebuffer
.nr_samples
> 1 && rs
->multisample_enable
) {
3449 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3450 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3452 if (sctx
->framebuffer
.state
.zsbuf
) {
3453 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3454 z_samples
= MAX2(1, z_samples
);
3456 z_samples
= coverage_samples
;
3458 } else if (sctx
->smoothing_enabled
) {
3459 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3461 coverage_samples
= color_samples
= z_samples
= 1;
3464 /* Required by OpenGL line rasterization.
3466 * TODO: We should also enable perpendicular endcaps for AA lines,
3467 * but that requires implementing line stippling in the pixel
3468 * shader. SC can only do line stippling with axis-aligned
3471 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3472 unsigned sc_aa_config
= 0;
3474 if (coverage_samples
> 1) {
3475 /* distance from the pixel center, indexed by log2(nr_samples) */
3476 static unsigned max_dist
[] = {
3483 unsigned log_samples
= util_logbase2(coverage_samples
);
3484 unsigned log_z_samples
= util_logbase2(z_samples
);
3485 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3486 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3488 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3489 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3490 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3491 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) |
3492 S_028BE0_COVERED_CENTROID_IS_CENTER(sctx
->chip_class
>= GFX10_3
);
3494 if (sctx
->framebuffer
.nr_samples
> 1) {
3495 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3496 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3497 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3498 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3499 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3500 } else if (sctx
->smoothing_enabled
) {
3501 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3505 unsigned initial_cdw
= cs
->current
.cdw
;
3507 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3508 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
, SI_TRACKED_PA_SC_LINE_CNTL
,
3509 sc_line_cntl
, sc_aa_config
);
3510 /* R_028804_DB_EQAA */
3511 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
, db_eqaa
);
3512 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3513 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
, SI_TRACKED_PA_SC_MODE_CNTL_1
,
3516 if (initial_cdw
!= cs
->current
.cdw
) {
3517 sctx
->context_roll
= true;
3519 /* GFX9: Flush DFSM when the AA mode changes. */
3520 if (sctx
->screen
->dfsm_allowed
) {
3521 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3522 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3527 void si_update_ps_iter_samples(struct si_context
*sctx
)
3529 if (sctx
->framebuffer
.nr_samples
> 1)
3530 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3531 if (sctx
->screen
->dpbb_allowed
)
3532 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3535 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3537 struct si_context
*sctx
= (struct si_context
*)ctx
;
3539 /* The hardware can only do sample shading with 2^n samples. */
3540 min_samples
= util_next_power_of_two(min_samples
);
3542 if (sctx
->ps_iter_samples
== min_samples
)
3545 sctx
->ps_iter_samples
= min_samples
;
3546 sctx
->do_update_shaders
= true;
3548 si_update_ps_iter_samples(sctx
);
3556 * Build the sampler view descriptor for a buffer texture.
3557 * @param state 256-bit descriptor; only the high 128 bits are filled in
3559 void si_make_buffer_descriptor(struct si_screen
*screen
, struct si_resource
*buf
,
3560 enum pipe_format format
, unsigned offset
, unsigned size
,
3563 const struct util_format_description
*desc
;
3565 unsigned num_records
;
3567 desc
= util_format_description(format
);
3568 stride
= desc
->block
.bits
/ 8;
3570 num_records
= size
/ stride
;
3571 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3573 /* The NUM_RECORDS field has a different meaning depending on the chip,
3574 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3577 * - If STRIDE == 0, it's in byte units.
3578 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3581 * - For SMEM and STRIDE == 0, it's in byte units.
3582 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3583 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3584 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3585 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3586 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3587 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3588 * That way the same descriptor can be used by both SMEM and VMEM.
3591 * - For SMEM and STRIDE == 0, it's in byte units.
3592 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3593 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3594 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3596 if (screen
->info
.chip_class
== GFX8
)
3597 num_records
*= stride
;
3600 state
[5] = S_008F04_STRIDE(stride
);
3601 state
[6] = num_records
;
3602 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3603 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3604 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3605 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
3607 if (screen
->info
.chip_class
>= GFX10
) {
3608 const struct gfx10_format
*fmt
= &gfx10_format_table
[format
];
3610 /* OOB_SELECT chooses the out-of-bounds check:
3611 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
3612 * - 1: index >= NUM_RECORDS
3613 * - 2: NUM_RECORDS == 0
3614 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
3615 * else: swizzle_address >= NUM_RECORDS
3617 state
[7] |= S_008F0C_FORMAT(fmt
->img_format
) |
3618 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_STRUCTURED_WITH_OFFSET
) |
3619 S_008F0C_RESOURCE_LEVEL(1);
3622 unsigned num_format
, data_format
;
3624 first_non_void
= util_format_get_first_non_void_channel(format
);
3625 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3626 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3628 state
[7] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
3632 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3634 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3636 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3637 /* For the pre-defined border color values (white, opaque
3638 * black, transparent black), the only thing that matters is
3639 * that the alpha channel winds up in the correct place
3640 * (because the RGB channels are all the same) so either of
3641 * these enumerations will work.
3643 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3644 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3646 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3647 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3648 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3649 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3651 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3652 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3653 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3654 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3655 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3662 * Build the sampler view descriptor for a texture.
3664 static void gfx10_make_texture_descriptor(
3665 struct si_screen
*screen
, struct si_texture
*tex
, bool sampler
, enum pipe_texture_target target
,
3666 enum pipe_format pipe_format
, const unsigned char state_swizzle
[4], unsigned first_level
,
3667 unsigned last_level
, unsigned first_layer
, unsigned last_layer
, unsigned width
, unsigned height
,
3668 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3670 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3671 const struct util_format_description
*desc
;
3672 unsigned img_format
;
3673 unsigned char swizzle
[4];
3677 desc
= util_format_description(pipe_format
);
3678 img_format
= gfx10_format_table
[pipe_format
].img_format
;
3680 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3681 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3682 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3683 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3684 bool is_stencil
= false;
3686 switch (pipe_format
) {
3687 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3688 case PIPE_FORMAT_X32_S8X24_UINT
:
3689 case PIPE_FORMAT_X8Z24_UNORM
:
3690 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3693 case PIPE_FORMAT_X24S8_UINT
:
3695 * X24S8 is implemented as an 8_8_8_8 data format, to
3696 * fix texture gathers. This affects at least
3697 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3699 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3703 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3704 is_stencil
= pipe_format
== PIPE_FORMAT_S8_UINT
;
3707 if (tex
->upgraded_depth
&& !is_stencil
) {
3708 assert(img_format
== V_008F0C_IMG_FORMAT_32_FLOAT
);
3709 img_format
= V_008F0C_IMG_FORMAT_32_FLOAT_CLAMP
;
3712 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3715 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
)) {
3716 /* For the purpose of shader images, treat cube maps as 2D
3719 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3721 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3724 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3726 depth
= res
->array_size
;
3727 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3728 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3729 depth
= res
->array_size
;
3730 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3731 depth
= res
->array_size
/ 6;
3734 state
[1] = S_00A004_FORMAT(img_format
) | S_00A004_WIDTH_LO(width
- 1);
3735 state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3736 S_00A008_RESOURCE_LEVEL(1);
3738 S_00A00C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3739 S_00A00C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3740 S_00A00C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3741 S_00A00C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3742 S_00A00C_BASE_LEVEL(res
->nr_samples
> 1 ? 0 : first_level
) |
3743 S_00A00C_LAST_LEVEL(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
) : last_level
) |
3744 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(desc
->swizzle
)) | S_00A00C_TYPE(type
);
3745 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
3746 * to know the total number of layers.
3749 S_00A010_DEPTH((type
== V_008F1C_SQ_RSRC_IMG_3D
&& sampler
) ? depth
- 1 : last_layer
) |
3750 S_00A010_BASE_ARRAY(first_layer
);
3751 state
[5] = S_00A014_ARRAY_PITCH(!!(type
== V_008F1C_SQ_RSRC_IMG_3D
&& !sampler
)) |
3752 S_00A014_MAX_MIP(res
->nr_samples
> 1 ? util_logbase2(res
->nr_samples
)
3753 : tex
->buffer
.b
.b
.last_level
) |
3754 S_00A014_PERF_MOD(4) |
3755 S_00A014_BIG_PAGE(screen
->info
.chip_class
>= GFX10_3
&&
3756 tex
->buffer
.bo_alignment
% (64 * 1024) == 0);
3760 if (vi_dcc_enabled(tex
, first_level
)) {
3761 state
[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B
) |
3762 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex
->surface
.u
.gfx9
.dcc
.max_compressed_block_size
) |
3763 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
3766 /* Initialize the sampler view for FMASK. */
3767 if (tex
->surface
.fmask_offset
) {
3770 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
3772 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3773 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3775 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F1
;
3778 format
= V_008F0C_IMG_FORMAT_FMASK8_S2_F2
;
3781 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F1
;
3784 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F2
;
3787 format
= V_008F0C_IMG_FORMAT_FMASK8_S4_F4
;
3790 format
= V_008F0C_IMG_FORMAT_FMASK8_S8_F1
;
3793 format
= V_008F0C_IMG_FORMAT_FMASK16_S8_F2
;
3796 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F4
;
3799 format
= V_008F0C_IMG_FORMAT_FMASK32_S8_F8
;
3802 format
= V_008F0C_IMG_FORMAT_FMASK16_S16_F1
;
3805 format
= V_008F0C_IMG_FORMAT_FMASK32_S16_F2
;
3808 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F4
;
3811 format
= V_008F0C_IMG_FORMAT_FMASK64_S16_F8
;
3814 unreachable("invalid nr_samples");
3817 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3818 fmask_state
[1] = S_00A004_BASE_ADDRESS_HI(va
>> 40) | S_00A004_FORMAT(format
) |
3819 S_00A004_WIDTH_LO(width
- 1);
3820 fmask_state
[2] = S_00A008_WIDTH_HI((width
- 1) >> 2) | S_00A008_HEIGHT(height
- 1) |
3821 S_00A008_RESOURCE_LEVEL(1);
3823 S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3824 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3825 S_00A00C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3826 S_00A00C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3827 fmask_state
[4] = S_00A010_DEPTH(last_layer
) | S_00A010_BASE_ARRAY(first_layer
);
3829 fmask_state
[6] = S_00A018_META_PIPE_ALIGNED(1);
3835 * Build the sampler view descriptor for a texture (SI-GFX9).
3837 static void si_make_texture_descriptor(struct si_screen
*screen
, struct si_texture
*tex
,
3838 bool sampler
, enum pipe_texture_target target
,
3839 enum pipe_format pipe_format
,
3840 const unsigned char state_swizzle
[4], unsigned first_level
,
3841 unsigned last_level
, unsigned first_layer
,
3842 unsigned last_layer
, unsigned width
, unsigned height
,
3843 unsigned depth
, uint32_t *state
, uint32_t *fmask_state
)
3845 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3846 const struct util_format_description
*desc
;
3847 unsigned char swizzle
[4];
3849 unsigned num_format
, data_format
, type
, num_samples
;
3852 desc
= util_format_description(pipe_format
);
3854 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
? MAX2(1, res
->nr_samples
)
3855 : MAX2(1, res
->nr_storage_samples
);
3857 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3858 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3859 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3860 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3862 switch (pipe_format
) {
3863 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3864 case PIPE_FORMAT_X32_S8X24_UINT
:
3865 case PIPE_FORMAT_X8Z24_UNORM
:
3866 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3868 case PIPE_FORMAT_X24S8_UINT
:
3870 * X24S8 is implemented as an 8_8_8_8 data format, to
3871 * fix texture gathers. This affects at least
3872 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3874 if (screen
->info
.chip_class
<= GFX8
)
3875 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3877 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3880 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3883 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3886 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3888 switch (pipe_format
) {
3889 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3890 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3893 if (first_non_void
< 0) {
3894 if (util_format_is_compressed(pipe_format
)) {
3895 switch (pipe_format
) {
3896 case PIPE_FORMAT_DXT1_SRGB
:
3897 case PIPE_FORMAT_DXT1_SRGBA
:
3898 case PIPE_FORMAT_DXT3_SRGBA
:
3899 case PIPE_FORMAT_DXT5_SRGBA
:
3900 case PIPE_FORMAT_BPTC_SRGBA
:
3901 case PIPE_FORMAT_ETC2_SRGB8
:
3902 case PIPE_FORMAT_ETC2_SRGB8A1
:
3903 case PIPE_FORMAT_ETC2_SRGBA8
:
3904 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3906 case PIPE_FORMAT_RGTC1_SNORM
:
3907 case PIPE_FORMAT_LATC1_SNORM
:
3908 case PIPE_FORMAT_RGTC2_SNORM
:
3909 case PIPE_FORMAT_LATC2_SNORM
:
3910 case PIPE_FORMAT_ETC2_R11_SNORM
:
3911 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3912 /* implies float, so use SNORM/UNORM to determine
3913 whether data is signed or not */
3914 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3915 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3918 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3921 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3922 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3924 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3926 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3927 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3929 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3931 switch (desc
->channel
[first_non_void
].type
) {
3932 case UTIL_FORMAT_TYPE_FLOAT
:
3933 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3935 case UTIL_FORMAT_TYPE_SIGNED
:
3936 if (desc
->channel
[first_non_void
].normalized
)
3937 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3938 else if (desc
->channel
[first_non_void
].pure_integer
)
3939 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3941 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3943 case UTIL_FORMAT_TYPE_UNSIGNED
:
3944 if (desc
->channel
[first_non_void
].normalized
)
3945 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3946 else if (desc
->channel
[first_non_void
].pure_integer
)
3947 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3949 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3954 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3955 if (data_format
== ~0) {
3959 /* S8 with Z32 HTILE needs a special format. */
3960 if (screen
->info
.chip_class
== GFX9
&& pipe_format
== PIPE_FORMAT_S8_UINT
)
3961 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3963 if (!sampler
&& (res
->target
== PIPE_TEXTURE_CUBE
|| res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3964 (screen
->info
.chip_class
<= GFX8
&& res
->target
== PIPE_TEXTURE_3D
))) {
3965 /* For the purpose of shader images, treat cube maps and 3D
3966 * textures as 2D arrays. For 3D textures, the address
3967 * calculations for mipmaps are different, so we rely on the
3968 * caller to effectively disable mipmaps.
3970 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3972 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3974 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
3977 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3979 depth
= res
->array_size
;
3980 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
|| type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3981 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3982 depth
= res
->array_size
;
3983 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3984 depth
= res
->array_size
/ 6;
3987 state
[1] = (S_008F14_DATA_FORMAT(data_format
) | S_008F14_NUM_FORMAT(num_format
));
3988 state
[2] = (S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1) | S_008F18_PERF_MOD(4));
3989 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3990 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3991 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3992 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3993 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
3994 S_008F1C_LAST_LEVEL(num_samples
> 1 ? util_logbase2(num_samples
) : last_level
) |
3995 S_008F1C_TYPE(type
));
3997 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4001 if (screen
->info
.chip_class
== GFX9
) {
4002 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
4004 /* Depth is the the last accessible layer on Gfx9.
4005 * The hw doesn't need to know the total number of layers.
4007 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
4008 state
[4] |= S_008F20_DEPTH(depth
- 1);
4010 state
[4] |= S_008F20_DEPTH(last_layer
);
4012 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
4013 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ? util_logbase2(num_samples
)
4014 : tex
->buffer
.b
.b
.last_level
);
4016 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
4017 state
[4] |= S_008F20_DEPTH(depth
- 1);
4018 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4021 if (vi_dcc_enabled(tex
, first_level
)) {
4022 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen
, pipe_format
));
4024 /* The last dword is unused by hw. The shader uses it to clear
4025 * bits in the first dword of sampler state.
4027 if (screen
->info
.chip_class
<= GFX7
&& res
->nr_samples
<= 1) {
4028 if (first_level
== last_level
)
4029 state
[7] = C_008F30_MAX_ANISO_RATIO
;
4031 state
[7] = 0xffffffff;
4035 /* Initialize the sampler view for FMASK. */
4036 if (tex
->surface
.fmask_offset
) {
4037 uint32_t data_format
, num_format
;
4039 va
= tex
->buffer
.gpu_address
+ tex
->surface
.fmask_offset
;
4041 #define FMASK(s, f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
4042 if (screen
->info
.chip_class
== GFX9
) {
4043 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
4044 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4046 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_8_2_1
;
4049 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_8_2_2
;
4052 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_8_4_1
;
4055 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_8_4_2
;
4058 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_8_4_4
;
4061 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_8_8_1
;
4064 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_16_8_2
;
4067 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_32_8_4
;
4070 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_32_8_8
;
4073 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_16_16_1
;
4076 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_32_16_2
;
4079 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_64_16_4
;
4082 num_format
= V_008F14_IMG_NUM_FORMAT_FMASK_64_16_8
;
4085 unreachable("invalid nr_samples");
4088 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
4090 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
4093 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
4096 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
4099 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
4102 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
4105 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
4108 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
4111 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
4114 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
4117 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
4120 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
4123 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
4126 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
4129 unreachable("invalid nr_samples");
4131 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
4135 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
4136 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) | S_008F14_DATA_FORMAT(data_format
) |
4137 S_008F14_NUM_FORMAT(num_format
);
4138 fmask_state
[2] = S_008F18_WIDTH(width
- 1) | S_008F18_HEIGHT(height
- 1);
4140 S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
4141 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) | S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
4142 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
4144 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
4148 if (screen
->info
.chip_class
== GFX9
) {
4149 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
4151 S_008F20_DEPTH(last_layer
) | S_008F20_PITCH(tex
->surface
.u
.gfx9
.fmask
.epitch
);
4152 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(1) |
4153 S_008F24_META_RB_ALIGNED(1);
4155 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
4156 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
4157 S_008F20_PITCH(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
4158 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
4164 * Create a sampler view.
4166 * @param ctx context
4167 * @param texture texture
4168 * @param state sampler view template
4169 * @param width0 width0 override (for compressed textures as int)
4170 * @param height0 height0 override (for compressed textures as int)
4171 * @param force_level set the base address to the level (for compressed textures)
4173 struct pipe_sampler_view
*si_create_sampler_view_custom(struct pipe_context
*ctx
,
4174 struct pipe_resource
*texture
,
4175 const struct pipe_sampler_view
*state
,
4176 unsigned width0
, unsigned height0
,
4177 unsigned force_level
)
4179 struct si_context
*sctx
= (struct si_context
*)ctx
;
4180 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4181 struct si_texture
*tex
= (struct si_texture
*)texture
;
4182 unsigned base_level
, first_level
, last_level
;
4183 unsigned char state_swizzle
[4];
4184 unsigned height
, depth
, width
;
4185 unsigned last_layer
= state
->u
.tex
.last_layer
;
4186 enum pipe_format pipe_format
;
4187 const struct legacy_surf_level
*surflevel
;
4192 /* initialize base object */
4193 view
->base
= *state
;
4194 view
->base
.texture
= NULL
;
4195 view
->base
.reference
.count
= 1;
4196 view
->base
.context
= ctx
;
4199 pipe_resource_reference(&view
->base
.texture
, texture
);
4201 if (state
->format
== PIPE_FORMAT_X24S8_UINT
|| state
->format
== PIPE_FORMAT_S8X24_UINT
||
4202 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
|| state
->format
== PIPE_FORMAT_S8_UINT
)
4203 view
->is_stencil_sampler
= true;
4205 /* Buffer resource. */
4206 if (texture
->target
== PIPE_BUFFER
) {
4207 si_make_buffer_descriptor(sctx
->screen
, si_resource(texture
), state
->format
,
4208 state
->u
.buf
.offset
, state
->u
.buf
.size
, view
->state
);
4212 state_swizzle
[0] = state
->swizzle_r
;
4213 state_swizzle
[1] = state
->swizzle_g
;
4214 state_swizzle
[2] = state
->swizzle_b
;
4215 state_swizzle
[3] = state
->swizzle_a
;
4218 first_level
= state
->u
.tex
.first_level
;
4219 last_level
= state
->u
.tex
.last_level
;
4222 depth
= texture
->depth0
;
4224 if (sctx
->chip_class
<= GFX8
&& force_level
) {
4225 assert(force_level
== first_level
&& force_level
== last_level
);
4226 base_level
= force_level
;
4229 width
= u_minify(width
, force_level
);
4230 height
= u_minify(height
, force_level
);
4231 depth
= u_minify(depth
, force_level
);
4234 /* This is not needed if gallium frontends set last_layer correctly. */
4235 if (state
->target
== PIPE_TEXTURE_1D
|| state
->target
== PIPE_TEXTURE_2D
||
4236 state
->target
== PIPE_TEXTURE_RECT
|| state
->target
== PIPE_TEXTURE_CUBE
)
4237 last_layer
= state
->u
.tex
.first_layer
;
4239 /* Texturing with separate depth and stencil. */
4240 pipe_format
= state
->format
;
4242 /* Depth/stencil texturing sometimes needs separate texture. */
4243 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4244 if (!tex
->flushed_depth_texture
&& !si_init_flushed_depth_texture(ctx
, texture
)) {
4245 pipe_resource_reference(&view
->base
.texture
, NULL
);
4250 assert(tex
->flushed_depth_texture
);
4252 /* Override format for the case where the flushed texture
4253 * contains only Z or only S.
4255 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4256 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4258 tex
= tex
->flushed_depth_texture
;
4261 surflevel
= tex
->surface
.u
.legacy
.level
;
4263 if (tex
->db_compatible
) {
4264 if (!view
->is_stencil_sampler
)
4265 pipe_format
= tex
->db_render_format
;
4267 switch (pipe_format
) {
4268 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4269 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4271 case PIPE_FORMAT_X8Z24_UNORM
:
4272 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4273 /* Z24 is always stored like this for DB
4276 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4278 case PIPE_FORMAT_X24S8_UINT
:
4279 case PIPE_FORMAT_S8X24_UINT
:
4280 case PIPE_FORMAT_X32_S8X24_UINT
:
4281 pipe_format
= PIPE_FORMAT_S8_UINT
;
4282 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4288 view
->dcc_incompatible
=
4289 vi_dcc_formats_are_incompatible(texture
, state
->u
.tex
.first_level
, state
->format
);
4291 sctx
->screen
->make_texture_descriptor(
4292 sctx
->screen
, tex
, true, state
->target
, pipe_format
, state_swizzle
, first_level
, last_level
,
4293 state
->u
.tex
.first_layer
, last_layer
, width
, height
, depth
, view
->state
, view
->fmask_state
);
4295 const struct util_format_description
*desc
= util_format_description(pipe_format
);
4296 view
->is_integer
= false;
4298 for (unsigned i
= 0; i
< desc
->nr_channels
; ++i
) {
4299 if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_VOID
)
4302 /* Whether the number format is {U,S}{SCALED,INT} */
4303 view
->is_integer
= (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
||
4304 desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) &&
4305 (desc
->channel
[i
].pure_integer
|| !desc
->channel
[i
].normalized
);
4309 view
->base_level_info
= &surflevel
[base_level
];
4310 view
->base_level
= base_level
;
4311 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4315 static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context
*ctx
,
4316 struct pipe_resource
*texture
,
4317 const struct pipe_sampler_view
*state
)
4319 return si_create_sampler_view_custom(ctx
, texture
, state
, texture
? texture
->width0
: 0,
4320 texture
? texture
->height0
: 0, 0);
4323 static void si_sampler_view_destroy(struct pipe_context
*ctx
, struct pipe_sampler_view
*state
)
4325 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4327 pipe_resource_reference(&state
->texture
, NULL
);
4331 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4333 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4334 (linear_filter
&& (wrap
== PIPE_TEX_WRAP_CLAMP
|| wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4337 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4338 const struct pipe_sampler_state
*state
,
4339 const union pipe_color_union
*color
, bool is_integer
)
4341 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4342 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4344 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4345 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4346 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4347 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4349 #define simple_border_types(elt) \
4351 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 0) \
4352 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4353 if (color->elt[0] == 0 && color->elt[1] == 0 && color->elt[2] == 0 && color->elt[3] == 1) \
4354 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4355 if (color->elt[0] == 1 && color->elt[1] == 1 && color->elt[2] == 1 && color->elt[3] == 1) \
4356 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4360 simple_border_types(ui
);
4362 simple_border_types(f
);
4364 #undef simple_border_types
4368 /* Check if the border has been uploaded already. */
4369 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4370 if (memcmp(&sctx
->border_color_table
[i
], color
, sizeof(*color
)) == 0)
4373 if (i
>= SI_MAX_BORDER_COLORS
) {
4374 /* Getting 4096 unique border colors is very unlikely. */
4375 fprintf(stderr
, "radeonsi: The border color table is full. "
4376 "Any new border colors will be just black. "
4377 "Please file a bug.\n");
4378 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4381 if (i
== sctx
->border_color_count
) {
4382 /* Upload a new border color. */
4383 memcpy(&sctx
->border_color_table
[i
], color
, sizeof(*color
));
4384 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
], color
, sizeof(*color
));
4385 sctx
->border_color_count
++;
4388 return S_008F3C_BORDER_COLOR_PTR(i
) |
4389 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4392 static inline int S_FIXED(float value
, unsigned frac_bits
)
4394 return value
* (1 << frac_bits
);
4397 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4399 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4400 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4401 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4403 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4404 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4407 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4420 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4421 const struct pipe_sampler_state
*state
)
4423 struct si_context
*sctx
= (struct si_context
*)ctx
;
4424 struct si_screen
*sscreen
= sctx
->screen
;
4425 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4426 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
: state
->max_anisotropy
;
4427 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4428 bool trunc_coord
= state
->min_img_filter
== PIPE_TEX_FILTER_NEAREST
&&
4429 state
->mag_img_filter
== PIPE_TEX_FILTER_NEAREST
&&
4430 state
->compare_mode
== PIPE_TEX_COMPARE_NONE
;
4431 union pipe_color_union clamped_border_color
;
4438 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4441 (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) | S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4442 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) | S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4443 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4444 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4445 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) | S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4446 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4447 S_008F30_TRUNC_COORD(trunc_coord
) |
4448 S_008F30_COMPAT_MODE(sctx
->chip_class
== GFX8
|| sctx
->chip_class
== GFX9
));
4449 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4450 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4451 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4452 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4453 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4454 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4455 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4456 S_008F38_MIP_POINT_PRECLAMP(0));
4457 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4459 if (sscreen
->info
.chip_class
>= GFX10
) {
4460 rstate
->val
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
4462 rstate
->val
[2] |= S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= GFX8
) |
4463 S_008F38_FILTER_PREC_FIX(1) |
4464 S_008F38_ANISO_OVERRIDE_GFX8(sctx
->chip_class
>= GFX8
);
4467 /* Create sampler resource for integer textures. */
4468 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4469 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4471 /* Create sampler resource for upgraded depth textures. */
4472 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4474 for (unsigned i
= 0; i
< 4; ++i
) {
4475 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4476 * when the border color is 1.0. */
4477 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4480 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0) {
4481 if (sscreen
->info
.chip_class
<= GFX9
)
4482 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4484 rstate
->upgraded_depth_val
[3] =
4485 si_translate_border_color(sctx
, state
, &clamped_border_color
, false);
4491 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4493 struct si_context
*sctx
= (struct si_context
*)ctx
;
4495 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4498 sctx
->sample_mask
= sample_mask
;
4499 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4502 static void si_emit_sample_mask(struct si_context
*sctx
)
4504 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4505 unsigned mask
= sctx
->sample_mask
;
4507 /* Needed for line and polygon smoothing as well as for the Polaris
4508 * small primitive filter. We expect the gallium frontend to take care of
4511 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4512 (mask
& 1 && sctx
->blitter
->running
));
4514 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4515 radeon_emit(cs
, mask
| (mask
<< 16));
4516 radeon_emit(cs
, mask
| (mask
<< 16));
4519 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4522 struct si_sampler_state
*s
= state
;
4524 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4531 * Vertex elements & buffers
4534 struct si_fast_udiv_info32
si_compute_fast_udiv_info32(uint32_t D
, unsigned num_bits
)
4536 struct util_fast_udiv_info info
= util_compute_fast_udiv_info(D
, num_bits
, 32);
4538 struct si_fast_udiv_info32 result
= {
4547 static void *si_create_vertex_elements(struct pipe_context
*ctx
, unsigned count
,
4548 const struct pipe_vertex_element
*elements
)
4550 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4551 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4552 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4553 struct si_fast_udiv_info32 divisor_factors
[SI_MAX_ATTRIBS
] = {};
4554 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32
) == 16);
4555 STATIC_ASSERT(sizeof(divisor_factors
[0].multiplier
) == 4);
4556 STATIC_ASSERT(sizeof(divisor_factors
[0].pre_shift
) == 4);
4557 STATIC_ASSERT(sizeof(divisor_factors
[0].post_shift
) == 4);
4558 STATIC_ASSERT(sizeof(divisor_factors
[0].increment
) == 4);
4561 assert(count
<= SI_MAX_ATTRIBS
);
4567 unsigned alloc_count
=
4568 count
> sscreen
->num_vbos_in_user_sgprs
? count
- sscreen
->num_vbos_in_user_sgprs
: 0;
4569 v
->vb_desc_list_alloc_size
= align(alloc_count
* 16, SI_CPDMA_ALIGNMENT
);
4571 for (i
= 0; i
< count
; ++i
) {
4572 const struct util_format_description
*desc
;
4573 const struct util_format_channel_description
*channel
;
4575 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4577 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4582 unsigned instance_divisor
= elements
[i
].instance_divisor
;
4583 if (instance_divisor
) {
4584 v
->uses_instance_divisors
= true;
4586 if (instance_divisor
== 1) {
4587 v
->instance_divisor_is_one
|= 1u << i
;
4589 v
->instance_divisor_is_fetched
|= 1u << i
;
4590 divisor_factors
[i
] = si_compute_fast_udiv_info32(instance_divisor
, 32);
4594 if (!used
[vbo_index
]) {
4595 v
->first_vb_use_mask
|= 1 << i
;
4596 used
[vbo_index
] = true;
4599 desc
= util_format_description(elements
[i
].src_format
);
4600 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4601 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4603 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4604 v
->src_offset
[i
] = elements
[i
].src_offset
;
4605 v
->vertex_buffer_index
[i
] = vbo_index
;
4607 bool always_fix
= false;
4608 union si_vs_fix_fetch fix_fetch
;
4609 unsigned log_hw_load_size
; /* the load element size as seen by the hardware */
4612 log_hw_load_size
= MIN2(2, util_logbase2(desc
->block
.bits
) - 3);
4615 switch (channel
->type
) {
4616 case UTIL_FORMAT_TYPE_FLOAT
:
4617 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4619 case UTIL_FORMAT_TYPE_FIXED
:
4620 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4622 case UTIL_FORMAT_TYPE_SIGNED
: {
4623 if (channel
->pure_integer
)
4624 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SINT
;
4625 else if (channel
->normalized
)
4626 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SNORM
;
4628 fix_fetch
.u
.format
= AC_FETCH_FORMAT_SSCALED
;
4631 case UTIL_FORMAT_TYPE_UNSIGNED
: {
4632 if (channel
->pure_integer
)
4633 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UINT
;
4634 else if (channel
->normalized
)
4635 fix_fetch
.u
.format
= AC_FETCH_FORMAT_UNORM
;
4637 fix_fetch
.u
.format
= AC_FETCH_FORMAT_USCALED
;
4641 unreachable("bad format type");
4644 switch (elements
[i
].src_format
) {
4645 case PIPE_FORMAT_R11G11B10_FLOAT
:
4646 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FLOAT
;
4649 unreachable("bad other format");
4653 if (desc
->channel
[0].size
== 10) {
4654 fix_fetch
.u
.log_size
= 3; /* special encoding for 2_10_10_10 */
4655 log_hw_load_size
= 2;
4657 /* The hardware always treats the 2-bit alpha channel as
4658 * unsigned, so a shader workaround is needed. The affected
4659 * chips are GFX8 and older except Stoney (GFX8.1).
4661 always_fix
= sscreen
->info
.chip_class
<= GFX8
&& sscreen
->info
.family
!= CHIP_STONEY
&&
4662 channel
->type
== UTIL_FORMAT_TYPE_SIGNED
;
4663 } else if (elements
[i
].src_format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
4664 fix_fetch
.u
.log_size
= 3; /* special encoding */
4665 fix_fetch
.u
.format
= AC_FETCH_FORMAT_FIXED
;
4666 log_hw_load_size
= 2;
4668 fix_fetch
.u
.log_size
= util_logbase2(channel
->size
) - 3;
4669 fix_fetch
.u
.num_channels_m1
= desc
->nr_channels
- 1;
4672 * - doubles (multiple loads + truncate to float)
4673 * - 32-bit requiring a conversion
4675 always_fix
= (fix_fetch
.u
.log_size
== 3) ||
4676 (fix_fetch
.u
.log_size
== 2 && fix_fetch
.u
.format
!= AC_FETCH_FORMAT_FLOAT
&&
4677 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_UINT
&&
4678 fix_fetch
.u
.format
!= AC_FETCH_FORMAT_SINT
);
4680 /* Also fixup 8_8_8 and 16_16_16. */
4681 if (desc
->nr_channels
== 3 && fix_fetch
.u
.log_size
<= 1) {
4683 log_hw_load_size
= fix_fetch
.u
.log_size
;
4687 if (desc
->swizzle
[0] != PIPE_SWIZZLE_X
) {
4688 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_Z
&&
4689 (desc
->swizzle
[2] == PIPE_SWIZZLE_X
|| desc
->swizzle
[2] == PIPE_SWIZZLE_0
));
4690 fix_fetch
.u
.reverse
= 1;
4693 /* Force the workaround for unaligned access here already if the
4694 * offset relative to the vertex buffer base is unaligned.
4696 * There is a theoretical case in which this is too conservative:
4697 * if the vertex buffer's offset is also unaligned in just the
4698 * right way, we end up with an aligned address after all.
4699 * However, this case should be extremely rare in practice (it
4700 * won't happen in well-behaved applications), and taking it
4701 * into account would complicate the fast path (where everything
4702 * is nicely aligned).
4704 bool check_alignment
=
4705 log_hw_load_size
>= 1 &&
4706 (sscreen
->info
.chip_class
== GFX6
|| sscreen
->info
.chip_class
>= GFX10
);
4707 bool opencode
= sscreen
->options
.vs_fetch_always_opencode
;
4709 if (check_alignment
&& (elements
[i
].src_offset
& ((1 << log_hw_load_size
) - 1)) != 0)
4712 if (always_fix
|| check_alignment
|| opencode
)
4713 v
->fix_fetch
[i
] = fix_fetch
.bits
;
4716 v
->fix_fetch_opencode
|= 1 << i
;
4717 if (opencode
|| always_fix
)
4718 v
->fix_fetch_always
|= 1 << i
;
4720 if (check_alignment
&& !opencode
) {
4721 assert(log_hw_load_size
== 1 || log_hw_load_size
== 2);
4723 v
->fix_fetch_unaligned
|= 1 << i
;
4724 v
->hw_load_is_dword
|= (log_hw_load_size
- 1) << i
;
4725 v
->vb_alignment_check_mask
|= 1 << vbo_index
;
4728 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
4729 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
4730 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
4731 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3]));
4733 if (sscreen
->info
.chip_class
>= GFX10
) {
4734 const struct gfx10_format
*fmt
= &gfx10_format_table
[elements
[i
].src_format
];
4735 assert(fmt
->img_format
!= 0 && fmt
->img_format
< 128);
4736 v
->rsrc_word3
[i
] |= S_008F0C_FORMAT(fmt
->img_format
) | S_008F0C_RESOURCE_LEVEL(1);
4738 unsigned data_format
, num_format
;
4739 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4740 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4741 v
->rsrc_word3
[i
] |= S_008F0C_NUM_FORMAT(num_format
) | S_008F0C_DATA_FORMAT(data_format
);
4745 if (v
->instance_divisor_is_fetched
) {
4746 unsigned num_divisors
= util_last_bit(v
->instance_divisor_is_fetched
);
4748 v
->instance_divisor_factor_buffer
= (struct si_resource
*)pipe_buffer_create(
4749 &sscreen
->b
, 0, PIPE_USAGE_DEFAULT
, num_divisors
* sizeof(divisor_factors
[0]));
4750 if (!v
->instance_divisor_factor_buffer
) {
4755 sscreen
->ws
->buffer_map(v
->instance_divisor_factor_buffer
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
4756 memcpy(map
, divisor_factors
, num_divisors
* sizeof(divisor_factors
[0]));
4761 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4763 struct si_context
*sctx
= (struct si_context
*)ctx
;
4764 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4765 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4767 sctx
->vertex_elements
= v
;
4768 sctx
->num_vertex_elements
= v
? v
->count
: 0;
4770 if (sctx
->num_vertex_elements
) {
4771 sctx
->vertex_buffers_dirty
= true;
4773 sctx
->vertex_buffer_pointer_dirty
= false;
4774 sctx
->vertex_buffer_user_sgprs_dirty
= false;
4777 if (v
&& (!old
|| old
->count
!= v
->count
||
4778 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4779 /* we don't check which divisors changed */
4780 v
->uses_instance_divisors
||
4781 (old
->vb_alignment_check_mask
^ v
->vb_alignment_check_mask
) &
4782 sctx
->vertex_buffer_unaligned
||
4783 ((v
->vb_alignment_check_mask
& sctx
->vertex_buffer_unaligned
) &&
4784 memcmp(old
->vertex_buffer_index
, v
->vertex_buffer_index
,
4785 sizeof(v
->vertex_buffer_index
[0]) * v
->count
)) ||
4786 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4787 * functions of fix_fetch and the src_offset alignment.
4788 * If they change and fix_fetch doesn't, it must be due to different
4789 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4790 old
->fix_fetch_opencode
!= v
->fix_fetch_opencode
||
4791 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4792 sctx
->do_update_shaders
= true;
4794 if (v
&& v
->instance_divisor_is_fetched
) {
4795 struct pipe_constant_buffer cb
;
4797 cb
.buffer
= &v
->instance_divisor_factor_buffer
->b
.b
;
4798 cb
.user_buffer
= NULL
;
4799 cb
.buffer_offset
= 0;
4800 cb
.buffer_size
= 0xffffffff;
4801 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4805 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4807 struct si_context
*sctx
= (struct si_context
*)ctx
;
4808 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4810 if (sctx
->vertex_elements
== state
) {
4811 sctx
->vertex_elements
= NULL
;
4812 sctx
->num_vertex_elements
= 0;
4814 si_resource_reference(&v
->instance_divisor_factor_buffer
, NULL
);
4818 static void si_set_vertex_buffers(struct pipe_context
*ctx
, unsigned start_slot
, unsigned count
,
4819 const struct pipe_vertex_buffer
*buffers
)
4821 struct si_context
*sctx
= (struct si_context
*)ctx
;
4822 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4823 unsigned updated_mask
= u_bit_consecutive(start_slot
, count
);
4824 uint32_t orig_unaligned
= sctx
->vertex_buffer_unaligned
;
4825 uint32_t unaligned
= 0;
4828 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4831 for (i
= 0; i
< count
; i
++) {
4832 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4833 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4834 struct pipe_resource
*buf
= src
->buffer
.resource
;
4835 unsigned slot_bit
= 1 << (start_slot
+ i
);
4837 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4838 dsti
->buffer_offset
= src
->buffer_offset
;
4839 dsti
->stride
= src
->stride
;
4841 if (dsti
->buffer_offset
& 3 || dsti
->stride
& 3)
4842 unaligned
|= slot_bit
;
4844 si_context_add_resource_size(sctx
, buf
);
4846 si_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4849 for (i
= 0; i
< count
; i
++) {
4850 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4852 unaligned
&= ~updated_mask
;
4854 sctx
->vertex_buffers_dirty
= true;
4855 sctx
->vertex_buffer_unaligned
= (orig_unaligned
& ~updated_mask
) | unaligned
;
4857 /* Check whether alignment may have changed in a way that requires
4858 * shader changes. This check is conservative: a vertex buffer can only
4859 * trigger a shader change if the misalignment amount changes (e.g.
4860 * from byte-aligned to short-aligned), but we only keep track of
4861 * whether buffers are at least dword-aligned, since that should always
4862 * be the case in well-behaved applications anyway.
4864 if (sctx
->vertex_elements
&& (sctx
->vertex_elements
->vb_alignment_check_mask
&
4865 (unaligned
| orig_unaligned
) & updated_mask
))
4866 sctx
->do_update_shaders
= true;
4873 static void si_set_tess_state(struct pipe_context
*ctx
, const float default_outer_level
[4],
4874 const float default_inner_level
[2])
4876 struct si_context
*sctx
= (struct si_context
*)ctx
;
4877 struct pipe_constant_buffer cb
;
4880 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4881 memcpy(array
+ 4, default_inner_level
, sizeof(float) * 2);
4884 cb
.user_buffer
= NULL
;
4885 cb
.buffer_size
= sizeof(array
);
4887 si_upload_const_buffer(sctx
, (struct si_resource
**)&cb
.buffer
, (void *)array
, sizeof(array
),
4890 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4891 pipe_resource_reference(&cb
.buffer
, NULL
);
4894 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4896 struct si_context
*sctx
= (struct si_context
*)ctx
;
4898 si_update_fb_dirtiness_after_rendering(sctx
);
4900 /* Multisample surfaces are flushed in si_decompress_textures. */
4901 if (sctx
->framebuffer
.uncompressed_cb_mask
) {
4902 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4903 sctx
->framebuffer
.CB_has_shader_readable_metadata
,
4904 sctx
->framebuffer
.all_DCC_pipe_aligned
);
4908 /* This only ensures coherency for shader image/buffer stores. */
4909 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4911 struct si_context
*sctx
= (struct si_context
*)ctx
;
4913 if (!(flags
& ~PIPE_BARRIER_UPDATE
))
4916 /* Subsequent commands must wait for all shader invocations to
4918 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
| SI_CONTEXT_CS_PARTIAL_FLUSH
;
4920 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4921 sctx
->flags
|= SI_CONTEXT_INV_SCACHE
| SI_CONTEXT_INV_VCACHE
;
4923 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
| PIPE_BARRIER_SHADER_BUFFER
| PIPE_BARRIER_TEXTURE
|
4924 PIPE_BARRIER_IMAGE
| PIPE_BARRIER_STREAMOUT_BUFFER
| PIPE_BARRIER_GLOBAL_BUFFER
)) {
4925 /* As far as I can tell, L1 contents are written back to L2
4926 * automatically at end of shader, but the contents of other
4927 * L1 caches might still be stale. */
4928 sctx
->flags
|= SI_CONTEXT_INV_VCACHE
;
4931 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4932 /* Indices are read through TC L2 since GFX8.
4935 if (sctx
->screen
->info
.chip_class
<= GFX7
)
4936 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4939 /* MSAA color, any depth and any stencil are flushed in
4940 * si_decompress_textures when needed.
4942 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&& sctx
->framebuffer
.uncompressed_cb_mask
) {
4943 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4945 if (sctx
->chip_class
<= GFX8
)
4946 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4949 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4950 if (sctx
->screen
->info
.chip_class
<= GFX8
&& flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4951 sctx
->flags
|= SI_CONTEXT_WB_L2
;
4954 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4956 struct pipe_blend_state blend
;
4958 memset(&blend
, 0, sizeof(blend
));
4959 blend
.independent_blend_enable
= true;
4960 blend
.rt
[0].colormask
= 0xf;
4961 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4964 void si_init_state_compute_functions(struct si_context
*sctx
)
4966 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4967 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4968 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4969 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4970 sctx
->b
.memory_barrier
= si_memory_barrier
;
4973 void si_init_state_functions(struct si_context
*sctx
)
4975 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
4976 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
4977 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
4978 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
4979 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
4980 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
4981 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
4982 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
4983 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
4984 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
4985 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
4987 sctx
->b
.create_blend_state
= si_create_blend_state
;
4988 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4989 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4990 sctx
->b
.set_blend_color
= si_set_blend_color
;
4992 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4993 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4994 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4996 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4997 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4998 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
5000 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
5001 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
5002 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
5003 sctx
->custom_blend_eliminate_fastclear
=
5004 si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
5005 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
5007 sctx
->b
.set_clip_state
= si_set_clip_state
;
5008 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
5010 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
5012 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
5014 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
5015 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
5016 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
5017 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
5019 sctx
->b
.texture_barrier
= si_texture_barrier
;
5020 sctx
->b
.set_min_samples
= si_set_min_samples
;
5021 sctx
->b
.set_tess_state
= si_set_tess_state
;
5023 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
5026 void si_init_screen_state_functions(struct si_screen
*sscreen
)
5028 sscreen
->b
.is_format_supported
= si_is_format_supported
;
5030 if (sscreen
->info
.chip_class
>= GFX10
) {
5031 sscreen
->make_texture_descriptor
= gfx10_make_texture_descriptor
;
5033 sscreen
->make_texture_descriptor
= si_make_texture_descriptor
;
5037 static void si_set_grbm_gfx_index(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned value
)
5039 unsigned reg
= sctx
->chip_class
>= GFX7
? R_030800_GRBM_GFX_INDEX
: R_00802C_GRBM_GFX_INDEX
;
5040 si_pm4_set_reg(pm4
, reg
, value
);
5043 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
, struct si_pm4_state
*pm4
, unsigned se
)
5045 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
5046 si_set_grbm_gfx_index(sctx
, pm4
,
5047 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) : S_030800_SE_INDEX(se
)) |
5048 S_030800_SH_BROADCAST_WRITES(1) |
5049 S_030800_INSTANCE_BROADCAST_WRITES(1));
5052 static void si_write_harvested_raster_configs(struct si_context
*sctx
, struct si_pm4_state
*pm4
,
5053 unsigned raster_config
, unsigned raster_config_1
)
5055 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
5056 unsigned raster_config_se
[4];
5059 ac_get_harvested_configs(&sctx
->screen
->info
, raster_config
, &raster_config_1
, raster_config_se
);
5061 for (se
= 0; se
< num_se
; se
++) {
5062 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
5063 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
5065 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
5067 if (sctx
->chip_class
>= GFX7
) {
5068 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5072 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
5074 struct si_screen
*sscreen
= sctx
->screen
;
5075 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
5076 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
5077 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
5078 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
5080 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
5081 /* Always use the default config when all backends are enabled
5082 * (or when we failed to determine the enabled backends).
5084 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config
);
5085 if (sctx
->chip_class
>= GFX7
)
5086 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
5088 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
5092 void si_init_cs_preamble_state(struct si_context
*sctx
, bool uses_reg_shadowing
)
5094 struct si_screen
*sscreen
= sctx
->screen
;
5095 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
5096 bool has_clear_state
= sscreen
->info
.has_clear_state
;
5097 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
5102 if (!uses_reg_shadowing
) {
5103 si_pm4_cmd_add(pm4
, PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
5104 si_pm4_cmd_add(pm4
, CC0_UPDATE_LOAD_ENABLES(1));
5105 si_pm4_cmd_add(pm4
, CC1_UPDATE_SHADOW_ENABLES(1));
5107 if (has_clear_state
) {
5108 si_pm4_cmd_add(pm4
, PKT3(PKT3_CLEAR_STATE
, 0, 0));
5109 si_pm4_cmd_add(pm4
, 0);
5113 /* CLEAR_STATE doesn't restore these correctly. */
5114 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
5115 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
5116 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5118 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
5119 if (!has_clear_state
)
5120 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
5122 if (!has_clear_state
) {
5123 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
5124 S_028230_ER_TRI(0xA) | S_028230_ER_POINT(0xA) | S_028230_ER_RECT(0xA) |
5125 /* Required by DX10_DIAMOND_TEST_ENA: */
5126 S_028230_ER_LINE_LR(0x1A) | S_028230_ER_LINE_RL(0x26) |
5127 S_028230_ER_LINE_TB(0xA) | S_028230_ER_LINE_BT(0xA));
5128 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
5129 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
5130 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
5131 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
5132 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
5133 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
5134 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
5135 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
5136 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
5139 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5140 if (sctx
->chip_class
>= GFX7
)
5141 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, S_028084_ADDRESS(border_color_va
>> 40));
5143 if (sctx
->chip_class
== GFX6
) {
5144 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
,
5145 S_008A14_NUM_CLIP_SEQ(3) | S_008A14_CLIP_VTX_REORDER_ENA(1));
5148 if (sctx
->chip_class
<= GFX7
|| !has_clear_state
) {
5149 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5150 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5152 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5153 * I don't know why. Deduced by trial and error.
5155 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
5156 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
5157 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
5158 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
5159 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5162 if (sctx
->chip_class
>= GFX7
) {
5163 /* Compute LATE_ALLOC_VS.LIMIT. */
5164 unsigned num_cu_per_sh
= sscreen
->info
.min_good_cu_per_sa
;
5165 unsigned late_alloc_wave64
= 0; /* The limit is per SA. */
5166 unsigned cu_mask_vs
= 0xffff;
5167 unsigned cu_mask_gs
= 0xffff;
5169 if (sctx
->chip_class
>= GFX10
) {
5170 /* For Wave32, the hw will launch twice the number of late
5171 * alloc waves, so 1 == 2x wave32.
5173 if (!sscreen
->info
.use_late_alloc
) {
5174 late_alloc_wave64
= 0;
5175 } else if (num_cu_per_sh
<= 6) {
5176 late_alloc_wave64
= num_cu_per_sh
- 2;
5178 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5180 /* CU2 & CU3 disabled because of the dual CU design */
5181 /* Late alloc is not used for NGG on Navi14 due to a hw bug. */
5182 cu_mask_vs
= 0xfff3;
5183 cu_mask_gs
= sscreen
->use_ngg
&& sctx
->family
!= CHIP_NAVI14
? 0xfff3 : 0xffff;
5186 if (!sscreen
->info
.use_late_alloc
) {
5187 late_alloc_wave64
= 0;
5188 } else if (num_cu_per_sh
<= 4) {
5189 /* Too few available compute units per SA. Disallowing
5190 * VS to run on one CU could hurt us more than late VS
5191 * allocation would help.
5193 * 2 is the highest safe number that allows us to keep
5196 late_alloc_wave64
= 2;
5198 /* This is a good initial value, allowing 1 late_alloc
5199 * wave per SIMD on num_cu - 2.
5201 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
5204 if (late_alloc_wave64
> 2)
5205 cu_mask_vs
= 0xfffe; /* 1 CU disabled */
5208 /* VS can't execute on one CU if the limit is > 2. */
5209 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5210 S_00B118_CU_EN(cu_mask_vs
) | S_00B118_WAVE_LIMIT(0x3F));
5211 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(late_alloc_wave64
));
5212 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5213 S_00B21C_CU_EN(cu_mask_gs
) | S_00B21C_WAVE_LIMIT(0x3F));
5214 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5215 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5218 if (sctx
->chip_class
<= GFX8
) {
5219 si_set_raster_config(sctx
, pm4
);
5221 /* FIXME calculate these values somehow ??? */
5222 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
5223 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
5225 /* These registers, when written, also overwrite the CLEAR_STATE
5226 * context, so we can't rely on CLEAR_STATE setting them.
5227 * It would be an issue if there was another UMD changing them.
5229 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
5230 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
5231 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
5234 if (sctx
->chip_class
>= GFX7
&& sctx
->chip_class
<= GFX8
) {
5235 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
5236 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5237 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, S_00B41C_WAVE_LIMIT(0x3F));
5238 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5239 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5241 /* If this is 0, Bonaire can hang even if GS isn't being used.
5242 * Other chips are unaffected. These are suboptimal values,
5243 * but we don't use on-chip GS.
5245 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5246 S_028A44_ES_VERTS_PER_SUBGRP(64) | S_028A44_GS_PRIMS_PER_SUBGRP(4));
5249 if (sctx
->chip_class
== GFX8
) {
5250 unsigned vgt_tess_distribution
;
5252 vgt_tess_distribution
= S_028B50_ACCUM_ISOLINE(32) | S_028B50_ACCUM_TRI(11) |
5253 S_028B50_ACCUM_QUAD(11) | S_028B50_DONUT_SPLIT(16);
5255 /* Testing with Unigine Heaven extreme tesselation yielded best results
5256 * with TRAP_SPLIT = 3.
5258 if (sctx
->family
== CHIP_FIJI
|| sctx
->family
>= CHIP_POLARIS10
)
5259 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5261 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5264 if (sscreen
->info
.chip_class
<= GFX9
) {
5265 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
5268 if (sctx
->chip_class
== GFX9
) {
5269 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
5270 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
5271 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
5274 if (sctx
->chip_class
>= GFX9
) {
5275 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5276 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5278 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
,
5279 S_028B50_ACCUM_ISOLINE(40) | S_028B50_ACCUM_TRI(30) | S_028B50_ACCUM_QUAD(24) |
5280 S_028B50_DONUT_SPLIT(24) | S_028B50_TRAP_SPLIT(6));
5281 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5282 S_028C48_MAX_ALLOC_COUNT(sscreen
->info
.pbb_max_alloc_count
- 1) |
5283 S_028C48_MAX_PRIM_PER_BATCH(1023));
5284 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5285 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5287 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5288 si_pm4_set_reg(pm4
, R_0301EC_CP_COHER_START_DELAY
,
5289 sctx
->chip_class
>= GFX10
? 0x20 : 0);
5292 if (sctx
->chip_class
>= GFX10
) {
5293 /* Logical CUs 16 - 31 */
5294 si_pm4_set_reg(pm4
, R_00B004_SPI_SHADER_PGM_RSRC4_PS
, S_00B004_CU_EN(0xffff));
5295 si_pm4_set_reg(pm4
, R_00B104_SPI_SHADER_PGM_RSRC4_VS
, S_00B104_CU_EN(0xffff));
5296 si_pm4_set_reg(pm4
, R_00B404_SPI_SHADER_PGM_RSRC4_HS
, S_00B404_CU_EN(0xffff));
5298 si_pm4_set_reg(pm4
, R_00B0C8_SPI_SHADER_USER_ACCUM_PS_0
, 0);
5299 si_pm4_set_reg(pm4
, R_00B0CC_SPI_SHADER_USER_ACCUM_PS_1
, 0);
5300 si_pm4_set_reg(pm4
, R_00B0D0_SPI_SHADER_USER_ACCUM_PS_2
, 0);
5301 si_pm4_set_reg(pm4
, R_00B0D4_SPI_SHADER_USER_ACCUM_PS_3
, 0);
5302 si_pm4_set_reg(pm4
, R_00B1C8_SPI_SHADER_USER_ACCUM_VS_0
, 0);
5303 si_pm4_set_reg(pm4
, R_00B1CC_SPI_SHADER_USER_ACCUM_VS_1
, 0);
5304 si_pm4_set_reg(pm4
, R_00B1D0_SPI_SHADER_USER_ACCUM_VS_2
, 0);
5305 si_pm4_set_reg(pm4
, R_00B1D4_SPI_SHADER_USER_ACCUM_VS_3
, 0);
5306 si_pm4_set_reg(pm4
, R_00B2C8_SPI_SHADER_USER_ACCUM_ESGS_0
, 0);
5307 si_pm4_set_reg(pm4
, R_00B2CC_SPI_SHADER_USER_ACCUM_ESGS_1
, 0);
5308 si_pm4_set_reg(pm4
, R_00B2D0_SPI_SHADER_USER_ACCUM_ESGS_2
, 0);
5309 si_pm4_set_reg(pm4
, R_00B2D4_SPI_SHADER_USER_ACCUM_ESGS_3
, 0);
5310 si_pm4_set_reg(pm4
, R_00B4C8_SPI_SHADER_USER_ACCUM_LSHS_0
, 0);
5311 si_pm4_set_reg(pm4
, R_00B4CC_SPI_SHADER_USER_ACCUM_LSHS_1
, 0);
5312 si_pm4_set_reg(pm4
, R_00B4D0_SPI_SHADER_USER_ACCUM_LSHS_2
, 0);
5313 si_pm4_set_reg(pm4
, R_00B4D4_SPI_SHADER_USER_ACCUM_LSHS_3
, 0);
5315 si_pm4_set_reg(pm4
, R_00B0C0_SPI_SHADER_REQ_CTRL_PS
,
5316 S_00B0C0_SOFT_GROUPING_EN(1) |
5317 S_00B0C0_NUMBER_OF_REQUESTS_PER_CU(4 - 1));
5318 si_pm4_set_reg(pm4
, R_00B1C0_SPI_SHADER_REQ_CTRL_VS
, 0);
5320 si_pm4_set_reg(pm4
, R_028428_CB_COVERAGE_OUT_CONTROL
, 0);
5321 si_pm4_set_reg(pm4
, R_028A98_VGT_DRAW_PAYLOAD_CNTL
, 0);
5323 /* Break up a pixel wave if it contains deallocs for more than
5324 * half the parameter cache.
5326 * To avoid a deadlock where pixel waves aren't launched
5327 * because they're waiting for more pixels while the frontend
5328 * is stuck waiting for PC space, the maximum allowed value is
5329 * the size of the PC minus the largest possible allocation for
5330 * a single primitive shader subgroup.
5332 si_pm4_set_reg(pm4
, R_028C50_PA_SC_NGG_MODE_CNTL
, S_028C50_MAX_DEALLOCS_IN_WAVE(512));
5333 /* Reuse for legacy (non-NGG) only. */
5334 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5336 if (!has_clear_state
) {
5337 si_pm4_set_reg(pm4
, R_02835C_PA_SC_TILE_STEERING_OVERRIDE
,
5338 sscreen
->info
.pa_sc_tile_steering_override
);
5342 si_pm4_set_reg(pm4
, R_030964_GE_MAX_VTX_INDX
, ~0);
5343 si_pm4_set_reg(pm4
, R_030924_GE_MIN_VTX_INDX
, 0);
5344 si_pm4_set_reg(pm4
, R_030928_GE_INDX_OFFSET
, 0);
5345 si_pm4_set_reg(pm4
, R_03097C_GE_STEREO_CNTL
, 0);
5346 si_pm4_set_reg(pm4
, R_030988_GE_USER_VGPR_EN
, 0);
5349 if (sctx
->chip_class
>= GFX10_3
) {
5350 si_pm4_set_reg(pm4
, R_028750_SX_PS_DOWNCONVERT_CONTROL
, 0xff);
5351 si_pm4_set_reg(pm4
, 0x28848, 1 << 9); /* This fixes sample shading. */
5354 sctx
->cs_preamble_state
= pm4
;