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[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x)
79 {
80 return x <= 0 ? 0 :
81 x >= 4096 ? 0xffff : x * 16;
82 }
83
84 /*
85 * Inferred framebuffer and blender state.
86 *
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
89 */
90 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
91 {
92 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
93 struct si_state_blend *blend = sctx->queued.named.blend;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
97 unsigned i;
98
99 if (blend)
100 cb_target_mask &= blend->cb_target_mask;
101
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
105 *
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
107 */
108 if (blend && blend->dual_src_blend &&
109 sctx->ps_shader.cso &&
110 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
111 cb_target_mask = 0;
112
113 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
114
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
117 */
118 if (sctx->screen->dfsm_allowed &&
119 sctx->last_cb_target_mask != cb_target_mask) {
120 sctx->last_cb_target_mask = cb_target_mask;
121
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->b.rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx->screen->b.has_rbplus) {
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 }
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 R600_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 /**
381 * Get rid of DST in the blend factors by commuting the operands:
382 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
383 */
384 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
385 unsigned *dst_factor, unsigned expected_dst,
386 unsigned replacement_src)
387 {
388 if (*src_factor == expected_dst &&
389 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
390 *src_factor = PIPE_BLENDFACTOR_ZERO;
391 *dst_factor = replacement_src;
392
393 /* Commuting the operands requires reversing subtractions. */
394 if (*func == PIPE_BLEND_SUBTRACT)
395 *func = PIPE_BLEND_REVERSE_SUBTRACT;
396 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
397 *func = PIPE_BLEND_SUBTRACT;
398 }
399 }
400
401 static bool si_blend_factor_uses_dst(unsigned factor)
402 {
403 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
404 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
405 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
406 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
407 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
408 }
409
410 static void *si_create_blend_state_mode(struct pipe_context *ctx,
411 const struct pipe_blend_state *state,
412 unsigned mode)
413 {
414 struct si_context *sctx = (struct si_context*)ctx;
415 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
416 struct si_pm4_state *pm4 = &blend->pm4;
417 uint32_t sx_mrt_blend_opt[8] = {0};
418 uint32_t color_control = 0;
419
420 if (!blend)
421 return NULL;
422
423 blend->alpha_to_coverage = state->alpha_to_coverage;
424 blend->alpha_to_one = state->alpha_to_one;
425 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
426
427 if (state->logicop_enable) {
428 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
429 } else {
430 color_control |= S_028808_ROP3(0xcc);
431 }
432
433 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
434 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
435 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
436 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
439
440 if (state->alpha_to_coverage)
441 blend->need_src_alpha_4bit |= 0xf;
442
443 blend->cb_target_mask = 0;
444 blend->cb_target_enabled_4bit = 0;
445
446 for (int i = 0; i < 8; i++) {
447 /* state->rt entries > 0 only written if independent blending */
448 const int j = state->independent_blend_enable ? i : 0;
449
450 unsigned eqRGB = state->rt[j].rgb_func;
451 unsigned srcRGB = state->rt[j].rgb_src_factor;
452 unsigned dstRGB = state->rt[j].rgb_dst_factor;
453 unsigned eqA = state->rt[j].alpha_func;
454 unsigned srcA = state->rt[j].alpha_src_factor;
455 unsigned dstA = state->rt[j].alpha_dst_factor;
456
457 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
458 unsigned blend_cntl = 0;
459
460 sx_mrt_blend_opt[i] =
461 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
462 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
463
464 /* Only set dual source blending for MRT0 to avoid a hang. */
465 if (i >= 1 && blend->dual_src_blend) {
466 /* Vulkan does this for dual source blending. */
467 if (i == 1)
468 blend_cntl |= S_028780_ENABLE(1);
469
470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
471 continue;
472 }
473
474 /* Only addition and subtraction equations are supported with
475 * dual source blending.
476 */
477 if (blend->dual_src_blend &&
478 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
479 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
480 assert(!"Unsupported equation for dual source blending");
481 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
482 continue;
483 }
484
485 /* cb_render_state will disable unused ones */
486 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
487 if (state->rt[j].colormask)
488 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
489
490 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
491 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
492 continue;
493 }
494
495 /* Blending optimizations for RB+.
496 * These transformations don't change the behavior.
497 *
498 * First, get rid of DST in the blend factors:
499 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
500 */
501 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
502 PIPE_BLENDFACTOR_DST_COLOR,
503 PIPE_BLENDFACTOR_SRC_COLOR);
504 si_blend_remove_dst(&eqA, &srcA, &dstA,
505 PIPE_BLENDFACTOR_DST_COLOR,
506 PIPE_BLENDFACTOR_SRC_COLOR);
507 si_blend_remove_dst(&eqA, &srcA, &dstA,
508 PIPE_BLENDFACTOR_DST_ALPHA,
509 PIPE_BLENDFACTOR_SRC_ALPHA);
510
511 /* Look up the ideal settings from tables. */
512 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
513 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
514 srcA_opt = si_translate_blend_opt_factor(srcA, true);
515 dstA_opt = si_translate_blend_opt_factor(dstA, true);
516
517 /* Handle interdependencies. */
518 if (si_blend_factor_uses_dst(srcRGB))
519 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
520 if (si_blend_factor_uses_dst(srcA))
521 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
522
523 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
524 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
525 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
527 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
528
529 /* Set the final value. */
530 sx_mrt_blend_opt[i] =
531 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
532 S_028760_COLOR_DST_OPT(dstRGB_opt) |
533 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
534 S_028760_ALPHA_SRC_OPT(srcA_opt) |
535 S_028760_ALPHA_DST_OPT(dstA_opt) |
536 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
537
538 /* Set blend state. */
539 blend_cntl |= S_028780_ENABLE(1);
540 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
541 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
542 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
543
544 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
545 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
546 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
547 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
548 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
549 }
550 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
551
552 blend->blend_enable_4bit |= 0xfu << (i * 4);
553
554 /* This is only important for formats without alpha. */
555 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
556 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
558 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
560 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
561 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
562 }
563
564 if (blend->cb_target_mask) {
565 color_control |= S_028808_MODE(mode);
566 } else {
567 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
568 }
569
570 if (sctx->screen->b.has_rbplus) {
571 /* Disable RB+ blend optimizations for dual source blending.
572 * Vulkan does this.
573 */
574 if (blend->dual_src_blend) {
575 for (int i = 0; i < 8; i++) {
576 sx_mrt_blend_opt[i] =
577 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
578 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
579 }
580 }
581
582 for (int i = 0; i < 8; i++)
583 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
584 sx_mrt_blend_opt[i]);
585
586 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
587 if (blend->dual_src_blend || state->logicop_enable ||
588 mode == V_028808_CB_RESOLVE)
589 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
590 }
591
592 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
593 return blend;
594 }
595
596 static void *si_create_blend_state(struct pipe_context *ctx,
597 const struct pipe_blend_state *state)
598 {
599 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
600 }
601
602 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
603 {
604 struct si_context *sctx = (struct si_context *)ctx;
605 struct si_state_blend *old_blend = sctx->queued.named.blend;
606 struct si_state_blend *blend = (struct si_state_blend *)state;
607
608 if (!state)
609 return;
610
611 if (!old_blend ||
612 old_blend->cb_target_mask != blend->cb_target_mask ||
613 old_blend->dual_src_blend != blend->dual_src_blend)
614 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
615
616 si_pm4_bind_state(sctx, blend, state);
617
618 if (!old_blend ||
619 old_blend->cb_target_mask != blend->cb_target_mask ||
620 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
621 old_blend->alpha_to_one != blend->alpha_to_one ||
622 old_blend->dual_src_blend != blend->dual_src_blend ||
623 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
624 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
625 sctx->do_update_shaders = true;
626
627 if (sctx->screen->dpbb_allowed &&
628 (!old_blend ||
629 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
630 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
631 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
632 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
633 }
634
635 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
636 {
637 struct si_context *sctx = (struct si_context *)ctx;
638 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
639 }
640
641 static void si_set_blend_color(struct pipe_context *ctx,
642 const struct pipe_blend_color *state)
643 {
644 struct si_context *sctx = (struct si_context *)ctx;
645 static const struct pipe_blend_color zeros;
646
647 sctx->blend_color.state = *state;
648 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
649 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
650 }
651
652 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
653 {
654 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
655
656 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
657 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
658 }
659
660 /*
661 * Clipping
662 */
663
664 static void si_set_clip_state(struct pipe_context *ctx,
665 const struct pipe_clip_state *state)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 struct pipe_constant_buffer cb;
669 static const struct pipe_clip_state zeros;
670
671 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
672 return;
673
674 sctx->clip_state.state = *state;
675 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
676 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
677
678 cb.buffer = NULL;
679 cb.user_buffer = state->ucp;
680 cb.buffer_offset = 0;
681 cb.buffer_size = 4*4*8;
682 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
683 pipe_resource_reference(&cb.buffer, NULL);
684 }
685
686 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
687 {
688 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
689
690 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
691 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
692 }
693
694 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
695 {
696 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
697 struct si_shader *vs = si_get_vs_state(sctx);
698 struct si_shader_selector *vs_sel = vs->selector;
699 struct tgsi_shader_info *info = &vs_sel->info;
700 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
701 unsigned window_space =
702 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
703 unsigned clipdist_mask = vs_sel->clipdist_mask;
704 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
705 unsigned culldist_mask = vs_sel->culldist_mask;
706 unsigned total_mask;
707
708 if (vs->key.opt.clip_disable) {
709 assert(!info->culldist_writemask);
710 clipdist_mask = 0;
711 culldist_mask = 0;
712 }
713 total_mask = clipdist_mask | culldist_mask;
714
715 /* Clip distances on points have no effect, so need to be implemented
716 * as cull distances. This applies for the clipvertex case as well.
717 *
718 * Setting this for primitives other than points should have no adverse
719 * effects.
720 */
721 clipdist_mask &= rs->clip_plane_enable;
722 culldist_mask |= clipdist_mask;
723
724 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
725 vs_sel->pa_cl_vs_out_cntl |
726 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
727 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
728 clipdist_mask | (culldist_mask << 8));
729 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
730 rs->pa_cl_clip_cntl |
731 ucp_mask |
732 S_028810_CLIP_DISABLE(window_space));
733 }
734
735 /*
736 * inferred state between framebuffer and rasterizer
737 */
738 static void si_update_poly_offset_state(struct si_context *sctx)
739 {
740 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
741
742 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
743 si_pm4_bind_state(sctx, poly_offset, NULL);
744 return;
745 }
746
747 /* Use the user format, not db_render_format, so that the polygon
748 * offset behaves as expected by applications.
749 */
750 switch (sctx->framebuffer.state.zsbuf->texture->format) {
751 case PIPE_FORMAT_Z16_UNORM:
752 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
753 break;
754 default: /* 24-bit */
755 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
756 break;
757 case PIPE_FORMAT_Z32_FLOAT:
758 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
759 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
760 break;
761 }
762 }
763
764 /*
765 * Rasterizer
766 */
767
768 static uint32_t si_translate_fill(uint32_t func)
769 {
770 switch(func) {
771 case PIPE_POLYGON_MODE_FILL:
772 return V_028814_X_DRAW_TRIANGLES;
773 case PIPE_POLYGON_MODE_LINE:
774 return V_028814_X_DRAW_LINES;
775 case PIPE_POLYGON_MODE_POINT:
776 return V_028814_X_DRAW_POINTS;
777 default:
778 assert(0);
779 return V_028814_X_DRAW_POINTS;
780 }
781 }
782
783 static void *si_create_rs_state(struct pipe_context *ctx,
784 const struct pipe_rasterizer_state *state)
785 {
786 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
787 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
788 struct si_pm4_state *pm4 = &rs->pm4;
789 unsigned tmp, i;
790 float psize_min, psize_max;
791
792 if (!rs) {
793 return NULL;
794 }
795
796 rs->scissor_enable = state->scissor;
797 rs->clip_halfz = state->clip_halfz;
798 rs->two_side = state->light_twoside;
799 rs->multisample_enable = state->multisample;
800 rs->force_persample_interp = state->force_persample_interp;
801 rs->clip_plane_enable = state->clip_plane_enable;
802 rs->line_stipple_enable = state->line_stipple_enable;
803 rs->poly_stipple_enable = state->poly_stipple_enable;
804 rs->line_smooth = state->line_smooth;
805 rs->poly_smooth = state->poly_smooth;
806 rs->uses_poly_offset = state->offset_point || state->offset_line ||
807 state->offset_tri;
808 rs->clamp_fragment_color = state->clamp_fragment_color;
809 rs->clamp_vertex_color = state->clamp_vertex_color;
810 rs->flatshade = state->flatshade;
811 rs->sprite_coord_enable = state->sprite_coord_enable;
812 rs->rasterizer_discard = state->rasterizer_discard;
813 rs->pa_sc_line_stipple = state->line_stipple_enable ?
814 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
815 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
816 rs->pa_cl_clip_cntl =
817 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
818 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
819 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
820 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
821 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
822
823 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
824 S_0286D4_FLAT_SHADE_ENA(1) |
825 S_0286D4_PNT_SPRITE_ENA(1) |
826 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
827 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
828 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
829 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
830 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
831
832 /* point size 12.4 fixed point */
833 tmp = (unsigned)(state->point_size * 8.0);
834 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
835
836 if (state->point_size_per_vertex) {
837 psize_min = util_get_min_point_size(state);
838 psize_max = 8192;
839 } else {
840 /* Force the point size to be as if the vertex output was disabled. */
841 psize_min = state->point_size;
842 psize_max = state->point_size;
843 }
844 /* Divide by two, because 0.5 = 1 pixel. */
845 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
846 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
847 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
848
849 tmp = (unsigned)state->line_width * 8;
850 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
851 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
852 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
853 S_028A48_MSAA_ENABLE(state->multisample ||
854 state->poly_smooth ||
855 state->line_smooth) |
856 S_028A48_VPORT_SCISSOR_ENABLE(1) |
857 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
858
859 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
860 S_028BE4_PIX_CENTER(state->half_pixel_center) |
861 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
862
863 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
864 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
865 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
866 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
867 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
868 S_028814_FACE(!state->front_ccw) |
869 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
870 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
871 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
872 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
873 state->fill_back != PIPE_POLYGON_MODE_FILL) |
874 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
875 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
876
877 if (!rs->uses_poly_offset)
878 return rs;
879
880 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
881 if (!rs->pm4_poly_offset) {
882 FREE(rs);
883 return NULL;
884 }
885
886 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
887 for (i = 0; i < 3; i++) {
888 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
889 float offset_units = state->offset_units;
890 float offset_scale = state->offset_scale * 16.0f;
891 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
892
893 if (!state->offset_units_unscaled) {
894 switch (i) {
895 case 0: /* 16-bit zbuffer */
896 offset_units *= 4.0f;
897 pa_su_poly_offset_db_fmt_cntl =
898 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
899 break;
900 case 1: /* 24-bit zbuffer */
901 offset_units *= 2.0f;
902 pa_su_poly_offset_db_fmt_cntl =
903 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
904 break;
905 case 2: /* 32-bit zbuffer */
906 offset_units *= 1.0f;
907 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
908 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
909 break;
910 }
911 }
912
913 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
914 fui(offset_scale));
915 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
916 fui(offset_units));
917 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
918 fui(offset_scale));
919 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
920 fui(offset_units));
921 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
922 pa_su_poly_offset_db_fmt_cntl);
923 }
924
925 return rs;
926 }
927
928 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
929 {
930 struct si_context *sctx = (struct si_context *)ctx;
931 struct si_state_rasterizer *old_rs =
932 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
933 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
934
935 if (!state)
936 return;
937
938 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
939 si_mark_atom_dirty(sctx, &sctx->db_render_state);
940
941 /* Update the small primitive filter workaround if necessary. */
942 if (sctx->screen->has_msaa_sample_loc_bug &&
943 sctx->framebuffer.nr_samples > 1)
944 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
945 }
946
947 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
948 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
949
950 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
951
952 si_pm4_bind_state(sctx, rasterizer, rs);
953 si_update_poly_offset_state(sctx);
954
955 if (!old_rs ||
956 old_rs->clip_plane_enable != rs->clip_plane_enable ||
957 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
958 si_mark_atom_dirty(sctx, &sctx->clip_regs);
959
960 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
961 rs->line_stipple_enable;
962
963 if (!old_rs ||
964 old_rs->clip_plane_enable != rs->clip_plane_enable ||
965 old_rs->rasterizer_discard != rs->rasterizer_discard ||
966 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
967 old_rs->flatshade != rs->flatshade ||
968 old_rs->two_side != rs->two_side ||
969 old_rs->multisample_enable != rs->multisample_enable ||
970 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
971 old_rs->poly_smooth != rs->poly_smooth ||
972 old_rs->line_smooth != rs->line_smooth ||
973 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
974 old_rs->force_persample_interp != rs->force_persample_interp)
975 sctx->do_update_shaders = true;
976 }
977
978 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
979 {
980 struct si_context *sctx = (struct si_context *)ctx;
981 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
982
983 if (sctx->queued.named.rasterizer == state)
984 si_pm4_bind_state(sctx, poly_offset, NULL);
985
986 FREE(rs->pm4_poly_offset);
987 si_pm4_delete_state(sctx, rasterizer, rs);
988 }
989
990 /*
991 * infeered state between dsa and stencil ref
992 */
993 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
994 {
995 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
996 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
997 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
998
999 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1000 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1001 S_028430_STENCILMASK(dsa->valuemask[0]) |
1002 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1003 S_028430_STENCILOPVAL(1));
1004 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1005 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1006 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1007 S_028434_STENCILOPVAL_BF(1));
1008 }
1009
1010 static void si_set_stencil_ref(struct pipe_context *ctx,
1011 const struct pipe_stencil_ref *state)
1012 {
1013 struct si_context *sctx = (struct si_context *)ctx;
1014
1015 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1016 return;
1017
1018 sctx->stencil_ref.state = *state;
1019 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1020 }
1021
1022
1023 /*
1024 * DSA
1025 */
1026
1027 static uint32_t si_translate_stencil_op(int s_op)
1028 {
1029 switch (s_op) {
1030 case PIPE_STENCIL_OP_KEEP:
1031 return V_02842C_STENCIL_KEEP;
1032 case PIPE_STENCIL_OP_ZERO:
1033 return V_02842C_STENCIL_ZERO;
1034 case PIPE_STENCIL_OP_REPLACE:
1035 return V_02842C_STENCIL_REPLACE_TEST;
1036 case PIPE_STENCIL_OP_INCR:
1037 return V_02842C_STENCIL_ADD_CLAMP;
1038 case PIPE_STENCIL_OP_DECR:
1039 return V_02842C_STENCIL_SUB_CLAMP;
1040 case PIPE_STENCIL_OP_INCR_WRAP:
1041 return V_02842C_STENCIL_ADD_WRAP;
1042 case PIPE_STENCIL_OP_DECR_WRAP:
1043 return V_02842C_STENCIL_SUB_WRAP;
1044 case PIPE_STENCIL_OP_INVERT:
1045 return V_02842C_STENCIL_INVERT;
1046 default:
1047 R600_ERR("Unknown stencil op %d", s_op);
1048 assert(0);
1049 break;
1050 }
1051 return 0;
1052 }
1053
1054 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1055 {
1056 return s->enabled && s->writemask &&
1057 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1058 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1059 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1060 }
1061
1062 static void *si_create_dsa_state(struct pipe_context *ctx,
1063 const struct pipe_depth_stencil_alpha_state *state)
1064 {
1065 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1066 struct si_pm4_state *pm4 = &dsa->pm4;
1067 unsigned db_depth_control;
1068 uint32_t db_stencil_control = 0;
1069
1070 if (!dsa) {
1071 return NULL;
1072 }
1073
1074 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1075 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1076 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1077 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1078
1079 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1080 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1081 S_028800_ZFUNC(state->depth.func) |
1082 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1083
1084 /* stencil */
1085 if (state->stencil[0].enabled) {
1086 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1087 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1088 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1089 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1090 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1091
1092 if (state->stencil[1].enabled) {
1093 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1094 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1095 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1096 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1097 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1098 }
1099 }
1100
1101 /* alpha */
1102 if (state->alpha.enabled) {
1103 dsa->alpha_func = state->alpha.func;
1104
1105 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1106 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1107 } else {
1108 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1109 }
1110
1111 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1112 if (state->stencil[0].enabled)
1113 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1114 if (state->depth.bounds_test) {
1115 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1116 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1117 }
1118
1119 dsa->depth_enabled = state->depth.enabled;
1120 dsa->depth_write_enabled = state->depth.enabled &&
1121 state->depth.writemask;
1122 dsa->stencil_enabled = state->stencil[0].enabled;
1123 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1124 (si_dsa_writes_stencil(&state->stencil[0]) ||
1125 si_dsa_writes_stencil(&state->stencil[1]));
1126 dsa->db_can_write = dsa->depth_write_enabled ||
1127 dsa->stencil_write_enabled;
1128 return dsa;
1129 }
1130
1131 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1132 {
1133 struct si_context *sctx = (struct si_context *)ctx;
1134 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1135 struct si_state_dsa *dsa = state;
1136
1137 if (!state)
1138 return;
1139
1140 si_pm4_bind_state(sctx, dsa, dsa);
1141
1142 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1143 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1144 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1145 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1146 }
1147
1148 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1149 sctx->do_update_shaders = true;
1150
1151 if (sctx->screen->dpbb_allowed &&
1152 (!old_dsa ||
1153 (old_dsa->depth_enabled != dsa->depth_enabled ||
1154 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1155 old_dsa->db_can_write != dsa->db_can_write)))
1156 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1157 }
1158
1159 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1160 {
1161 struct si_context *sctx = (struct si_context *)ctx;
1162 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1163 }
1164
1165 static void *si_create_db_flush_dsa(struct si_context *sctx)
1166 {
1167 struct pipe_depth_stencil_alpha_state dsa = {};
1168
1169 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1170 }
1171
1172 /* DB RENDER STATE */
1173
1174 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1175 {
1176 struct si_context *sctx = (struct si_context*)ctx;
1177
1178 /* Pipeline stat & streamout queries. */
1179 if (enable) {
1180 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1181 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1182 } else {
1183 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1184 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1185 }
1186
1187 /* Occlusion queries. */
1188 if (sctx->occlusion_queries_disabled != !enable) {
1189 sctx->occlusion_queries_disabled = !enable;
1190 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1191 }
1192 }
1193
1194 static void si_set_occlusion_query_state(struct pipe_context *ctx,
1195 bool old_enable,
1196 bool old_perfect_enable)
1197 {
1198 struct si_context *sctx = (struct si_context*)ctx;
1199
1200 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1201 }
1202
1203 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1204 {
1205 struct si_context *sctx = (struct si_context*)ctx;
1206
1207 st->saved_compute = sctx->cs_shader_state.program;
1208
1209 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1210 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1211 }
1212
1213 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1214 {
1215 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1216 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1217 unsigned db_shader_control;
1218
1219 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1220
1221 /* DB_RENDER_CONTROL */
1222 if (sctx->dbcb_depth_copy_enabled ||
1223 sctx->dbcb_stencil_copy_enabled) {
1224 radeon_emit(cs,
1225 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1226 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1227 S_028000_COPY_CENTROID(1) |
1228 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1229 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1230 radeon_emit(cs,
1231 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1232 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1233 } else {
1234 radeon_emit(cs,
1235 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1236 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1237 }
1238
1239 /* DB_COUNT_CONTROL (occlusion queries) */
1240 if (sctx->b.num_occlusion_queries > 0 &&
1241 !sctx->occlusion_queries_disabled) {
1242 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1243
1244 if (sctx->b.chip_class >= CIK) {
1245 radeon_emit(cs,
1246 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1247 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1248 S_028004_ZPASS_ENABLE(1) |
1249 S_028004_SLICE_EVEN_ENABLE(1) |
1250 S_028004_SLICE_ODD_ENABLE(1));
1251 } else {
1252 radeon_emit(cs,
1253 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1254 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1255 }
1256 } else {
1257 /* Disable occlusion queries. */
1258 if (sctx->b.chip_class >= CIK) {
1259 radeon_emit(cs, 0);
1260 } else {
1261 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1262 }
1263 }
1264
1265 /* DB_RENDER_OVERRIDE2 */
1266 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1267 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1268 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1269 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1270
1271 db_shader_control = sctx->ps_db_shader_control;
1272
1273 /* Bug workaround for smoothing (overrasterization) on SI. */
1274 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1275 db_shader_control &= C_02880C_Z_ORDER;
1276 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1277 }
1278
1279 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1280 if (!rs || !rs->multisample_enable)
1281 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1282
1283 if (sctx->screen->b.has_rbplus &&
1284 !sctx->screen->b.rbplus_allowed)
1285 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1286
1287 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1288 db_shader_control);
1289 }
1290
1291 /*
1292 * format translation
1293 */
1294 static uint32_t si_translate_colorformat(enum pipe_format format)
1295 {
1296 const struct util_format_description *desc = util_format_description(format);
1297 if (!desc)
1298 return V_028C70_COLOR_INVALID;
1299
1300 #define HAS_SIZE(x,y,z,w) \
1301 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1302 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1303
1304 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1305 return V_028C70_COLOR_10_11_11;
1306
1307 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1308 return V_028C70_COLOR_INVALID;
1309
1310 /* hw cannot support mixed formats (except depth/stencil, since
1311 * stencil is not written to). */
1312 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1313 return V_028C70_COLOR_INVALID;
1314
1315 switch (desc->nr_channels) {
1316 case 1:
1317 switch (desc->channel[0].size) {
1318 case 8:
1319 return V_028C70_COLOR_8;
1320 case 16:
1321 return V_028C70_COLOR_16;
1322 case 32:
1323 return V_028C70_COLOR_32;
1324 }
1325 break;
1326 case 2:
1327 if (desc->channel[0].size == desc->channel[1].size) {
1328 switch (desc->channel[0].size) {
1329 case 8:
1330 return V_028C70_COLOR_8_8;
1331 case 16:
1332 return V_028C70_COLOR_16_16;
1333 case 32:
1334 return V_028C70_COLOR_32_32;
1335 }
1336 } else if (HAS_SIZE(8,24,0,0)) {
1337 return V_028C70_COLOR_24_8;
1338 } else if (HAS_SIZE(24,8,0,0)) {
1339 return V_028C70_COLOR_8_24;
1340 }
1341 break;
1342 case 3:
1343 if (HAS_SIZE(5,6,5,0)) {
1344 return V_028C70_COLOR_5_6_5;
1345 } else if (HAS_SIZE(32,8,24,0)) {
1346 return V_028C70_COLOR_X24_8_32_FLOAT;
1347 }
1348 break;
1349 case 4:
1350 if (desc->channel[0].size == desc->channel[1].size &&
1351 desc->channel[0].size == desc->channel[2].size &&
1352 desc->channel[0].size == desc->channel[3].size) {
1353 switch (desc->channel[0].size) {
1354 case 4:
1355 return V_028C70_COLOR_4_4_4_4;
1356 case 8:
1357 return V_028C70_COLOR_8_8_8_8;
1358 case 16:
1359 return V_028C70_COLOR_16_16_16_16;
1360 case 32:
1361 return V_028C70_COLOR_32_32_32_32;
1362 }
1363 } else if (HAS_SIZE(5,5,5,1)) {
1364 return V_028C70_COLOR_1_5_5_5;
1365 } else if (HAS_SIZE(10,10,10,2)) {
1366 return V_028C70_COLOR_2_10_10_10;
1367 }
1368 break;
1369 }
1370 return V_028C70_COLOR_INVALID;
1371 }
1372
1373 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1374 {
1375 if (SI_BIG_ENDIAN) {
1376 switch(colorformat) {
1377 /* 8-bit buffers. */
1378 case V_028C70_COLOR_8:
1379 return V_028C70_ENDIAN_NONE;
1380
1381 /* 16-bit buffers. */
1382 case V_028C70_COLOR_5_6_5:
1383 case V_028C70_COLOR_1_5_5_5:
1384 case V_028C70_COLOR_4_4_4_4:
1385 case V_028C70_COLOR_16:
1386 case V_028C70_COLOR_8_8:
1387 return V_028C70_ENDIAN_8IN16;
1388
1389 /* 32-bit buffers. */
1390 case V_028C70_COLOR_8_8_8_8:
1391 case V_028C70_COLOR_2_10_10_10:
1392 case V_028C70_COLOR_8_24:
1393 case V_028C70_COLOR_24_8:
1394 case V_028C70_COLOR_16_16:
1395 return V_028C70_ENDIAN_8IN32;
1396
1397 /* 64-bit buffers. */
1398 case V_028C70_COLOR_16_16_16_16:
1399 return V_028C70_ENDIAN_8IN16;
1400
1401 case V_028C70_COLOR_32_32:
1402 return V_028C70_ENDIAN_8IN32;
1403
1404 /* 128-bit buffers. */
1405 case V_028C70_COLOR_32_32_32_32:
1406 return V_028C70_ENDIAN_8IN32;
1407 default:
1408 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1409 }
1410 } else {
1411 return V_028C70_ENDIAN_NONE;
1412 }
1413 }
1414
1415 static uint32_t si_translate_dbformat(enum pipe_format format)
1416 {
1417 switch (format) {
1418 case PIPE_FORMAT_Z16_UNORM:
1419 return V_028040_Z_16;
1420 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1421 case PIPE_FORMAT_X8Z24_UNORM:
1422 case PIPE_FORMAT_Z24X8_UNORM:
1423 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1424 return V_028040_Z_24; /* deprecated on SI */
1425 case PIPE_FORMAT_Z32_FLOAT:
1426 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1427 return V_028040_Z_32_FLOAT;
1428 default:
1429 return V_028040_Z_INVALID;
1430 }
1431 }
1432
1433 /*
1434 * Texture translation
1435 */
1436
1437 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1438 enum pipe_format format,
1439 const struct util_format_description *desc,
1440 int first_non_void)
1441 {
1442 struct si_screen *sscreen = (struct si_screen*)screen;
1443 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1444 sscreen->b.info.drm_minor >= 31) ||
1445 sscreen->b.info.drm_major == 3;
1446 bool uniform = true;
1447 int i;
1448
1449 /* Colorspace (return non-RGB formats directly). */
1450 switch (desc->colorspace) {
1451 /* Depth stencil formats */
1452 case UTIL_FORMAT_COLORSPACE_ZS:
1453 switch (format) {
1454 case PIPE_FORMAT_Z16_UNORM:
1455 return V_008F14_IMG_DATA_FORMAT_16;
1456 case PIPE_FORMAT_X24S8_UINT:
1457 case PIPE_FORMAT_S8X24_UINT:
1458 /*
1459 * Implemented as an 8_8_8_8 data format to fix texture
1460 * gathers in stencil sampling. This affects at least
1461 * GL45-CTS.texture_cube_map_array.sampling on VI.
1462 */
1463 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1464 case PIPE_FORMAT_Z24X8_UNORM:
1465 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1466 return V_008F14_IMG_DATA_FORMAT_8_24;
1467 case PIPE_FORMAT_X8Z24_UNORM:
1468 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1469 return V_008F14_IMG_DATA_FORMAT_24_8;
1470 case PIPE_FORMAT_S8_UINT:
1471 return V_008F14_IMG_DATA_FORMAT_8;
1472 case PIPE_FORMAT_Z32_FLOAT:
1473 return V_008F14_IMG_DATA_FORMAT_32;
1474 case PIPE_FORMAT_X32_S8X24_UINT:
1475 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1476 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1477 default:
1478 goto out_unknown;
1479 }
1480
1481 case UTIL_FORMAT_COLORSPACE_YUV:
1482 goto out_unknown; /* TODO */
1483
1484 case UTIL_FORMAT_COLORSPACE_SRGB:
1485 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1486 goto out_unknown;
1487 break;
1488
1489 default:
1490 break;
1491 }
1492
1493 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1494 if (!enable_compressed_formats)
1495 goto out_unknown;
1496
1497 switch (format) {
1498 case PIPE_FORMAT_RGTC1_SNORM:
1499 case PIPE_FORMAT_LATC1_SNORM:
1500 case PIPE_FORMAT_RGTC1_UNORM:
1501 case PIPE_FORMAT_LATC1_UNORM:
1502 return V_008F14_IMG_DATA_FORMAT_BC4;
1503 case PIPE_FORMAT_RGTC2_SNORM:
1504 case PIPE_FORMAT_LATC2_SNORM:
1505 case PIPE_FORMAT_RGTC2_UNORM:
1506 case PIPE_FORMAT_LATC2_UNORM:
1507 return V_008F14_IMG_DATA_FORMAT_BC5;
1508 default:
1509 goto out_unknown;
1510 }
1511 }
1512
1513 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1514 (sscreen->b.family == CHIP_STONEY ||
1515 sscreen->b.chip_class >= GFX9)) {
1516 switch (format) {
1517 case PIPE_FORMAT_ETC1_RGB8:
1518 case PIPE_FORMAT_ETC2_RGB8:
1519 case PIPE_FORMAT_ETC2_SRGB8:
1520 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1521 case PIPE_FORMAT_ETC2_RGB8A1:
1522 case PIPE_FORMAT_ETC2_SRGB8A1:
1523 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1524 case PIPE_FORMAT_ETC2_RGBA8:
1525 case PIPE_FORMAT_ETC2_SRGBA8:
1526 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1527 case PIPE_FORMAT_ETC2_R11_UNORM:
1528 case PIPE_FORMAT_ETC2_R11_SNORM:
1529 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1530 case PIPE_FORMAT_ETC2_RG11_UNORM:
1531 case PIPE_FORMAT_ETC2_RG11_SNORM:
1532 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1533 default:
1534 goto out_unknown;
1535 }
1536 }
1537
1538 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1539 if (!enable_compressed_formats)
1540 goto out_unknown;
1541
1542 switch (format) {
1543 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1544 case PIPE_FORMAT_BPTC_SRGBA:
1545 return V_008F14_IMG_DATA_FORMAT_BC7;
1546 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1547 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1548 return V_008F14_IMG_DATA_FORMAT_BC6;
1549 default:
1550 goto out_unknown;
1551 }
1552 }
1553
1554 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1555 switch (format) {
1556 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1557 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1558 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1559 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1560 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1561 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1562 default:
1563 goto out_unknown;
1564 }
1565 }
1566
1567 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1568 if (!enable_compressed_formats)
1569 goto out_unknown;
1570
1571 if (!util_format_s3tc_enabled) {
1572 goto out_unknown;
1573 }
1574
1575 switch (format) {
1576 case PIPE_FORMAT_DXT1_RGB:
1577 case PIPE_FORMAT_DXT1_RGBA:
1578 case PIPE_FORMAT_DXT1_SRGB:
1579 case PIPE_FORMAT_DXT1_SRGBA:
1580 return V_008F14_IMG_DATA_FORMAT_BC1;
1581 case PIPE_FORMAT_DXT3_RGBA:
1582 case PIPE_FORMAT_DXT3_SRGBA:
1583 return V_008F14_IMG_DATA_FORMAT_BC2;
1584 case PIPE_FORMAT_DXT5_RGBA:
1585 case PIPE_FORMAT_DXT5_SRGBA:
1586 return V_008F14_IMG_DATA_FORMAT_BC3;
1587 default:
1588 goto out_unknown;
1589 }
1590 }
1591
1592 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1593 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1594 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1595 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1596 }
1597
1598 /* R8G8Bx_SNORM - TODO CxV8U8 */
1599
1600 /* hw cannot support mixed formats (except depth/stencil, since only
1601 * depth is read).*/
1602 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1603 goto out_unknown;
1604
1605 /* See whether the components are of the same size. */
1606 for (i = 1; i < desc->nr_channels; i++) {
1607 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1608 }
1609
1610 /* Non-uniform formats. */
1611 if (!uniform) {
1612 switch(desc->nr_channels) {
1613 case 3:
1614 if (desc->channel[0].size == 5 &&
1615 desc->channel[1].size == 6 &&
1616 desc->channel[2].size == 5) {
1617 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1618 }
1619 goto out_unknown;
1620 case 4:
1621 if (desc->channel[0].size == 5 &&
1622 desc->channel[1].size == 5 &&
1623 desc->channel[2].size == 5 &&
1624 desc->channel[3].size == 1) {
1625 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1626 }
1627 if (desc->channel[0].size == 10 &&
1628 desc->channel[1].size == 10 &&
1629 desc->channel[2].size == 10 &&
1630 desc->channel[3].size == 2) {
1631 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1632 }
1633 goto out_unknown;
1634 }
1635 goto out_unknown;
1636 }
1637
1638 if (first_non_void < 0 || first_non_void > 3)
1639 goto out_unknown;
1640
1641 /* uniform formats */
1642 switch (desc->channel[first_non_void].size) {
1643 case 4:
1644 switch (desc->nr_channels) {
1645 #if 0 /* Not supported for render targets */
1646 case 2:
1647 return V_008F14_IMG_DATA_FORMAT_4_4;
1648 #endif
1649 case 4:
1650 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1651 }
1652 break;
1653 case 8:
1654 switch (desc->nr_channels) {
1655 case 1:
1656 return V_008F14_IMG_DATA_FORMAT_8;
1657 case 2:
1658 return V_008F14_IMG_DATA_FORMAT_8_8;
1659 case 4:
1660 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1661 }
1662 break;
1663 case 16:
1664 switch (desc->nr_channels) {
1665 case 1:
1666 return V_008F14_IMG_DATA_FORMAT_16;
1667 case 2:
1668 return V_008F14_IMG_DATA_FORMAT_16_16;
1669 case 4:
1670 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1671 }
1672 break;
1673 case 32:
1674 switch (desc->nr_channels) {
1675 case 1:
1676 return V_008F14_IMG_DATA_FORMAT_32;
1677 case 2:
1678 return V_008F14_IMG_DATA_FORMAT_32_32;
1679 #if 0 /* Not supported for render targets */
1680 case 3:
1681 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1682 #endif
1683 case 4:
1684 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1685 }
1686 }
1687
1688 out_unknown:
1689 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1690 return ~0;
1691 }
1692
1693 static unsigned si_tex_wrap(unsigned wrap)
1694 {
1695 switch (wrap) {
1696 default:
1697 case PIPE_TEX_WRAP_REPEAT:
1698 return V_008F30_SQ_TEX_WRAP;
1699 case PIPE_TEX_WRAP_CLAMP:
1700 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1701 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1702 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1703 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1704 return V_008F30_SQ_TEX_CLAMP_BORDER;
1705 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1706 return V_008F30_SQ_TEX_MIRROR;
1707 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1708 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1709 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1710 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1711 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1712 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1713 }
1714 }
1715
1716 static unsigned si_tex_mipfilter(unsigned filter)
1717 {
1718 switch (filter) {
1719 case PIPE_TEX_MIPFILTER_NEAREST:
1720 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1721 case PIPE_TEX_MIPFILTER_LINEAR:
1722 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1723 default:
1724 case PIPE_TEX_MIPFILTER_NONE:
1725 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1726 }
1727 }
1728
1729 static unsigned si_tex_compare(unsigned compare)
1730 {
1731 switch (compare) {
1732 default:
1733 case PIPE_FUNC_NEVER:
1734 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1735 case PIPE_FUNC_LESS:
1736 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1737 case PIPE_FUNC_EQUAL:
1738 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1739 case PIPE_FUNC_LEQUAL:
1740 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1741 case PIPE_FUNC_GREATER:
1742 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1743 case PIPE_FUNC_NOTEQUAL:
1744 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1745 case PIPE_FUNC_GEQUAL:
1746 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1747 case PIPE_FUNC_ALWAYS:
1748 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1749 }
1750 }
1751
1752 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1753 unsigned view_target, unsigned nr_samples)
1754 {
1755 unsigned res_target = rtex->resource.b.b.target;
1756
1757 if (view_target == PIPE_TEXTURE_CUBE ||
1758 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1759 res_target = view_target;
1760 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1761 else if (res_target == PIPE_TEXTURE_CUBE ||
1762 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1763 res_target = PIPE_TEXTURE_2D_ARRAY;
1764
1765 /* GFX9 allocates 1D textures as 2D. */
1766 if ((res_target == PIPE_TEXTURE_1D ||
1767 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1768 sscreen->b.chip_class >= GFX9 &&
1769 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1770 if (res_target == PIPE_TEXTURE_1D)
1771 res_target = PIPE_TEXTURE_2D;
1772 else
1773 res_target = PIPE_TEXTURE_2D_ARRAY;
1774 }
1775
1776 switch (res_target) {
1777 default:
1778 case PIPE_TEXTURE_1D:
1779 return V_008F1C_SQ_RSRC_IMG_1D;
1780 case PIPE_TEXTURE_1D_ARRAY:
1781 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1782 case PIPE_TEXTURE_2D:
1783 case PIPE_TEXTURE_RECT:
1784 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1785 V_008F1C_SQ_RSRC_IMG_2D;
1786 case PIPE_TEXTURE_2D_ARRAY:
1787 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1788 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1789 case PIPE_TEXTURE_3D:
1790 return V_008F1C_SQ_RSRC_IMG_3D;
1791 case PIPE_TEXTURE_CUBE:
1792 case PIPE_TEXTURE_CUBE_ARRAY:
1793 return V_008F1C_SQ_RSRC_IMG_CUBE;
1794 }
1795 }
1796
1797 /*
1798 * Format support testing
1799 */
1800
1801 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1802 {
1803 const struct util_format_description *desc = util_format_description(format);
1804 if (!desc)
1805 return false;
1806
1807 return si_translate_texformat(screen, format, desc,
1808 util_format_get_first_non_void_channel(format)) != ~0U;
1809 }
1810
1811 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1812 const struct util_format_description *desc,
1813 int first_non_void)
1814 {
1815 int i;
1816
1817 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1818 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1819
1820 assert(first_non_void >= 0);
1821
1822 if (desc->nr_channels == 4 &&
1823 desc->channel[0].size == 10 &&
1824 desc->channel[1].size == 10 &&
1825 desc->channel[2].size == 10 &&
1826 desc->channel[3].size == 2)
1827 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1828
1829 /* See whether the components are of the same size. */
1830 for (i = 0; i < desc->nr_channels; i++) {
1831 if (desc->channel[first_non_void].size != desc->channel[i].size)
1832 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1833 }
1834
1835 switch (desc->channel[first_non_void].size) {
1836 case 8:
1837 switch (desc->nr_channels) {
1838 case 1:
1839 case 3: /* 3 loads */
1840 return V_008F0C_BUF_DATA_FORMAT_8;
1841 case 2:
1842 return V_008F0C_BUF_DATA_FORMAT_8_8;
1843 case 4:
1844 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1845 }
1846 break;
1847 case 16:
1848 switch (desc->nr_channels) {
1849 case 1:
1850 case 3: /* 3 loads */
1851 return V_008F0C_BUF_DATA_FORMAT_16;
1852 case 2:
1853 return V_008F0C_BUF_DATA_FORMAT_16_16;
1854 case 4:
1855 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1856 }
1857 break;
1858 case 32:
1859 switch (desc->nr_channels) {
1860 case 1:
1861 return V_008F0C_BUF_DATA_FORMAT_32;
1862 case 2:
1863 return V_008F0C_BUF_DATA_FORMAT_32_32;
1864 case 3:
1865 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1866 case 4:
1867 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1868 }
1869 break;
1870 case 64:
1871 /* Legacy double formats. */
1872 switch (desc->nr_channels) {
1873 case 1: /* 1 load */
1874 return V_008F0C_BUF_DATA_FORMAT_32_32;
1875 case 2: /* 1 load */
1876 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1877 case 3: /* 3 loads */
1878 return V_008F0C_BUF_DATA_FORMAT_32_32;
1879 case 4: /* 2 loads */
1880 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1881 }
1882 break;
1883 }
1884
1885 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1886 }
1887
1888 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1889 const struct util_format_description *desc,
1890 int first_non_void)
1891 {
1892 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1893 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1894
1895 assert(first_non_void >= 0);
1896
1897 switch (desc->channel[first_non_void].type) {
1898 case UTIL_FORMAT_TYPE_SIGNED:
1899 case UTIL_FORMAT_TYPE_FIXED:
1900 if (desc->channel[first_non_void].size >= 32 ||
1901 desc->channel[first_non_void].pure_integer)
1902 return V_008F0C_BUF_NUM_FORMAT_SINT;
1903 else if (desc->channel[first_non_void].normalized)
1904 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1905 else
1906 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1907 break;
1908 case UTIL_FORMAT_TYPE_UNSIGNED:
1909 if (desc->channel[first_non_void].size >= 32 ||
1910 desc->channel[first_non_void].pure_integer)
1911 return V_008F0C_BUF_NUM_FORMAT_UINT;
1912 else if (desc->channel[first_non_void].normalized)
1913 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1914 else
1915 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1916 break;
1917 case UTIL_FORMAT_TYPE_FLOAT:
1918 default:
1919 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1920 }
1921 }
1922
1923 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1924 enum pipe_format format,
1925 unsigned usage)
1926 {
1927 const struct util_format_description *desc;
1928 int first_non_void;
1929 unsigned data_format;
1930
1931 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1932 PIPE_BIND_SAMPLER_VIEW |
1933 PIPE_BIND_VERTEX_BUFFER)) == 0);
1934
1935 desc = util_format_description(format);
1936 if (!desc)
1937 return 0;
1938
1939 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1940 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1941 * for read-only access (with caveats surrounding bounds checks), but
1942 * obviously fails for write access which we have to implement for
1943 * shader images. Luckily, OpenGL doesn't expect this to be supported
1944 * anyway, and so the only impact is on PBO uploads / downloads, which
1945 * shouldn't be expected to be fast for GL_RGB anyway.
1946 */
1947 if (desc->block.bits == 3 * 8 ||
1948 desc->block.bits == 3 * 16) {
1949 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1950 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1951 if (!usage)
1952 return 0;
1953 }
1954 }
1955
1956 first_non_void = util_format_get_first_non_void_channel(format);
1957 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1958 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1959 return 0;
1960
1961 return usage;
1962 }
1963
1964 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1965 {
1966 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1967 r600_translate_colorswap(format, false) != ~0U;
1968 }
1969
1970 static bool si_is_zs_format_supported(enum pipe_format format)
1971 {
1972 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1973 }
1974
1975 static boolean si_is_format_supported(struct pipe_screen *screen,
1976 enum pipe_format format,
1977 enum pipe_texture_target target,
1978 unsigned sample_count,
1979 unsigned usage)
1980 {
1981 unsigned retval = 0;
1982
1983 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1984 R600_ERR("r600: unsupported texture type %d\n", target);
1985 return false;
1986 }
1987
1988 if (!util_format_is_supported(format, usage))
1989 return false;
1990
1991 if (sample_count > 1) {
1992 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1993 return false;
1994
1995 if (usage & PIPE_BIND_SHADER_IMAGE)
1996 return false;
1997
1998 switch (sample_count) {
1999 case 2:
2000 case 4:
2001 case 8:
2002 break;
2003 case 16:
2004 if (format == PIPE_FORMAT_NONE)
2005 return true;
2006 else
2007 return false;
2008 default:
2009 return false;
2010 }
2011 }
2012
2013 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2014 PIPE_BIND_SHADER_IMAGE)) {
2015 if (target == PIPE_BUFFER) {
2016 retval |= si_is_vertex_format_supported(
2017 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2018 PIPE_BIND_SHADER_IMAGE));
2019 } else {
2020 if (si_is_sampler_format_supported(screen, format))
2021 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2022 PIPE_BIND_SHADER_IMAGE);
2023 }
2024 }
2025
2026 if ((usage & (PIPE_BIND_RENDER_TARGET |
2027 PIPE_BIND_DISPLAY_TARGET |
2028 PIPE_BIND_SCANOUT |
2029 PIPE_BIND_SHARED |
2030 PIPE_BIND_BLENDABLE)) &&
2031 si_is_colorbuffer_format_supported(format)) {
2032 retval |= usage &
2033 (PIPE_BIND_RENDER_TARGET |
2034 PIPE_BIND_DISPLAY_TARGET |
2035 PIPE_BIND_SCANOUT |
2036 PIPE_BIND_SHARED);
2037 if (!util_format_is_pure_integer(format) &&
2038 !util_format_is_depth_or_stencil(format))
2039 retval |= usage & PIPE_BIND_BLENDABLE;
2040 }
2041
2042 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2043 si_is_zs_format_supported(format)) {
2044 retval |= PIPE_BIND_DEPTH_STENCIL;
2045 }
2046
2047 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2048 retval |= si_is_vertex_format_supported(screen, format,
2049 PIPE_BIND_VERTEX_BUFFER);
2050 }
2051
2052 if ((usage & PIPE_BIND_LINEAR) &&
2053 !util_format_is_compressed(format) &&
2054 !(usage & PIPE_BIND_DEPTH_STENCIL))
2055 retval |= PIPE_BIND_LINEAR;
2056
2057 return retval == usage;
2058 }
2059
2060 /*
2061 * framebuffer handling
2062 */
2063
2064 static void si_choose_spi_color_formats(struct r600_surface *surf,
2065 unsigned format, unsigned swap,
2066 unsigned ntype, bool is_depth)
2067 {
2068 /* Alpha is needed for alpha-to-coverage.
2069 * Blending may be with or without alpha.
2070 */
2071 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2072 unsigned alpha = 0; /* exports alpha, but may not support blending */
2073 unsigned blend = 0; /* supports blending, but may not export alpha */
2074 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2075
2076 /* Choose the SPI color formats. These are required values for RB+.
2077 * Other chips have multiple choices, though they are not necessarily better.
2078 */
2079 switch (format) {
2080 case V_028C70_COLOR_5_6_5:
2081 case V_028C70_COLOR_1_5_5_5:
2082 case V_028C70_COLOR_5_5_5_1:
2083 case V_028C70_COLOR_4_4_4_4:
2084 case V_028C70_COLOR_10_11_11:
2085 case V_028C70_COLOR_11_11_10:
2086 case V_028C70_COLOR_8:
2087 case V_028C70_COLOR_8_8:
2088 case V_028C70_COLOR_8_8_8_8:
2089 case V_028C70_COLOR_10_10_10_2:
2090 case V_028C70_COLOR_2_10_10_10:
2091 if (ntype == V_028C70_NUMBER_UINT)
2092 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2093 else if (ntype == V_028C70_NUMBER_SINT)
2094 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2095 else
2096 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2097 break;
2098
2099 case V_028C70_COLOR_16:
2100 case V_028C70_COLOR_16_16:
2101 case V_028C70_COLOR_16_16_16_16:
2102 if (ntype == V_028C70_NUMBER_UNORM ||
2103 ntype == V_028C70_NUMBER_SNORM) {
2104 /* UNORM16 and SNORM16 don't support blending */
2105 if (ntype == V_028C70_NUMBER_UNORM)
2106 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2107 else
2108 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2109
2110 /* Use 32 bits per channel for blending. */
2111 if (format == V_028C70_COLOR_16) {
2112 if (swap == V_028C70_SWAP_STD) { /* R */
2113 blend = V_028714_SPI_SHADER_32_R;
2114 blend_alpha = V_028714_SPI_SHADER_32_AR;
2115 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2116 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2117 else
2118 assert(0);
2119 } else if (format == V_028C70_COLOR_16_16) {
2120 if (swap == V_028C70_SWAP_STD) { /* RG */
2121 blend = V_028714_SPI_SHADER_32_GR;
2122 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2123 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2124 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2125 else
2126 assert(0);
2127 } else /* 16_16_16_16 */
2128 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2129 } else if (ntype == V_028C70_NUMBER_UINT)
2130 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2131 else if (ntype == V_028C70_NUMBER_SINT)
2132 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2133 else if (ntype == V_028C70_NUMBER_FLOAT)
2134 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2135 else
2136 assert(0);
2137 break;
2138
2139 case V_028C70_COLOR_32:
2140 if (swap == V_028C70_SWAP_STD) { /* R */
2141 blend = normal = V_028714_SPI_SHADER_32_R;
2142 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2143 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2144 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2145 else
2146 assert(0);
2147 break;
2148
2149 case V_028C70_COLOR_32_32:
2150 if (swap == V_028C70_SWAP_STD) { /* RG */
2151 blend = normal = V_028714_SPI_SHADER_32_GR;
2152 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2153 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2154 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2155 else
2156 assert(0);
2157 break;
2158
2159 case V_028C70_COLOR_32_32_32_32:
2160 case V_028C70_COLOR_8_24:
2161 case V_028C70_COLOR_24_8:
2162 case V_028C70_COLOR_X24_8_32_FLOAT:
2163 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2164 break;
2165
2166 default:
2167 assert(0);
2168 return;
2169 }
2170
2171 /* The DB->CB copy needs 32_ABGR. */
2172 if (is_depth)
2173 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2174
2175 surf->spi_shader_col_format = normal;
2176 surf->spi_shader_col_format_alpha = alpha;
2177 surf->spi_shader_col_format_blend = blend;
2178 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2179 }
2180
2181 static void si_initialize_color_surface(struct si_context *sctx,
2182 struct r600_surface *surf)
2183 {
2184 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2185 unsigned color_info, color_attrib, color_view;
2186 unsigned format, swap, ntype, endian;
2187 const struct util_format_description *desc;
2188 int firstchan;
2189 unsigned blend_clamp = 0, blend_bypass = 0;
2190
2191 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2192 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2193
2194 desc = util_format_description(surf->base.format);
2195 for (firstchan = 0; firstchan < 4; firstchan++) {
2196 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2197 break;
2198 }
2199 }
2200 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2201 ntype = V_028C70_NUMBER_FLOAT;
2202 } else {
2203 ntype = V_028C70_NUMBER_UNORM;
2204 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2205 ntype = V_028C70_NUMBER_SRGB;
2206 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2207 if (desc->channel[firstchan].pure_integer) {
2208 ntype = V_028C70_NUMBER_SINT;
2209 } else {
2210 assert(desc->channel[firstchan].normalized);
2211 ntype = V_028C70_NUMBER_SNORM;
2212 }
2213 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2214 if (desc->channel[firstchan].pure_integer) {
2215 ntype = V_028C70_NUMBER_UINT;
2216 } else {
2217 assert(desc->channel[firstchan].normalized);
2218 ntype = V_028C70_NUMBER_UNORM;
2219 }
2220 }
2221 }
2222
2223 format = si_translate_colorformat(surf->base.format);
2224 if (format == V_028C70_COLOR_INVALID) {
2225 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2226 }
2227 assert(format != V_028C70_COLOR_INVALID);
2228 swap = r600_translate_colorswap(surf->base.format, false);
2229 endian = si_colorformat_endian_swap(format);
2230
2231 /* blend clamp should be set for all NORM/SRGB types */
2232 if (ntype == V_028C70_NUMBER_UNORM ||
2233 ntype == V_028C70_NUMBER_SNORM ||
2234 ntype == V_028C70_NUMBER_SRGB)
2235 blend_clamp = 1;
2236
2237 /* set blend bypass according to docs if SINT/UINT or
2238 8/24 COLOR variants */
2239 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2240 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2241 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2242 blend_clamp = 0;
2243 blend_bypass = 1;
2244 }
2245
2246 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2247 if (format == V_028C70_COLOR_8 ||
2248 format == V_028C70_COLOR_8_8 ||
2249 format == V_028C70_COLOR_8_8_8_8)
2250 surf->color_is_int8 = true;
2251 else if (format == V_028C70_COLOR_10_10_10_2 ||
2252 format == V_028C70_COLOR_2_10_10_10)
2253 surf->color_is_int10 = true;
2254 }
2255
2256 color_info = S_028C70_FORMAT(format) |
2257 S_028C70_COMP_SWAP(swap) |
2258 S_028C70_BLEND_CLAMP(blend_clamp) |
2259 S_028C70_BLEND_BYPASS(blend_bypass) |
2260 S_028C70_SIMPLE_FLOAT(1) |
2261 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2262 ntype != V_028C70_NUMBER_SNORM &&
2263 ntype != V_028C70_NUMBER_SRGB &&
2264 format != V_028C70_COLOR_8_24 &&
2265 format != V_028C70_COLOR_24_8) |
2266 S_028C70_NUMBER_TYPE(ntype) |
2267 S_028C70_ENDIAN(endian);
2268
2269 /* Intensity is implemented as Red, so treat it that way. */
2270 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2271 util_format_is_intensity(surf->base.format));
2272
2273 if (rtex->resource.b.b.nr_samples > 1) {
2274 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2275
2276 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2277 S_028C74_NUM_FRAGMENTS(log_samples);
2278
2279 if (rtex->fmask.size) {
2280 color_info |= S_028C70_COMPRESSION(1);
2281 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2282
2283 if (sctx->b.chip_class == SI) {
2284 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2285 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2286 }
2287 }
2288 }
2289
2290 surf->cb_color_view = color_view;
2291 surf->cb_color_info = color_info;
2292 surf->cb_color_attrib = color_attrib;
2293
2294 if (sctx->b.chip_class >= VI) {
2295 unsigned max_uncompressed_block_size = 2;
2296
2297 if (rtex->resource.b.b.nr_samples > 1) {
2298 if (rtex->surface.bpe == 1)
2299 max_uncompressed_block_size = 0;
2300 else if (rtex->surface.bpe == 2)
2301 max_uncompressed_block_size = 1;
2302 }
2303
2304 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2305 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2306 }
2307
2308 /* This must be set for fast clear to work without FMASK. */
2309 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2310 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2311 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2312 }
2313
2314 if (sctx->b.chip_class >= GFX9) {
2315 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2316
2317 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2318 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2319 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2320 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2321 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2322 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2323 }
2324
2325 /* Determine pixel shader export format */
2326 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2327
2328 surf->color_initialized = true;
2329 }
2330
2331 static void si_init_depth_surface(struct si_context *sctx,
2332 struct r600_surface *surf)
2333 {
2334 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2335 unsigned level = surf->base.u.tex.level;
2336 unsigned format, stencil_format;
2337 uint32_t z_info, s_info;
2338
2339 format = si_translate_dbformat(rtex->db_render_format);
2340 stencil_format = rtex->surface.has_stencil ?
2341 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2342
2343 assert(format != V_028040_Z_INVALID);
2344 if (format == V_028040_Z_INVALID)
2345 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2346
2347 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2348 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2349 surf->db_htile_data_base = 0;
2350 surf->db_htile_surface = 0;
2351
2352 if (sctx->b.chip_class >= GFX9) {
2353 assert(rtex->surface.u.gfx9.surf_offset == 0);
2354 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2355 surf->db_stencil_base = (rtex->resource.gpu_address +
2356 rtex->surface.u.gfx9.stencil_offset) >> 8;
2357 z_info = S_028038_FORMAT(format) |
2358 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2359 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2360 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2361 s_info = S_02803C_FORMAT(stencil_format) |
2362 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2363 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2364 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2365 surf->db_depth_view |= S_028008_MIPID(level);
2366 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2367 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2368
2369 if (r600_htile_enabled(rtex, level)) {
2370 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2371 S_028038_ALLOW_EXPCLEAR(1);
2372
2373 if (rtex->tc_compatible_htile) {
2374 unsigned max_zplanes = 4;
2375
2376 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2377 rtex->resource.b.b.nr_samples > 1)
2378 max_zplanes = 2;
2379
2380 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2381 S_028038_ITERATE_FLUSH(1);
2382 s_info |= S_02803C_ITERATE_FLUSH(1);
2383 }
2384
2385 if (rtex->surface.has_stencil) {
2386 /* Stencil buffer workaround ported from the SI-CI-VI code.
2387 * See that for explanation.
2388 */
2389 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2390 } else {
2391 /* Use all HTILE for depth if there's no stencil. */
2392 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2393 }
2394
2395 surf->db_htile_data_base = (rtex->resource.gpu_address +
2396 rtex->htile_offset) >> 8;
2397 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2398 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2399 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2400 }
2401 } else {
2402 /* SI-CI-VI */
2403 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2404
2405 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2406
2407 surf->db_depth_base = (rtex->resource.gpu_address +
2408 rtex->surface.u.legacy.level[level].offset) >> 8;
2409 surf->db_stencil_base = (rtex->resource.gpu_address +
2410 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2411
2412 z_info = S_028040_FORMAT(format) |
2413 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2414 s_info = S_028044_FORMAT(stencil_format);
2415 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2416
2417 if (sctx->b.chip_class >= CIK) {
2418 struct radeon_info *info = &sctx->screen->b.info;
2419 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2420 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2421 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2422 unsigned tile_mode = info->si_tile_mode_array[index];
2423 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2424 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2425
2426 surf->db_depth_info |=
2427 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2428 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2429 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2430 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2431 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2432 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2433 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2434 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2435 } else {
2436 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2437 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2438 tile_mode_index = si_tile_mode_index(rtex, level, true);
2439 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2440 }
2441
2442 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2443 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2444 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2445 levelinfo->nblk_y) / 64 - 1);
2446
2447 if (r600_htile_enabled(rtex, level)) {
2448 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2449 S_028040_ALLOW_EXPCLEAR(1);
2450
2451 if (rtex->surface.has_stencil) {
2452 /* Workaround: For a not yet understood reason, the
2453 * combination of MSAA, fast stencil clear and stencil
2454 * decompress messes with subsequent stencil buffer
2455 * uses. Problem was reproduced on Verde, Bonaire,
2456 * Tonga, and Carrizo.
2457 *
2458 * Disabling EXPCLEAR works around the problem.
2459 *
2460 * Check piglit's arb_texture_multisample-stencil-clear
2461 * test if you want to try changing this.
2462 */
2463 if (rtex->resource.b.b.nr_samples <= 1)
2464 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2465 } else if (!rtex->tc_compatible_htile) {
2466 /* Use all of the htile_buffer for depth if there's no stencil.
2467 * This must not be set when TC-compatible HTILE is enabled
2468 * due to a hw bug.
2469 */
2470 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2471 }
2472
2473 surf->db_htile_data_base = (rtex->resource.gpu_address +
2474 rtex->htile_offset) >> 8;
2475 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2476
2477 if (rtex->tc_compatible_htile) {
2478 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2479
2480 if (rtex->resource.b.b.nr_samples <= 1)
2481 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2482 else if (rtex->resource.b.b.nr_samples <= 4)
2483 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2484 else
2485 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2486 }
2487 }
2488 }
2489
2490 surf->db_z_info = z_info;
2491 surf->db_stencil_info = s_info;
2492
2493 surf->depth_initialized = true;
2494 }
2495
2496 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2497 {
2498 if (sctx->decompression_enabled)
2499 return;
2500
2501 if (sctx->framebuffer.state.zsbuf) {
2502 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2503 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2504
2505 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2506
2507 if (rtex->surface.has_stencil)
2508 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2509 }
2510 if (sctx->framebuffer.compressed_cb_mask) {
2511 struct pipe_surface *surf;
2512 struct r600_texture *rtex;
2513 unsigned mask = sctx->framebuffer.compressed_cb_mask;
2514
2515 do {
2516 unsigned i = u_bit_scan(&mask);
2517 surf = sctx->framebuffer.state.cbufs[i];
2518 rtex = (struct r600_texture*)surf->texture;
2519
2520 if (rtex->fmask.size)
2521 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2522 if (rtex->dcc_gather_statistics)
2523 rtex->separate_dcc_dirty = true;
2524 } while (mask);
2525 }
2526 }
2527
2528 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2529 {
2530 for (int i = 0; i < state->nr_cbufs; ++i) {
2531 struct r600_surface *surf = NULL;
2532 struct r600_texture *rtex;
2533
2534 if (!state->cbufs[i])
2535 continue;
2536 surf = (struct r600_surface*)state->cbufs[i];
2537 rtex = (struct r600_texture*)surf->base.texture;
2538
2539 p_atomic_dec(&rtex->framebuffers_bound);
2540 }
2541 }
2542
2543 static void si_set_framebuffer_state(struct pipe_context *ctx,
2544 const struct pipe_framebuffer_state *state)
2545 {
2546 struct si_context *sctx = (struct si_context *)ctx;
2547 struct pipe_constant_buffer constbuf = {0};
2548 struct r600_surface *surf = NULL;
2549 struct r600_texture *rtex;
2550 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2551 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2552 bool unbound = false;
2553 int i;
2554
2555 si_update_fb_dirtiness_after_rendering(sctx);
2556
2557 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2558 if (!sctx->framebuffer.state.cbufs[i])
2559 continue;
2560
2561 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2562 if (rtex->dcc_gather_statistics)
2563 vi_separate_dcc_stop_query(ctx, rtex);
2564 }
2565
2566 /* Disable DCC if the formats are incompatible. */
2567 for (i = 0; i < state->nr_cbufs; i++) {
2568 if (!state->cbufs[i])
2569 continue;
2570
2571 surf = (struct r600_surface*)state->cbufs[i];
2572 rtex = (struct r600_texture*)surf->base.texture;
2573
2574 if (!surf->dcc_incompatible)
2575 continue;
2576
2577 /* Since the DCC decompression calls back into set_framebuffer-
2578 * _state, we need to unbind the framebuffer, so that
2579 * vi_separate_dcc_stop_query isn't called twice with the same
2580 * color buffer.
2581 */
2582 if (!unbound) {
2583 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2584 unbound = true;
2585 }
2586
2587 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2588 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2589 sctx->b.decompress_dcc(ctx, rtex);
2590
2591 surf->dcc_incompatible = false;
2592 }
2593
2594 /* Only flush TC when changing the framebuffer state, because
2595 * the only client not using TC that can change textures is
2596 * the framebuffer.
2597 *
2598 * Wait for compute shaders because of possible transitions:
2599 * - FB write -> shader read
2600 * - shader write -> FB read
2601 *
2602 * DB caches are flushed on demand (using si_decompress_textures).
2603 *
2604 * When MSAA is enabled, CB and TC caches are flushed on demand
2605 * (after FMASK decompression). Shader write -> FB read transitions
2606 * cannot happen for MSAA textures, because MSAA shader images are
2607 * not supported.
2608 *
2609 * Only flush and wait for CB if there is actually a bound color buffer.
2610 */
2611 if (sctx->framebuffer.nr_samples <= 1 &&
2612 sctx->framebuffer.state.nr_cbufs)
2613 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2614 sctx->framebuffer.CB_has_shader_readable_metadata);
2615
2616 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2617
2618 /* u_blitter doesn't invoke depth decompression when it does multiple
2619 * blits in a row, but the only case when it matters for DB is when
2620 * doing generate_mipmap. So here we flush DB manually between
2621 * individual generate_mipmap blits.
2622 * Note that lower mipmap levels aren't compressed.
2623 */
2624 if (sctx->generate_mipmap_for_depth) {
2625 si_make_DB_shader_coherent(sctx, 1, false,
2626 sctx->framebuffer.DB_has_shader_readable_metadata);
2627 } else if (sctx->b.chip_class == GFX9) {
2628 /* It appears that DB metadata "leaks" in a sequence of:
2629 * - depth clear
2630 * - DCC decompress for shader image writes (with DB disabled)
2631 * - render with DEPTH_BEFORE_SHADER=1
2632 * Flushing DB metadata works around the problem.
2633 */
2634 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2635 }
2636
2637 /* Take the maximum of the old and new count. If the new count is lower,
2638 * dirtying is needed to disable the unbound colorbuffers.
2639 */
2640 sctx->framebuffer.dirty_cbufs |=
2641 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2642 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2643
2644 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2645 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2646
2647 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2648 sctx->framebuffer.spi_shader_col_format = 0;
2649 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2650 sctx->framebuffer.spi_shader_col_format_blend = 0;
2651 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2652 sctx->framebuffer.color_is_int8 = 0;
2653 sctx->framebuffer.color_is_int10 = 0;
2654
2655 sctx->framebuffer.compressed_cb_mask = 0;
2656 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2657 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2658 sctx->framebuffer.any_dst_linear = false;
2659 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2660 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2661
2662 for (i = 0; i < state->nr_cbufs; i++) {
2663 if (!state->cbufs[i])
2664 continue;
2665
2666 surf = (struct r600_surface*)state->cbufs[i];
2667 rtex = (struct r600_texture*)surf->base.texture;
2668
2669 if (!surf->color_initialized) {
2670 si_initialize_color_surface(sctx, surf);
2671 }
2672
2673 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2674 sctx->framebuffer.spi_shader_col_format |=
2675 surf->spi_shader_col_format << (i * 4);
2676 sctx->framebuffer.spi_shader_col_format_alpha |=
2677 surf->spi_shader_col_format_alpha << (i * 4);
2678 sctx->framebuffer.spi_shader_col_format_blend |=
2679 surf->spi_shader_col_format_blend << (i * 4);
2680 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2681 surf->spi_shader_col_format_blend_alpha << (i * 4);
2682
2683 if (surf->color_is_int8)
2684 sctx->framebuffer.color_is_int8 |= 1 << i;
2685 if (surf->color_is_int10)
2686 sctx->framebuffer.color_is_int10 |= 1 << i;
2687
2688 if (rtex->fmask.size) {
2689 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2690 }
2691
2692 if (rtex->surface.is_linear)
2693 sctx->framebuffer.any_dst_linear = true;
2694
2695 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2696 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2697
2698 r600_context_add_resource_size(ctx, surf->base.texture);
2699
2700 p_atomic_inc(&rtex->framebuffers_bound);
2701
2702 if (rtex->dcc_gather_statistics) {
2703 /* Dirty tracking must be enabled for DCC usage analysis. */
2704 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2705 vi_separate_dcc_start_query(ctx, rtex);
2706 }
2707 }
2708
2709 if (state->zsbuf) {
2710 surf = (struct r600_surface*)state->zsbuf;
2711 rtex = (struct r600_texture*)surf->base.texture;
2712
2713 if (!surf->depth_initialized) {
2714 si_init_depth_surface(sctx, surf);
2715 }
2716
2717 if (vi_tc_compat_htile_enabled(rtex, surf->base.u.tex.level))
2718 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2719
2720 r600_context_add_resource_size(ctx, surf->base.texture);
2721 }
2722
2723 si_update_poly_offset_state(sctx);
2724 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2725 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2726
2727 if (sctx->screen->dpbb_allowed)
2728 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2729
2730 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2731 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2732
2733 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2734 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2735 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2736
2737 /* Set sample locations as fragment shader constants. */
2738 switch (sctx->framebuffer.nr_samples) {
2739 case 1:
2740 constbuf.user_buffer = sctx->b.sample_locations_1x;
2741 break;
2742 case 2:
2743 constbuf.user_buffer = sctx->b.sample_locations_2x;
2744 break;
2745 case 4:
2746 constbuf.user_buffer = sctx->b.sample_locations_4x;
2747 break;
2748 case 8:
2749 constbuf.user_buffer = sctx->b.sample_locations_8x;
2750 break;
2751 case 16:
2752 constbuf.user_buffer = sctx->b.sample_locations_16x;
2753 break;
2754 default:
2755 R600_ERR("Requested an invalid number of samples %i.\n",
2756 sctx->framebuffer.nr_samples);
2757 assert(0);
2758 }
2759 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2760 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2761
2762 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2763 }
2764
2765 sctx->do_update_shaders = true;
2766
2767 if (!sctx->decompression_enabled) {
2768 /* Prevent textures decompression when the framebuffer state
2769 * changes come from the decompression passes themselves.
2770 */
2771 sctx->need_check_render_feedback = true;
2772 }
2773 }
2774
2775 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2776 {
2777 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2778 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2779 unsigned i, nr_cbufs = state->nr_cbufs;
2780 struct r600_texture *tex = NULL;
2781 struct r600_surface *cb = NULL;
2782 unsigned cb_color_info = 0;
2783
2784 /* Colorbuffers. */
2785 for (i = 0; i < nr_cbufs; i++) {
2786 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2787 unsigned cb_color_attrib;
2788
2789 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2790 continue;
2791
2792 cb = (struct r600_surface*)state->cbufs[i];
2793 if (!cb) {
2794 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2795 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2796 continue;
2797 }
2798
2799 tex = (struct r600_texture *)cb->base.texture;
2800 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2801 &tex->resource, RADEON_USAGE_READWRITE,
2802 tex->resource.b.b.nr_samples > 1 ?
2803 RADEON_PRIO_COLOR_BUFFER_MSAA :
2804 RADEON_PRIO_COLOR_BUFFER);
2805
2806 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2807 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2808 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2809 RADEON_PRIO_CMASK);
2810 }
2811
2812 if (tex->dcc_separate_buffer)
2813 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2814 tex->dcc_separate_buffer,
2815 RADEON_USAGE_READWRITE,
2816 RADEON_PRIO_DCC);
2817
2818 /* Compute mutable surface parameters. */
2819 cb_color_base = tex->resource.gpu_address >> 8;
2820 cb_color_fmask = 0;
2821 cb_dcc_base = 0;
2822 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2823 cb_color_attrib = cb->cb_color_attrib;
2824
2825 if (tex->fmask.size) {
2826 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2827 cb_color_fmask |= tex->fmask.tile_swizzle;
2828 }
2829
2830 /* Set up DCC. */
2831 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2832 bool is_msaa_resolve_dst = state->cbufs[0] &&
2833 state->cbufs[0]->texture->nr_samples > 1 &&
2834 state->cbufs[1] == &cb->base &&
2835 state->cbufs[1]->texture->nr_samples <= 1;
2836
2837 if (!is_msaa_resolve_dst)
2838 cb_color_info |= S_028C70_DCC_ENABLE(1);
2839
2840 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2841 tex->dcc_offset) >> 8;
2842 cb_dcc_base |= tex->surface.tile_swizzle;
2843 }
2844
2845 if (sctx->b.chip_class >= GFX9) {
2846 struct gfx9_surf_meta_flags meta;
2847
2848 if (tex->dcc_offset)
2849 meta = tex->surface.u.gfx9.dcc;
2850 else
2851 meta = tex->surface.u.gfx9.cmask;
2852
2853 /* Set mutable surface parameters. */
2854 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2855 cb_color_base |= tex->surface.tile_swizzle;
2856 if (!tex->fmask.size)
2857 cb_color_fmask = cb_color_base;
2858 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2859 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2860 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2861 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2862
2863 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2864 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2865 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2866 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2867 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2868 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2869 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2870 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2871 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2872 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2873 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2874 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2875 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2876 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2877 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2878 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2879
2880 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2881 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2882 } else {
2883 /* Compute mutable surface parameters (SI-CI-VI). */
2884 const struct legacy_surf_level *level_info =
2885 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2886 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2887 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2888
2889 cb_color_base += level_info->offset >> 8;
2890 /* Only macrotiled modes can set tile swizzle. */
2891 if (level_info->mode == RADEON_SURF_MODE_2D)
2892 cb_color_base |= tex->surface.tile_swizzle;
2893
2894 if (!tex->fmask.size)
2895 cb_color_fmask = cb_color_base;
2896 if (cb_dcc_base)
2897 cb_dcc_base += level_info->dcc_offset >> 8;
2898
2899 pitch_tile_max = level_info->nblk_x / 8 - 1;
2900 slice_tile_max = level_info->nblk_x *
2901 level_info->nblk_y / 64 - 1;
2902 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2903
2904 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2905 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2906 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2907
2908 if (tex->fmask.size) {
2909 if (sctx->b.chip_class >= CIK)
2910 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2911 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2912 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2913 } else {
2914 /* This must be set for fast clear to work without FMASK. */
2915 if (sctx->b.chip_class >= CIK)
2916 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2917 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2918 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2919 }
2920
2921 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2922 sctx->b.chip_class >= VI ? 14 : 13);
2923 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2924 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2925 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2926 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2927 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2928 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2929 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2930 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2931 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2932 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2933 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2934 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2935 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2936
2937 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2938 radeon_emit(cs, cb_dcc_base);
2939 }
2940 }
2941 for (; i < 8 ; i++)
2942 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2943 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2944
2945 /* ZS buffer. */
2946 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2947 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2948 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2949
2950 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2951 &rtex->resource, RADEON_USAGE_READWRITE,
2952 zb->base.texture->nr_samples > 1 ?
2953 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2954 RADEON_PRIO_DEPTH_BUFFER);
2955
2956 if (sctx->b.chip_class >= GFX9) {
2957 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2958 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2959 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2960 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2961
2962 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2963 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2964 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2965 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2966 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2967 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2968 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2969 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2970 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2971 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2972 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2973 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2974
2975 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2976 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2977 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2978 } else {
2979 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2980
2981 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2982 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2983 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2984 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2985 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2986 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2987 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2988 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2989 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2990 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2991 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2992 }
2993
2994 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2995 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2996 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2997
2998 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2999 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3000 } else if (sctx->framebuffer.dirty_zsbuf) {
3001 if (sctx->b.chip_class >= GFX9)
3002 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3003 else
3004 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3005
3006 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3007 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3008 }
3009
3010 /* Framebuffer dimensions. */
3011 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3012 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3013 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3014
3015 if (sctx->screen->dfsm_allowed) {
3016 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3017 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3018 }
3019
3020 sctx->framebuffer.dirty_cbufs = 0;
3021 sctx->framebuffer.dirty_zsbuf = false;
3022 }
3023
3024 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3025 struct r600_atom *atom)
3026 {
3027 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3028 unsigned nr_samples = sctx->framebuffer.nr_samples;
3029 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3030
3031 /* Smoothing (only possible with nr_samples == 1) uses the same
3032 * sample locations as the MSAA it simulates.
3033 */
3034 if (nr_samples <= 1 && sctx->smoothing_enabled)
3035 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3036
3037 /* On Polaris, the small primitive filter uses the sample locations
3038 * even when MSAA is off, so we need to make sure they're set to 0.
3039 */
3040 if (has_msaa_sample_loc_bug)
3041 nr_samples = MAX2(nr_samples, 1);
3042
3043 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3044 sctx->msaa_sample_locs.nr_samples = nr_samples;
3045 cayman_emit_msaa_sample_locs(cs, nr_samples);
3046 }
3047
3048 if (sctx->b.family >= CHIP_POLARIS10) {
3049 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3050 unsigned small_prim_filter_cntl =
3051 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3052 /* line bug */
3053 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3054
3055 /* The alternative of setting sample locations to 0 would
3056 * require a DB flush to avoid Z errors, see
3057 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3058 */
3059 if (has_msaa_sample_loc_bug &&
3060 sctx->framebuffer.nr_samples > 1 &&
3061 rs && !rs->multisample_enable)
3062 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3063
3064 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3065 small_prim_filter_cntl);
3066 }
3067 }
3068
3069 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3070 {
3071 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3072 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
3073 /* 33% faster rendering to linear color buffers */
3074 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3075 unsigned sc_mode_cntl_1 =
3076 S_028A4C_WALK_SIZE(dst_is_linear) |
3077 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3078 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3079 /* always 1: */
3080 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3081 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3082 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3083 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3084 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3085 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3086
3087 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
3088 sctx->ps_iter_samples,
3089 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
3090 sc_mode_cntl_1);
3091
3092 /* GFX9: Flush DFSM when the AA mode changes. */
3093 if (sctx->screen->dfsm_allowed) {
3094 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3095 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3096 }
3097 }
3098
3099 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3100 {
3101 struct si_context *sctx = (struct si_context *)ctx;
3102
3103 if (sctx->ps_iter_samples == min_samples)
3104 return;
3105
3106 sctx->ps_iter_samples = min_samples;
3107 sctx->do_update_shaders = true;
3108
3109 if (sctx->framebuffer.nr_samples > 1)
3110 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3111 if (sctx->screen->dpbb_allowed)
3112 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3113 }
3114
3115 /*
3116 * Samplers
3117 */
3118
3119 /**
3120 * Build the sampler view descriptor for a buffer texture.
3121 * @param state 256-bit descriptor; only the high 128 bits are filled in
3122 */
3123 void
3124 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3125 enum pipe_format format,
3126 unsigned offset, unsigned size,
3127 uint32_t *state)
3128 {
3129 const struct util_format_description *desc;
3130 int first_non_void;
3131 unsigned stride;
3132 unsigned num_records;
3133 unsigned num_format, data_format;
3134
3135 desc = util_format_description(format);
3136 first_non_void = util_format_get_first_non_void_channel(format);
3137 stride = desc->block.bits / 8;
3138 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3139 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3140
3141 num_records = size / stride;
3142 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3143
3144 /* The NUM_RECORDS field has a different meaning depending on the chip,
3145 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3146 *
3147 * SI-CIK:
3148 * - If STRIDE == 0, it's in byte units.
3149 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3150 *
3151 * VI:
3152 * - For SMEM and STRIDE == 0, it's in byte units.
3153 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3154 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3155 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3156 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3157 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3158 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3159 * That way the same descriptor can be used by both SMEM and VMEM.
3160 *
3161 * GFX9:
3162 * - For SMEM and STRIDE == 0, it's in byte units.
3163 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3164 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3165 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3166 */
3167 if (screen->b.chip_class >= GFX9)
3168 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3169 * from STRIDE to bytes. This works around it by setting
3170 * NUM_RECORDS to at least the size of one element, so that
3171 * the first element is readable when IDXEN == 0.
3172 *
3173 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3174 * IDXEN is enforced?
3175 */
3176 num_records = num_records ? MAX2(num_records, stride) : 0;
3177 else if (screen->b.chip_class == VI)
3178 num_records *= stride;
3179
3180 state[4] = 0;
3181 state[5] = S_008F04_STRIDE(stride);
3182 state[6] = num_records;
3183 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3184 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3185 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3186 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3187 S_008F0C_NUM_FORMAT(num_format) |
3188 S_008F0C_DATA_FORMAT(data_format);
3189 }
3190
3191 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3192 {
3193 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3194
3195 if (swizzle[3] == PIPE_SWIZZLE_X) {
3196 /* For the pre-defined border color values (white, opaque
3197 * black, transparent black), the only thing that matters is
3198 * that the alpha channel winds up in the correct place
3199 * (because the RGB channels are all the same) so either of
3200 * these enumerations will work.
3201 */
3202 if (swizzle[2] == PIPE_SWIZZLE_Y)
3203 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3204 else
3205 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3206 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3207 if (swizzle[1] == PIPE_SWIZZLE_Y)
3208 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3209 else
3210 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3211 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3212 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3213 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3214 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3215 }
3216
3217 return bc_swizzle;
3218 }
3219
3220 /**
3221 * Build the sampler view descriptor for a texture.
3222 */
3223 void
3224 si_make_texture_descriptor(struct si_screen *screen,
3225 struct r600_texture *tex,
3226 bool sampler,
3227 enum pipe_texture_target target,
3228 enum pipe_format pipe_format,
3229 const unsigned char state_swizzle[4],
3230 unsigned first_level, unsigned last_level,
3231 unsigned first_layer, unsigned last_layer,
3232 unsigned width, unsigned height, unsigned depth,
3233 uint32_t *state,
3234 uint32_t *fmask_state)
3235 {
3236 struct pipe_resource *res = &tex->resource.b.b;
3237 const struct util_format_description *desc;
3238 unsigned char swizzle[4];
3239 int first_non_void;
3240 unsigned num_format, data_format, type;
3241 uint64_t va;
3242
3243 desc = util_format_description(pipe_format);
3244
3245 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3246 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3247 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3248 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3249
3250 switch (pipe_format) {
3251 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3252 case PIPE_FORMAT_X32_S8X24_UINT:
3253 case PIPE_FORMAT_X8Z24_UNORM:
3254 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3255 break;
3256 case PIPE_FORMAT_X24S8_UINT:
3257 /*
3258 * X24S8 is implemented as an 8_8_8_8 data format, to
3259 * fix texture gathers. This affects at least
3260 * GL45-CTS.texture_cube_map_array.sampling on VI.
3261 */
3262 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3263 break;
3264 default:
3265 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3266 }
3267 } else {
3268 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3269 }
3270
3271 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3272
3273 switch (pipe_format) {
3274 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3275 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3276 break;
3277 default:
3278 if (first_non_void < 0) {
3279 if (util_format_is_compressed(pipe_format)) {
3280 switch (pipe_format) {
3281 case PIPE_FORMAT_DXT1_SRGB:
3282 case PIPE_FORMAT_DXT1_SRGBA:
3283 case PIPE_FORMAT_DXT3_SRGBA:
3284 case PIPE_FORMAT_DXT5_SRGBA:
3285 case PIPE_FORMAT_BPTC_SRGBA:
3286 case PIPE_FORMAT_ETC2_SRGB8:
3287 case PIPE_FORMAT_ETC2_SRGB8A1:
3288 case PIPE_FORMAT_ETC2_SRGBA8:
3289 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3290 break;
3291 case PIPE_FORMAT_RGTC1_SNORM:
3292 case PIPE_FORMAT_LATC1_SNORM:
3293 case PIPE_FORMAT_RGTC2_SNORM:
3294 case PIPE_FORMAT_LATC2_SNORM:
3295 case PIPE_FORMAT_ETC2_R11_SNORM:
3296 case PIPE_FORMAT_ETC2_RG11_SNORM:
3297 /* implies float, so use SNORM/UNORM to determine
3298 whether data is signed or not */
3299 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3300 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3301 break;
3302 default:
3303 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3304 break;
3305 }
3306 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3307 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3308 } else {
3309 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3310 }
3311 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3312 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3313 } else {
3314 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3315
3316 switch (desc->channel[first_non_void].type) {
3317 case UTIL_FORMAT_TYPE_FLOAT:
3318 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3319 break;
3320 case UTIL_FORMAT_TYPE_SIGNED:
3321 if (desc->channel[first_non_void].normalized)
3322 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3323 else if (desc->channel[first_non_void].pure_integer)
3324 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3325 else
3326 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3327 break;
3328 case UTIL_FORMAT_TYPE_UNSIGNED:
3329 if (desc->channel[first_non_void].normalized)
3330 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3331 else if (desc->channel[first_non_void].pure_integer)
3332 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3333 else
3334 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3335 }
3336 }
3337 }
3338
3339 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3340 if (data_format == ~0) {
3341 data_format = 0;
3342 }
3343
3344 /* S8 with Z32 HTILE needs a special format. */
3345 if (screen->b.chip_class >= GFX9 &&
3346 pipe_format == PIPE_FORMAT_S8_UINT &&
3347 tex->tc_compatible_htile)
3348 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3349
3350 if (!sampler &&
3351 (res->target == PIPE_TEXTURE_CUBE ||
3352 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3353 (screen->b.chip_class <= VI &&
3354 res->target == PIPE_TEXTURE_3D))) {
3355 /* For the purpose of shader images, treat cube maps and 3D
3356 * textures as 2D arrays. For 3D textures, the address
3357 * calculations for mipmaps are different, so we rely on the
3358 * caller to effectively disable mipmaps.
3359 */
3360 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3361
3362 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3363 } else {
3364 type = si_tex_dim(screen, tex, target, res->nr_samples);
3365 }
3366
3367 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3368 height = 1;
3369 depth = res->array_size;
3370 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3371 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3372 if (sampler || res->target != PIPE_TEXTURE_3D)
3373 depth = res->array_size;
3374 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3375 depth = res->array_size / 6;
3376
3377 state[0] = 0;
3378 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3379 S_008F14_NUM_FORMAT_GFX6(num_format));
3380 state[2] = (S_008F18_WIDTH(width - 1) |
3381 S_008F18_HEIGHT(height - 1) |
3382 S_008F18_PERF_MOD(4));
3383 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3384 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3385 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3386 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3387 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3388 0 : first_level) |
3389 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3390 util_logbase2(res->nr_samples) :
3391 last_level) |
3392 S_008F1C_TYPE(type));
3393 state[4] = 0;
3394 state[5] = S_008F24_BASE_ARRAY(first_layer);
3395 state[6] = 0;
3396 state[7] = 0;
3397
3398 if (screen->b.chip_class >= GFX9) {
3399 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3400
3401 /* Depth is the the last accessible layer on Gfx9.
3402 * The hw doesn't need to know the total number of layers.
3403 */
3404 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3405 state[4] |= S_008F20_DEPTH(depth - 1);
3406 else
3407 state[4] |= S_008F20_DEPTH(last_layer);
3408
3409 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3410 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3411 util_logbase2(res->nr_samples) :
3412 tex->resource.b.b.last_level);
3413 } else {
3414 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3415 state[4] |= S_008F20_DEPTH(depth - 1);
3416 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3417 }
3418
3419 if (tex->dcc_offset) {
3420 unsigned swap = r600_translate_colorswap(pipe_format, false);
3421
3422 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3423 } else {
3424 /* The last dword is unused by hw. The shader uses it to clear
3425 * bits in the first dword of sampler state.
3426 */
3427 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3428 if (first_level == last_level)
3429 state[7] = C_008F30_MAX_ANISO_RATIO;
3430 else
3431 state[7] = 0xffffffff;
3432 }
3433 }
3434
3435 /* Initialize the sampler view for FMASK. */
3436 if (tex->fmask.size) {
3437 uint32_t data_format, num_format;
3438
3439 va = tex->resource.gpu_address + tex->fmask.offset;
3440
3441 if (screen->b.chip_class >= GFX9) {
3442 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3443 switch (res->nr_samples) {
3444 case 2:
3445 num_format = V_008F14_IMG_FMASK_8_2_2;
3446 break;
3447 case 4:
3448 num_format = V_008F14_IMG_FMASK_8_4_4;
3449 break;
3450 case 8:
3451 num_format = V_008F14_IMG_FMASK_32_8_8;
3452 break;
3453 default:
3454 unreachable("invalid nr_samples");
3455 }
3456 } else {
3457 switch (res->nr_samples) {
3458 case 2:
3459 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3460 break;
3461 case 4:
3462 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3463 break;
3464 case 8:
3465 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3466 break;
3467 default:
3468 unreachable("invalid nr_samples");
3469 }
3470 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3471 }
3472
3473 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3474 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3475 S_008F14_DATA_FORMAT_GFX6(data_format) |
3476 S_008F14_NUM_FORMAT_GFX6(num_format);
3477 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3478 S_008F18_HEIGHT(height - 1);
3479 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3480 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3481 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3482 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3483 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3484 fmask_state[4] = 0;
3485 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3486 fmask_state[6] = 0;
3487 fmask_state[7] = 0;
3488
3489 if (screen->b.chip_class >= GFX9) {
3490 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3491 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3492 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3493 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3494 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3495 } else {
3496 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3497 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3498 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3499 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3500 }
3501 }
3502 }
3503
3504 /**
3505 * Create a sampler view.
3506 *
3507 * @param ctx context
3508 * @param texture texture
3509 * @param state sampler view template
3510 * @param width0 width0 override (for compressed textures as int)
3511 * @param height0 height0 override (for compressed textures as int)
3512 * @param force_level set the base address to the level (for compressed textures)
3513 */
3514 struct pipe_sampler_view *
3515 si_create_sampler_view_custom(struct pipe_context *ctx,
3516 struct pipe_resource *texture,
3517 const struct pipe_sampler_view *state,
3518 unsigned width0, unsigned height0,
3519 unsigned force_level)
3520 {
3521 struct si_context *sctx = (struct si_context*)ctx;
3522 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3523 struct r600_texture *tmp = (struct r600_texture*)texture;
3524 unsigned base_level, first_level, last_level;
3525 unsigned char state_swizzle[4];
3526 unsigned height, depth, width;
3527 unsigned last_layer = state->u.tex.last_layer;
3528 enum pipe_format pipe_format;
3529 const struct legacy_surf_level *surflevel;
3530
3531 if (!view)
3532 return NULL;
3533
3534 /* initialize base object */
3535 view->base = *state;
3536 view->base.texture = NULL;
3537 view->base.reference.count = 1;
3538 view->base.context = ctx;
3539
3540 assert(texture);
3541 pipe_resource_reference(&view->base.texture, texture);
3542
3543 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3544 state->format == PIPE_FORMAT_S8X24_UINT ||
3545 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3546 state->format == PIPE_FORMAT_S8_UINT)
3547 view->is_stencil_sampler = true;
3548
3549 /* Buffer resource. */
3550 if (texture->target == PIPE_BUFFER) {
3551 si_make_buffer_descriptor(sctx->screen,
3552 (struct r600_resource *)texture,
3553 state->format,
3554 state->u.buf.offset,
3555 state->u.buf.size,
3556 view->state);
3557 return &view->base;
3558 }
3559
3560 state_swizzle[0] = state->swizzle_r;
3561 state_swizzle[1] = state->swizzle_g;
3562 state_swizzle[2] = state->swizzle_b;
3563 state_swizzle[3] = state->swizzle_a;
3564
3565 base_level = 0;
3566 first_level = state->u.tex.first_level;
3567 last_level = state->u.tex.last_level;
3568 width = width0;
3569 height = height0;
3570 depth = texture->depth0;
3571
3572 if (sctx->b.chip_class <= VI && force_level) {
3573 assert(force_level == first_level &&
3574 force_level == last_level);
3575 base_level = force_level;
3576 first_level = 0;
3577 last_level = 0;
3578 width = u_minify(width, force_level);
3579 height = u_minify(height, force_level);
3580 depth = u_minify(depth, force_level);
3581 }
3582
3583 /* This is not needed if state trackers set last_layer correctly. */
3584 if (state->target == PIPE_TEXTURE_1D ||
3585 state->target == PIPE_TEXTURE_2D ||
3586 state->target == PIPE_TEXTURE_RECT ||
3587 state->target == PIPE_TEXTURE_CUBE)
3588 last_layer = state->u.tex.first_layer;
3589
3590 /* Texturing with separate depth and stencil. */
3591 pipe_format = state->format;
3592
3593 /* Depth/stencil texturing sometimes needs separate texture. */
3594 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3595 if (!tmp->flushed_depth_texture &&
3596 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3597 pipe_resource_reference(&view->base.texture, NULL);
3598 FREE(view);
3599 return NULL;
3600 }
3601
3602 assert(tmp->flushed_depth_texture);
3603
3604 /* Override format for the case where the flushed texture
3605 * contains only Z or only S.
3606 */
3607 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3608 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3609
3610 tmp = tmp->flushed_depth_texture;
3611 }
3612
3613 surflevel = tmp->surface.u.legacy.level;
3614
3615 if (tmp->db_compatible) {
3616 if (!view->is_stencil_sampler)
3617 pipe_format = tmp->db_render_format;
3618
3619 switch (pipe_format) {
3620 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3621 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3622 break;
3623 case PIPE_FORMAT_X8Z24_UNORM:
3624 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3625 /* Z24 is always stored like this for DB
3626 * compatibility.
3627 */
3628 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3629 break;
3630 case PIPE_FORMAT_X24S8_UINT:
3631 case PIPE_FORMAT_S8X24_UINT:
3632 case PIPE_FORMAT_X32_S8X24_UINT:
3633 pipe_format = PIPE_FORMAT_S8_UINT;
3634 surflevel = tmp->surface.u.legacy.stencil_level;
3635 break;
3636 default:;
3637 }
3638 }
3639
3640 view->dcc_incompatible =
3641 vi_dcc_formats_are_incompatible(texture,
3642 state->u.tex.first_level,
3643 state->format);
3644
3645 si_make_texture_descriptor(sctx->screen, tmp, true,
3646 state->target, pipe_format, state_swizzle,
3647 first_level, last_level,
3648 state->u.tex.first_layer, last_layer,
3649 width, height, depth,
3650 view->state, view->fmask_state);
3651
3652 view->base_level_info = &surflevel[base_level];
3653 view->base_level = base_level;
3654 view->block_width = util_format_get_blockwidth(pipe_format);
3655 return &view->base;
3656 }
3657
3658 static struct pipe_sampler_view *
3659 si_create_sampler_view(struct pipe_context *ctx,
3660 struct pipe_resource *texture,
3661 const struct pipe_sampler_view *state)
3662 {
3663 return si_create_sampler_view_custom(ctx, texture, state,
3664 texture ? texture->width0 : 0,
3665 texture ? texture->height0 : 0, 0);
3666 }
3667
3668 static void si_sampler_view_destroy(struct pipe_context *ctx,
3669 struct pipe_sampler_view *state)
3670 {
3671 struct si_sampler_view *view = (struct si_sampler_view *)state;
3672
3673 pipe_resource_reference(&state->texture, NULL);
3674 FREE(view);
3675 }
3676
3677 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3678 {
3679 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3680 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3681 (linear_filter &&
3682 (wrap == PIPE_TEX_WRAP_CLAMP ||
3683 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3684 }
3685
3686 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3687 {
3688 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3689 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3690
3691 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3692 state->border_color.ui[2] || state->border_color.ui[3]) &&
3693 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3694 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3695 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3696 }
3697
3698 static void *si_create_sampler_state(struct pipe_context *ctx,
3699 const struct pipe_sampler_state *state)
3700 {
3701 struct si_context *sctx = (struct si_context *)ctx;
3702 struct r600_common_screen *rscreen = sctx->b.screen;
3703 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3704 unsigned border_color_type, border_color_index = 0;
3705 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3706 : state->max_anisotropy;
3707 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3708
3709 if (!rstate) {
3710 return NULL;
3711 }
3712
3713 if (!sampler_state_needs_border_color(state))
3714 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3715 else if (state->border_color.f[0] == 0 &&
3716 state->border_color.f[1] == 0 &&
3717 state->border_color.f[2] == 0 &&
3718 state->border_color.f[3] == 0)
3719 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3720 else if (state->border_color.f[0] == 0 &&
3721 state->border_color.f[1] == 0 &&
3722 state->border_color.f[2] == 0 &&
3723 state->border_color.f[3] == 1)
3724 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3725 else if (state->border_color.f[0] == 1 &&
3726 state->border_color.f[1] == 1 &&
3727 state->border_color.f[2] == 1 &&
3728 state->border_color.f[3] == 1)
3729 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3730 else {
3731 int i;
3732
3733 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3734
3735 /* Check if the border has been uploaded already. */
3736 for (i = 0; i < sctx->border_color_count; i++)
3737 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3738 sizeof(state->border_color)) == 0)
3739 break;
3740
3741 if (i >= SI_MAX_BORDER_COLORS) {
3742 /* Getting 4096 unique border colors is very unlikely. */
3743 fprintf(stderr, "radeonsi: The border color table is full. "
3744 "Any new border colors will be just black. "
3745 "Please file a bug.\n");
3746 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3747 } else {
3748 if (i == sctx->border_color_count) {
3749 /* Upload a new border color. */
3750 memcpy(&sctx->border_color_table[i], &state->border_color,
3751 sizeof(state->border_color));
3752 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3753 &state->border_color,
3754 sizeof(state->border_color));
3755 sctx->border_color_count++;
3756 }
3757
3758 border_color_index = i;
3759 }
3760 }
3761
3762 #ifdef DEBUG
3763 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3764 #endif
3765 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3766 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3767 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3768 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3769 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3770 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3771 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3772 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3773 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3774 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3775 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3776 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3777 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3778 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3779 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3780 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3781 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3782 S_008F38_MIP_POINT_PRECLAMP(1) |
3783 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3784 S_008F38_FILTER_PREC_FIX(1) |
3785 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3786 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3787 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3788 return rstate;
3789 }
3790
3791 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3792 {
3793 struct si_context *sctx = (struct si_context *)ctx;
3794
3795 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3796 return;
3797
3798 sctx->sample_mask.sample_mask = sample_mask;
3799 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3800 }
3801
3802 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3803 {
3804 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3805 unsigned mask = sctx->sample_mask.sample_mask;
3806
3807 /* Needed for line and polygon smoothing as well as for the Polaris
3808 * small primitive filter. We expect the state tracker to take care of
3809 * this for us.
3810 */
3811 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3812 (mask & 1 && sctx->blitter->running));
3813
3814 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3815 radeon_emit(cs, mask | (mask << 16));
3816 radeon_emit(cs, mask | (mask << 16));
3817 }
3818
3819 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3820 {
3821 #ifdef DEBUG
3822 struct si_sampler_state *s = state;
3823
3824 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3825 s->magic = 0;
3826 #endif
3827 free(state);
3828 }
3829
3830 /*
3831 * Vertex elements & buffers
3832 */
3833
3834 static void *si_create_vertex_elements(struct pipe_context *ctx,
3835 unsigned count,
3836 const struct pipe_vertex_element *elements)
3837 {
3838 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3839 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
3840 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3841 int i;
3842
3843 assert(count <= SI_MAX_ATTRIBS);
3844 if (!v)
3845 return NULL;
3846
3847 v->count = count;
3848 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3849
3850 for (i = 0; i < count; ++i) {
3851 const struct util_format_description *desc;
3852 const struct util_format_channel_description *channel;
3853 unsigned data_format, num_format;
3854 int first_non_void;
3855 unsigned vbo_index = elements[i].vertex_buffer_index;
3856 unsigned char swizzle[4];
3857
3858 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3859 FREE(v);
3860 return NULL;
3861 }
3862
3863 if (elements[i].instance_divisor) {
3864 v->uses_instance_divisors = true;
3865 v->instance_divisors[i] = elements[i].instance_divisor;
3866
3867 if (v->instance_divisors[i] == 1)
3868 v->instance_divisor_is_one |= 1u << i;
3869 else
3870 v->instance_divisor_is_fetched |= 1u << i;
3871 }
3872
3873 if (!used[vbo_index]) {
3874 v->first_vb_use_mask |= 1 << i;
3875 used[vbo_index] = true;
3876 }
3877
3878 desc = util_format_description(elements[i].src_format);
3879 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3880 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3881 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3882 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3883 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3884
3885 v->format_size[i] = desc->block.bits / 8;
3886 v->src_offset[i] = elements[i].src_offset;
3887 v->vertex_buffer_index[i] = vbo_index;
3888
3889 /* The hardware always treats the 2-bit alpha channel as
3890 * unsigned, so a shader workaround is needed. The affected
3891 * chips are VI and older except Stoney (GFX8.1).
3892 */
3893 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3894 sscreen->b.chip_class <= VI &&
3895 sscreen->b.family != CHIP_STONEY) {
3896 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3897 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3898 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3899 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3900 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3901 /* This isn't actually used in OpenGL. */
3902 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3903 }
3904 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3905 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3906 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3907 else
3908 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3909 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3910 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3911 if (channel->normalized) {
3912 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3913 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3914 else
3915 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3916 } else {
3917 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3918 }
3919 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3920 if (channel->normalized) {
3921 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3922 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3923 else
3924 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3925 } else {
3926 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3927 }
3928 }
3929 } else if (channel && channel->size == 64 &&
3930 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3931 switch (desc->nr_channels) {
3932 case 1:
3933 case 2:
3934 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3935 swizzle[0] = PIPE_SWIZZLE_X;
3936 swizzle[1] = PIPE_SWIZZLE_Y;
3937 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3938 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3939 break;
3940 case 3:
3941 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3942 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3943 swizzle[1] = PIPE_SWIZZLE_Y;
3944 swizzle[2] = PIPE_SWIZZLE_0;
3945 swizzle[3] = PIPE_SWIZZLE_0;
3946 break;
3947 case 4:
3948 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3949 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3950 swizzle[1] = PIPE_SWIZZLE_Y;
3951 swizzle[2] = PIPE_SWIZZLE_Z;
3952 swizzle[3] = PIPE_SWIZZLE_W;
3953 break;
3954 default:
3955 assert(0);
3956 }
3957 } else if (channel && desc->nr_channels == 3) {
3958 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3959
3960 if (channel->size == 8) {
3961 if (channel->pure_integer)
3962 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3963 else
3964 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3965 } else if (channel->size == 16) {
3966 if (channel->pure_integer)
3967 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3968 else
3969 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3970 }
3971 }
3972
3973 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3974 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3975 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3976 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3977 S_008F0C_NUM_FORMAT(num_format) |
3978 S_008F0C_DATA_FORMAT(data_format);
3979 }
3980 return v;
3981 }
3982
3983 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3984 {
3985 struct si_context *sctx = (struct si_context *)ctx;
3986 struct si_vertex_elements *old = sctx->vertex_elements;
3987 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
3988
3989 sctx->vertex_elements = v;
3990 sctx->vertex_buffers_dirty = true;
3991
3992 if (v &&
3993 (!old ||
3994 old->count != v->count ||
3995 old->uses_instance_divisors != v->uses_instance_divisors ||
3996 v->uses_instance_divisors || /* we don't check which divisors changed */
3997 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
3998 sctx->do_update_shaders = true;
3999
4000 if (v && v->instance_divisor_is_fetched) {
4001 struct pipe_constant_buffer cb;
4002
4003 cb.buffer = NULL;
4004 cb.user_buffer = v->instance_divisors;
4005 cb.buffer_offset = 0;
4006 cb.buffer_size = sizeof(uint32_t) * v->count;
4007 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4008 }
4009 }
4010
4011 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4012 {
4013 struct si_context *sctx = (struct si_context *)ctx;
4014
4015 if (sctx->vertex_elements == state)
4016 sctx->vertex_elements = NULL;
4017 FREE(state);
4018 }
4019
4020 static void si_set_vertex_buffers(struct pipe_context *ctx,
4021 unsigned start_slot, unsigned count,
4022 const struct pipe_vertex_buffer *buffers)
4023 {
4024 struct si_context *sctx = (struct si_context *)ctx;
4025 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4026 int i;
4027
4028 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4029
4030 if (buffers) {
4031 for (i = 0; i < count; i++) {
4032 const struct pipe_vertex_buffer *src = buffers + i;
4033 struct pipe_vertex_buffer *dsti = dst + i;
4034 struct pipe_resource *buf = src->buffer.resource;
4035
4036 pipe_resource_reference(&dsti->buffer.resource, buf);
4037 dsti->buffer_offset = src->buffer_offset;
4038 dsti->stride = src->stride;
4039 r600_context_add_resource_size(ctx, buf);
4040 if (buf)
4041 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4042 }
4043 } else {
4044 for (i = 0; i < count; i++) {
4045 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4046 }
4047 }
4048 sctx->vertex_buffers_dirty = true;
4049 }
4050
4051 /*
4052 * Misc
4053 */
4054
4055 static void si_set_tess_state(struct pipe_context *ctx,
4056 const float default_outer_level[4],
4057 const float default_inner_level[2])
4058 {
4059 struct si_context *sctx = (struct si_context *)ctx;
4060 struct pipe_constant_buffer cb;
4061 float array[8];
4062
4063 memcpy(array, default_outer_level, sizeof(float) * 4);
4064 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4065
4066 cb.buffer = NULL;
4067 cb.user_buffer = NULL;
4068 cb.buffer_size = sizeof(array);
4069
4070 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4071 (void*)array, sizeof(array),
4072 &cb.buffer_offset);
4073
4074 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4075 pipe_resource_reference(&cb.buffer, NULL);
4076 }
4077
4078 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4079 {
4080 struct si_context *sctx = (struct si_context *)ctx;
4081
4082 si_update_fb_dirtiness_after_rendering(sctx);
4083
4084 /* Multisample surfaces are flushed in si_decompress_textures. */
4085 if (sctx->framebuffer.nr_samples <= 1 &&
4086 sctx->framebuffer.state.nr_cbufs)
4087 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4088 sctx->framebuffer.CB_has_shader_readable_metadata);
4089 }
4090
4091 /* This only ensures coherency for shader image/buffer stores. */
4092 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4093 {
4094 struct si_context *sctx = (struct si_context *)ctx;
4095
4096 /* Subsequent commands must wait for all shader invocations to
4097 * complete. */
4098 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4099 SI_CONTEXT_CS_PARTIAL_FLUSH;
4100
4101 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4102 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4103 SI_CONTEXT_INV_VMEM_L1;
4104
4105 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4106 PIPE_BARRIER_SHADER_BUFFER |
4107 PIPE_BARRIER_TEXTURE |
4108 PIPE_BARRIER_IMAGE |
4109 PIPE_BARRIER_STREAMOUT_BUFFER |
4110 PIPE_BARRIER_GLOBAL_BUFFER)) {
4111 /* As far as I can tell, L1 contents are written back to L2
4112 * automatically at end of shader, but the contents of other
4113 * L1 caches might still be stale. */
4114 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4115 }
4116
4117 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4118 /* Indices are read through TC L2 since VI.
4119 * L1 isn't used.
4120 */
4121 if (sctx->screen->b.chip_class <= CIK)
4122 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4123 }
4124
4125 /* MSAA color, any depth and any stencil are flushed in
4126 * si_decompress_textures when needed.
4127 */
4128 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4129 sctx->framebuffer.nr_samples <= 1 &&
4130 sctx->framebuffer.state.nr_cbufs) {
4131 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4132
4133 if (sctx->b.chip_class <= VI)
4134 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4135 }
4136
4137 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4138 if (sctx->screen->b.chip_class <= VI &&
4139 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4140 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4141 }
4142
4143 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4144 {
4145 struct pipe_blend_state blend;
4146
4147 memset(&blend, 0, sizeof(blend));
4148 blend.independent_blend_enable = true;
4149 blend.rt[0].colormask = 0xf;
4150 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4151 }
4152
4153 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4154 bool include_draw_vbo)
4155 {
4156 si_need_cs_space((struct si_context*)ctx);
4157 }
4158
4159 static void si_init_config(struct si_context *sctx);
4160
4161 void si_init_state_functions(struct si_context *sctx)
4162 {
4163 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4164 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4165 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4166 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4167 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4168
4169 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4170 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4171 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4172 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4173 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4174 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4175 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4176 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4177 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4178 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4179 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4180
4181 sctx->b.b.create_blend_state = si_create_blend_state;
4182 sctx->b.b.bind_blend_state = si_bind_blend_state;
4183 sctx->b.b.delete_blend_state = si_delete_blend_state;
4184 sctx->b.b.set_blend_color = si_set_blend_color;
4185
4186 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4187 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4188 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4189
4190 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4191 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4192 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4193
4194 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4195 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4196 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4197 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4198 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4199
4200 sctx->b.b.set_clip_state = si_set_clip_state;
4201 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4202
4203 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4204 sctx->b.b.get_sample_position = cayman_get_sample_position;
4205
4206 sctx->b.b.create_sampler_state = si_create_sampler_state;
4207 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4208
4209 sctx->b.b.create_sampler_view = si_create_sampler_view;
4210 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4211
4212 sctx->b.b.set_sample_mask = si_set_sample_mask;
4213
4214 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4215 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4216 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4217 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4218
4219 sctx->b.b.texture_barrier = si_texture_barrier;
4220 sctx->b.b.memory_barrier = si_memory_barrier;
4221 sctx->b.b.set_min_samples = si_set_min_samples;
4222 sctx->b.b.set_tess_state = si_set_tess_state;
4223
4224 sctx->b.b.set_active_query_state = si_set_active_query_state;
4225 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4226 sctx->b.save_qbo_state = si_save_qbo_state;
4227 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4228
4229 sctx->b.b.draw_vbo = si_draw_vbo;
4230
4231 si_init_config(sctx);
4232 }
4233
4234 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4235 {
4236 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4237 }
4238
4239 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4240 struct r600_texture *rtex,
4241 struct radeon_bo_metadata *md)
4242 {
4243 struct si_screen *sscreen = (struct si_screen*)rscreen;
4244 struct pipe_resource *res = &rtex->resource.b.b;
4245 static const unsigned char swizzle[] = {
4246 PIPE_SWIZZLE_X,
4247 PIPE_SWIZZLE_Y,
4248 PIPE_SWIZZLE_Z,
4249 PIPE_SWIZZLE_W
4250 };
4251 uint32_t desc[8], i;
4252 bool is_array = util_resource_is_array_texture(res);
4253
4254 /* DRM 2.x.x doesn't support this. */
4255 if (rscreen->info.drm_major != 3)
4256 return;
4257
4258 assert(rtex->dcc_separate_buffer == NULL);
4259 assert(rtex->fmask.size == 0);
4260
4261 /* Metadata image format format version 1:
4262 * [0] = 1 (metadata format identifier)
4263 * [1] = (VENDOR_ID << 16) | PCI_ID
4264 * [2:9] = image descriptor for the whole resource
4265 * [2] is always 0, because the base address is cleared
4266 * [9] is the DCC offset bits [39:8] from the beginning of
4267 * the buffer
4268 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4269 */
4270
4271 md->metadata[0] = 1; /* metadata image format version 1 */
4272
4273 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4274 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4275
4276 si_make_texture_descriptor(sscreen, rtex, true,
4277 res->target, res->format,
4278 swizzle, 0, res->last_level, 0,
4279 is_array ? res->array_size - 1 : 0,
4280 res->width0, res->height0, res->depth0,
4281 desc, NULL);
4282
4283 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4284 0, 0, rtex->surface.blk_w, false, desc);
4285
4286 /* Clear the base address and set the relative DCC offset. */
4287 desc[0] = 0;
4288 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4289 desc[7] = rtex->dcc_offset >> 8;
4290
4291 /* Dwords [2:9] contain the image descriptor. */
4292 memcpy(&md->metadata[2], desc, sizeof(desc));
4293 md->size_metadata = 10 * 4;
4294
4295 /* Dwords [10:..] contain the mipmap level offsets. */
4296 if (rscreen->chip_class <= VI) {
4297 for (i = 0; i <= res->last_level; i++)
4298 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4299
4300 md->size_metadata += (1 + res->last_level) * 4;
4301 }
4302 }
4303
4304 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4305 struct r600_texture *rtex,
4306 struct radeon_bo_metadata *md)
4307 {
4308 uint32_t *desc = &md->metadata[2];
4309
4310 if (rscreen->chip_class < VI)
4311 return;
4312
4313 /* Return if DCC is enabled. The texture should be set up with it
4314 * already.
4315 */
4316 if (md->size_metadata >= 11 * 4 &&
4317 md->metadata[0] != 0 &&
4318 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4319 G_008F28_COMPRESSION_EN(desc[6])) {
4320 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4321 return;
4322 }
4323
4324 /* Disable DCC. These are always set by texture_from_handle and must
4325 * be cleared here.
4326 */
4327 rtex->dcc_offset = 0;
4328 }
4329
4330 void si_init_screen_state_functions(struct si_screen *sscreen)
4331 {
4332 sscreen->b.b.is_format_supported = si_is_format_supported;
4333 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4334 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4335 }
4336
4337 static void si_set_grbm_gfx_index(struct si_context *sctx,
4338 struct si_pm4_state *pm4, unsigned value)
4339 {
4340 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4341 GRBM_GFX_INDEX;
4342 si_pm4_set_reg(pm4, reg, value);
4343 }
4344
4345 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4346 struct si_pm4_state *pm4, unsigned se)
4347 {
4348 assert(se == ~0 || se < sctx->screen->b.info.max_se);
4349 si_set_grbm_gfx_index(sctx, pm4,
4350 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4351 S_030800_SE_INDEX(se)) |
4352 S_030800_SH_BROADCAST_WRITES(1) |
4353 S_030800_INSTANCE_BROADCAST_WRITES(1));
4354 }
4355
4356 static void
4357 si_write_harvested_raster_configs(struct si_context *sctx,
4358 struct si_pm4_state *pm4,
4359 unsigned raster_config,
4360 unsigned raster_config_1)
4361 {
4362 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4363 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4364 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4365 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4366 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4367 unsigned rb_per_se = num_rb / num_se;
4368 unsigned se_mask[4];
4369 unsigned se;
4370
4371 se_mask[0] = ((1 << rb_per_se) - 1);
4372 se_mask[1] = (se_mask[0] << rb_per_se);
4373 se_mask[2] = (se_mask[1] << rb_per_se);
4374 se_mask[3] = (se_mask[2] << rb_per_se);
4375
4376 se_mask[0] &= rb_mask;
4377 se_mask[1] &= rb_mask;
4378 se_mask[2] &= rb_mask;
4379 se_mask[3] &= rb_mask;
4380
4381 assert(num_se == 1 || num_se == 2 || num_se == 4);
4382 assert(sh_per_se == 1 || sh_per_se == 2);
4383 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4384
4385 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4386 * fields are for, so I'm leaving them as their default
4387 * values. */
4388
4389 for (se = 0; se < num_se; se++) {
4390 unsigned raster_config_se = raster_config;
4391 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4392 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4393 int idx = (se / 2) * 2;
4394
4395 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4396 raster_config_se &= C_028350_SE_MAP;
4397
4398 if (!se_mask[idx]) {
4399 raster_config_se |=
4400 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4401 } else {
4402 raster_config_se |=
4403 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4404 }
4405 }
4406
4407 pkr0_mask &= rb_mask;
4408 pkr1_mask &= rb_mask;
4409 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4410 raster_config_se &= C_028350_PKR_MAP;
4411
4412 if (!pkr0_mask) {
4413 raster_config_se |=
4414 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4415 } else {
4416 raster_config_se |=
4417 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4418 }
4419 }
4420
4421 if (rb_per_se >= 2) {
4422 unsigned rb0_mask = 1 << (se * rb_per_se);
4423 unsigned rb1_mask = rb0_mask << 1;
4424
4425 rb0_mask &= rb_mask;
4426 rb1_mask &= rb_mask;
4427 if (!rb0_mask || !rb1_mask) {
4428 raster_config_se &= C_028350_RB_MAP_PKR0;
4429
4430 if (!rb0_mask) {
4431 raster_config_se |=
4432 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4433 } else {
4434 raster_config_se |=
4435 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4436 }
4437 }
4438
4439 if (rb_per_se > 2) {
4440 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4441 rb1_mask = rb0_mask << 1;
4442 rb0_mask &= rb_mask;
4443 rb1_mask &= rb_mask;
4444 if (!rb0_mask || !rb1_mask) {
4445 raster_config_se &= C_028350_RB_MAP_PKR1;
4446
4447 if (!rb0_mask) {
4448 raster_config_se |=
4449 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4450 } else {
4451 raster_config_se |=
4452 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4453 }
4454 }
4455 }
4456 }
4457
4458 si_set_grbm_gfx_index_se(sctx, pm4, se);
4459 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4460 }
4461 si_set_grbm_gfx_index(sctx, pm4, ~0);
4462
4463 if (sctx->b.chip_class >= CIK) {
4464 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4465 (!se_mask[2] && !se_mask[3]))) {
4466 raster_config_1 &= C_028354_SE_PAIR_MAP;
4467
4468 if (!se_mask[0] && !se_mask[1]) {
4469 raster_config_1 |=
4470 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4471 } else {
4472 raster_config_1 |=
4473 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4474 }
4475 }
4476
4477 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4478 }
4479 }
4480
4481 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4482 {
4483 struct si_screen *sscreen = sctx->screen;
4484 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4485 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4486 unsigned raster_config, raster_config_1;
4487
4488 switch (sctx->b.family) {
4489 case CHIP_TAHITI:
4490 case CHIP_PITCAIRN:
4491 raster_config = 0x2a00126a;
4492 raster_config_1 = 0x00000000;
4493 break;
4494 case CHIP_VERDE:
4495 raster_config = 0x0000124a;
4496 raster_config_1 = 0x00000000;
4497 break;
4498 case CHIP_OLAND:
4499 raster_config = 0x00000082;
4500 raster_config_1 = 0x00000000;
4501 break;
4502 case CHIP_HAINAN:
4503 raster_config = 0x00000000;
4504 raster_config_1 = 0x00000000;
4505 break;
4506 case CHIP_BONAIRE:
4507 raster_config = 0x16000012;
4508 raster_config_1 = 0x00000000;
4509 break;
4510 case CHIP_HAWAII:
4511 raster_config = 0x3a00161a;
4512 raster_config_1 = 0x0000002e;
4513 break;
4514 case CHIP_FIJI:
4515 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4516 /* old kernels with old tiling config */
4517 raster_config = 0x16000012;
4518 raster_config_1 = 0x0000002a;
4519 } else {
4520 raster_config = 0x3a00161a;
4521 raster_config_1 = 0x0000002e;
4522 }
4523 break;
4524 case CHIP_POLARIS10:
4525 raster_config = 0x16000012;
4526 raster_config_1 = 0x0000002a;
4527 break;
4528 case CHIP_POLARIS11:
4529 case CHIP_POLARIS12:
4530 raster_config = 0x16000012;
4531 raster_config_1 = 0x00000000;
4532 break;
4533 case CHIP_TONGA:
4534 raster_config = 0x16000012;
4535 raster_config_1 = 0x0000002a;
4536 break;
4537 case CHIP_ICELAND:
4538 if (num_rb == 1)
4539 raster_config = 0x00000000;
4540 else
4541 raster_config = 0x00000002;
4542 raster_config_1 = 0x00000000;
4543 break;
4544 case CHIP_CARRIZO:
4545 raster_config = 0x00000002;
4546 raster_config_1 = 0x00000000;
4547 break;
4548 case CHIP_KAVERI:
4549 /* KV should be 0x00000002, but that causes problems with radeon */
4550 raster_config = 0x00000000; /* 0x00000002 */
4551 raster_config_1 = 0x00000000;
4552 break;
4553 case CHIP_KABINI:
4554 case CHIP_MULLINS:
4555 case CHIP_STONEY:
4556 raster_config = 0x00000000;
4557 raster_config_1 = 0x00000000;
4558 break;
4559 default:
4560 fprintf(stderr,
4561 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4562 raster_config = 0x00000000;
4563 raster_config_1 = 0x00000000;
4564 }
4565
4566 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4567 /* Always use the default config when all backends are enabled
4568 * (or when we failed to determine the enabled backends).
4569 */
4570 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4571 raster_config);
4572 if (sctx->b.chip_class >= CIK)
4573 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4574 raster_config_1);
4575 } else {
4576 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4577 }
4578 }
4579
4580 static void si_init_config(struct si_context *sctx)
4581 {
4582 struct si_screen *sscreen = sctx->screen;
4583 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4584 bool has_clear_state = sscreen->has_clear_state;
4585 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4586
4587 /* Only SI can disable CLEAR_STATE for now. */
4588 assert(has_clear_state || sscreen->b.chip_class == SI);
4589
4590 if (!pm4)
4591 return;
4592
4593 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4594 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4595 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4596 si_pm4_cmd_end(pm4, false);
4597
4598 if (has_clear_state) {
4599 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4600 si_pm4_cmd_add(pm4, 0);
4601 si_pm4_cmd_end(pm4, false);
4602 }
4603
4604 if (sctx->b.chip_class <= VI)
4605 si_set_raster_config(sctx, pm4);
4606
4607 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4608 if (!has_clear_state)
4609 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4610
4611 /* FIXME calculate these values somehow ??? */
4612 if (sctx->b.chip_class <= VI) {
4613 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4614 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4615 }
4616
4617 if (!has_clear_state) {
4618 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4619 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4620 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4621 }
4622
4623 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4624 if (!has_clear_state)
4625 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4626 if (sctx->b.chip_class < CIK)
4627 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4628 S_008A14_CLIP_VTX_REORDER_ENA(1));
4629
4630 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4631 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4632
4633 if (!has_clear_state)
4634 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4635
4636 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4637 * I don't know why. Deduced by trial and error.
4638 */
4639 if (sctx->b.chip_class <= CIK) {
4640 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4641 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4642 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4643 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4644 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4645 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4646 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4647 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4648 }
4649
4650 if (!has_clear_state) {
4651 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4652 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4653 S_028230_ER_TRI(0xA) |
4654 S_028230_ER_POINT(0xA) |
4655 S_028230_ER_RECT(0xA) |
4656 /* Required by DX10_DIAMOND_TEST_ENA: */
4657 S_028230_ER_LINE_LR(0x1A) |
4658 S_028230_ER_LINE_RL(0x26) |
4659 S_028230_ER_LINE_TB(0xA) |
4660 S_028230_ER_LINE_BT(0xA));
4661 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4662 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4663 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4664 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4665 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4666 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4667 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4668 }
4669
4670 if (sctx->b.chip_class >= GFX9) {
4671 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4672 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4673 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4674 } else {
4675 /* These registers, when written, also overwrite the CLEAR_STATE
4676 * context, so we can't rely on CLEAR_STATE setting them.
4677 * It would be an issue if there was another UMD changing them.
4678 */
4679 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4680 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4681 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4682 }
4683
4684 if (sctx->b.chip_class >= CIK) {
4685 if (sctx->b.chip_class >= GFX9) {
4686 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4687 } else {
4688 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4689 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4690 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4691
4692 /* If this is 0, Bonaire can hang even if GS isn't being used.
4693 * Other chips are unaffected. These are suboptimal values,
4694 * but we don't use on-chip GS.
4695 */
4696 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4697 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4698 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4699 }
4700 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4701
4702 /* Compute LATE_ALLOC_VS.LIMIT. */
4703 unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
4704 (sscreen->b.info.max_se *
4705 sscreen->b.info.max_sh_per_se);
4706 unsigned late_alloc_limit; /* The limit is per SH. */
4707
4708 if (sctx->b.family == CHIP_KABINI) {
4709 late_alloc_limit = 0; /* Potential hang on Kabini. */
4710 } else if (num_cu_per_sh <= 4) {
4711 /* Too few available compute units per SH. Disallowing
4712 * VS to run on one CU could hurt us more than late VS
4713 * allocation would help.
4714 *
4715 * 2 is the highest safe number that allows us to keep
4716 * all CUs enabled.
4717 */
4718 late_alloc_limit = 2;
4719 } else {
4720 /* This is a good initial value, allowing 1 late_alloc
4721 * wave per SIMD on num_cu - 2.
4722 */
4723 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4724
4725 /* The limit is 0-based, so 0 means 1. */
4726 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4727 late_alloc_limit -= 1;
4728 }
4729
4730 /* VS can't execute on one CU if the limit is > 2. */
4731 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4732 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff));
4733 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4734 S_00B11C_LIMIT(late_alloc_limit));
4735 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4736 }
4737
4738 if (sctx->b.chip_class >= VI) {
4739 unsigned vgt_tess_distribution;
4740
4741 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4742 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4743 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4744
4745 vgt_tess_distribution =
4746 S_028B50_ACCUM_ISOLINE(32) |
4747 S_028B50_ACCUM_TRI(11) |
4748 S_028B50_ACCUM_QUAD(11) |
4749 S_028B50_DONUT_SPLIT(16);
4750
4751 /* Testing with Unigine Heaven extreme tesselation yielded best results
4752 * with TRAP_SPLIT = 3.
4753 */
4754 if (sctx->b.family == CHIP_FIJI ||
4755 sctx->b.family >= CHIP_POLARIS10)
4756 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4757
4758 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4759 } else if (!has_clear_state) {
4760 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4761 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4762 }
4763
4764 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4765 if (sctx->b.chip_class >= CIK)
4766 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4767 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4768 RADEON_PRIO_BORDER_COLORS);
4769
4770 if (sctx->b.chip_class >= GFX9) {
4771 unsigned num_se = sscreen->b.info.max_se;
4772 unsigned pc_lines = 0;
4773
4774 switch (sctx->b.family) {
4775 case CHIP_VEGA10:
4776 pc_lines = 4096;
4777 break;
4778 case CHIP_RAVEN:
4779 pc_lines = 1024;
4780 break;
4781 default:
4782 assert(0);
4783 }
4784
4785 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4786 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4787 S_028C48_MAX_PRIM_PER_BATCH(1023));
4788 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4789 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4790 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4791 }
4792
4793 si_pm4_upload_indirect_buffer(sctx, pm4);
4794 sctx->init_config = pm4;
4795 }