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android: radeonsi: add support for sid_tables.h generated sources
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend->dual_src_blend &&
269 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
270 mask = 0;
271
272 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
273 }
274
275 /*
276 * Blender functions
277 */
278
279 static uint32_t si_translate_blend_function(int blend_func)
280 {
281 switch (blend_func) {
282 case PIPE_BLEND_ADD:
283 return V_028780_COMB_DST_PLUS_SRC;
284 case PIPE_BLEND_SUBTRACT:
285 return V_028780_COMB_SRC_MINUS_DST;
286 case PIPE_BLEND_REVERSE_SUBTRACT:
287 return V_028780_COMB_DST_MINUS_SRC;
288 case PIPE_BLEND_MIN:
289 return V_028780_COMB_MIN_DST_SRC;
290 case PIPE_BLEND_MAX:
291 return V_028780_COMB_MAX_DST_SRC;
292 default:
293 R600_ERR("Unknown blend function %d\n", blend_func);
294 assert(0);
295 break;
296 }
297 return 0;
298 }
299
300 static uint32_t si_translate_blend_factor(int blend_fact)
301 {
302 switch (blend_fact) {
303 case PIPE_BLENDFACTOR_ONE:
304 return V_028780_BLEND_ONE;
305 case PIPE_BLENDFACTOR_SRC_COLOR:
306 return V_028780_BLEND_SRC_COLOR;
307 case PIPE_BLENDFACTOR_SRC_ALPHA:
308 return V_028780_BLEND_SRC_ALPHA;
309 case PIPE_BLENDFACTOR_DST_ALPHA:
310 return V_028780_BLEND_DST_ALPHA;
311 case PIPE_BLENDFACTOR_DST_COLOR:
312 return V_028780_BLEND_DST_COLOR;
313 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
314 return V_028780_BLEND_SRC_ALPHA_SATURATE;
315 case PIPE_BLENDFACTOR_CONST_COLOR:
316 return V_028780_BLEND_CONSTANT_COLOR;
317 case PIPE_BLENDFACTOR_CONST_ALPHA:
318 return V_028780_BLEND_CONSTANT_ALPHA;
319 case PIPE_BLENDFACTOR_ZERO:
320 return V_028780_BLEND_ZERO;
321 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
322 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
323 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
324 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
325 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
326 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
327 case PIPE_BLENDFACTOR_INV_DST_COLOR:
328 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
329 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
331 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
333 case PIPE_BLENDFACTOR_SRC1_COLOR:
334 return V_028780_BLEND_SRC1_COLOR;
335 case PIPE_BLENDFACTOR_SRC1_ALPHA:
336 return V_028780_BLEND_SRC1_ALPHA;
337 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
338 return V_028780_BLEND_INV_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
340 return V_028780_BLEND_INV_SRC1_ALPHA;
341 default:
342 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
343 assert(0);
344 break;
345 }
346 return 0;
347 }
348
349 static void *si_create_blend_state_mode(struct pipe_context *ctx,
350 const struct pipe_blend_state *state,
351 unsigned mode)
352 {
353 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
354 struct si_pm4_state *pm4 = &blend->pm4;
355
356 uint32_t color_control = 0;
357
358 if (blend == NULL)
359 return NULL;
360
361 blend->alpha_to_one = state->alpha_to_one;
362 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
363
364 if (state->logicop_enable) {
365 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
366 } else {
367 color_control |= S_028808_ROP3(0xcc);
368 }
369
370 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
371 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
372 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
373 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
374 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
375 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
376
377 blend->cb_target_mask = 0;
378 for (int i = 0; i < 8; i++) {
379 /* state->rt entries > 0 only written if independent blending */
380 const int j = state->independent_blend_enable ? i : 0;
381
382 unsigned eqRGB = state->rt[j].rgb_func;
383 unsigned srcRGB = state->rt[j].rgb_src_factor;
384 unsigned dstRGB = state->rt[j].rgb_dst_factor;
385 unsigned eqA = state->rt[j].alpha_func;
386 unsigned srcA = state->rt[j].alpha_src_factor;
387 unsigned dstA = state->rt[j].alpha_dst_factor;
388
389 unsigned blend_cntl = 0;
390
391 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
392 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
393
394 if (!state->rt[j].blend_enable) {
395 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
396 continue;
397 }
398
399 blend_cntl |= S_028780_ENABLE(1);
400 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
401 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
402 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
403
404 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
405 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
406 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
407 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
408 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
409 }
410 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
411 }
412
413 if (blend->cb_target_mask) {
414 color_control |= S_028808_MODE(mode);
415 } else {
416 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
417 }
418 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
419
420 return blend;
421 }
422
423 static void *si_create_blend_state(struct pipe_context *ctx,
424 const struct pipe_blend_state *state)
425 {
426 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
427 }
428
429 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
430 {
431 struct si_context *sctx = (struct si_context *)ctx;
432 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
433 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
434 }
435
436 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
437 {
438 struct si_context *sctx = (struct si_context *)ctx;
439 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
440 }
441
442 static void si_set_blend_color(struct pipe_context *ctx,
443 const struct pipe_blend_color *state)
444 {
445 struct si_context *sctx = (struct si_context *)ctx;
446
447 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
448 return;
449
450 sctx->blend_color.state = *state;
451 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
452 }
453
454 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
455 {
456 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
457
458 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
459 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
460 }
461
462 /*
463 * Clipping, scissors and viewport
464 */
465
466 static void si_set_clip_state(struct pipe_context *ctx,
467 const struct pipe_clip_state *state)
468 {
469 struct si_context *sctx = (struct si_context *)ctx;
470 struct pipe_constant_buffer cb;
471
472 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
473 return;
474
475 sctx->clip_state.state = *state;
476 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
477
478 cb.buffer = NULL;
479 cb.user_buffer = state->ucp;
480 cb.buffer_offset = 0;
481 cb.buffer_size = 4*4*8;
482 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
483 pipe_resource_reference(&cb.buffer, NULL);
484 }
485
486 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
487 {
488 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
489
490 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
491 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
492 }
493
494 #define SIX_BITS 0x3F
495
496 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
497 {
498 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
499 struct tgsi_shader_info *info = si_get_vs_info(sctx);
500 unsigned window_space =
501 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
502 unsigned clipdist_mask =
503 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
504
505 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
506 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
507 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
508 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
509 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
510 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
511 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
512 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
513 info->writes_edgeflag ||
514 info->writes_layer ||
515 info->writes_viewport_index) |
516 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
517 (sctx->queued.named.rasterizer->clip_plane_enable &
518 clipdist_mask));
519 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
520 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
521 (clipdist_mask ? 0 :
522 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
523 S_028810_CLIP_DISABLE(window_space));
524 }
525
526 static void si_set_scissor_states(struct pipe_context *ctx,
527 unsigned start_slot,
528 unsigned num_scissors,
529 const struct pipe_scissor_state *state)
530 {
531 struct si_context *sctx = (struct si_context *)ctx;
532 int i;
533
534 for (i = 0; i < num_scissors; i++)
535 sctx->scissors.states[start_slot + i] = state[i];
536
537 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
538 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
539 }
540
541 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
542 {
543 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
544 struct pipe_scissor_state *states = sctx->scissors.states;
545 unsigned mask = sctx->scissors.dirty_mask;
546
547 /* The simple case: Only 1 viewport is active. */
548 if (mask & 1 &&
549 !si_get_vs_info(sctx)->writes_viewport_index) {
550 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
551 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
552 S_028250_TL_Y(states[0].miny) |
553 S_028250_WINDOW_OFFSET_DISABLE(1));
554 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
555 S_028254_BR_Y(states[0].maxy));
556 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
557 return;
558 }
559
560 while (mask) {
561 int start, count, i;
562
563 u_bit_scan_consecutive_range(&mask, &start, &count);
564
565 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
566 start * 4 * 2, count * 2);
567 for (i = start; i < start+count; i++) {
568 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
569 S_028250_TL_Y(states[i].miny) |
570 S_028250_WINDOW_OFFSET_DISABLE(1));
571 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
572 S_028254_BR_Y(states[i].maxy));
573 }
574 }
575 sctx->scissors.dirty_mask = 0;
576 }
577
578 static void si_set_viewport_states(struct pipe_context *ctx,
579 unsigned start_slot,
580 unsigned num_viewports,
581 const struct pipe_viewport_state *state)
582 {
583 struct si_context *sctx = (struct si_context *)ctx;
584 int i;
585
586 for (i = 0; i < num_viewports; i++)
587 sctx->viewports.states[start_slot + i] = state[i];
588
589 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
590 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
591 }
592
593 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
594 {
595 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
596 struct pipe_viewport_state *states = sctx->viewports.states;
597 unsigned mask = sctx->viewports.dirty_mask;
598
599 /* The simple case: Only 1 viewport is active. */
600 if (mask & 1 &&
601 !si_get_vs_info(sctx)->writes_viewport_index) {
602 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
603 radeon_emit(cs, fui(states[0].scale[0]));
604 radeon_emit(cs, fui(states[0].translate[0]));
605 radeon_emit(cs, fui(states[0].scale[1]));
606 radeon_emit(cs, fui(states[0].translate[1]));
607 radeon_emit(cs, fui(states[0].scale[2]));
608 radeon_emit(cs, fui(states[0].translate[2]));
609 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
610 return;
611 }
612
613 while (mask) {
614 int start, count, i;
615
616 u_bit_scan_consecutive_range(&mask, &start, &count);
617
618 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
619 start * 4 * 6, count * 6);
620 for (i = start; i < start+count; i++) {
621 radeon_emit(cs, fui(states[i].scale[0]));
622 radeon_emit(cs, fui(states[i].translate[0]));
623 radeon_emit(cs, fui(states[i].scale[1]));
624 radeon_emit(cs, fui(states[i].translate[1]));
625 radeon_emit(cs, fui(states[i].scale[2]));
626 radeon_emit(cs, fui(states[i].translate[2]));
627 }
628 }
629 sctx->viewports.dirty_mask = 0;
630 }
631
632 /*
633 * inferred state between framebuffer and rasterizer
634 */
635 static void si_update_poly_offset_state(struct si_context *sctx)
636 {
637 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
638
639 if (!rs || !sctx->framebuffer.state.zsbuf)
640 return;
641
642 switch (sctx->framebuffer.state.zsbuf->texture->format) {
643 case PIPE_FORMAT_Z16_UNORM:
644 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
645 break;
646 default: /* 24-bit */
647 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
648 break;
649 case PIPE_FORMAT_Z32_FLOAT:
650 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
651 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
652 break;
653 }
654 }
655
656 /*
657 * Rasterizer
658 */
659
660 static uint32_t si_translate_fill(uint32_t func)
661 {
662 switch(func) {
663 case PIPE_POLYGON_MODE_FILL:
664 return V_028814_X_DRAW_TRIANGLES;
665 case PIPE_POLYGON_MODE_LINE:
666 return V_028814_X_DRAW_LINES;
667 case PIPE_POLYGON_MODE_POINT:
668 return V_028814_X_DRAW_POINTS;
669 default:
670 assert(0);
671 return V_028814_X_DRAW_POINTS;
672 }
673 }
674
675 static void *si_create_rs_state(struct pipe_context *ctx,
676 const struct pipe_rasterizer_state *state)
677 {
678 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
679 struct si_pm4_state *pm4 = &rs->pm4;
680 unsigned tmp, i;
681 float psize_min, psize_max;
682
683 if (rs == NULL) {
684 return NULL;
685 }
686
687 rs->two_side = state->light_twoside;
688 rs->multisample_enable = state->multisample;
689 rs->clip_plane_enable = state->clip_plane_enable;
690 rs->line_stipple_enable = state->line_stipple_enable;
691 rs->poly_stipple_enable = state->poly_stipple_enable;
692 rs->line_smooth = state->line_smooth;
693 rs->poly_smooth = state->poly_smooth;
694
695 rs->flatshade = state->flatshade;
696 rs->sprite_coord_enable = state->sprite_coord_enable;
697 rs->pa_sc_line_stipple = state->line_stipple_enable ?
698 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
699 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
700 rs->pa_cl_clip_cntl =
701 S_028810_PS_UCP_MODE(3) |
702 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
703 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
704 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
705 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
706 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
707
708 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
709 S_0286D4_FLAT_SHADE_ENA(1) |
710 S_0286D4_PNT_SPRITE_ENA(1) |
711 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
712 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
713 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
714 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
715 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
716
717 /* point size 12.4 fixed point */
718 tmp = (unsigned)(state->point_size * 8.0);
719 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
720
721 if (state->point_size_per_vertex) {
722 psize_min = util_get_min_point_size(state);
723 psize_max = 8192;
724 } else {
725 /* Force the point size to be as if the vertex output was disabled. */
726 psize_min = state->point_size;
727 psize_max = state->point_size;
728 }
729 /* Divide by two, because 0.5 = 1 pixel. */
730 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
731 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
732 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
733
734 tmp = (unsigned)state->line_width * 8;
735 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
736 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
737 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
738 S_028A48_MSAA_ENABLE(state->multisample ||
739 state->poly_smooth ||
740 state->line_smooth) |
741 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
742
743 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
744 S_028BE4_PIX_CENTER(state->half_pixel_center) |
745 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
746
747 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
748 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
749 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
750 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
751 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
752 S_028814_FACE(!state->front_ccw) |
753 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
754 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
755 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
756 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
757 state->fill_back != PIPE_POLYGON_MODE_FILL) |
758 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
759 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
760
761 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
762 for (i = 0; i < 3; i++) {
763 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
764 float offset_units = state->offset_units;
765 float offset_scale = state->offset_scale * 16.0f;
766
767 switch (i) {
768 case 0: /* 16-bit zbuffer */
769 offset_units *= 4.0f;
770 break;
771 case 1: /* 24-bit zbuffer */
772 offset_units *= 2.0f;
773 break;
774 case 2: /* 32-bit zbuffer */
775 offset_units *= 1.0f;
776 break;
777 }
778
779 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
780 fui(offset_scale));
781 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
782 fui(offset_units));
783 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
784 fui(offset_scale));
785 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
786 fui(offset_units));
787 }
788
789 return rs;
790 }
791
792 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
793 {
794 struct si_context *sctx = (struct si_context *)ctx;
795 struct si_state_rasterizer *old_rs =
796 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
797 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
798
799 if (state == NULL)
800 return;
801
802 if (sctx->framebuffer.nr_samples > 1 &&
803 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
804 si_mark_atom_dirty(sctx, &sctx->db_render_state);
805
806 si_pm4_bind_state(sctx, rasterizer, rs);
807 si_update_poly_offset_state(sctx);
808
809 si_mark_atom_dirty(sctx, &sctx->clip_regs);
810 }
811
812 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
813 {
814 struct si_context *sctx = (struct si_context *)ctx;
815
816 if (sctx->queued.named.rasterizer == state)
817 si_pm4_bind_state(sctx, poly_offset, NULL);
818 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
819 }
820
821 /*
822 * infeered state between dsa and stencil ref
823 */
824 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
825 {
826 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
827 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
828 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
829
830 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
831 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
832 S_028430_STENCILMASK(dsa->valuemask[0]) |
833 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
834 S_028430_STENCILOPVAL(1));
835 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
836 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
837 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
838 S_028434_STENCILOPVAL_BF(1));
839 }
840
841 static void si_set_stencil_ref(struct pipe_context *ctx,
842 const struct pipe_stencil_ref *state)
843 {
844 struct si_context *sctx = (struct si_context *)ctx;
845
846 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
847 return;
848
849 sctx->stencil_ref.state = *state;
850 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
851 }
852
853
854 /*
855 * DSA
856 */
857
858 static uint32_t si_translate_stencil_op(int s_op)
859 {
860 switch (s_op) {
861 case PIPE_STENCIL_OP_KEEP:
862 return V_02842C_STENCIL_KEEP;
863 case PIPE_STENCIL_OP_ZERO:
864 return V_02842C_STENCIL_ZERO;
865 case PIPE_STENCIL_OP_REPLACE:
866 return V_02842C_STENCIL_REPLACE_TEST;
867 case PIPE_STENCIL_OP_INCR:
868 return V_02842C_STENCIL_ADD_CLAMP;
869 case PIPE_STENCIL_OP_DECR:
870 return V_02842C_STENCIL_SUB_CLAMP;
871 case PIPE_STENCIL_OP_INCR_WRAP:
872 return V_02842C_STENCIL_ADD_WRAP;
873 case PIPE_STENCIL_OP_DECR_WRAP:
874 return V_02842C_STENCIL_SUB_WRAP;
875 case PIPE_STENCIL_OP_INVERT:
876 return V_02842C_STENCIL_INVERT;
877 default:
878 R600_ERR("Unknown stencil op %d", s_op);
879 assert(0);
880 break;
881 }
882 return 0;
883 }
884
885 static void *si_create_dsa_state(struct pipe_context *ctx,
886 const struct pipe_depth_stencil_alpha_state *state)
887 {
888 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
889 struct si_pm4_state *pm4 = &dsa->pm4;
890 unsigned db_depth_control;
891 uint32_t db_stencil_control = 0;
892
893 if (dsa == NULL) {
894 return NULL;
895 }
896
897 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
898 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
899 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
900 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
901
902 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
903 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
904 S_028800_ZFUNC(state->depth.func) |
905 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
906
907 /* stencil */
908 if (state->stencil[0].enabled) {
909 db_depth_control |= S_028800_STENCIL_ENABLE(1);
910 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
911 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
912 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
913 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
914
915 if (state->stencil[1].enabled) {
916 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
917 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
918 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
919 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
920 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
921 }
922 }
923
924 /* alpha */
925 if (state->alpha.enabled) {
926 dsa->alpha_func = state->alpha.func;
927
928 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
929 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
930 } else {
931 dsa->alpha_func = PIPE_FUNC_ALWAYS;
932 }
933
934 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
935 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
936 if (state->depth.bounds_test) {
937 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
938 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
939 }
940
941 return dsa;
942 }
943
944 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
945 {
946 struct si_context *sctx = (struct si_context *)ctx;
947 struct si_state_dsa *dsa = state;
948
949 if (state == NULL)
950 return;
951
952 si_pm4_bind_state(sctx, dsa, dsa);
953
954 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
955 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
956 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
957 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
958 }
959 }
960
961 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
962 {
963 struct si_context *sctx = (struct si_context *)ctx;
964 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
965 }
966
967 static void *si_create_db_flush_dsa(struct si_context *sctx)
968 {
969 struct pipe_depth_stencil_alpha_state dsa = {};
970
971 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
972 }
973
974 /* DB RENDER STATE */
975
976 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
977 {
978 struct si_context *sctx = (struct si_context*)ctx;
979
980 si_mark_atom_dirty(sctx, &sctx->db_render_state);
981 }
982
983 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
984 {
985 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
986 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
987 unsigned db_shader_control;
988
989 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
990
991 /* DB_RENDER_CONTROL */
992 if (sctx->dbcb_depth_copy_enabled ||
993 sctx->dbcb_stencil_copy_enabled) {
994 radeon_emit(cs,
995 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
996 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
997 S_028000_COPY_CENTROID(1) |
998 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
999 } else if (sctx->db_inplace_flush_enabled) {
1000 radeon_emit(cs,
1001 S_028000_DEPTH_COMPRESS_DISABLE(1) |
1002 S_028000_STENCIL_COMPRESS_DISABLE(1));
1003 } else if (sctx->db_depth_clear) {
1004 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1005 } else {
1006 radeon_emit(cs, 0);
1007 }
1008
1009 /* DB_COUNT_CONTROL (occlusion queries) */
1010 if (sctx->b.num_occlusion_queries > 0) {
1011 if (sctx->b.chip_class >= CIK) {
1012 radeon_emit(cs,
1013 S_028004_PERFECT_ZPASS_COUNTS(1) |
1014 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1015 S_028004_ZPASS_ENABLE(1) |
1016 S_028004_SLICE_EVEN_ENABLE(1) |
1017 S_028004_SLICE_ODD_ENABLE(1));
1018 } else {
1019 radeon_emit(cs,
1020 S_028004_PERFECT_ZPASS_COUNTS(1) |
1021 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1022 }
1023 } else {
1024 /* Disable occlusion queries. */
1025 if (sctx->b.chip_class >= CIK) {
1026 radeon_emit(cs, 0);
1027 } else {
1028 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1029 }
1030 }
1031
1032 /* DB_RENDER_OVERRIDE2 */
1033 if (sctx->db_depth_disable_expclear) {
1034 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1035 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1036 } else {
1037 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1038 }
1039
1040 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1041 sctx->ps_db_shader_control;
1042
1043 /* Bug workaround for smoothing (overrasterization) on SI. */
1044 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1045 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1046 else
1047 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1048
1049 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1050 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1051 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1052
1053 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1054 db_shader_control);
1055 }
1056
1057 /*
1058 * format translation
1059 */
1060 static uint32_t si_translate_colorformat(enum pipe_format format)
1061 {
1062 const struct util_format_description *desc = util_format_description(format);
1063
1064 #define HAS_SIZE(x,y,z,w) \
1065 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1066 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1067
1068 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1069 return V_028C70_COLOR_10_11_11;
1070
1071 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1072 return V_028C70_COLOR_INVALID;
1073
1074 switch (desc->nr_channels) {
1075 case 1:
1076 switch (desc->channel[0].size) {
1077 case 8:
1078 return V_028C70_COLOR_8;
1079 case 16:
1080 return V_028C70_COLOR_16;
1081 case 32:
1082 return V_028C70_COLOR_32;
1083 }
1084 break;
1085 case 2:
1086 if (desc->channel[0].size == desc->channel[1].size) {
1087 switch (desc->channel[0].size) {
1088 case 8:
1089 return V_028C70_COLOR_8_8;
1090 case 16:
1091 return V_028C70_COLOR_16_16;
1092 case 32:
1093 return V_028C70_COLOR_32_32;
1094 }
1095 } else if (HAS_SIZE(8,24,0,0)) {
1096 return V_028C70_COLOR_24_8;
1097 } else if (HAS_SIZE(24,8,0,0)) {
1098 return V_028C70_COLOR_8_24;
1099 }
1100 break;
1101 case 3:
1102 if (HAS_SIZE(5,6,5,0)) {
1103 return V_028C70_COLOR_5_6_5;
1104 } else if (HAS_SIZE(32,8,24,0)) {
1105 return V_028C70_COLOR_X24_8_32_FLOAT;
1106 }
1107 break;
1108 case 4:
1109 if (desc->channel[0].size == desc->channel[1].size &&
1110 desc->channel[0].size == desc->channel[2].size &&
1111 desc->channel[0].size == desc->channel[3].size) {
1112 switch (desc->channel[0].size) {
1113 case 4:
1114 return V_028C70_COLOR_4_4_4_4;
1115 case 8:
1116 return V_028C70_COLOR_8_8_8_8;
1117 case 16:
1118 return V_028C70_COLOR_16_16_16_16;
1119 case 32:
1120 return V_028C70_COLOR_32_32_32_32;
1121 }
1122 } else if (HAS_SIZE(5,5,5,1)) {
1123 return V_028C70_COLOR_1_5_5_5;
1124 } else if (HAS_SIZE(10,10,10,2)) {
1125 return V_028C70_COLOR_2_10_10_10;
1126 }
1127 break;
1128 }
1129 return V_028C70_COLOR_INVALID;
1130 }
1131
1132 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1133 {
1134 if (SI_BIG_ENDIAN) {
1135 switch(colorformat) {
1136 /* 8-bit buffers. */
1137 case V_028C70_COLOR_8:
1138 return V_028C70_ENDIAN_NONE;
1139
1140 /* 16-bit buffers. */
1141 case V_028C70_COLOR_5_6_5:
1142 case V_028C70_COLOR_1_5_5_5:
1143 case V_028C70_COLOR_4_4_4_4:
1144 case V_028C70_COLOR_16:
1145 case V_028C70_COLOR_8_8:
1146 return V_028C70_ENDIAN_8IN16;
1147
1148 /* 32-bit buffers. */
1149 case V_028C70_COLOR_8_8_8_8:
1150 case V_028C70_COLOR_2_10_10_10:
1151 case V_028C70_COLOR_8_24:
1152 case V_028C70_COLOR_24_8:
1153 case V_028C70_COLOR_16_16:
1154 return V_028C70_ENDIAN_8IN32;
1155
1156 /* 64-bit buffers. */
1157 case V_028C70_COLOR_16_16_16_16:
1158 return V_028C70_ENDIAN_8IN16;
1159
1160 case V_028C70_COLOR_32_32:
1161 return V_028C70_ENDIAN_8IN32;
1162
1163 /* 128-bit buffers. */
1164 case V_028C70_COLOR_32_32_32_32:
1165 return V_028C70_ENDIAN_8IN32;
1166 default:
1167 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1168 }
1169 } else {
1170 return V_028C70_ENDIAN_NONE;
1171 }
1172 }
1173
1174 /* Returns the size in bits of the widest component of a CB format */
1175 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1176 {
1177 switch(colorformat) {
1178 case V_028C70_COLOR_4_4_4_4:
1179 return 4;
1180
1181 case V_028C70_COLOR_1_5_5_5:
1182 case V_028C70_COLOR_5_5_5_1:
1183 return 5;
1184
1185 case V_028C70_COLOR_5_6_5:
1186 return 6;
1187
1188 case V_028C70_COLOR_8:
1189 case V_028C70_COLOR_8_8:
1190 case V_028C70_COLOR_8_8_8_8:
1191 return 8;
1192
1193 case V_028C70_COLOR_10_10_10_2:
1194 case V_028C70_COLOR_2_10_10_10:
1195 return 10;
1196
1197 case V_028C70_COLOR_10_11_11:
1198 case V_028C70_COLOR_11_11_10:
1199 return 11;
1200
1201 case V_028C70_COLOR_16:
1202 case V_028C70_COLOR_16_16:
1203 case V_028C70_COLOR_16_16_16_16:
1204 return 16;
1205
1206 case V_028C70_COLOR_8_24:
1207 case V_028C70_COLOR_24_8:
1208 return 24;
1209
1210 case V_028C70_COLOR_32:
1211 case V_028C70_COLOR_32_32:
1212 case V_028C70_COLOR_32_32_32_32:
1213 case V_028C70_COLOR_X24_8_32_FLOAT:
1214 return 32;
1215 }
1216
1217 assert(!"Unknown maximum component size");
1218 return 0;
1219 }
1220
1221 static uint32_t si_translate_dbformat(enum pipe_format format)
1222 {
1223 switch (format) {
1224 case PIPE_FORMAT_Z16_UNORM:
1225 return V_028040_Z_16;
1226 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1227 case PIPE_FORMAT_X8Z24_UNORM:
1228 case PIPE_FORMAT_Z24X8_UNORM:
1229 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1230 return V_028040_Z_24; /* deprecated on SI */
1231 case PIPE_FORMAT_Z32_FLOAT:
1232 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1233 return V_028040_Z_32_FLOAT;
1234 default:
1235 return V_028040_Z_INVALID;
1236 }
1237 }
1238
1239 /*
1240 * Texture translation
1241 */
1242
1243 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1244 enum pipe_format format,
1245 const struct util_format_description *desc,
1246 int first_non_void)
1247 {
1248 struct si_screen *sscreen = (struct si_screen*)screen;
1249 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1250 sscreen->b.info.drm_minor >= 31) ||
1251 sscreen->b.info.drm_major == 3;
1252 boolean uniform = TRUE;
1253 int i;
1254
1255 /* Colorspace (return non-RGB formats directly). */
1256 switch (desc->colorspace) {
1257 /* Depth stencil formats */
1258 case UTIL_FORMAT_COLORSPACE_ZS:
1259 switch (format) {
1260 case PIPE_FORMAT_Z16_UNORM:
1261 return V_008F14_IMG_DATA_FORMAT_16;
1262 case PIPE_FORMAT_X24S8_UINT:
1263 case PIPE_FORMAT_Z24X8_UNORM:
1264 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1265 return V_008F14_IMG_DATA_FORMAT_8_24;
1266 case PIPE_FORMAT_X8Z24_UNORM:
1267 case PIPE_FORMAT_S8X24_UINT:
1268 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1269 return V_008F14_IMG_DATA_FORMAT_24_8;
1270 case PIPE_FORMAT_S8_UINT:
1271 return V_008F14_IMG_DATA_FORMAT_8;
1272 case PIPE_FORMAT_Z32_FLOAT:
1273 return V_008F14_IMG_DATA_FORMAT_32;
1274 case PIPE_FORMAT_X32_S8X24_UINT:
1275 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1276 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1277 default:
1278 goto out_unknown;
1279 }
1280
1281 case UTIL_FORMAT_COLORSPACE_YUV:
1282 goto out_unknown; /* TODO */
1283
1284 case UTIL_FORMAT_COLORSPACE_SRGB:
1285 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1286 goto out_unknown;
1287 break;
1288
1289 default:
1290 break;
1291 }
1292
1293 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1294 if (!enable_compressed_formats)
1295 goto out_unknown;
1296
1297 switch (format) {
1298 case PIPE_FORMAT_RGTC1_SNORM:
1299 case PIPE_FORMAT_LATC1_SNORM:
1300 case PIPE_FORMAT_RGTC1_UNORM:
1301 case PIPE_FORMAT_LATC1_UNORM:
1302 return V_008F14_IMG_DATA_FORMAT_BC4;
1303 case PIPE_FORMAT_RGTC2_SNORM:
1304 case PIPE_FORMAT_LATC2_SNORM:
1305 case PIPE_FORMAT_RGTC2_UNORM:
1306 case PIPE_FORMAT_LATC2_UNORM:
1307 return V_008F14_IMG_DATA_FORMAT_BC5;
1308 default:
1309 goto out_unknown;
1310 }
1311 }
1312
1313 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1314 if (!enable_compressed_formats)
1315 goto out_unknown;
1316
1317 switch (format) {
1318 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1319 case PIPE_FORMAT_BPTC_SRGBA:
1320 return V_008F14_IMG_DATA_FORMAT_BC7;
1321 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1322 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1323 return V_008F14_IMG_DATA_FORMAT_BC6;
1324 default:
1325 goto out_unknown;
1326 }
1327 }
1328
1329 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1330 switch (format) {
1331 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1332 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1333 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1334 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1335 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1336 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1337 default:
1338 goto out_unknown;
1339 }
1340 }
1341
1342 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1343 if (!enable_compressed_formats)
1344 goto out_unknown;
1345
1346 if (!util_format_s3tc_enabled) {
1347 goto out_unknown;
1348 }
1349
1350 switch (format) {
1351 case PIPE_FORMAT_DXT1_RGB:
1352 case PIPE_FORMAT_DXT1_RGBA:
1353 case PIPE_FORMAT_DXT1_SRGB:
1354 case PIPE_FORMAT_DXT1_SRGBA:
1355 return V_008F14_IMG_DATA_FORMAT_BC1;
1356 case PIPE_FORMAT_DXT3_RGBA:
1357 case PIPE_FORMAT_DXT3_SRGBA:
1358 return V_008F14_IMG_DATA_FORMAT_BC2;
1359 case PIPE_FORMAT_DXT5_RGBA:
1360 case PIPE_FORMAT_DXT5_SRGBA:
1361 return V_008F14_IMG_DATA_FORMAT_BC3;
1362 default:
1363 goto out_unknown;
1364 }
1365 }
1366
1367 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1368 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1369 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1370 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1371 }
1372
1373 /* R8G8Bx_SNORM - TODO CxV8U8 */
1374
1375 /* See whether the components are of the same size. */
1376 for (i = 1; i < desc->nr_channels; i++) {
1377 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1378 }
1379
1380 /* Non-uniform formats. */
1381 if (!uniform) {
1382 switch(desc->nr_channels) {
1383 case 3:
1384 if (desc->channel[0].size == 5 &&
1385 desc->channel[1].size == 6 &&
1386 desc->channel[2].size == 5) {
1387 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1388 }
1389 goto out_unknown;
1390 case 4:
1391 if (desc->channel[0].size == 5 &&
1392 desc->channel[1].size == 5 &&
1393 desc->channel[2].size == 5 &&
1394 desc->channel[3].size == 1) {
1395 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1396 }
1397 if (desc->channel[0].size == 10 &&
1398 desc->channel[1].size == 10 &&
1399 desc->channel[2].size == 10 &&
1400 desc->channel[3].size == 2) {
1401 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1402 }
1403 goto out_unknown;
1404 }
1405 goto out_unknown;
1406 }
1407
1408 if (first_non_void < 0 || first_non_void > 3)
1409 goto out_unknown;
1410
1411 /* uniform formats */
1412 switch (desc->channel[first_non_void].size) {
1413 case 4:
1414 switch (desc->nr_channels) {
1415 #if 0 /* Not supported for render targets */
1416 case 2:
1417 return V_008F14_IMG_DATA_FORMAT_4_4;
1418 #endif
1419 case 4:
1420 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1421 }
1422 break;
1423 case 8:
1424 switch (desc->nr_channels) {
1425 case 1:
1426 return V_008F14_IMG_DATA_FORMAT_8;
1427 case 2:
1428 return V_008F14_IMG_DATA_FORMAT_8_8;
1429 case 4:
1430 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1431 }
1432 break;
1433 case 16:
1434 switch (desc->nr_channels) {
1435 case 1:
1436 return V_008F14_IMG_DATA_FORMAT_16;
1437 case 2:
1438 return V_008F14_IMG_DATA_FORMAT_16_16;
1439 case 4:
1440 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1441 }
1442 break;
1443 case 32:
1444 switch (desc->nr_channels) {
1445 case 1:
1446 return V_008F14_IMG_DATA_FORMAT_32;
1447 case 2:
1448 return V_008F14_IMG_DATA_FORMAT_32_32;
1449 #if 0 /* Not supported for render targets */
1450 case 3:
1451 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1452 #endif
1453 case 4:
1454 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1455 }
1456 }
1457
1458 out_unknown:
1459 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1460 return ~0;
1461 }
1462
1463 static unsigned si_tex_wrap(unsigned wrap)
1464 {
1465 switch (wrap) {
1466 default:
1467 case PIPE_TEX_WRAP_REPEAT:
1468 return V_008F30_SQ_TEX_WRAP;
1469 case PIPE_TEX_WRAP_CLAMP:
1470 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1471 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1472 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1473 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1474 return V_008F30_SQ_TEX_CLAMP_BORDER;
1475 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1476 return V_008F30_SQ_TEX_MIRROR;
1477 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1478 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1479 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1480 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1481 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1482 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1483 }
1484 }
1485
1486 static unsigned si_tex_filter(unsigned filter)
1487 {
1488 switch (filter) {
1489 default:
1490 case PIPE_TEX_FILTER_NEAREST:
1491 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1492 case PIPE_TEX_FILTER_LINEAR:
1493 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1494 }
1495 }
1496
1497 static unsigned si_tex_mipfilter(unsigned filter)
1498 {
1499 switch (filter) {
1500 case PIPE_TEX_MIPFILTER_NEAREST:
1501 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1502 case PIPE_TEX_MIPFILTER_LINEAR:
1503 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1504 default:
1505 case PIPE_TEX_MIPFILTER_NONE:
1506 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1507 }
1508 }
1509
1510 static unsigned si_tex_compare(unsigned compare)
1511 {
1512 switch (compare) {
1513 default:
1514 case PIPE_FUNC_NEVER:
1515 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1516 case PIPE_FUNC_LESS:
1517 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1518 case PIPE_FUNC_EQUAL:
1519 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1520 case PIPE_FUNC_LEQUAL:
1521 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1522 case PIPE_FUNC_GREATER:
1523 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1524 case PIPE_FUNC_NOTEQUAL:
1525 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1526 case PIPE_FUNC_GEQUAL:
1527 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1528 case PIPE_FUNC_ALWAYS:
1529 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1530 }
1531 }
1532
1533 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1534 {
1535 switch (dim) {
1536 default:
1537 case PIPE_TEXTURE_1D:
1538 return V_008F1C_SQ_RSRC_IMG_1D;
1539 case PIPE_TEXTURE_1D_ARRAY:
1540 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1541 case PIPE_TEXTURE_2D:
1542 case PIPE_TEXTURE_RECT:
1543 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1544 V_008F1C_SQ_RSRC_IMG_2D;
1545 case PIPE_TEXTURE_2D_ARRAY:
1546 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1547 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1548 case PIPE_TEXTURE_3D:
1549 return V_008F1C_SQ_RSRC_IMG_3D;
1550 case PIPE_TEXTURE_CUBE:
1551 case PIPE_TEXTURE_CUBE_ARRAY:
1552 return V_008F1C_SQ_RSRC_IMG_CUBE;
1553 }
1554 }
1555
1556 /*
1557 * Format support testing
1558 */
1559
1560 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1561 {
1562 return si_translate_texformat(screen, format, util_format_description(format),
1563 util_format_get_first_non_void_channel(format)) != ~0U;
1564 }
1565
1566 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1567 const struct util_format_description *desc,
1568 int first_non_void)
1569 {
1570 unsigned type = desc->channel[first_non_void].type;
1571 int i;
1572
1573 if (type == UTIL_FORMAT_TYPE_FIXED)
1574 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1575
1576 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1577 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1578
1579 if (desc->nr_channels == 4 &&
1580 desc->channel[0].size == 10 &&
1581 desc->channel[1].size == 10 &&
1582 desc->channel[2].size == 10 &&
1583 desc->channel[3].size == 2)
1584 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1585
1586 /* See whether the components are of the same size. */
1587 for (i = 0; i < desc->nr_channels; i++) {
1588 if (desc->channel[first_non_void].size != desc->channel[i].size)
1589 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1590 }
1591
1592 switch (desc->channel[first_non_void].size) {
1593 case 8:
1594 switch (desc->nr_channels) {
1595 case 1:
1596 return V_008F0C_BUF_DATA_FORMAT_8;
1597 case 2:
1598 return V_008F0C_BUF_DATA_FORMAT_8_8;
1599 case 3:
1600 case 4:
1601 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1602 }
1603 break;
1604 case 16:
1605 switch (desc->nr_channels) {
1606 case 1:
1607 return V_008F0C_BUF_DATA_FORMAT_16;
1608 case 2:
1609 return V_008F0C_BUF_DATA_FORMAT_16_16;
1610 case 3:
1611 case 4:
1612 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1613 }
1614 break;
1615 case 32:
1616 /* From the Southern Islands ISA documentation about MTBUF:
1617 * 'Memory reads of data in memory that is 32 or 64 bits do not
1618 * undergo any format conversion.'
1619 */
1620 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1621 !desc->channel[first_non_void].pure_integer)
1622 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1623
1624 switch (desc->nr_channels) {
1625 case 1:
1626 return V_008F0C_BUF_DATA_FORMAT_32;
1627 case 2:
1628 return V_008F0C_BUF_DATA_FORMAT_32_32;
1629 case 3:
1630 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1631 case 4:
1632 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1633 }
1634 break;
1635 }
1636
1637 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1638 }
1639
1640 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1641 const struct util_format_description *desc,
1642 int first_non_void)
1643 {
1644 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1645 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1646
1647 switch (desc->channel[first_non_void].type) {
1648 case UTIL_FORMAT_TYPE_SIGNED:
1649 if (desc->channel[first_non_void].normalized)
1650 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1651 else if (desc->channel[first_non_void].pure_integer)
1652 return V_008F0C_BUF_NUM_FORMAT_SINT;
1653 else
1654 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1655 break;
1656 case UTIL_FORMAT_TYPE_UNSIGNED:
1657 if (desc->channel[first_non_void].normalized)
1658 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1659 else if (desc->channel[first_non_void].pure_integer)
1660 return V_008F0C_BUF_NUM_FORMAT_UINT;
1661 else
1662 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1663 break;
1664 case UTIL_FORMAT_TYPE_FLOAT:
1665 default:
1666 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1667 }
1668 }
1669
1670 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1671 {
1672 const struct util_format_description *desc;
1673 int first_non_void;
1674 unsigned data_format;
1675
1676 desc = util_format_description(format);
1677 first_non_void = util_format_get_first_non_void_channel(format);
1678 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1679 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1680 }
1681
1682 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1683 {
1684 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1685 r600_translate_colorswap(format) != ~0U;
1686 }
1687
1688 static bool si_is_zs_format_supported(enum pipe_format format)
1689 {
1690 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1691 }
1692
1693 boolean si_is_format_supported(struct pipe_screen *screen,
1694 enum pipe_format format,
1695 enum pipe_texture_target target,
1696 unsigned sample_count,
1697 unsigned usage)
1698 {
1699 unsigned retval = 0;
1700
1701 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1702 R600_ERR("r600: unsupported texture type %d\n", target);
1703 return FALSE;
1704 }
1705
1706 if (!util_format_is_supported(format, usage))
1707 return FALSE;
1708
1709 if (sample_count > 1) {
1710 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1711 return FALSE;
1712
1713 switch (sample_count) {
1714 case 2:
1715 case 4:
1716 case 8:
1717 break;
1718 default:
1719 return FALSE;
1720 }
1721 }
1722
1723 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1724 if (target == PIPE_BUFFER) {
1725 if (si_is_vertex_format_supported(screen, format))
1726 retval |= PIPE_BIND_SAMPLER_VIEW;
1727 } else {
1728 if (si_is_sampler_format_supported(screen, format))
1729 retval |= PIPE_BIND_SAMPLER_VIEW;
1730 }
1731 }
1732
1733 if ((usage & (PIPE_BIND_RENDER_TARGET |
1734 PIPE_BIND_DISPLAY_TARGET |
1735 PIPE_BIND_SCANOUT |
1736 PIPE_BIND_SHARED |
1737 PIPE_BIND_BLENDABLE)) &&
1738 si_is_colorbuffer_format_supported(format)) {
1739 retval |= usage &
1740 (PIPE_BIND_RENDER_TARGET |
1741 PIPE_BIND_DISPLAY_TARGET |
1742 PIPE_BIND_SCANOUT |
1743 PIPE_BIND_SHARED);
1744 if (!util_format_is_pure_integer(format) &&
1745 !util_format_is_depth_or_stencil(format))
1746 retval |= usage & PIPE_BIND_BLENDABLE;
1747 }
1748
1749 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1750 si_is_zs_format_supported(format)) {
1751 retval |= PIPE_BIND_DEPTH_STENCIL;
1752 }
1753
1754 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1755 si_is_vertex_format_supported(screen, format)) {
1756 retval |= PIPE_BIND_VERTEX_BUFFER;
1757 }
1758
1759 if (usage & PIPE_BIND_TRANSFER_READ)
1760 retval |= PIPE_BIND_TRANSFER_READ;
1761 if (usage & PIPE_BIND_TRANSFER_WRITE)
1762 retval |= PIPE_BIND_TRANSFER_WRITE;
1763
1764 return retval == usage;
1765 }
1766
1767 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1768 {
1769 unsigned tile_mode_index = 0;
1770
1771 if (stencil) {
1772 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1773 } else {
1774 tile_mode_index = rtex->surface.tiling_index[level];
1775 }
1776 return tile_mode_index;
1777 }
1778
1779 /*
1780 * framebuffer handling
1781 */
1782
1783 static void si_initialize_color_surface(struct si_context *sctx,
1784 struct r600_surface *surf)
1785 {
1786 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1787 unsigned level = surf->base.u.tex.level;
1788 uint64_t offset = rtex->surface.level[level].offset;
1789 unsigned pitch, slice;
1790 unsigned color_info, color_attrib, color_pitch, color_view;
1791 unsigned tile_mode_index;
1792 unsigned format, swap, ntype, endian;
1793 const struct util_format_description *desc;
1794 int i;
1795 unsigned blend_clamp = 0, blend_bypass = 0;
1796 unsigned max_comp_size;
1797
1798 /* Layered rendering doesn't work with LINEAR_GENERAL.
1799 * (LINEAR_ALIGNED and others work) */
1800 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1801 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1802 offset += rtex->surface.level[level].slice_size *
1803 surf->base.u.tex.first_layer;
1804 color_view = 0;
1805 } else {
1806 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1807 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1808 }
1809
1810 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1811 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1812 if (slice) {
1813 slice = slice - 1;
1814 }
1815
1816 tile_mode_index = si_tile_mode_index(rtex, level, false);
1817
1818 desc = util_format_description(surf->base.format);
1819 for (i = 0; i < 4; i++) {
1820 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1821 break;
1822 }
1823 }
1824 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1825 ntype = V_028C70_NUMBER_FLOAT;
1826 } else {
1827 ntype = V_028C70_NUMBER_UNORM;
1828 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1829 ntype = V_028C70_NUMBER_SRGB;
1830 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1831 if (desc->channel[i].pure_integer) {
1832 ntype = V_028C70_NUMBER_SINT;
1833 } else {
1834 assert(desc->channel[i].normalized);
1835 ntype = V_028C70_NUMBER_SNORM;
1836 }
1837 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1838 if (desc->channel[i].pure_integer) {
1839 ntype = V_028C70_NUMBER_UINT;
1840 } else {
1841 assert(desc->channel[i].normalized);
1842 ntype = V_028C70_NUMBER_UNORM;
1843 }
1844 }
1845 }
1846
1847 format = si_translate_colorformat(surf->base.format);
1848 if (format == V_028C70_COLOR_INVALID) {
1849 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1850 }
1851 assert(format != V_028C70_COLOR_INVALID);
1852 swap = r600_translate_colorswap(surf->base.format);
1853 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1854 endian = V_028C70_ENDIAN_NONE;
1855 } else {
1856 endian = si_colorformat_endian_swap(format);
1857 }
1858
1859 /* blend clamp should be set for all NORM/SRGB types */
1860 if (ntype == V_028C70_NUMBER_UNORM ||
1861 ntype == V_028C70_NUMBER_SNORM ||
1862 ntype == V_028C70_NUMBER_SRGB)
1863 blend_clamp = 1;
1864
1865 /* set blend bypass according to docs if SINT/UINT or
1866 8/24 COLOR variants */
1867 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1868 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1869 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1870 blend_clamp = 0;
1871 blend_bypass = 1;
1872 }
1873
1874 color_info = S_028C70_FORMAT(format) |
1875 S_028C70_COMP_SWAP(swap) |
1876 S_028C70_BLEND_CLAMP(blend_clamp) |
1877 S_028C70_BLEND_BYPASS(blend_bypass) |
1878 S_028C70_NUMBER_TYPE(ntype) |
1879 S_028C70_ENDIAN(endian);
1880
1881 color_pitch = S_028C64_TILE_MAX(pitch);
1882
1883 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1884 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1885
1886 if (rtex->resource.b.b.nr_samples > 1) {
1887 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1888
1889 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1890 S_028C74_NUM_FRAGMENTS(log_samples);
1891
1892 if (rtex->fmask.size) {
1893 color_info |= S_028C70_COMPRESSION(1);
1894 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1895
1896 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1897
1898 if (sctx->b.chip_class == SI) {
1899 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1900 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1901 }
1902 if (sctx->b.chip_class >= CIK) {
1903 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1904 }
1905 }
1906 }
1907
1908 offset += rtex->resource.gpu_address;
1909
1910 surf->cb_color_base = offset >> 8;
1911 surf->cb_color_pitch = color_pitch;
1912 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1913 surf->cb_color_view = color_view;
1914 surf->cb_color_info = color_info;
1915 surf->cb_color_attrib = color_attrib;
1916
1917 if (sctx->b.chip_class >= VI)
1918 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1919
1920 if (rtex->fmask.size) {
1921 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1922 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1923 } else {
1924 /* This must be set for fast clear to work without FMASK. */
1925 surf->cb_color_fmask = surf->cb_color_base;
1926 surf->cb_color_fmask_slice = surf->cb_color_slice;
1927 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1928
1929 if (sctx->b.chip_class == SI) {
1930 unsigned bankh = util_logbase2(rtex->surface.bankh);
1931 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1932 }
1933
1934 if (sctx->b.chip_class >= CIK) {
1935 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1936 }
1937 }
1938
1939 /* Determine pixel shader export format */
1940 max_comp_size = si_colorformat_max_comp_size(format);
1941 if (ntype == V_028C70_NUMBER_SRGB ||
1942 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1943 max_comp_size <= 10) ||
1944 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1945 surf->export_16bpc = true;
1946 }
1947
1948 surf->color_initialized = true;
1949 }
1950
1951 static void si_init_depth_surface(struct si_context *sctx,
1952 struct r600_surface *surf)
1953 {
1954 struct si_screen *sscreen = sctx->screen;
1955 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1956 unsigned level = surf->base.u.tex.level;
1957 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1958 unsigned format, tile_mode_index, array_mode;
1959 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1960 uint32_t z_info, s_info, db_depth_info;
1961 uint64_t z_offs, s_offs;
1962 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1963
1964 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1965 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1966 case PIPE_FORMAT_X8Z24_UNORM:
1967 case PIPE_FORMAT_Z24X8_UNORM:
1968 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1969 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1970 break;
1971 case PIPE_FORMAT_Z32_FLOAT:
1972 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1973 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1974 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1975 break;
1976 case PIPE_FORMAT_Z16_UNORM:
1977 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1978 break;
1979 default:
1980 assert(0);
1981 }
1982
1983 format = si_translate_dbformat(rtex->resource.b.b.format);
1984
1985 if (format == V_028040_Z_INVALID) {
1986 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1987 }
1988 assert(format != V_028040_Z_INVALID);
1989
1990 s_offs = z_offs = rtex->resource.gpu_address;
1991 z_offs += rtex->surface.level[level].offset;
1992 s_offs += rtex->surface.stencil_level[level].offset;
1993
1994 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1995
1996 z_info = S_028040_FORMAT(format);
1997 if (rtex->resource.b.b.nr_samples > 1) {
1998 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1999 }
2000
2001 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2002 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2003 else
2004 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2005
2006 if (sctx->b.chip_class >= CIK) {
2007 switch (rtex->surface.level[level].mode) {
2008 case RADEON_SURF_MODE_2D:
2009 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2010 break;
2011 case RADEON_SURF_MODE_1D:
2012 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2013 case RADEON_SURF_MODE_LINEAR:
2014 default:
2015 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2016 break;
2017 }
2018 tile_split = rtex->surface.tile_split;
2019 stile_split = rtex->surface.stencil_tile_split;
2020 macro_aspect = rtex->surface.mtilea;
2021 bankw = rtex->surface.bankw;
2022 bankh = rtex->surface.bankh;
2023 tile_split = cik_tile_split(tile_split);
2024 stile_split = cik_tile_split(stile_split);
2025 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2026 bankw = cik_bank_wh(bankw);
2027 bankh = cik_bank_wh(bankh);
2028 nbanks = si_num_banks(sscreen, rtex);
2029 tile_mode_index = si_tile_mode_index(rtex, level, false);
2030 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2031
2032 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2033 S_02803C_PIPE_CONFIG(pipe_config) |
2034 S_02803C_BANK_WIDTH(bankw) |
2035 S_02803C_BANK_HEIGHT(bankh) |
2036 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2037 S_02803C_NUM_BANKS(nbanks);
2038 z_info |= S_028040_TILE_SPLIT(tile_split);
2039 s_info |= S_028044_TILE_SPLIT(stile_split);
2040 } else {
2041 tile_mode_index = si_tile_mode_index(rtex, level, false);
2042 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2043 tile_mode_index = si_tile_mode_index(rtex, level, true);
2044 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2045 }
2046
2047 /* HiZ aka depth buffer htile */
2048 /* use htile only for first level */
2049 if (rtex->htile_buffer && !level) {
2050 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2051 S_028040_ALLOW_EXPCLEAR(1);
2052
2053 /* Use all of the htile_buffer for depth, because we don't
2054 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2055 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2056
2057 uint64_t va = rtex->htile_buffer->gpu_address;
2058 db_htile_data_base = va >> 8;
2059 db_htile_surface = S_028ABC_FULL_CACHE(1);
2060 } else {
2061 db_htile_data_base = 0;
2062 db_htile_surface = 0;
2063 }
2064
2065 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2066
2067 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2068 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2069 surf->db_htile_data_base = db_htile_data_base;
2070 surf->db_depth_info = db_depth_info;
2071 surf->db_z_info = z_info;
2072 surf->db_stencil_info = s_info;
2073 surf->db_depth_base = z_offs >> 8;
2074 surf->db_stencil_base = s_offs >> 8;
2075 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2076 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2077 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2078 levelinfo->nblk_y) / 64 - 1);
2079 surf->db_htile_surface = db_htile_surface;
2080 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2081
2082 surf->depth_initialized = true;
2083 }
2084
2085 static void si_set_framebuffer_state(struct pipe_context *ctx,
2086 const struct pipe_framebuffer_state *state)
2087 {
2088 struct si_context *sctx = (struct si_context *)ctx;
2089 struct pipe_constant_buffer constbuf = {0};
2090 struct r600_surface *surf = NULL;
2091 struct r600_texture *rtex;
2092 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2093 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2094 int i;
2095
2096 /* Only flush TC when changing the framebuffer state, because
2097 * the only client not using TC that can change textures is
2098 * the framebuffer.
2099 *
2100 * Flush all CB and DB caches here because all buffers can be used
2101 * for write by both TC (with shader image stores) and CB/DB.
2102 */
2103 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2104 SI_CONTEXT_INV_TC_L2 |
2105 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2106
2107 /* Take the maximum of the old and new count. If the new count is lower,
2108 * dirtying is needed to disable the unbound colorbuffers.
2109 */
2110 sctx->framebuffer.dirty_cbufs |=
2111 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2112 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2113
2114 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2115
2116 sctx->framebuffer.export_16bpc = 0;
2117 sctx->framebuffer.compressed_cb_mask = 0;
2118 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2119 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2120 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2121 util_format_is_pure_integer(state->cbufs[0]->format);
2122
2123 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2124 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2125
2126 for (i = 0; i < state->nr_cbufs; i++) {
2127 if (!state->cbufs[i])
2128 continue;
2129
2130 surf = (struct r600_surface*)state->cbufs[i];
2131 rtex = (struct r600_texture*)surf->base.texture;
2132
2133 if (!surf->color_initialized) {
2134 si_initialize_color_surface(sctx, surf);
2135 }
2136
2137 if (surf->export_16bpc) {
2138 sctx->framebuffer.export_16bpc |= 1 << i;
2139 }
2140
2141 if (rtex->fmask.size && rtex->cmask.size) {
2142 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2143 }
2144 r600_context_add_resource_size(ctx, surf->base.texture);
2145 }
2146 /* Set the 16BPC export for possible dual-src blending. */
2147 if (i == 1 && surf && surf->export_16bpc) {
2148 sctx->framebuffer.export_16bpc |= 1 << 1;
2149 }
2150
2151 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2152
2153 if (state->zsbuf) {
2154 surf = (struct r600_surface*)state->zsbuf;
2155
2156 if (!surf->depth_initialized) {
2157 si_init_depth_surface(sctx, surf);
2158 }
2159 r600_context_add_resource_size(ctx, surf->base.texture);
2160 }
2161
2162 si_update_poly_offset_state(sctx);
2163 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2164 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2165
2166 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2167 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2168 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2169
2170 /* Set sample locations as fragment shader constants. */
2171 switch (sctx->framebuffer.nr_samples) {
2172 case 1:
2173 constbuf.user_buffer = sctx->b.sample_locations_1x;
2174 break;
2175 case 2:
2176 constbuf.user_buffer = sctx->b.sample_locations_2x;
2177 break;
2178 case 4:
2179 constbuf.user_buffer = sctx->b.sample_locations_4x;
2180 break;
2181 case 8:
2182 constbuf.user_buffer = sctx->b.sample_locations_8x;
2183 break;
2184 case 16:
2185 constbuf.user_buffer = sctx->b.sample_locations_16x;
2186 break;
2187 default:
2188 assert(0);
2189 }
2190 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2191 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2192 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2193
2194 /* Smoothing (only possible with nr_samples == 1) uses the same
2195 * sample locations as the MSAA it simulates.
2196 *
2197 * Therefore, don't update the sample locations when
2198 * transitioning from no AA to smoothing-equivalent AA, and
2199 * vice versa.
2200 */
2201 if ((sctx->framebuffer.nr_samples != 1 ||
2202 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2203 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2204 old_nr_samples != 1))
2205 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2206 }
2207 }
2208
2209 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2210 {
2211 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2212 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2213 unsigned i, nr_cbufs = state->nr_cbufs;
2214 struct r600_texture *tex = NULL;
2215 struct r600_surface *cb = NULL;
2216
2217 /* Colorbuffers. */
2218 for (i = 0; i < nr_cbufs; i++) {
2219 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2220 continue;
2221
2222 cb = (struct r600_surface*)state->cbufs[i];
2223 if (!cb) {
2224 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2225 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2226 continue;
2227 }
2228
2229 tex = (struct r600_texture *)cb->base.texture;
2230 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2231 &tex->resource, RADEON_USAGE_READWRITE,
2232 tex->surface.nsamples > 1 ?
2233 RADEON_PRIO_COLOR_BUFFER_MSAA :
2234 RADEON_PRIO_COLOR_BUFFER);
2235
2236 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2237 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2238 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2239 RADEON_PRIO_COLOR_META);
2240 }
2241
2242 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2243 sctx->b.chip_class >= VI ? 14 : 13);
2244 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2245 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2246 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2247 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2248 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2249 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2250 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2251 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2252 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2253 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2254 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2255 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2256 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2257
2258 if (sctx->b.chip_class >= VI)
2259 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2260 }
2261 /* set CB_COLOR1_INFO for possible dual-src blending */
2262 if (i == 1 && state->cbufs[0] &&
2263 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2264 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2265 cb->cb_color_info | tex->cb_color_info);
2266 i++;
2267 }
2268 for (; i < 8 ; i++)
2269 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2270 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2271
2272 /* ZS buffer. */
2273 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2274 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2275 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2276
2277 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2278 &rtex->resource, RADEON_USAGE_READWRITE,
2279 zb->base.texture->nr_samples > 1 ?
2280 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2281 RADEON_PRIO_DEPTH_BUFFER);
2282
2283 if (zb->db_htile_data_base) {
2284 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2285 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2286 RADEON_PRIO_DEPTH_META);
2287 }
2288
2289 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2290 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2291
2292 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2293 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2294 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2295 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2296 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2297 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2298 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2299 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2300 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2301 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2302 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2303
2304 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2305 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2306 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2307 zb->pa_su_poly_offset_db_fmt_cntl);
2308 } else if (sctx->framebuffer.dirty_zsbuf) {
2309 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2310 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2311 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2312 }
2313
2314 /* Framebuffer dimensions. */
2315 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2316 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2317 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2318
2319 sctx->framebuffer.dirty_cbufs = 0;
2320 sctx->framebuffer.dirty_zsbuf = false;
2321 }
2322
2323 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2324 struct r600_atom *atom)
2325 {
2326 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2327 unsigned nr_samples = sctx->framebuffer.nr_samples;
2328
2329 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2330 SI_NUM_SMOOTH_AA_SAMPLES);
2331 }
2332
2333 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2334 {
2335 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2336
2337 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2338 sctx->ps_iter_samples,
2339 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2340 }
2341
2342
2343 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2344 {
2345 struct si_context *sctx = (struct si_context *)ctx;
2346
2347 if (sctx->ps_iter_samples == min_samples)
2348 return;
2349
2350 sctx->ps_iter_samples = min_samples;
2351
2352 if (sctx->framebuffer.nr_samples > 1)
2353 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2354 }
2355
2356 /*
2357 * Samplers
2358 */
2359
2360 /**
2361 * Create a sampler view.
2362 *
2363 * @param ctx context
2364 * @param texture texture
2365 * @param state sampler view template
2366 * @param width0 width0 override (for compressed textures as int)
2367 * @param height0 height0 override (for compressed textures as int)
2368 * @param force_level set the base address to the level (for compressed textures)
2369 */
2370 struct pipe_sampler_view *
2371 si_create_sampler_view_custom(struct pipe_context *ctx,
2372 struct pipe_resource *texture,
2373 const struct pipe_sampler_view *state,
2374 unsigned width0, unsigned height0,
2375 unsigned force_level)
2376 {
2377 struct si_context *sctx = (struct si_context*)ctx;
2378 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2379 struct r600_texture *tmp = (struct r600_texture*)texture;
2380 const struct util_format_description *desc;
2381 unsigned format, num_format, base_level, first_level, last_level;
2382 uint32_t pitch = 0;
2383 unsigned char state_swizzle[4], swizzle[4];
2384 unsigned height, depth, width;
2385 enum pipe_format pipe_format = state->format;
2386 struct radeon_surf_level *surflevel;
2387 int first_non_void;
2388 uint64_t va;
2389
2390 if (view == NULL)
2391 return NULL;
2392
2393 /* initialize base object */
2394 view->base = *state;
2395 view->base.texture = NULL;
2396 view->base.reference.count = 1;
2397 view->base.context = ctx;
2398
2399 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2400 if (!texture) {
2401 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2402 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2403 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2404 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2405 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2406 return &view->base;
2407 }
2408
2409 pipe_resource_reference(&view->base.texture, texture);
2410 view->resource = &tmp->resource;
2411
2412 /* Buffer resource. */
2413 if (texture->target == PIPE_BUFFER) {
2414 unsigned stride, num_records;
2415
2416 desc = util_format_description(state->format);
2417 first_non_void = util_format_get_first_non_void_channel(state->format);
2418 stride = desc->block.bits / 8;
2419 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2420 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2421 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2422
2423 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2424 num_records = MIN2(num_records, texture->width0 / stride);
2425
2426 if (sctx->b.chip_class >= VI)
2427 num_records *= stride;
2428
2429 view->state[4] = va;
2430 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2431 S_008F04_STRIDE(stride);
2432 view->state[6] = num_records;
2433 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2434 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2435 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2436 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2437 S_008F0C_NUM_FORMAT(num_format) |
2438 S_008F0C_DATA_FORMAT(format);
2439
2440 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2441 return &view->base;
2442 }
2443
2444 state_swizzle[0] = state->swizzle_r;
2445 state_swizzle[1] = state->swizzle_g;
2446 state_swizzle[2] = state->swizzle_b;
2447 state_swizzle[3] = state->swizzle_a;
2448
2449 surflevel = tmp->surface.level;
2450
2451 /* Texturing with separate depth and stencil. */
2452 if (tmp->is_depth && !tmp->is_flushing_texture) {
2453 switch (pipe_format) {
2454 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2455 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2456 break;
2457 case PIPE_FORMAT_X8Z24_UNORM:
2458 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2459 /* Z24 is always stored like this. */
2460 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2461 break;
2462 case PIPE_FORMAT_X24S8_UINT:
2463 case PIPE_FORMAT_S8X24_UINT:
2464 case PIPE_FORMAT_X32_S8X24_UINT:
2465 pipe_format = PIPE_FORMAT_S8_UINT;
2466 surflevel = tmp->surface.stencil_level;
2467 break;
2468 default:;
2469 }
2470 }
2471
2472 desc = util_format_description(pipe_format);
2473
2474 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2475 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2476 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2477
2478 switch (pipe_format) {
2479 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2480 case PIPE_FORMAT_X24S8_UINT:
2481 case PIPE_FORMAT_X32_S8X24_UINT:
2482 case PIPE_FORMAT_X8Z24_UNORM:
2483 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2484 break;
2485 default:
2486 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2487 }
2488 } else {
2489 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2490 }
2491
2492 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2493
2494 switch (pipe_format) {
2495 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2496 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2497 break;
2498 default:
2499 if (first_non_void < 0) {
2500 if (util_format_is_compressed(pipe_format)) {
2501 switch (pipe_format) {
2502 case PIPE_FORMAT_DXT1_SRGB:
2503 case PIPE_FORMAT_DXT1_SRGBA:
2504 case PIPE_FORMAT_DXT3_SRGBA:
2505 case PIPE_FORMAT_DXT5_SRGBA:
2506 case PIPE_FORMAT_BPTC_SRGBA:
2507 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2508 break;
2509 case PIPE_FORMAT_RGTC1_SNORM:
2510 case PIPE_FORMAT_LATC1_SNORM:
2511 case PIPE_FORMAT_RGTC2_SNORM:
2512 case PIPE_FORMAT_LATC2_SNORM:
2513 /* implies float, so use SNORM/UNORM to determine
2514 whether data is signed or not */
2515 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2516 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2517 break;
2518 default:
2519 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2520 break;
2521 }
2522 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2523 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2524 } else {
2525 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2526 }
2527 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2528 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2529 } else {
2530 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2531
2532 switch (desc->channel[first_non_void].type) {
2533 case UTIL_FORMAT_TYPE_FLOAT:
2534 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2535 break;
2536 case UTIL_FORMAT_TYPE_SIGNED:
2537 if (desc->channel[first_non_void].normalized)
2538 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2539 else if (desc->channel[first_non_void].pure_integer)
2540 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2541 else
2542 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2543 break;
2544 case UTIL_FORMAT_TYPE_UNSIGNED:
2545 if (desc->channel[first_non_void].normalized)
2546 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2547 else if (desc->channel[first_non_void].pure_integer)
2548 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2549 else
2550 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2551 }
2552 }
2553 }
2554
2555 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2556 if (format == ~0) {
2557 format = 0;
2558 }
2559
2560 base_level = 0;
2561 first_level = state->u.tex.first_level;
2562 last_level = state->u.tex.last_level;
2563 width = width0;
2564 height = height0;
2565 depth = texture->depth0;
2566
2567 if (force_level) {
2568 assert(force_level == first_level &&
2569 force_level == last_level);
2570 base_level = force_level;
2571 first_level = 0;
2572 last_level = 0;
2573 width = u_minify(width, force_level);
2574 height = u_minify(height, force_level);
2575 depth = u_minify(depth, force_level);
2576 }
2577
2578 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2579
2580 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2581 height = 1;
2582 depth = texture->array_size;
2583 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2584 depth = texture->array_size;
2585 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2586 depth = texture->array_size / 6;
2587
2588 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2589
2590 view->state[0] = va >> 8;
2591 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2592 S_008F14_DATA_FORMAT(format) |
2593 S_008F14_NUM_FORMAT(num_format));
2594 view->state[2] = (S_008F18_WIDTH(width - 1) |
2595 S_008F18_HEIGHT(height - 1));
2596 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2597 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2598 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2599 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2600 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2601 0 : first_level) |
2602 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2603 util_logbase2(texture->nr_samples) :
2604 last_level) |
2605 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2606 S_008F1C_POW2_PAD(texture->last_level > 0) |
2607 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2608 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2609 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2610 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2611 view->state[6] = 0;
2612 view->state[7] = 0;
2613
2614 /* Initialize the sampler view for FMASK. */
2615 if (tmp->fmask.size) {
2616 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2617 uint32_t fmask_format;
2618
2619 switch (texture->nr_samples) {
2620 case 2:
2621 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2622 break;
2623 case 4:
2624 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2625 break;
2626 case 8:
2627 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2628 break;
2629 default:
2630 assert(0);
2631 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2632 }
2633
2634 view->fmask_state[0] = va >> 8;
2635 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2636 S_008F14_DATA_FORMAT(fmask_format) |
2637 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2638 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2639 S_008F18_HEIGHT(height - 1);
2640 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2641 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2642 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2643 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2644 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2645 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2646 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2647 S_008F20_PITCH(tmp->fmask.pitch - 1);
2648 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2649 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2650 view->fmask_state[6] = 0;
2651 view->fmask_state[7] = 0;
2652 }
2653
2654 return &view->base;
2655 }
2656
2657 static struct pipe_sampler_view *
2658 si_create_sampler_view(struct pipe_context *ctx,
2659 struct pipe_resource *texture,
2660 const struct pipe_sampler_view *state)
2661 {
2662 return si_create_sampler_view_custom(ctx, texture, state,
2663 texture ? texture->width0 : 0,
2664 texture ? texture->height0 : 0, 0);
2665 }
2666
2667 static void si_sampler_view_destroy(struct pipe_context *ctx,
2668 struct pipe_sampler_view *state)
2669 {
2670 struct si_sampler_view *view = (struct si_sampler_view *)state;
2671
2672 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2673 LIST_DELINIT(&view->list);
2674
2675 pipe_resource_reference(&state->texture, NULL);
2676 FREE(view);
2677 }
2678
2679 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2680 {
2681 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2682 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2683 (linear_filter &&
2684 (wrap == PIPE_TEX_WRAP_CLAMP ||
2685 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2686 }
2687
2688 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2689 {
2690 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2691 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2692
2693 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2694 state->border_color.ui[2] || state->border_color.ui[3]) &&
2695 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2696 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2697 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2698 }
2699
2700 static void *si_create_sampler_state(struct pipe_context *ctx,
2701 const struct pipe_sampler_state *state)
2702 {
2703 struct si_context *sctx = (struct si_context *)ctx;
2704 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2705 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2706 unsigned border_color_type, border_color_index = 0;
2707
2708 if (rstate == NULL) {
2709 return NULL;
2710 }
2711
2712 if (!sampler_state_needs_border_color(state))
2713 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2714 else if (state->border_color.f[0] == 0 &&
2715 state->border_color.f[1] == 0 &&
2716 state->border_color.f[2] == 0 &&
2717 state->border_color.f[3] == 0)
2718 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2719 else if (state->border_color.f[0] == 0 &&
2720 state->border_color.f[1] == 0 &&
2721 state->border_color.f[2] == 0 &&
2722 state->border_color.f[3] == 1)
2723 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2724 else if (state->border_color.f[0] == 1 &&
2725 state->border_color.f[1] == 1 &&
2726 state->border_color.f[2] == 1 &&
2727 state->border_color.f[3] == 1)
2728 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2729 else {
2730 int i;
2731
2732 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2733
2734 /* Check if the border has been uploaded already. */
2735 for (i = 0; i < sctx->border_color_count; i++)
2736 if (memcmp(&sctx->border_color_table[i], &state->border_color,
2737 sizeof(state->border_color)) == 0)
2738 break;
2739
2740 if (i >= SI_MAX_BORDER_COLORS) {
2741 /* Getting 4096 unique border colors is very unlikely. */
2742 fprintf(stderr, "radeonsi: The border color table is full. "
2743 "Any new border colors will be just black. "
2744 "Please file a bug.\n");
2745 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2746 } else {
2747 if (i == sctx->border_color_count) {
2748 /* Upload a new border color. */
2749 memcpy(&sctx->border_color_table[i], &state->border_color,
2750 sizeof(state->border_color));
2751 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
2752 &state->border_color,
2753 sizeof(state->border_color));
2754 sctx->border_color_count++;
2755 }
2756
2757 border_color_index = i;
2758 }
2759 }
2760
2761 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2762 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2763 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2764 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2765 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2766 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2767 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2768 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2769 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2770 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2771 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2772 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2773 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2774 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
2775 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2776 return rstate;
2777 }
2778
2779 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2780 {
2781 struct si_context *sctx = (struct si_context *)ctx;
2782
2783 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2784 return;
2785
2786 sctx->sample_mask.sample_mask = sample_mask;
2787 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2788 }
2789
2790 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2791 {
2792 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2793 unsigned mask = sctx->sample_mask.sample_mask;
2794
2795 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2796 radeon_emit(cs, mask | (mask << 16));
2797 radeon_emit(cs, mask | (mask << 16));
2798 }
2799
2800 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2801 {
2802 free(state);
2803 }
2804
2805 /*
2806 * Vertex elements & buffers
2807 */
2808
2809 static void *si_create_vertex_elements(struct pipe_context *ctx,
2810 unsigned count,
2811 const struct pipe_vertex_element *elements)
2812 {
2813 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2814 int i;
2815
2816 assert(count < SI_MAX_ATTRIBS);
2817 if (!v)
2818 return NULL;
2819
2820 v->count = count;
2821 for (i = 0; i < count; ++i) {
2822 const struct util_format_description *desc;
2823 unsigned data_format, num_format;
2824 int first_non_void;
2825
2826 desc = util_format_description(elements[i].src_format);
2827 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2828 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2829 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2830
2831 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2832 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2833 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2834 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2835 S_008F0C_NUM_FORMAT(num_format) |
2836 S_008F0C_DATA_FORMAT(data_format);
2837 v->format_size[i] = desc->block.bits / 8;
2838 }
2839 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2840
2841 return v;
2842 }
2843
2844 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2845 {
2846 struct si_context *sctx = (struct si_context *)ctx;
2847 struct si_vertex_element *v = (struct si_vertex_element*)state;
2848
2849 sctx->vertex_elements = v;
2850 sctx->vertex_buffers_dirty = true;
2851 }
2852
2853 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2854 {
2855 struct si_context *sctx = (struct si_context *)ctx;
2856
2857 if (sctx->vertex_elements == state)
2858 sctx->vertex_elements = NULL;
2859 FREE(state);
2860 }
2861
2862 static void si_set_vertex_buffers(struct pipe_context *ctx,
2863 unsigned start_slot, unsigned count,
2864 const struct pipe_vertex_buffer *buffers)
2865 {
2866 struct si_context *sctx = (struct si_context *)ctx;
2867 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2868 int i;
2869
2870 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2871
2872 if (buffers) {
2873 for (i = 0; i < count; i++) {
2874 const struct pipe_vertex_buffer *src = buffers + i;
2875 struct pipe_vertex_buffer *dsti = dst + i;
2876
2877 pipe_resource_reference(&dsti->buffer, src->buffer);
2878 dsti->buffer_offset = src->buffer_offset;
2879 dsti->stride = src->stride;
2880 r600_context_add_resource_size(ctx, src->buffer);
2881 }
2882 } else {
2883 for (i = 0; i < count; i++) {
2884 pipe_resource_reference(&dst[i].buffer, NULL);
2885 }
2886 }
2887 sctx->vertex_buffers_dirty = true;
2888 }
2889
2890 static void si_set_index_buffer(struct pipe_context *ctx,
2891 const struct pipe_index_buffer *ib)
2892 {
2893 struct si_context *sctx = (struct si_context *)ctx;
2894
2895 if (ib) {
2896 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2897 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2898 r600_context_add_resource_size(ctx, ib->buffer);
2899 } else {
2900 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2901 }
2902 }
2903
2904 /*
2905 * Misc
2906 */
2907 static void si_set_polygon_stipple(struct pipe_context *ctx,
2908 const struct pipe_poly_stipple *state)
2909 {
2910 struct si_context *sctx = (struct si_context *)ctx;
2911 struct pipe_resource *tex;
2912 struct pipe_sampler_view *view;
2913 bool is_zero = true;
2914 bool is_one = true;
2915 int i;
2916
2917 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2918 * the resource is NULL/invalid. Take advantage of this fact and skip
2919 * texture allocation if the stipple pattern is constant.
2920 *
2921 * This is an optimization for the common case when stippling isn't
2922 * used but set_polygon_stipple is still called by st/mesa.
2923 */
2924 for (i = 0; i < Elements(state->stipple); i++) {
2925 is_zero = is_zero && state->stipple[i] == 0;
2926 is_one = is_one && state->stipple[i] == 0xffffffff;
2927 }
2928
2929 if (is_zero || is_one) {
2930 struct pipe_sampler_view templ = {{0}};
2931
2932 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2933 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2934 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2935 /* The pattern should be inverted in the texture. */
2936 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2937
2938 view = ctx->create_sampler_view(ctx, NULL, &templ);
2939 } else {
2940 /* Create a new texture. */
2941 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2942 if (!tex)
2943 return;
2944
2945 view = util_pstipple_create_sampler_view(ctx, tex);
2946 pipe_resource_reference(&tex, NULL);
2947 }
2948
2949 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2950 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2951 pipe_sampler_view_reference(&view, NULL);
2952
2953 /* Bind the sampler state if needed. */
2954 if (!sctx->pstipple_sampler_state) {
2955 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2956 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2957 SI_POLY_STIPPLE_SAMPLER, 1,
2958 &sctx->pstipple_sampler_state);
2959 }
2960 }
2961
2962 static void si_set_tess_state(struct pipe_context *ctx,
2963 const float default_outer_level[4],
2964 const float default_inner_level[2])
2965 {
2966 struct si_context *sctx = (struct si_context *)ctx;
2967 struct pipe_constant_buffer cb;
2968 float array[8];
2969
2970 memcpy(array, default_outer_level, sizeof(float) * 4);
2971 memcpy(array+4, default_inner_level, sizeof(float) * 2);
2972
2973 cb.buffer = NULL;
2974 cb.user_buffer = NULL;
2975 cb.buffer_size = sizeof(array);
2976
2977 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
2978 (void*)array, sizeof(array),
2979 &cb.buffer_offset);
2980
2981 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
2982 SI_DRIVER_STATE_CONST_BUF, &cb);
2983 pipe_resource_reference(&cb.buffer, NULL);
2984 }
2985
2986 static void si_texture_barrier(struct pipe_context *ctx)
2987 {
2988 struct si_context *sctx = (struct si_context *)ctx;
2989
2990 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2991 SI_CONTEXT_INV_TC_L2 |
2992 SI_CONTEXT_FLUSH_AND_INV_CB;
2993 }
2994
2995 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2996 {
2997 struct pipe_blend_state blend;
2998
2999 memset(&blend, 0, sizeof(blend));
3000 blend.independent_blend_enable = true;
3001 blend.rt[0].colormask = 0xf;
3002 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3003 }
3004
3005 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3006 bool include_draw_vbo)
3007 {
3008 si_need_cs_space((struct si_context*)ctx);
3009 }
3010
3011 static void si_init_config(struct si_context *sctx);
3012
3013 void si_init_state_functions(struct si_context *sctx)
3014 {
3015 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3016 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3017
3018 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3019 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3020 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3021 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3022 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3023 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3024 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3025 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3026 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3027 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3028 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3029 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3030 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3031
3032 sctx->b.b.create_blend_state = si_create_blend_state;
3033 sctx->b.b.bind_blend_state = si_bind_blend_state;
3034 sctx->b.b.delete_blend_state = si_delete_blend_state;
3035 sctx->b.b.set_blend_color = si_set_blend_color;
3036
3037 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3038 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3039 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3040
3041 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3042 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3043 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3044
3045 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3046 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3047 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3048 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3049
3050 sctx->b.b.set_clip_state = si_set_clip_state;
3051 sctx->b.b.set_scissor_states = si_set_scissor_states;
3052 sctx->b.b.set_viewport_states = si_set_viewport_states;
3053 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3054
3055 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3056 sctx->b.b.get_sample_position = cayman_get_sample_position;
3057
3058 sctx->b.b.create_sampler_state = si_create_sampler_state;
3059 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3060
3061 sctx->b.b.create_sampler_view = si_create_sampler_view;
3062 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3063
3064 sctx->b.b.set_sample_mask = si_set_sample_mask;
3065
3066 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3067 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3068 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3069 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3070 sctx->b.b.set_index_buffer = si_set_index_buffer;
3071
3072 sctx->b.b.texture_barrier = si_texture_barrier;
3073 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3074 sctx->b.b.set_min_samples = si_set_min_samples;
3075 sctx->b.b.set_tess_state = si_set_tess_state;
3076
3077 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3078 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3079
3080 sctx->b.b.draw_vbo = si_draw_vbo;
3081
3082 if (sctx->b.chip_class >= CIK) {
3083 sctx->b.dma_copy = cik_sdma_copy;
3084 } else {
3085 sctx->b.dma_copy = si_dma_copy;
3086 }
3087
3088 si_init_config(sctx);
3089 }
3090
3091 static void
3092 si_write_harvested_raster_configs(struct si_context *sctx,
3093 struct si_pm4_state *pm4,
3094 unsigned raster_config,
3095 unsigned raster_config_1)
3096 {
3097 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3098 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3099 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3100 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3101 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3102 unsigned rb_per_se = num_rb / num_se;
3103 unsigned se_mask[4];
3104 unsigned se;
3105
3106 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3107 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3108 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3109 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3110
3111 assert(num_se == 1 || num_se == 2 || num_se == 4);
3112 assert(sh_per_se == 1 || sh_per_se == 2);
3113 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3114
3115 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3116 * fields are for, so I'm leaving them as their default
3117 * values. */
3118
3119 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3120 (!se_mask[2] && !se_mask[3]))) {
3121 raster_config_1 &= C_028354_SE_PAIR_MAP;
3122
3123 if (!se_mask[0] && !se_mask[1]) {
3124 raster_config_1 |=
3125 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3126 } else {
3127 raster_config_1 |=
3128 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3129 }
3130 }
3131
3132 for (se = 0; se < num_se; se++) {
3133 unsigned raster_config_se = raster_config;
3134 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3135 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3136 int idx = (se / 2) * 2;
3137
3138 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3139 raster_config_se &= C_028350_SE_MAP;
3140
3141 if (!se_mask[idx]) {
3142 raster_config_se |=
3143 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3144 } else {
3145 raster_config_se |=
3146 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3147 }
3148 }
3149
3150 pkr0_mask &= rb_mask;
3151 pkr1_mask &= rb_mask;
3152 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3153 raster_config_se &= C_028350_PKR_MAP;
3154
3155 if (!pkr0_mask) {
3156 raster_config_se |=
3157 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3158 } else {
3159 raster_config_se |=
3160 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3161 }
3162 }
3163
3164 if (rb_per_se >= 2) {
3165 unsigned rb0_mask = 1 << (se * rb_per_se);
3166 unsigned rb1_mask = rb0_mask << 1;
3167
3168 rb0_mask &= rb_mask;
3169 rb1_mask &= rb_mask;
3170 if (!rb0_mask || !rb1_mask) {
3171 raster_config_se &= C_028350_RB_MAP_PKR0;
3172
3173 if (!rb0_mask) {
3174 raster_config_se |=
3175 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3176 } else {
3177 raster_config_se |=
3178 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3179 }
3180 }
3181
3182 if (rb_per_se > 2) {
3183 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3184 rb1_mask = rb0_mask << 1;
3185 rb0_mask &= rb_mask;
3186 rb1_mask &= rb_mask;
3187 if (!rb0_mask || !rb1_mask) {
3188 raster_config_se &= C_028350_RB_MAP_PKR1;
3189
3190 if (!rb0_mask) {
3191 raster_config_se |=
3192 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3193 } else {
3194 raster_config_se |=
3195 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3196 }
3197 }
3198 }
3199 }
3200
3201 /* GRBM_GFX_INDEX is privileged on VI */
3202 if (sctx->b.chip_class <= CIK)
3203 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3204 SE_INDEX(se) | SH_BROADCAST_WRITES |
3205 INSTANCE_BROADCAST_WRITES);
3206 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3207 if (sctx->b.chip_class >= CIK)
3208 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3209 }
3210
3211 /* GRBM_GFX_INDEX is privileged on VI */
3212 if (sctx->b.chip_class <= CIK)
3213 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3214 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3215 INSTANCE_BROADCAST_WRITES);
3216 }
3217
3218 static void si_init_config(struct si_context *sctx)
3219 {
3220 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3221 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3222 unsigned raster_config, raster_config_1;
3223 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3224 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3225 int i;
3226
3227 if (pm4 == NULL)
3228 return;
3229
3230 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3231 si_pm4_cmd_add(pm4, 0x80000000);
3232 si_pm4_cmd_add(pm4, 0x80000000);
3233 si_pm4_cmd_end(pm4, false);
3234
3235 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3236 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3237
3238 /* FIXME calculate these values somehow ??? */
3239 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3240 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3241 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3242
3243 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3244 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3245
3246 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3247 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3248 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3249 if (sctx->b.chip_class < CIK)
3250 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3251 S_008A14_CLIP_VTX_REORDER_ENA(1));
3252
3253 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3254 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3255
3256 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3257
3258 for (i = 0; i < 16; i++) {
3259 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3260 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3261 }
3262
3263 switch (sctx->screen->b.family) {
3264 case CHIP_TAHITI:
3265 case CHIP_PITCAIRN:
3266 raster_config = 0x2a00126a;
3267 raster_config_1 = 0x00000000;
3268 break;
3269 case CHIP_VERDE:
3270 raster_config = 0x0000124a;
3271 raster_config_1 = 0x00000000;
3272 break;
3273 case CHIP_OLAND:
3274 raster_config = 0x00000082;
3275 raster_config_1 = 0x00000000;
3276 break;
3277 case CHIP_HAINAN:
3278 raster_config = 0x00000000;
3279 raster_config_1 = 0x00000000;
3280 break;
3281 case CHIP_BONAIRE:
3282 raster_config = 0x16000012;
3283 raster_config_1 = 0x00000000;
3284 break;
3285 case CHIP_HAWAII:
3286 raster_config = 0x3a00161a;
3287 raster_config_1 = 0x0000002e;
3288 break;
3289 case CHIP_FIJI:
3290 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3291 raster_config = 0x16000012; /* 0x3a00161a */
3292 raster_config_1 = 0x0000002a; /* 0x0000002e */
3293 break;
3294 case CHIP_TONGA:
3295 raster_config = 0x16000012;
3296 raster_config_1 = 0x0000002a;
3297 break;
3298 case CHIP_ICELAND:
3299 raster_config = 0x00000002;
3300 raster_config_1 = 0x00000000;
3301 break;
3302 case CHIP_CARRIZO:
3303 raster_config = 0x00000002;
3304 raster_config_1 = 0x00000000;
3305 break;
3306 case CHIP_KAVERI:
3307 /* KV should be 0x00000002, but that causes problems with radeon */
3308 raster_config = 0x00000000; /* 0x00000002 */
3309 raster_config_1 = 0x00000000;
3310 break;
3311 case CHIP_KABINI:
3312 case CHIP_MULLINS:
3313 raster_config = 0x00000000;
3314 raster_config_1 = 0x00000000;
3315 break;
3316 default:
3317 fprintf(stderr,
3318 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3319 raster_config = 0x00000000;
3320 raster_config_1 = 0x00000000;
3321 break;
3322 }
3323
3324 /* Always use the default config when all backends are enabled
3325 * (or when we failed to determine the enabled backends).
3326 */
3327 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3328 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3329 raster_config);
3330 if (sctx->b.chip_class >= CIK)
3331 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3332 raster_config_1);
3333 } else {
3334 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3335 }
3336
3337 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3338 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3339 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3340 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3341 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3342 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3343 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3344
3345 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3346 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3347 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3348 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3349 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3350 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3351 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3352 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3353 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3354 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3355 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3356 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3357 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3358
3359 /* There is a hang if stencil is used and fast stencil is enabled
3360 * regardless of whether HTILE is depth-only or not.
3361 */
3362 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3363 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3364 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3365 S_02800C_FAST_STENCIL_DISABLE(1));
3366
3367 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3368 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3369 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3370
3371 if (sctx->b.chip_class >= CIK) {
3372 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3373 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3374 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3375 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3376 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3377 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3378 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3379 }
3380
3381 if (sctx->b.chip_class >= VI) {
3382 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3383 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3384 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3385 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3386 }
3387
3388 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3389 if (sctx->b.chip_class >= CIK)
3390 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3391 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3392 RADEON_PRIO_SHADER_DATA);
3393
3394 si_pm4_upload_indirect_buffer(sctx, pm4);
3395 sctx->init_config = pm4;
3396 }