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radeonsi: fix UINT/SINT clamping for 10-bit formats on <= CIK
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37 #include "util/u_upload_mgr.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array;
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
92 * if there is not enough PS outputs.
93 */
94 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
95 {
96 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
97 struct si_state_blend *blend = sctx->queued.named.blend;
98 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
99 * but you never know. */
100 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
101 unsigned i;
102
103 if (blend)
104 cb_target_mask &= blend->cb_target_mask;
105
106 /* Avoid a hang that happens when dual source blending is enabled
107 * but there is not enough color outputs. This is undefined behavior,
108 * so disable color writes completely.
109 *
110 * Reproducible with Unigine Heaven 4.0 and drirc missing.
111 */
112 if (blend && blend->dual_src_blend &&
113 sctx->ps_shader.cso &&
114 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
115 cb_target_mask = 0;
116
117 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
118
119 /* STONEY-specific register settings. */
120 if (sctx->b.family == CHIP_STONEY) {
121 unsigned spi_shader_col_format =
122 sctx->ps_shader.cso ?
123 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
124 unsigned sx_ps_downconvert = 0;
125 unsigned sx_blend_opt_epsilon = 0;
126 unsigned sx_blend_opt_control = 0;
127
128 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
129 struct r600_surface *surf =
130 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
131 unsigned format, swap, spi_format, colormask;
132 bool has_alpha, has_rgb;
133
134 if (!surf)
135 continue;
136
137 format = G_028C70_FORMAT(surf->cb_color_info);
138 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
139 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
140 colormask = (cb_target_mask >> (i * 4)) & 0xf;
141
142 /* Set if RGB and A are present. */
143 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
144
145 if (format == V_028C70_COLOR_8 ||
146 format == V_028C70_COLOR_16 ||
147 format == V_028C70_COLOR_32)
148 has_rgb = !has_alpha;
149 else
150 has_rgb = true;
151
152 /* Check the colormask and export format. */
153 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
154 has_rgb = false;
155 if (!(colormask & PIPE_MASK_A))
156 has_alpha = false;
157
158 if (spi_format == V_028714_SPI_SHADER_ZERO) {
159 has_rgb = false;
160 has_alpha = false;
161 }
162
163 /* Disable value checking for disabled channels. */
164 if (!has_rgb)
165 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
166 if (!has_alpha)
167 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
168
169 /* Enable down-conversion for 32bpp and smaller formats. */
170 switch (format) {
171 case V_028C70_COLOR_8:
172 case V_028C70_COLOR_8_8:
173 case V_028C70_COLOR_8_8_8_8:
174 /* For 1 and 2-channel formats, use the superset thereof. */
175 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
178 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
179 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
180 }
181 break;
182
183 case V_028C70_COLOR_5_6_5:
184 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_1_5_5_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_4_4_4_4:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_32:
205 if (swap == V_0280A0_SWAP_STD &&
206 spi_format == V_028714_SPI_SHADER_32_R)
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
208 else if (swap == V_0280A0_SWAP_ALT_REV &&
209 spi_format == V_028714_SPI_SHADER_32_AR)
210 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
211 break;
212
213 case V_028C70_COLOR_16:
214 case V_028C70_COLOR_16_16:
215 /* For 1-channel formats, use the superset thereof. */
216 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
220 if (swap == V_0280A0_SWAP_STD ||
221 swap == V_0280A0_SWAP_STD_REV)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
223 else
224 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
225 }
226 break;
227
228 case V_028C70_COLOR_10_11_11:
229 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
231 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_2_10_10_10:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
239 }
240 break;
241 }
242 }
243
244 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
245 sx_ps_downconvert = 0;
246 sx_blend_opt_epsilon = 0;
247 sx_blend_opt_control = 0;
248 }
249
250 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
251 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
252 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
253 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
254 }
255 }
256
257 /*
258 * Blender functions
259 */
260
261 static uint32_t si_translate_blend_function(int blend_func)
262 {
263 switch (blend_func) {
264 case PIPE_BLEND_ADD:
265 return V_028780_COMB_DST_PLUS_SRC;
266 case PIPE_BLEND_SUBTRACT:
267 return V_028780_COMB_SRC_MINUS_DST;
268 case PIPE_BLEND_REVERSE_SUBTRACT:
269 return V_028780_COMB_DST_MINUS_SRC;
270 case PIPE_BLEND_MIN:
271 return V_028780_COMB_MIN_DST_SRC;
272 case PIPE_BLEND_MAX:
273 return V_028780_COMB_MAX_DST_SRC;
274 default:
275 R600_ERR("Unknown blend function %d\n", blend_func);
276 assert(0);
277 break;
278 }
279 return 0;
280 }
281
282 static uint32_t si_translate_blend_factor(int blend_fact)
283 {
284 switch (blend_fact) {
285 case PIPE_BLENDFACTOR_ONE:
286 return V_028780_BLEND_ONE;
287 case PIPE_BLENDFACTOR_SRC_COLOR:
288 return V_028780_BLEND_SRC_COLOR;
289 case PIPE_BLENDFACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case PIPE_BLENDFACTOR_DST_ALPHA:
292 return V_028780_BLEND_DST_ALPHA;
293 case PIPE_BLENDFACTOR_DST_COLOR:
294 return V_028780_BLEND_DST_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE;
297 case PIPE_BLENDFACTOR_CONST_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_CONST_ALPHA:
300 return V_028780_BLEND_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_ZERO:
302 return V_028780_BLEND_ZERO;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_SRC1_COLOR:
316 return V_028780_BLEND_SRC1_COLOR;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA:
318 return V_028780_BLEND_SRC1_ALPHA;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
322 return V_028780_BLEND_INV_SRC1_ALPHA;
323 default:
324 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
325 assert(0);
326 break;
327 }
328 return 0;
329 }
330
331 static uint32_t si_translate_blend_opt_function(int blend_func)
332 {
333 switch (blend_func) {
334 case PIPE_BLEND_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case PIPE_BLEND_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case PIPE_BLEND_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case PIPE_BLEND_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case PIPE_BLEND_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
350 {
351 switch (blend_fact) {
352 case PIPE_BLENDFACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case PIPE_BLENDFACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case PIPE_BLENDFACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case PIPE_BLENDFACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 /**
375 * Get rid of DST in the blend factors by commuting the operands:
376 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 */
378 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
379 unsigned *dst_factor, unsigned expected_dst,
380 unsigned replacement_src)
381 {
382 if (*src_factor == expected_dst &&
383 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
384 *src_factor = PIPE_BLENDFACTOR_ZERO;
385 *dst_factor = replacement_src;
386
387 /* Commuting the operands requires reversing subtractions. */
388 if (*func == PIPE_BLEND_SUBTRACT)
389 *func = PIPE_BLEND_REVERSE_SUBTRACT;
390 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
391 *func = PIPE_BLEND_SUBTRACT;
392 }
393 }
394
395 static bool si_blend_factor_uses_dst(unsigned factor)
396 {
397 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
398 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
399 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
400 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
401 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
402 }
403
404 static void *si_create_blend_state_mode(struct pipe_context *ctx,
405 const struct pipe_blend_state *state,
406 unsigned mode)
407 {
408 struct si_context *sctx = (struct si_context*)ctx;
409 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
410 struct si_pm4_state *pm4 = &blend->pm4;
411 uint32_t sx_mrt_blend_opt[8] = {0};
412 uint32_t color_control = 0;
413
414 if (!blend)
415 return NULL;
416
417 blend->alpha_to_coverage = state->alpha_to_coverage;
418 blend->alpha_to_one = state->alpha_to_one;
419 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
420
421 if (state->logicop_enable) {
422 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
423 } else {
424 color_control |= S_028808_ROP3(0xcc);
425 }
426
427 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
428 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
429 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
432 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433
434 if (state->alpha_to_coverage)
435 blend->need_src_alpha_4bit |= 0xf;
436
437 blend->cb_target_mask = 0;
438 for (int i = 0; i < 8; i++) {
439 /* state->rt entries > 0 only written if independent blending */
440 const int j = state->independent_blend_enable ? i : 0;
441
442 unsigned eqRGB = state->rt[j].rgb_func;
443 unsigned srcRGB = state->rt[j].rgb_src_factor;
444 unsigned dstRGB = state->rt[j].rgb_dst_factor;
445 unsigned eqA = state->rt[j].alpha_func;
446 unsigned srcA = state->rt[j].alpha_src_factor;
447 unsigned dstA = state->rt[j].alpha_dst_factor;
448
449 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
450 unsigned blend_cntl = 0;
451
452 sx_mrt_blend_opt[i] =
453 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
454 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
455
456 /* Only set dual source blending for MRT0 to avoid a hang. */
457 if (i >= 1 && blend->dual_src_blend) {
458 /* Vulkan does this for dual source blending. */
459 if (i == 1)
460 blend_cntl |= S_028780_ENABLE(1);
461
462 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
463 continue;
464 }
465
466 /* Only addition and subtraction equations are supported with
467 * dual source blending.
468 */
469 if (blend->dual_src_blend &&
470 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
471 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
472 assert(!"Unsupported equation for dual source blending");
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* cb_render_state will disable unused ones */
478 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
479
480 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
481 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
482 continue;
483 }
484
485 /* Blending optimizations for Stoney.
486 * These transformations don't change the behavior.
487 *
488 * First, get rid of DST in the blend factors:
489 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
490 */
491 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
492 PIPE_BLENDFACTOR_DST_COLOR,
493 PIPE_BLENDFACTOR_SRC_COLOR);
494 si_blend_remove_dst(&eqA, &srcA, &dstA,
495 PIPE_BLENDFACTOR_DST_COLOR,
496 PIPE_BLENDFACTOR_SRC_COLOR);
497 si_blend_remove_dst(&eqA, &srcA, &dstA,
498 PIPE_BLENDFACTOR_DST_ALPHA,
499 PIPE_BLENDFACTOR_SRC_ALPHA);
500
501 /* Look up the ideal settings from tables. */
502 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
503 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
504 srcA_opt = si_translate_blend_opt_factor(srcA, true);
505 dstA_opt = si_translate_blend_opt_factor(dstA, true);
506
507 /* Handle interdependencies. */
508 if (si_blend_factor_uses_dst(srcRGB))
509 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
510 if (si_blend_factor_uses_dst(srcA))
511 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
512
513 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
514 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
516 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
517 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
518
519 /* Set the final value. */
520 sx_mrt_blend_opt[i] =
521 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
522 S_028760_COLOR_DST_OPT(dstRGB_opt) |
523 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
524 S_028760_ALPHA_SRC_OPT(srcA_opt) |
525 S_028760_ALPHA_DST_OPT(dstA_opt) |
526 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
527
528 /* Set blend state. */
529 blend_cntl |= S_028780_ENABLE(1);
530 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
531 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
532 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
533
534 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
535 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
536 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
537 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
538 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
539 }
540 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
541
542 blend->blend_enable_4bit |= 0xfu << (i * 4);
543
544 /* This is only important for formats without alpha. */
545 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
547 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
549 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
550 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
551 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
552 }
553
554 if (blend->cb_target_mask) {
555 color_control |= S_028808_MODE(mode);
556 } else {
557 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
558 }
559
560 if (sctx->b.family == CHIP_STONEY) {
561 /* Disable RB+ blend optimizations for dual source blending.
562 * Vulkan does this.
563 */
564 if (blend->dual_src_blend) {
565 for (int i = 0; i < 8; i++) {
566 sx_mrt_blend_opt[i] =
567 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
568 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
569 }
570 }
571
572 for (int i = 0; i < 8; i++)
573 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
574 sx_mrt_blend_opt[i]);
575
576 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
577 if (blend->dual_src_blend || state->logicop_enable ||
578 mode == V_028808_CB_RESOLVE)
579 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
580 }
581
582 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
583 return blend;
584 }
585
586 static void *si_create_blend_state(struct pipe_context *ctx,
587 const struct pipe_blend_state *state)
588 {
589 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
590 }
591
592 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
593 {
594 struct si_context *sctx = (struct si_context *)ctx;
595 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
596 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
597 sctx->do_update_shaders = true;
598 }
599
600 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
601 {
602 struct si_context *sctx = (struct si_context *)ctx;
603 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
604 }
605
606 static void si_set_blend_color(struct pipe_context *ctx,
607 const struct pipe_blend_color *state)
608 {
609 struct si_context *sctx = (struct si_context *)ctx;
610
611 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
612 return;
613
614 sctx->blend_color.state = *state;
615 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
616 }
617
618 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
619 {
620 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
621
622 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
623 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
624 }
625
626 /*
627 * Clipping
628 */
629
630 static void si_set_clip_state(struct pipe_context *ctx,
631 const struct pipe_clip_state *state)
632 {
633 struct si_context *sctx = (struct si_context *)ctx;
634 struct pipe_constant_buffer cb;
635
636 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
637 return;
638
639 sctx->clip_state.state = *state;
640 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
641
642 cb.buffer = NULL;
643 cb.user_buffer = state->ucp;
644 cb.buffer_offset = 0;
645 cb.buffer_size = 4*4*8;
646 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
647 pipe_resource_reference(&cb.buffer, NULL);
648 }
649
650 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
651 {
652 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
653
654 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
655 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
656 }
657
658 #define SIX_BITS 0x3F
659
660 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
661 {
662 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
663 struct si_shader *vs = si_get_vs_state(sctx);
664 struct tgsi_shader_info *info = si_get_vs_info(sctx);
665 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
666 unsigned window_space =
667 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
668 unsigned clipdist_mask =
669 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
670 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
671 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
672 unsigned total_mask;
673 bool misc_vec_ena;
674
675 if (vs->key.opt.hw_vs.clip_disable) {
676 assert(!info->culldist_writemask);
677 clipdist_mask = 0;
678 culldist_mask = 0;
679 }
680 total_mask = clipdist_mask | culldist_mask;
681
682 /* Clip distances on points have no effect, so need to be implemented
683 * as cull distances. This applies for the clipvertex case as well.
684 *
685 * Setting this for primitives other than points should have no adverse
686 * effects.
687 */
688 clipdist_mask &= rs->clip_plane_enable;
689 culldist_mask |= clipdist_mask;
690
691 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
692 info->writes_layer || info->writes_viewport_index;
693
694 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
695 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
696 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
697 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
698 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
699 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
700 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
701 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
702 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
703 clipdist_mask | (culldist_mask << 8));
704 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
705 rs->pa_cl_clip_cntl |
706 ucp_mask |
707 S_028810_CLIP_DISABLE(window_space));
708
709 /* reuse needs to be set off if we write oViewport */
710 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
711 S_028AB4_REUSE_OFF(info->writes_viewport_index));
712 }
713
714 /*
715 * inferred state between framebuffer and rasterizer
716 */
717 static void si_update_poly_offset_state(struct si_context *sctx)
718 {
719 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
720
721 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
722 si_pm4_bind_state(sctx, poly_offset, NULL);
723 return;
724 }
725
726 /* Use the user format, not db_render_format, so that the polygon
727 * offset behaves as expected by applications.
728 */
729 switch (sctx->framebuffer.state.zsbuf->texture->format) {
730 case PIPE_FORMAT_Z16_UNORM:
731 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
732 break;
733 default: /* 24-bit */
734 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
735 break;
736 case PIPE_FORMAT_Z32_FLOAT:
737 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
738 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
739 break;
740 }
741 }
742
743 /*
744 * Rasterizer
745 */
746
747 static uint32_t si_translate_fill(uint32_t func)
748 {
749 switch(func) {
750 case PIPE_POLYGON_MODE_FILL:
751 return V_028814_X_DRAW_TRIANGLES;
752 case PIPE_POLYGON_MODE_LINE:
753 return V_028814_X_DRAW_LINES;
754 case PIPE_POLYGON_MODE_POINT:
755 return V_028814_X_DRAW_POINTS;
756 default:
757 assert(0);
758 return V_028814_X_DRAW_POINTS;
759 }
760 }
761
762 static void *si_create_rs_state(struct pipe_context *ctx,
763 const struct pipe_rasterizer_state *state)
764 {
765 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
766 struct si_pm4_state *pm4 = &rs->pm4;
767 unsigned tmp, i;
768 float psize_min, psize_max;
769
770 if (!rs) {
771 return NULL;
772 }
773
774 rs->scissor_enable = state->scissor;
775 rs->clip_halfz = state->clip_halfz;
776 rs->two_side = state->light_twoside;
777 rs->multisample_enable = state->multisample;
778 rs->force_persample_interp = state->force_persample_interp;
779 rs->clip_plane_enable = state->clip_plane_enable;
780 rs->line_stipple_enable = state->line_stipple_enable;
781 rs->poly_stipple_enable = state->poly_stipple_enable;
782 rs->line_smooth = state->line_smooth;
783 rs->poly_smooth = state->poly_smooth;
784 rs->uses_poly_offset = state->offset_point || state->offset_line ||
785 state->offset_tri;
786 rs->clamp_fragment_color = state->clamp_fragment_color;
787 rs->flatshade = state->flatshade;
788 rs->sprite_coord_enable = state->sprite_coord_enable;
789 rs->rasterizer_discard = state->rasterizer_discard;
790 rs->pa_sc_line_stipple = state->line_stipple_enable ?
791 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
792 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
793 rs->pa_cl_clip_cntl =
794 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
795 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
796 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
797 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
798 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
799
800 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
801 S_0286D4_FLAT_SHADE_ENA(1) |
802 S_0286D4_PNT_SPRITE_ENA(1) |
803 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
804 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
805 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
806 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
807 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
808
809 /* point size 12.4 fixed point */
810 tmp = (unsigned)(state->point_size * 8.0);
811 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
812
813 if (state->point_size_per_vertex) {
814 psize_min = util_get_min_point_size(state);
815 psize_max = 8192;
816 } else {
817 /* Force the point size to be as if the vertex output was disabled. */
818 psize_min = state->point_size;
819 psize_max = state->point_size;
820 }
821 /* Divide by two, because 0.5 = 1 pixel. */
822 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
823 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
824 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
825
826 tmp = (unsigned)state->line_width * 8;
827 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
828 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
829 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
830 S_028A48_MSAA_ENABLE(state->multisample ||
831 state->poly_smooth ||
832 state->line_smooth) |
833 S_028A48_VPORT_SCISSOR_ENABLE(1));
834
835 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
836 S_028BE4_PIX_CENTER(state->half_pixel_center) |
837 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
838
839 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
840 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
841 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
842 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
843 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
844 S_028814_FACE(!state->front_ccw) |
845 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
846 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
847 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
848 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
849 state->fill_back != PIPE_POLYGON_MODE_FILL) |
850 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
851 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
852 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
853 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
854
855 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
856 for (i = 0; i < 3; i++) {
857 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
858 float offset_units = state->offset_units;
859 float offset_scale = state->offset_scale * 16.0f;
860 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
861
862 if (!state->offset_units_unscaled) {
863 switch (i) {
864 case 0: /* 16-bit zbuffer */
865 offset_units *= 4.0f;
866 pa_su_poly_offset_db_fmt_cntl =
867 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
868 break;
869 case 1: /* 24-bit zbuffer */
870 offset_units *= 2.0f;
871 pa_su_poly_offset_db_fmt_cntl =
872 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
873 break;
874 case 2: /* 32-bit zbuffer */
875 offset_units *= 1.0f;
876 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
877 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
878 break;
879 }
880 }
881
882 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
883 fui(offset_scale));
884 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
885 fui(offset_units));
886 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
887 fui(offset_scale));
888 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
889 fui(offset_units));
890 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
891 pa_su_poly_offset_db_fmt_cntl);
892 }
893
894 return rs;
895 }
896
897 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
898 {
899 struct si_context *sctx = (struct si_context *)ctx;
900 struct si_state_rasterizer *old_rs =
901 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
902 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
903
904 if (!state)
905 return;
906
907 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
908 si_mark_atom_dirty(sctx, &sctx->db_render_state);
909
910 /* Update the small primitive filter workaround if necessary. */
911 if (sctx->b.family >= CHIP_POLARIS10 &&
912 sctx->framebuffer.nr_samples > 1)
913 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
914 }
915
916 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
917
918 si_pm4_bind_state(sctx, rasterizer, rs);
919 si_update_poly_offset_state(sctx);
920
921 si_mark_atom_dirty(sctx, &sctx->clip_regs);
922 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
923 rs->line_stipple_enable;
924 sctx->do_update_shaders = true;
925 }
926
927 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
928 {
929 struct si_context *sctx = (struct si_context *)ctx;
930
931 if (sctx->queued.named.rasterizer == state)
932 si_pm4_bind_state(sctx, poly_offset, NULL);
933 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
934 }
935
936 /*
937 * infeered state between dsa and stencil ref
938 */
939 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
940 {
941 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
942 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
943 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
944
945 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
946 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
947 S_028430_STENCILMASK(dsa->valuemask[0]) |
948 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
949 S_028430_STENCILOPVAL(1));
950 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
951 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
952 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
953 S_028434_STENCILOPVAL_BF(1));
954 }
955
956 static void si_set_stencil_ref(struct pipe_context *ctx,
957 const struct pipe_stencil_ref *state)
958 {
959 struct si_context *sctx = (struct si_context *)ctx;
960
961 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
962 return;
963
964 sctx->stencil_ref.state = *state;
965 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
966 }
967
968
969 /*
970 * DSA
971 */
972
973 static uint32_t si_translate_stencil_op(int s_op)
974 {
975 switch (s_op) {
976 case PIPE_STENCIL_OP_KEEP:
977 return V_02842C_STENCIL_KEEP;
978 case PIPE_STENCIL_OP_ZERO:
979 return V_02842C_STENCIL_ZERO;
980 case PIPE_STENCIL_OP_REPLACE:
981 return V_02842C_STENCIL_REPLACE_TEST;
982 case PIPE_STENCIL_OP_INCR:
983 return V_02842C_STENCIL_ADD_CLAMP;
984 case PIPE_STENCIL_OP_DECR:
985 return V_02842C_STENCIL_SUB_CLAMP;
986 case PIPE_STENCIL_OP_INCR_WRAP:
987 return V_02842C_STENCIL_ADD_WRAP;
988 case PIPE_STENCIL_OP_DECR_WRAP:
989 return V_02842C_STENCIL_SUB_WRAP;
990 case PIPE_STENCIL_OP_INVERT:
991 return V_02842C_STENCIL_INVERT;
992 default:
993 R600_ERR("Unknown stencil op %d", s_op);
994 assert(0);
995 break;
996 }
997 return 0;
998 }
999
1000 static void *si_create_dsa_state(struct pipe_context *ctx,
1001 const struct pipe_depth_stencil_alpha_state *state)
1002 {
1003 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1004 struct si_pm4_state *pm4 = &dsa->pm4;
1005 unsigned db_depth_control;
1006 uint32_t db_stencil_control = 0;
1007
1008 if (!dsa) {
1009 return NULL;
1010 }
1011
1012 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1013 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1014 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1015 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1016
1017 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1018 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1019 S_028800_ZFUNC(state->depth.func) |
1020 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1021
1022 /* stencil */
1023 if (state->stencil[0].enabled) {
1024 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1025 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1026 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1027 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1028 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1029
1030 if (state->stencil[1].enabled) {
1031 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1032 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1033 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1034 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1035 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1036 }
1037 }
1038
1039 /* alpha */
1040 if (state->alpha.enabled) {
1041 dsa->alpha_func = state->alpha.func;
1042
1043 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1044 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1045 } else {
1046 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1047 }
1048
1049 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1050 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1051 if (state->depth.bounds_test) {
1052 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1053 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1054 }
1055
1056 return dsa;
1057 }
1058
1059 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1060 {
1061 struct si_context *sctx = (struct si_context *)ctx;
1062 struct si_state_dsa *dsa = state;
1063
1064 if (!state)
1065 return;
1066
1067 si_pm4_bind_state(sctx, dsa, dsa);
1068
1069 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1070 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1071 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1072 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1073 }
1074 sctx->do_update_shaders = true;
1075 }
1076
1077 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1078 {
1079 struct si_context *sctx = (struct si_context *)ctx;
1080 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1081 }
1082
1083 static void *si_create_db_flush_dsa(struct si_context *sctx)
1084 {
1085 struct pipe_depth_stencil_alpha_state dsa = {};
1086
1087 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1088 }
1089
1090 /* DB RENDER STATE */
1091
1092 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1093 {
1094 struct si_context *sctx = (struct si_context*)ctx;
1095
1096 /* Pipeline stat & streamout queries. */
1097 if (enable) {
1098 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1099 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1100 } else {
1101 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1102 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1103 }
1104
1105 /* Occlusion queries. */
1106 if (sctx->occlusion_queries_disabled != !enable) {
1107 sctx->occlusion_queries_disabled = !enable;
1108 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1109 }
1110 }
1111
1112 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1113 {
1114 struct si_context *sctx = (struct si_context*)ctx;
1115
1116 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1117 }
1118
1119 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1120 {
1121 struct si_context *sctx = (struct si_context*)ctx;
1122
1123 st->saved_compute = sctx->cs_shader_state.program;
1124
1125 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1126 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1127 }
1128
1129 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1130 {
1131 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1132 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1133 unsigned db_shader_control;
1134
1135 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1136
1137 /* DB_RENDER_CONTROL */
1138 if (sctx->dbcb_depth_copy_enabled ||
1139 sctx->dbcb_stencil_copy_enabled) {
1140 radeon_emit(cs,
1141 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1142 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1143 S_028000_COPY_CENTROID(1) |
1144 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1145 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1146 radeon_emit(cs,
1147 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1148 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1149 } else {
1150 radeon_emit(cs,
1151 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1152 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1153 }
1154
1155 /* DB_COUNT_CONTROL (occlusion queries) */
1156 if (sctx->b.num_occlusion_queries > 0 &&
1157 !sctx->occlusion_queries_disabled) {
1158 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1159
1160 if (sctx->b.chip_class >= CIK) {
1161 radeon_emit(cs,
1162 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1163 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1164 S_028004_ZPASS_ENABLE(1) |
1165 S_028004_SLICE_EVEN_ENABLE(1) |
1166 S_028004_SLICE_ODD_ENABLE(1));
1167 } else {
1168 radeon_emit(cs,
1169 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1170 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1171 }
1172 } else {
1173 /* Disable occlusion queries. */
1174 if (sctx->b.chip_class >= CIK) {
1175 radeon_emit(cs, 0);
1176 } else {
1177 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1178 }
1179 }
1180
1181 /* DB_RENDER_OVERRIDE2 */
1182 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1183 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1184 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1185 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1186
1187 db_shader_control = sctx->ps_db_shader_control;
1188
1189 /* Bug workaround for smoothing (overrasterization) on SI. */
1190 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1191 db_shader_control &= C_02880C_Z_ORDER;
1192 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1193 }
1194
1195 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1196 if (!rs || !rs->multisample_enable)
1197 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1198
1199 if (sctx->b.family == CHIP_STONEY &&
1200 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1201 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1202
1203 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1204 db_shader_control);
1205 }
1206
1207 /*
1208 * format translation
1209 */
1210 static uint32_t si_translate_colorformat(enum pipe_format format)
1211 {
1212 const struct util_format_description *desc = util_format_description(format);
1213
1214 #define HAS_SIZE(x,y,z,w) \
1215 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1216 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1217
1218 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1219 return V_028C70_COLOR_10_11_11;
1220
1221 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1222 return V_028C70_COLOR_INVALID;
1223
1224 /* hw cannot support mixed formats (except depth/stencil, since
1225 * stencil is not written to). */
1226 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1227 return V_028C70_COLOR_INVALID;
1228
1229 switch (desc->nr_channels) {
1230 case 1:
1231 switch (desc->channel[0].size) {
1232 case 8:
1233 return V_028C70_COLOR_8;
1234 case 16:
1235 return V_028C70_COLOR_16;
1236 case 32:
1237 return V_028C70_COLOR_32;
1238 }
1239 break;
1240 case 2:
1241 if (desc->channel[0].size == desc->channel[1].size) {
1242 switch (desc->channel[0].size) {
1243 case 8:
1244 return V_028C70_COLOR_8_8;
1245 case 16:
1246 return V_028C70_COLOR_16_16;
1247 case 32:
1248 return V_028C70_COLOR_32_32;
1249 }
1250 } else if (HAS_SIZE(8,24,0,0)) {
1251 return V_028C70_COLOR_24_8;
1252 } else if (HAS_SIZE(24,8,0,0)) {
1253 return V_028C70_COLOR_8_24;
1254 }
1255 break;
1256 case 3:
1257 if (HAS_SIZE(5,6,5,0)) {
1258 return V_028C70_COLOR_5_6_5;
1259 } else if (HAS_SIZE(32,8,24,0)) {
1260 return V_028C70_COLOR_X24_8_32_FLOAT;
1261 }
1262 break;
1263 case 4:
1264 if (desc->channel[0].size == desc->channel[1].size &&
1265 desc->channel[0].size == desc->channel[2].size &&
1266 desc->channel[0].size == desc->channel[3].size) {
1267 switch (desc->channel[0].size) {
1268 case 4:
1269 return V_028C70_COLOR_4_4_4_4;
1270 case 8:
1271 return V_028C70_COLOR_8_8_8_8;
1272 case 16:
1273 return V_028C70_COLOR_16_16_16_16;
1274 case 32:
1275 return V_028C70_COLOR_32_32_32_32;
1276 }
1277 } else if (HAS_SIZE(5,5,5,1)) {
1278 return V_028C70_COLOR_1_5_5_5;
1279 } else if (HAS_SIZE(10,10,10,2)) {
1280 return V_028C70_COLOR_2_10_10_10;
1281 }
1282 break;
1283 }
1284 return V_028C70_COLOR_INVALID;
1285 }
1286
1287 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1288 {
1289 if (SI_BIG_ENDIAN) {
1290 switch(colorformat) {
1291 /* 8-bit buffers. */
1292 case V_028C70_COLOR_8:
1293 return V_028C70_ENDIAN_NONE;
1294
1295 /* 16-bit buffers. */
1296 case V_028C70_COLOR_5_6_5:
1297 case V_028C70_COLOR_1_5_5_5:
1298 case V_028C70_COLOR_4_4_4_4:
1299 case V_028C70_COLOR_16:
1300 case V_028C70_COLOR_8_8:
1301 return V_028C70_ENDIAN_8IN16;
1302
1303 /* 32-bit buffers. */
1304 case V_028C70_COLOR_8_8_8_8:
1305 case V_028C70_COLOR_2_10_10_10:
1306 case V_028C70_COLOR_8_24:
1307 case V_028C70_COLOR_24_8:
1308 case V_028C70_COLOR_16_16:
1309 return V_028C70_ENDIAN_8IN32;
1310
1311 /* 64-bit buffers. */
1312 case V_028C70_COLOR_16_16_16_16:
1313 return V_028C70_ENDIAN_8IN16;
1314
1315 case V_028C70_COLOR_32_32:
1316 return V_028C70_ENDIAN_8IN32;
1317
1318 /* 128-bit buffers. */
1319 case V_028C70_COLOR_32_32_32_32:
1320 return V_028C70_ENDIAN_8IN32;
1321 default:
1322 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1323 }
1324 } else {
1325 return V_028C70_ENDIAN_NONE;
1326 }
1327 }
1328
1329 static uint32_t si_translate_dbformat(enum pipe_format format)
1330 {
1331 switch (format) {
1332 case PIPE_FORMAT_Z16_UNORM:
1333 return V_028040_Z_16;
1334 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1335 case PIPE_FORMAT_X8Z24_UNORM:
1336 case PIPE_FORMAT_Z24X8_UNORM:
1337 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1338 return V_028040_Z_24; /* deprecated on SI */
1339 case PIPE_FORMAT_Z32_FLOAT:
1340 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1341 return V_028040_Z_32_FLOAT;
1342 default:
1343 return V_028040_Z_INVALID;
1344 }
1345 }
1346
1347 /*
1348 * Texture translation
1349 */
1350
1351 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1352 enum pipe_format format,
1353 const struct util_format_description *desc,
1354 int first_non_void)
1355 {
1356 struct si_screen *sscreen = (struct si_screen*)screen;
1357 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1358 sscreen->b.info.drm_minor >= 31) ||
1359 sscreen->b.info.drm_major == 3;
1360 bool uniform = true;
1361 int i;
1362
1363 /* Colorspace (return non-RGB formats directly). */
1364 switch (desc->colorspace) {
1365 /* Depth stencil formats */
1366 case UTIL_FORMAT_COLORSPACE_ZS:
1367 switch (format) {
1368 case PIPE_FORMAT_Z16_UNORM:
1369 return V_008F14_IMG_DATA_FORMAT_16;
1370 case PIPE_FORMAT_X24S8_UINT:
1371 case PIPE_FORMAT_S8X24_UINT:
1372 /*
1373 * Implemented as an 8_8_8_8 data format to fix texture
1374 * gathers in stencil sampling. This affects at least
1375 * GL45-CTS.texture_cube_map_array.sampling on VI.
1376 */
1377 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1378 case PIPE_FORMAT_Z24X8_UNORM:
1379 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1380 return V_008F14_IMG_DATA_FORMAT_8_24;
1381 case PIPE_FORMAT_X8Z24_UNORM:
1382 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1383 return V_008F14_IMG_DATA_FORMAT_24_8;
1384 case PIPE_FORMAT_S8_UINT:
1385 return V_008F14_IMG_DATA_FORMAT_8;
1386 case PIPE_FORMAT_Z32_FLOAT:
1387 return V_008F14_IMG_DATA_FORMAT_32;
1388 case PIPE_FORMAT_X32_S8X24_UINT:
1389 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1390 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1391 default:
1392 goto out_unknown;
1393 }
1394
1395 case UTIL_FORMAT_COLORSPACE_YUV:
1396 goto out_unknown; /* TODO */
1397
1398 case UTIL_FORMAT_COLORSPACE_SRGB:
1399 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1400 goto out_unknown;
1401 break;
1402
1403 default:
1404 break;
1405 }
1406
1407 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1408 if (!enable_compressed_formats)
1409 goto out_unknown;
1410
1411 switch (format) {
1412 case PIPE_FORMAT_RGTC1_SNORM:
1413 case PIPE_FORMAT_LATC1_SNORM:
1414 case PIPE_FORMAT_RGTC1_UNORM:
1415 case PIPE_FORMAT_LATC1_UNORM:
1416 return V_008F14_IMG_DATA_FORMAT_BC4;
1417 case PIPE_FORMAT_RGTC2_SNORM:
1418 case PIPE_FORMAT_LATC2_SNORM:
1419 case PIPE_FORMAT_RGTC2_UNORM:
1420 case PIPE_FORMAT_LATC2_UNORM:
1421 return V_008F14_IMG_DATA_FORMAT_BC5;
1422 default:
1423 goto out_unknown;
1424 }
1425 }
1426
1427 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1428 sscreen->b.family == CHIP_STONEY) {
1429 switch (format) {
1430 case PIPE_FORMAT_ETC1_RGB8:
1431 case PIPE_FORMAT_ETC2_RGB8:
1432 case PIPE_FORMAT_ETC2_SRGB8:
1433 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1434 case PIPE_FORMAT_ETC2_RGB8A1:
1435 case PIPE_FORMAT_ETC2_SRGB8A1:
1436 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1437 case PIPE_FORMAT_ETC2_RGBA8:
1438 case PIPE_FORMAT_ETC2_SRGBA8:
1439 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1440 case PIPE_FORMAT_ETC2_R11_UNORM:
1441 case PIPE_FORMAT_ETC2_R11_SNORM:
1442 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1443 case PIPE_FORMAT_ETC2_RG11_UNORM:
1444 case PIPE_FORMAT_ETC2_RG11_SNORM:
1445 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1446 default:
1447 goto out_unknown;
1448 }
1449 }
1450
1451 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1452 if (!enable_compressed_formats)
1453 goto out_unknown;
1454
1455 switch (format) {
1456 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1457 case PIPE_FORMAT_BPTC_SRGBA:
1458 return V_008F14_IMG_DATA_FORMAT_BC7;
1459 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1460 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1461 return V_008F14_IMG_DATA_FORMAT_BC6;
1462 default:
1463 goto out_unknown;
1464 }
1465 }
1466
1467 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1468 switch (format) {
1469 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1470 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1471 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1472 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1473 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1474 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1475 default:
1476 goto out_unknown;
1477 }
1478 }
1479
1480 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1481 if (!enable_compressed_formats)
1482 goto out_unknown;
1483
1484 if (!util_format_s3tc_enabled) {
1485 goto out_unknown;
1486 }
1487
1488 switch (format) {
1489 case PIPE_FORMAT_DXT1_RGB:
1490 case PIPE_FORMAT_DXT1_RGBA:
1491 case PIPE_FORMAT_DXT1_SRGB:
1492 case PIPE_FORMAT_DXT1_SRGBA:
1493 return V_008F14_IMG_DATA_FORMAT_BC1;
1494 case PIPE_FORMAT_DXT3_RGBA:
1495 case PIPE_FORMAT_DXT3_SRGBA:
1496 return V_008F14_IMG_DATA_FORMAT_BC2;
1497 case PIPE_FORMAT_DXT5_RGBA:
1498 case PIPE_FORMAT_DXT5_SRGBA:
1499 return V_008F14_IMG_DATA_FORMAT_BC3;
1500 default:
1501 goto out_unknown;
1502 }
1503 }
1504
1505 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1506 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1507 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1508 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1509 }
1510
1511 /* R8G8Bx_SNORM - TODO CxV8U8 */
1512
1513 /* hw cannot support mixed formats (except depth/stencil, since only
1514 * depth is read).*/
1515 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1516 goto out_unknown;
1517
1518 /* See whether the components are of the same size. */
1519 for (i = 1; i < desc->nr_channels; i++) {
1520 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1521 }
1522
1523 /* Non-uniform formats. */
1524 if (!uniform) {
1525 switch(desc->nr_channels) {
1526 case 3:
1527 if (desc->channel[0].size == 5 &&
1528 desc->channel[1].size == 6 &&
1529 desc->channel[2].size == 5) {
1530 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1531 }
1532 goto out_unknown;
1533 case 4:
1534 if (desc->channel[0].size == 5 &&
1535 desc->channel[1].size == 5 &&
1536 desc->channel[2].size == 5 &&
1537 desc->channel[3].size == 1) {
1538 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1539 }
1540 if (desc->channel[0].size == 10 &&
1541 desc->channel[1].size == 10 &&
1542 desc->channel[2].size == 10 &&
1543 desc->channel[3].size == 2) {
1544 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1545 }
1546 goto out_unknown;
1547 }
1548 goto out_unknown;
1549 }
1550
1551 if (first_non_void < 0 || first_non_void > 3)
1552 goto out_unknown;
1553
1554 /* uniform formats */
1555 switch (desc->channel[first_non_void].size) {
1556 case 4:
1557 switch (desc->nr_channels) {
1558 #if 0 /* Not supported for render targets */
1559 case 2:
1560 return V_008F14_IMG_DATA_FORMAT_4_4;
1561 #endif
1562 case 4:
1563 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1564 }
1565 break;
1566 case 8:
1567 switch (desc->nr_channels) {
1568 case 1:
1569 return V_008F14_IMG_DATA_FORMAT_8;
1570 case 2:
1571 return V_008F14_IMG_DATA_FORMAT_8_8;
1572 case 4:
1573 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1574 }
1575 break;
1576 case 16:
1577 switch (desc->nr_channels) {
1578 case 1:
1579 return V_008F14_IMG_DATA_FORMAT_16;
1580 case 2:
1581 return V_008F14_IMG_DATA_FORMAT_16_16;
1582 case 4:
1583 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1584 }
1585 break;
1586 case 32:
1587 switch (desc->nr_channels) {
1588 case 1:
1589 return V_008F14_IMG_DATA_FORMAT_32;
1590 case 2:
1591 return V_008F14_IMG_DATA_FORMAT_32_32;
1592 #if 0 /* Not supported for render targets */
1593 case 3:
1594 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1595 #endif
1596 case 4:
1597 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1598 }
1599 }
1600
1601 out_unknown:
1602 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1603 return ~0;
1604 }
1605
1606 static unsigned si_tex_wrap(unsigned wrap)
1607 {
1608 switch (wrap) {
1609 default:
1610 case PIPE_TEX_WRAP_REPEAT:
1611 return V_008F30_SQ_TEX_WRAP;
1612 case PIPE_TEX_WRAP_CLAMP:
1613 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1614 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1615 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1616 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1617 return V_008F30_SQ_TEX_CLAMP_BORDER;
1618 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1619 return V_008F30_SQ_TEX_MIRROR;
1620 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1621 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1622 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1623 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1624 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1625 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1626 }
1627 }
1628
1629 static unsigned si_tex_mipfilter(unsigned filter)
1630 {
1631 switch (filter) {
1632 case PIPE_TEX_MIPFILTER_NEAREST:
1633 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1634 case PIPE_TEX_MIPFILTER_LINEAR:
1635 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1636 default:
1637 case PIPE_TEX_MIPFILTER_NONE:
1638 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1639 }
1640 }
1641
1642 static unsigned si_tex_compare(unsigned compare)
1643 {
1644 switch (compare) {
1645 default:
1646 case PIPE_FUNC_NEVER:
1647 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1648 case PIPE_FUNC_LESS:
1649 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1650 case PIPE_FUNC_EQUAL:
1651 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1652 case PIPE_FUNC_LEQUAL:
1653 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1654 case PIPE_FUNC_GREATER:
1655 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1656 case PIPE_FUNC_NOTEQUAL:
1657 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1658 case PIPE_FUNC_GEQUAL:
1659 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1660 case PIPE_FUNC_ALWAYS:
1661 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1662 }
1663 }
1664
1665 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1666 unsigned nr_samples)
1667 {
1668 if (view_target == PIPE_TEXTURE_CUBE ||
1669 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1670 res_target = view_target;
1671 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1672 else if (res_target == PIPE_TEXTURE_CUBE ||
1673 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1674 res_target = PIPE_TEXTURE_2D_ARRAY;
1675
1676 switch (res_target) {
1677 default:
1678 case PIPE_TEXTURE_1D:
1679 return V_008F1C_SQ_RSRC_IMG_1D;
1680 case PIPE_TEXTURE_1D_ARRAY:
1681 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1682 case PIPE_TEXTURE_2D:
1683 case PIPE_TEXTURE_RECT:
1684 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1685 V_008F1C_SQ_RSRC_IMG_2D;
1686 case PIPE_TEXTURE_2D_ARRAY:
1687 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1688 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1689 case PIPE_TEXTURE_3D:
1690 return V_008F1C_SQ_RSRC_IMG_3D;
1691 case PIPE_TEXTURE_CUBE:
1692 case PIPE_TEXTURE_CUBE_ARRAY:
1693 return V_008F1C_SQ_RSRC_IMG_CUBE;
1694 }
1695 }
1696
1697 /*
1698 * Format support testing
1699 */
1700
1701 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1702 {
1703 return si_translate_texformat(screen, format, util_format_description(format),
1704 util_format_get_first_non_void_channel(format)) != ~0U;
1705 }
1706
1707 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1708 const struct util_format_description *desc,
1709 int first_non_void)
1710 {
1711 int i;
1712
1713 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1714 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1715
1716 assert(first_non_void >= 0);
1717
1718 if (desc->nr_channels == 4 &&
1719 desc->channel[0].size == 10 &&
1720 desc->channel[1].size == 10 &&
1721 desc->channel[2].size == 10 &&
1722 desc->channel[3].size == 2)
1723 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1724
1725 /* See whether the components are of the same size. */
1726 for (i = 0; i < desc->nr_channels; i++) {
1727 if (desc->channel[first_non_void].size != desc->channel[i].size)
1728 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1729 }
1730
1731 switch (desc->channel[first_non_void].size) {
1732 case 8:
1733 switch (desc->nr_channels) {
1734 case 1:
1735 case 3: /* 3 loads */
1736 return V_008F0C_BUF_DATA_FORMAT_8;
1737 case 2:
1738 return V_008F0C_BUF_DATA_FORMAT_8_8;
1739 case 4:
1740 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1741 }
1742 break;
1743 case 16:
1744 switch (desc->nr_channels) {
1745 case 1:
1746 case 3: /* 3 loads */
1747 return V_008F0C_BUF_DATA_FORMAT_16;
1748 case 2:
1749 return V_008F0C_BUF_DATA_FORMAT_16_16;
1750 case 4:
1751 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1752 }
1753 break;
1754 case 32:
1755 switch (desc->nr_channels) {
1756 case 1:
1757 return V_008F0C_BUF_DATA_FORMAT_32;
1758 case 2:
1759 return V_008F0C_BUF_DATA_FORMAT_32_32;
1760 case 3:
1761 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1762 case 4:
1763 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1764 }
1765 break;
1766 case 64:
1767 /* Legacy double formats. */
1768 switch (desc->nr_channels) {
1769 case 1: /* 1 load */
1770 return V_008F0C_BUF_DATA_FORMAT_32_32;
1771 case 2: /* 1 load */
1772 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1773 case 3: /* 3 loads */
1774 return V_008F0C_BUF_DATA_FORMAT_32_32;
1775 case 4: /* 2 loads */
1776 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1777 }
1778 break;
1779 }
1780
1781 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1782 }
1783
1784 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1785 const struct util_format_description *desc,
1786 int first_non_void)
1787 {
1788 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1789 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1790
1791 assert(first_non_void >= 0);
1792
1793 switch (desc->channel[first_non_void].type) {
1794 case UTIL_FORMAT_TYPE_SIGNED:
1795 case UTIL_FORMAT_TYPE_FIXED:
1796 if (desc->channel[first_non_void].size >= 32 ||
1797 desc->channel[first_non_void].pure_integer)
1798 return V_008F0C_BUF_NUM_FORMAT_SINT;
1799 else if (desc->channel[first_non_void].normalized)
1800 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1801 else
1802 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1803 break;
1804 case UTIL_FORMAT_TYPE_UNSIGNED:
1805 if (desc->channel[first_non_void].size >= 32 ||
1806 desc->channel[first_non_void].pure_integer)
1807 return V_008F0C_BUF_NUM_FORMAT_UINT;
1808 else if (desc->channel[first_non_void].normalized)
1809 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1810 else
1811 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1812 break;
1813 case UTIL_FORMAT_TYPE_FLOAT:
1814 default:
1815 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1816 }
1817 }
1818
1819 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1820 enum pipe_format format,
1821 unsigned usage)
1822 {
1823 const struct util_format_description *desc;
1824 int first_non_void;
1825 unsigned data_format;
1826
1827 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1828 PIPE_BIND_SAMPLER_VIEW |
1829 PIPE_BIND_VERTEX_BUFFER)) == 0);
1830
1831 desc = util_format_description(format);
1832
1833 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1834 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1835 * for read-only access (with caveats surrounding bounds checks), but
1836 * obviously fails for write access which we have to implement for
1837 * shader images. Luckily, OpenGL doesn't expect this to be supported
1838 * anyway, and so the only impact is on PBO uploads / downloads, which
1839 * shouldn't be expected to be fast for GL_RGB anyway.
1840 */
1841 if (desc->block.bits == 3 * 8 ||
1842 desc->block.bits == 3 * 16) {
1843 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1844 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1845 if (!usage)
1846 return 0;
1847 }
1848 }
1849
1850 first_non_void = util_format_get_first_non_void_channel(format);
1851 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1852 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1853 return 0;
1854
1855 return usage;
1856 }
1857
1858 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1859 {
1860 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1861 r600_translate_colorswap(format, false) != ~0U;
1862 }
1863
1864 static bool si_is_zs_format_supported(enum pipe_format format)
1865 {
1866 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1867 }
1868
1869 static boolean si_is_format_supported(struct pipe_screen *screen,
1870 enum pipe_format format,
1871 enum pipe_texture_target target,
1872 unsigned sample_count,
1873 unsigned usage)
1874 {
1875 unsigned retval = 0;
1876
1877 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1878 R600_ERR("r600: unsupported texture type %d\n", target);
1879 return false;
1880 }
1881
1882 if (!util_format_is_supported(format, usage))
1883 return false;
1884
1885 if (sample_count > 1) {
1886 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1887 return false;
1888
1889 if (usage & PIPE_BIND_SHADER_IMAGE)
1890 return false;
1891
1892 switch (sample_count) {
1893 case 2:
1894 case 4:
1895 case 8:
1896 break;
1897 case 16:
1898 if (format == PIPE_FORMAT_NONE)
1899 return true;
1900 else
1901 return false;
1902 default:
1903 return false;
1904 }
1905 }
1906
1907 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1908 PIPE_BIND_SHADER_IMAGE)) {
1909 if (target == PIPE_BUFFER) {
1910 retval |= si_is_vertex_format_supported(
1911 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1912 PIPE_BIND_SHADER_IMAGE));
1913 } else {
1914 if (si_is_sampler_format_supported(screen, format))
1915 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1916 PIPE_BIND_SHADER_IMAGE);
1917 }
1918 }
1919
1920 if ((usage & (PIPE_BIND_RENDER_TARGET |
1921 PIPE_BIND_DISPLAY_TARGET |
1922 PIPE_BIND_SCANOUT |
1923 PIPE_BIND_SHARED |
1924 PIPE_BIND_BLENDABLE)) &&
1925 si_is_colorbuffer_format_supported(format)) {
1926 retval |= usage &
1927 (PIPE_BIND_RENDER_TARGET |
1928 PIPE_BIND_DISPLAY_TARGET |
1929 PIPE_BIND_SCANOUT |
1930 PIPE_BIND_SHARED);
1931 if (!util_format_is_pure_integer(format) &&
1932 !util_format_is_depth_or_stencil(format))
1933 retval |= usage & PIPE_BIND_BLENDABLE;
1934 }
1935
1936 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1937 si_is_zs_format_supported(format)) {
1938 retval |= PIPE_BIND_DEPTH_STENCIL;
1939 }
1940
1941 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1942 retval |= si_is_vertex_format_supported(screen, format,
1943 PIPE_BIND_VERTEX_BUFFER);
1944 }
1945
1946 if ((usage & PIPE_BIND_LINEAR) &&
1947 !util_format_is_compressed(format) &&
1948 !(usage & PIPE_BIND_DEPTH_STENCIL))
1949 retval |= PIPE_BIND_LINEAR;
1950
1951 return retval == usage;
1952 }
1953
1954 /*
1955 * framebuffer handling
1956 */
1957
1958 static void si_choose_spi_color_formats(struct r600_surface *surf,
1959 unsigned format, unsigned swap,
1960 unsigned ntype, bool is_depth)
1961 {
1962 /* Alpha is needed for alpha-to-coverage.
1963 * Blending may be with or without alpha.
1964 */
1965 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1966 unsigned alpha = 0; /* exports alpha, but may not support blending */
1967 unsigned blend = 0; /* supports blending, but may not export alpha */
1968 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1969
1970 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1971 * Other chips have multiple choices, though they are not necessarily better.
1972 */
1973 switch (format) {
1974 case V_028C70_COLOR_5_6_5:
1975 case V_028C70_COLOR_1_5_5_5:
1976 case V_028C70_COLOR_5_5_5_1:
1977 case V_028C70_COLOR_4_4_4_4:
1978 case V_028C70_COLOR_10_11_11:
1979 case V_028C70_COLOR_11_11_10:
1980 case V_028C70_COLOR_8:
1981 case V_028C70_COLOR_8_8:
1982 case V_028C70_COLOR_8_8_8_8:
1983 case V_028C70_COLOR_10_10_10_2:
1984 case V_028C70_COLOR_2_10_10_10:
1985 if (ntype == V_028C70_NUMBER_UINT)
1986 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1987 else if (ntype == V_028C70_NUMBER_SINT)
1988 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1989 else
1990 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1991 break;
1992
1993 case V_028C70_COLOR_16:
1994 case V_028C70_COLOR_16_16:
1995 case V_028C70_COLOR_16_16_16_16:
1996 if (ntype == V_028C70_NUMBER_UNORM ||
1997 ntype == V_028C70_NUMBER_SNORM) {
1998 /* UNORM16 and SNORM16 don't support blending */
1999 if (ntype == V_028C70_NUMBER_UNORM)
2000 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2001 else
2002 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2003
2004 /* Use 32 bits per channel for blending. */
2005 if (format == V_028C70_COLOR_16) {
2006 if (swap == V_028C70_SWAP_STD) { /* R */
2007 blend = V_028714_SPI_SHADER_32_R;
2008 blend_alpha = V_028714_SPI_SHADER_32_AR;
2009 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2010 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2011 else
2012 assert(0);
2013 } else if (format == V_028C70_COLOR_16_16) {
2014 if (swap == V_028C70_SWAP_STD) { /* RG */
2015 blend = V_028714_SPI_SHADER_32_GR;
2016 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2017 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2018 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2019 else
2020 assert(0);
2021 } else /* 16_16_16_16 */
2022 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2023 } else if (ntype == V_028C70_NUMBER_UINT)
2024 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2025 else if (ntype == V_028C70_NUMBER_SINT)
2026 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2027 else if (ntype == V_028C70_NUMBER_FLOAT)
2028 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2029 else
2030 assert(0);
2031 break;
2032
2033 case V_028C70_COLOR_32:
2034 if (swap == V_028C70_SWAP_STD) { /* R */
2035 blend = normal = V_028714_SPI_SHADER_32_R;
2036 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2037 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2038 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2039 else
2040 assert(0);
2041 break;
2042
2043 case V_028C70_COLOR_32_32:
2044 if (swap == V_028C70_SWAP_STD) { /* RG */
2045 blend = normal = V_028714_SPI_SHADER_32_GR;
2046 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2047 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2048 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2049 else
2050 assert(0);
2051 break;
2052
2053 case V_028C70_COLOR_32_32_32_32:
2054 case V_028C70_COLOR_8_24:
2055 case V_028C70_COLOR_24_8:
2056 case V_028C70_COLOR_X24_8_32_FLOAT:
2057 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2058 break;
2059
2060 default:
2061 assert(0);
2062 return;
2063 }
2064
2065 /* The DB->CB copy needs 32_ABGR. */
2066 if (is_depth)
2067 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2068
2069 surf->spi_shader_col_format = normal;
2070 surf->spi_shader_col_format_alpha = alpha;
2071 surf->spi_shader_col_format_blend = blend;
2072 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2073 }
2074
2075 static void si_initialize_color_surface(struct si_context *sctx,
2076 struct r600_surface *surf)
2077 {
2078 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2079 unsigned color_info, color_attrib, color_view;
2080 unsigned format, swap, ntype, endian;
2081 const struct util_format_description *desc;
2082 int i;
2083 unsigned blend_clamp = 0, blend_bypass = 0;
2084
2085 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2086 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2087
2088 desc = util_format_description(surf->base.format);
2089 for (i = 0; i < 4; i++) {
2090 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2091 break;
2092 }
2093 }
2094 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2095 ntype = V_028C70_NUMBER_FLOAT;
2096 } else {
2097 ntype = V_028C70_NUMBER_UNORM;
2098 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2099 ntype = V_028C70_NUMBER_SRGB;
2100 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2101 if (desc->channel[i].pure_integer) {
2102 ntype = V_028C70_NUMBER_SINT;
2103 } else {
2104 assert(desc->channel[i].normalized);
2105 ntype = V_028C70_NUMBER_SNORM;
2106 }
2107 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2108 if (desc->channel[i].pure_integer) {
2109 ntype = V_028C70_NUMBER_UINT;
2110 } else {
2111 assert(desc->channel[i].normalized);
2112 ntype = V_028C70_NUMBER_UNORM;
2113 }
2114 }
2115 }
2116
2117 format = si_translate_colorformat(surf->base.format);
2118 if (format == V_028C70_COLOR_INVALID) {
2119 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2120 }
2121 assert(format != V_028C70_COLOR_INVALID);
2122 swap = r600_translate_colorswap(surf->base.format, false);
2123 endian = si_colorformat_endian_swap(format);
2124
2125 /* blend clamp should be set for all NORM/SRGB types */
2126 if (ntype == V_028C70_NUMBER_UNORM ||
2127 ntype == V_028C70_NUMBER_SNORM ||
2128 ntype == V_028C70_NUMBER_SRGB)
2129 blend_clamp = 1;
2130
2131 /* set blend bypass according to docs if SINT/UINT or
2132 8/24 COLOR variants */
2133 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2134 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2135 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2136 blend_clamp = 0;
2137 blend_bypass = 1;
2138 }
2139
2140 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2141 if (format == V_028C70_COLOR_8 ||
2142 format == V_028C70_COLOR_8_8 ||
2143 format == V_028C70_COLOR_8_8_8_8)
2144 surf->color_is_int8 = true;
2145 else if (format == V_028C70_COLOR_10_10_10_2 ||
2146 format == V_028C70_COLOR_2_10_10_10)
2147 surf->color_is_int10 = true;
2148 }
2149
2150 color_info = S_028C70_FORMAT(format) |
2151 S_028C70_COMP_SWAP(swap) |
2152 S_028C70_BLEND_CLAMP(blend_clamp) |
2153 S_028C70_BLEND_BYPASS(blend_bypass) |
2154 S_028C70_SIMPLE_FLOAT(1) |
2155 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2156 ntype != V_028C70_NUMBER_SNORM &&
2157 ntype != V_028C70_NUMBER_SRGB &&
2158 format != V_028C70_COLOR_8_24 &&
2159 format != V_028C70_COLOR_24_8) |
2160 S_028C70_NUMBER_TYPE(ntype) |
2161 S_028C70_ENDIAN(endian);
2162
2163 /* Intensity is implemented as Red, so treat it that way. */
2164 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2165 util_format_is_intensity(surf->base.format));
2166
2167 if (rtex->resource.b.b.nr_samples > 1) {
2168 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2169
2170 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2171 S_028C74_NUM_FRAGMENTS(log_samples);
2172
2173 if (rtex->fmask.size) {
2174 color_info |= S_028C70_COMPRESSION(1);
2175 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2176
2177 if (sctx->b.chip_class == SI) {
2178 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2179 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2180 }
2181 }
2182 }
2183
2184 surf->cb_color_view = color_view;
2185 surf->cb_color_info = color_info;
2186 surf->cb_color_attrib = color_attrib;
2187
2188 if (sctx->b.chip_class >= VI) {
2189 unsigned max_uncompressed_block_size = 2;
2190
2191 if (rtex->resource.b.b.nr_samples > 1) {
2192 if (rtex->surface.bpe == 1)
2193 max_uncompressed_block_size = 0;
2194 else if (rtex->surface.bpe == 2)
2195 max_uncompressed_block_size = 1;
2196 }
2197
2198 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2199 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2200 }
2201
2202 /* This must be set for fast clear to work without FMASK. */
2203 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2204 unsigned bankh = util_logbase2(rtex->surface.bankh);
2205 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2206 }
2207
2208 /* Determine pixel shader export format */
2209 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2210
2211 surf->color_initialized = true;
2212 }
2213
2214 static void si_init_depth_surface(struct si_context *sctx,
2215 struct r600_surface *surf)
2216 {
2217 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2218 unsigned level = surf->base.u.tex.level;
2219 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2220 unsigned format;
2221 uint32_t z_info, s_info, db_depth_info;
2222 uint64_t z_offs, s_offs;
2223 uint32_t db_htile_data_base, db_htile_surface;
2224
2225 format = si_translate_dbformat(rtex->db_render_format);
2226
2227 if (format == V_028040_Z_INVALID) {
2228 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2229 }
2230 assert(format != V_028040_Z_INVALID);
2231
2232 s_offs = z_offs = rtex->resource.gpu_address;
2233 z_offs += rtex->surface.level[level].offset;
2234 s_offs += rtex->surface.stencil_level[level].offset;
2235
2236 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2237
2238 z_info = S_028040_FORMAT(format);
2239 if (rtex->resource.b.b.nr_samples > 1) {
2240 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2241 }
2242
2243 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2244 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2245 else
2246 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2247
2248 if (sctx->b.chip_class >= CIK) {
2249 struct radeon_info *info = &sctx->screen->b.info;
2250 unsigned index = rtex->surface.tiling_index[level];
2251 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2252 unsigned macro_index = rtex->surface.macro_tile_index;
2253 unsigned tile_mode = info->si_tile_mode_array[index];
2254 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2255 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2256
2257 db_depth_info |=
2258 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2259 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2260 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2261 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2262 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2263 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2264 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2265 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2266 } else {
2267 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2268 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2269 tile_mode_index = si_tile_mode_index(rtex, level, true);
2270 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2271 }
2272
2273 /* HiZ aka depth buffer htile */
2274 /* use htile only for first level */
2275 if (rtex->htile_buffer && !level) {
2276 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2277 S_028040_ALLOW_EXPCLEAR(1);
2278
2279 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2280 /* Workaround: For a not yet understood reason, the
2281 * combination of MSAA, fast stencil clear and stencil
2282 * decompress messes with subsequent stencil buffer
2283 * uses. Problem was reproduced on Verde, Bonaire,
2284 * Tonga, and Carrizo.
2285 *
2286 * Disabling EXPCLEAR works around the problem.
2287 *
2288 * Check piglit's arb_texture_multisample-stencil-clear
2289 * test if you want to try changing this.
2290 */
2291 if (rtex->resource.b.b.nr_samples <= 1)
2292 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2293 } else if (!rtex->tc_compatible_htile) {
2294 /* Use all of the htile_buffer for depth if there's no stencil.
2295 * This must not be set when TC-compatible HTILE is enabled
2296 * due to a hw bug.
2297 */
2298 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2299 }
2300
2301 uint64_t va = rtex->htile_buffer->gpu_address;
2302 db_htile_data_base = va >> 8;
2303 db_htile_surface = S_028ABC_FULL_CACHE(1);
2304
2305 if (rtex->tc_compatible_htile) {
2306 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2307
2308 switch (rtex->resource.b.b.nr_samples) {
2309 case 0:
2310 case 1:
2311 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2312 break;
2313 case 2:
2314 case 4:
2315 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2316 break;
2317 case 8:
2318 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2319 break;
2320 default:
2321 assert(0);
2322 }
2323 }
2324 } else {
2325 db_htile_data_base = 0;
2326 db_htile_surface = 0;
2327 }
2328
2329 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2330
2331 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2332 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2333 surf->db_htile_data_base = db_htile_data_base;
2334 surf->db_depth_info = db_depth_info;
2335 surf->db_z_info = z_info;
2336 surf->db_stencil_info = s_info;
2337 surf->db_depth_base = z_offs >> 8;
2338 surf->db_stencil_base = s_offs >> 8;
2339 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2340 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2341 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2342 levelinfo->nblk_y) / 64 - 1);
2343 surf->db_htile_surface = db_htile_surface;
2344
2345 surf->depth_initialized = true;
2346 }
2347
2348 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2349 {
2350 for (int i = 0; i < state->nr_cbufs; ++i) {
2351 struct r600_surface *surf = NULL;
2352 struct r600_texture *rtex;
2353
2354 if (!state->cbufs[i])
2355 continue;
2356 surf = (struct r600_surface*)state->cbufs[i];
2357 rtex = (struct r600_texture*)surf->base.texture;
2358
2359 p_atomic_dec(&rtex->framebuffers_bound);
2360 }
2361 }
2362
2363 static void si_set_framebuffer_state(struct pipe_context *ctx,
2364 const struct pipe_framebuffer_state *state)
2365 {
2366 struct si_context *sctx = (struct si_context *)ctx;
2367 struct pipe_constant_buffer constbuf = {0};
2368 struct r600_surface *surf = NULL;
2369 struct r600_texture *rtex;
2370 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2371 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2372 int i;
2373
2374 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2375 if (!sctx->framebuffer.state.cbufs[i])
2376 continue;
2377
2378 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2379 if (rtex->dcc_gather_statistics)
2380 vi_separate_dcc_stop_query(ctx, rtex);
2381 }
2382
2383 /* Only flush TC when changing the framebuffer state, because
2384 * the only client not using TC that can change textures is
2385 * the framebuffer.
2386 *
2387 * Flush all CB and DB caches here because all buffers can be used
2388 * for write by both TC (with shader image stores) and CB/DB.
2389 */
2390 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2391 SI_CONTEXT_INV_GLOBAL_L2 |
2392 SI_CONTEXT_FLUSH_AND_INV_CB |
2393 SI_CONTEXT_FLUSH_AND_INV_DB |
2394 SI_CONTEXT_CS_PARTIAL_FLUSH;
2395
2396 /* Take the maximum of the old and new count. If the new count is lower,
2397 * dirtying is needed to disable the unbound colorbuffers.
2398 */
2399 sctx->framebuffer.dirty_cbufs |=
2400 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2401 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2402
2403 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2404 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2405
2406 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2407 sctx->framebuffer.spi_shader_col_format = 0;
2408 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2409 sctx->framebuffer.spi_shader_col_format_blend = 0;
2410 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2411 sctx->framebuffer.color_is_int8 = 0;
2412 sctx->framebuffer.color_is_int10 = 0;
2413
2414 sctx->framebuffer.compressed_cb_mask = 0;
2415 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2416 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2417 sctx->framebuffer.any_dst_linear = false;
2418
2419 for (i = 0; i < state->nr_cbufs; i++) {
2420 if (!state->cbufs[i])
2421 continue;
2422
2423 surf = (struct r600_surface*)state->cbufs[i];
2424 rtex = (struct r600_texture*)surf->base.texture;
2425
2426 if (!surf->color_initialized) {
2427 si_initialize_color_surface(sctx, surf);
2428 }
2429
2430 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2431 sctx->framebuffer.spi_shader_col_format |=
2432 surf->spi_shader_col_format << (i * 4);
2433 sctx->framebuffer.spi_shader_col_format_alpha |=
2434 surf->spi_shader_col_format_alpha << (i * 4);
2435 sctx->framebuffer.spi_shader_col_format_blend |=
2436 surf->spi_shader_col_format_blend << (i * 4);
2437 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2438 surf->spi_shader_col_format_blend_alpha << (i * 4);
2439
2440 if (surf->color_is_int8)
2441 sctx->framebuffer.color_is_int8 |= 1 << i;
2442 if (surf->color_is_int10)
2443 sctx->framebuffer.color_is_int10 |= 1 << i;
2444
2445 if (rtex->fmask.size) {
2446 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2447 }
2448
2449 if (rtex->surface.is_linear)
2450 sctx->framebuffer.any_dst_linear = true;
2451
2452 r600_context_add_resource_size(ctx, surf->base.texture);
2453
2454 p_atomic_inc(&rtex->framebuffers_bound);
2455
2456 if (rtex->dcc_gather_statistics) {
2457 /* Dirty tracking must be enabled for DCC usage analysis. */
2458 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2459 vi_separate_dcc_start_query(ctx, rtex);
2460 }
2461 }
2462
2463 if (state->zsbuf) {
2464 surf = (struct r600_surface*)state->zsbuf;
2465 rtex = (struct r600_texture*)surf->base.texture;
2466
2467 if (!surf->depth_initialized) {
2468 si_init_depth_surface(sctx, surf);
2469 }
2470 r600_context_add_resource_size(ctx, surf->base.texture);
2471 }
2472
2473 si_update_poly_offset_state(sctx);
2474 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2475 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2476
2477 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2478 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2479
2480 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2481 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2482 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2483
2484 /* Set sample locations as fragment shader constants. */
2485 switch (sctx->framebuffer.nr_samples) {
2486 case 1:
2487 constbuf.user_buffer = sctx->b.sample_locations_1x;
2488 break;
2489 case 2:
2490 constbuf.user_buffer = sctx->b.sample_locations_2x;
2491 break;
2492 case 4:
2493 constbuf.user_buffer = sctx->b.sample_locations_4x;
2494 break;
2495 case 8:
2496 constbuf.user_buffer = sctx->b.sample_locations_8x;
2497 break;
2498 case 16:
2499 constbuf.user_buffer = sctx->b.sample_locations_16x;
2500 break;
2501 default:
2502 R600_ERR("Requested an invalid number of samples %i.\n",
2503 sctx->framebuffer.nr_samples);
2504 assert(0);
2505 }
2506 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2507 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2508
2509 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2510 }
2511
2512 sctx->need_check_render_feedback = true;
2513 sctx->do_update_shaders = true;
2514 sctx->framebuffer.do_update_surf_dirtiness = true;
2515 }
2516
2517 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2518 {
2519 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2520 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2521 unsigned i, nr_cbufs = state->nr_cbufs;
2522 struct r600_texture *tex = NULL;
2523 struct r600_surface *cb = NULL;
2524 unsigned cb_color_info = 0;
2525
2526 /* Colorbuffers. */
2527 for (i = 0; i < nr_cbufs; i++) {
2528 const struct radeon_surf_level *level_info;
2529 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2530 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2531 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2532
2533 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2534 continue;
2535
2536 cb = (struct r600_surface*)state->cbufs[i];
2537 if (!cb) {
2538 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2539 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2540 continue;
2541 }
2542
2543 tex = (struct r600_texture *)cb->base.texture;
2544 level_info = &tex->surface.level[cb->base.u.tex.level];
2545 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2546 &tex->resource, RADEON_USAGE_READWRITE,
2547 tex->resource.b.b.nr_samples > 1 ?
2548 RADEON_PRIO_COLOR_BUFFER_MSAA :
2549 RADEON_PRIO_COLOR_BUFFER);
2550
2551 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2552 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2553 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2554 RADEON_PRIO_CMASK);
2555 }
2556
2557 if (tex->dcc_separate_buffer)
2558 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2559 tex->dcc_separate_buffer,
2560 RADEON_USAGE_READWRITE,
2561 RADEON_PRIO_DCC);
2562
2563 /* Compute mutable surface parameters. */
2564 pitch_tile_max = level_info->nblk_x / 8 - 1;
2565 slice_tile_max = level_info->nblk_x *
2566 level_info->nblk_y / 64 - 1;
2567 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2568
2569 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2570 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2571 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2572 cb_color_attrib = cb->cb_color_attrib |
2573 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2574
2575 if (tex->fmask.size) {
2576 if (sctx->b.chip_class >= CIK)
2577 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2578 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2579 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2580 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2581 } else {
2582 /* This must be set for fast clear to work without FMASK. */
2583 if (sctx->b.chip_class >= CIK)
2584 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2585 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2586 cb_color_fmask = cb_color_base;
2587 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2588 }
2589
2590 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2591
2592 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2593 bool is_msaa_resolve_dst = state->cbufs[0] &&
2594 state->cbufs[0]->texture->nr_samples > 1 &&
2595 state->cbufs[1] == &cb->base &&
2596 state->cbufs[1]->texture->nr_samples <= 1;
2597
2598 if (!is_msaa_resolve_dst)
2599 cb_color_info |= S_028C70_DCC_ENABLE(1);
2600 }
2601
2602 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2603 sctx->b.chip_class >= VI ? 14 : 13);
2604 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2605 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2606 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2607 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2608 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2609 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2610 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2611 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2612 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2613 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2614 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2615 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2616 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2617
2618 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2619 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2620 tex->dcc_offset +
2621 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2622 }
2623 for (; i < 8 ; i++)
2624 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2625 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2626
2627 /* ZS buffer. */
2628 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2629 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2630 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2631
2632 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2633 &rtex->resource, RADEON_USAGE_READWRITE,
2634 zb->base.texture->nr_samples > 1 ?
2635 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2636 RADEON_PRIO_DEPTH_BUFFER);
2637
2638 if (zb->db_htile_data_base) {
2639 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2640 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2641 RADEON_PRIO_HTILE);
2642 }
2643
2644 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2645 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2646
2647 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2648 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2649 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2650 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2651 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2652 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2653 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2654 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2655 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2656 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2657 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2658
2659 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2660 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2661 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2662
2663 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2664 } else if (sctx->framebuffer.dirty_zsbuf) {
2665 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2666 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2667 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2668 }
2669
2670 /* Framebuffer dimensions. */
2671 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2672 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2673 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2674
2675 sctx->framebuffer.dirty_cbufs = 0;
2676 sctx->framebuffer.dirty_zsbuf = false;
2677 }
2678
2679 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2680 struct r600_atom *atom)
2681 {
2682 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2683 unsigned nr_samples = sctx->framebuffer.nr_samples;
2684
2685 /* Smoothing (only possible with nr_samples == 1) uses the same
2686 * sample locations as the MSAA it simulates.
2687 */
2688 if (nr_samples <= 1 && sctx->smoothing_enabled)
2689 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2690
2691 /* On Polaris, the small primitive filter uses the sample locations
2692 * even when MSAA is off, so we need to make sure they're set to 0.
2693 */
2694 if (sctx->b.family >= CHIP_POLARIS10)
2695 nr_samples = MAX2(nr_samples, 1);
2696
2697 if (nr_samples >= 1 &&
2698 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2699 sctx->msaa_sample_locs.nr_samples = nr_samples;
2700 cayman_emit_msaa_sample_locs(cs, nr_samples);
2701 }
2702
2703 if (sctx->b.family >= CHIP_POLARIS10) {
2704 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2705 unsigned small_prim_filter_cntl =
2706 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2707 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2708
2709 /* The alternative of setting sample locations to 0 would
2710 * require a DB flush to avoid Z errors, see
2711 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2712 */
2713 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2714 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2715
2716 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2717 small_prim_filter_cntl);
2718 }
2719 }
2720
2721 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2722 {
2723 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2724 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2725 /* 33% faster rendering to linear color buffers */
2726 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2727 unsigned sc_mode_cntl_1 =
2728 S_028A4C_WALK_SIZE(dst_is_linear) |
2729 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2730 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2731 /* always 1: */
2732 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2733 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2734 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2735 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2736 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2737 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2738
2739 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2740 sctx->ps_iter_samples,
2741 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2742 sc_mode_cntl_1);
2743 }
2744
2745 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2746 {
2747 struct si_context *sctx = (struct si_context *)ctx;
2748
2749 if (sctx->ps_iter_samples == min_samples)
2750 return;
2751
2752 sctx->ps_iter_samples = min_samples;
2753 sctx->do_update_shaders = true;
2754
2755 if (sctx->framebuffer.nr_samples > 1)
2756 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2757 }
2758
2759 /*
2760 * Samplers
2761 */
2762
2763 /**
2764 * Build the sampler view descriptor for a buffer texture.
2765 * @param state 256-bit descriptor; only the high 128 bits are filled in
2766 */
2767 void
2768 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2769 enum pipe_format format,
2770 unsigned offset, unsigned size,
2771 uint32_t *state)
2772 {
2773 const struct util_format_description *desc;
2774 int first_non_void;
2775 unsigned stride;
2776 unsigned num_records;
2777 unsigned num_format, data_format;
2778
2779 desc = util_format_description(format);
2780 first_non_void = util_format_get_first_non_void_channel(format);
2781 stride = desc->block.bits / 8;
2782 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2783 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2784
2785 num_records = size / stride;
2786 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2787
2788 if (screen->b.chip_class >= VI)
2789 num_records *= stride;
2790
2791 state[4] = 0;
2792 state[5] = S_008F04_STRIDE(stride);
2793 state[6] = num_records;
2794 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2795 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2796 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2797 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2798 S_008F0C_NUM_FORMAT(num_format) |
2799 S_008F0C_DATA_FORMAT(data_format);
2800 }
2801
2802 /**
2803 * Build the sampler view descriptor for a texture.
2804 */
2805 void
2806 si_make_texture_descriptor(struct si_screen *screen,
2807 struct r600_texture *tex,
2808 bool sampler,
2809 enum pipe_texture_target target,
2810 enum pipe_format pipe_format,
2811 const unsigned char state_swizzle[4],
2812 unsigned first_level, unsigned last_level,
2813 unsigned first_layer, unsigned last_layer,
2814 unsigned width, unsigned height, unsigned depth,
2815 uint32_t *state,
2816 uint32_t *fmask_state)
2817 {
2818 struct pipe_resource *res = &tex->resource.b.b;
2819 const struct util_format_description *desc;
2820 unsigned char swizzle[4];
2821 int first_non_void;
2822 unsigned num_format, data_format, type;
2823 uint64_t va;
2824
2825 desc = util_format_description(pipe_format);
2826
2827 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2828 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2829 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2830 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
2831
2832 switch (pipe_format) {
2833 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2834 case PIPE_FORMAT_X32_S8X24_UINT:
2835 case PIPE_FORMAT_X8Z24_UNORM:
2836 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2837 break;
2838 case PIPE_FORMAT_X24S8_UINT:
2839 /*
2840 * X24S8 is implemented as an 8_8_8_8 data format, to
2841 * fix texture gathers. This affects at least
2842 * GL45-CTS.texture_cube_map_array.sampling on VI.
2843 */
2844 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
2845 break;
2846 default:
2847 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2848 }
2849 } else {
2850 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2851 }
2852
2853 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2854
2855 switch (pipe_format) {
2856 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2857 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2858 break;
2859 default:
2860 if (first_non_void < 0) {
2861 if (util_format_is_compressed(pipe_format)) {
2862 switch (pipe_format) {
2863 case PIPE_FORMAT_DXT1_SRGB:
2864 case PIPE_FORMAT_DXT1_SRGBA:
2865 case PIPE_FORMAT_DXT3_SRGBA:
2866 case PIPE_FORMAT_DXT5_SRGBA:
2867 case PIPE_FORMAT_BPTC_SRGBA:
2868 case PIPE_FORMAT_ETC2_SRGB8:
2869 case PIPE_FORMAT_ETC2_SRGB8A1:
2870 case PIPE_FORMAT_ETC2_SRGBA8:
2871 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2872 break;
2873 case PIPE_FORMAT_RGTC1_SNORM:
2874 case PIPE_FORMAT_LATC1_SNORM:
2875 case PIPE_FORMAT_RGTC2_SNORM:
2876 case PIPE_FORMAT_LATC2_SNORM:
2877 case PIPE_FORMAT_ETC2_R11_SNORM:
2878 case PIPE_FORMAT_ETC2_RG11_SNORM:
2879 /* implies float, so use SNORM/UNORM to determine
2880 whether data is signed or not */
2881 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2882 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2883 break;
2884 default:
2885 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2886 break;
2887 }
2888 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2889 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2890 } else {
2891 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2892 }
2893 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2894 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2895 } else {
2896 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2897
2898 switch (desc->channel[first_non_void].type) {
2899 case UTIL_FORMAT_TYPE_FLOAT:
2900 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2901 break;
2902 case UTIL_FORMAT_TYPE_SIGNED:
2903 if (desc->channel[first_non_void].normalized)
2904 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2905 else if (desc->channel[first_non_void].pure_integer)
2906 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2907 else
2908 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2909 break;
2910 case UTIL_FORMAT_TYPE_UNSIGNED:
2911 if (desc->channel[first_non_void].normalized)
2912 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2913 else if (desc->channel[first_non_void].pure_integer)
2914 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2915 else
2916 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2917 }
2918 }
2919 }
2920
2921 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2922 if (data_format == ~0) {
2923 data_format = 0;
2924 }
2925
2926 if (!sampler &&
2927 (res->target == PIPE_TEXTURE_CUBE ||
2928 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2929 res->target == PIPE_TEXTURE_3D)) {
2930 /* For the purpose of shader images, treat cube maps and 3D
2931 * textures as 2D arrays. For 3D textures, the address
2932 * calculations for mipmaps are different, so we rely on the
2933 * caller to effectively disable mipmaps.
2934 */
2935 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2936
2937 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2938 } else {
2939 type = si_tex_dim(res->target, target, res->nr_samples);
2940 }
2941
2942 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2943 height = 1;
2944 depth = res->array_size;
2945 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2946 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2947 if (sampler || res->target != PIPE_TEXTURE_3D)
2948 depth = res->array_size;
2949 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2950 depth = res->array_size / 6;
2951
2952 state[0] = 0;
2953 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2954 S_008F14_NUM_FORMAT(num_format));
2955 state[2] = (S_008F18_WIDTH(width - 1) |
2956 S_008F18_HEIGHT(height - 1) |
2957 S_008F18_PERF_MOD(4));
2958 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2959 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2960 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2961 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2962 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2963 0 : first_level) |
2964 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2965 util_logbase2(res->nr_samples) :
2966 last_level) |
2967 S_008F1C_POW2_PAD(res->last_level > 0) |
2968 S_008F1C_TYPE(type));
2969 state[4] = S_008F20_DEPTH(depth - 1);
2970 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2971 S_008F24_LAST_ARRAY(last_layer));
2972 state[6] = 0;
2973 state[7] = 0;
2974
2975 if (tex->dcc_offset) {
2976 unsigned swap = r600_translate_colorswap(pipe_format, false);
2977
2978 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2979 } else {
2980 /* The last dword is unused by hw. The shader uses it to clear
2981 * bits in the first dword of sampler state.
2982 */
2983 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2984 if (first_level == last_level)
2985 state[7] = C_008F30_MAX_ANISO_RATIO;
2986 else
2987 state[7] = 0xffffffff;
2988 }
2989 }
2990
2991 /* Initialize the sampler view for FMASK. */
2992 if (tex->fmask.size) {
2993 uint32_t fmask_format;
2994
2995 va = tex->resource.gpu_address + tex->fmask.offset;
2996
2997 switch (res->nr_samples) {
2998 case 2:
2999 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3000 break;
3001 case 4:
3002 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3003 break;
3004 case 8:
3005 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3006 break;
3007 default:
3008 assert(0);
3009 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
3010 }
3011
3012 fmask_state[0] = va >> 8;
3013 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3014 S_008F14_DATA_FORMAT(fmask_format) |
3015 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
3016 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3017 S_008F18_HEIGHT(height - 1);
3018 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3019 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3020 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3021 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3022 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3023 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3024 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3025 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3026 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3027 S_008F24_LAST_ARRAY(last_layer);
3028 fmask_state[6] = 0;
3029 fmask_state[7] = 0;
3030 }
3031 }
3032
3033 /**
3034 * Create a sampler view.
3035 *
3036 * @param ctx context
3037 * @param texture texture
3038 * @param state sampler view template
3039 * @param width0 width0 override (for compressed textures as int)
3040 * @param height0 height0 override (for compressed textures as int)
3041 * @param force_level set the base address to the level (for compressed textures)
3042 */
3043 struct pipe_sampler_view *
3044 si_create_sampler_view_custom(struct pipe_context *ctx,
3045 struct pipe_resource *texture,
3046 const struct pipe_sampler_view *state,
3047 unsigned width0, unsigned height0,
3048 unsigned force_level)
3049 {
3050 struct si_context *sctx = (struct si_context*)ctx;
3051 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3052 struct r600_texture *tmp = (struct r600_texture*)texture;
3053 unsigned base_level, first_level, last_level;
3054 unsigned char state_swizzle[4];
3055 unsigned height, depth, width;
3056 unsigned last_layer = state->u.tex.last_layer;
3057 enum pipe_format pipe_format;
3058 const struct radeon_surf_level *surflevel;
3059
3060 if (!view)
3061 return NULL;
3062
3063 /* initialize base object */
3064 view->base = *state;
3065 view->base.texture = NULL;
3066 view->base.reference.count = 1;
3067 view->base.context = ctx;
3068
3069 assert(texture);
3070 pipe_resource_reference(&view->base.texture, texture);
3071
3072 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3073 state->format == PIPE_FORMAT_S8X24_UINT ||
3074 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3075 state->format == PIPE_FORMAT_S8_UINT)
3076 view->is_stencil_sampler = true;
3077
3078 /* Buffer resource. */
3079 if (texture->target == PIPE_BUFFER) {
3080 si_make_buffer_descriptor(sctx->screen,
3081 (struct r600_resource *)texture,
3082 state->format,
3083 state->u.buf.offset,
3084 state->u.buf.size,
3085 view->state);
3086 return &view->base;
3087 }
3088
3089 state_swizzle[0] = state->swizzle_r;
3090 state_swizzle[1] = state->swizzle_g;
3091 state_swizzle[2] = state->swizzle_b;
3092 state_swizzle[3] = state->swizzle_a;
3093
3094 base_level = 0;
3095 first_level = state->u.tex.first_level;
3096 last_level = state->u.tex.last_level;
3097 width = width0;
3098 height = height0;
3099 depth = texture->depth0;
3100
3101 if (force_level) {
3102 assert(force_level == first_level &&
3103 force_level == last_level);
3104 base_level = force_level;
3105 first_level = 0;
3106 last_level = 0;
3107 width = u_minify(width, force_level);
3108 height = u_minify(height, force_level);
3109 depth = u_minify(depth, force_level);
3110 }
3111
3112 /* This is not needed if state trackers set last_layer correctly. */
3113 if (state->target == PIPE_TEXTURE_1D ||
3114 state->target == PIPE_TEXTURE_2D ||
3115 state->target == PIPE_TEXTURE_RECT ||
3116 state->target == PIPE_TEXTURE_CUBE)
3117 last_layer = state->u.tex.first_layer;
3118
3119 /* Texturing with separate depth and stencil. */
3120 pipe_format = state->format;
3121
3122 /* Depth/stencil texturing sometimes needs separate texture. */
3123 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3124 if (!tmp->flushed_depth_texture &&
3125 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3126 pipe_resource_reference(&view->base.texture, NULL);
3127 FREE(view);
3128 return NULL;
3129 }
3130
3131 assert(tmp->flushed_depth_texture);
3132
3133 /* Override format for the case where the flushed texture
3134 * contains only Z or only S.
3135 */
3136 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3137 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3138
3139 tmp = tmp->flushed_depth_texture;
3140 }
3141
3142 surflevel = tmp->surface.level;
3143
3144 if (tmp->db_compatible) {
3145 if (!view->is_stencil_sampler)
3146 pipe_format = tmp->db_render_format;
3147
3148 switch (pipe_format) {
3149 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3150 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3151 break;
3152 case PIPE_FORMAT_X8Z24_UNORM:
3153 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3154 /* Z24 is always stored like this for DB
3155 * compatibility.
3156 */
3157 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3158 break;
3159 case PIPE_FORMAT_X24S8_UINT:
3160 case PIPE_FORMAT_S8X24_UINT:
3161 case PIPE_FORMAT_X32_S8X24_UINT:
3162 pipe_format = PIPE_FORMAT_S8_UINT;
3163 surflevel = tmp->surface.stencil_level;
3164 break;
3165 default:;
3166 }
3167 }
3168
3169 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3170 state->u.tex.first_level,
3171 state->format);
3172
3173 si_make_texture_descriptor(sctx->screen, tmp, true,
3174 state->target, pipe_format, state_swizzle,
3175 first_level, last_level,
3176 state->u.tex.first_layer, last_layer,
3177 width, height, depth,
3178 view->state, view->fmask_state);
3179
3180 view->base_level_info = &surflevel[base_level];
3181 view->base_level = base_level;
3182 view->block_width = util_format_get_blockwidth(pipe_format);
3183 return &view->base;
3184 }
3185
3186 static struct pipe_sampler_view *
3187 si_create_sampler_view(struct pipe_context *ctx,
3188 struct pipe_resource *texture,
3189 const struct pipe_sampler_view *state)
3190 {
3191 return si_create_sampler_view_custom(ctx, texture, state,
3192 texture ? texture->width0 : 0,
3193 texture ? texture->height0 : 0, 0);
3194 }
3195
3196 static void si_sampler_view_destroy(struct pipe_context *ctx,
3197 struct pipe_sampler_view *state)
3198 {
3199 struct si_sampler_view *view = (struct si_sampler_view *)state;
3200
3201 pipe_resource_reference(&state->texture, NULL);
3202 FREE(view);
3203 }
3204
3205 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3206 {
3207 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3208 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3209 (linear_filter &&
3210 (wrap == PIPE_TEX_WRAP_CLAMP ||
3211 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3212 }
3213
3214 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3215 {
3216 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3217 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3218
3219 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3220 state->border_color.ui[2] || state->border_color.ui[3]) &&
3221 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3222 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3223 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3224 }
3225
3226 static void *si_create_sampler_state(struct pipe_context *ctx,
3227 const struct pipe_sampler_state *state)
3228 {
3229 struct si_context *sctx = (struct si_context *)ctx;
3230 struct r600_common_screen *rscreen = sctx->b.screen;
3231 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3232 unsigned border_color_type, border_color_index = 0;
3233 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3234 : state->max_anisotropy;
3235 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3236
3237 if (!rstate) {
3238 return NULL;
3239 }
3240
3241 if (!sampler_state_needs_border_color(state))
3242 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3243 else if (state->border_color.f[0] == 0 &&
3244 state->border_color.f[1] == 0 &&
3245 state->border_color.f[2] == 0 &&
3246 state->border_color.f[3] == 0)
3247 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3248 else if (state->border_color.f[0] == 0 &&
3249 state->border_color.f[1] == 0 &&
3250 state->border_color.f[2] == 0 &&
3251 state->border_color.f[3] == 1)
3252 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3253 else if (state->border_color.f[0] == 1 &&
3254 state->border_color.f[1] == 1 &&
3255 state->border_color.f[2] == 1 &&
3256 state->border_color.f[3] == 1)
3257 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3258 else {
3259 int i;
3260
3261 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3262
3263 /* Check if the border has been uploaded already. */
3264 for (i = 0; i < sctx->border_color_count; i++)
3265 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3266 sizeof(state->border_color)) == 0)
3267 break;
3268
3269 if (i >= SI_MAX_BORDER_COLORS) {
3270 /* Getting 4096 unique border colors is very unlikely. */
3271 fprintf(stderr, "radeonsi: The border color table is full. "
3272 "Any new border colors will be just black. "
3273 "Please file a bug.\n");
3274 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3275 } else {
3276 if (i == sctx->border_color_count) {
3277 /* Upload a new border color. */
3278 memcpy(&sctx->border_color_table[i], &state->border_color,
3279 sizeof(state->border_color));
3280 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3281 &state->border_color,
3282 sizeof(state->border_color));
3283 sctx->border_color_count++;
3284 }
3285
3286 border_color_index = i;
3287 }
3288 }
3289
3290 #ifdef DEBUG
3291 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3292 #endif
3293 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3294 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3295 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3296 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3297 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3298 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3299 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3300 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3301 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3302 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3303 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3304 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3305 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3306 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3307 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3308 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3309 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3310 S_008F38_MIP_POINT_PRECLAMP(1) |
3311 S_008F38_DISABLE_LSB_CEIL(1) |
3312 S_008F38_FILTER_PREC_FIX(1) |
3313 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3314 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3315 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3316 return rstate;
3317 }
3318
3319 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3320 {
3321 struct si_context *sctx = (struct si_context *)ctx;
3322
3323 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3324 return;
3325
3326 sctx->sample_mask.sample_mask = sample_mask;
3327 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3328 }
3329
3330 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3331 {
3332 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3333 unsigned mask = sctx->sample_mask.sample_mask;
3334
3335 /* Needed for line and polygon smoothing as well as for the Polaris
3336 * small primitive filter. We expect the state tracker to take care of
3337 * this for us.
3338 */
3339 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3340 (mask & 1 && sctx->blitter->running));
3341
3342 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3343 radeon_emit(cs, mask | (mask << 16));
3344 radeon_emit(cs, mask | (mask << 16));
3345 }
3346
3347 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3348 {
3349 #ifdef DEBUG
3350 struct si_sampler_state *s = state;
3351
3352 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3353 s->magic = 0;
3354 #endif
3355 free(state);
3356 }
3357
3358 /*
3359 * Vertex elements & buffers
3360 */
3361
3362 static void *si_create_vertex_elements(struct pipe_context *ctx,
3363 unsigned count,
3364 const struct pipe_vertex_element *elements)
3365 {
3366 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3367 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3368 int i;
3369
3370 assert(count <= SI_MAX_ATTRIBS);
3371 if (!v)
3372 return NULL;
3373
3374 v->count = count;
3375 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3376
3377 for (i = 0; i < count; ++i) {
3378 const struct util_format_description *desc;
3379 const struct util_format_channel_description *channel;
3380 unsigned data_format, num_format;
3381 int first_non_void;
3382 unsigned vbo_index = elements[i].vertex_buffer_index;
3383 unsigned char swizzle[4];
3384
3385 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3386 FREE(v);
3387 return NULL;
3388 }
3389
3390 if (!used[vbo_index]) {
3391 v->first_vb_use_mask |= 1 << i;
3392 used[vbo_index] = true;
3393 }
3394
3395 desc = util_format_description(elements[i].src_format);
3396 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3397 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3398 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3399 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3400 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3401
3402 v->format_size[i] = desc->block.bits / 8;
3403
3404 /* The hardware always treats the 2-bit alpha channel as
3405 * unsigned, so a shader workaround is needed.
3406 */
3407 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3408 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3409 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3410 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3411 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3412 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3413 /* This isn't actually used in OpenGL. */
3414 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3415 }
3416 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3417 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3418 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3419 else
3420 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3421 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3422 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3423 if (channel->normalized) {
3424 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3425 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3426 else
3427 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3428 } else {
3429 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3430 }
3431 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3432 if (channel->normalized) {
3433 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3434 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3435 else
3436 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3437 } else {
3438 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3439 }
3440 }
3441 } else if (channel && channel->size == 64 &&
3442 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3443 switch (desc->nr_channels) {
3444 case 1:
3445 case 2:
3446 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3447 swizzle[0] = PIPE_SWIZZLE_X;
3448 swizzle[1] = PIPE_SWIZZLE_Y;
3449 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3450 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3451 break;
3452 case 3:
3453 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3454 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3455 swizzle[1] = PIPE_SWIZZLE_Y;
3456 swizzle[2] = PIPE_SWIZZLE_0;
3457 swizzle[3] = PIPE_SWIZZLE_0;
3458 break;
3459 case 4:
3460 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3461 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3462 swizzle[1] = PIPE_SWIZZLE_Y;
3463 swizzle[2] = PIPE_SWIZZLE_Z;
3464 swizzle[3] = PIPE_SWIZZLE_W;
3465 break;
3466 default:
3467 assert(0);
3468 }
3469 } else if (channel && desc->nr_channels == 3) {
3470 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3471
3472 if (channel->size == 8) {
3473 if (channel->pure_integer)
3474 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3475 else
3476 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3477 } else if (channel->size == 16) {
3478 if (channel->pure_integer)
3479 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3480 else
3481 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3482 }
3483 }
3484
3485 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3486 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3487 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3488 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3489 S_008F0C_NUM_FORMAT(num_format) |
3490 S_008F0C_DATA_FORMAT(data_format);
3491 }
3492 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3493
3494 return v;
3495 }
3496
3497 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3498 {
3499 struct si_context *sctx = (struct si_context *)ctx;
3500 struct si_vertex_element *v = (struct si_vertex_element*)state;
3501
3502 sctx->vertex_elements = v;
3503 sctx->vertex_buffers_dirty = true;
3504 sctx->do_update_shaders = true;
3505 }
3506
3507 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3508 {
3509 struct si_context *sctx = (struct si_context *)ctx;
3510
3511 if (sctx->vertex_elements == state)
3512 sctx->vertex_elements = NULL;
3513 FREE(state);
3514 }
3515
3516 static void si_set_vertex_buffers(struct pipe_context *ctx,
3517 unsigned start_slot, unsigned count,
3518 const struct pipe_vertex_buffer *buffers)
3519 {
3520 struct si_context *sctx = (struct si_context *)ctx;
3521 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3522 int i;
3523
3524 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3525
3526 if (buffers) {
3527 for (i = 0; i < count; i++) {
3528 const struct pipe_vertex_buffer *src = buffers + i;
3529 struct pipe_vertex_buffer *dsti = dst + i;
3530
3531 if (unlikely(src->user_buffer)) {
3532 /* Zero-stride attribs only. */
3533 assert(src->stride == 0);
3534
3535 /* Assume the attrib has 4 dwords like the vbo
3536 * module. This is also a good upper bound.
3537 *
3538 * Use const_uploader to upload into VRAM directly.
3539 */
3540 u_upload_data(sctx->b.b.const_uploader, 0, 16, 16,
3541 src->user_buffer,
3542 &dsti->buffer_offset,
3543 &dsti->buffer);
3544 dsti->stride = 0;
3545 } else {
3546 struct pipe_resource *buf = src->buffer;
3547
3548 pipe_resource_reference(&dsti->buffer, buf);
3549 dsti->buffer_offset = src->buffer_offset;
3550 dsti->stride = src->stride;
3551 r600_context_add_resource_size(ctx, buf);
3552 if (buf)
3553 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3554 }
3555 }
3556 } else {
3557 for (i = 0; i < count; i++) {
3558 pipe_resource_reference(&dst[i].buffer, NULL);
3559 }
3560 }
3561 sctx->vertex_buffers_dirty = true;
3562 }
3563
3564 static void si_set_index_buffer(struct pipe_context *ctx,
3565 const struct pipe_index_buffer *ib)
3566 {
3567 struct si_context *sctx = (struct si_context *)ctx;
3568
3569 if (ib) {
3570 struct pipe_resource *buf = ib->buffer;
3571
3572 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3573 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3574 r600_context_add_resource_size(ctx, buf);
3575 if (buf)
3576 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3577 } else {
3578 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3579 }
3580 }
3581
3582 /*
3583 * Misc
3584 */
3585
3586 static void si_set_tess_state(struct pipe_context *ctx,
3587 const float default_outer_level[4],
3588 const float default_inner_level[2])
3589 {
3590 struct si_context *sctx = (struct si_context *)ctx;
3591 struct pipe_constant_buffer cb;
3592 float array[8];
3593
3594 memcpy(array, default_outer_level, sizeof(float) * 4);
3595 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3596
3597 cb.buffer = NULL;
3598 cb.user_buffer = NULL;
3599 cb.buffer_size = sizeof(array);
3600
3601 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3602 (void*)array, sizeof(array),
3603 &cb.buffer_offset);
3604
3605 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3606 pipe_resource_reference(&cb.buffer, NULL);
3607 }
3608
3609 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3610 {
3611 struct si_context *sctx = (struct si_context *)ctx;
3612
3613 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3614 SI_CONTEXT_INV_GLOBAL_L2 |
3615 SI_CONTEXT_FLUSH_AND_INV_CB;
3616 sctx->framebuffer.do_update_surf_dirtiness = true;
3617 }
3618
3619 /* This only ensures coherency for shader image/buffer stores. */
3620 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3621 {
3622 struct si_context *sctx = (struct si_context *)ctx;
3623
3624 /* Subsequent commands must wait for all shader invocations to
3625 * complete. */
3626 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3627 SI_CONTEXT_CS_PARTIAL_FLUSH;
3628
3629 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3630 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3631 SI_CONTEXT_INV_VMEM_L1;
3632
3633 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3634 PIPE_BARRIER_SHADER_BUFFER |
3635 PIPE_BARRIER_TEXTURE |
3636 PIPE_BARRIER_IMAGE |
3637 PIPE_BARRIER_STREAMOUT_BUFFER |
3638 PIPE_BARRIER_GLOBAL_BUFFER)) {
3639 /* As far as I can tell, L1 contents are written back to L2
3640 * automatically at end of shader, but the contents of other
3641 * L1 caches might still be stale. */
3642 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3643 }
3644
3645 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3646 /* Indices are read through TC L2 since VI.
3647 * L1 isn't used.
3648 */
3649 if (sctx->screen->b.chip_class <= CIK)
3650 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3651 }
3652
3653 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3654 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3655 SI_CONTEXT_FLUSH_AND_INV_DB;
3656
3657 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3658 PIPE_BARRIER_INDIRECT_BUFFER))
3659 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3660 }
3661
3662 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3663 {
3664 struct pipe_blend_state blend;
3665
3666 memset(&blend, 0, sizeof(blend));
3667 blend.independent_blend_enable = true;
3668 blend.rt[0].colormask = 0xf;
3669 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3670 }
3671
3672 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3673 bool include_draw_vbo)
3674 {
3675 si_need_cs_space((struct si_context*)ctx);
3676 }
3677
3678 static void si_init_config(struct si_context *sctx);
3679
3680 void si_init_state_functions(struct si_context *sctx)
3681 {
3682 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3683 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3684 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3685 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3686 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3687
3688 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3689 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3690 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3691 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3692 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3693 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3694 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3695 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3696 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3697 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3698
3699 sctx->b.b.create_blend_state = si_create_blend_state;
3700 sctx->b.b.bind_blend_state = si_bind_blend_state;
3701 sctx->b.b.delete_blend_state = si_delete_blend_state;
3702 sctx->b.b.set_blend_color = si_set_blend_color;
3703
3704 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3705 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3706 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3707
3708 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3709 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3710 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3711
3712 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3713 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3714 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3715 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3716 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3717
3718 sctx->b.b.set_clip_state = si_set_clip_state;
3719 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3720
3721 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3722 sctx->b.b.get_sample_position = cayman_get_sample_position;
3723
3724 sctx->b.b.create_sampler_state = si_create_sampler_state;
3725 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3726
3727 sctx->b.b.create_sampler_view = si_create_sampler_view;
3728 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3729
3730 sctx->b.b.set_sample_mask = si_set_sample_mask;
3731
3732 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3733 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3734 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3735 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3736 sctx->b.b.set_index_buffer = si_set_index_buffer;
3737
3738 sctx->b.b.texture_barrier = si_texture_barrier;
3739 sctx->b.b.memory_barrier = si_memory_barrier;
3740 sctx->b.b.set_min_samples = si_set_min_samples;
3741 sctx->b.b.set_tess_state = si_set_tess_state;
3742
3743 sctx->b.b.set_active_query_state = si_set_active_query_state;
3744 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3745 sctx->b.save_qbo_state = si_save_qbo_state;
3746 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3747
3748 sctx->b.b.draw_vbo = si_draw_vbo;
3749
3750 si_init_config(sctx);
3751 }
3752
3753 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3754 {
3755 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3756 }
3757
3758 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3759 struct r600_texture *rtex,
3760 struct radeon_bo_metadata *md)
3761 {
3762 struct si_screen *sscreen = (struct si_screen*)rscreen;
3763 struct pipe_resource *res = &rtex->resource.b.b;
3764 static const unsigned char swizzle[] = {
3765 PIPE_SWIZZLE_X,
3766 PIPE_SWIZZLE_Y,
3767 PIPE_SWIZZLE_Z,
3768 PIPE_SWIZZLE_W
3769 };
3770 uint32_t desc[8], i;
3771 bool is_array = util_resource_is_array_texture(res);
3772
3773 /* DRM 2.x.x doesn't support this. */
3774 if (rscreen->info.drm_major != 3)
3775 return;
3776
3777 assert(rtex->dcc_separate_buffer == NULL);
3778 assert(rtex->fmask.size == 0);
3779
3780 /* Metadata image format format version 1:
3781 * [0] = 1 (metadata format identifier)
3782 * [1] = (VENDOR_ID << 16) | PCI_ID
3783 * [2:9] = image descriptor for the whole resource
3784 * [2] is always 0, because the base address is cleared
3785 * [9] is the DCC offset bits [39:8] from the beginning of
3786 * the buffer
3787 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3788 */
3789
3790 md->metadata[0] = 1; /* metadata image format version 1 */
3791
3792 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3793 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3794
3795 si_make_texture_descriptor(sscreen, rtex, true,
3796 res->target, res->format,
3797 swizzle, 0, res->last_level, 0,
3798 is_array ? res->array_size - 1 : 0,
3799 res->width0, res->height0, res->depth0,
3800 desc, NULL);
3801
3802 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3803 rtex->surface.blk_w, false, desc);
3804
3805 /* Clear the base address and set the relative DCC offset. */
3806 desc[0] = 0;
3807 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3808 desc[7] = rtex->dcc_offset >> 8;
3809
3810 /* Dwords [2:9] contain the image descriptor. */
3811 memcpy(&md->metadata[2], desc, sizeof(desc));
3812
3813 /* Dwords [10:..] contain the mipmap level offsets. */
3814 for (i = 0; i <= res->last_level; i++)
3815 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3816
3817 md->size_metadata = (11 + res->last_level) * 4;
3818 }
3819
3820 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3821 struct r600_texture *rtex,
3822 struct radeon_bo_metadata *md)
3823 {
3824 uint32_t *desc = &md->metadata[2];
3825
3826 if (rscreen->chip_class < VI)
3827 return;
3828
3829 /* Return if DCC is enabled. The texture should be set up with it
3830 * already.
3831 */
3832 if (md->size_metadata >= 11 * 4 &&
3833 md->metadata[0] != 0 &&
3834 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3835 G_008F28_COMPRESSION_EN(desc[6])) {
3836 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3837 return;
3838 }
3839
3840 /* Disable DCC. These are always set by texture_from_handle and must
3841 * be cleared here.
3842 */
3843 rtex->dcc_offset = 0;
3844 }
3845
3846 void si_init_screen_state_functions(struct si_screen *sscreen)
3847 {
3848 sscreen->b.b.is_format_supported = si_is_format_supported;
3849 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3850 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3851 }
3852
3853 static void
3854 si_write_harvested_raster_configs(struct si_context *sctx,
3855 struct si_pm4_state *pm4,
3856 unsigned raster_config,
3857 unsigned raster_config_1)
3858 {
3859 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3860 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3861 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3862 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3863 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3864 unsigned rb_per_se = num_rb / num_se;
3865 unsigned se_mask[4];
3866 unsigned se;
3867
3868 se_mask[0] = ((1 << rb_per_se) - 1);
3869 se_mask[1] = (se_mask[0] << rb_per_se);
3870 se_mask[2] = (se_mask[1] << rb_per_se);
3871 se_mask[3] = (se_mask[2] << rb_per_se);
3872
3873 se_mask[0] &= rb_mask;
3874 se_mask[1] &= rb_mask;
3875 se_mask[2] &= rb_mask;
3876 se_mask[3] &= rb_mask;
3877
3878 assert(num_se == 1 || num_se == 2 || num_se == 4);
3879 assert(sh_per_se == 1 || sh_per_se == 2);
3880 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3881
3882 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3883 * fields are for, so I'm leaving them as their default
3884 * values. */
3885
3886 for (se = 0; se < num_se; se++) {
3887 unsigned raster_config_se = raster_config;
3888 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3889 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3890 int idx = (se / 2) * 2;
3891
3892 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3893 raster_config_se &= C_028350_SE_MAP;
3894
3895 if (!se_mask[idx]) {
3896 raster_config_se |=
3897 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3898 } else {
3899 raster_config_se |=
3900 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3901 }
3902 }
3903
3904 pkr0_mask &= rb_mask;
3905 pkr1_mask &= rb_mask;
3906 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3907 raster_config_se &= C_028350_PKR_MAP;
3908
3909 if (!pkr0_mask) {
3910 raster_config_se |=
3911 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3912 } else {
3913 raster_config_se |=
3914 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3915 }
3916 }
3917
3918 if (rb_per_se >= 2) {
3919 unsigned rb0_mask = 1 << (se * rb_per_se);
3920 unsigned rb1_mask = rb0_mask << 1;
3921
3922 rb0_mask &= rb_mask;
3923 rb1_mask &= rb_mask;
3924 if (!rb0_mask || !rb1_mask) {
3925 raster_config_se &= C_028350_RB_MAP_PKR0;
3926
3927 if (!rb0_mask) {
3928 raster_config_se |=
3929 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3930 } else {
3931 raster_config_se |=
3932 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3933 }
3934 }
3935
3936 if (rb_per_se > 2) {
3937 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3938 rb1_mask = rb0_mask << 1;
3939 rb0_mask &= rb_mask;
3940 rb1_mask &= rb_mask;
3941 if (!rb0_mask || !rb1_mask) {
3942 raster_config_se &= C_028350_RB_MAP_PKR1;
3943
3944 if (!rb0_mask) {
3945 raster_config_se |=
3946 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3947 } else {
3948 raster_config_se |=
3949 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3950 }
3951 }
3952 }
3953 }
3954
3955 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3956 if (sctx->b.chip_class < CIK)
3957 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3958 SE_INDEX(se) | SH_BROADCAST_WRITES |
3959 INSTANCE_BROADCAST_WRITES);
3960 else
3961 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3962 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3963 S_030800_INSTANCE_BROADCAST_WRITES(1));
3964 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3965 }
3966
3967 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3968 if (sctx->b.chip_class < CIK)
3969 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3970 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3971 INSTANCE_BROADCAST_WRITES);
3972 else {
3973 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3974 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3975 S_030800_INSTANCE_BROADCAST_WRITES(1));
3976
3977 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3978 (!se_mask[2] && !se_mask[3]))) {
3979 raster_config_1 &= C_028354_SE_PAIR_MAP;
3980
3981 if (!se_mask[0] && !se_mask[1]) {
3982 raster_config_1 |=
3983 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3984 } else {
3985 raster_config_1 |=
3986 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3987 }
3988 }
3989
3990 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3991 }
3992 }
3993
3994 static void si_init_config(struct si_context *sctx)
3995 {
3996 struct si_screen *sscreen = sctx->screen;
3997 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3998 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3999 unsigned raster_config, raster_config_1;
4000 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4001 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4002
4003 if (!pm4)
4004 return;
4005
4006 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4007 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4008 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4009 si_pm4_cmd_end(pm4, false);
4010
4011 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4012 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4013
4014 /* FIXME calculate these values somehow ??? */
4015 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4016 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4017 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4018
4019 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4020 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4021
4022 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4023 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4024 if (sctx->b.chip_class < CIK)
4025 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4026 S_008A14_CLIP_VTX_REORDER_ENA(1));
4027
4028 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4029 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4030
4031 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4032
4033 switch (sctx->screen->b.family) {
4034 case CHIP_TAHITI:
4035 case CHIP_PITCAIRN:
4036 raster_config = 0x2a00126a;
4037 raster_config_1 = 0x00000000;
4038 break;
4039 case CHIP_VERDE:
4040 raster_config = 0x0000124a;
4041 raster_config_1 = 0x00000000;
4042 break;
4043 case CHIP_OLAND:
4044 raster_config = 0x00000082;
4045 raster_config_1 = 0x00000000;
4046 break;
4047 case CHIP_HAINAN:
4048 raster_config = 0x00000000;
4049 raster_config_1 = 0x00000000;
4050 break;
4051 case CHIP_BONAIRE:
4052 raster_config = 0x16000012;
4053 raster_config_1 = 0x00000000;
4054 break;
4055 case CHIP_HAWAII:
4056 raster_config = 0x3a00161a;
4057 raster_config_1 = 0x0000002e;
4058 break;
4059 case CHIP_FIJI:
4060 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4061 /* old kernels with old tiling config */
4062 raster_config = 0x16000012;
4063 raster_config_1 = 0x0000002a;
4064 } else {
4065 raster_config = 0x3a00161a;
4066 raster_config_1 = 0x0000002e;
4067 }
4068 break;
4069 case CHIP_POLARIS10:
4070 raster_config = 0x16000012;
4071 raster_config_1 = 0x0000002a;
4072 break;
4073 case CHIP_POLARIS11:
4074 case CHIP_POLARIS12:
4075 raster_config = 0x16000012;
4076 raster_config_1 = 0x00000000;
4077 break;
4078 case CHIP_TONGA:
4079 raster_config = 0x16000012;
4080 raster_config_1 = 0x0000002a;
4081 break;
4082 case CHIP_ICELAND:
4083 if (num_rb == 1)
4084 raster_config = 0x00000000;
4085 else
4086 raster_config = 0x00000002;
4087 raster_config_1 = 0x00000000;
4088 break;
4089 case CHIP_CARRIZO:
4090 raster_config = 0x00000002;
4091 raster_config_1 = 0x00000000;
4092 break;
4093 case CHIP_KAVERI:
4094 /* KV should be 0x00000002, but that causes problems with radeon */
4095 raster_config = 0x00000000; /* 0x00000002 */
4096 raster_config_1 = 0x00000000;
4097 break;
4098 case CHIP_KABINI:
4099 case CHIP_MULLINS:
4100 case CHIP_STONEY:
4101 raster_config = 0x00000000;
4102 raster_config_1 = 0x00000000;
4103 break;
4104 default:
4105 fprintf(stderr,
4106 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4107 raster_config = 0x00000000;
4108 raster_config_1 = 0x00000000;
4109 break;
4110 }
4111
4112 /* Always use the default config when all backends are enabled
4113 * (or when we failed to determine the enabled backends).
4114 */
4115 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4116 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4117 raster_config);
4118 if (sctx->b.chip_class >= CIK)
4119 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4120 raster_config_1);
4121 } else {
4122 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4123 }
4124
4125 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4126 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4127 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4128 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4129 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4130 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4131 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4132
4133 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4134 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4135 S_028230_ER_TRI(0xA) |
4136 S_028230_ER_POINT(0xA) |
4137 S_028230_ER_RECT(0xA) |
4138 /* Required by DX10_DIAMOND_TEST_ENA: */
4139 S_028230_ER_LINE_LR(0x1A) |
4140 S_028230_ER_LINE_RL(0x26) |
4141 S_028230_ER_LINE_TB(0xA) |
4142 S_028230_ER_LINE_BT(0xA));
4143 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4144 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4145 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4146 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4147 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4148 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4149 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4150
4151 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4152 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4153 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4154
4155 if (sctx->b.chip_class >= CIK) {
4156 /* If this is 0, Bonaire can hang even if GS isn't being used.
4157 * Other chips are unaffected. These are suboptimal values,
4158 * but we don't use on-chip GS.
4159 */
4160 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4161 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4162 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4163
4164 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4165 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4166 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4167 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4168
4169 if (sscreen->b.info.num_good_compute_units /
4170 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4171 /* Too few available compute units per SH. Disallowing
4172 * VS to run on CU0 could hurt us more than late VS
4173 * allocation would help.
4174 *
4175 * LATE_ALLOC_VS = 2 is the highest safe number.
4176 */
4177 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4178 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4179 } else {
4180 /* Set LATE_ALLOC_VS == 31. It should be less than
4181 * the number of scratch waves. Limitations:
4182 * - VS can't execute on CU0.
4183 * - If HS writes outputs to LDS, LS can't execute on CU0.
4184 */
4185 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4186 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4187 }
4188
4189 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4190 }
4191
4192 if (sctx->b.chip_class >= VI) {
4193 unsigned vgt_tess_distribution;
4194
4195 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4196 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4197 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4198 if (sctx->b.family < CHIP_POLARIS10)
4199 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4200 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4201
4202 vgt_tess_distribution =
4203 S_028B50_ACCUM_ISOLINE(32) |
4204 S_028B50_ACCUM_TRI(11) |
4205 S_028B50_ACCUM_QUAD(11) |
4206 S_028B50_DONUT_SPLIT(16);
4207
4208 /* Testing with Unigine Heaven extreme tesselation yielded best results
4209 * with TRAP_SPLIT = 3.
4210 */
4211 if (sctx->b.family == CHIP_FIJI ||
4212 sctx->b.family >= CHIP_POLARIS10)
4213 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4214
4215 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4216 } else {
4217 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4218 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4219 }
4220
4221 if (sctx->b.family == CHIP_STONEY)
4222 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4223
4224 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4225 if (sctx->b.chip_class >= CIK)
4226 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4227 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4228 RADEON_PRIO_BORDER_COLORS);
4229
4230 si_pm4_upload_indirect_buffer(sctx, pm4);
4231 sctx->init_config = pm4;
4232 }