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radeonsi: emit_msaa_sample_locs packets optimization
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_winsys_cs *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
91 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
92
93 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
94 * I think we don't have to do anything between IBs.
95 */
96 if (sctx->screen->dfsm_allowed &&
97 sctx->last_cb_target_mask != cb_target_mask) {
98 sctx->last_cb_target_mask = cb_target_mask;
99
100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
102 }
103
104 if (sctx->chip_class >= VI) {
105 /* DCC MSAA workaround for blending.
106 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
107 * COMBINER_DISABLE, but that would be more complicated.
108 */
109 bool oc_disable = (sctx->chip_class == VI ||
110 sctx->chip_class == GFX9) &&
111 blend &&
112 blend->blend_enable_4bit & cb_target_mask &&
113 sctx->framebuffer.nr_samples >= 2;
114
115 radeon_opt_set_context_reg(
116 sctx, R_028424_CB_DCC_CONTROL,
117 SI_TRACKED_CB_DCC_CONTROL,
118 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
119 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
120 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
121 }
122
123 /* RB+ register settings. */
124 if (sctx->screen->rbplus_allowed) {
125 unsigned spi_shader_col_format =
126 sctx->ps_shader.cso ?
127 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
128 unsigned sx_ps_downconvert = 0;
129 unsigned sx_blend_opt_epsilon = 0;
130 unsigned sx_blend_opt_control = 0;
131
132 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
133 struct r600_surface *surf =
134 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
135 unsigned format, swap, spi_format, colormask;
136 bool has_alpha, has_rgb;
137
138 if (!surf)
139 continue;
140
141 format = G_028C70_FORMAT(surf->cb_color_info);
142 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
143 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
144 colormask = (cb_target_mask >> (i * 4)) & 0xf;
145
146 /* Set if RGB and A are present. */
147 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
148
149 if (format == V_028C70_COLOR_8 ||
150 format == V_028C70_COLOR_16 ||
151 format == V_028C70_COLOR_32)
152 has_rgb = !has_alpha;
153 else
154 has_rgb = true;
155
156 /* Check the colormask and export format. */
157 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
158 has_rgb = false;
159 if (!(colormask & PIPE_MASK_A))
160 has_alpha = false;
161
162 if (spi_format == V_028714_SPI_SHADER_ZERO) {
163 has_rgb = false;
164 has_alpha = false;
165 }
166
167 /* Disable value checking for disabled channels. */
168 if (!has_rgb)
169 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
170 if (!has_alpha)
171 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
172
173 /* Enable down-conversion for 32bpp and smaller formats. */
174 switch (format) {
175 case V_028C70_COLOR_8:
176 case V_028C70_COLOR_8_8:
177 case V_028C70_COLOR_8_8_8_8:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
180 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
182 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
183 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
184 }
185 break;
186
187 case V_028C70_COLOR_5_6_5:
188 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
189 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
190 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
191 }
192 break;
193
194 case V_028C70_COLOR_1_5_5_5:
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
196 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
197 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
198 }
199 break;
200
201 case V_028C70_COLOR_4_4_4_4:
202 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
203 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
204 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
205 }
206 break;
207
208 case V_028C70_COLOR_32:
209 if (swap == V_028C70_SWAP_STD &&
210 spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV &&
213 spi_format == V_028714_SPI_SHADER_32_AR)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
215 break;
216
217 case V_028C70_COLOR_16:
218 case V_028C70_COLOR_16_16:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
224 if (swap == V_028C70_SWAP_STD ||
225 swap == V_028C70_SWAP_STD_REV)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
227 else
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
229 }
230 break;
231
232 case V_028C70_COLOR_10_11_11:
233 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
235 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
236 }
237 break;
238
239 case V_028C70_COLOR_2_10_10_10:
240 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
242 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
243 }
244 break;
245 }
246 }
247
248 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
249 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
250 SI_TRACKED_SX_PS_DOWNCONVERT,
251 sx_ps_downconvert, sx_blend_opt_epsilon,
252 sx_blend_opt_control);
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 PRINT_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 static void si_blend_check_commutativity(struct si_screen *sscreen,
374 struct si_state_blend *blend,
375 enum pipe_blend_func func,
376 enum pipe_blendfactor src,
377 enum pipe_blendfactor dst,
378 unsigned chanmask)
379 {
380 /* Src factor is allowed when it does not depend on Dst */
381 static const uint32_t src_allowed =
382 (1u << PIPE_BLENDFACTOR_ONE) |
383 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
384 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
386 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
387 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
389 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
397
398 if (dst == PIPE_BLENDFACTOR_ONE &&
399 (src_allowed & (1u << src))) {
400 /* Addition is commutative, but floating point addition isn't
401 * associative: subtle changes can be introduced via different
402 * rounding.
403 *
404 * Out-of-order is also non-deterministic, which means that
405 * this breaks OpenGL invariance requirements. So only enable
406 * out-of-order additive blending if explicitly allowed by a
407 * setting.
408 */
409 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
410 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
411 blend->commutative_4bit |= chanmask;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
425 *src_factor = PIPE_BLENDFACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == PIPE_BLEND_SUBTRACT)
430 *func = PIPE_BLEND_REVERSE_SUBTRACT;
431 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
432 *func = PIPE_BLEND_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
439 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
440 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
441 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
442 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
443 }
444
445 static void *si_create_blend_state_mode(struct pipe_context *ctx,
446 const struct pipe_blend_state *state,
447 unsigned mode)
448 {
449 struct si_context *sctx = (struct si_context*)ctx;
450 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
451 struct si_pm4_state *pm4 = &blend->pm4;
452 uint32_t sx_mrt_blend_opt[8] = {0};
453 uint32_t color_control = 0;
454
455 if (!blend)
456 return NULL;
457
458 blend->alpha_to_coverage = state->alpha_to_coverage;
459 blend->alpha_to_one = state->alpha_to_one;
460 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
461 blend->logicop_enable = state->logicop_enable;
462
463 if (state->logicop_enable) {
464 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
465 } else {
466 color_control |= S_028808_ROP3(0xcc);
467 }
468
469 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
472 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
475
476 if (state->alpha_to_coverage)
477 blend->need_src_alpha_4bit |= 0xf;
478
479 blend->cb_target_mask = 0;
480 blend->cb_target_enabled_4bit = 0;
481
482 for (int i = 0; i < 8; i++) {
483 /* state->rt entries > 0 only written if independent blending */
484 const int j = state->independent_blend_enable ? i : 0;
485
486 unsigned eqRGB = state->rt[j].rgb_func;
487 unsigned srcRGB = state->rt[j].rgb_src_factor;
488 unsigned dstRGB = state->rt[j].rgb_dst_factor;
489 unsigned eqA = state->rt[j].alpha_func;
490 unsigned srcA = state->rt[j].alpha_src_factor;
491 unsigned dstA = state->rt[j].alpha_dst_factor;
492
493 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
494 unsigned blend_cntl = 0;
495
496 sx_mrt_blend_opt[i] =
497 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
498 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
499
500 /* Only set dual source blending for MRT0 to avoid a hang. */
501 if (i >= 1 && blend->dual_src_blend) {
502 /* Vulkan does this for dual source blending. */
503 if (i == 1)
504 blend_cntl |= S_028780_ENABLE(1);
505
506 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
507 continue;
508 }
509
510 /* Only addition and subtraction equations are supported with
511 * dual source blending.
512 */
513 if (blend->dual_src_blend &&
514 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
515 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
518 continue;
519 }
520
521 /* cb_render_state will disable unused ones */
522 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
523 if (state->rt[j].colormask)
524 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
525
526 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 si_blend_check_commutativity(sctx->screen, blend,
532 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
533 si_blend_check_commutativity(sctx->screen, blend,
534 eqA, srcA, dstA, 0x8 << (4 * i));
535
536 /* Blending optimizations for RB+.
537 * These transformations don't change the behavior.
538 *
539 * First, get rid of DST in the blend factors:
540 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
541 */
542 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
543 PIPE_BLENDFACTOR_DST_COLOR,
544 PIPE_BLENDFACTOR_SRC_COLOR);
545 si_blend_remove_dst(&eqA, &srcA, &dstA,
546 PIPE_BLENDFACTOR_DST_COLOR,
547 PIPE_BLENDFACTOR_SRC_COLOR);
548 si_blend_remove_dst(&eqA, &srcA, &dstA,
549 PIPE_BLENDFACTOR_DST_ALPHA,
550 PIPE_BLENDFACTOR_SRC_ALPHA);
551
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
554 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
555 srcA_opt = si_translate_blend_opt_factor(srcA, true);
556 dstA_opt = si_translate_blend_opt_factor(dstA, true);
557
558 /* Handle interdependencies. */
559 if (si_blend_factor_uses_dst(srcRGB))
560 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
561 if (si_blend_factor_uses_dst(srcA))
562 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
563
564 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
565 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
566 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
567 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
568 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
569
570 /* Set the final value. */
571 sx_mrt_blend_opt[i] =
572 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
573 S_028760_COLOR_DST_OPT(dstRGB_opt) |
574 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
575 S_028760_ALPHA_SRC_OPT(srcA_opt) |
576 S_028760_ALPHA_DST_OPT(dstA_opt) |
577 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
578
579 /* Set blend state. */
580 blend_cntl |= S_028780_ENABLE(1);
581 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
582 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
583 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
584
585 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
586 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
587 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
588 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
589 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
590 }
591 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
592
593 blend->blend_enable_4bit |= 0xfu << (i * 4);
594
595 /* This is only important for formats without alpha. */
596 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
598 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
599 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
600 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
601 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
602 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
603 }
604
605 if (blend->cb_target_mask) {
606 color_control |= S_028808_MODE(mode);
607 } else {
608 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
609 }
610
611 if (sctx->screen->rbplus_allowed) {
612 /* Disable RB+ blend optimizations for dual source blending.
613 * Vulkan does this.
614 */
615 if (blend->dual_src_blend) {
616 for (int i = 0; i < 8; i++) {
617 sx_mrt_blend_opt[i] =
618 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
620 }
621 }
622
623 for (int i = 0; i < 8; i++)
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
625 sx_mrt_blend_opt[i]);
626
627 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
628 if (blend->dual_src_blend || state->logicop_enable ||
629 mode == V_028808_CB_RESOLVE)
630 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
631 }
632
633 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
634 return blend;
635 }
636
637 static void *si_create_blend_state(struct pipe_context *ctx,
638 const struct pipe_blend_state *state)
639 {
640 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
641 }
642
643 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 struct si_state_blend *old_blend = sctx->queued.named.blend;
647 struct si_state_blend *blend = (struct si_state_blend *)state;
648
649 if (!state)
650 return;
651
652 si_pm4_bind_state(sctx, blend, state);
653
654 if (!old_blend ||
655 old_blend->cb_target_mask != blend->cb_target_mask ||
656 old_blend->dual_src_blend != blend->dual_src_blend ||
657 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
658 sctx->framebuffer.nr_samples >= 2 &&
659 sctx->screen->dcc_msaa_allowed))
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
661
662 if (!old_blend ||
663 old_blend->cb_target_mask != blend->cb_target_mask ||
664 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
665 old_blend->alpha_to_one != blend->alpha_to_one ||
666 old_blend->dual_src_blend != blend->dual_src_blend ||
667 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
668 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
669 sctx->do_update_shaders = true;
670
671 if (sctx->screen->dpbb_allowed &&
672 (!old_blend ||
673 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
676 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
677
678 if (sctx->screen->has_out_of_order_rast &&
679 (!old_blend ||
680 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
681 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
682 old_blend->commutative_4bit != blend->commutative_4bit ||
683 old_blend->logicop_enable != blend->logicop_enable)))
684 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
685 }
686
687 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
691 }
692
693 static void si_set_blend_color(struct pipe_context *ctx,
694 const struct pipe_blend_color *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 static const struct pipe_blend_color zeros;
698
699 sctx->blend_color.state = *state;
700 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
701 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
702 }
703
704 static void si_emit_blend_color(struct si_context *sctx)
705 {
706 struct radeon_winsys_cs *cs = sctx->gfx_cs;
707
708 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
709 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
710 }
711
712 /*
713 * Clipping
714 */
715
716 static void si_set_clip_state(struct pipe_context *ctx,
717 const struct pipe_clip_state *state)
718 {
719 struct si_context *sctx = (struct si_context *)ctx;
720 struct pipe_constant_buffer cb;
721 static const struct pipe_clip_state zeros;
722
723 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
724 return;
725
726 sctx->clip_state.state = *state;
727 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
728 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
729
730 cb.buffer = NULL;
731 cb.user_buffer = state->ucp;
732 cb.buffer_offset = 0;
733 cb.buffer_size = 4*4*8;
734 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
735 pipe_resource_reference(&cb.buffer, NULL);
736 }
737
738 static void si_emit_clip_state(struct si_context *sctx)
739 {
740 struct radeon_winsys_cs *cs = sctx->gfx_cs;
741
742 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
743 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
744 }
745
746 static void si_emit_clip_regs(struct si_context *sctx)
747 {
748 struct radeon_winsys_cs *cs = sctx->gfx_cs;
749 struct si_shader *vs = si_get_vs_state(sctx);
750 struct si_shader_selector *vs_sel = vs->selector;
751 struct tgsi_shader_info *info = &vs_sel->info;
752 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
753 unsigned window_space =
754 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
755 unsigned clipdist_mask = vs_sel->clipdist_mask;
756 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
757 unsigned culldist_mask = vs_sel->culldist_mask;
758 unsigned total_mask;
759
760 if (vs->key.opt.clip_disable) {
761 assert(!info->culldist_writemask);
762 clipdist_mask = 0;
763 culldist_mask = 0;
764 }
765 total_mask = clipdist_mask | culldist_mask;
766
767 /* Clip distances on points have no effect, so need to be implemented
768 * as cull distances. This applies for the clipvertex case as well.
769 *
770 * Setting this for primitives other than points should have no adverse
771 * effects.
772 */
773 clipdist_mask &= rs->clip_plane_enable;
774 culldist_mask |= clipdist_mask;
775
776 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
777 vs_sel->pa_cl_vs_out_cntl |
778 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
779 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
780 clipdist_mask | (culldist_mask << 8));
781 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
782 rs->pa_cl_clip_cntl |
783 ucp_mask |
784 S_028810_CLIP_DISABLE(window_space));
785 }
786
787 /*
788 * inferred state between framebuffer and rasterizer
789 */
790 static void si_update_poly_offset_state(struct si_context *sctx)
791 {
792 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
793
794 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
795 si_pm4_bind_state(sctx, poly_offset, NULL);
796 return;
797 }
798
799 /* Use the user format, not db_render_format, so that the polygon
800 * offset behaves as expected by applications.
801 */
802 switch (sctx->framebuffer.state.zsbuf->texture->format) {
803 case PIPE_FORMAT_Z16_UNORM:
804 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
805 break;
806 default: /* 24-bit */
807 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
808 break;
809 case PIPE_FORMAT_Z32_FLOAT:
810 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
811 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
812 break;
813 }
814 }
815
816 /*
817 * Rasterizer
818 */
819
820 static uint32_t si_translate_fill(uint32_t func)
821 {
822 switch(func) {
823 case PIPE_POLYGON_MODE_FILL:
824 return V_028814_X_DRAW_TRIANGLES;
825 case PIPE_POLYGON_MODE_LINE:
826 return V_028814_X_DRAW_LINES;
827 case PIPE_POLYGON_MODE_POINT:
828 return V_028814_X_DRAW_POINTS;
829 default:
830 assert(0);
831 return V_028814_X_DRAW_POINTS;
832 }
833 }
834
835 static void *si_create_rs_state(struct pipe_context *ctx,
836 const struct pipe_rasterizer_state *state)
837 {
838 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
839 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
840 struct si_pm4_state *pm4 = &rs->pm4;
841 unsigned tmp, i;
842 float psize_min, psize_max;
843
844 if (!rs) {
845 return NULL;
846 }
847
848 rs->scissor_enable = state->scissor;
849 rs->clip_halfz = state->clip_halfz;
850 rs->two_side = state->light_twoside;
851 rs->multisample_enable = state->multisample;
852 rs->force_persample_interp = state->force_persample_interp;
853 rs->clip_plane_enable = state->clip_plane_enable;
854 rs->line_stipple_enable = state->line_stipple_enable;
855 rs->poly_stipple_enable = state->poly_stipple_enable;
856 rs->line_smooth = state->line_smooth;
857 rs->line_width = state->line_width;
858 rs->poly_smooth = state->poly_smooth;
859 rs->uses_poly_offset = state->offset_point || state->offset_line ||
860 state->offset_tri;
861 rs->clamp_fragment_color = state->clamp_fragment_color;
862 rs->clamp_vertex_color = state->clamp_vertex_color;
863 rs->flatshade = state->flatshade;
864 rs->sprite_coord_enable = state->sprite_coord_enable;
865 rs->rasterizer_discard = state->rasterizer_discard;
866 rs->pa_sc_line_stipple = state->line_stipple_enable ?
867 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
868 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
869 rs->pa_cl_clip_cntl =
870 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
871 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
872 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
873 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
874 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
875
876 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
877 S_0286D4_FLAT_SHADE_ENA(1) |
878 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
879 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
880 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
881 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
882 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
883 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
884
885 /* point size 12.4 fixed point */
886 tmp = (unsigned)(state->point_size * 8.0);
887 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
888
889 if (state->point_size_per_vertex) {
890 psize_min = util_get_min_point_size(state);
891 psize_max = 8192;
892 } else {
893 /* Force the point size to be as if the vertex output was disabled. */
894 psize_min = state->point_size;
895 psize_max = state->point_size;
896 }
897 rs->max_point_size = psize_max;
898
899 /* Divide by two, because 0.5 = 1 pixel. */
900 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
901 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
902 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
903
904 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
905 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
906 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
907 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
908 S_028A48_MSAA_ENABLE(state->multisample ||
909 state->poly_smooth ||
910 state->line_smooth) |
911 S_028A48_VPORT_SCISSOR_ENABLE(1) |
912 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
913
914 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
915 S_028BE4_PIX_CENTER(state->half_pixel_center) |
916 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
917
918 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
919 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
920 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
921 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
922 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
923 S_028814_FACE(!state->front_ccw) |
924 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
925 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
926 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
927 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
928 state->fill_back != PIPE_POLYGON_MODE_FILL) |
929 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
930 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
931
932 if (!rs->uses_poly_offset)
933 return rs;
934
935 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
936 if (!rs->pm4_poly_offset) {
937 FREE(rs);
938 return NULL;
939 }
940
941 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
942 for (i = 0; i < 3; i++) {
943 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
944 float offset_units = state->offset_units;
945 float offset_scale = state->offset_scale * 16.0f;
946 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
947
948 if (!state->offset_units_unscaled) {
949 switch (i) {
950 case 0: /* 16-bit zbuffer */
951 offset_units *= 4.0f;
952 pa_su_poly_offset_db_fmt_cntl =
953 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
954 break;
955 case 1: /* 24-bit zbuffer */
956 offset_units *= 2.0f;
957 pa_su_poly_offset_db_fmt_cntl =
958 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
959 break;
960 case 2: /* 32-bit zbuffer */
961 offset_units *= 1.0f;
962 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
963 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
964 break;
965 }
966 }
967
968 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
969 fui(offset_scale));
970 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
971 fui(offset_units));
972 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
973 fui(offset_scale));
974 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
975 fui(offset_units));
976 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
977 pa_su_poly_offset_db_fmt_cntl);
978 }
979
980 return rs;
981 }
982
983 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
984 {
985 struct si_context *sctx = (struct si_context *)ctx;
986 struct si_state_rasterizer *old_rs =
987 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
988 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
989
990 if (!state)
991 return;
992
993 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
994 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
995
996 /* Update the small primitive filter workaround if necessary. */
997 if (sctx->screen->has_msaa_sample_loc_bug &&
998 sctx->framebuffer.nr_samples > 1)
999 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1000 }
1001
1002 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1003 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1004
1005 si_pm4_bind_state(sctx, rasterizer, rs);
1006 si_update_poly_offset_state(sctx);
1007
1008 if (!old_rs ||
1009 (old_rs->scissor_enable != rs->scissor_enable ||
1010 old_rs->line_width != rs->line_width ||
1011 old_rs->max_point_size != rs->max_point_size)) {
1012 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1013 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1014 }
1015
1016 if (!old_rs ||
1017 old_rs->clip_halfz != rs->clip_halfz) {
1018 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1019 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1020 }
1021
1022 if (!old_rs ||
1023 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1024 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1025 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1026
1027 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1028 rs->line_stipple_enable;
1029
1030 if (!old_rs ||
1031 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1032 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1033 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1034 old_rs->flatshade != rs->flatshade ||
1035 old_rs->two_side != rs->two_side ||
1036 old_rs->multisample_enable != rs->multisample_enable ||
1037 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1038 old_rs->poly_smooth != rs->poly_smooth ||
1039 old_rs->line_smooth != rs->line_smooth ||
1040 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1041 old_rs->force_persample_interp != rs->force_persample_interp)
1042 sctx->do_update_shaders = true;
1043 }
1044
1045 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1046 {
1047 struct si_context *sctx = (struct si_context *)ctx;
1048 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1049
1050 if (sctx->queued.named.rasterizer == state)
1051 si_pm4_bind_state(sctx, poly_offset, NULL);
1052
1053 FREE(rs->pm4_poly_offset);
1054 si_pm4_delete_state(sctx, rasterizer, rs);
1055 }
1056
1057 /*
1058 * infeered state between dsa and stencil ref
1059 */
1060 static void si_emit_stencil_ref(struct si_context *sctx)
1061 {
1062 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1063 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1064 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1065
1066 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1067 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1068 S_028430_STENCILMASK(dsa->valuemask[0]) |
1069 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1070 S_028430_STENCILOPVAL(1));
1071 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1072 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1073 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1074 S_028434_STENCILOPVAL_BF(1));
1075 }
1076
1077 static void si_set_stencil_ref(struct pipe_context *ctx,
1078 const struct pipe_stencil_ref *state)
1079 {
1080 struct si_context *sctx = (struct si_context *)ctx;
1081
1082 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1083 return;
1084
1085 sctx->stencil_ref.state = *state;
1086 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1087 }
1088
1089
1090 /*
1091 * DSA
1092 */
1093
1094 static uint32_t si_translate_stencil_op(int s_op)
1095 {
1096 switch (s_op) {
1097 case PIPE_STENCIL_OP_KEEP:
1098 return V_02842C_STENCIL_KEEP;
1099 case PIPE_STENCIL_OP_ZERO:
1100 return V_02842C_STENCIL_ZERO;
1101 case PIPE_STENCIL_OP_REPLACE:
1102 return V_02842C_STENCIL_REPLACE_TEST;
1103 case PIPE_STENCIL_OP_INCR:
1104 return V_02842C_STENCIL_ADD_CLAMP;
1105 case PIPE_STENCIL_OP_DECR:
1106 return V_02842C_STENCIL_SUB_CLAMP;
1107 case PIPE_STENCIL_OP_INCR_WRAP:
1108 return V_02842C_STENCIL_ADD_WRAP;
1109 case PIPE_STENCIL_OP_DECR_WRAP:
1110 return V_02842C_STENCIL_SUB_WRAP;
1111 case PIPE_STENCIL_OP_INVERT:
1112 return V_02842C_STENCIL_INVERT;
1113 default:
1114 PRINT_ERR("Unknown stencil op %d", s_op);
1115 assert(0);
1116 break;
1117 }
1118 return 0;
1119 }
1120
1121 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1122 {
1123 return s->enabled && s->writemask &&
1124 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1125 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1126 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1127 }
1128
1129 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1130 {
1131 /* REPLACE is normally order invariant, except when the stencil
1132 * reference value is written by the fragment shader. Tracking this
1133 * interaction does not seem worth the effort, so be conservative. */
1134 return op != PIPE_STENCIL_OP_INCR &&
1135 op != PIPE_STENCIL_OP_DECR &&
1136 op != PIPE_STENCIL_OP_REPLACE;
1137 }
1138
1139 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1140 * invariant in the sense that the set of passing fragments as well as the
1141 * final stencil buffer result does not depend on the order of fragments. */
1142 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1143 {
1144 return !state->enabled || !state->writemask ||
1145 /* The following assumes that Z writes are disabled. */
1146 (state->func == PIPE_FUNC_ALWAYS &&
1147 si_order_invariant_stencil_op(state->zpass_op) &&
1148 si_order_invariant_stencil_op(state->zfail_op)) ||
1149 (state->func == PIPE_FUNC_NEVER &&
1150 si_order_invariant_stencil_op(state->fail_op));
1151 }
1152
1153 static void *si_create_dsa_state(struct pipe_context *ctx,
1154 const struct pipe_depth_stencil_alpha_state *state)
1155 {
1156 struct si_context *sctx = (struct si_context *)ctx;
1157 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1158 struct si_pm4_state *pm4 = &dsa->pm4;
1159 unsigned db_depth_control;
1160 uint32_t db_stencil_control = 0;
1161
1162 if (!dsa) {
1163 return NULL;
1164 }
1165
1166 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1167 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1168 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1169 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1170
1171 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1172 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1173 S_028800_ZFUNC(state->depth.func) |
1174 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1175
1176 /* stencil */
1177 if (state->stencil[0].enabled) {
1178 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1179 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1180 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1181 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1182 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1183
1184 if (state->stencil[1].enabled) {
1185 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1186 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1187 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1188 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1189 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1190 }
1191 }
1192
1193 /* alpha */
1194 if (state->alpha.enabled) {
1195 dsa->alpha_func = state->alpha.func;
1196
1197 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1198 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1199 } else {
1200 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1201 }
1202
1203 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1204 if (state->stencil[0].enabled)
1205 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1206 if (state->depth.bounds_test) {
1207 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1208 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1209 }
1210
1211 dsa->depth_enabled = state->depth.enabled;
1212 dsa->depth_write_enabled = state->depth.enabled &&
1213 state->depth.writemask;
1214 dsa->stencil_enabled = state->stencil[0].enabled;
1215 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1216 (si_dsa_writes_stencil(&state->stencil[0]) ||
1217 si_dsa_writes_stencil(&state->stencil[1]));
1218 dsa->db_can_write = dsa->depth_write_enabled ||
1219 dsa->stencil_write_enabled;
1220
1221 bool zfunc_is_ordered =
1222 state->depth.func == PIPE_FUNC_NEVER ||
1223 state->depth.func == PIPE_FUNC_LESS ||
1224 state->depth.func == PIPE_FUNC_LEQUAL ||
1225 state->depth.func == PIPE_FUNC_GREATER ||
1226 state->depth.func == PIPE_FUNC_GEQUAL;
1227
1228 bool nozwrite_and_order_invariant_stencil =
1229 !dsa->db_can_write ||
1230 (!dsa->depth_write_enabled &&
1231 si_order_invariant_stencil_state(&state->stencil[0]) &&
1232 si_order_invariant_stencil_state(&state->stencil[1]));
1233
1234 dsa->order_invariance[1].zs =
1235 nozwrite_and_order_invariant_stencil ||
1236 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1237 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1238
1239 dsa->order_invariance[1].pass_set =
1240 nozwrite_and_order_invariant_stencil ||
1241 (!dsa->stencil_write_enabled &&
1242 (state->depth.func == PIPE_FUNC_ALWAYS ||
1243 state->depth.func == PIPE_FUNC_NEVER));
1244 dsa->order_invariance[0].pass_set =
1245 !dsa->depth_write_enabled ||
1246 (state->depth.func == PIPE_FUNC_ALWAYS ||
1247 state->depth.func == PIPE_FUNC_NEVER);
1248
1249 dsa->order_invariance[1].pass_last =
1250 sctx->screen->assume_no_z_fights &&
1251 !dsa->stencil_write_enabled &&
1252 dsa->depth_write_enabled && zfunc_is_ordered;
1253 dsa->order_invariance[0].pass_last =
1254 sctx->screen->assume_no_z_fights &&
1255 dsa->depth_write_enabled && zfunc_is_ordered;
1256
1257 return dsa;
1258 }
1259
1260 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1261 {
1262 struct si_context *sctx = (struct si_context *)ctx;
1263 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1264 struct si_state_dsa *dsa = state;
1265
1266 if (!state)
1267 return;
1268
1269 si_pm4_bind_state(sctx, dsa, dsa);
1270
1271 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1272 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1273 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1274 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1275 }
1276
1277 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1278 sctx->do_update_shaders = true;
1279
1280 if (sctx->screen->dpbb_allowed &&
1281 (!old_dsa ||
1282 (old_dsa->depth_enabled != dsa->depth_enabled ||
1283 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1284 old_dsa->db_can_write != dsa->db_can_write)))
1285 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1286
1287 if (sctx->screen->has_out_of_order_rast &&
1288 (!old_dsa ||
1289 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1290 sizeof(old_dsa->order_invariance))))
1291 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1292 }
1293
1294 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1295 {
1296 struct si_context *sctx = (struct si_context *)ctx;
1297 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1298 }
1299
1300 static void *si_create_db_flush_dsa(struct si_context *sctx)
1301 {
1302 struct pipe_depth_stencil_alpha_state dsa = {};
1303
1304 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1305 }
1306
1307 /* DB RENDER STATE */
1308
1309 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1310 {
1311 struct si_context *sctx = (struct si_context*)ctx;
1312
1313 /* Pipeline stat & streamout queries. */
1314 if (enable) {
1315 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1316 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1317 } else {
1318 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1319 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1320 }
1321
1322 /* Occlusion queries. */
1323 if (sctx->occlusion_queries_disabled != !enable) {
1324 sctx->occlusion_queries_disabled = !enable;
1325 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1326 }
1327 }
1328
1329 void si_set_occlusion_query_state(struct si_context *sctx,
1330 bool old_perfect_enable)
1331 {
1332 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1333
1334 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1335
1336 if (perfect_enable != old_perfect_enable)
1337 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1338 }
1339
1340 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1341 {
1342 st->saved_compute = sctx->cs_shader_state.program;
1343
1344 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1345 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1346 }
1347
1348 static void si_emit_db_render_state(struct si_context *sctx)
1349 {
1350 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1351 unsigned db_shader_control, db_render_control, db_count_control;
1352
1353 /* DB_RENDER_CONTROL */
1354 if (sctx->dbcb_depth_copy_enabled ||
1355 sctx->dbcb_stencil_copy_enabled) {
1356 db_render_control =
1357 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1358 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1359 S_028000_COPY_CENTROID(1) |
1360 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1361 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1362 db_render_control =
1363 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1364 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1365 } else {
1366 db_render_control =
1367 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1368 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1369 }
1370
1371 /* DB_COUNT_CONTROL (occlusion queries) */
1372 if (sctx->num_occlusion_queries > 0 &&
1373 !sctx->occlusion_queries_disabled) {
1374 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1375
1376 if (sctx->chip_class >= CIK) {
1377 db_count_control =
1378 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1379 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1380 S_028004_ZPASS_ENABLE(1) |
1381 S_028004_SLICE_EVEN_ENABLE(1) |
1382 S_028004_SLICE_ODD_ENABLE(1);
1383 } else {
1384 db_count_control =
1385 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1386 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1387 }
1388 } else {
1389 /* Disable occlusion queries. */
1390 if (sctx->chip_class >= CIK) {
1391 db_count_control = 0;
1392 } else {
1393 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1394 }
1395 }
1396
1397 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1398 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1399 db_count_control);
1400
1401 /* DB_RENDER_OVERRIDE2 */
1402 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1403 SI_TRACKED_DB_RENDER_OVERRIDE2,
1404 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1405 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1406 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1407
1408 db_shader_control = sctx->ps_db_shader_control;
1409
1410 /* Bug workaround for smoothing (overrasterization) on SI. */
1411 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1412 db_shader_control &= C_02880C_Z_ORDER;
1413 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1414 }
1415
1416 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1417 if (!rs || !rs->multisample_enable)
1418 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1419
1420 if (sctx->screen->has_rbplus &&
1421 !sctx->screen->rbplus_allowed)
1422 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1423
1424 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1425 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1426 }
1427
1428 /*
1429 * format translation
1430 */
1431 static uint32_t si_translate_colorformat(enum pipe_format format)
1432 {
1433 const struct util_format_description *desc = util_format_description(format);
1434 if (!desc)
1435 return V_028C70_COLOR_INVALID;
1436
1437 #define HAS_SIZE(x,y,z,w) \
1438 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1439 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1440
1441 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1442 return V_028C70_COLOR_10_11_11;
1443
1444 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1445 return V_028C70_COLOR_INVALID;
1446
1447 /* hw cannot support mixed formats (except depth/stencil, since
1448 * stencil is not written to). */
1449 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1450 return V_028C70_COLOR_INVALID;
1451
1452 switch (desc->nr_channels) {
1453 case 1:
1454 switch (desc->channel[0].size) {
1455 case 8:
1456 return V_028C70_COLOR_8;
1457 case 16:
1458 return V_028C70_COLOR_16;
1459 case 32:
1460 return V_028C70_COLOR_32;
1461 }
1462 break;
1463 case 2:
1464 if (desc->channel[0].size == desc->channel[1].size) {
1465 switch (desc->channel[0].size) {
1466 case 8:
1467 return V_028C70_COLOR_8_8;
1468 case 16:
1469 return V_028C70_COLOR_16_16;
1470 case 32:
1471 return V_028C70_COLOR_32_32;
1472 }
1473 } else if (HAS_SIZE(8,24,0,0)) {
1474 return V_028C70_COLOR_24_8;
1475 } else if (HAS_SIZE(24,8,0,0)) {
1476 return V_028C70_COLOR_8_24;
1477 }
1478 break;
1479 case 3:
1480 if (HAS_SIZE(5,6,5,0)) {
1481 return V_028C70_COLOR_5_6_5;
1482 } else if (HAS_SIZE(32,8,24,0)) {
1483 return V_028C70_COLOR_X24_8_32_FLOAT;
1484 }
1485 break;
1486 case 4:
1487 if (desc->channel[0].size == desc->channel[1].size &&
1488 desc->channel[0].size == desc->channel[2].size &&
1489 desc->channel[0].size == desc->channel[3].size) {
1490 switch (desc->channel[0].size) {
1491 case 4:
1492 return V_028C70_COLOR_4_4_4_4;
1493 case 8:
1494 return V_028C70_COLOR_8_8_8_8;
1495 case 16:
1496 return V_028C70_COLOR_16_16_16_16;
1497 case 32:
1498 return V_028C70_COLOR_32_32_32_32;
1499 }
1500 } else if (HAS_SIZE(5,5,5,1)) {
1501 return V_028C70_COLOR_1_5_5_5;
1502 } else if (HAS_SIZE(1,5,5,5)) {
1503 return V_028C70_COLOR_5_5_5_1;
1504 } else if (HAS_SIZE(10,10,10,2)) {
1505 return V_028C70_COLOR_2_10_10_10;
1506 }
1507 break;
1508 }
1509 return V_028C70_COLOR_INVALID;
1510 }
1511
1512 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1513 {
1514 if (SI_BIG_ENDIAN) {
1515 switch(colorformat) {
1516 /* 8-bit buffers. */
1517 case V_028C70_COLOR_8:
1518 return V_028C70_ENDIAN_NONE;
1519
1520 /* 16-bit buffers. */
1521 case V_028C70_COLOR_5_6_5:
1522 case V_028C70_COLOR_1_5_5_5:
1523 case V_028C70_COLOR_4_4_4_4:
1524 case V_028C70_COLOR_16:
1525 case V_028C70_COLOR_8_8:
1526 return V_028C70_ENDIAN_8IN16;
1527
1528 /* 32-bit buffers. */
1529 case V_028C70_COLOR_8_8_8_8:
1530 case V_028C70_COLOR_2_10_10_10:
1531 case V_028C70_COLOR_8_24:
1532 case V_028C70_COLOR_24_8:
1533 case V_028C70_COLOR_16_16:
1534 return V_028C70_ENDIAN_8IN32;
1535
1536 /* 64-bit buffers. */
1537 case V_028C70_COLOR_16_16_16_16:
1538 return V_028C70_ENDIAN_8IN16;
1539
1540 case V_028C70_COLOR_32_32:
1541 return V_028C70_ENDIAN_8IN32;
1542
1543 /* 128-bit buffers. */
1544 case V_028C70_COLOR_32_32_32_32:
1545 return V_028C70_ENDIAN_8IN32;
1546 default:
1547 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1548 }
1549 } else {
1550 return V_028C70_ENDIAN_NONE;
1551 }
1552 }
1553
1554 static uint32_t si_translate_dbformat(enum pipe_format format)
1555 {
1556 switch (format) {
1557 case PIPE_FORMAT_Z16_UNORM:
1558 return V_028040_Z_16;
1559 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1560 case PIPE_FORMAT_X8Z24_UNORM:
1561 case PIPE_FORMAT_Z24X8_UNORM:
1562 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1563 return V_028040_Z_24; /* deprecated on SI */
1564 case PIPE_FORMAT_Z32_FLOAT:
1565 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1566 return V_028040_Z_32_FLOAT;
1567 default:
1568 return V_028040_Z_INVALID;
1569 }
1570 }
1571
1572 /*
1573 * Texture translation
1574 */
1575
1576 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1577 enum pipe_format format,
1578 const struct util_format_description *desc,
1579 int first_non_void)
1580 {
1581 struct si_screen *sscreen = (struct si_screen*)screen;
1582 bool uniform = true;
1583 int i;
1584
1585 /* Colorspace (return non-RGB formats directly). */
1586 switch (desc->colorspace) {
1587 /* Depth stencil formats */
1588 case UTIL_FORMAT_COLORSPACE_ZS:
1589 switch (format) {
1590 case PIPE_FORMAT_Z16_UNORM:
1591 return V_008F14_IMG_DATA_FORMAT_16;
1592 case PIPE_FORMAT_X24S8_UINT:
1593 case PIPE_FORMAT_S8X24_UINT:
1594 /*
1595 * Implemented as an 8_8_8_8 data format to fix texture
1596 * gathers in stencil sampling. This affects at least
1597 * GL45-CTS.texture_cube_map_array.sampling on VI.
1598 */
1599 if (sscreen->info.chip_class <= VI)
1600 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1601
1602 if (format == PIPE_FORMAT_X24S8_UINT)
1603 return V_008F14_IMG_DATA_FORMAT_8_24;
1604 else
1605 return V_008F14_IMG_DATA_FORMAT_24_8;
1606 case PIPE_FORMAT_Z24X8_UNORM:
1607 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1608 return V_008F14_IMG_DATA_FORMAT_8_24;
1609 case PIPE_FORMAT_X8Z24_UNORM:
1610 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1611 return V_008F14_IMG_DATA_FORMAT_24_8;
1612 case PIPE_FORMAT_S8_UINT:
1613 return V_008F14_IMG_DATA_FORMAT_8;
1614 case PIPE_FORMAT_Z32_FLOAT:
1615 return V_008F14_IMG_DATA_FORMAT_32;
1616 case PIPE_FORMAT_X32_S8X24_UINT:
1617 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1618 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1619 default:
1620 goto out_unknown;
1621 }
1622
1623 case UTIL_FORMAT_COLORSPACE_YUV:
1624 goto out_unknown; /* TODO */
1625
1626 case UTIL_FORMAT_COLORSPACE_SRGB:
1627 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1628 goto out_unknown;
1629 break;
1630
1631 default:
1632 break;
1633 }
1634
1635 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1636 if (!sscreen->info.has_format_bc1_through_bc7)
1637 goto out_unknown;
1638
1639 switch (format) {
1640 case PIPE_FORMAT_RGTC1_SNORM:
1641 case PIPE_FORMAT_LATC1_SNORM:
1642 case PIPE_FORMAT_RGTC1_UNORM:
1643 case PIPE_FORMAT_LATC1_UNORM:
1644 return V_008F14_IMG_DATA_FORMAT_BC4;
1645 case PIPE_FORMAT_RGTC2_SNORM:
1646 case PIPE_FORMAT_LATC2_SNORM:
1647 case PIPE_FORMAT_RGTC2_UNORM:
1648 case PIPE_FORMAT_LATC2_UNORM:
1649 return V_008F14_IMG_DATA_FORMAT_BC5;
1650 default:
1651 goto out_unknown;
1652 }
1653 }
1654
1655 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1656 (sscreen->info.family == CHIP_STONEY ||
1657 sscreen->info.family == CHIP_VEGA10 ||
1658 sscreen->info.family == CHIP_RAVEN)) {
1659 switch (format) {
1660 case PIPE_FORMAT_ETC1_RGB8:
1661 case PIPE_FORMAT_ETC2_RGB8:
1662 case PIPE_FORMAT_ETC2_SRGB8:
1663 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1664 case PIPE_FORMAT_ETC2_RGB8A1:
1665 case PIPE_FORMAT_ETC2_SRGB8A1:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1667 case PIPE_FORMAT_ETC2_RGBA8:
1668 case PIPE_FORMAT_ETC2_SRGBA8:
1669 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1670 case PIPE_FORMAT_ETC2_R11_UNORM:
1671 case PIPE_FORMAT_ETC2_R11_SNORM:
1672 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1673 case PIPE_FORMAT_ETC2_RG11_UNORM:
1674 case PIPE_FORMAT_ETC2_RG11_SNORM:
1675 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1676 default:
1677 goto out_unknown;
1678 }
1679 }
1680
1681 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1682 if (!sscreen->info.has_format_bc1_through_bc7)
1683 goto out_unknown;
1684
1685 switch (format) {
1686 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1687 case PIPE_FORMAT_BPTC_SRGBA:
1688 return V_008F14_IMG_DATA_FORMAT_BC7;
1689 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1690 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1691 return V_008F14_IMG_DATA_FORMAT_BC6;
1692 default:
1693 goto out_unknown;
1694 }
1695 }
1696
1697 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1698 switch (format) {
1699 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1700 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1701 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1702 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1703 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1704 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1705 default:
1706 goto out_unknown;
1707 }
1708 }
1709
1710 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1711 if (!sscreen->info.has_format_bc1_through_bc7)
1712 goto out_unknown;
1713
1714 switch (format) {
1715 case PIPE_FORMAT_DXT1_RGB:
1716 case PIPE_FORMAT_DXT1_RGBA:
1717 case PIPE_FORMAT_DXT1_SRGB:
1718 case PIPE_FORMAT_DXT1_SRGBA:
1719 return V_008F14_IMG_DATA_FORMAT_BC1;
1720 case PIPE_FORMAT_DXT3_RGBA:
1721 case PIPE_FORMAT_DXT3_SRGBA:
1722 return V_008F14_IMG_DATA_FORMAT_BC2;
1723 case PIPE_FORMAT_DXT5_RGBA:
1724 case PIPE_FORMAT_DXT5_SRGBA:
1725 return V_008F14_IMG_DATA_FORMAT_BC3;
1726 default:
1727 goto out_unknown;
1728 }
1729 }
1730
1731 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1732 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1733 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1734 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1735 }
1736
1737 /* R8G8Bx_SNORM - TODO CxV8U8 */
1738
1739 /* hw cannot support mixed formats (except depth/stencil, since only
1740 * depth is read).*/
1741 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1742 goto out_unknown;
1743
1744 /* See whether the components are of the same size. */
1745 for (i = 1; i < desc->nr_channels; i++) {
1746 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1747 }
1748
1749 /* Non-uniform formats. */
1750 if (!uniform) {
1751 switch(desc->nr_channels) {
1752 case 3:
1753 if (desc->channel[0].size == 5 &&
1754 desc->channel[1].size == 6 &&
1755 desc->channel[2].size == 5) {
1756 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1757 }
1758 goto out_unknown;
1759 case 4:
1760 if (desc->channel[0].size == 5 &&
1761 desc->channel[1].size == 5 &&
1762 desc->channel[2].size == 5 &&
1763 desc->channel[3].size == 1) {
1764 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1765 }
1766 if (desc->channel[0].size == 1 &&
1767 desc->channel[1].size == 5 &&
1768 desc->channel[2].size == 5 &&
1769 desc->channel[3].size == 5) {
1770 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1771 }
1772 if (desc->channel[0].size == 10 &&
1773 desc->channel[1].size == 10 &&
1774 desc->channel[2].size == 10 &&
1775 desc->channel[3].size == 2) {
1776 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1777 }
1778 goto out_unknown;
1779 }
1780 goto out_unknown;
1781 }
1782
1783 if (first_non_void < 0 || first_non_void > 3)
1784 goto out_unknown;
1785
1786 /* uniform formats */
1787 switch (desc->channel[first_non_void].size) {
1788 case 4:
1789 switch (desc->nr_channels) {
1790 #if 0 /* Not supported for render targets */
1791 case 2:
1792 return V_008F14_IMG_DATA_FORMAT_4_4;
1793 #endif
1794 case 4:
1795 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1796 }
1797 break;
1798 case 8:
1799 switch (desc->nr_channels) {
1800 case 1:
1801 return V_008F14_IMG_DATA_FORMAT_8;
1802 case 2:
1803 return V_008F14_IMG_DATA_FORMAT_8_8;
1804 case 4:
1805 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1806 }
1807 break;
1808 case 16:
1809 switch (desc->nr_channels) {
1810 case 1:
1811 return V_008F14_IMG_DATA_FORMAT_16;
1812 case 2:
1813 return V_008F14_IMG_DATA_FORMAT_16_16;
1814 case 4:
1815 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1816 }
1817 break;
1818 case 32:
1819 switch (desc->nr_channels) {
1820 case 1:
1821 return V_008F14_IMG_DATA_FORMAT_32;
1822 case 2:
1823 return V_008F14_IMG_DATA_FORMAT_32_32;
1824 #if 0 /* Not supported for render targets */
1825 case 3:
1826 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1827 #endif
1828 case 4:
1829 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1830 }
1831 }
1832
1833 out_unknown:
1834 return ~0;
1835 }
1836
1837 static unsigned si_tex_wrap(unsigned wrap)
1838 {
1839 switch (wrap) {
1840 default:
1841 case PIPE_TEX_WRAP_REPEAT:
1842 return V_008F30_SQ_TEX_WRAP;
1843 case PIPE_TEX_WRAP_CLAMP:
1844 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1845 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1846 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1847 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1848 return V_008F30_SQ_TEX_CLAMP_BORDER;
1849 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1850 return V_008F30_SQ_TEX_MIRROR;
1851 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1852 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1853 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1854 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1855 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1856 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1857 }
1858 }
1859
1860 static unsigned si_tex_mipfilter(unsigned filter)
1861 {
1862 switch (filter) {
1863 case PIPE_TEX_MIPFILTER_NEAREST:
1864 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1865 case PIPE_TEX_MIPFILTER_LINEAR:
1866 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1867 default:
1868 case PIPE_TEX_MIPFILTER_NONE:
1869 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1870 }
1871 }
1872
1873 static unsigned si_tex_compare(unsigned compare)
1874 {
1875 switch (compare) {
1876 default:
1877 case PIPE_FUNC_NEVER:
1878 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1879 case PIPE_FUNC_LESS:
1880 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1881 case PIPE_FUNC_EQUAL:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1883 case PIPE_FUNC_LEQUAL:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1885 case PIPE_FUNC_GREATER:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1887 case PIPE_FUNC_NOTEQUAL:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1889 case PIPE_FUNC_GEQUAL:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1891 case PIPE_FUNC_ALWAYS:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1893 }
1894 }
1895
1896 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1897 unsigned view_target, unsigned nr_samples)
1898 {
1899 unsigned res_target = rtex->buffer.b.b.target;
1900
1901 if (view_target == PIPE_TEXTURE_CUBE ||
1902 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1903 res_target = view_target;
1904 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1905 else if (res_target == PIPE_TEXTURE_CUBE ||
1906 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1907 res_target = PIPE_TEXTURE_2D_ARRAY;
1908
1909 /* GFX9 allocates 1D textures as 2D. */
1910 if ((res_target == PIPE_TEXTURE_1D ||
1911 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1912 sscreen->info.chip_class >= GFX9 &&
1913 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1914 if (res_target == PIPE_TEXTURE_1D)
1915 res_target = PIPE_TEXTURE_2D;
1916 else
1917 res_target = PIPE_TEXTURE_2D_ARRAY;
1918 }
1919
1920 switch (res_target) {
1921 default:
1922 case PIPE_TEXTURE_1D:
1923 return V_008F1C_SQ_RSRC_IMG_1D;
1924 case PIPE_TEXTURE_1D_ARRAY:
1925 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1926 case PIPE_TEXTURE_2D:
1927 case PIPE_TEXTURE_RECT:
1928 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1929 V_008F1C_SQ_RSRC_IMG_2D;
1930 case PIPE_TEXTURE_2D_ARRAY:
1931 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1932 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1933 case PIPE_TEXTURE_3D:
1934 return V_008F1C_SQ_RSRC_IMG_3D;
1935 case PIPE_TEXTURE_CUBE:
1936 case PIPE_TEXTURE_CUBE_ARRAY:
1937 return V_008F1C_SQ_RSRC_IMG_CUBE;
1938 }
1939 }
1940
1941 /*
1942 * Format support testing
1943 */
1944
1945 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1946 {
1947 const struct util_format_description *desc = util_format_description(format);
1948 if (!desc)
1949 return false;
1950
1951 return si_translate_texformat(screen, format, desc,
1952 util_format_get_first_non_void_channel(format)) != ~0U;
1953 }
1954
1955 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1956 const struct util_format_description *desc,
1957 int first_non_void)
1958 {
1959 int i;
1960
1961 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1962 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1963
1964 assert(first_non_void >= 0);
1965
1966 if (desc->nr_channels == 4 &&
1967 desc->channel[0].size == 10 &&
1968 desc->channel[1].size == 10 &&
1969 desc->channel[2].size == 10 &&
1970 desc->channel[3].size == 2)
1971 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1972
1973 /* See whether the components are of the same size. */
1974 for (i = 0; i < desc->nr_channels; i++) {
1975 if (desc->channel[first_non_void].size != desc->channel[i].size)
1976 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1977 }
1978
1979 switch (desc->channel[first_non_void].size) {
1980 case 8:
1981 switch (desc->nr_channels) {
1982 case 1:
1983 case 3: /* 3 loads */
1984 return V_008F0C_BUF_DATA_FORMAT_8;
1985 case 2:
1986 return V_008F0C_BUF_DATA_FORMAT_8_8;
1987 case 4:
1988 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1989 }
1990 break;
1991 case 16:
1992 switch (desc->nr_channels) {
1993 case 1:
1994 case 3: /* 3 loads */
1995 return V_008F0C_BUF_DATA_FORMAT_16;
1996 case 2:
1997 return V_008F0C_BUF_DATA_FORMAT_16_16;
1998 case 4:
1999 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2000 }
2001 break;
2002 case 32:
2003 switch (desc->nr_channels) {
2004 case 1:
2005 return V_008F0C_BUF_DATA_FORMAT_32;
2006 case 2:
2007 return V_008F0C_BUF_DATA_FORMAT_32_32;
2008 case 3:
2009 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2010 case 4:
2011 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2012 }
2013 break;
2014 case 64:
2015 /* Legacy double formats. */
2016 switch (desc->nr_channels) {
2017 case 1: /* 1 load */
2018 return V_008F0C_BUF_DATA_FORMAT_32_32;
2019 case 2: /* 1 load */
2020 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2021 case 3: /* 3 loads */
2022 return V_008F0C_BUF_DATA_FORMAT_32_32;
2023 case 4: /* 2 loads */
2024 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2025 }
2026 break;
2027 }
2028
2029 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2030 }
2031
2032 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2033 const struct util_format_description *desc,
2034 int first_non_void)
2035 {
2036 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2037 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2038
2039 assert(first_non_void >= 0);
2040
2041 switch (desc->channel[first_non_void].type) {
2042 case UTIL_FORMAT_TYPE_SIGNED:
2043 case UTIL_FORMAT_TYPE_FIXED:
2044 if (desc->channel[first_non_void].size >= 32 ||
2045 desc->channel[first_non_void].pure_integer)
2046 return V_008F0C_BUF_NUM_FORMAT_SINT;
2047 else if (desc->channel[first_non_void].normalized)
2048 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2049 else
2050 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2051 break;
2052 case UTIL_FORMAT_TYPE_UNSIGNED:
2053 if (desc->channel[first_non_void].size >= 32 ||
2054 desc->channel[first_non_void].pure_integer)
2055 return V_008F0C_BUF_NUM_FORMAT_UINT;
2056 else if (desc->channel[first_non_void].normalized)
2057 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2058 else
2059 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2060 break;
2061 case UTIL_FORMAT_TYPE_FLOAT:
2062 default:
2063 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2064 }
2065 }
2066
2067 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2068 enum pipe_format format,
2069 unsigned usage)
2070 {
2071 const struct util_format_description *desc;
2072 int first_non_void;
2073 unsigned data_format;
2074
2075 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2076 PIPE_BIND_SAMPLER_VIEW |
2077 PIPE_BIND_VERTEX_BUFFER)) == 0);
2078
2079 desc = util_format_description(format);
2080 if (!desc)
2081 return 0;
2082
2083 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2084 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2085 * for read-only access (with caveats surrounding bounds checks), but
2086 * obviously fails for write access which we have to implement for
2087 * shader images. Luckily, OpenGL doesn't expect this to be supported
2088 * anyway, and so the only impact is on PBO uploads / downloads, which
2089 * shouldn't be expected to be fast for GL_RGB anyway.
2090 */
2091 if (desc->block.bits == 3 * 8 ||
2092 desc->block.bits == 3 * 16) {
2093 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2094 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2095 if (!usage)
2096 return 0;
2097 }
2098 }
2099
2100 first_non_void = util_format_get_first_non_void_channel(format);
2101 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2102 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2103 return 0;
2104
2105 return usage;
2106 }
2107
2108 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2109 {
2110 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2111 si_translate_colorswap(format, false) != ~0U;
2112 }
2113
2114 static bool si_is_zs_format_supported(enum pipe_format format)
2115 {
2116 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2117 }
2118
2119 static boolean si_is_format_supported(struct pipe_screen *screen,
2120 enum pipe_format format,
2121 enum pipe_texture_target target,
2122 unsigned sample_count,
2123 unsigned usage)
2124 {
2125 struct si_screen *sscreen = (struct si_screen *)screen;
2126 unsigned retval = 0;
2127
2128 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2129 PRINT_ERR("r600: unsupported texture type %d\n", target);
2130 return false;
2131 }
2132
2133 if (!util_format_is_supported(format, usage))
2134 return false;
2135
2136 if (sample_count > 1) {
2137 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2138 return false;
2139
2140 if (usage & PIPE_BIND_SHADER_IMAGE)
2141 return false;
2142
2143 switch (sample_count) {
2144 case 2:
2145 case 4:
2146 case 8:
2147 break;
2148 case 16:
2149 /* Allow resource_copy_region with nr_samples == 16. */
2150 if (sscreen->eqaa_force_coverage_samples == 16 &&
2151 !util_format_is_depth_or_stencil(format))
2152 return true;
2153 if (format == PIPE_FORMAT_NONE)
2154 return true;
2155 else
2156 return false;
2157 default:
2158 return false;
2159 }
2160 }
2161
2162 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2163 PIPE_BIND_SHADER_IMAGE)) {
2164 if (target == PIPE_BUFFER) {
2165 retval |= si_is_vertex_format_supported(
2166 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2167 PIPE_BIND_SHADER_IMAGE));
2168 } else {
2169 if (si_is_sampler_format_supported(screen, format))
2170 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2171 PIPE_BIND_SHADER_IMAGE);
2172 }
2173 }
2174
2175 if ((usage & (PIPE_BIND_RENDER_TARGET |
2176 PIPE_BIND_DISPLAY_TARGET |
2177 PIPE_BIND_SCANOUT |
2178 PIPE_BIND_SHARED |
2179 PIPE_BIND_BLENDABLE)) &&
2180 si_is_colorbuffer_format_supported(format)) {
2181 retval |= usage &
2182 (PIPE_BIND_RENDER_TARGET |
2183 PIPE_BIND_DISPLAY_TARGET |
2184 PIPE_BIND_SCANOUT |
2185 PIPE_BIND_SHARED);
2186 if (!util_format_is_pure_integer(format) &&
2187 !util_format_is_depth_or_stencil(format))
2188 retval |= usage & PIPE_BIND_BLENDABLE;
2189 }
2190
2191 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2192 si_is_zs_format_supported(format)) {
2193 retval |= PIPE_BIND_DEPTH_STENCIL;
2194 }
2195
2196 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2197 retval |= si_is_vertex_format_supported(screen, format,
2198 PIPE_BIND_VERTEX_BUFFER);
2199 }
2200
2201 if ((usage & PIPE_BIND_LINEAR) &&
2202 !util_format_is_compressed(format) &&
2203 !(usage & PIPE_BIND_DEPTH_STENCIL))
2204 retval |= PIPE_BIND_LINEAR;
2205
2206 return retval == usage;
2207 }
2208
2209 /*
2210 * framebuffer handling
2211 */
2212
2213 static void si_choose_spi_color_formats(struct r600_surface *surf,
2214 unsigned format, unsigned swap,
2215 unsigned ntype, bool is_depth)
2216 {
2217 /* Alpha is needed for alpha-to-coverage.
2218 * Blending may be with or without alpha.
2219 */
2220 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2221 unsigned alpha = 0; /* exports alpha, but may not support blending */
2222 unsigned blend = 0; /* supports blending, but may not export alpha */
2223 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2224
2225 /* Choose the SPI color formats. These are required values for RB+.
2226 * Other chips have multiple choices, though they are not necessarily better.
2227 */
2228 switch (format) {
2229 case V_028C70_COLOR_5_6_5:
2230 case V_028C70_COLOR_1_5_5_5:
2231 case V_028C70_COLOR_5_5_5_1:
2232 case V_028C70_COLOR_4_4_4_4:
2233 case V_028C70_COLOR_10_11_11:
2234 case V_028C70_COLOR_11_11_10:
2235 case V_028C70_COLOR_8:
2236 case V_028C70_COLOR_8_8:
2237 case V_028C70_COLOR_8_8_8_8:
2238 case V_028C70_COLOR_10_10_10_2:
2239 case V_028C70_COLOR_2_10_10_10:
2240 if (ntype == V_028C70_NUMBER_UINT)
2241 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2242 else if (ntype == V_028C70_NUMBER_SINT)
2243 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2244 else
2245 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2246 break;
2247
2248 case V_028C70_COLOR_16:
2249 case V_028C70_COLOR_16_16:
2250 case V_028C70_COLOR_16_16_16_16:
2251 if (ntype == V_028C70_NUMBER_UNORM ||
2252 ntype == V_028C70_NUMBER_SNORM) {
2253 /* UNORM16 and SNORM16 don't support blending */
2254 if (ntype == V_028C70_NUMBER_UNORM)
2255 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2256 else
2257 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2258
2259 /* Use 32 bits per channel for blending. */
2260 if (format == V_028C70_COLOR_16) {
2261 if (swap == V_028C70_SWAP_STD) { /* R */
2262 blend = V_028714_SPI_SHADER_32_R;
2263 blend_alpha = V_028714_SPI_SHADER_32_AR;
2264 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2265 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2266 else
2267 assert(0);
2268 } else if (format == V_028C70_COLOR_16_16) {
2269 if (swap == V_028C70_SWAP_STD) { /* RG */
2270 blend = V_028714_SPI_SHADER_32_GR;
2271 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2272 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2273 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2274 else
2275 assert(0);
2276 } else /* 16_16_16_16 */
2277 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2278 } else if (ntype == V_028C70_NUMBER_UINT)
2279 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2280 else if (ntype == V_028C70_NUMBER_SINT)
2281 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2282 else if (ntype == V_028C70_NUMBER_FLOAT)
2283 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2284 else
2285 assert(0);
2286 break;
2287
2288 case V_028C70_COLOR_32:
2289 if (swap == V_028C70_SWAP_STD) { /* R */
2290 blend = normal = V_028714_SPI_SHADER_32_R;
2291 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2292 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2293 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2294 else
2295 assert(0);
2296 break;
2297
2298 case V_028C70_COLOR_32_32:
2299 if (swap == V_028C70_SWAP_STD) { /* RG */
2300 blend = normal = V_028714_SPI_SHADER_32_GR;
2301 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2302 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2303 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2304 else
2305 assert(0);
2306 break;
2307
2308 case V_028C70_COLOR_32_32_32_32:
2309 case V_028C70_COLOR_8_24:
2310 case V_028C70_COLOR_24_8:
2311 case V_028C70_COLOR_X24_8_32_FLOAT:
2312 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2313 break;
2314
2315 default:
2316 assert(0);
2317 return;
2318 }
2319
2320 /* The DB->CB copy needs 32_ABGR. */
2321 if (is_depth)
2322 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2323
2324 surf->spi_shader_col_format = normal;
2325 surf->spi_shader_col_format_alpha = alpha;
2326 surf->spi_shader_col_format_blend = blend;
2327 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2328 }
2329
2330 static void si_initialize_color_surface(struct si_context *sctx,
2331 struct r600_surface *surf)
2332 {
2333 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2334 unsigned color_info, color_attrib;
2335 unsigned format, swap, ntype, endian;
2336 const struct util_format_description *desc;
2337 int firstchan;
2338 unsigned blend_clamp = 0, blend_bypass = 0;
2339
2340 desc = util_format_description(surf->base.format);
2341 for (firstchan = 0; firstchan < 4; firstchan++) {
2342 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2343 break;
2344 }
2345 }
2346 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2347 ntype = V_028C70_NUMBER_FLOAT;
2348 } else {
2349 ntype = V_028C70_NUMBER_UNORM;
2350 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2351 ntype = V_028C70_NUMBER_SRGB;
2352 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2353 if (desc->channel[firstchan].pure_integer) {
2354 ntype = V_028C70_NUMBER_SINT;
2355 } else {
2356 assert(desc->channel[firstchan].normalized);
2357 ntype = V_028C70_NUMBER_SNORM;
2358 }
2359 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2360 if (desc->channel[firstchan].pure_integer) {
2361 ntype = V_028C70_NUMBER_UINT;
2362 } else {
2363 assert(desc->channel[firstchan].normalized);
2364 ntype = V_028C70_NUMBER_UNORM;
2365 }
2366 }
2367 }
2368
2369 format = si_translate_colorformat(surf->base.format);
2370 if (format == V_028C70_COLOR_INVALID) {
2371 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2372 }
2373 assert(format != V_028C70_COLOR_INVALID);
2374 swap = si_translate_colorswap(surf->base.format, false);
2375 endian = si_colorformat_endian_swap(format);
2376
2377 /* blend clamp should be set for all NORM/SRGB types */
2378 if (ntype == V_028C70_NUMBER_UNORM ||
2379 ntype == V_028C70_NUMBER_SNORM ||
2380 ntype == V_028C70_NUMBER_SRGB)
2381 blend_clamp = 1;
2382
2383 /* set blend bypass according to docs if SINT/UINT or
2384 8/24 COLOR variants */
2385 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2386 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2387 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2388 blend_clamp = 0;
2389 blend_bypass = 1;
2390 }
2391
2392 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2393 if (format == V_028C70_COLOR_8 ||
2394 format == V_028C70_COLOR_8_8 ||
2395 format == V_028C70_COLOR_8_8_8_8)
2396 surf->color_is_int8 = true;
2397 else if (format == V_028C70_COLOR_10_10_10_2 ||
2398 format == V_028C70_COLOR_2_10_10_10)
2399 surf->color_is_int10 = true;
2400 }
2401
2402 color_info = S_028C70_FORMAT(format) |
2403 S_028C70_COMP_SWAP(swap) |
2404 S_028C70_BLEND_CLAMP(blend_clamp) |
2405 S_028C70_BLEND_BYPASS(blend_bypass) |
2406 S_028C70_SIMPLE_FLOAT(1) |
2407 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2408 ntype != V_028C70_NUMBER_SNORM &&
2409 ntype != V_028C70_NUMBER_SRGB &&
2410 format != V_028C70_COLOR_8_24 &&
2411 format != V_028C70_COLOR_24_8) |
2412 S_028C70_NUMBER_TYPE(ntype) |
2413 S_028C70_ENDIAN(endian);
2414
2415 /* Intensity is implemented as Red, so treat it that way. */
2416 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2417 util_format_is_intensity(surf->base.format));
2418
2419 if (rtex->buffer.b.b.nr_samples > 1) {
2420 unsigned log_samples = util_logbase2(rtex->buffer.b.b.nr_samples);
2421 unsigned log_fragments = util_logbase2(rtex->num_color_samples);
2422
2423 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2424 S_028C74_NUM_FRAGMENTS(log_fragments);
2425
2426 if (rtex->surface.fmask_size) {
2427 color_info |= S_028C70_COMPRESSION(1);
2428 unsigned fmask_bankh = util_logbase2(rtex->surface.u.legacy.fmask.bankh);
2429
2430 if (sctx->chip_class == SI) {
2431 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2432 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2433 }
2434 }
2435 }
2436
2437 if (sctx->chip_class >= VI) {
2438 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2439 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2440
2441 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2442 64 for APU because all of our APUs to date use DIMMs which have
2443 a request granularity size of 64B while all other chips have a
2444 32B request size */
2445 if (!sctx->screen->info.has_dedicated_vram)
2446 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2447
2448 if (rtex->num_color_samples > 1) {
2449 if (rtex->surface.bpe == 1)
2450 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2451 else if (rtex->surface.bpe == 2)
2452 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2453 }
2454
2455 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2456 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2457 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2458 }
2459
2460 /* This must be set for fast clear to work without FMASK. */
2461 if (!rtex->surface.fmask_size && sctx->chip_class == SI) {
2462 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2463 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2464 }
2465
2466 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2467 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2468
2469 if (sctx->chip_class >= GFX9) {
2470 unsigned mip0_depth = util_max_layer(&rtex->buffer.b.b, 0);
2471
2472 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2473 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2474 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2475 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2476 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2477 S_028C68_MAX_MIP(rtex->buffer.b.b.last_level);
2478 }
2479
2480 surf->cb_color_view = color_view;
2481 surf->cb_color_info = color_info;
2482 surf->cb_color_attrib = color_attrib;
2483
2484 /* Determine pixel shader export format */
2485 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2486
2487 surf->color_initialized = true;
2488 }
2489
2490 static void si_init_depth_surface(struct si_context *sctx,
2491 struct r600_surface *surf)
2492 {
2493 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2494 unsigned level = surf->base.u.tex.level;
2495 unsigned format, stencil_format;
2496 uint32_t z_info, s_info;
2497
2498 format = si_translate_dbformat(rtex->db_render_format);
2499 stencil_format = rtex->surface.has_stencil ?
2500 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2501
2502 assert(format != V_028040_Z_INVALID);
2503 if (format == V_028040_Z_INVALID)
2504 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->buffer.b.b.format);
2505
2506 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2507 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2508 surf->db_htile_data_base = 0;
2509 surf->db_htile_surface = 0;
2510
2511 if (sctx->chip_class >= GFX9) {
2512 assert(rtex->surface.u.gfx9.surf_offset == 0);
2513 surf->db_depth_base = rtex->buffer.gpu_address >> 8;
2514 surf->db_stencil_base = (rtex->buffer.gpu_address +
2515 rtex->surface.u.gfx9.stencil_offset) >> 8;
2516 z_info = S_028038_FORMAT(format) |
2517 S_028038_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples)) |
2518 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2519 S_028038_MAXMIP(rtex->buffer.b.b.last_level);
2520 s_info = S_02803C_FORMAT(stencil_format) |
2521 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2522 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2523 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2524 surf->db_depth_view |= S_028008_MIPID(level);
2525 surf->db_depth_size = S_02801C_X_MAX(rtex->buffer.b.b.width0 - 1) |
2526 S_02801C_Y_MAX(rtex->buffer.b.b.height0 - 1);
2527
2528 if (si_htile_enabled(rtex, level)) {
2529 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2530 S_028038_ALLOW_EXPCLEAR(1);
2531
2532 if (rtex->tc_compatible_htile) {
2533 unsigned max_zplanes = 4;
2534
2535 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2536 rtex->buffer.b.b.nr_samples > 1)
2537 max_zplanes = 2;
2538
2539 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2540 S_028038_ITERATE_FLUSH(1);
2541 s_info |= S_02803C_ITERATE_FLUSH(1);
2542 }
2543
2544 if (rtex->surface.has_stencil) {
2545 /* Stencil buffer workaround ported from the SI-CI-VI code.
2546 * See that for explanation.
2547 */
2548 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->buffer.b.b.nr_samples <= 1);
2549 } else {
2550 /* Use all HTILE for depth if there's no stencil. */
2551 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2552 }
2553
2554 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2555 rtex->htile_offset) >> 8;
2556 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2557 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2558 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2559 }
2560 } else {
2561 /* SI-CI-VI */
2562 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2563
2564 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2565
2566 surf->db_depth_base = (rtex->buffer.gpu_address +
2567 rtex->surface.u.legacy.level[level].offset) >> 8;
2568 surf->db_stencil_base = (rtex->buffer.gpu_address +
2569 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2570
2571 z_info = S_028040_FORMAT(format) |
2572 S_028040_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples));
2573 s_info = S_028044_FORMAT(stencil_format);
2574 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2575
2576 if (sctx->chip_class >= CIK) {
2577 struct radeon_info *info = &sctx->screen->info;
2578 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2579 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2580 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2581 unsigned tile_mode = info->si_tile_mode_array[index];
2582 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2583 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2584
2585 surf->db_depth_info |=
2586 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2587 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2588 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2589 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2590 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2591 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2592 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2593 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2594 } else {
2595 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2596 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2597 tile_mode_index = si_tile_mode_index(rtex, level, true);
2598 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2599 }
2600
2601 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2602 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2603 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2604 levelinfo->nblk_y) / 64 - 1);
2605
2606 if (si_htile_enabled(rtex, level)) {
2607 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2608 S_028040_ALLOW_EXPCLEAR(1);
2609
2610 if (rtex->surface.has_stencil) {
2611 /* Workaround: For a not yet understood reason, the
2612 * combination of MSAA, fast stencil clear and stencil
2613 * decompress messes with subsequent stencil buffer
2614 * uses. Problem was reproduced on Verde, Bonaire,
2615 * Tonga, and Carrizo.
2616 *
2617 * Disabling EXPCLEAR works around the problem.
2618 *
2619 * Check piglit's arb_texture_multisample-stencil-clear
2620 * test if you want to try changing this.
2621 */
2622 if (rtex->buffer.b.b.nr_samples <= 1)
2623 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2624 } else if (!rtex->tc_compatible_htile) {
2625 /* Use all of the htile_buffer for depth if there's no stencil.
2626 * This must not be set when TC-compatible HTILE is enabled
2627 * due to a hw bug.
2628 */
2629 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2630 }
2631
2632 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2633 rtex->htile_offset) >> 8;
2634 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2635
2636 if (rtex->tc_compatible_htile) {
2637 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2638
2639 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2640 if (rtex->buffer.b.b.nr_samples <= 1)
2641 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2642 else if (rtex->buffer.b.b.nr_samples <= 4)
2643 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2644 else
2645 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2646 }
2647 }
2648 }
2649
2650 surf->db_z_info = z_info;
2651 surf->db_stencil_info = s_info;
2652
2653 surf->depth_initialized = true;
2654 }
2655
2656 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2657 {
2658 if (sctx->decompression_enabled)
2659 return;
2660
2661 if (sctx->framebuffer.state.zsbuf) {
2662 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2663 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2664
2665 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2666
2667 if (rtex->surface.has_stencil)
2668 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2669 }
2670
2671 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2672 while (compressed_cb_mask) {
2673 unsigned i = u_bit_scan(&compressed_cb_mask);
2674 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2675 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2676
2677 if (rtex->surface.fmask_size)
2678 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2679 if (rtex->dcc_gather_statistics)
2680 rtex->separate_dcc_dirty = true;
2681 }
2682 }
2683
2684 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2685 {
2686 for (int i = 0; i < state->nr_cbufs; ++i) {
2687 struct r600_surface *surf = NULL;
2688 struct r600_texture *rtex;
2689
2690 if (!state->cbufs[i])
2691 continue;
2692 surf = (struct r600_surface*)state->cbufs[i];
2693 rtex = (struct r600_texture*)surf->base.texture;
2694
2695 p_atomic_dec(&rtex->framebuffers_bound);
2696 }
2697 }
2698
2699 static void si_set_framebuffer_state(struct pipe_context *ctx,
2700 const struct pipe_framebuffer_state *state)
2701 {
2702 struct si_context *sctx = (struct si_context *)ctx;
2703 struct pipe_constant_buffer constbuf = {0};
2704 struct r600_surface *surf = NULL;
2705 struct r600_texture *rtex;
2706 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2707 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2708 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2709 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2710 bool old_has_stencil =
2711 old_has_zsbuf &&
2712 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2713 bool unbound = false;
2714 int i;
2715
2716 si_update_fb_dirtiness_after_rendering(sctx);
2717
2718 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2719 if (!sctx->framebuffer.state.cbufs[i])
2720 continue;
2721
2722 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2723 if (rtex->dcc_gather_statistics)
2724 vi_separate_dcc_stop_query(sctx, rtex);
2725 }
2726
2727 /* Disable DCC if the formats are incompatible. */
2728 for (i = 0; i < state->nr_cbufs; i++) {
2729 if (!state->cbufs[i])
2730 continue;
2731
2732 surf = (struct r600_surface*)state->cbufs[i];
2733 rtex = (struct r600_texture*)surf->base.texture;
2734
2735 if (!surf->dcc_incompatible)
2736 continue;
2737
2738 /* Since the DCC decompression calls back into set_framebuffer-
2739 * _state, we need to unbind the framebuffer, so that
2740 * vi_separate_dcc_stop_query isn't called twice with the same
2741 * color buffer.
2742 */
2743 if (!unbound) {
2744 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2745 unbound = true;
2746 }
2747
2748 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2749 if (!si_texture_disable_dcc(sctx, rtex))
2750 si_decompress_dcc(sctx, rtex);
2751
2752 surf->dcc_incompatible = false;
2753 }
2754
2755 /* Only flush TC when changing the framebuffer state, because
2756 * the only client not using TC that can change textures is
2757 * the framebuffer.
2758 *
2759 * Wait for compute shaders because of possible transitions:
2760 * - FB write -> shader read
2761 * - shader write -> FB read
2762 *
2763 * DB caches are flushed on demand (using si_decompress_textures).
2764 *
2765 * When MSAA is enabled, CB and TC caches are flushed on demand
2766 * (after FMASK decompression). Shader write -> FB read transitions
2767 * cannot happen for MSAA textures, because MSAA shader images are
2768 * not supported.
2769 *
2770 * Only flush and wait for CB if there is actually a bound color buffer.
2771 */
2772 if (sctx->framebuffer.uncompressed_cb_mask)
2773 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2774 sctx->framebuffer.CB_has_shader_readable_metadata);
2775
2776 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2777
2778 /* u_blitter doesn't invoke depth decompression when it does multiple
2779 * blits in a row, but the only case when it matters for DB is when
2780 * doing generate_mipmap. So here we flush DB manually between
2781 * individual generate_mipmap blits.
2782 * Note that lower mipmap levels aren't compressed.
2783 */
2784 if (sctx->generate_mipmap_for_depth) {
2785 si_make_DB_shader_coherent(sctx, 1, false,
2786 sctx->framebuffer.DB_has_shader_readable_metadata);
2787 } else if (sctx->chip_class == GFX9) {
2788 /* It appears that DB metadata "leaks" in a sequence of:
2789 * - depth clear
2790 * - DCC decompress for shader image writes (with DB disabled)
2791 * - render with DEPTH_BEFORE_SHADER=1
2792 * Flushing DB metadata works around the problem.
2793 */
2794 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2795 }
2796
2797 /* Take the maximum of the old and new count. If the new count is lower,
2798 * dirtying is needed to disable the unbound colorbuffers.
2799 */
2800 sctx->framebuffer.dirty_cbufs |=
2801 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2802 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2803
2804 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2805 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2806
2807 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2808 sctx->framebuffer.spi_shader_col_format = 0;
2809 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2810 sctx->framebuffer.spi_shader_col_format_blend = 0;
2811 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2812 sctx->framebuffer.color_is_int8 = 0;
2813 sctx->framebuffer.color_is_int10 = 0;
2814
2815 sctx->framebuffer.compressed_cb_mask = 0;
2816 sctx->framebuffer.uncompressed_cb_mask = 0;
2817 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2818 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2819 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2820 sctx->framebuffer.any_dst_linear = false;
2821 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2822 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2823
2824 for (i = 0; i < state->nr_cbufs; i++) {
2825 if (!state->cbufs[i])
2826 continue;
2827
2828 surf = (struct r600_surface*)state->cbufs[i];
2829 rtex = (struct r600_texture*)surf->base.texture;
2830
2831 if (!surf->color_initialized) {
2832 si_initialize_color_surface(sctx, surf);
2833 }
2834
2835 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2836 sctx->framebuffer.spi_shader_col_format |=
2837 surf->spi_shader_col_format << (i * 4);
2838 sctx->framebuffer.spi_shader_col_format_alpha |=
2839 surf->spi_shader_col_format_alpha << (i * 4);
2840 sctx->framebuffer.spi_shader_col_format_blend |=
2841 surf->spi_shader_col_format_blend << (i * 4);
2842 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2843 surf->spi_shader_col_format_blend_alpha << (i * 4);
2844
2845 if (surf->color_is_int8)
2846 sctx->framebuffer.color_is_int8 |= 1 << i;
2847 if (surf->color_is_int10)
2848 sctx->framebuffer.color_is_int10 |= 1 << i;
2849
2850 if (rtex->surface.fmask_size)
2851 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2852 else
2853 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2854
2855 /* Don't update nr_color_samples for non-AA buffers.
2856 * (e.g. destination of MSAA resolve)
2857 */
2858 if (rtex->buffer.b.b.nr_samples >= 2 &&
2859 rtex->num_color_samples < rtex->buffer.b.b.nr_samples) {
2860 sctx->framebuffer.nr_color_samples =
2861 MIN2(sctx->framebuffer.nr_color_samples,
2862 rtex->num_color_samples);
2863 }
2864
2865 if (rtex->surface.is_linear)
2866 sctx->framebuffer.any_dst_linear = true;
2867
2868 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2869 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2870
2871 si_context_add_resource_size(sctx, surf->base.texture);
2872
2873 p_atomic_inc(&rtex->framebuffers_bound);
2874
2875 if (rtex->dcc_gather_statistics) {
2876 /* Dirty tracking must be enabled for DCC usage analysis. */
2877 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2878 vi_separate_dcc_start_query(sctx, rtex);
2879 }
2880 }
2881
2882 struct r600_texture *zstex = NULL;
2883
2884 if (state->zsbuf) {
2885 surf = (struct r600_surface*)state->zsbuf;
2886 zstex = (struct r600_texture*)surf->base.texture;
2887
2888 if (!surf->depth_initialized) {
2889 si_init_depth_surface(sctx, surf);
2890 }
2891
2892 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2893 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2894
2895 si_context_add_resource_size(sctx, surf->base.texture);
2896 }
2897
2898 si_update_ps_colorbuf0_slot(sctx);
2899 si_update_poly_offset_state(sctx);
2900 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2901 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2902
2903 if (sctx->screen->dpbb_allowed)
2904 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2905
2906 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2907 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2908
2909 if (sctx->screen->has_out_of_order_rast &&
2910 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2911 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2912 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2913 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2914
2915 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2916 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2917 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2918
2919 /* Set sample locations as fragment shader constants. */
2920 switch (sctx->framebuffer.nr_samples) {
2921 case 1:
2922 constbuf.user_buffer = sctx->sample_locations_1x;
2923 break;
2924 case 2:
2925 constbuf.user_buffer = sctx->sample_locations_2x;
2926 break;
2927 case 4:
2928 constbuf.user_buffer = sctx->sample_locations_4x;
2929 break;
2930 case 8:
2931 constbuf.user_buffer = sctx->sample_locations_8x;
2932 break;
2933 case 16:
2934 constbuf.user_buffer = sctx->sample_locations_16x;
2935 break;
2936 default:
2937 PRINT_ERR("Requested an invalid number of samples %i.\n",
2938 sctx->framebuffer.nr_samples);
2939 assert(0);
2940 }
2941 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2942 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2943
2944 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2945 }
2946
2947 sctx->do_update_shaders = true;
2948
2949 if (!sctx->decompression_enabled) {
2950 /* Prevent textures decompression when the framebuffer state
2951 * changes come from the decompression passes themselves.
2952 */
2953 sctx->need_check_render_feedback = true;
2954 }
2955 }
2956
2957 static void si_emit_framebuffer_state(struct si_context *sctx)
2958 {
2959 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2960 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2961 unsigned i, nr_cbufs = state->nr_cbufs;
2962 struct r600_texture *tex = NULL;
2963 struct r600_surface *cb = NULL;
2964 unsigned cb_color_info = 0;
2965
2966 /* Colorbuffers. */
2967 for (i = 0; i < nr_cbufs; i++) {
2968 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2969 unsigned cb_color_attrib;
2970
2971 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2972 continue;
2973
2974 cb = (struct r600_surface*)state->cbufs[i];
2975 if (!cb) {
2976 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2977 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2978 continue;
2979 }
2980
2981 tex = (struct r600_texture *)cb->base.texture;
2982 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2983 &tex->buffer, RADEON_USAGE_READWRITE,
2984 tex->buffer.b.b.nr_samples > 1 ?
2985 RADEON_PRIO_COLOR_BUFFER_MSAA :
2986 RADEON_PRIO_COLOR_BUFFER);
2987
2988 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2989 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2990 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2991 RADEON_PRIO_CMASK);
2992 }
2993
2994 if (tex->dcc_separate_buffer)
2995 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2996 tex->dcc_separate_buffer,
2997 RADEON_USAGE_READWRITE,
2998 RADEON_PRIO_DCC);
2999
3000 /* Compute mutable surface parameters. */
3001 cb_color_base = tex->buffer.gpu_address >> 8;
3002 cb_color_fmask = 0;
3003 cb_color_cmask = tex->cmask.base_address_reg;
3004 cb_dcc_base = 0;
3005 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3006 cb_color_attrib = cb->cb_color_attrib;
3007
3008 if (cb->base.u.tex.level > 0)
3009 cb_color_info &= C_028C70_FAST_CLEAR;
3010
3011 if (tex->surface.fmask_size) {
3012 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3013 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3014 }
3015
3016 /* Set up DCC. */
3017 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3018 bool is_msaa_resolve_dst = state->cbufs[0] &&
3019 state->cbufs[0]->texture->nr_samples > 1 &&
3020 state->cbufs[1] == &cb->base &&
3021 state->cbufs[1]->texture->nr_samples <= 1;
3022
3023 if (!is_msaa_resolve_dst)
3024 cb_color_info |= S_028C70_DCC_ENABLE(1);
3025
3026 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3027 tex->dcc_offset) >> 8;
3028 cb_dcc_base |= tex->surface.tile_swizzle;
3029 }
3030
3031 if (sctx->chip_class >= GFX9) {
3032 struct gfx9_surf_meta_flags meta;
3033
3034 if (tex->dcc_offset)
3035 meta = tex->surface.u.gfx9.dcc;
3036 else
3037 meta = tex->surface.u.gfx9.cmask;
3038
3039 /* Set mutable surface parameters. */
3040 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3041 cb_color_base |= tex->surface.tile_swizzle;
3042 if (!tex->surface.fmask_size)
3043 cb_color_fmask = cb_color_base;
3044 if (cb->base.u.tex.level > 0)
3045 cb_color_cmask = cb_color_base;
3046 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3047 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3048 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3049 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3050
3051 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3052 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3053 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3054 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3055 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3056 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3057 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3058 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3059 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3060 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3061 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3062 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3063 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3064 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3065 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3066 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3067
3068 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3069 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3070 } else {
3071 /* Compute mutable surface parameters (SI-CI-VI). */
3072 const struct legacy_surf_level *level_info =
3073 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3074 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3075 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3076
3077 cb_color_base += level_info->offset >> 8;
3078 /* Only macrotiled modes can set tile swizzle. */
3079 if (level_info->mode == RADEON_SURF_MODE_2D)
3080 cb_color_base |= tex->surface.tile_swizzle;
3081
3082 if (!tex->surface.fmask_size)
3083 cb_color_fmask = cb_color_base;
3084 if (cb->base.u.tex.level > 0)
3085 cb_color_cmask = cb_color_base;
3086 if (cb_dcc_base)
3087 cb_dcc_base += level_info->dcc_offset >> 8;
3088
3089 pitch_tile_max = level_info->nblk_x / 8 - 1;
3090 slice_tile_max = level_info->nblk_x *
3091 level_info->nblk_y / 64 - 1;
3092 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3093
3094 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3095 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3096 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3097
3098 if (tex->surface.fmask_size) {
3099 if (sctx->chip_class >= CIK)
3100 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3101 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3102 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3103 } else {
3104 /* This must be set for fast clear to work without FMASK. */
3105 if (sctx->chip_class >= CIK)
3106 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3107 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3108 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3109 }
3110
3111 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3112 sctx->chip_class >= VI ? 14 : 13);
3113 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3114 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3115 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3116 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3117 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3118 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3119 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3120 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3121 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3122 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3123 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3124 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3125 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3126
3127 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3128 radeon_emit(cs, cb_dcc_base);
3129 }
3130 }
3131 for (; i < 8 ; i++)
3132 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3133 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3134
3135 /* ZS buffer. */
3136 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3137 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3138 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3139
3140 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3141 &rtex->buffer, RADEON_USAGE_READWRITE,
3142 zb->base.texture->nr_samples > 1 ?
3143 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3144 RADEON_PRIO_DEPTH_BUFFER);
3145
3146 if (sctx->chip_class >= GFX9) {
3147 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3148 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3149 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3150 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3151
3152 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3153 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3154 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3155 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3156 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3157 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3158 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3159 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3160 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3161 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3162 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3163 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3164
3165 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3166 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3167 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3168 } else {
3169 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3170
3171 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3172 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3173 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3174 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3175 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3176 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3177 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3178 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3179 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3180 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3181 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3182 }
3183
3184 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3185 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3186 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3187
3188 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3189 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3190 } else if (sctx->framebuffer.dirty_zsbuf) {
3191 if (sctx->chip_class >= GFX9)
3192 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3193 else
3194 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3195
3196 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3197 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3198 }
3199
3200 /* Framebuffer dimensions. */
3201 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3202 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3203 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3204
3205 if (sctx->screen->dfsm_allowed) {
3206 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3207 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3208 }
3209
3210 sctx->framebuffer.dirty_cbufs = 0;
3211 sctx->framebuffer.dirty_zsbuf = false;
3212 }
3213
3214 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3215 {
3216 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3217 unsigned nr_samples = sctx->framebuffer.nr_samples;
3218 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3219
3220 /* Smoothing (only possible with nr_samples == 1) uses the same
3221 * sample locations as the MSAA it simulates.
3222 */
3223 if (nr_samples <= 1 && sctx->smoothing_enabled)
3224 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3225
3226 /* On Polaris, the small primitive filter uses the sample locations
3227 * even when MSAA is off, so we need to make sure they're set to 0.
3228 */
3229 if (has_msaa_sample_loc_bug)
3230 nr_samples = MAX2(nr_samples, 1);
3231
3232 if (nr_samples != sctx->sample_locs_num_samples) {
3233 sctx->sample_locs_num_samples = nr_samples;
3234 si_emit_sample_locations(cs, nr_samples);
3235 }
3236
3237 if (sctx->family >= CHIP_POLARIS10) {
3238 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3239 unsigned small_prim_filter_cntl =
3240 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3241 /* line bug */
3242 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3243
3244 /* The alternative of setting sample locations to 0 would
3245 * require a DB flush to avoid Z errors, see
3246 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3247 */
3248 if (has_msaa_sample_loc_bug &&
3249 sctx->framebuffer.nr_samples > 1 &&
3250 rs && !rs->multisample_enable)
3251 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3252
3253 radeon_opt_set_context_reg(sctx,
3254 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3255 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3256 small_prim_filter_cntl);
3257 }
3258 }
3259
3260 static bool si_out_of_order_rasterization(struct si_context *sctx)
3261 {
3262 struct si_state_blend *blend = sctx->queued.named.blend;
3263 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3264
3265 if (!sctx->screen->has_out_of_order_rast)
3266 return false;
3267
3268 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3269
3270 if (blend) {
3271 colormask &= blend->cb_target_enabled_4bit;
3272 } else {
3273 colormask = 0;
3274 }
3275
3276 /* Conservative: No logic op. */
3277 if (colormask && blend->logicop_enable)
3278 return false;
3279
3280 struct si_dsa_order_invariance dsa_order_invariant = {
3281 .zs = true, .pass_set = true, .pass_last = false
3282 };
3283
3284 if (sctx->framebuffer.state.zsbuf) {
3285 struct r600_texture *zstex =
3286 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3287 bool has_stencil = zstex->surface.has_stencil;
3288 dsa_order_invariant = dsa->order_invariance[has_stencil];
3289 if (!dsa_order_invariant.zs)
3290 return false;
3291
3292 /* The set of PS invocations is always order invariant,
3293 * except when early Z/S tests are requested. */
3294 if (sctx->ps_shader.cso &&
3295 sctx->ps_shader.cso->info.writes_memory &&
3296 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3297 !dsa_order_invariant.pass_set)
3298 return false;
3299
3300 if (sctx->num_perfect_occlusion_queries != 0 &&
3301 !dsa_order_invariant.pass_set)
3302 return false;
3303 }
3304
3305 if (!colormask)
3306 return true;
3307
3308 unsigned blendmask = colormask & blend->blend_enable_4bit;
3309
3310 if (blendmask) {
3311 /* Only commutative blending. */
3312 if (blendmask & ~blend->commutative_4bit)
3313 return false;
3314
3315 if (!dsa_order_invariant.pass_set)
3316 return false;
3317 }
3318
3319 if (colormask & ~blendmask) {
3320 if (!dsa_order_invariant.pass_last)
3321 return false;
3322 }
3323
3324 return true;
3325 }
3326
3327 static void si_emit_msaa_config(struct si_context *sctx)
3328 {
3329 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3330 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3331 /* 33% faster rendering to linear color buffers */
3332 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3333 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3334 unsigned sc_mode_cntl_1 =
3335 S_028A4C_WALK_SIZE(dst_is_linear) |
3336 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3337 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3338 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3339 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3340 /* always 1: */
3341 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3342 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3343 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3344 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3345 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3346 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3347 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3348 S_028804_INCOHERENT_EQAA_READS(1) |
3349 S_028804_INTERPOLATE_COMP_Z(1) |
3350 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3351 unsigned coverage_samples, color_samples, z_samples;
3352
3353 /* S: Coverage samples (up to 16x):
3354 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3355 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3356 *
3357 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3358 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3359 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3360 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3361 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3362 * # Z samples).
3363 *
3364 * F: Color samples (up to 8x, must be <= coverage samples):
3365 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3366 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3367 *
3368 * Can be anything between coverage and color samples:
3369 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3370 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3371 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3372 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3373 * # All are currently set the same as coverage samples.
3374 *
3375 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3376 * flag for undefined color samples. A shader-based resolve must handle unknowns
3377 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3378 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3379 * useful. The CB resolve always drops unknowns.
3380 *
3381 * Sensible AA configurations:
3382 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3383 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3384 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3385 * EQAA 8s 8z 8f = 8x MSAA
3386 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3387 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3388 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3389 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3390 * EQAA 4s 4z 4f = 4x MSAA
3391 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3392 * EQAA 2s 2z 2f = 2x MSAA
3393 */
3394 if (sctx->framebuffer.nr_samples > 1) {
3395 coverage_samples = sctx->framebuffer.nr_samples;
3396 color_samples = sctx->framebuffer.nr_color_samples;
3397
3398 if (sctx->framebuffer.state.zsbuf) {
3399 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3400 z_samples = MAX2(1, z_samples);
3401 } else {
3402 z_samples = coverage_samples;
3403 }
3404 } else if (sctx->smoothing_enabled) {
3405 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3406 } else {
3407 coverage_samples = color_samples = z_samples = 1;
3408 }
3409
3410 /* Required by OpenGL line rasterization.
3411 *
3412 * TODO: We should also enable perpendicular endcaps for AA lines,
3413 * but that requires implementing line stippling in the pixel
3414 * shader. SC can only do line stippling with axis-aligned
3415 * endcaps.
3416 */
3417 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3418 unsigned sc_aa_config = 0;
3419
3420 if (coverage_samples > 1) {
3421 /* distance from the pixel center, indexed by log2(nr_samples) */
3422 static unsigned max_dist[] = {
3423 0, /* unused */
3424 4, /* 2x MSAA */
3425 6, /* 4x MSAA */
3426 7, /* 8x MSAA */
3427 8, /* 16x MSAA */
3428 };
3429 unsigned log_samples = util_logbase2(coverage_samples);
3430 unsigned log_z_samples = util_logbase2(z_samples);
3431 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3432 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3433
3434 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3435 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3436 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3437 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3438
3439 if (sctx->framebuffer.nr_samples > 1) {
3440 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3441 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3442 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3443 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3444 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3445 } else if (sctx->smoothing_enabled) {
3446 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3447 }
3448 }
3449
3450 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3451 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3452 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3453 sc_aa_config);
3454 /* R_028804_DB_EQAA */
3455 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3456 db_eqaa);
3457 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3458 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3459 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3460
3461 /* GFX9: Flush DFSM when the AA mode changes. */
3462 if (sctx->screen->dfsm_allowed) {
3463 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3464 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3465 }
3466 }
3467
3468 void si_update_ps_iter_samples(struct si_context *sctx)
3469 {
3470 if (sctx->framebuffer.nr_samples > 1)
3471 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3472 if (sctx->screen->dpbb_allowed)
3473 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3474 }
3475
3476 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3477 {
3478 struct si_context *sctx = (struct si_context *)ctx;
3479
3480 /* The hardware can only do sample shading with 2^n samples. */
3481 min_samples = util_next_power_of_two(min_samples);
3482
3483 if (sctx->ps_iter_samples == min_samples)
3484 return;
3485
3486 sctx->ps_iter_samples = min_samples;
3487 sctx->do_update_shaders = true;
3488
3489 si_update_ps_iter_samples(sctx);
3490 }
3491
3492 /*
3493 * Samplers
3494 */
3495
3496 /**
3497 * Build the sampler view descriptor for a buffer texture.
3498 * @param state 256-bit descriptor; only the high 128 bits are filled in
3499 */
3500 void
3501 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3502 enum pipe_format format,
3503 unsigned offset, unsigned size,
3504 uint32_t *state)
3505 {
3506 const struct util_format_description *desc;
3507 int first_non_void;
3508 unsigned stride;
3509 unsigned num_records;
3510 unsigned num_format, data_format;
3511
3512 desc = util_format_description(format);
3513 first_non_void = util_format_get_first_non_void_channel(format);
3514 stride = desc->block.bits / 8;
3515 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3516 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3517
3518 num_records = size / stride;
3519 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3520
3521 /* The NUM_RECORDS field has a different meaning depending on the chip,
3522 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3523 *
3524 * SI-CIK:
3525 * - If STRIDE == 0, it's in byte units.
3526 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3527 *
3528 * VI:
3529 * - For SMEM and STRIDE == 0, it's in byte units.
3530 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3531 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3532 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3533 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3534 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3535 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3536 * That way the same descriptor can be used by both SMEM and VMEM.
3537 *
3538 * GFX9:
3539 * - For SMEM and STRIDE == 0, it's in byte units.
3540 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3541 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3542 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3543 */
3544 if (screen->info.chip_class >= GFX9)
3545 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3546 * from STRIDE to bytes. This works around it by setting
3547 * NUM_RECORDS to at least the size of one element, so that
3548 * the first element is readable when IDXEN == 0.
3549 *
3550 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3551 * IDXEN is enforced?
3552 */
3553 num_records = num_records ? MAX2(num_records, stride) : 0;
3554 else if (screen->info.chip_class == VI)
3555 num_records *= stride;
3556
3557 state[4] = 0;
3558 state[5] = S_008F04_STRIDE(stride);
3559 state[6] = num_records;
3560 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3561 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3562 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3563 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3564 S_008F0C_NUM_FORMAT(num_format) |
3565 S_008F0C_DATA_FORMAT(data_format);
3566 }
3567
3568 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3569 {
3570 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3571
3572 if (swizzle[3] == PIPE_SWIZZLE_X) {
3573 /* For the pre-defined border color values (white, opaque
3574 * black, transparent black), the only thing that matters is
3575 * that the alpha channel winds up in the correct place
3576 * (because the RGB channels are all the same) so either of
3577 * these enumerations will work.
3578 */
3579 if (swizzle[2] == PIPE_SWIZZLE_Y)
3580 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3581 else
3582 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3583 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3584 if (swizzle[1] == PIPE_SWIZZLE_Y)
3585 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3586 else
3587 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3588 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3589 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3590 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3591 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3592 }
3593
3594 return bc_swizzle;
3595 }
3596
3597 /**
3598 * Build the sampler view descriptor for a texture.
3599 */
3600 void
3601 si_make_texture_descriptor(struct si_screen *screen,
3602 struct r600_texture *tex,
3603 bool sampler,
3604 enum pipe_texture_target target,
3605 enum pipe_format pipe_format,
3606 const unsigned char state_swizzle[4],
3607 unsigned first_level, unsigned last_level,
3608 unsigned first_layer, unsigned last_layer,
3609 unsigned width, unsigned height, unsigned depth,
3610 uint32_t *state,
3611 uint32_t *fmask_state)
3612 {
3613 struct pipe_resource *res = &tex->buffer.b.b;
3614 const struct util_format_description *desc;
3615 unsigned char swizzle[4];
3616 int first_non_void;
3617 unsigned num_format, data_format, type, num_samples;
3618 uint64_t va;
3619
3620 desc = util_format_description(pipe_format);
3621
3622 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3623 MAX2(1, res->nr_samples) : tex->num_color_samples;
3624
3625 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3626 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3627 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3628 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3629
3630 switch (pipe_format) {
3631 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3632 case PIPE_FORMAT_X32_S8X24_UINT:
3633 case PIPE_FORMAT_X8Z24_UNORM:
3634 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3635 break;
3636 case PIPE_FORMAT_X24S8_UINT:
3637 /*
3638 * X24S8 is implemented as an 8_8_8_8 data format, to
3639 * fix texture gathers. This affects at least
3640 * GL45-CTS.texture_cube_map_array.sampling on VI.
3641 */
3642 if (screen->info.chip_class <= VI)
3643 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3644 else
3645 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3646 break;
3647 default:
3648 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3649 }
3650 } else {
3651 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3652 }
3653
3654 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3655
3656 switch (pipe_format) {
3657 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3658 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3659 break;
3660 default:
3661 if (first_non_void < 0) {
3662 if (util_format_is_compressed(pipe_format)) {
3663 switch (pipe_format) {
3664 case PIPE_FORMAT_DXT1_SRGB:
3665 case PIPE_FORMAT_DXT1_SRGBA:
3666 case PIPE_FORMAT_DXT3_SRGBA:
3667 case PIPE_FORMAT_DXT5_SRGBA:
3668 case PIPE_FORMAT_BPTC_SRGBA:
3669 case PIPE_FORMAT_ETC2_SRGB8:
3670 case PIPE_FORMAT_ETC2_SRGB8A1:
3671 case PIPE_FORMAT_ETC2_SRGBA8:
3672 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3673 break;
3674 case PIPE_FORMAT_RGTC1_SNORM:
3675 case PIPE_FORMAT_LATC1_SNORM:
3676 case PIPE_FORMAT_RGTC2_SNORM:
3677 case PIPE_FORMAT_LATC2_SNORM:
3678 case PIPE_FORMAT_ETC2_R11_SNORM:
3679 case PIPE_FORMAT_ETC2_RG11_SNORM:
3680 /* implies float, so use SNORM/UNORM to determine
3681 whether data is signed or not */
3682 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3683 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3684 break;
3685 default:
3686 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3687 break;
3688 }
3689 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3690 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3691 } else {
3692 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3693 }
3694 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3695 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3696 } else {
3697 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3698
3699 switch (desc->channel[first_non_void].type) {
3700 case UTIL_FORMAT_TYPE_FLOAT:
3701 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3702 break;
3703 case UTIL_FORMAT_TYPE_SIGNED:
3704 if (desc->channel[first_non_void].normalized)
3705 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3706 else if (desc->channel[first_non_void].pure_integer)
3707 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3708 else
3709 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3710 break;
3711 case UTIL_FORMAT_TYPE_UNSIGNED:
3712 if (desc->channel[first_non_void].normalized)
3713 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3714 else if (desc->channel[first_non_void].pure_integer)
3715 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3716 else
3717 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3718 }
3719 }
3720 }
3721
3722 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3723 if (data_format == ~0) {
3724 data_format = 0;
3725 }
3726
3727 /* S8 with Z32 HTILE needs a special format. */
3728 if (screen->info.chip_class >= GFX9 &&
3729 pipe_format == PIPE_FORMAT_S8_UINT &&
3730 tex->tc_compatible_htile)
3731 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3732
3733 if (!sampler &&
3734 (res->target == PIPE_TEXTURE_CUBE ||
3735 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3736 (screen->info.chip_class <= VI &&
3737 res->target == PIPE_TEXTURE_3D))) {
3738 /* For the purpose of shader images, treat cube maps and 3D
3739 * textures as 2D arrays. For 3D textures, the address
3740 * calculations for mipmaps are different, so we rely on the
3741 * caller to effectively disable mipmaps.
3742 */
3743 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3744
3745 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3746 } else {
3747 type = si_tex_dim(screen, tex, target, num_samples);
3748 }
3749
3750 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3751 height = 1;
3752 depth = res->array_size;
3753 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3754 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3755 if (sampler || res->target != PIPE_TEXTURE_3D)
3756 depth = res->array_size;
3757 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3758 depth = res->array_size / 6;
3759
3760 state[0] = 0;
3761 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3762 S_008F14_NUM_FORMAT_GFX6(num_format));
3763 state[2] = (S_008F18_WIDTH(width - 1) |
3764 S_008F18_HEIGHT(height - 1) |
3765 S_008F18_PERF_MOD(4));
3766 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3767 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3768 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3769 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3770 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3771 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3772 util_logbase2(num_samples) :
3773 last_level) |
3774 S_008F1C_TYPE(type));
3775 state[4] = 0;
3776 state[5] = S_008F24_BASE_ARRAY(first_layer);
3777 state[6] = 0;
3778 state[7] = 0;
3779
3780 if (screen->info.chip_class >= GFX9) {
3781 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3782
3783 /* Depth is the the last accessible layer on Gfx9.
3784 * The hw doesn't need to know the total number of layers.
3785 */
3786 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3787 state[4] |= S_008F20_DEPTH(depth - 1);
3788 else
3789 state[4] |= S_008F20_DEPTH(last_layer);
3790
3791 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3792 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3793 util_logbase2(num_samples) :
3794 tex->buffer.b.b.last_level);
3795 } else {
3796 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3797 state[4] |= S_008F20_DEPTH(depth - 1);
3798 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3799 }
3800
3801 if (tex->dcc_offset) {
3802 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3803 } else {
3804 /* The last dword is unused by hw. The shader uses it to clear
3805 * bits in the first dword of sampler state.
3806 */
3807 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3808 if (first_level == last_level)
3809 state[7] = C_008F30_MAX_ANISO_RATIO;
3810 else
3811 state[7] = 0xffffffff;
3812 }
3813 }
3814
3815 /* Initialize the sampler view for FMASK. */
3816 if (tex->surface.fmask_size) {
3817 uint32_t data_format, num_format;
3818
3819 va = tex->buffer.gpu_address + tex->fmask_offset;
3820
3821 #define FMASK(s,f) (((unsigned)(s) * 16) + (f))
3822 if (screen->info.chip_class >= GFX9) {
3823 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3824 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3825 case FMASK(2,1):
3826 num_format = V_008F14_IMG_FMASK_8_2_1;
3827 break;
3828 case FMASK(2,2):
3829 num_format = V_008F14_IMG_FMASK_8_2_2;
3830 break;
3831 case FMASK(4,1):
3832 num_format = V_008F14_IMG_FMASK_8_4_1;
3833 break;
3834 case FMASK(4,2):
3835 num_format = V_008F14_IMG_FMASK_8_4_2;
3836 break;
3837 case FMASK(4,4):
3838 num_format = V_008F14_IMG_FMASK_8_4_4;
3839 break;
3840 case FMASK(8,1):
3841 num_format = V_008F14_IMG_FMASK_8_8_1;
3842 break;
3843 case FMASK(8,2):
3844 num_format = V_008F14_IMG_FMASK_16_8_2;
3845 break;
3846 case FMASK(8,4):
3847 num_format = V_008F14_IMG_FMASK_32_8_4;
3848 break;
3849 case FMASK(8,8):
3850 num_format = V_008F14_IMG_FMASK_32_8_8;
3851 break;
3852 case FMASK(16,1):
3853 num_format = V_008F14_IMG_FMASK_16_16_1;
3854 break;
3855 case FMASK(16,2):
3856 num_format = V_008F14_IMG_FMASK_32_16_2;
3857 break;
3858 case FMASK(16,4):
3859 num_format = V_008F14_IMG_FMASK_64_16_4;
3860 break;
3861 case FMASK(16,8):
3862 num_format = V_008F14_IMG_FMASK_64_16_8;
3863 break;
3864 default:
3865 unreachable("invalid nr_samples");
3866 }
3867 } else {
3868 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3869 case FMASK(2,1):
3870 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3871 break;
3872 case FMASK(2,2):
3873 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3874 break;
3875 case FMASK(4,1):
3876 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3877 break;
3878 case FMASK(4,2):
3879 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3880 break;
3881 case FMASK(4,4):
3882 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3883 break;
3884 case FMASK(8,1):
3885 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3886 break;
3887 case FMASK(8,2):
3888 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3889 break;
3890 case FMASK(8,4):
3891 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3892 break;
3893 case FMASK(8,8):
3894 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3895 break;
3896 case FMASK(16,1):
3897 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3898 break;
3899 case FMASK(16,2):
3900 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3901 break;
3902 case FMASK(16,4):
3903 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3904 break;
3905 case FMASK(16,8):
3906 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3907 break;
3908 default:
3909 unreachable("invalid nr_samples");
3910 }
3911 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3912 }
3913 #undef FMASK
3914
3915 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3916 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3917 S_008F14_DATA_FORMAT_GFX6(data_format) |
3918 S_008F14_NUM_FORMAT_GFX6(num_format);
3919 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3920 S_008F18_HEIGHT(height - 1);
3921 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3922 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3923 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3924 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3925 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3926 fmask_state[4] = 0;
3927 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3928 fmask_state[6] = 0;
3929 fmask_state[7] = 0;
3930
3931 if (screen->info.chip_class >= GFX9) {
3932 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3933 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3934 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3935 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3936 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3937 } else {
3938 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3939 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3940 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3941 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3942 }
3943 }
3944 }
3945
3946 /**
3947 * Create a sampler view.
3948 *
3949 * @param ctx context
3950 * @param texture texture
3951 * @param state sampler view template
3952 * @param width0 width0 override (for compressed textures as int)
3953 * @param height0 height0 override (for compressed textures as int)
3954 * @param force_level set the base address to the level (for compressed textures)
3955 */
3956 struct pipe_sampler_view *
3957 si_create_sampler_view_custom(struct pipe_context *ctx,
3958 struct pipe_resource *texture,
3959 const struct pipe_sampler_view *state,
3960 unsigned width0, unsigned height0,
3961 unsigned force_level)
3962 {
3963 struct si_context *sctx = (struct si_context*)ctx;
3964 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3965 struct r600_texture *tmp = (struct r600_texture*)texture;
3966 unsigned base_level, first_level, last_level;
3967 unsigned char state_swizzle[4];
3968 unsigned height, depth, width;
3969 unsigned last_layer = state->u.tex.last_layer;
3970 enum pipe_format pipe_format;
3971 const struct legacy_surf_level *surflevel;
3972
3973 if (!view)
3974 return NULL;
3975
3976 /* initialize base object */
3977 view->base = *state;
3978 view->base.texture = NULL;
3979 view->base.reference.count = 1;
3980 view->base.context = ctx;
3981
3982 assert(texture);
3983 pipe_resource_reference(&view->base.texture, texture);
3984
3985 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3986 state->format == PIPE_FORMAT_S8X24_UINT ||
3987 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3988 state->format == PIPE_FORMAT_S8_UINT)
3989 view->is_stencil_sampler = true;
3990
3991 /* Buffer resource. */
3992 if (texture->target == PIPE_BUFFER) {
3993 si_make_buffer_descriptor(sctx->screen,
3994 r600_resource(texture),
3995 state->format,
3996 state->u.buf.offset,
3997 state->u.buf.size,
3998 view->state);
3999 return &view->base;
4000 }
4001
4002 state_swizzle[0] = state->swizzle_r;
4003 state_swizzle[1] = state->swizzle_g;
4004 state_swizzle[2] = state->swizzle_b;
4005 state_swizzle[3] = state->swizzle_a;
4006
4007 base_level = 0;
4008 first_level = state->u.tex.first_level;
4009 last_level = state->u.tex.last_level;
4010 width = width0;
4011 height = height0;
4012 depth = texture->depth0;
4013
4014 if (sctx->chip_class <= VI && force_level) {
4015 assert(force_level == first_level &&
4016 force_level == last_level);
4017 base_level = force_level;
4018 first_level = 0;
4019 last_level = 0;
4020 width = u_minify(width, force_level);
4021 height = u_minify(height, force_level);
4022 depth = u_minify(depth, force_level);
4023 }
4024
4025 /* This is not needed if state trackers set last_layer correctly. */
4026 if (state->target == PIPE_TEXTURE_1D ||
4027 state->target == PIPE_TEXTURE_2D ||
4028 state->target == PIPE_TEXTURE_RECT ||
4029 state->target == PIPE_TEXTURE_CUBE)
4030 last_layer = state->u.tex.first_layer;
4031
4032 /* Texturing with separate depth and stencil. */
4033 pipe_format = state->format;
4034
4035 /* Depth/stencil texturing sometimes needs separate texture. */
4036 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
4037 if (!tmp->flushed_depth_texture &&
4038 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4039 pipe_resource_reference(&view->base.texture, NULL);
4040 FREE(view);
4041 return NULL;
4042 }
4043
4044 assert(tmp->flushed_depth_texture);
4045
4046 /* Override format for the case where the flushed texture
4047 * contains only Z or only S.
4048 */
4049 if (tmp->flushed_depth_texture->buffer.b.b.format != tmp->buffer.b.b.format)
4050 pipe_format = tmp->flushed_depth_texture->buffer.b.b.format;
4051
4052 tmp = tmp->flushed_depth_texture;
4053 }
4054
4055 surflevel = tmp->surface.u.legacy.level;
4056
4057 if (tmp->db_compatible) {
4058 if (!view->is_stencil_sampler)
4059 pipe_format = tmp->db_render_format;
4060
4061 switch (pipe_format) {
4062 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4063 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4064 break;
4065 case PIPE_FORMAT_X8Z24_UNORM:
4066 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4067 /* Z24 is always stored like this for DB
4068 * compatibility.
4069 */
4070 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4071 break;
4072 case PIPE_FORMAT_X24S8_UINT:
4073 case PIPE_FORMAT_S8X24_UINT:
4074 case PIPE_FORMAT_X32_S8X24_UINT:
4075 pipe_format = PIPE_FORMAT_S8_UINT;
4076 surflevel = tmp->surface.u.legacy.stencil_level;
4077 break;
4078 default:;
4079 }
4080 }
4081
4082 view->dcc_incompatible =
4083 vi_dcc_formats_are_incompatible(texture,
4084 state->u.tex.first_level,
4085 state->format);
4086
4087 si_make_texture_descriptor(sctx->screen, tmp, true,
4088 state->target, pipe_format, state_swizzle,
4089 first_level, last_level,
4090 state->u.tex.first_layer, last_layer,
4091 width, height, depth,
4092 view->state, view->fmask_state);
4093
4094 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4095 view->is_integer =
4096 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4097 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4098 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4099 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4100 view->base_level_info = &surflevel[base_level];
4101 view->base_level = base_level;
4102 view->block_width = util_format_get_blockwidth(pipe_format);
4103 return &view->base;
4104 }
4105
4106 static struct pipe_sampler_view *
4107 si_create_sampler_view(struct pipe_context *ctx,
4108 struct pipe_resource *texture,
4109 const struct pipe_sampler_view *state)
4110 {
4111 return si_create_sampler_view_custom(ctx, texture, state,
4112 texture ? texture->width0 : 0,
4113 texture ? texture->height0 : 0, 0);
4114 }
4115
4116 static void si_sampler_view_destroy(struct pipe_context *ctx,
4117 struct pipe_sampler_view *state)
4118 {
4119 struct si_sampler_view *view = (struct si_sampler_view *)state;
4120
4121 pipe_resource_reference(&state->texture, NULL);
4122 FREE(view);
4123 }
4124
4125 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4126 {
4127 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4128 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4129 (linear_filter &&
4130 (wrap == PIPE_TEX_WRAP_CLAMP ||
4131 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4132 }
4133
4134 static uint32_t si_translate_border_color(struct si_context *sctx,
4135 const struct pipe_sampler_state *state,
4136 const union pipe_color_union *color,
4137 bool is_integer)
4138 {
4139 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4140 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4141
4142 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4143 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4144 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4145 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4146
4147 #define simple_border_types(elt) \
4148 do { \
4149 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4150 color->elt[2] == 0 && color->elt[3] == 0) \
4151 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4152 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4153 color->elt[2] == 0 && color->elt[3] == 1) \
4154 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4155 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4156 color->elt[2] == 1 && color->elt[3] == 1) \
4157 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4158 } while (false)
4159
4160 if (is_integer)
4161 simple_border_types(ui);
4162 else
4163 simple_border_types(f);
4164
4165 #undef simple_border_types
4166
4167 int i;
4168
4169 /* Check if the border has been uploaded already. */
4170 for (i = 0; i < sctx->border_color_count; i++)
4171 if (memcmp(&sctx->border_color_table[i], color,
4172 sizeof(*color)) == 0)
4173 break;
4174
4175 if (i >= SI_MAX_BORDER_COLORS) {
4176 /* Getting 4096 unique border colors is very unlikely. */
4177 fprintf(stderr, "radeonsi: The border color table is full. "
4178 "Any new border colors will be just black. "
4179 "Please file a bug.\n");
4180 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4181 }
4182
4183 if (i == sctx->border_color_count) {
4184 /* Upload a new border color. */
4185 memcpy(&sctx->border_color_table[i], color,
4186 sizeof(*color));
4187 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4188 color, sizeof(*color));
4189 sctx->border_color_count++;
4190 }
4191
4192 return S_008F3C_BORDER_COLOR_PTR(i) |
4193 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4194 }
4195
4196 static inline int S_FIXED(float value, unsigned frac_bits)
4197 {
4198 return value * (1 << frac_bits);
4199 }
4200
4201 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4202 {
4203 if (filter == PIPE_TEX_FILTER_LINEAR)
4204 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4205 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4206 else
4207 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4208 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4209 }
4210
4211 static inline unsigned si_tex_aniso_filter(unsigned filter)
4212 {
4213 if (filter < 2)
4214 return 0;
4215 if (filter < 4)
4216 return 1;
4217 if (filter < 8)
4218 return 2;
4219 if (filter < 16)
4220 return 3;
4221 return 4;
4222 }
4223
4224 static void *si_create_sampler_state(struct pipe_context *ctx,
4225 const struct pipe_sampler_state *state)
4226 {
4227 struct si_context *sctx = (struct si_context *)ctx;
4228 struct si_screen *sscreen = sctx->screen;
4229 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4230 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4231 : state->max_anisotropy;
4232 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4233 union pipe_color_union clamped_border_color;
4234
4235 if (!rstate) {
4236 return NULL;
4237 }
4238
4239 #ifdef DEBUG
4240 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4241 #endif
4242 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4243 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4244 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4245 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4246 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4247 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4248 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4249 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4250 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4251 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4252 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4253 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4254 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4255 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4256 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4257 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4258 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4259 S_008F38_MIP_POINT_PRECLAMP(0) |
4260 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4261 S_008F38_FILTER_PREC_FIX(1) |
4262 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4263 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4264
4265 /* Create sampler resource for integer textures. */
4266 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4267 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4268
4269 /* Create sampler resource for upgraded depth textures. */
4270 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4271
4272 for (unsigned i = 0; i < 4; ++i) {
4273 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4274 * when the border color is 1.0. */
4275 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4276 }
4277
4278 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4279 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4280 else
4281 rstate->upgraded_depth_val[3] =
4282 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4283 S_008F3C_UPGRADED_DEPTH(1);
4284
4285 return rstate;
4286 }
4287
4288 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4289 {
4290 struct si_context *sctx = (struct si_context *)ctx;
4291
4292 if (sctx->sample_mask == (uint16_t)sample_mask)
4293 return;
4294
4295 sctx->sample_mask = sample_mask;
4296 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4297 }
4298
4299 static void si_emit_sample_mask(struct si_context *sctx)
4300 {
4301 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4302 unsigned mask = sctx->sample_mask;
4303
4304 /* Needed for line and polygon smoothing as well as for the Polaris
4305 * small primitive filter. We expect the state tracker to take care of
4306 * this for us.
4307 */
4308 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4309 (mask & 1 && sctx->blitter->running));
4310
4311 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4312 radeon_emit(cs, mask | (mask << 16));
4313 radeon_emit(cs, mask | (mask << 16));
4314 }
4315
4316 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4317 {
4318 #ifdef DEBUG
4319 struct si_sampler_state *s = state;
4320
4321 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4322 s->magic = 0;
4323 #endif
4324 free(state);
4325 }
4326
4327 /*
4328 * Vertex elements & buffers
4329 */
4330
4331 static void *si_create_vertex_elements(struct pipe_context *ctx,
4332 unsigned count,
4333 const struct pipe_vertex_element *elements)
4334 {
4335 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4336 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4337 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4338 int i;
4339
4340 assert(count <= SI_MAX_ATTRIBS);
4341 if (!v)
4342 return NULL;
4343
4344 v->count = count;
4345 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4346
4347 for (i = 0; i < count; ++i) {
4348 const struct util_format_description *desc;
4349 const struct util_format_channel_description *channel;
4350 unsigned data_format, num_format;
4351 int first_non_void;
4352 unsigned vbo_index = elements[i].vertex_buffer_index;
4353 unsigned char swizzle[4];
4354
4355 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4356 FREE(v);
4357 return NULL;
4358 }
4359
4360 if (elements[i].instance_divisor) {
4361 v->uses_instance_divisors = true;
4362 v->instance_divisors[i] = elements[i].instance_divisor;
4363
4364 if (v->instance_divisors[i] == 1)
4365 v->instance_divisor_is_one |= 1u << i;
4366 else
4367 v->instance_divisor_is_fetched |= 1u << i;
4368 }
4369
4370 if (!used[vbo_index]) {
4371 v->first_vb_use_mask |= 1 << i;
4372 used[vbo_index] = true;
4373 }
4374
4375 desc = util_format_description(elements[i].src_format);
4376 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4377 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4378 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4379 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4380 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4381
4382 v->format_size[i] = desc->block.bits / 8;
4383 v->src_offset[i] = elements[i].src_offset;
4384 v->vertex_buffer_index[i] = vbo_index;
4385
4386 /* The hardware always treats the 2-bit alpha channel as
4387 * unsigned, so a shader workaround is needed. The affected
4388 * chips are VI and older except Stoney (GFX8.1).
4389 */
4390 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4391 sscreen->info.chip_class <= VI &&
4392 sscreen->info.family != CHIP_STONEY) {
4393 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4394 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4395 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4396 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4397 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4398 /* This isn't actually used in OpenGL. */
4399 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4400 }
4401 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4402 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4403 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4404 else
4405 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4406 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4407 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4408 if (channel->normalized) {
4409 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4410 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4411 else
4412 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4413 } else {
4414 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4415 }
4416 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4417 if (channel->normalized) {
4418 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4419 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4420 else
4421 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4422 } else {
4423 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4424 }
4425 }
4426 } else if (channel && channel->size == 64 &&
4427 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4428 switch (desc->nr_channels) {
4429 case 1:
4430 case 2:
4431 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4432 swizzle[0] = PIPE_SWIZZLE_X;
4433 swizzle[1] = PIPE_SWIZZLE_Y;
4434 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4435 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4436 break;
4437 case 3:
4438 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4439 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4440 swizzle[1] = PIPE_SWIZZLE_Y;
4441 swizzle[2] = PIPE_SWIZZLE_0;
4442 swizzle[3] = PIPE_SWIZZLE_0;
4443 break;
4444 case 4:
4445 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4446 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4447 swizzle[1] = PIPE_SWIZZLE_Y;
4448 swizzle[2] = PIPE_SWIZZLE_Z;
4449 swizzle[3] = PIPE_SWIZZLE_W;
4450 break;
4451 default:
4452 assert(0);
4453 }
4454 } else if (channel && desc->nr_channels == 3) {
4455 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4456
4457 if (channel->size == 8) {
4458 if (channel->pure_integer)
4459 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4460 else
4461 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4462 } else if (channel->size == 16) {
4463 if (channel->pure_integer)
4464 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4465 else
4466 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4467 }
4468 }
4469
4470 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4471 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4472 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4473 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4474 S_008F0C_NUM_FORMAT(num_format) |
4475 S_008F0C_DATA_FORMAT(data_format);
4476 }
4477 return v;
4478 }
4479
4480 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4481 {
4482 struct si_context *sctx = (struct si_context *)ctx;
4483 struct si_vertex_elements *old = sctx->vertex_elements;
4484 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4485
4486 sctx->vertex_elements = v;
4487 sctx->vertex_buffers_dirty = true;
4488
4489 if (v &&
4490 (!old ||
4491 old->count != v->count ||
4492 old->uses_instance_divisors != v->uses_instance_divisors ||
4493 v->uses_instance_divisors || /* we don't check which divisors changed */
4494 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4495 sctx->do_update_shaders = true;
4496
4497 if (v && v->instance_divisor_is_fetched) {
4498 struct pipe_constant_buffer cb;
4499
4500 cb.buffer = NULL;
4501 cb.user_buffer = v->instance_divisors;
4502 cb.buffer_offset = 0;
4503 cb.buffer_size = sizeof(uint32_t) * v->count;
4504 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4505 }
4506 }
4507
4508 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4509 {
4510 struct si_context *sctx = (struct si_context *)ctx;
4511
4512 if (sctx->vertex_elements == state)
4513 sctx->vertex_elements = NULL;
4514 FREE(state);
4515 }
4516
4517 static void si_set_vertex_buffers(struct pipe_context *ctx,
4518 unsigned start_slot, unsigned count,
4519 const struct pipe_vertex_buffer *buffers)
4520 {
4521 struct si_context *sctx = (struct si_context *)ctx;
4522 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4523 int i;
4524
4525 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4526
4527 if (buffers) {
4528 for (i = 0; i < count; i++) {
4529 const struct pipe_vertex_buffer *src = buffers + i;
4530 struct pipe_vertex_buffer *dsti = dst + i;
4531 struct pipe_resource *buf = src->buffer.resource;
4532
4533 pipe_resource_reference(&dsti->buffer.resource, buf);
4534 dsti->buffer_offset = src->buffer_offset;
4535 dsti->stride = src->stride;
4536 si_context_add_resource_size(sctx, buf);
4537 if (buf)
4538 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4539 }
4540 } else {
4541 for (i = 0; i < count; i++) {
4542 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4543 }
4544 }
4545 sctx->vertex_buffers_dirty = true;
4546 }
4547
4548 /*
4549 * Misc
4550 */
4551
4552 static void si_set_tess_state(struct pipe_context *ctx,
4553 const float default_outer_level[4],
4554 const float default_inner_level[2])
4555 {
4556 struct si_context *sctx = (struct si_context *)ctx;
4557 struct pipe_constant_buffer cb;
4558 float array[8];
4559
4560 memcpy(array, default_outer_level, sizeof(float) * 4);
4561 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4562
4563 cb.buffer = NULL;
4564 cb.user_buffer = NULL;
4565 cb.buffer_size = sizeof(array);
4566
4567 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4568 (void*)array, sizeof(array),
4569 &cb.buffer_offset);
4570
4571 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4572 pipe_resource_reference(&cb.buffer, NULL);
4573 }
4574
4575 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4576 {
4577 struct si_context *sctx = (struct si_context *)ctx;
4578
4579 si_update_fb_dirtiness_after_rendering(sctx);
4580
4581 /* Multisample surfaces are flushed in si_decompress_textures. */
4582 if (sctx->framebuffer.uncompressed_cb_mask)
4583 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4584 sctx->framebuffer.CB_has_shader_readable_metadata);
4585 }
4586
4587 /* This only ensures coherency for shader image/buffer stores. */
4588 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4589 {
4590 struct si_context *sctx = (struct si_context *)ctx;
4591
4592 /* Subsequent commands must wait for all shader invocations to
4593 * complete. */
4594 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4595 SI_CONTEXT_CS_PARTIAL_FLUSH;
4596
4597 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4598 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4599 SI_CONTEXT_INV_VMEM_L1;
4600
4601 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4602 PIPE_BARRIER_SHADER_BUFFER |
4603 PIPE_BARRIER_TEXTURE |
4604 PIPE_BARRIER_IMAGE |
4605 PIPE_BARRIER_STREAMOUT_BUFFER |
4606 PIPE_BARRIER_GLOBAL_BUFFER)) {
4607 /* As far as I can tell, L1 contents are written back to L2
4608 * automatically at end of shader, but the contents of other
4609 * L1 caches might still be stale. */
4610 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4611 }
4612
4613 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4614 /* Indices are read through TC L2 since VI.
4615 * L1 isn't used.
4616 */
4617 if (sctx->screen->info.chip_class <= CIK)
4618 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4619 }
4620
4621 /* MSAA color, any depth and any stencil are flushed in
4622 * si_decompress_textures when needed.
4623 */
4624 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4625 sctx->framebuffer.uncompressed_cb_mask) {
4626 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4627
4628 if (sctx->chip_class <= VI)
4629 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4630 }
4631
4632 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4633 if (sctx->screen->info.chip_class <= VI &&
4634 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4635 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4636 }
4637
4638 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4639 {
4640 struct pipe_blend_state blend;
4641
4642 memset(&blend, 0, sizeof(blend));
4643 blend.independent_blend_enable = true;
4644 blend.rt[0].colormask = 0xf;
4645 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4646 }
4647
4648 static void si_init_config(struct si_context *sctx);
4649
4650 void si_init_state_functions(struct si_context *sctx)
4651 {
4652 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4653 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4654 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4655 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4656 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4657 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4658 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4659 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4660 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4661 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4662 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4663
4664 sctx->b.create_blend_state = si_create_blend_state;
4665 sctx->b.bind_blend_state = si_bind_blend_state;
4666 sctx->b.delete_blend_state = si_delete_blend_state;
4667 sctx->b.set_blend_color = si_set_blend_color;
4668
4669 sctx->b.create_rasterizer_state = si_create_rs_state;
4670 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4671 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4672
4673 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4674 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4675 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4676
4677 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4678 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4679 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4680 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4681 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4682
4683 sctx->b.set_clip_state = si_set_clip_state;
4684 sctx->b.set_stencil_ref = si_set_stencil_ref;
4685
4686 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4687
4688 sctx->b.create_sampler_state = si_create_sampler_state;
4689 sctx->b.delete_sampler_state = si_delete_sampler_state;
4690
4691 sctx->b.create_sampler_view = si_create_sampler_view;
4692 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4693
4694 sctx->b.set_sample_mask = si_set_sample_mask;
4695
4696 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4697 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4698 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4699 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4700
4701 sctx->b.texture_barrier = si_texture_barrier;
4702 sctx->b.memory_barrier = si_memory_barrier;
4703 sctx->b.set_min_samples = si_set_min_samples;
4704 sctx->b.set_tess_state = si_set_tess_state;
4705
4706 sctx->b.set_active_query_state = si_set_active_query_state;
4707
4708 sctx->b.draw_vbo = si_draw_vbo;
4709
4710 si_init_config(sctx);
4711 }
4712
4713 void si_init_screen_state_functions(struct si_screen *sscreen)
4714 {
4715 sscreen->b.is_format_supported = si_is_format_supported;
4716 }
4717
4718 static void si_set_grbm_gfx_index(struct si_context *sctx,
4719 struct si_pm4_state *pm4, unsigned value)
4720 {
4721 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4722 R_00802C_GRBM_GFX_INDEX;
4723 si_pm4_set_reg(pm4, reg, value);
4724 }
4725
4726 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4727 struct si_pm4_state *pm4, unsigned se)
4728 {
4729 assert(se == ~0 || se < sctx->screen->info.max_se);
4730 si_set_grbm_gfx_index(sctx, pm4,
4731 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4732 S_030800_SE_INDEX(se)) |
4733 S_030800_SH_BROADCAST_WRITES(1) |
4734 S_030800_INSTANCE_BROADCAST_WRITES(1));
4735 }
4736
4737 static void
4738 si_write_harvested_raster_configs(struct si_context *sctx,
4739 struct si_pm4_state *pm4,
4740 unsigned raster_config,
4741 unsigned raster_config_1)
4742 {
4743 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4744 unsigned raster_config_se[4];
4745 unsigned se;
4746
4747 ac_get_harvested_configs(&sctx->screen->info,
4748 raster_config,
4749 &raster_config_1,
4750 raster_config_se);
4751
4752 for (se = 0; se < num_se; se++) {
4753 si_set_grbm_gfx_index_se(sctx, pm4, se);
4754 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4755 }
4756 si_set_grbm_gfx_index(sctx, pm4, ~0);
4757
4758 if (sctx->chip_class >= CIK) {
4759 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4760 }
4761 }
4762
4763 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4764 {
4765 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4766 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4767 unsigned raster_config, raster_config_1;
4768
4769 ac_get_raster_config(&sctx->screen->info,
4770 &raster_config,
4771 &raster_config_1);
4772
4773 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4774 /* Always use the default config when all backends are enabled
4775 * (or when we failed to determine the enabled backends).
4776 */
4777 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4778 raster_config);
4779 if (sctx->chip_class >= CIK)
4780 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4781 raster_config_1);
4782 } else {
4783 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4784 }
4785 }
4786
4787 static void si_init_config(struct si_context *sctx)
4788 {
4789 struct si_screen *sscreen = sctx->screen;
4790 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4791 bool has_clear_state = sscreen->has_clear_state;
4792 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4793
4794 /* Only SI can disable CLEAR_STATE for now. */
4795 assert(has_clear_state || sscreen->info.chip_class == SI);
4796
4797 if (!pm4)
4798 return;
4799
4800 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4801 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4802 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4803 si_pm4_cmd_end(pm4, false);
4804
4805 if (has_clear_state) {
4806 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4807 si_pm4_cmd_add(pm4, 0);
4808 si_pm4_cmd_end(pm4, false);
4809 }
4810
4811 if (sctx->chip_class <= VI)
4812 si_set_raster_config(sctx, pm4);
4813
4814 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4815 if (!has_clear_state)
4816 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4817
4818 /* FIXME calculate these values somehow ??? */
4819 if (sctx->chip_class <= VI) {
4820 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4821 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4822 }
4823
4824 if (!has_clear_state) {
4825 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4826 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4827 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4828 }
4829
4830 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4831 if (!has_clear_state)
4832 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4833 if (sctx->chip_class < CIK)
4834 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4835 S_008A14_CLIP_VTX_REORDER_ENA(1));
4836
4837 if (!has_clear_state)
4838 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4839
4840 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4841 * I don't know why. Deduced by trial and error.
4842 */
4843 if (sctx->chip_class <= CIK) {
4844 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4845 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4846 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4847 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4848 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4849 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4850 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4851 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4852 }
4853
4854 if (!has_clear_state) {
4855 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4856 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4857 S_028230_ER_TRI(0xA) |
4858 S_028230_ER_POINT(0xA) |
4859 S_028230_ER_RECT(0xA) |
4860 /* Required by DX10_DIAMOND_TEST_ENA: */
4861 S_028230_ER_LINE_LR(0x1A) |
4862 S_028230_ER_LINE_RL(0x26) |
4863 S_028230_ER_LINE_TB(0xA) |
4864 S_028230_ER_LINE_BT(0xA));
4865 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4866 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4867 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4868 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4869 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4870 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4871 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4872 }
4873
4874 if (sctx->chip_class >= GFX9) {
4875 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4876 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4877 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4878 } else {
4879 /* These registers, when written, also overwrite the CLEAR_STATE
4880 * context, so we can't rely on CLEAR_STATE setting them.
4881 * It would be an issue if there was another UMD changing them.
4882 */
4883 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4884 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4885 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4886 }
4887
4888 if (sctx->chip_class >= CIK) {
4889 if (sctx->chip_class >= GFX9) {
4890 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4891 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4892 } else {
4893 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4894 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4895 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4896 S_00B41C_WAVE_LIMIT(0x3F));
4897 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4898 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4899
4900 /* If this is 0, Bonaire can hang even if GS isn't being used.
4901 * Other chips are unaffected. These are suboptimal values,
4902 * but we don't use on-chip GS.
4903 */
4904 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4905 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4906 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4907 }
4908 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4909 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4910
4911 /* Compute LATE_ALLOC_VS.LIMIT. */
4912 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4913 (sscreen->info.max_se *
4914 sscreen->info.max_sh_per_se);
4915 unsigned late_alloc_limit; /* The limit is per SH. */
4916
4917 if (sctx->family == CHIP_KABINI) {
4918 late_alloc_limit = 0; /* Potential hang on Kabini. */
4919 } else if (num_cu_per_sh <= 4) {
4920 /* Too few available compute units per SH. Disallowing
4921 * VS to run on one CU could hurt us more than late VS
4922 * allocation would help.
4923 *
4924 * 2 is the highest safe number that allows us to keep
4925 * all CUs enabled.
4926 */
4927 late_alloc_limit = 2;
4928 } else {
4929 /* This is a good initial value, allowing 1 late_alloc
4930 * wave per SIMD on num_cu - 2.
4931 */
4932 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4933
4934 /* The limit is 0-based, so 0 means 1. */
4935 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4936 late_alloc_limit -= 1;
4937 }
4938
4939 /* VS can't execute on one CU if the limit is > 2. */
4940 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4941 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4942 S_00B118_WAVE_LIMIT(0x3F));
4943 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4944 S_00B11C_LIMIT(late_alloc_limit));
4945 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4946 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4947 }
4948
4949 if (sctx->chip_class >= VI) {
4950 unsigned vgt_tess_distribution;
4951
4952 vgt_tess_distribution =
4953 S_028B50_ACCUM_ISOLINE(32) |
4954 S_028B50_ACCUM_TRI(11) |
4955 S_028B50_ACCUM_QUAD(11) |
4956 S_028B50_DONUT_SPLIT(16);
4957
4958 /* Testing with Unigine Heaven extreme tesselation yielded best results
4959 * with TRAP_SPLIT = 3.
4960 */
4961 if (sctx->family == CHIP_FIJI ||
4962 sctx->family >= CHIP_POLARIS10)
4963 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4964
4965 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4966 } else if (!has_clear_state) {
4967 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4968 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4969 }
4970
4971 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4972 if (sctx->chip_class >= CIK) {
4973 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4974 S_028084_ADDRESS(border_color_va >> 40));
4975 }
4976 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4977 RADEON_PRIO_BORDER_COLORS);
4978
4979 if (sctx->chip_class >= GFX9) {
4980 unsigned num_se = sscreen->info.max_se;
4981 unsigned pc_lines = 0;
4982
4983 switch (sctx->family) {
4984 case CHIP_VEGA10:
4985 case CHIP_VEGA12:
4986 pc_lines = 4096;
4987 break;
4988 case CHIP_RAVEN:
4989 pc_lines = 1024;
4990 break;
4991 default:
4992 assert(0);
4993 }
4994
4995 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4996 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4997 S_028C48_MAX_PRIM_PER_BATCH(1023));
4998 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4999 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5000 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5001 }
5002
5003 si_pm4_upload_indirect_buffer(sctx, pm4);
5004 sctx->init_config = pm4;
5005 }