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radeonsi: implement uncompressed MSAA rendering and color resolving
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_format_s3tc.h"
35 #include "tgsi/tgsi_parse.h"
36 #include "radeonsi_pipe.h"
37 #include "radeonsi_shader.h"
38 #include "si_state.h"
39 #include "sid.h"
40
41 static uint32_t cik_num_banks(uint32_t nbanks)
42 {
43 switch (nbanks) {
44 case 2:
45 return V_02803C_ADDR_SURF_2_BANK;
46 case 4:
47 return V_02803C_ADDR_SURF_4_BANK;
48 case 8:
49 default:
50 return V_02803C_ADDR_SURF_8_BANK;
51 case 16:
52 return V_02803C_ADDR_SURF_16_BANK;
53 }
54 }
55
56
57 static unsigned cik_tile_split(unsigned tile_split)
58 {
59 switch (tile_split) {
60 case 64:
61 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
62 break;
63 case 128:
64 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
65 break;
66 case 256:
67 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
68 break;
69 case 512:
70 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
71 break;
72 default:
73 case 1024:
74 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
75 break;
76 case 2048:
77 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
78 break;
79 case 4096:
80 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
81 break;
82 }
83 return tile_split;
84 }
85
86 static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
87 {
88 switch (macro_tile_aspect) {
89 default:
90 case 1:
91 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
92 break;
93 case 2:
94 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
95 break;
96 case 4:
97 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
98 break;
99 case 8:
100 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
101 break;
102 }
103 return macro_tile_aspect;
104 }
105
106 static unsigned cik_bank_wh(unsigned bankwh)
107 {
108 switch (bankwh) {
109 default:
110 case 1:
111 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
112 break;
113 case 2:
114 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
115 break;
116 case 4:
117 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
118 break;
119 case 8:
120 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
121 break;
122 }
123 return bankwh;
124 }
125
126 static unsigned cik_db_pipe_config(unsigned tile_pipes,
127 unsigned num_rbs)
128 {
129 unsigned pipe_config;
130
131 switch (tile_pipes) {
132 case 8:
133 pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
134 break;
135 case 4:
136 default:
137 if (num_rbs == 4)
138 pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
139 else
140 pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
141 break;
142 case 2:
143 pipe_config = V_02803C_ADDR_SURF_P2;
144 break;
145 }
146 return pipe_config;
147 }
148
149 /*
150 * inferred framebuffer and blender state
151 */
152 static void si_update_fb_blend_state(struct r600_context *rctx)
153 {
154 struct si_pm4_state *pm4;
155 struct si_state_blend *blend = rctx->queued.named.blend;
156 uint32_t mask;
157
158 if (blend == NULL)
159 return;
160
161 pm4 = si_pm4_alloc_state(rctx);
162 if (pm4 == NULL)
163 return;
164
165 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
166 mask &= blend->cb_target_mask;
167 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
168
169 si_pm4_set_state(rctx, fb_blend, pm4);
170 }
171
172 /*
173 * Blender functions
174 */
175
176 static uint32_t si_translate_blend_function(int blend_func)
177 {
178 switch (blend_func) {
179 case PIPE_BLEND_ADD:
180 return V_028780_COMB_DST_PLUS_SRC;
181 case PIPE_BLEND_SUBTRACT:
182 return V_028780_COMB_SRC_MINUS_DST;
183 case PIPE_BLEND_REVERSE_SUBTRACT:
184 return V_028780_COMB_DST_MINUS_SRC;
185 case PIPE_BLEND_MIN:
186 return V_028780_COMB_MIN_DST_SRC;
187 case PIPE_BLEND_MAX:
188 return V_028780_COMB_MAX_DST_SRC;
189 default:
190 R600_ERR("Unknown blend function %d\n", blend_func);
191 assert(0);
192 break;
193 }
194 return 0;
195 }
196
197 static uint32_t si_translate_blend_factor(int blend_fact)
198 {
199 switch (blend_fact) {
200 case PIPE_BLENDFACTOR_ONE:
201 return V_028780_BLEND_ONE;
202 case PIPE_BLENDFACTOR_SRC_COLOR:
203 return V_028780_BLEND_SRC_COLOR;
204 case PIPE_BLENDFACTOR_SRC_ALPHA:
205 return V_028780_BLEND_SRC_ALPHA;
206 case PIPE_BLENDFACTOR_DST_ALPHA:
207 return V_028780_BLEND_DST_ALPHA;
208 case PIPE_BLENDFACTOR_DST_COLOR:
209 return V_028780_BLEND_DST_COLOR;
210 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
211 return V_028780_BLEND_SRC_ALPHA_SATURATE;
212 case PIPE_BLENDFACTOR_CONST_COLOR:
213 return V_028780_BLEND_CONSTANT_COLOR;
214 case PIPE_BLENDFACTOR_CONST_ALPHA:
215 return V_028780_BLEND_CONSTANT_ALPHA;
216 case PIPE_BLENDFACTOR_ZERO:
217 return V_028780_BLEND_ZERO;
218 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
219 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
220 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
221 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
222 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
223 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
224 case PIPE_BLENDFACTOR_INV_DST_COLOR:
225 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
226 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
227 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
228 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
229 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
230 case PIPE_BLENDFACTOR_SRC1_COLOR:
231 return V_028780_BLEND_SRC1_COLOR;
232 case PIPE_BLENDFACTOR_SRC1_ALPHA:
233 return V_028780_BLEND_SRC1_ALPHA;
234 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
235 return V_028780_BLEND_INV_SRC1_COLOR;
236 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
237 return V_028780_BLEND_INV_SRC1_ALPHA;
238 default:
239 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
240 assert(0);
241 break;
242 }
243 return 0;
244 }
245
246 static void *si_create_blend_state_mode(struct pipe_context *ctx,
247 const struct pipe_blend_state *state,
248 unsigned mode)
249 {
250 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
251 struct si_pm4_state *pm4 = &blend->pm4;
252
253 uint32_t color_control;
254
255 if (blend == NULL)
256 return NULL;
257
258 color_control = S_028808_MODE(mode);
259 if (state->logicop_enable) {
260 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
261 } else {
262 color_control |= S_028808_ROP3(0xcc);
263 }
264 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
265
266 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
267 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
268 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
269 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
270 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
271 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
272
273 blend->cb_target_mask = 0;
274 for (int i = 0; i < 8; i++) {
275 /* state->rt entries > 0 only written if independent blending */
276 const int j = state->independent_blend_enable ? i : 0;
277
278 unsigned eqRGB = state->rt[j].rgb_func;
279 unsigned srcRGB = state->rt[j].rgb_src_factor;
280 unsigned dstRGB = state->rt[j].rgb_dst_factor;
281 unsigned eqA = state->rt[j].alpha_func;
282 unsigned srcA = state->rt[j].alpha_src_factor;
283 unsigned dstA = state->rt[j].alpha_dst_factor;
284
285 unsigned blend_cntl = 0;
286
287 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
288 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
289
290 if (!state->rt[j].blend_enable) {
291 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
292 continue;
293 }
294
295 blend_cntl |= S_028780_ENABLE(1);
296 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
297 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
298 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
299
300 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
301 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
302 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
303 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
304 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
305 }
306 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
307 }
308
309 return blend;
310 }
311
312 static void *si_create_blend_state(struct pipe_context *ctx,
313 const struct pipe_blend_state *state)
314 {
315 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
316 }
317
318 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
319 {
320 struct r600_context *rctx = (struct r600_context *)ctx;
321 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
322 si_update_fb_blend_state(rctx);
323 }
324
325 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
326 {
327 struct r600_context *rctx = (struct r600_context *)ctx;
328 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
329 }
330
331 static void si_set_blend_color(struct pipe_context *ctx,
332 const struct pipe_blend_color *state)
333 {
334 struct r600_context *rctx = (struct r600_context *)ctx;
335 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
336
337 if (pm4 == NULL)
338 return;
339
340 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
341 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
342 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
343 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
344
345 si_pm4_set_state(rctx, blend_color, pm4);
346 }
347
348 /*
349 * Clipping, scissors and viewport
350 */
351
352 static void si_set_clip_state(struct pipe_context *ctx,
353 const struct pipe_clip_state *state)
354 {
355 struct r600_context *rctx = (struct r600_context *)ctx;
356 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
357 struct pipe_constant_buffer cb;
358
359 if (pm4 == NULL)
360 return;
361
362 for (int i = 0; i < 6; i++) {
363 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
364 fui(state->ucp[i][0]));
365 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
366 fui(state->ucp[i][1]));
367 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
368 fui(state->ucp[i][2]));
369 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
370 fui(state->ucp[i][3]));
371 }
372
373 cb.buffer = NULL;
374 cb.user_buffer = state->ucp;
375 cb.buffer_offset = 0;
376 cb.buffer_size = 4*4*8;
377 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
378 pipe_resource_reference(&cb.buffer, NULL);
379
380 si_pm4_set_state(rctx, clip, pm4);
381 }
382
383 static void si_set_scissor_states(struct pipe_context *ctx,
384 unsigned start_slot,
385 unsigned num_scissors,
386 const struct pipe_scissor_state *state)
387 {
388 struct r600_context *rctx = (struct r600_context *)ctx;
389 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
390 uint32_t tl, br;
391
392 if (pm4 == NULL)
393 return;
394
395 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
396 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
397 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
398 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
399 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
400 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
401 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
402 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
403 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
404 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
405
406 si_pm4_set_state(rctx, scissor, pm4);
407 }
408
409 static void si_set_viewport_states(struct pipe_context *ctx,
410 unsigned start_slot,
411 unsigned num_viewports,
412 const struct pipe_viewport_state *state)
413 {
414 struct r600_context *rctx = (struct r600_context *)ctx;
415 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
416 struct si_pm4_state *pm4 = &viewport->pm4;
417
418 if (viewport == NULL)
419 return;
420
421 viewport->viewport = *state;
422 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
423 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
424 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
425 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
426 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
427 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
428 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
429 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
430 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
431
432 si_pm4_set_state(rctx, viewport, viewport);
433 }
434
435 /*
436 * inferred state between framebuffer and rasterizer
437 */
438 static void si_update_fb_rs_state(struct r600_context *rctx)
439 {
440 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
441 struct si_pm4_state *pm4;
442 unsigned offset_db_fmt_cntl = 0, depth;
443 float offset_units;
444
445 if (!rs || !rctx->framebuffer.zsbuf)
446 return;
447
448 offset_units = rctx->queued.named.rasterizer->offset_units;
449 switch (rctx->framebuffer.zsbuf->texture->format) {
450 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
451 case PIPE_FORMAT_X8Z24_UNORM:
452 case PIPE_FORMAT_Z24X8_UNORM:
453 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
454 depth = -24;
455 offset_units *= 2.0f;
456 break;
457 case PIPE_FORMAT_Z32_FLOAT:
458 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
459 depth = -23;
460 offset_units *= 1.0f;
461 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
462 break;
463 case PIPE_FORMAT_Z16_UNORM:
464 depth = -16;
465 offset_units *= 4.0f;
466 break;
467 default:
468 return;
469 }
470
471 pm4 = si_pm4_alloc_state(rctx);
472
473 if (pm4 == NULL)
474 return;
475
476 /* FIXME some of those reg can be computed with cso */
477 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
478 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
479 fui(rctx->queued.named.rasterizer->offset_scale));
480 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
481 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
482 fui(rctx->queued.named.rasterizer->offset_scale));
483 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
484 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
485
486 si_pm4_set_state(rctx, fb_rs, pm4);
487 }
488
489 /*
490 * Rasterizer
491 */
492
493 static uint32_t si_translate_fill(uint32_t func)
494 {
495 switch(func) {
496 case PIPE_POLYGON_MODE_FILL:
497 return V_028814_X_DRAW_TRIANGLES;
498 case PIPE_POLYGON_MODE_LINE:
499 return V_028814_X_DRAW_LINES;
500 case PIPE_POLYGON_MODE_POINT:
501 return V_028814_X_DRAW_POINTS;
502 default:
503 assert(0);
504 return V_028814_X_DRAW_POINTS;
505 }
506 }
507
508 static void *si_create_rs_state(struct pipe_context *ctx,
509 const struct pipe_rasterizer_state *state)
510 {
511 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
512 struct si_pm4_state *pm4 = &rs->pm4;
513 unsigned tmp;
514 unsigned prov_vtx = 1, polygon_dual_mode;
515 unsigned clip_rule;
516 float psize_min, psize_max;
517
518 if (rs == NULL) {
519 return NULL;
520 }
521
522 rs->two_side = state->light_twoside;
523 rs->clip_plane_enable = state->clip_plane_enable;
524
525 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
526 state->fill_back != PIPE_POLYGON_MODE_FILL);
527
528 if (state->flatshade_first)
529 prov_vtx = 0;
530
531 rs->flatshade = state->flatshade;
532 rs->sprite_coord_enable = state->sprite_coord_enable;
533 rs->pa_sc_line_stipple = state->line_stipple_enable ?
534 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
535 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
536 rs->pa_su_sc_mode_cntl =
537 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
538 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
539 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
540 S_028814_FACE(!state->front_ccw) |
541 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
542 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
543 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
544 S_028814_POLY_MODE(polygon_dual_mode) |
545 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
546 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
547 rs->pa_cl_clip_cntl =
548 S_028810_PS_UCP_MODE(3) |
549 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
550 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
551 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
552
553 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
554
555 /* offset */
556 rs->offset_units = state->offset_units;
557 rs->offset_scale = state->offset_scale * 12.0f;
558
559 tmp = S_0286D4_FLAT_SHADE_ENA(1);
560 if (state->sprite_coord_enable) {
561 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
562 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
563 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
564 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
565 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
566 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
567 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
568 }
569 }
570 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
571
572 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
573 /* point size 12.4 fixed point */
574 tmp = (unsigned)(state->point_size * 8.0);
575 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
576
577 if (state->point_size_per_vertex) {
578 psize_min = util_get_min_point_size(state);
579 psize_max = 8192;
580 } else {
581 /* Force the point size to be as if the vertex output was disabled. */
582 psize_min = state->point_size;
583 psize_max = state->point_size;
584 }
585 /* Divide by two, because 0.5 = 1 pixel. */
586 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
587 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
588 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
589
590 tmp = (unsigned)state->line_width * 8;
591 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
592 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
593 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
594 S_028A48_MSAA_ENABLE(state->multisample));
595
596 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
597 S_028BE4_PIX_CENTER(state->half_pixel_center) |
598 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
599 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
600 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
601 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
602 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
603
604 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
605 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
606
607 return rs;
608 }
609
610 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
611 {
612 struct r600_context *rctx = (struct r600_context *)ctx;
613 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
614
615 if (state == NULL)
616 return;
617
618 // TODO
619 rctx->sprite_coord_enable = rs->sprite_coord_enable;
620 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
621 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
622
623 si_pm4_bind_state(rctx, rasterizer, rs);
624 si_update_fb_rs_state(rctx);
625 }
626
627 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
628 {
629 struct r600_context *rctx = (struct r600_context *)ctx;
630 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
631 }
632
633 /*
634 * infeered state between dsa and stencil ref
635 */
636 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
637 {
638 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
639 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
640 struct si_state_dsa *dsa = rctx->queued.named.dsa;
641
642 if (pm4 == NULL)
643 return;
644
645 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
646 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
647 S_028430_STENCILMASK(dsa->valuemask[0]) |
648 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
649 S_028430_STENCILOPVAL(1));
650 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
651 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
652 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
653 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
654 S_028434_STENCILOPVAL_BF(1));
655
656 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
657 }
658
659 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
660 const struct pipe_stencil_ref *state)
661 {
662 struct r600_context *rctx = (struct r600_context *)ctx;
663 rctx->stencil_ref = *state;
664 si_update_dsa_stencil_ref(rctx);
665 }
666
667
668 /*
669 * DSA
670 */
671
672 static uint32_t si_translate_stencil_op(int s_op)
673 {
674 switch (s_op) {
675 case PIPE_STENCIL_OP_KEEP:
676 return V_02842C_STENCIL_KEEP;
677 case PIPE_STENCIL_OP_ZERO:
678 return V_02842C_STENCIL_ZERO;
679 case PIPE_STENCIL_OP_REPLACE:
680 return V_02842C_STENCIL_REPLACE_TEST;
681 case PIPE_STENCIL_OP_INCR:
682 return V_02842C_STENCIL_ADD_CLAMP;
683 case PIPE_STENCIL_OP_DECR:
684 return V_02842C_STENCIL_SUB_CLAMP;
685 case PIPE_STENCIL_OP_INCR_WRAP:
686 return V_02842C_STENCIL_ADD_WRAP;
687 case PIPE_STENCIL_OP_DECR_WRAP:
688 return V_02842C_STENCIL_SUB_WRAP;
689 case PIPE_STENCIL_OP_INVERT:
690 return V_02842C_STENCIL_INVERT;
691 default:
692 R600_ERR("Unknown stencil op %d", s_op);
693 assert(0);
694 break;
695 }
696 return 0;
697 }
698
699 static void *si_create_dsa_state(struct pipe_context *ctx,
700 const struct pipe_depth_stencil_alpha_state *state)
701 {
702 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
703 struct si_pm4_state *pm4 = &dsa->pm4;
704 unsigned db_depth_control;
705 unsigned db_render_override, db_render_control;
706 uint32_t db_stencil_control = 0;
707
708 if (dsa == NULL) {
709 return NULL;
710 }
711
712 dsa->valuemask[0] = state->stencil[0].valuemask;
713 dsa->valuemask[1] = state->stencil[1].valuemask;
714 dsa->writemask[0] = state->stencil[0].writemask;
715 dsa->writemask[1] = state->stencil[1].writemask;
716
717 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
718 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
719 S_028800_ZFUNC(state->depth.func);
720
721 /* stencil */
722 if (state->stencil[0].enabled) {
723 db_depth_control |= S_028800_STENCIL_ENABLE(1);
724 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
725 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
726 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
727 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
728
729 if (state->stencil[1].enabled) {
730 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
731 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
732 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
733 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
734 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
735 }
736 }
737
738 /* alpha */
739 if (state->alpha.enabled) {
740 dsa->alpha_func = state->alpha.func;
741 dsa->alpha_ref = state->alpha.ref_value;
742 } else {
743 dsa->alpha_func = PIPE_FUNC_ALWAYS;
744 }
745
746 /* misc */
747 db_render_control = 0;
748 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
749 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
750 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
751 /* TODO db_render_override depends on query */
752 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
753 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
754 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
755 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
756 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
757 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
758 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
759 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
760 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
761 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
762 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
763 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
764 dsa->db_render_override = db_render_override;
765
766 return dsa;
767 }
768
769 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
770 {
771 struct r600_context *rctx = (struct r600_context *)ctx;
772 struct si_state_dsa *dsa = state;
773
774 if (state == NULL)
775 return;
776
777 si_pm4_bind_state(rctx, dsa, dsa);
778 si_update_dsa_stencil_ref(rctx);
779 }
780
781 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
782 {
783 struct r600_context *rctx = (struct r600_context *)ctx;
784 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
785 }
786
787 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
788 bool copy_stencil)
789 {
790 struct pipe_depth_stencil_alpha_state dsa;
791 struct si_state_dsa *state;
792
793 memset(&dsa, 0, sizeof(dsa));
794
795 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
796 if (copy_depth || copy_stencil) {
797 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
798 S_028000_DEPTH_COPY(copy_depth) |
799 S_028000_STENCIL_COPY(copy_stencil) |
800 S_028000_COPY_CENTROID(1));
801 } else {
802 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
803 S_028000_DEPTH_COMPRESS_DISABLE(1) |
804 S_028000_STENCIL_COMPRESS_DISABLE(1));
805 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
806 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
807 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
808 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
809 S_02800C_DISABLE_TILE_RATE_TILES(1));
810 }
811
812 return state;
813 }
814
815 /*
816 * format translation
817 */
818 static uint32_t si_translate_colorformat(enum pipe_format format)
819 {
820 switch (format) {
821 /* 8-bit buffers. */
822 case PIPE_FORMAT_A8_UNORM:
823 case PIPE_FORMAT_A8_SNORM:
824 case PIPE_FORMAT_A8_UINT:
825 case PIPE_FORMAT_A8_SINT:
826 case PIPE_FORMAT_I8_UNORM:
827 case PIPE_FORMAT_I8_SNORM:
828 case PIPE_FORMAT_I8_UINT:
829 case PIPE_FORMAT_I8_SINT:
830 case PIPE_FORMAT_L8_UNORM:
831 case PIPE_FORMAT_L8_SNORM:
832 case PIPE_FORMAT_L8_UINT:
833 case PIPE_FORMAT_L8_SINT:
834 case PIPE_FORMAT_L8_SRGB:
835 case PIPE_FORMAT_R8_UNORM:
836 case PIPE_FORMAT_R8_SNORM:
837 case PIPE_FORMAT_R8_UINT:
838 case PIPE_FORMAT_R8_SINT:
839 return V_028C70_COLOR_8;
840
841 /* 16-bit buffers. */
842 case PIPE_FORMAT_B5G6R5_UNORM:
843 return V_028C70_COLOR_5_6_5;
844
845 case PIPE_FORMAT_B5G5R5A1_UNORM:
846 case PIPE_FORMAT_B5G5R5X1_UNORM:
847 return V_028C70_COLOR_1_5_5_5;
848
849 case PIPE_FORMAT_B4G4R4A4_UNORM:
850 case PIPE_FORMAT_B4G4R4X4_UNORM:
851 return V_028C70_COLOR_4_4_4_4;
852
853 case PIPE_FORMAT_L8A8_UNORM:
854 case PIPE_FORMAT_L8A8_SNORM:
855 case PIPE_FORMAT_L8A8_UINT:
856 case PIPE_FORMAT_L8A8_SINT:
857 case PIPE_FORMAT_R8G8_SNORM:
858 case PIPE_FORMAT_R8G8_UNORM:
859 case PIPE_FORMAT_R8G8_UINT:
860 case PIPE_FORMAT_R8G8_SINT:
861 return V_028C70_COLOR_8_8;
862
863 case PIPE_FORMAT_Z16_UNORM:
864 case PIPE_FORMAT_R16_UNORM:
865 case PIPE_FORMAT_R16_SNORM:
866 case PIPE_FORMAT_R16_UINT:
867 case PIPE_FORMAT_R16_SINT:
868 case PIPE_FORMAT_R16_FLOAT:
869 case PIPE_FORMAT_L16_UNORM:
870 case PIPE_FORMAT_L16_SNORM:
871 case PIPE_FORMAT_L16_FLOAT:
872 case PIPE_FORMAT_I16_UNORM:
873 case PIPE_FORMAT_I16_SNORM:
874 case PIPE_FORMAT_I16_FLOAT:
875 case PIPE_FORMAT_A16_UNORM:
876 case PIPE_FORMAT_A16_SNORM:
877 case PIPE_FORMAT_A16_FLOAT:
878 return V_028C70_COLOR_16;
879
880 /* 32-bit buffers. */
881 case PIPE_FORMAT_A8B8G8R8_SRGB:
882 case PIPE_FORMAT_A8B8G8R8_UNORM:
883 case PIPE_FORMAT_A8R8G8B8_UNORM:
884 case PIPE_FORMAT_B8G8R8A8_SRGB:
885 case PIPE_FORMAT_B8G8R8A8_UNORM:
886 case PIPE_FORMAT_B8G8R8X8_UNORM:
887 case PIPE_FORMAT_R8G8B8A8_SNORM:
888 case PIPE_FORMAT_R8G8B8A8_UNORM:
889 case PIPE_FORMAT_R8G8B8X8_UNORM:
890 case PIPE_FORMAT_R8G8B8X8_SNORM:
891 case PIPE_FORMAT_R8G8B8X8_SRGB:
892 case PIPE_FORMAT_R8G8B8X8_UINT:
893 case PIPE_FORMAT_R8G8B8X8_SINT:
894 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
895 case PIPE_FORMAT_X8B8G8R8_UNORM:
896 case PIPE_FORMAT_X8R8G8B8_UNORM:
897 case PIPE_FORMAT_R8G8B8A8_SSCALED:
898 case PIPE_FORMAT_R8G8B8A8_USCALED:
899 case PIPE_FORMAT_R8G8B8A8_SINT:
900 case PIPE_FORMAT_R8G8B8A8_UINT:
901 return V_028C70_COLOR_8_8_8_8;
902
903 case PIPE_FORMAT_R10G10B10A2_UNORM:
904 case PIPE_FORMAT_R10G10B10X2_SNORM:
905 case PIPE_FORMAT_B10G10R10A2_UNORM:
906 case PIPE_FORMAT_B10G10R10A2_UINT:
907 case PIPE_FORMAT_B10G10R10X2_UNORM:
908 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
909 return V_028C70_COLOR_2_10_10_10;
910
911 case PIPE_FORMAT_Z24X8_UNORM:
912 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
913 return V_028C70_COLOR_8_24;
914
915 case PIPE_FORMAT_S8X24_UINT:
916 case PIPE_FORMAT_X8Z24_UNORM:
917 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
918 return V_028C70_COLOR_24_8;
919
920 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
921 return V_028C70_COLOR_X24_8_32_FLOAT;
922
923 case PIPE_FORMAT_I32_FLOAT:
924 case PIPE_FORMAT_L32_FLOAT:
925 case PIPE_FORMAT_R32_FLOAT:
926 case PIPE_FORMAT_A32_FLOAT:
927 case PIPE_FORMAT_Z32_FLOAT:
928 return V_028C70_COLOR_32;
929
930 case PIPE_FORMAT_L16A16_UNORM:
931 case PIPE_FORMAT_L16A16_SNORM:
932 case PIPE_FORMAT_L16A16_FLOAT:
933 case PIPE_FORMAT_R16G16_SSCALED:
934 case PIPE_FORMAT_R16G16_UNORM:
935 case PIPE_FORMAT_R16G16_SNORM:
936 case PIPE_FORMAT_R16G16_UINT:
937 case PIPE_FORMAT_R16G16_SINT:
938 case PIPE_FORMAT_R16G16_FLOAT:
939 return V_028C70_COLOR_16_16;
940
941 case PIPE_FORMAT_R11G11B10_FLOAT:
942 return V_028C70_COLOR_10_11_11;
943
944 /* 64-bit buffers. */
945 case PIPE_FORMAT_R16G16B16A16_UINT:
946 case PIPE_FORMAT_R16G16B16A16_SINT:
947 case PIPE_FORMAT_R16G16B16A16_USCALED:
948 case PIPE_FORMAT_R16G16B16A16_SSCALED:
949 case PIPE_FORMAT_R16G16B16A16_UNORM:
950 case PIPE_FORMAT_R16G16B16A16_SNORM:
951 case PIPE_FORMAT_R16G16B16A16_FLOAT:
952 case PIPE_FORMAT_R16G16B16X16_UNORM:
953 case PIPE_FORMAT_R16G16B16X16_SNORM:
954 case PIPE_FORMAT_R16G16B16X16_FLOAT:
955 case PIPE_FORMAT_R16G16B16X16_UINT:
956 case PIPE_FORMAT_R16G16B16X16_SINT:
957 return V_028C70_COLOR_16_16_16_16;
958
959 case PIPE_FORMAT_L32A32_FLOAT:
960 case PIPE_FORMAT_L32A32_UINT:
961 case PIPE_FORMAT_L32A32_SINT:
962 case PIPE_FORMAT_R32G32_FLOAT:
963 case PIPE_FORMAT_R32G32_USCALED:
964 case PIPE_FORMAT_R32G32_SSCALED:
965 case PIPE_FORMAT_R32G32_SINT:
966 case PIPE_FORMAT_R32G32_UINT:
967 return V_028C70_COLOR_32_32;
968
969 /* 128-bit buffers. */
970 case PIPE_FORMAT_R32G32B32A32_SNORM:
971 case PIPE_FORMAT_R32G32B32A32_UNORM:
972 case PIPE_FORMAT_R32G32B32A32_SSCALED:
973 case PIPE_FORMAT_R32G32B32A32_USCALED:
974 case PIPE_FORMAT_R32G32B32A32_SINT:
975 case PIPE_FORMAT_R32G32B32A32_UINT:
976 case PIPE_FORMAT_R32G32B32A32_FLOAT:
977 case PIPE_FORMAT_R32G32B32X32_FLOAT:
978 case PIPE_FORMAT_R32G32B32X32_UINT:
979 case PIPE_FORMAT_R32G32B32X32_SINT:
980 return V_028C70_COLOR_32_32_32_32;
981
982 /* YUV buffers. */
983 case PIPE_FORMAT_UYVY:
984 case PIPE_FORMAT_YUYV:
985 /* 96-bit buffers. */
986 case PIPE_FORMAT_R32G32B32_FLOAT:
987 /* 8-bit buffers. */
988 case PIPE_FORMAT_L4A4_UNORM:
989 case PIPE_FORMAT_R4A4_UNORM:
990 case PIPE_FORMAT_A4R4_UNORM:
991 default:
992 return V_028C70_COLOR_INVALID; /* Unsupported. */
993 }
994 }
995
996 static uint32_t si_translate_colorswap(enum pipe_format format)
997 {
998 switch (format) {
999 /* 8-bit buffers. */
1000 case PIPE_FORMAT_L4A4_UNORM:
1001 case PIPE_FORMAT_A4R4_UNORM:
1002 return V_028C70_SWAP_ALT;
1003
1004 case PIPE_FORMAT_A8_UNORM:
1005 case PIPE_FORMAT_A8_SNORM:
1006 case PIPE_FORMAT_A8_UINT:
1007 case PIPE_FORMAT_A8_SINT:
1008 case PIPE_FORMAT_R4A4_UNORM:
1009 return V_028C70_SWAP_ALT_REV;
1010 case PIPE_FORMAT_I8_UNORM:
1011 case PIPE_FORMAT_I8_SNORM:
1012 case PIPE_FORMAT_L8_UNORM:
1013 case PIPE_FORMAT_L8_SNORM:
1014 case PIPE_FORMAT_I8_UINT:
1015 case PIPE_FORMAT_I8_SINT:
1016 case PIPE_FORMAT_L8_UINT:
1017 case PIPE_FORMAT_L8_SINT:
1018 case PIPE_FORMAT_L8_SRGB:
1019 case PIPE_FORMAT_R8_UNORM:
1020 case PIPE_FORMAT_R8_SNORM:
1021 case PIPE_FORMAT_R8_UINT:
1022 case PIPE_FORMAT_R8_SINT:
1023 return V_028C70_SWAP_STD;
1024
1025 /* 16-bit buffers. */
1026 case PIPE_FORMAT_B5G6R5_UNORM:
1027 return V_028C70_SWAP_STD_REV;
1028
1029 case PIPE_FORMAT_B5G5R5A1_UNORM:
1030 case PIPE_FORMAT_B5G5R5X1_UNORM:
1031 return V_028C70_SWAP_ALT;
1032
1033 case PIPE_FORMAT_B4G4R4A4_UNORM:
1034 case PIPE_FORMAT_B4G4R4X4_UNORM:
1035 return V_028C70_SWAP_ALT;
1036
1037 case PIPE_FORMAT_Z16_UNORM:
1038 return V_028C70_SWAP_STD;
1039
1040 case PIPE_FORMAT_L8A8_UNORM:
1041 case PIPE_FORMAT_L8A8_SNORM:
1042 case PIPE_FORMAT_L8A8_UINT:
1043 case PIPE_FORMAT_L8A8_SINT:
1044 return V_028C70_SWAP_ALT;
1045 case PIPE_FORMAT_R8G8_SNORM:
1046 case PIPE_FORMAT_R8G8_UNORM:
1047 case PIPE_FORMAT_R8G8_UINT:
1048 case PIPE_FORMAT_R8G8_SINT:
1049 return V_028C70_SWAP_STD;
1050
1051 case PIPE_FORMAT_I16_UNORM:
1052 case PIPE_FORMAT_I16_SNORM:
1053 case PIPE_FORMAT_I16_FLOAT:
1054 case PIPE_FORMAT_L16_UNORM:
1055 case PIPE_FORMAT_L16_SNORM:
1056 case PIPE_FORMAT_L16_FLOAT:
1057 case PIPE_FORMAT_R16_UNORM:
1058 case PIPE_FORMAT_R16_SNORM:
1059 case PIPE_FORMAT_R16_UINT:
1060 case PIPE_FORMAT_R16_SINT:
1061 case PIPE_FORMAT_R16_FLOAT:
1062 return V_028C70_SWAP_STD;
1063
1064 case PIPE_FORMAT_A16_UNORM:
1065 case PIPE_FORMAT_A16_SNORM:
1066 case PIPE_FORMAT_A16_FLOAT:
1067 return V_028C70_SWAP_ALT_REV;
1068
1069 /* 32-bit buffers. */
1070 case PIPE_FORMAT_A8B8G8R8_SRGB:
1071 return V_028C70_SWAP_STD_REV;
1072 case PIPE_FORMAT_B8G8R8A8_SRGB:
1073 return V_028C70_SWAP_ALT;
1074
1075 case PIPE_FORMAT_B8G8R8A8_UNORM:
1076 case PIPE_FORMAT_B8G8R8X8_UNORM:
1077 return V_028C70_SWAP_ALT;
1078
1079 case PIPE_FORMAT_A8R8G8B8_UNORM:
1080 case PIPE_FORMAT_X8R8G8B8_UNORM:
1081 return V_028C70_SWAP_ALT_REV;
1082 case PIPE_FORMAT_R8G8B8A8_SNORM:
1083 case PIPE_FORMAT_R8G8B8A8_UNORM:
1084 case PIPE_FORMAT_R8G8B8A8_SSCALED:
1085 case PIPE_FORMAT_R8G8B8A8_USCALED:
1086 case PIPE_FORMAT_R8G8B8A8_SINT:
1087 case PIPE_FORMAT_R8G8B8A8_UINT:
1088 case PIPE_FORMAT_R8G8B8X8_UNORM:
1089 case PIPE_FORMAT_R8G8B8X8_SNORM:
1090 case PIPE_FORMAT_R8G8B8X8_SRGB:
1091 case PIPE_FORMAT_R8G8B8X8_UINT:
1092 case PIPE_FORMAT_R8G8B8X8_SINT:
1093 return V_028C70_SWAP_STD;
1094
1095 case PIPE_FORMAT_A8B8G8R8_UNORM:
1096 case PIPE_FORMAT_X8B8G8R8_UNORM:
1097 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
1098 return V_028C70_SWAP_STD_REV;
1099
1100 case PIPE_FORMAT_Z24X8_UNORM:
1101 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1102 return V_028C70_SWAP_STD;
1103
1104 case PIPE_FORMAT_S8X24_UINT:
1105 case PIPE_FORMAT_X8Z24_UNORM:
1106 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1107 return V_028C70_SWAP_STD_REV;
1108
1109 case PIPE_FORMAT_R10G10B10A2_UNORM:
1110 case PIPE_FORMAT_R10G10B10X2_SNORM:
1111 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
1112 return V_028C70_SWAP_STD;
1113
1114 case PIPE_FORMAT_B10G10R10A2_UNORM:
1115 case PIPE_FORMAT_B10G10R10A2_UINT:
1116 case PIPE_FORMAT_B10G10R10X2_UNORM:
1117 return V_028C70_SWAP_ALT;
1118
1119 case PIPE_FORMAT_R11G11B10_FLOAT:
1120 case PIPE_FORMAT_I32_FLOAT:
1121 case PIPE_FORMAT_L32_FLOAT:
1122 case PIPE_FORMAT_R32_FLOAT:
1123 case PIPE_FORMAT_R32_UINT:
1124 case PIPE_FORMAT_R32_SINT:
1125 case PIPE_FORMAT_Z32_FLOAT:
1126 case PIPE_FORMAT_R16G16_FLOAT:
1127 case PIPE_FORMAT_R16G16_UNORM:
1128 case PIPE_FORMAT_R16G16_SNORM:
1129 case PIPE_FORMAT_R16G16_UINT:
1130 case PIPE_FORMAT_R16G16_SINT:
1131 return V_028C70_SWAP_STD;
1132
1133 case PIPE_FORMAT_L16A16_UNORM:
1134 case PIPE_FORMAT_L16A16_SNORM:
1135 case PIPE_FORMAT_L16A16_FLOAT:
1136 return V_028C70_SWAP_ALT;
1137
1138 case PIPE_FORMAT_A32_FLOAT:
1139 return V_028C70_SWAP_ALT_REV;
1140
1141 /* 64-bit buffers. */
1142 case PIPE_FORMAT_R32G32_FLOAT:
1143 case PIPE_FORMAT_R32G32_UINT:
1144 case PIPE_FORMAT_R32G32_SINT:
1145 case PIPE_FORMAT_R16G16B16A16_UNORM:
1146 case PIPE_FORMAT_R16G16B16A16_SNORM:
1147 case PIPE_FORMAT_R16G16B16A16_USCALED:
1148 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1149 case PIPE_FORMAT_R16G16B16A16_UINT:
1150 case PIPE_FORMAT_R16G16B16A16_SINT:
1151 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1152 case PIPE_FORMAT_R16G16B16X16_UNORM:
1153 case PIPE_FORMAT_R16G16B16X16_SNORM:
1154 case PIPE_FORMAT_R16G16B16X16_FLOAT:
1155 case PIPE_FORMAT_R16G16B16X16_UINT:
1156 case PIPE_FORMAT_R16G16B16X16_SINT:
1157 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1158 return V_028C70_SWAP_STD;
1159
1160 case PIPE_FORMAT_L32A32_FLOAT:
1161 case PIPE_FORMAT_L32A32_UINT:
1162 case PIPE_FORMAT_L32A32_SINT:
1163 return V_028C70_SWAP_ALT;
1164
1165 /* 128-bit buffers. */
1166 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1167 case PIPE_FORMAT_R32G32B32A32_SNORM:
1168 case PIPE_FORMAT_R32G32B32A32_UNORM:
1169 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1170 case PIPE_FORMAT_R32G32B32A32_USCALED:
1171 case PIPE_FORMAT_R32G32B32A32_SINT:
1172 case PIPE_FORMAT_R32G32B32A32_UINT:
1173 case PIPE_FORMAT_R32G32B32X32_FLOAT:
1174 case PIPE_FORMAT_R32G32B32X32_UINT:
1175 case PIPE_FORMAT_R32G32B32X32_SINT:
1176 return V_028C70_SWAP_STD;
1177 default:
1178 R600_ERR("unsupported colorswap format %d\n", format);
1179 return ~0U;
1180 }
1181 return ~0U;
1182 }
1183
1184 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1185 {
1186 if (R600_BIG_ENDIAN) {
1187 switch(colorformat) {
1188 /* 8-bit buffers. */
1189 case V_028C70_COLOR_8:
1190 return V_028C70_ENDIAN_NONE;
1191
1192 /* 16-bit buffers. */
1193 case V_028C70_COLOR_5_6_5:
1194 case V_028C70_COLOR_1_5_5_5:
1195 case V_028C70_COLOR_4_4_4_4:
1196 case V_028C70_COLOR_16:
1197 case V_028C70_COLOR_8_8:
1198 return V_028C70_ENDIAN_8IN16;
1199
1200 /* 32-bit buffers. */
1201 case V_028C70_COLOR_8_8_8_8:
1202 case V_028C70_COLOR_2_10_10_10:
1203 case V_028C70_COLOR_8_24:
1204 case V_028C70_COLOR_24_8:
1205 case V_028C70_COLOR_16_16:
1206 return V_028C70_ENDIAN_8IN32;
1207
1208 /* 64-bit buffers. */
1209 case V_028C70_COLOR_16_16_16_16:
1210 return V_028C70_ENDIAN_8IN16;
1211
1212 case V_028C70_COLOR_32_32:
1213 return V_028C70_ENDIAN_8IN32;
1214
1215 /* 128-bit buffers. */
1216 case V_028C70_COLOR_32_32_32_32:
1217 return V_028C70_ENDIAN_8IN32;
1218 default:
1219 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1220 }
1221 } else {
1222 return V_028C70_ENDIAN_NONE;
1223 }
1224 }
1225
1226 /* Returns the size in bits of the widest component of a CB format */
1227 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1228 {
1229 switch(colorformat) {
1230 case V_028C70_COLOR_4_4_4_4:
1231 return 4;
1232
1233 case V_028C70_COLOR_1_5_5_5:
1234 case V_028C70_COLOR_5_5_5_1:
1235 return 5;
1236
1237 case V_028C70_COLOR_5_6_5:
1238 return 6;
1239
1240 case V_028C70_COLOR_8:
1241 case V_028C70_COLOR_8_8:
1242 case V_028C70_COLOR_8_8_8_8:
1243 return 8;
1244
1245 case V_028C70_COLOR_10_10_10_2:
1246 case V_028C70_COLOR_2_10_10_10:
1247 return 10;
1248
1249 case V_028C70_COLOR_10_11_11:
1250 case V_028C70_COLOR_11_11_10:
1251 return 11;
1252
1253 case V_028C70_COLOR_16:
1254 case V_028C70_COLOR_16_16:
1255 case V_028C70_COLOR_16_16_16_16:
1256 return 16;
1257
1258 case V_028C70_COLOR_8_24:
1259 case V_028C70_COLOR_24_8:
1260 return 24;
1261
1262 case V_028C70_COLOR_32:
1263 case V_028C70_COLOR_32_32:
1264 case V_028C70_COLOR_32_32_32_32:
1265 case V_028C70_COLOR_X24_8_32_FLOAT:
1266 return 32;
1267 }
1268
1269 assert(!"Unknown maximum component size");
1270 return 0;
1271 }
1272
1273 static uint32_t si_translate_dbformat(enum pipe_format format)
1274 {
1275 switch (format) {
1276 case PIPE_FORMAT_Z16_UNORM:
1277 return V_028040_Z_16;
1278 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1279 case PIPE_FORMAT_X8Z24_UNORM:
1280 case PIPE_FORMAT_Z24X8_UNORM:
1281 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1282 return V_028040_Z_24; /* deprecated on SI */
1283 case PIPE_FORMAT_Z32_FLOAT:
1284 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1285 return V_028040_Z_32_FLOAT;
1286 default:
1287 return V_028040_Z_INVALID;
1288 }
1289 }
1290
1291 /*
1292 * Texture translation
1293 */
1294
1295 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1296 enum pipe_format format,
1297 const struct util_format_description *desc,
1298 int first_non_void)
1299 {
1300 struct r600_screen *rscreen = (struct r600_screen*)screen;
1301 bool enable_s3tc = rscreen->info.drm_minor >= 31;
1302 boolean uniform = TRUE;
1303 int i;
1304
1305 /* Colorspace (return non-RGB formats directly). */
1306 switch (desc->colorspace) {
1307 /* Depth stencil formats */
1308 case UTIL_FORMAT_COLORSPACE_ZS:
1309 switch (format) {
1310 case PIPE_FORMAT_Z16_UNORM:
1311 return V_008F14_IMG_DATA_FORMAT_16;
1312 case PIPE_FORMAT_X24S8_UINT:
1313 case PIPE_FORMAT_Z24X8_UNORM:
1314 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1315 return V_008F14_IMG_DATA_FORMAT_8_24;
1316 case PIPE_FORMAT_X8Z24_UNORM:
1317 case PIPE_FORMAT_S8X24_UINT:
1318 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1319 return V_008F14_IMG_DATA_FORMAT_24_8;
1320 case PIPE_FORMAT_S8_UINT:
1321 return V_008F14_IMG_DATA_FORMAT_8;
1322 case PIPE_FORMAT_Z32_FLOAT:
1323 return V_008F14_IMG_DATA_FORMAT_32;
1324 case PIPE_FORMAT_X32_S8X24_UINT:
1325 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1326 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1327 default:
1328 goto out_unknown;
1329 }
1330
1331 case UTIL_FORMAT_COLORSPACE_YUV:
1332 goto out_unknown; /* TODO */
1333
1334 case UTIL_FORMAT_COLORSPACE_SRGB:
1335 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1336 goto out_unknown;
1337 break;
1338
1339 default:
1340 break;
1341 }
1342
1343 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1344 if (!enable_s3tc)
1345 goto out_unknown;
1346
1347 switch (format) {
1348 case PIPE_FORMAT_RGTC1_SNORM:
1349 case PIPE_FORMAT_LATC1_SNORM:
1350 case PIPE_FORMAT_RGTC1_UNORM:
1351 case PIPE_FORMAT_LATC1_UNORM:
1352 return V_008F14_IMG_DATA_FORMAT_BC4;
1353 case PIPE_FORMAT_RGTC2_SNORM:
1354 case PIPE_FORMAT_LATC2_SNORM:
1355 case PIPE_FORMAT_RGTC2_UNORM:
1356 case PIPE_FORMAT_LATC2_UNORM:
1357 return V_008F14_IMG_DATA_FORMAT_BC5;
1358 default:
1359 goto out_unknown;
1360 }
1361 }
1362
1363 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1364
1365 if (!enable_s3tc)
1366 goto out_unknown;
1367
1368 if (!util_format_s3tc_enabled) {
1369 goto out_unknown;
1370 }
1371
1372 switch (format) {
1373 case PIPE_FORMAT_DXT1_RGB:
1374 case PIPE_FORMAT_DXT1_RGBA:
1375 case PIPE_FORMAT_DXT1_SRGB:
1376 case PIPE_FORMAT_DXT1_SRGBA:
1377 return V_008F14_IMG_DATA_FORMAT_BC1;
1378 case PIPE_FORMAT_DXT3_RGBA:
1379 case PIPE_FORMAT_DXT3_SRGBA:
1380 return V_008F14_IMG_DATA_FORMAT_BC2;
1381 case PIPE_FORMAT_DXT5_RGBA:
1382 case PIPE_FORMAT_DXT5_SRGBA:
1383 return V_008F14_IMG_DATA_FORMAT_BC3;
1384 default:
1385 goto out_unknown;
1386 }
1387 }
1388
1389 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1390 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1391 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1392 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1393 }
1394
1395 /* R8G8Bx_SNORM - TODO CxV8U8 */
1396
1397 /* See whether the components are of the same size. */
1398 for (i = 1; i < desc->nr_channels; i++) {
1399 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1400 }
1401
1402 /* Non-uniform formats. */
1403 if (!uniform) {
1404 switch(desc->nr_channels) {
1405 case 3:
1406 if (desc->channel[0].size == 5 &&
1407 desc->channel[1].size == 6 &&
1408 desc->channel[2].size == 5) {
1409 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1410 }
1411 goto out_unknown;
1412 case 4:
1413 if (desc->channel[0].size == 5 &&
1414 desc->channel[1].size == 5 &&
1415 desc->channel[2].size == 5 &&
1416 desc->channel[3].size == 1) {
1417 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1418 }
1419 if (desc->channel[0].size == 10 &&
1420 desc->channel[1].size == 10 &&
1421 desc->channel[2].size == 10 &&
1422 desc->channel[3].size == 2) {
1423 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1424 }
1425 goto out_unknown;
1426 }
1427 goto out_unknown;
1428 }
1429
1430 if (first_non_void < 0 || first_non_void > 3)
1431 goto out_unknown;
1432
1433 /* uniform formats */
1434 switch (desc->channel[first_non_void].size) {
1435 case 4:
1436 switch (desc->nr_channels) {
1437 #if 0 /* Not supported for render targets */
1438 case 2:
1439 return V_008F14_IMG_DATA_FORMAT_4_4;
1440 #endif
1441 case 4:
1442 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1443 }
1444 break;
1445 case 8:
1446 switch (desc->nr_channels) {
1447 case 1:
1448 return V_008F14_IMG_DATA_FORMAT_8;
1449 case 2:
1450 return V_008F14_IMG_DATA_FORMAT_8_8;
1451 case 4:
1452 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1453 }
1454 break;
1455 case 16:
1456 switch (desc->nr_channels) {
1457 case 1:
1458 return V_008F14_IMG_DATA_FORMAT_16;
1459 case 2:
1460 return V_008F14_IMG_DATA_FORMAT_16_16;
1461 case 4:
1462 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1463 }
1464 break;
1465 case 32:
1466 switch (desc->nr_channels) {
1467 case 1:
1468 return V_008F14_IMG_DATA_FORMAT_32;
1469 case 2:
1470 return V_008F14_IMG_DATA_FORMAT_32_32;
1471 #if 0 /* Not supported for render targets */
1472 case 3:
1473 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1474 #endif
1475 case 4:
1476 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1477 }
1478 }
1479
1480 out_unknown:
1481 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1482 return ~0;
1483 }
1484
1485 static unsigned si_tex_wrap(unsigned wrap)
1486 {
1487 switch (wrap) {
1488 default:
1489 case PIPE_TEX_WRAP_REPEAT:
1490 return V_008F30_SQ_TEX_WRAP;
1491 case PIPE_TEX_WRAP_CLAMP:
1492 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1493 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1494 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1495 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1496 return V_008F30_SQ_TEX_CLAMP_BORDER;
1497 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1498 return V_008F30_SQ_TEX_MIRROR;
1499 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1500 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1501 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1502 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1503 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1504 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1505 }
1506 }
1507
1508 static unsigned si_tex_filter(unsigned filter)
1509 {
1510 switch (filter) {
1511 default:
1512 case PIPE_TEX_FILTER_NEAREST:
1513 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1514 case PIPE_TEX_FILTER_LINEAR:
1515 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1516 }
1517 }
1518
1519 static unsigned si_tex_mipfilter(unsigned filter)
1520 {
1521 switch (filter) {
1522 case PIPE_TEX_MIPFILTER_NEAREST:
1523 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1524 case PIPE_TEX_MIPFILTER_LINEAR:
1525 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1526 default:
1527 case PIPE_TEX_MIPFILTER_NONE:
1528 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1529 }
1530 }
1531
1532 static unsigned si_tex_compare(unsigned compare)
1533 {
1534 switch (compare) {
1535 default:
1536 case PIPE_FUNC_NEVER:
1537 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1538 case PIPE_FUNC_LESS:
1539 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1540 case PIPE_FUNC_EQUAL:
1541 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1542 case PIPE_FUNC_LEQUAL:
1543 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1544 case PIPE_FUNC_GREATER:
1545 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1546 case PIPE_FUNC_NOTEQUAL:
1547 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1548 case PIPE_FUNC_GEQUAL:
1549 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1550 case PIPE_FUNC_ALWAYS:
1551 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1552 }
1553 }
1554
1555 static unsigned si_tex_dim(unsigned dim)
1556 {
1557 switch (dim) {
1558 default:
1559 case PIPE_TEXTURE_1D:
1560 return V_008F1C_SQ_RSRC_IMG_1D;
1561 case PIPE_TEXTURE_1D_ARRAY:
1562 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1563 case PIPE_TEXTURE_2D:
1564 case PIPE_TEXTURE_RECT:
1565 return V_008F1C_SQ_RSRC_IMG_2D;
1566 case PIPE_TEXTURE_2D_ARRAY:
1567 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1568 case PIPE_TEXTURE_3D:
1569 return V_008F1C_SQ_RSRC_IMG_3D;
1570 case PIPE_TEXTURE_CUBE:
1571 return V_008F1C_SQ_RSRC_IMG_CUBE;
1572 }
1573 }
1574
1575 /*
1576 * Format support testing
1577 */
1578
1579 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1580 {
1581 return si_translate_texformat(screen, format, util_format_description(format),
1582 util_format_get_first_non_void_channel(format)) != ~0U;
1583 }
1584
1585 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1586 enum pipe_format format,
1587 const struct util_format_description *desc,
1588 int first_non_void)
1589 {
1590 unsigned type = desc->channel[first_non_void].type;
1591 int i;
1592
1593 if (type == UTIL_FORMAT_TYPE_FIXED)
1594 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1595
1596 /* See whether the components are of the same size. */
1597 for (i = 0; i < desc->nr_channels; i++) {
1598 if (desc->channel[first_non_void].size != desc->channel[i].size)
1599 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1600 }
1601
1602 switch (desc->channel[first_non_void].size) {
1603 case 8:
1604 switch (desc->nr_channels) {
1605 case 1:
1606 return V_008F0C_BUF_DATA_FORMAT_8;
1607 case 2:
1608 return V_008F0C_BUF_DATA_FORMAT_8_8;
1609 case 3:
1610 case 4:
1611 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1612 }
1613 break;
1614 case 16:
1615 switch (desc->nr_channels) {
1616 case 1:
1617 return V_008F0C_BUF_DATA_FORMAT_16;
1618 case 2:
1619 return V_008F0C_BUF_DATA_FORMAT_16_16;
1620 case 3:
1621 case 4:
1622 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1623 }
1624 break;
1625 case 32:
1626 if (type != UTIL_FORMAT_TYPE_FLOAT)
1627 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1628
1629 switch (desc->nr_channels) {
1630 case 1:
1631 return V_008F0C_BUF_DATA_FORMAT_32;
1632 case 2:
1633 return V_008F0C_BUF_DATA_FORMAT_32_32;
1634 case 3:
1635 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1636 case 4:
1637 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1638 }
1639 break;
1640 }
1641
1642 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1643 }
1644
1645 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1646 {
1647 const struct util_format_description *desc;
1648 int first_non_void;
1649 unsigned data_format;
1650
1651 desc = util_format_description(format);
1652 first_non_void = util_format_get_first_non_void_channel(format);
1653 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1654 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1655 }
1656
1657 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1658 {
1659 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1660 si_translate_colorswap(format) != ~0U;
1661 }
1662
1663 static bool si_is_zs_format_supported(enum pipe_format format)
1664 {
1665 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1666 }
1667
1668 boolean si_is_format_supported(struct pipe_screen *screen,
1669 enum pipe_format format,
1670 enum pipe_texture_target target,
1671 unsigned sample_count,
1672 unsigned usage)
1673 {
1674 struct r600_screen *rscreen = (struct r600_screen *)screen;
1675 unsigned retval = 0;
1676
1677 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1678 R600_ERR("r600: unsupported texture type %d\n", target);
1679 return FALSE;
1680 }
1681
1682 if (!util_format_is_supported(format, usage))
1683 return FALSE;
1684
1685 if (sample_count > 1) {
1686 if (rscreen->chip_class >= CIK)
1687 return FALSE;
1688
1689 switch (sample_count) {
1690 case 2:
1691 case 4:
1692 case 8:
1693 break;
1694 default:
1695 return FALSE;
1696 }
1697 }
1698
1699 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1700 si_is_sampler_format_supported(screen, format)) {
1701 retval |= PIPE_BIND_SAMPLER_VIEW;
1702 }
1703
1704 if ((usage & (PIPE_BIND_RENDER_TARGET |
1705 PIPE_BIND_DISPLAY_TARGET |
1706 PIPE_BIND_SCANOUT |
1707 PIPE_BIND_SHARED)) &&
1708 si_is_colorbuffer_format_supported(format)) {
1709 retval |= usage &
1710 (PIPE_BIND_RENDER_TARGET |
1711 PIPE_BIND_DISPLAY_TARGET |
1712 PIPE_BIND_SCANOUT |
1713 PIPE_BIND_SHARED);
1714 }
1715
1716 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1717 si_is_zs_format_supported(format)) {
1718 retval |= PIPE_BIND_DEPTH_STENCIL;
1719 }
1720
1721 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1722 si_is_vertex_format_supported(screen, format)) {
1723 retval |= PIPE_BIND_VERTEX_BUFFER;
1724 }
1725
1726 if (usage & PIPE_BIND_TRANSFER_READ)
1727 retval |= PIPE_BIND_TRANSFER_READ;
1728 if (usage & PIPE_BIND_TRANSFER_WRITE)
1729 retval |= PIPE_BIND_TRANSFER_WRITE;
1730
1731 return retval == usage;
1732 }
1733
1734 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1735 {
1736 unsigned tile_mode_index = 0;
1737
1738 if (stencil) {
1739 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1740 } else {
1741 tile_mode_index = rtex->surface.tiling_index[level];
1742 }
1743 return tile_mode_index;
1744 }
1745
1746 /*
1747 * framebuffer handling
1748 */
1749
1750 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1751 const struct pipe_framebuffer_state *state, int cb)
1752 {
1753 struct r600_texture *rtex;
1754 struct r600_surface *surf;
1755 unsigned level = state->cbufs[cb]->u.tex.level;
1756 unsigned pitch, slice;
1757 unsigned color_info, color_attrib;
1758 unsigned tile_mode_index;
1759 unsigned format, swap, ntype, endian;
1760 uint64_t offset;
1761 const struct util_format_description *desc;
1762 int i;
1763 unsigned blend_clamp = 0, blend_bypass = 0;
1764 unsigned max_comp_size;
1765
1766 surf = (struct r600_surface *)state->cbufs[cb];
1767 rtex = (struct r600_texture*)state->cbufs[cb]->texture;
1768
1769 offset = rtex->surface.level[level].offset;
1770 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1771 offset += rtex->surface.level[level].slice_size *
1772 state->cbufs[cb]->u.tex.first_layer;
1773 }
1774 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1775 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1776 if (slice) {
1777 slice = slice - 1;
1778 }
1779
1780 tile_mode_index = si_tile_mode_index(rtex, level, false);
1781
1782 desc = util_format_description(surf->base.format);
1783 for (i = 0; i < 4; i++) {
1784 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1785 break;
1786 }
1787 }
1788 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1789 ntype = V_028C70_NUMBER_FLOAT;
1790 } else {
1791 ntype = V_028C70_NUMBER_UNORM;
1792 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1793 ntype = V_028C70_NUMBER_SRGB;
1794 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1795 if (desc->channel[i].pure_integer) {
1796 ntype = V_028C70_NUMBER_SINT;
1797 } else {
1798 assert(desc->channel[i].normalized);
1799 ntype = V_028C70_NUMBER_SNORM;
1800 }
1801 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1802 if (desc->channel[i].pure_integer) {
1803 ntype = V_028C70_NUMBER_UINT;
1804 } else {
1805 assert(desc->channel[i].normalized);
1806 ntype = V_028C70_NUMBER_UNORM;
1807 }
1808 }
1809 }
1810
1811 format = si_translate_colorformat(surf->base.format);
1812 if (format == V_028C70_COLOR_INVALID) {
1813 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1814 }
1815 assert(format != V_028C70_COLOR_INVALID);
1816 swap = si_translate_colorswap(surf->base.format);
1817 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1818 endian = V_028C70_ENDIAN_NONE;
1819 } else {
1820 endian = si_colorformat_endian_swap(format);
1821 }
1822
1823 /* blend clamp should be set for all NORM/SRGB types */
1824 if (ntype == V_028C70_NUMBER_UNORM ||
1825 ntype == V_028C70_NUMBER_SNORM ||
1826 ntype == V_028C70_NUMBER_SRGB)
1827 blend_clamp = 1;
1828
1829 /* set blend bypass according to docs if SINT/UINT or
1830 8/24 COLOR variants */
1831 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1832 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1833 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1834 blend_clamp = 0;
1835 blend_bypass = 1;
1836 }
1837
1838 color_info = S_028C70_FORMAT(format) |
1839 S_028C70_COMP_SWAP(swap) |
1840 S_028C70_BLEND_CLAMP(blend_clamp) |
1841 S_028C70_BLEND_BYPASS(blend_bypass) |
1842 S_028C70_NUMBER_TYPE(ntype) |
1843 S_028C70_ENDIAN(endian);
1844
1845 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1846 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1847
1848 if (rtex->resource.b.b.nr_samples > 1) {
1849 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1850 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1851 S_028C74_NUM_FRAGMENTS(log_samples);
1852 }
1853
1854 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1855 offset >>= 8;
1856
1857 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1858 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1859 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1860 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1861 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1862
1863 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1864 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1865 } else {
1866 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1867 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1868 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1869 }
1870 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1871 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1872
1873 /* set CB_COLOR1_INFO for possible dual-src blending */
1874 if (state->nr_cbufs == 1) {
1875 assert(cb == 0);
1876 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + 1 * 0x3C, color_info);
1877 }
1878
1879 /* Determine pixel shader export format */
1880 max_comp_size = si_colorformat_max_comp_size(format);
1881 if (ntype == V_028C70_NUMBER_SRGB ||
1882 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1883 max_comp_size <= 10) ||
1884 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1885 rctx->export_16bpc |= 1 << cb;
1886 /* set SPI_SHADER_COL_FORMAT for possible dual-src blending */
1887 if (state->nr_cbufs == 1)
1888 rctx->export_16bpc |= 1 << 1;
1889 }
1890 }
1891
1892 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1893 const struct pipe_framebuffer_state *state)
1894 {
1895 struct r600_screen *rscreen = rctx->screen;
1896 struct r600_texture *rtex;
1897 struct r600_surface *surf;
1898 unsigned level, pitch, slice, format, tile_mode_index, array_mode;
1899 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1900 uint32_t z_info, s_info, db_depth_info;
1901 uint64_t z_offs, s_offs;
1902
1903 if (state->zsbuf == NULL) {
1904 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1905 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1906 return;
1907 }
1908
1909 surf = (struct r600_surface *)state->zsbuf;
1910 level = surf->base.u.tex.level;
1911 rtex = (struct r600_texture*)surf->base.texture;
1912
1913 format = si_translate_dbformat(rtex->real_format);
1914
1915 if (format == V_028040_Z_INVALID) {
1916 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
1917 }
1918 assert(format != V_028040_Z_INVALID);
1919
1920 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1921 z_offs += rtex->surface.level[level].offset;
1922 s_offs += rtex->surface.stencil_level[level].offset;
1923
1924 z_offs >>= 8;
1925 s_offs >>= 8;
1926
1927 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1928 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1929 if (slice) {
1930 slice = slice - 1;
1931 }
1932
1933 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1934
1935 z_info = S_028040_FORMAT(format);
1936 if (rtex->resource.b.b.nr_samples > 1) {
1937 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1938 }
1939
1940 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1941 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1942 else
1943 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1944
1945 if (rctx->chip_class >= CIK) {
1946 switch (rtex->surface.level[level].mode) {
1947 case RADEON_SURF_MODE_2D:
1948 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1949 break;
1950 case RADEON_SURF_MODE_1D:
1951 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1952 case RADEON_SURF_MODE_LINEAR:
1953 default:
1954 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1955 break;
1956 }
1957 tile_split = rtex->surface.tile_split;
1958 stile_split = rtex->surface.stencil_tile_split;
1959 macro_aspect = rtex->surface.mtilea;
1960 bankw = rtex->surface.bankw;
1961 bankh = rtex->surface.bankh;
1962 tile_split = cik_tile_split(tile_split);
1963 stile_split = cik_tile_split(stile_split);
1964 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1965 bankw = cik_bank_wh(bankw);
1966 bankh = cik_bank_wh(bankh);
1967 nbanks = cik_num_banks(rscreen->tiling_info.num_banks);
1968 pipe_config = cik_db_pipe_config(rscreen->info.r600_num_tile_pipes,
1969 rscreen->info.r600_num_backends);
1970
1971 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1972 S_02803C_PIPE_CONFIG(pipe_config) |
1973 S_02803C_BANK_WIDTH(bankw) |
1974 S_02803C_BANK_HEIGHT(bankh) |
1975 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1976 S_02803C_NUM_BANKS(nbanks);
1977 z_info |= S_028040_TILE_SPLIT(tile_split);
1978 s_info |= S_028044_TILE_SPLIT(stile_split);
1979 } else {
1980 tile_mode_index = si_tile_mode_index(rtex, level, false);
1981 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1982 tile_mode_index = si_tile_mode_index(rtex, level, true);
1983 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1984 }
1985
1986 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1987 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1988 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1989
1990 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, db_depth_info);
1991 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1992 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1993
1994 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1995 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1996 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1997 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1998 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1999
2000 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
2001 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
2002 }
2003
2004 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y) \
2005 (((s0x) & 0xf) | (((s0y) & 0xf) << 4) | \
2006 (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) | \
2007 (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) | \
2008 (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
2009
2010 /* 2xMSAA
2011 * There are two locations (-4, 4), (4, -4). */
2012 static uint32_t sample_locs_2x[] = {
2013 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2014 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2015 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2016 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
2017 };
2018 static unsigned max_dist_2x = 4;
2019 /* 4xMSAA
2020 * There are 4 locations: (-2, -2), (2, 2), (-6, 6), (6, -6). */
2021 static uint32_t sample_locs_4x[] = {
2022 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2023 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2024 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2025 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
2026 };
2027 static unsigned max_dist_4x = 6;
2028 /* Cayman/SI 8xMSAA */
2029 static uint32_t cm_sample_locs_8x[] = {
2030 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2031 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2032 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2033 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
2034 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2035 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2036 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2037 FILL_SREG( 6, 0, 0, 0, -5, 3, 4, 4),
2038 };
2039 static unsigned cm_max_dist_8x = 8;
2040 /* Cayman/SI 16xMSAA */
2041 static uint32_t cm_sample_locs_16x[] = {
2042 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2043 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2044 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2045 FILL_SREG(-7, -3, 7, 3, 1, -5, -5, 5),
2046 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2047 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2048 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2049 FILL_SREG(-3, -7, 3, 7, 5, -1, -1, 1),
2050 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2051 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2052 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2053 FILL_SREG(-8, -6, 4, 2, 2, -8, -2, 6),
2054 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2055 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2056 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2057 FILL_SREG(-4, -2, 0, 4, 6, -4, -6, 0),
2058 };
2059 static unsigned cm_max_dist_16x = 8;
2060
2061 static void si_get_sample_position(struct pipe_context *ctx,
2062 unsigned sample_count,
2063 unsigned sample_index,
2064 float *out_value)
2065 {
2066 int offset, index;
2067 struct {
2068 int idx:4;
2069 } val;
2070 switch (sample_count) {
2071 case 1:
2072 default:
2073 out_value[0] = out_value[1] = 0.5;
2074 break;
2075 case 2:
2076 offset = 4 * (sample_index * 2);
2077 val.idx = (sample_locs_2x[0] >> offset) & 0xf;
2078 out_value[0] = (float)(val.idx + 8) / 16.0f;
2079 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf;
2080 out_value[1] = (float)(val.idx + 8) / 16.0f;
2081 break;
2082 case 4:
2083 offset = 4 * (sample_index * 2);
2084 val.idx = (sample_locs_4x[0] >> offset) & 0xf;
2085 out_value[0] = (float)(val.idx + 8) / 16.0f;
2086 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf;
2087 out_value[1] = (float)(val.idx + 8) / 16.0f;
2088 break;
2089 case 8:
2090 offset = 4 * (sample_index % 4 * 2);
2091 index = (sample_index / 4) * 4;
2092 val.idx = (cm_sample_locs_8x[index] >> offset) & 0xf;
2093 out_value[0] = (float)(val.idx + 8) / 16.0f;
2094 val.idx = (cm_sample_locs_8x[index] >> (offset + 4)) & 0xf;
2095 out_value[1] = (float)(val.idx + 8) / 16.0f;
2096 break;
2097 case 16:
2098 offset = 4 * (sample_index % 4 * 2);
2099 index = (sample_index / 4) * 4;
2100 val.idx = (cm_sample_locs_16x[index] >> offset) & 0xf;
2101 out_value[0] = (float)(val.idx + 8) / 16.0f;
2102 val.idx = (cm_sample_locs_16x[index] >> (offset + 4)) & 0xf;
2103 out_value[1] = (float)(val.idx + 8) / 16.0f;
2104 break;
2105 }
2106 }
2107
2108 static void si_set_msaa_state(struct r600_context *rctx, struct si_pm4_state *pm4, int nr_samples)
2109 {
2110 unsigned max_dist = 0;
2111
2112 switch (nr_samples) {
2113 default:
2114 nr_samples = 0;
2115 break;
2116 case 2:
2117 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_2x[0]);
2118 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_2x[1]);
2119 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_2x[2]);
2120 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_2x[3]);
2121 max_dist = max_dist_2x;
2122 break;
2123 case 4:
2124 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, sample_locs_4x[0]);
2125 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, sample_locs_4x[1]);
2126 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, sample_locs_4x[2]);
2127 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, sample_locs_4x[3]);
2128 max_dist = max_dist_4x;
2129 break;
2130 case 8:
2131 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_8x[0]);
2132 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_8x[4]);
2133 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, 0);
2134 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, 0);
2135 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_8x[1]);
2136 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_8x[5]);
2137 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, 0);
2138 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, 0);
2139 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_8x[2]);
2140 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_8x[6]);
2141 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, 0);
2142 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, 0);
2143 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_8x[3]);
2144 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_8x[7]);
2145 max_dist = cm_max_dist_8x;
2146 break;
2147 case 16:
2148 si_pm4_set_reg(pm4, R_028BF8_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0, cm_sample_locs_16x[0]);
2149 si_pm4_set_reg(pm4, R_028BFC_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_1, cm_sample_locs_16x[4]);
2150 si_pm4_set_reg(pm4, R_028C00_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_2, cm_sample_locs_16x[8]);
2151 si_pm4_set_reg(pm4, R_028C04_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_3, cm_sample_locs_16x[12]);
2152 si_pm4_set_reg(pm4, R_028C08_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_0, cm_sample_locs_16x[1]);
2153 si_pm4_set_reg(pm4, R_028C0C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_1, cm_sample_locs_16x[5]);
2154 si_pm4_set_reg(pm4, R_028C10_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_2, cm_sample_locs_16x[9]);
2155 si_pm4_set_reg(pm4, R_028C14_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y0_3, cm_sample_locs_16x[13]);
2156 si_pm4_set_reg(pm4, R_028C18_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_0, cm_sample_locs_16x[2]);
2157 si_pm4_set_reg(pm4, R_028C1C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_1, cm_sample_locs_16x[6]);
2158 si_pm4_set_reg(pm4, R_028C20_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_2, cm_sample_locs_16x[10]);
2159 si_pm4_set_reg(pm4, R_028C24_PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y1_3, cm_sample_locs_16x[14]);
2160 si_pm4_set_reg(pm4, R_028C28_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_0, cm_sample_locs_16x[3]);
2161 si_pm4_set_reg(pm4, R_028C2C_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_1, cm_sample_locs_16x[7]);
2162 si_pm4_set_reg(pm4, R_028C30_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_2, cm_sample_locs_16x[11]);
2163 si_pm4_set_reg(pm4, R_028C34_PA_SC_AA_SAMPLE_LOCS_PIXEL_X1Y1_3, cm_sample_locs_16x[15]);
2164 max_dist = cm_max_dist_16x;
2165 break;
2166 }
2167
2168 if (nr_samples > 1) {
2169 unsigned log_samples = util_logbase2(nr_samples);
2170
2171 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL,
2172 S_028BDC_LAST_PIXEL(1) |
2173 S_028BDC_EXPAND_LINE_WIDTH(1));
2174 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG,
2175 S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
2176 S_028BE0_MAX_SAMPLE_DIST(max_dist) |
2177 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples));
2178
2179 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2180 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
2181 S_028804_PS_ITER_SAMPLES(log_samples) |
2182 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
2183 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
2184 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2185 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2186 } else {
2187 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, S_028BDC_LAST_PIXEL(1));
2188 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0);
2189
2190 si_pm4_set_reg(pm4, R_028804_DB_EQAA,
2191 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
2192 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
2193 }
2194 }
2195
2196 static void si_set_framebuffer_state(struct pipe_context *ctx,
2197 const struct pipe_framebuffer_state *state)
2198 {
2199 struct r600_context *rctx = (struct r600_context *)ctx;
2200 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2201 uint32_t tl, br;
2202 int tl_x, tl_y, br_x, br_y, nr_samples;
2203
2204 if (pm4 == NULL)
2205 return;
2206
2207 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
2208
2209 if (state->zsbuf)
2210 si_pm4_inval_zsbuf_cache(pm4);
2211
2212 util_copy_framebuffer_state(&rctx->framebuffer, state);
2213
2214 /* build states */
2215 rctx->export_16bpc = 0;
2216 for (int i = 0; i < state->nr_cbufs; i++) {
2217 si_cb(rctx, pm4, state, i);
2218 }
2219 assert(!(rctx->export_16bpc & ~0xff));
2220 si_db(rctx, pm4, state);
2221
2222 tl_x = 0;
2223 tl_y = 0;
2224 br_x = state->width;
2225 br_y = state->height;
2226
2227 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
2228 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
2229
2230 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
2231 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
2232 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
2233 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
2234 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
2235 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
2236 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
2237 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
2238 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
2239 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2240
2241 if (state->nr_cbufs)
2242 nr_samples = state->cbufs[0]->texture->nr_samples;
2243 else if (state->zsbuf)
2244 nr_samples = state->zsbuf->texture->nr_samples;
2245 else
2246 nr_samples = 0;
2247
2248 si_set_msaa_state(rctx, pm4, nr_samples);
2249 rctx->fb_log_samples = util_logbase2(nr_samples);
2250
2251 si_pm4_set_state(rctx, framebuffer, pm4);
2252 si_update_fb_rs_state(rctx);
2253 si_update_fb_blend_state(rctx);
2254 }
2255
2256 /*
2257 * shaders
2258 */
2259
2260 /* Compute the key for the hw shader variant */
2261 static INLINE void si_shader_selector_key(struct pipe_context *ctx,
2262 struct si_pipe_shader_selector *sel,
2263 union si_shader_key *key)
2264 {
2265 struct r600_context *rctx = (struct r600_context *)ctx;
2266 memset(key, 0, sizeof(*key));
2267
2268 if (sel->type == PIPE_SHADER_VERTEX) {
2269 unsigned i;
2270 if (!rctx->vertex_elements)
2271 return;
2272
2273 for (i = 0; i < rctx->vertex_elements->count; ++i)
2274 key->vs.instance_divisors[i] = rctx->vertex_elements->elements[i].instance_divisor;
2275
2276 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf0)
2277 key->vs.ucps_enabled |= 0x2;
2278 if (rctx->queued.named.rasterizer->clip_plane_enable & 0xf)
2279 key->vs.ucps_enabled |= 0x1;
2280 } else if (sel->type == PIPE_SHADER_FRAGMENT) {
2281 if (sel->fs_write_all)
2282 key->ps.nr_cbufs = rctx->framebuffer.nr_cbufs;
2283 key->ps.export_16bpc = rctx->export_16bpc;
2284 if (rctx->queued.named.rasterizer) {
2285 key->ps.color_two_side = rctx->queued.named.rasterizer->two_side;
2286 key->ps.flatshade = rctx->queued.named.rasterizer->flatshade;
2287 }
2288 if (rctx->queued.named.dsa) {
2289 key->ps.alpha_func = rctx->queued.named.dsa->alpha_func;
2290 key->ps.alpha_ref = rctx->queued.named.dsa->alpha_ref;
2291 } else {
2292 key->ps.alpha_func = PIPE_FUNC_ALWAYS;
2293 }
2294 }
2295 }
2296
2297 /* Select the hw shader variant depending on the current state.
2298 * (*dirty) is set to 1 if current variant was changed */
2299 int si_shader_select(struct pipe_context *ctx,
2300 struct si_pipe_shader_selector *sel,
2301 unsigned *dirty)
2302 {
2303 union si_shader_key key;
2304 struct si_pipe_shader * shader = NULL;
2305 int r;
2306
2307 si_shader_selector_key(ctx, sel, &key);
2308
2309 /* Check if we don't need to change anything.
2310 * This path is also used for most shaders that don't need multiple
2311 * variants, it will cost just a computation of the key and this
2312 * test. */
2313 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
2314 return 0;
2315 }
2316
2317 /* lookup if we have other variants in the list */
2318 if (sel->num_shaders > 1) {
2319 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
2320
2321 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
2322 p = c;
2323 c = c->next_variant;
2324 }
2325
2326 if (c) {
2327 p->next_variant = c->next_variant;
2328 shader = c;
2329 }
2330 }
2331
2332 if (unlikely(!shader)) {
2333 shader = CALLOC(1, sizeof(struct si_pipe_shader));
2334 shader->selector = sel;
2335 shader->key = key;
2336
2337 r = si_pipe_shader_create(ctx, shader);
2338 if (unlikely(r)) {
2339 R600_ERR("Failed to build shader variant (type=%u) %d\n",
2340 sel->type, r);
2341 sel->current = NULL;
2342 FREE(shader);
2343 return r;
2344 }
2345
2346 /* We don't know the value of fs_write_all property until we built
2347 * at least one variant, so we may need to recompute the key (include
2348 * rctx->framebuffer.nr_cbufs) after building first variant. */
2349 if (sel->type == PIPE_SHADER_FRAGMENT &&
2350 sel->num_shaders == 0 &&
2351 shader->shader.fs_write_all) {
2352 sel->fs_write_all = 1;
2353 si_shader_selector_key(ctx, sel, &shader->key);
2354 }
2355
2356 sel->num_shaders++;
2357 }
2358
2359 if (dirty)
2360 *dirty = 1;
2361
2362 shader->next_variant = sel->current;
2363 sel->current = shader;
2364
2365 return 0;
2366 }
2367
2368 static void *si_create_shader_state(struct pipe_context *ctx,
2369 const struct pipe_shader_state *state,
2370 unsigned pipe_shader_type)
2371 {
2372 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
2373 int r;
2374
2375 sel->type = pipe_shader_type;
2376 sel->tokens = tgsi_dup_tokens(state->tokens);
2377 sel->so = state->stream_output;
2378
2379 r = si_shader_select(ctx, sel, NULL);
2380 if (r) {
2381 free(sel);
2382 return NULL;
2383 }
2384
2385 return sel;
2386 }
2387
2388 static void *si_create_fs_state(struct pipe_context *ctx,
2389 const struct pipe_shader_state *state)
2390 {
2391 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
2392 }
2393
2394 static void *si_create_vs_state(struct pipe_context *ctx,
2395 const struct pipe_shader_state *state)
2396 {
2397 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2398 }
2399
2400 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2401 {
2402 struct r600_context *rctx = (struct r600_context *)ctx;
2403 struct si_pipe_shader_selector *sel = state;
2404
2405 if (rctx->vs_shader == sel)
2406 return;
2407
2408 rctx->vs_shader = sel;
2409
2410 if (sel && sel->current)
2411 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2412 else
2413 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2414 }
2415
2416 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2417 {
2418 struct r600_context *rctx = (struct r600_context *)ctx;
2419 struct si_pipe_shader_selector *sel = state;
2420
2421 if (rctx->ps_shader == sel)
2422 return;
2423
2424 rctx->ps_shader = sel;
2425
2426 if (sel && sel->current)
2427 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2428 else
2429 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2430 }
2431
2432 static void si_delete_shader_selector(struct pipe_context *ctx,
2433 struct si_pipe_shader_selector *sel)
2434 {
2435 struct r600_context *rctx = (struct r600_context *)ctx;
2436 struct si_pipe_shader *p = sel->current, *c;
2437
2438 while (p) {
2439 c = p->next_variant;
2440 si_pm4_delete_state(rctx, vs, p->pm4);
2441 si_pipe_shader_destroy(ctx, p);
2442 free(p);
2443 p = c;
2444 }
2445
2446 free(sel->tokens);
2447 free(sel);
2448 }
2449
2450 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2451 {
2452 struct r600_context *rctx = (struct r600_context *)ctx;
2453 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2454
2455 if (rctx->vs_shader == sel) {
2456 rctx->vs_shader = NULL;
2457 }
2458
2459 si_delete_shader_selector(ctx, sel);
2460 }
2461
2462 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2463 {
2464 struct r600_context *rctx = (struct r600_context *)ctx;
2465 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2466
2467 if (rctx->ps_shader == sel) {
2468 rctx->ps_shader = NULL;
2469 }
2470
2471 si_delete_shader_selector(ctx, sel);
2472 }
2473
2474 /*
2475 * Samplers
2476 */
2477
2478 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2479 struct pipe_resource *texture,
2480 const struct pipe_sampler_view *state)
2481 {
2482 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2483 struct r600_texture *tmp = (struct r600_texture*)texture;
2484 const struct util_format_description *desc;
2485 unsigned format, num_format;
2486 uint32_t pitch = 0;
2487 unsigned char state_swizzle[4], swizzle[4];
2488 unsigned height, depth, width;
2489 enum pipe_format pipe_format = state->format;
2490 struct radeon_surface_level *surflevel;
2491 int first_non_void;
2492 uint64_t va;
2493
2494 if (view == NULL)
2495 return NULL;
2496
2497 /* initialize base object */
2498 view->base = *state;
2499 view->base.texture = NULL;
2500 pipe_reference(NULL, &texture->reference);
2501 view->base.texture = texture;
2502 view->base.reference.count = 1;
2503 view->base.context = ctx;
2504
2505 state_swizzle[0] = state->swizzle_r;
2506 state_swizzle[1] = state->swizzle_g;
2507 state_swizzle[2] = state->swizzle_b;
2508 state_swizzle[3] = state->swizzle_a;
2509
2510 surflevel = tmp->surface.level;
2511
2512 /* Texturing with separate depth and stencil. */
2513 if (tmp->is_depth && !tmp->is_flushing_texture) {
2514 switch (pipe_format) {
2515 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2516 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2517 break;
2518 case PIPE_FORMAT_X8Z24_UNORM:
2519 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2520 /* Z24 is always stored like this. */
2521 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2522 break;
2523 case PIPE_FORMAT_X24S8_UINT:
2524 case PIPE_FORMAT_S8X24_UINT:
2525 case PIPE_FORMAT_X32_S8X24_UINT:
2526 pipe_format = PIPE_FORMAT_S8_UINT;
2527 surflevel = tmp->surface.stencil_level;
2528 break;
2529 default:;
2530 }
2531 }
2532
2533 desc = util_format_description(pipe_format);
2534
2535 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2536 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2537 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2538
2539 switch (pipe_format) {
2540 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2541 case PIPE_FORMAT_X24S8_UINT:
2542 case PIPE_FORMAT_X32_S8X24_UINT:
2543 case PIPE_FORMAT_X8Z24_UNORM:
2544 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2545 break;
2546 default:
2547 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2548 }
2549 } else {
2550 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2551 }
2552
2553 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2554
2555 switch (pipe_format) {
2556 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2557 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2558 break;
2559 default:
2560 if (first_non_void < 0) {
2561 if (util_format_is_compressed(pipe_format)) {
2562 switch (pipe_format) {
2563 case PIPE_FORMAT_DXT1_SRGB:
2564 case PIPE_FORMAT_DXT1_SRGBA:
2565 case PIPE_FORMAT_DXT3_SRGBA:
2566 case PIPE_FORMAT_DXT5_SRGBA:
2567 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2568 break;
2569 case PIPE_FORMAT_RGTC1_SNORM:
2570 case PIPE_FORMAT_LATC1_SNORM:
2571 case PIPE_FORMAT_RGTC2_SNORM:
2572 case PIPE_FORMAT_LATC2_SNORM:
2573 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2574 break;
2575 default:
2576 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2577 break;
2578 }
2579 } else {
2580 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2581 }
2582 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2583 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2584 } else {
2585 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2586
2587 switch (desc->channel[first_non_void].type) {
2588 case UTIL_FORMAT_TYPE_FLOAT:
2589 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2590 break;
2591 case UTIL_FORMAT_TYPE_SIGNED:
2592 if (desc->channel[first_non_void].normalized)
2593 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2594 else if (desc->channel[first_non_void].pure_integer)
2595 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2596 else
2597 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2598 break;
2599 case UTIL_FORMAT_TYPE_UNSIGNED:
2600 if (desc->channel[first_non_void].normalized)
2601 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2602 else if (desc->channel[first_non_void].pure_integer)
2603 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2604 else
2605 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2606 }
2607 }
2608 }
2609
2610 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2611 if (format == ~0) {
2612 format = 0;
2613 }
2614
2615 view->resource = &tmp->resource;
2616
2617 /* not supported any more */
2618 //endian = si_colorformat_endian_swap(format);
2619
2620 width = surflevel[0].npix_x;
2621 height = surflevel[0].npix_y;
2622 depth = surflevel[0].npix_z;
2623 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2624
2625 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2626 height = 1;
2627 depth = texture->array_size;
2628 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2629 depth = texture->array_size;
2630 }
2631
2632 va = r600_resource_va(ctx->screen, texture);
2633 va += surflevel[0].offset;
2634 view->state[0] = va >> 8;
2635 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2636 S_008F14_DATA_FORMAT(format) |
2637 S_008F14_NUM_FORMAT(num_format));
2638 view->state[2] = (S_008F18_WIDTH(width - 1) |
2639 S_008F18_HEIGHT(height - 1));
2640 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2641 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2642 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2643 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2644 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2645 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2646 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2647 S_008F1C_POW2_PAD(texture->last_level > 0) |
2648 S_008F1C_TYPE(si_tex_dim(texture->target)));
2649 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2650 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2651 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2652 view->state[6] = 0;
2653 view->state[7] = 0;
2654
2655 return &view->base;
2656 }
2657
2658 static void si_sampler_view_destroy(struct pipe_context *ctx,
2659 struct pipe_sampler_view *state)
2660 {
2661 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2662
2663 pipe_resource_reference(&state->texture, NULL);
2664 FREE(resource);
2665 }
2666
2667 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2668 {
2669 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2670 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2671 (linear_filter &&
2672 (wrap == PIPE_TEX_WRAP_CLAMP ||
2673 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2674 }
2675
2676 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2677 {
2678 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2679 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2680
2681 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2682 state->border_color.ui[2] || state->border_color.ui[3]) &&
2683 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2684 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2685 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2686 }
2687
2688 static void *si_create_sampler_state(struct pipe_context *ctx,
2689 const struct pipe_sampler_state *state)
2690 {
2691 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2692 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2693 unsigned border_color_type;
2694
2695 if (rstate == NULL) {
2696 return NULL;
2697 }
2698
2699 if (sampler_state_needs_border_color(state))
2700 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2701 else
2702 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2703
2704 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2705 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2706 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2707 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2708 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2709 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2710 aniso_flag_offset << 16 | /* XXX */
2711 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2712 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2713 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2714 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2715 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2716 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2717 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2718 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2719
2720 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2721 memcpy(rstate->border_color, state->border_color.ui,
2722 sizeof(rstate->border_color));
2723 }
2724
2725 return rstate;
2726 }
2727
2728 static struct si_pm4_state *si_set_sampler_views(struct r600_context *rctx,
2729 unsigned shader, unsigned count,
2730 struct pipe_sampler_view **views)
2731 {
2732 struct r600_textures_info *samplers = &rctx->samplers[shader];
2733 struct si_pipe_sampler_view **rviews = (struct si_pipe_sampler_view **)views;
2734 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2735 int i;
2736
2737 si_pm4_inval_texture_cache(pm4);
2738
2739 for (i = 0; i < count; i++) {
2740 if (views[i]) {
2741 struct r600_texture *rtex =
2742 (struct r600_texture*)views[i]->texture;
2743
2744 if (rtex->is_depth && !rtex->is_flushing_texture) {
2745 samplers->depth_texture_mask |= 1 << i;
2746 } else {
2747 samplers->depth_texture_mask &= ~(1 << i);
2748 }
2749
2750 si_set_sampler_view(rctx, shader, i, views[i], rviews[i]->state);
2751 } else {
2752 samplers->depth_texture_mask &= ~(1 << i);
2753 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2754 }
2755 }
2756 for (; i < samplers->n_views; i++) {
2757 si_set_sampler_view(rctx, shader, i, NULL, NULL);
2758 }
2759
2760 samplers->n_views = count;
2761 return pm4;
2762 }
2763
2764 static void si_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
2765 struct pipe_sampler_view **views)
2766 {
2767 struct r600_context *rctx = (struct r600_context *)ctx;
2768 struct si_pm4_state *pm4;
2769
2770 pm4 = si_set_sampler_views(rctx, PIPE_SHADER_VERTEX, count, views);
2771 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2772 }
2773
2774 static void si_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
2775 struct pipe_sampler_view **views)
2776 {
2777 struct r600_context *rctx = (struct r600_context *)ctx;
2778 struct si_pm4_state *pm4;
2779
2780 pm4 = si_set_sampler_views(rctx, PIPE_SHADER_FRAGMENT, count, views);
2781 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2782 }
2783
2784 static struct si_pm4_state *si_bind_sampler_states(struct r600_context *rctx, unsigned count,
2785 void **states,
2786 struct r600_textures_info *samplers,
2787 unsigned user_data_reg)
2788 {
2789 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2790 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2791 uint32_t *border_color_table = NULL;
2792 int i, j;
2793
2794 if (!count)
2795 goto out;
2796
2797 si_pm4_inval_texture_cache(pm4);
2798
2799 si_pm4_sh_data_begin(pm4);
2800 for (i = 0; i < count; i++) {
2801 if (rstates[i] &&
2802 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2803 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2804 if (!rctx->border_color_table ||
2805 ((rctx->border_color_offset + count - i) &
2806 C_008F3C_BORDER_COLOR_PTR)) {
2807 si_resource_reference(&rctx->border_color_table, NULL);
2808 rctx->border_color_offset = 0;
2809
2810 rctx->border_color_table =
2811 si_resource_create_custom(&rctx->screen->screen,
2812 PIPE_USAGE_STAGING,
2813 4096 * 4 * 4);
2814 }
2815
2816 if (!border_color_table) {
2817 border_color_table =
2818 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2819 rctx->cs,
2820 PIPE_TRANSFER_WRITE |
2821 PIPE_TRANSFER_UNSYNCHRONIZED);
2822 }
2823
2824 for (j = 0; j < 4; j++) {
2825 border_color_table[4 * rctx->border_color_offset + j] =
2826 util_le32_to_cpu(rstates[i]->border_color[j]);
2827 }
2828
2829 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2830 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2831 }
2832
2833 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2834 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2835 }
2836 }
2837 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2838
2839 if (border_color_table) {
2840 uint64_t va_offset =
2841 r600_resource_va(&rctx->screen->screen,
2842 (void*)rctx->border_color_table);
2843
2844 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2845 if (rctx->chip_class >= CIK)
2846 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2847 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2848 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2849 }
2850
2851 memcpy(samplers->samplers, states, sizeof(void*) * count);
2852
2853 out:
2854 samplers->n_samplers = count;
2855 return pm4;
2856 }
2857
2858 static void si_bind_vs_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2859 {
2860 struct r600_context *rctx = (struct r600_context *)ctx;
2861 struct si_pm4_state *pm4;
2862
2863 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_VERTEX],
2864 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2865 si_pm4_set_state(rctx, vs_sampler, pm4);
2866 }
2867
2868 static void si_bind_ps_sampler_states(struct pipe_context *ctx, unsigned count, void **states)
2869 {
2870 struct r600_context *rctx = (struct r600_context *)ctx;
2871 struct si_pm4_state *pm4;
2872
2873 pm4 = si_bind_sampler_states(rctx, count, states, &rctx->samplers[PIPE_SHADER_FRAGMENT],
2874 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2875 si_pm4_set_state(rctx, ps_sampler, pm4);
2876 }
2877
2878 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2879 {
2880 struct r600_context *rctx = (struct r600_context *)ctx;
2881 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
2882 uint16_t mask = sample_mask;
2883
2884 if (pm4 == NULL)
2885 return;
2886
2887 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2888 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2889
2890 si_pm4_set_state(rctx, sample_mask, pm4);
2891 }
2892
2893 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2894 {
2895 free(state);
2896 }
2897
2898 /*
2899 * Constants
2900 */
2901 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2902 struct pipe_constant_buffer *input)
2903 {
2904 struct r600_context *rctx = (struct r600_context *)ctx;
2905 struct r600_constbuf_state *state = &rctx->constbuf_state[shader];
2906 struct pipe_constant_buffer *cb;
2907 const uint8_t *ptr;
2908
2909 /* Note that the state tracker can unbind constant buffers by
2910 * passing NULL here.
2911 */
2912 if (unlikely(!input || (!input->buffer && !input->user_buffer))) {
2913 state->enabled_mask &= ~(1 << index);
2914 state->dirty_mask &= ~(1 << index);
2915 pipe_resource_reference(&state->cb[index].buffer, NULL);
2916 return;
2917 }
2918
2919 cb = &state->cb[index];
2920 cb->buffer_size = input->buffer_size;
2921
2922 ptr = input->user_buffer;
2923
2924 if (ptr) {
2925 r600_upload_const_buffer(rctx,
2926 (struct si_resource**)&cb->buffer, ptr,
2927 cb->buffer_size, &cb->buffer_offset);
2928 } else {
2929 /* Setup the hw buffer. */
2930 cb->buffer_offset = input->buffer_offset;
2931 pipe_resource_reference(&cb->buffer, input->buffer);
2932 }
2933
2934 state->enabled_mask |= 1 << index;
2935 state->dirty_mask |= 1 << index;
2936 }
2937
2938 /*
2939 * Vertex elements & buffers
2940 */
2941
2942 static void *si_create_vertex_elements(struct pipe_context *ctx,
2943 unsigned count,
2944 const struct pipe_vertex_element *elements)
2945 {
2946 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2947 int i;
2948
2949 assert(count < PIPE_MAX_ATTRIBS);
2950 if (!v)
2951 return NULL;
2952
2953 v->count = count;
2954 for (i = 0; i < count; ++i) {
2955 const struct util_format_description *desc;
2956 unsigned data_format, num_format;
2957 int first_non_void;
2958
2959 desc = util_format_description(elements[i].src_format);
2960 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2961 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2962 desc, first_non_void);
2963
2964 switch (desc->channel[first_non_void].type) {
2965 case UTIL_FORMAT_TYPE_FIXED:
2966 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2967 break;
2968 case UTIL_FORMAT_TYPE_SIGNED:
2969 if (desc->channel[first_non_void].normalized)
2970 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2971 else if (desc->channel[first_non_void].pure_integer)
2972 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
2973 else
2974 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
2975 break;
2976 case UTIL_FORMAT_TYPE_UNSIGNED:
2977 if (desc->channel[first_non_void].normalized)
2978 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2979 else if (desc->channel[first_non_void].pure_integer)
2980 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
2981 else
2982 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
2983 break;
2984 case UTIL_FORMAT_TYPE_FLOAT:
2985 default:
2986 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2987 }
2988
2989 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2990 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2991 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2992 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2993 S_008F0C_NUM_FORMAT(num_format) |
2994 S_008F0C_DATA_FORMAT(data_format);
2995 }
2996 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2997
2998 return v;
2999 }
3000
3001 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3002 {
3003 struct r600_context *rctx = (struct r600_context *)ctx;
3004 struct si_vertex_element *v = (struct si_vertex_element*)state;
3005
3006 rctx->vertex_elements = v;
3007 }
3008
3009 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3010 {
3011 struct r600_context *rctx = (struct r600_context *)ctx;
3012
3013 if (rctx->vertex_elements == state)
3014 rctx->vertex_elements = NULL;
3015 FREE(state);
3016 }
3017
3018 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
3019 const struct pipe_vertex_buffer *buffers)
3020 {
3021 struct r600_context *rctx = (struct r600_context *)ctx;
3022
3023 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
3024 }
3025
3026 static void si_set_index_buffer(struct pipe_context *ctx,
3027 const struct pipe_index_buffer *ib)
3028 {
3029 struct r600_context *rctx = (struct r600_context *)ctx;
3030
3031 if (ib) {
3032 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
3033 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
3034 } else {
3035 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
3036 }
3037 }
3038
3039 /*
3040 * Misc
3041 */
3042 static void si_set_polygon_stipple(struct pipe_context *ctx,
3043 const struct pipe_poly_stipple *state)
3044 {
3045 }
3046
3047 static void si_texture_barrier(struct pipe_context *ctx)
3048 {
3049 struct r600_context *rctx = (struct r600_context *)ctx;
3050 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3051
3052 if (pm4 == NULL)
3053 return;
3054
3055 si_pm4_inval_texture_cache(pm4);
3056 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
3057 si_pm4_set_state(rctx, texture_barrier, pm4);
3058 }
3059
3060 static void *si_create_resolve_blend(struct r600_context *rctx)
3061 {
3062 struct pipe_blend_state blend;
3063
3064 memset(&blend, 0, sizeof(blend));
3065 blend.independent_blend_enable = true;
3066 blend.rt[0].colormask = 0xf;
3067 return si_create_blend_state_mode(&rctx->context, &blend, V_028808_CB_RESOLVE);
3068 }
3069
3070 void si_init_state_functions(struct r600_context *rctx)
3071 {
3072 rctx->context.create_blend_state = si_create_blend_state;
3073 rctx->context.bind_blend_state = si_bind_blend_state;
3074 rctx->context.delete_blend_state = si_delete_blend_state;
3075 rctx->context.set_blend_color = si_set_blend_color;
3076
3077 rctx->context.create_rasterizer_state = si_create_rs_state;
3078 rctx->context.bind_rasterizer_state = si_bind_rs_state;
3079 rctx->context.delete_rasterizer_state = si_delete_rs_state;
3080
3081 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
3082 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3083 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3084
3085 rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
3086 rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
3087 rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
3088 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
3089 rctx->custom_blend_resolve = si_create_resolve_blend(rctx);
3090
3091 rctx->context.set_clip_state = si_set_clip_state;
3092 rctx->context.set_scissor_states = si_set_scissor_states;
3093 rctx->context.set_viewport_states = si_set_viewport_states;
3094 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
3095
3096 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
3097 rctx->context.get_sample_position = si_get_sample_position;
3098
3099 rctx->context.create_vs_state = si_create_vs_state;
3100 rctx->context.create_fs_state = si_create_fs_state;
3101 rctx->context.bind_vs_state = si_bind_vs_shader;
3102 rctx->context.bind_fs_state = si_bind_ps_shader;
3103 rctx->context.delete_vs_state = si_delete_vs_shader;
3104 rctx->context.delete_fs_state = si_delete_ps_shader;
3105
3106 rctx->context.create_sampler_state = si_create_sampler_state;
3107 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler_states;
3108 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler_states;
3109 rctx->context.delete_sampler_state = si_delete_sampler_state;
3110
3111 rctx->context.create_sampler_view = si_create_sampler_view;
3112 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_views;
3113 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_views;
3114 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
3115
3116 rctx->context.set_sample_mask = si_set_sample_mask;
3117
3118 rctx->context.set_constant_buffer = si_set_constant_buffer;
3119
3120 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
3121 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
3122 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
3123 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
3124 rctx->context.set_index_buffer = si_set_index_buffer;
3125
3126 rctx->context.create_stream_output_target = si_create_so_target;
3127 rctx->context.stream_output_target_destroy = si_so_target_destroy;
3128 rctx->context.set_stream_output_targets = si_set_so_targets;
3129
3130 rctx->context.texture_barrier = si_texture_barrier;
3131 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
3132
3133 rctx->context.draw_vbo = si_draw_vbo;
3134 }
3135
3136 void si_init_config(struct r600_context *rctx)
3137 {
3138 struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
3139
3140 if (pm4 == NULL)
3141 return;
3142
3143 si_cmd_context_control(pm4);
3144
3145 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
3146
3147 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
3148 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
3149 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3150 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3151 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
3152 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
3153 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
3154 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
3155 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
3156 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
3157 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
3158 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
3159 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
3160 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3161 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3162 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
3163 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3164 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
3165 S_028AA8_SWITCH_ON_EOP(1) |
3166 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
3167 S_028AA8_PRIMGROUP_SIZE(63));
3168 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
3169 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3170 if (rctx->chip_class < CIK)
3171 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3172 S_008A14_CLIP_VTX_REORDER_ENA(1));
3173
3174 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
3175 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3176 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3177
3178 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3179
3180 if (rctx->chip_class >= CIK) {
3181 switch (rctx->screen->family) {
3182 case CHIP_BONAIRE:
3183 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3184 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3185 break;
3186 case CHIP_KAVERI:
3187 /* XXX todo */
3188 case CHIP_KABINI:
3189 /* XXX todo */
3190 default:
3191 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3192 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
3193 break;
3194 }
3195 } else {
3196 switch (rctx->screen->family) {
3197 case CHIP_TAHITI:
3198 case CHIP_PITCAIRN:
3199 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
3200 break;
3201 case CHIP_VERDE:
3202 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
3203 break;
3204 case CHIP_OLAND:
3205 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
3206 break;
3207 case CHIP_HAINAN:
3208 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3209 break;
3210 default:
3211 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
3212 break;
3213 }
3214 }
3215
3216 si_pm4_set_state(rctx, init, pm4);
3217 }