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radeonsi: avoid redundant CB and DB register updates
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state),
51 unsigned num_dw)
52 {
53 atom->emit = (void*)emit_func;
54 atom->num_dw = num_dw;
55 atom->dirty = false;
56 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
57 *list_elem = atom;
58 }
59
60 unsigned si_array_mode(unsigned mode)
61 {
62 switch (mode) {
63 case RADEON_SURF_MODE_LINEAR_ALIGNED:
64 return V_009910_ARRAY_LINEAR_ALIGNED;
65 case RADEON_SURF_MODE_1D:
66 return V_009910_ARRAY_1D_TILED_THIN1;
67 case RADEON_SURF_MODE_2D:
68 return V_009910_ARRAY_2D_TILED_THIN1;
69 default:
70 case RADEON_SURF_MODE_LINEAR:
71 return V_009910_ARRAY_LINEAR_GENERAL;
72 }
73 }
74
75 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
76 {
77 if (sscreen->b.chip_class >= CIK &&
78 sscreen->b.info.cik_macrotile_mode_array_valid) {
79 unsigned index, tileb;
80
81 tileb = 8 * 8 * tex->surface.bpe;
82 tileb = MIN2(tex->surface.tile_split, tileb);
83
84 for (index = 0; tileb > 64; index++) {
85 tileb >>= 1;
86 }
87 assert(index < 16);
88
89 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
90 }
91
92 if (sscreen->b.chip_class == SI &&
93 sscreen->b.info.si_tile_mode_array_valid) {
94 /* Don't use stencil_tiling_index, because num_banks is always
95 * read from the depth mode. */
96 unsigned tile_mode_index = tex->surface.tiling_index[0];
97 assert(tile_mode_index < 32);
98
99 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
100 }
101
102 /* The old way. */
103 switch (sscreen->b.tiling_info.num_banks) {
104 case 2:
105 return V_02803C_ADDR_SURF_2_BANK;
106 case 4:
107 return V_02803C_ADDR_SURF_4_BANK;
108 case 8:
109 default:
110 return V_02803C_ADDR_SURF_8_BANK;
111 case 16:
112 return V_02803C_ADDR_SURF_16_BANK;
113 }
114 }
115
116 unsigned cik_tile_split(unsigned tile_split)
117 {
118 switch (tile_split) {
119 case 64:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
121 break;
122 case 128:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
124 break;
125 case 256:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
127 break;
128 case 512:
129 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
130 break;
131 default:
132 case 1024:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
134 break;
135 case 2048:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
137 break;
138 case 4096:
139 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
140 break;
141 }
142 return tile_split;
143 }
144
145 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
146 {
147 switch (macro_tile_aspect) {
148 default:
149 case 1:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
151 break;
152 case 2:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
154 break;
155 case 4:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
157 break;
158 case 8:
159 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
160 break;
161 }
162 return macro_tile_aspect;
163 }
164
165 unsigned cik_bank_wh(unsigned bankwh)
166 {
167 switch (bankwh) {
168 default:
169 case 1:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
171 break;
172 case 2:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
174 break;
175 case 4:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
177 break;
178 case 8:
179 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
180 break;
181 }
182 return bankwh;
183 }
184
185 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
186 {
187 if (sscreen->b.info.si_tile_mode_array_valid) {
188 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
189
190 return G_009910_PIPE_CONFIG(gb_tile_mode);
191 }
192
193 /* This is probably broken for a lot of chips, but it's only used
194 * if the kernel cannot return the tile mode array for CIK. */
195 switch (sscreen->b.info.r600_num_tile_pipes) {
196 case 16:
197 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
198 case 8:
199 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
200 case 4:
201 default:
202 if (sscreen->b.info.r600_num_backends == 4)
203 return V_02803C_X_ADDR_SURF_P4_16X16;
204 else
205 return V_02803C_X_ADDR_SURF_P4_8X16;
206 case 2:
207 return V_02803C_ADDR_SURF_P2;
208 }
209 }
210
211 static unsigned si_map_swizzle(unsigned swizzle)
212 {
213 switch (swizzle) {
214 case UTIL_FORMAT_SWIZZLE_Y:
215 return V_008F0C_SQ_SEL_Y;
216 case UTIL_FORMAT_SWIZZLE_Z:
217 return V_008F0C_SQ_SEL_Z;
218 case UTIL_FORMAT_SWIZZLE_W:
219 return V_008F0C_SQ_SEL_W;
220 case UTIL_FORMAT_SWIZZLE_0:
221 return V_008F0C_SQ_SEL_0;
222 case UTIL_FORMAT_SWIZZLE_1:
223 return V_008F0C_SQ_SEL_1;
224 default: /* UTIL_FORMAT_SWIZZLE_X */
225 return V_008F0C_SQ_SEL_X;
226 }
227 }
228
229 static uint32_t S_FIXED(float value, uint32_t frac_bits)
230 {
231 return value * (1 << frac_bits);
232 }
233
234 /* 12.4 fixed-point */
235 static unsigned si_pack_float_12p4(float x)
236 {
237 return x <= 0 ? 0 :
238 x >= 4096 ? 0xffff : x * 16;
239 }
240
241 /*
242 * Inferred framebuffer and blender state.
243 *
244 * One of the reasons this must be derived from the framebuffer state is that:
245 * - The blend state mask is 0xf most of the time.
246 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
247 * so COLOR1 is enabled pretty much all the time.
248 * So CB_TARGET_MASK is the only register that can disable COLOR1.
249 *
250 * Another reason is to avoid a hang with dual source blending.
251 */
252 void si_update_fb_blend_state(struct si_context *sctx)
253 {
254 struct si_pm4_state *pm4;
255 struct si_state_blend *blend = sctx->queued.named.blend;
256 uint32_t mask = 0, i;
257
258 if (blend == NULL)
259 return;
260
261 pm4 = CALLOC_STRUCT(si_pm4_state);
262 if (pm4 == NULL)
263 return;
264
265 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
266 if (sctx->framebuffer.state.cbufs[i])
267 mask |= 0xf << (4*i);
268 mask &= blend->cb_target_mask;
269
270 /* Avoid a hang that happens when dual source blending is enabled
271 * but there is not enough color outputs. This is undefined behavior,
272 * so disable color writes completely.
273 *
274 * Reproducible with Unigine Heaven 4.0 and drirc missing.
275 */
276 if (blend->dual_src_blend &&
277 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
278 mask = 0;
279
280 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
281 si_pm4_set_state(sctx, fb_blend, pm4);
282 }
283
284 /*
285 * Blender functions
286 */
287
288 static uint32_t si_translate_blend_function(int blend_func)
289 {
290 switch (blend_func) {
291 case PIPE_BLEND_ADD:
292 return V_028780_COMB_DST_PLUS_SRC;
293 case PIPE_BLEND_SUBTRACT:
294 return V_028780_COMB_SRC_MINUS_DST;
295 case PIPE_BLEND_REVERSE_SUBTRACT:
296 return V_028780_COMB_DST_MINUS_SRC;
297 case PIPE_BLEND_MIN:
298 return V_028780_COMB_MIN_DST_SRC;
299 case PIPE_BLEND_MAX:
300 return V_028780_COMB_MAX_DST_SRC;
301 default:
302 R600_ERR("Unknown blend function %d\n", blend_func);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
309 static uint32_t si_translate_blend_factor(int blend_fact)
310 {
311 switch (blend_fact) {
312 case PIPE_BLENDFACTOR_ONE:
313 return V_028780_BLEND_ONE;
314 case PIPE_BLENDFACTOR_SRC_COLOR:
315 return V_028780_BLEND_SRC_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA:
317 return V_028780_BLEND_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_DST_ALPHA:
319 return V_028780_BLEND_DST_ALPHA;
320 case PIPE_BLENDFACTOR_DST_COLOR:
321 return V_028780_BLEND_DST_COLOR;
322 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case PIPE_BLENDFACTOR_CONST_COLOR:
325 return V_028780_BLEND_CONSTANT_COLOR;
326 case PIPE_BLENDFACTOR_CONST_ALPHA:
327 return V_028780_BLEND_CONSTANT_ALPHA;
328 case PIPE_BLENDFACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
331 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
334 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
336 case PIPE_BLENDFACTOR_INV_DST_COLOR:
337 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
338 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
340 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
342 case PIPE_BLENDFACTOR_SRC1_COLOR:
343 return V_028780_BLEND_SRC1_COLOR;
344 case PIPE_BLENDFACTOR_SRC1_ALPHA:
345 return V_028780_BLEND_SRC1_ALPHA;
346 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
347 return V_028780_BLEND_INV_SRC1_COLOR;
348 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
349 return V_028780_BLEND_INV_SRC1_ALPHA;
350 default:
351 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
352 assert(0);
353 break;
354 }
355 return 0;
356 }
357
358 static void *si_create_blend_state_mode(struct pipe_context *ctx,
359 const struct pipe_blend_state *state,
360 unsigned mode)
361 {
362 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
363 struct si_pm4_state *pm4 = &blend->pm4;
364
365 uint32_t color_control = 0;
366
367 if (blend == NULL)
368 return NULL;
369
370 blend->alpha_to_one = state->alpha_to_one;
371 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
372
373 if (state->logicop_enable) {
374 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
375 } else {
376 color_control |= S_028808_ROP3(0xcc);
377 }
378
379 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
380 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
381 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
382 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
383 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
384 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
385
386 blend->cb_target_mask = 0;
387 for (int i = 0; i < 8; i++) {
388 /* state->rt entries > 0 only written if independent blending */
389 const int j = state->independent_blend_enable ? i : 0;
390
391 unsigned eqRGB = state->rt[j].rgb_func;
392 unsigned srcRGB = state->rt[j].rgb_src_factor;
393 unsigned dstRGB = state->rt[j].rgb_dst_factor;
394 unsigned eqA = state->rt[j].alpha_func;
395 unsigned srcA = state->rt[j].alpha_src_factor;
396 unsigned dstA = state->rt[j].alpha_dst_factor;
397
398 unsigned blend_cntl = 0;
399
400 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
401 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
402
403 if (!state->rt[j].blend_enable) {
404 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
405 continue;
406 }
407
408 blend_cntl |= S_028780_ENABLE(1);
409 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
410 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
411 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
412
413 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
414 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
415 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
416 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
417 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
418 }
419 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
420 }
421
422 if (blend->cb_target_mask) {
423 color_control |= S_028808_MODE(mode);
424 } else {
425 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
426 }
427 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
428
429 return blend;
430 }
431
432 static void *si_create_blend_state(struct pipe_context *ctx,
433 const struct pipe_blend_state *state)
434 {
435 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
436 }
437
438 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
439 {
440 struct si_context *sctx = (struct si_context *)ctx;
441 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
442 si_update_fb_blend_state(sctx);
443 }
444
445 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
446 {
447 struct si_context *sctx = (struct si_context *)ctx;
448 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
449 }
450
451 static void si_set_blend_color(struct pipe_context *ctx,
452 const struct pipe_blend_color *state)
453 {
454 struct si_context *sctx = (struct si_context *)ctx;
455 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
456
457 if (pm4 == NULL)
458 return;
459
460 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
461 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
462 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
463 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
464
465 si_pm4_set_state(sctx, blend_color, pm4);
466 }
467
468 /*
469 * Clipping, scissors and viewport
470 */
471
472 static void si_set_clip_state(struct pipe_context *ctx,
473 const struct pipe_clip_state *state)
474 {
475 struct si_context *sctx = (struct si_context *)ctx;
476 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
477 struct pipe_constant_buffer cb;
478
479 if (pm4 == NULL)
480 return;
481
482 for (int i = 0; i < 6; i++) {
483 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
484 fui(state->ucp[i][0]));
485 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
486 fui(state->ucp[i][1]));
487 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
488 fui(state->ucp[i][2]));
489 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
490 fui(state->ucp[i][3]));
491 }
492
493 cb.buffer = NULL;
494 cb.user_buffer = state->ucp;
495 cb.buffer_offset = 0;
496 cb.buffer_size = 4*4*8;
497 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
498 pipe_resource_reference(&cb.buffer, NULL);
499
500 si_pm4_set_state(sctx, clip, pm4);
501 }
502
503 #define SIX_BITS 0x3F
504
505 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
506 {
507 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
508 struct tgsi_shader_info *info = si_get_vs_info(sctx);
509 unsigned window_space =
510 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
511 unsigned clipdist_mask =
512 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
513
514 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
515 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
516 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
517 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
518 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
519 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
520 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
521 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
522 info->writes_edgeflag ||
523 info->writes_layer ||
524 info->writes_viewport_index) |
525 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
526 (sctx->queued.named.rasterizer->clip_plane_enable &
527 clipdist_mask));
528 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
529 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
530 (clipdist_mask ? 0 :
531 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
532 S_028810_CLIP_DISABLE(window_space));
533 }
534
535 static void si_set_scissor_states(struct pipe_context *ctx,
536 unsigned start_slot,
537 unsigned num_scissors,
538 const struct pipe_scissor_state *state)
539 {
540 struct si_context *sctx = (struct si_context *)ctx;
541 int i;
542
543 for (i = 0; i < num_scissors; i++)
544 sctx->scissors.states[start_slot + i] = state[i];
545
546 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
547 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
548 }
549
550 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
551 {
552 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
553 struct pipe_scissor_state *states = sctx->scissors.states;
554 unsigned mask = sctx->scissors.dirty_mask;
555
556 /* The simple case: Only 1 viewport is active. */
557 if (mask & 1 &&
558 !si_get_vs_info(sctx)->writes_viewport_index) {
559 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
560 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
561 S_028250_TL_Y(states[0].miny) |
562 S_028250_WINDOW_OFFSET_DISABLE(1));
563 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
564 S_028254_BR_Y(states[0].maxy));
565 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
566 return;
567 }
568
569 while (mask) {
570 int start, count, i;
571
572 u_bit_scan_consecutive_range(&mask, &start, &count);
573
574 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
575 start * 4 * 2, count * 2);
576 for (i = start; i < start+count; i++) {
577 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
578 S_028250_TL_Y(states[i].miny) |
579 S_028250_WINDOW_OFFSET_DISABLE(1));
580 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
581 S_028254_BR_Y(states[i].maxy));
582 }
583 }
584 sctx->scissors.dirty_mask = 0;
585 }
586
587 static void si_set_viewport_states(struct pipe_context *ctx,
588 unsigned start_slot,
589 unsigned num_viewports,
590 const struct pipe_viewport_state *state)
591 {
592 struct si_context *sctx = (struct si_context *)ctx;
593 int i;
594
595 for (i = 0; i < num_viewports; i++)
596 sctx->viewports.states[start_slot + i] = state[i];
597
598 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
599 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
600 }
601
602 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
603 {
604 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
605 struct pipe_viewport_state *states = sctx->viewports.states;
606 unsigned mask = sctx->viewports.dirty_mask;
607
608 /* The simple case: Only 1 viewport is active. */
609 if (mask & 1 &&
610 !si_get_vs_info(sctx)->writes_viewport_index) {
611 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
612 radeon_emit(cs, fui(states[0].scale[0]));
613 radeon_emit(cs, fui(states[0].translate[0]));
614 radeon_emit(cs, fui(states[0].scale[1]));
615 radeon_emit(cs, fui(states[0].translate[1]));
616 radeon_emit(cs, fui(states[0].scale[2]));
617 radeon_emit(cs, fui(states[0].translate[2]));
618 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
619 return;
620 }
621
622 while (mask) {
623 int start, count, i;
624
625 u_bit_scan_consecutive_range(&mask, &start, &count);
626
627 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
628 start * 4 * 6, count * 6);
629 for (i = start; i < start+count; i++) {
630 radeon_emit(cs, fui(states[i].scale[0]));
631 radeon_emit(cs, fui(states[i].translate[0]));
632 radeon_emit(cs, fui(states[i].scale[1]));
633 radeon_emit(cs, fui(states[i].translate[1]));
634 radeon_emit(cs, fui(states[i].scale[2]));
635 radeon_emit(cs, fui(states[i].translate[2]));
636 }
637 }
638 sctx->viewports.dirty_mask = 0;
639 }
640
641 /*
642 * inferred state between framebuffer and rasterizer
643 */
644 static void si_update_fb_rs_state(struct si_context *sctx)
645 {
646 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
647 struct si_pm4_state *pm4;
648 float offset_units;
649
650 if (!rs || !sctx->framebuffer.state.zsbuf)
651 return;
652
653 offset_units = sctx->queued.named.rasterizer->offset_units;
654 switch (sctx->framebuffer.state.zsbuf->texture->format) {
655 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
656 case PIPE_FORMAT_X8Z24_UNORM:
657 case PIPE_FORMAT_Z24X8_UNORM:
658 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
659 offset_units *= 2.0f;
660 break;
661 case PIPE_FORMAT_Z32_FLOAT:
662 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
663 offset_units *= 1.0f;
664 break;
665 case PIPE_FORMAT_Z16_UNORM:
666 offset_units *= 4.0f;
667 break;
668 default:
669 return;
670 }
671
672 pm4 = CALLOC_STRUCT(si_pm4_state);
673
674 if (pm4 == NULL)
675 return;
676
677 /* FIXME some of those reg can be computed with cso */
678 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
679 fui(sctx->queued.named.rasterizer->offset_scale));
680 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
681 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
682 fui(sctx->queued.named.rasterizer->offset_scale));
683 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
684
685 si_pm4_set_state(sctx, fb_rs, pm4);
686 }
687
688 /*
689 * Rasterizer
690 */
691
692 static uint32_t si_translate_fill(uint32_t func)
693 {
694 switch(func) {
695 case PIPE_POLYGON_MODE_FILL:
696 return V_028814_X_DRAW_TRIANGLES;
697 case PIPE_POLYGON_MODE_LINE:
698 return V_028814_X_DRAW_LINES;
699 case PIPE_POLYGON_MODE_POINT:
700 return V_028814_X_DRAW_POINTS;
701 default:
702 assert(0);
703 return V_028814_X_DRAW_POINTS;
704 }
705 }
706
707 static void *si_create_rs_state(struct pipe_context *ctx,
708 const struct pipe_rasterizer_state *state)
709 {
710 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
711 struct si_pm4_state *pm4 = &rs->pm4;
712 unsigned tmp;
713 float psize_min, psize_max;
714
715 if (rs == NULL) {
716 return NULL;
717 }
718
719 rs->two_side = state->light_twoside;
720 rs->multisample_enable = state->multisample;
721 rs->clip_plane_enable = state->clip_plane_enable;
722 rs->line_stipple_enable = state->line_stipple_enable;
723 rs->poly_stipple_enable = state->poly_stipple_enable;
724 rs->line_smooth = state->line_smooth;
725 rs->poly_smooth = state->poly_smooth;
726
727 rs->flatshade = state->flatshade;
728 rs->sprite_coord_enable = state->sprite_coord_enable;
729 rs->pa_sc_line_stipple = state->line_stipple_enable ?
730 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
731 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
732 rs->pa_cl_clip_cntl =
733 S_028810_PS_UCP_MODE(3) |
734 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
735 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
736 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
737 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
738 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
739
740 /* offset */
741 rs->offset_units = state->offset_units;
742 rs->offset_scale = state->offset_scale * 16.0f;
743
744 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
745 S_0286D4_FLAT_SHADE_ENA(1) |
746 S_0286D4_PNT_SPRITE_ENA(1) |
747 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
748 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
749 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
750 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
751 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
752
753 /* point size 12.4 fixed point */
754 tmp = (unsigned)(state->point_size * 8.0);
755 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
756
757 if (state->point_size_per_vertex) {
758 psize_min = util_get_min_point_size(state);
759 psize_max = 8192;
760 } else {
761 /* Force the point size to be as if the vertex output was disabled. */
762 psize_min = state->point_size;
763 psize_max = state->point_size;
764 }
765 /* Divide by two, because 0.5 = 1 pixel. */
766 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
767 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
768 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
769
770 tmp = (unsigned)state->line_width * 8;
771 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
772 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
773 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
774 S_028A48_MSAA_ENABLE(state->multisample ||
775 state->poly_smooth ||
776 state->line_smooth) |
777 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
778
779 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
780 S_028BE4_PIX_CENTER(state->half_pixel_center) |
781 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
782
783 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
784 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
785 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
786 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
787 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
788 S_028814_FACE(!state->front_ccw) |
789 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
790 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
791 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
792 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
793 state->fill_back != PIPE_POLYGON_MODE_FILL) |
794 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
795 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
796 return rs;
797 }
798
799 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
800 {
801 struct si_context *sctx = (struct si_context *)ctx;
802 struct si_state_rasterizer *old_rs =
803 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
804 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
805
806 if (state == NULL)
807 return;
808
809 if (sctx->framebuffer.nr_samples > 1 &&
810 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
811 si_mark_atom_dirty(sctx, &sctx->db_render_state);
812
813 si_pm4_bind_state(sctx, rasterizer, rs);
814 si_update_fb_rs_state(sctx);
815
816 si_mark_atom_dirty(sctx, &sctx->clip_regs);
817 }
818
819 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
820 {
821 struct si_context *sctx = (struct si_context *)ctx;
822 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
823 }
824
825 /*
826 * infeered state between dsa and stencil ref
827 */
828 static void si_update_dsa_stencil_ref(struct si_context *sctx)
829 {
830 struct si_pm4_state *pm4;
831 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
832 struct si_state_dsa *dsa = sctx->queued.named.dsa;
833
834 if (!dsa)
835 return;
836
837 pm4 = CALLOC_STRUCT(si_pm4_state);
838 if (pm4 == NULL)
839 return;
840
841 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
842 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
843 S_028430_STENCILMASK(dsa->valuemask[0]) |
844 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
845 S_028430_STENCILOPVAL(1));
846 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
847 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
848 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
849 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
850 S_028434_STENCILOPVAL_BF(1));
851
852 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
853 }
854
855 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
856 const struct pipe_stencil_ref *state)
857 {
858 struct si_context *sctx = (struct si_context *)ctx;
859 sctx->stencil_ref = *state;
860 si_update_dsa_stencil_ref(sctx);
861 }
862
863
864 /*
865 * DSA
866 */
867
868 static uint32_t si_translate_stencil_op(int s_op)
869 {
870 switch (s_op) {
871 case PIPE_STENCIL_OP_KEEP:
872 return V_02842C_STENCIL_KEEP;
873 case PIPE_STENCIL_OP_ZERO:
874 return V_02842C_STENCIL_ZERO;
875 case PIPE_STENCIL_OP_REPLACE:
876 return V_02842C_STENCIL_REPLACE_TEST;
877 case PIPE_STENCIL_OP_INCR:
878 return V_02842C_STENCIL_ADD_CLAMP;
879 case PIPE_STENCIL_OP_DECR:
880 return V_02842C_STENCIL_SUB_CLAMP;
881 case PIPE_STENCIL_OP_INCR_WRAP:
882 return V_02842C_STENCIL_ADD_WRAP;
883 case PIPE_STENCIL_OP_DECR_WRAP:
884 return V_02842C_STENCIL_SUB_WRAP;
885 case PIPE_STENCIL_OP_INVERT:
886 return V_02842C_STENCIL_INVERT;
887 default:
888 R600_ERR("Unknown stencil op %d", s_op);
889 assert(0);
890 break;
891 }
892 return 0;
893 }
894
895 static void *si_create_dsa_state(struct pipe_context *ctx,
896 const struct pipe_depth_stencil_alpha_state *state)
897 {
898 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
899 struct si_pm4_state *pm4 = &dsa->pm4;
900 unsigned db_depth_control;
901 uint32_t db_stencil_control = 0;
902
903 if (dsa == NULL) {
904 return NULL;
905 }
906
907 dsa->valuemask[0] = state->stencil[0].valuemask;
908 dsa->valuemask[1] = state->stencil[1].valuemask;
909 dsa->writemask[0] = state->stencil[0].writemask;
910 dsa->writemask[1] = state->stencil[1].writemask;
911
912 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
913 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
914 S_028800_ZFUNC(state->depth.func) |
915 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
916
917 /* stencil */
918 if (state->stencil[0].enabled) {
919 db_depth_control |= S_028800_STENCIL_ENABLE(1);
920 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
921 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
922 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
923 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
924
925 if (state->stencil[1].enabled) {
926 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
927 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
928 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
929 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
930 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
931 }
932 }
933
934 /* alpha */
935 if (state->alpha.enabled) {
936 dsa->alpha_func = state->alpha.func;
937
938 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
939 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
940 } else {
941 dsa->alpha_func = PIPE_FUNC_ALWAYS;
942 }
943
944 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
945 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
946 if (state->depth.bounds_test) {
947 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
948 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
949 }
950
951 return dsa;
952 }
953
954 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
955 {
956 struct si_context *sctx = (struct si_context *)ctx;
957 struct si_state_dsa *dsa = state;
958
959 if (state == NULL)
960 return;
961
962 si_pm4_bind_state(sctx, dsa, dsa);
963 si_update_dsa_stencil_ref(sctx);
964 }
965
966 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
967 {
968 struct si_context *sctx = (struct si_context *)ctx;
969 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
970 }
971
972 static void *si_create_db_flush_dsa(struct si_context *sctx)
973 {
974 struct pipe_depth_stencil_alpha_state dsa = {};
975
976 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
977 }
978
979 /* DB RENDER STATE */
980
981 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
982 {
983 struct si_context *sctx = (struct si_context*)ctx;
984
985 si_mark_atom_dirty(sctx, &sctx->db_render_state);
986 }
987
988 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
989 {
990 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
991 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
992 unsigned db_shader_control;
993
994 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
995
996 /* DB_RENDER_CONTROL */
997 if (sctx->dbcb_depth_copy_enabled ||
998 sctx->dbcb_stencil_copy_enabled) {
999 radeon_emit(cs,
1000 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1001 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1002 S_028000_COPY_CENTROID(1) |
1003 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1004 } else if (sctx->db_inplace_flush_enabled) {
1005 radeon_emit(cs,
1006 S_028000_DEPTH_COMPRESS_DISABLE(1) |
1007 S_028000_STENCIL_COMPRESS_DISABLE(1));
1008 } else if (sctx->db_depth_clear) {
1009 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1010 } else {
1011 radeon_emit(cs, 0);
1012 }
1013
1014 /* DB_COUNT_CONTROL (occlusion queries) */
1015 if (sctx->b.num_occlusion_queries > 0) {
1016 if (sctx->b.chip_class >= CIK) {
1017 radeon_emit(cs,
1018 S_028004_PERFECT_ZPASS_COUNTS(1) |
1019 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1020 S_028004_ZPASS_ENABLE(1) |
1021 S_028004_SLICE_EVEN_ENABLE(1) |
1022 S_028004_SLICE_ODD_ENABLE(1));
1023 } else {
1024 radeon_emit(cs,
1025 S_028004_PERFECT_ZPASS_COUNTS(1) |
1026 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1027 }
1028 } else {
1029 /* Disable occlusion queries. */
1030 if (sctx->b.chip_class >= CIK) {
1031 radeon_emit(cs, 0);
1032 } else {
1033 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1034 }
1035 }
1036
1037 /* DB_RENDER_OVERRIDE2 */
1038 if (sctx->db_depth_disable_expclear) {
1039 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1040 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1041 } else {
1042 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1043 }
1044
1045 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1046 sctx->ps_db_shader_control;
1047
1048 /* Bug workaround for smoothing (overrasterization) on SI. */
1049 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1050 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1051 else
1052 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1053
1054 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1055 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1056 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1057
1058 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1059 db_shader_control);
1060 }
1061
1062 /*
1063 * format translation
1064 */
1065 static uint32_t si_translate_colorformat(enum pipe_format format)
1066 {
1067 const struct util_format_description *desc = util_format_description(format);
1068
1069 #define HAS_SIZE(x,y,z,w) \
1070 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1071 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1072
1073 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1074 return V_028C70_COLOR_10_11_11;
1075
1076 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1077 return V_028C70_COLOR_INVALID;
1078
1079 switch (desc->nr_channels) {
1080 case 1:
1081 switch (desc->channel[0].size) {
1082 case 8:
1083 return V_028C70_COLOR_8;
1084 case 16:
1085 return V_028C70_COLOR_16;
1086 case 32:
1087 return V_028C70_COLOR_32;
1088 }
1089 break;
1090 case 2:
1091 if (desc->channel[0].size == desc->channel[1].size) {
1092 switch (desc->channel[0].size) {
1093 case 8:
1094 return V_028C70_COLOR_8_8;
1095 case 16:
1096 return V_028C70_COLOR_16_16;
1097 case 32:
1098 return V_028C70_COLOR_32_32;
1099 }
1100 } else if (HAS_SIZE(8,24,0,0)) {
1101 return V_028C70_COLOR_24_8;
1102 } else if (HAS_SIZE(24,8,0,0)) {
1103 return V_028C70_COLOR_8_24;
1104 }
1105 break;
1106 case 3:
1107 if (HAS_SIZE(5,6,5,0)) {
1108 return V_028C70_COLOR_5_6_5;
1109 } else if (HAS_SIZE(32,8,24,0)) {
1110 return V_028C70_COLOR_X24_8_32_FLOAT;
1111 }
1112 break;
1113 case 4:
1114 if (desc->channel[0].size == desc->channel[1].size &&
1115 desc->channel[0].size == desc->channel[2].size &&
1116 desc->channel[0].size == desc->channel[3].size) {
1117 switch (desc->channel[0].size) {
1118 case 4:
1119 return V_028C70_COLOR_4_4_4_4;
1120 case 8:
1121 return V_028C70_COLOR_8_8_8_8;
1122 case 16:
1123 return V_028C70_COLOR_16_16_16_16;
1124 case 32:
1125 return V_028C70_COLOR_32_32_32_32;
1126 }
1127 } else if (HAS_SIZE(5,5,5,1)) {
1128 return V_028C70_COLOR_1_5_5_5;
1129 } else if (HAS_SIZE(10,10,10,2)) {
1130 return V_028C70_COLOR_2_10_10_10;
1131 }
1132 break;
1133 }
1134 return V_028C70_COLOR_INVALID;
1135 }
1136
1137 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1138 {
1139 if (SI_BIG_ENDIAN) {
1140 switch(colorformat) {
1141 /* 8-bit buffers. */
1142 case V_028C70_COLOR_8:
1143 return V_028C70_ENDIAN_NONE;
1144
1145 /* 16-bit buffers. */
1146 case V_028C70_COLOR_5_6_5:
1147 case V_028C70_COLOR_1_5_5_5:
1148 case V_028C70_COLOR_4_4_4_4:
1149 case V_028C70_COLOR_16:
1150 case V_028C70_COLOR_8_8:
1151 return V_028C70_ENDIAN_8IN16;
1152
1153 /* 32-bit buffers. */
1154 case V_028C70_COLOR_8_8_8_8:
1155 case V_028C70_COLOR_2_10_10_10:
1156 case V_028C70_COLOR_8_24:
1157 case V_028C70_COLOR_24_8:
1158 case V_028C70_COLOR_16_16:
1159 return V_028C70_ENDIAN_8IN32;
1160
1161 /* 64-bit buffers. */
1162 case V_028C70_COLOR_16_16_16_16:
1163 return V_028C70_ENDIAN_8IN16;
1164
1165 case V_028C70_COLOR_32_32:
1166 return V_028C70_ENDIAN_8IN32;
1167
1168 /* 128-bit buffers. */
1169 case V_028C70_COLOR_32_32_32_32:
1170 return V_028C70_ENDIAN_8IN32;
1171 default:
1172 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1173 }
1174 } else {
1175 return V_028C70_ENDIAN_NONE;
1176 }
1177 }
1178
1179 /* Returns the size in bits of the widest component of a CB format */
1180 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1181 {
1182 switch(colorformat) {
1183 case V_028C70_COLOR_4_4_4_4:
1184 return 4;
1185
1186 case V_028C70_COLOR_1_5_5_5:
1187 case V_028C70_COLOR_5_5_5_1:
1188 return 5;
1189
1190 case V_028C70_COLOR_5_6_5:
1191 return 6;
1192
1193 case V_028C70_COLOR_8:
1194 case V_028C70_COLOR_8_8:
1195 case V_028C70_COLOR_8_8_8_8:
1196 return 8;
1197
1198 case V_028C70_COLOR_10_10_10_2:
1199 case V_028C70_COLOR_2_10_10_10:
1200 return 10;
1201
1202 case V_028C70_COLOR_10_11_11:
1203 case V_028C70_COLOR_11_11_10:
1204 return 11;
1205
1206 case V_028C70_COLOR_16:
1207 case V_028C70_COLOR_16_16:
1208 case V_028C70_COLOR_16_16_16_16:
1209 return 16;
1210
1211 case V_028C70_COLOR_8_24:
1212 case V_028C70_COLOR_24_8:
1213 return 24;
1214
1215 case V_028C70_COLOR_32:
1216 case V_028C70_COLOR_32_32:
1217 case V_028C70_COLOR_32_32_32_32:
1218 case V_028C70_COLOR_X24_8_32_FLOAT:
1219 return 32;
1220 }
1221
1222 assert(!"Unknown maximum component size");
1223 return 0;
1224 }
1225
1226 static uint32_t si_translate_dbformat(enum pipe_format format)
1227 {
1228 switch (format) {
1229 case PIPE_FORMAT_Z16_UNORM:
1230 return V_028040_Z_16;
1231 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1232 case PIPE_FORMAT_X8Z24_UNORM:
1233 case PIPE_FORMAT_Z24X8_UNORM:
1234 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1235 return V_028040_Z_24; /* deprecated on SI */
1236 case PIPE_FORMAT_Z32_FLOAT:
1237 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1238 return V_028040_Z_32_FLOAT;
1239 default:
1240 return V_028040_Z_INVALID;
1241 }
1242 }
1243
1244 /*
1245 * Texture translation
1246 */
1247
1248 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1249 enum pipe_format format,
1250 const struct util_format_description *desc,
1251 int first_non_void)
1252 {
1253 struct si_screen *sscreen = (struct si_screen*)screen;
1254 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1255 sscreen->b.info.drm_minor >= 31) ||
1256 sscreen->b.info.drm_major == 3;
1257 boolean uniform = TRUE;
1258 int i;
1259
1260 /* Colorspace (return non-RGB formats directly). */
1261 switch (desc->colorspace) {
1262 /* Depth stencil formats */
1263 case UTIL_FORMAT_COLORSPACE_ZS:
1264 switch (format) {
1265 case PIPE_FORMAT_Z16_UNORM:
1266 return V_008F14_IMG_DATA_FORMAT_16;
1267 case PIPE_FORMAT_X24S8_UINT:
1268 case PIPE_FORMAT_Z24X8_UNORM:
1269 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1270 return V_008F14_IMG_DATA_FORMAT_8_24;
1271 case PIPE_FORMAT_X8Z24_UNORM:
1272 case PIPE_FORMAT_S8X24_UINT:
1273 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1274 return V_008F14_IMG_DATA_FORMAT_24_8;
1275 case PIPE_FORMAT_S8_UINT:
1276 return V_008F14_IMG_DATA_FORMAT_8;
1277 case PIPE_FORMAT_Z32_FLOAT:
1278 return V_008F14_IMG_DATA_FORMAT_32;
1279 case PIPE_FORMAT_X32_S8X24_UINT:
1280 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1281 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1282 default:
1283 goto out_unknown;
1284 }
1285
1286 case UTIL_FORMAT_COLORSPACE_YUV:
1287 goto out_unknown; /* TODO */
1288
1289 case UTIL_FORMAT_COLORSPACE_SRGB:
1290 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1291 goto out_unknown;
1292 break;
1293
1294 default:
1295 break;
1296 }
1297
1298 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1299 if (!enable_compressed_formats)
1300 goto out_unknown;
1301
1302 switch (format) {
1303 case PIPE_FORMAT_RGTC1_SNORM:
1304 case PIPE_FORMAT_LATC1_SNORM:
1305 case PIPE_FORMAT_RGTC1_UNORM:
1306 case PIPE_FORMAT_LATC1_UNORM:
1307 return V_008F14_IMG_DATA_FORMAT_BC4;
1308 case PIPE_FORMAT_RGTC2_SNORM:
1309 case PIPE_FORMAT_LATC2_SNORM:
1310 case PIPE_FORMAT_RGTC2_UNORM:
1311 case PIPE_FORMAT_LATC2_UNORM:
1312 return V_008F14_IMG_DATA_FORMAT_BC5;
1313 default:
1314 goto out_unknown;
1315 }
1316 }
1317
1318 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1319 if (!enable_compressed_formats)
1320 goto out_unknown;
1321
1322 switch (format) {
1323 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1324 case PIPE_FORMAT_BPTC_SRGBA:
1325 return V_008F14_IMG_DATA_FORMAT_BC7;
1326 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1327 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1328 return V_008F14_IMG_DATA_FORMAT_BC6;
1329 default:
1330 goto out_unknown;
1331 }
1332 }
1333
1334 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1335 switch (format) {
1336 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1337 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1338 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1339 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1340 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1341 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1342 default:
1343 goto out_unknown;
1344 }
1345 }
1346
1347 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1348 if (!enable_compressed_formats)
1349 goto out_unknown;
1350
1351 if (!util_format_s3tc_enabled) {
1352 goto out_unknown;
1353 }
1354
1355 switch (format) {
1356 case PIPE_FORMAT_DXT1_RGB:
1357 case PIPE_FORMAT_DXT1_RGBA:
1358 case PIPE_FORMAT_DXT1_SRGB:
1359 case PIPE_FORMAT_DXT1_SRGBA:
1360 return V_008F14_IMG_DATA_FORMAT_BC1;
1361 case PIPE_FORMAT_DXT3_RGBA:
1362 case PIPE_FORMAT_DXT3_SRGBA:
1363 return V_008F14_IMG_DATA_FORMAT_BC2;
1364 case PIPE_FORMAT_DXT5_RGBA:
1365 case PIPE_FORMAT_DXT5_SRGBA:
1366 return V_008F14_IMG_DATA_FORMAT_BC3;
1367 default:
1368 goto out_unknown;
1369 }
1370 }
1371
1372 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1373 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1374 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1375 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1376 }
1377
1378 /* R8G8Bx_SNORM - TODO CxV8U8 */
1379
1380 /* See whether the components are of the same size. */
1381 for (i = 1; i < desc->nr_channels; i++) {
1382 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1383 }
1384
1385 /* Non-uniform formats. */
1386 if (!uniform) {
1387 switch(desc->nr_channels) {
1388 case 3:
1389 if (desc->channel[0].size == 5 &&
1390 desc->channel[1].size == 6 &&
1391 desc->channel[2].size == 5) {
1392 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1393 }
1394 goto out_unknown;
1395 case 4:
1396 if (desc->channel[0].size == 5 &&
1397 desc->channel[1].size == 5 &&
1398 desc->channel[2].size == 5 &&
1399 desc->channel[3].size == 1) {
1400 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1401 }
1402 if (desc->channel[0].size == 10 &&
1403 desc->channel[1].size == 10 &&
1404 desc->channel[2].size == 10 &&
1405 desc->channel[3].size == 2) {
1406 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1407 }
1408 goto out_unknown;
1409 }
1410 goto out_unknown;
1411 }
1412
1413 if (first_non_void < 0 || first_non_void > 3)
1414 goto out_unknown;
1415
1416 /* uniform formats */
1417 switch (desc->channel[first_non_void].size) {
1418 case 4:
1419 switch (desc->nr_channels) {
1420 #if 0 /* Not supported for render targets */
1421 case 2:
1422 return V_008F14_IMG_DATA_FORMAT_4_4;
1423 #endif
1424 case 4:
1425 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1426 }
1427 break;
1428 case 8:
1429 switch (desc->nr_channels) {
1430 case 1:
1431 return V_008F14_IMG_DATA_FORMAT_8;
1432 case 2:
1433 return V_008F14_IMG_DATA_FORMAT_8_8;
1434 case 4:
1435 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1436 }
1437 break;
1438 case 16:
1439 switch (desc->nr_channels) {
1440 case 1:
1441 return V_008F14_IMG_DATA_FORMAT_16;
1442 case 2:
1443 return V_008F14_IMG_DATA_FORMAT_16_16;
1444 case 4:
1445 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1446 }
1447 break;
1448 case 32:
1449 switch (desc->nr_channels) {
1450 case 1:
1451 return V_008F14_IMG_DATA_FORMAT_32;
1452 case 2:
1453 return V_008F14_IMG_DATA_FORMAT_32_32;
1454 #if 0 /* Not supported for render targets */
1455 case 3:
1456 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1457 #endif
1458 case 4:
1459 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1460 }
1461 }
1462
1463 out_unknown:
1464 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1465 return ~0;
1466 }
1467
1468 static unsigned si_tex_wrap(unsigned wrap)
1469 {
1470 switch (wrap) {
1471 default:
1472 case PIPE_TEX_WRAP_REPEAT:
1473 return V_008F30_SQ_TEX_WRAP;
1474 case PIPE_TEX_WRAP_CLAMP:
1475 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1476 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1477 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1478 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1479 return V_008F30_SQ_TEX_CLAMP_BORDER;
1480 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1481 return V_008F30_SQ_TEX_MIRROR;
1482 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1483 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1484 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1485 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1486 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1487 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1488 }
1489 }
1490
1491 static unsigned si_tex_filter(unsigned filter)
1492 {
1493 switch (filter) {
1494 default:
1495 case PIPE_TEX_FILTER_NEAREST:
1496 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1497 case PIPE_TEX_FILTER_LINEAR:
1498 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1499 }
1500 }
1501
1502 static unsigned si_tex_mipfilter(unsigned filter)
1503 {
1504 switch (filter) {
1505 case PIPE_TEX_MIPFILTER_NEAREST:
1506 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1507 case PIPE_TEX_MIPFILTER_LINEAR:
1508 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1509 default:
1510 case PIPE_TEX_MIPFILTER_NONE:
1511 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1512 }
1513 }
1514
1515 static unsigned si_tex_compare(unsigned compare)
1516 {
1517 switch (compare) {
1518 default:
1519 case PIPE_FUNC_NEVER:
1520 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1521 case PIPE_FUNC_LESS:
1522 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1523 case PIPE_FUNC_EQUAL:
1524 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1525 case PIPE_FUNC_LEQUAL:
1526 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1527 case PIPE_FUNC_GREATER:
1528 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1529 case PIPE_FUNC_NOTEQUAL:
1530 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1531 case PIPE_FUNC_GEQUAL:
1532 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1533 case PIPE_FUNC_ALWAYS:
1534 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1535 }
1536 }
1537
1538 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1539 {
1540 switch (dim) {
1541 default:
1542 case PIPE_TEXTURE_1D:
1543 return V_008F1C_SQ_RSRC_IMG_1D;
1544 case PIPE_TEXTURE_1D_ARRAY:
1545 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1546 case PIPE_TEXTURE_2D:
1547 case PIPE_TEXTURE_RECT:
1548 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1549 V_008F1C_SQ_RSRC_IMG_2D;
1550 case PIPE_TEXTURE_2D_ARRAY:
1551 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1552 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1553 case PIPE_TEXTURE_3D:
1554 return V_008F1C_SQ_RSRC_IMG_3D;
1555 case PIPE_TEXTURE_CUBE:
1556 case PIPE_TEXTURE_CUBE_ARRAY:
1557 return V_008F1C_SQ_RSRC_IMG_CUBE;
1558 }
1559 }
1560
1561 /*
1562 * Format support testing
1563 */
1564
1565 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1566 {
1567 return si_translate_texformat(screen, format, util_format_description(format),
1568 util_format_get_first_non_void_channel(format)) != ~0U;
1569 }
1570
1571 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1572 const struct util_format_description *desc,
1573 int first_non_void)
1574 {
1575 unsigned type = desc->channel[first_non_void].type;
1576 int i;
1577
1578 if (type == UTIL_FORMAT_TYPE_FIXED)
1579 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1580
1581 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1582 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1583
1584 if (desc->nr_channels == 4 &&
1585 desc->channel[0].size == 10 &&
1586 desc->channel[1].size == 10 &&
1587 desc->channel[2].size == 10 &&
1588 desc->channel[3].size == 2)
1589 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1590
1591 /* See whether the components are of the same size. */
1592 for (i = 0; i < desc->nr_channels; i++) {
1593 if (desc->channel[first_non_void].size != desc->channel[i].size)
1594 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1595 }
1596
1597 switch (desc->channel[first_non_void].size) {
1598 case 8:
1599 switch (desc->nr_channels) {
1600 case 1:
1601 return V_008F0C_BUF_DATA_FORMAT_8;
1602 case 2:
1603 return V_008F0C_BUF_DATA_FORMAT_8_8;
1604 case 3:
1605 case 4:
1606 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1607 }
1608 break;
1609 case 16:
1610 switch (desc->nr_channels) {
1611 case 1:
1612 return V_008F0C_BUF_DATA_FORMAT_16;
1613 case 2:
1614 return V_008F0C_BUF_DATA_FORMAT_16_16;
1615 case 3:
1616 case 4:
1617 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1618 }
1619 break;
1620 case 32:
1621 /* From the Southern Islands ISA documentation about MTBUF:
1622 * 'Memory reads of data in memory that is 32 or 64 bits do not
1623 * undergo any format conversion.'
1624 */
1625 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1626 !desc->channel[first_non_void].pure_integer)
1627 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1628
1629 switch (desc->nr_channels) {
1630 case 1:
1631 return V_008F0C_BUF_DATA_FORMAT_32;
1632 case 2:
1633 return V_008F0C_BUF_DATA_FORMAT_32_32;
1634 case 3:
1635 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1636 case 4:
1637 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1638 }
1639 break;
1640 }
1641
1642 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1643 }
1644
1645 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1646 const struct util_format_description *desc,
1647 int first_non_void)
1648 {
1649 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1650 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1651
1652 switch (desc->channel[first_non_void].type) {
1653 case UTIL_FORMAT_TYPE_SIGNED:
1654 if (desc->channel[first_non_void].normalized)
1655 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1656 else if (desc->channel[first_non_void].pure_integer)
1657 return V_008F0C_BUF_NUM_FORMAT_SINT;
1658 else
1659 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1660 break;
1661 case UTIL_FORMAT_TYPE_UNSIGNED:
1662 if (desc->channel[first_non_void].normalized)
1663 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1664 else if (desc->channel[first_non_void].pure_integer)
1665 return V_008F0C_BUF_NUM_FORMAT_UINT;
1666 else
1667 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1668 break;
1669 case UTIL_FORMAT_TYPE_FLOAT:
1670 default:
1671 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1672 }
1673 }
1674
1675 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1676 {
1677 const struct util_format_description *desc;
1678 int first_non_void;
1679 unsigned data_format;
1680
1681 desc = util_format_description(format);
1682 first_non_void = util_format_get_first_non_void_channel(format);
1683 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1684 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1685 }
1686
1687 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1688 {
1689 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1690 r600_translate_colorswap(format) != ~0U;
1691 }
1692
1693 static bool si_is_zs_format_supported(enum pipe_format format)
1694 {
1695 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1696 }
1697
1698 boolean si_is_format_supported(struct pipe_screen *screen,
1699 enum pipe_format format,
1700 enum pipe_texture_target target,
1701 unsigned sample_count,
1702 unsigned usage)
1703 {
1704 unsigned retval = 0;
1705
1706 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1707 R600_ERR("r600: unsupported texture type %d\n", target);
1708 return FALSE;
1709 }
1710
1711 if (!util_format_is_supported(format, usage))
1712 return FALSE;
1713
1714 if (sample_count > 1) {
1715 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1716 return FALSE;
1717
1718 switch (sample_count) {
1719 case 2:
1720 case 4:
1721 case 8:
1722 break;
1723 default:
1724 return FALSE;
1725 }
1726 }
1727
1728 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1729 if (target == PIPE_BUFFER) {
1730 if (si_is_vertex_format_supported(screen, format))
1731 retval |= PIPE_BIND_SAMPLER_VIEW;
1732 } else {
1733 if (si_is_sampler_format_supported(screen, format))
1734 retval |= PIPE_BIND_SAMPLER_VIEW;
1735 }
1736 }
1737
1738 if ((usage & (PIPE_BIND_RENDER_TARGET |
1739 PIPE_BIND_DISPLAY_TARGET |
1740 PIPE_BIND_SCANOUT |
1741 PIPE_BIND_SHARED |
1742 PIPE_BIND_BLENDABLE)) &&
1743 si_is_colorbuffer_format_supported(format)) {
1744 retval |= usage &
1745 (PIPE_BIND_RENDER_TARGET |
1746 PIPE_BIND_DISPLAY_TARGET |
1747 PIPE_BIND_SCANOUT |
1748 PIPE_BIND_SHARED);
1749 if (!util_format_is_pure_integer(format) &&
1750 !util_format_is_depth_or_stencil(format))
1751 retval |= usage & PIPE_BIND_BLENDABLE;
1752 }
1753
1754 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1755 si_is_zs_format_supported(format)) {
1756 retval |= PIPE_BIND_DEPTH_STENCIL;
1757 }
1758
1759 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1760 si_is_vertex_format_supported(screen, format)) {
1761 retval |= PIPE_BIND_VERTEX_BUFFER;
1762 }
1763
1764 if (usage & PIPE_BIND_TRANSFER_READ)
1765 retval |= PIPE_BIND_TRANSFER_READ;
1766 if (usage & PIPE_BIND_TRANSFER_WRITE)
1767 retval |= PIPE_BIND_TRANSFER_WRITE;
1768
1769 return retval == usage;
1770 }
1771
1772 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1773 {
1774 unsigned tile_mode_index = 0;
1775
1776 if (stencil) {
1777 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1778 } else {
1779 tile_mode_index = rtex->surface.tiling_index[level];
1780 }
1781 return tile_mode_index;
1782 }
1783
1784 /*
1785 * framebuffer handling
1786 */
1787
1788 static void si_initialize_color_surface(struct si_context *sctx,
1789 struct r600_surface *surf)
1790 {
1791 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1792 unsigned level = surf->base.u.tex.level;
1793 uint64_t offset = rtex->surface.level[level].offset;
1794 unsigned pitch, slice;
1795 unsigned color_info, color_attrib, color_pitch, color_view;
1796 unsigned tile_mode_index;
1797 unsigned format, swap, ntype, endian;
1798 const struct util_format_description *desc;
1799 int i;
1800 unsigned blend_clamp = 0, blend_bypass = 0;
1801 unsigned max_comp_size;
1802
1803 /* Layered rendering doesn't work with LINEAR_GENERAL.
1804 * (LINEAR_ALIGNED and others work) */
1805 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1806 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1807 offset += rtex->surface.level[level].slice_size *
1808 surf->base.u.tex.first_layer;
1809 color_view = 0;
1810 } else {
1811 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1812 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1813 }
1814
1815 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1816 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1817 if (slice) {
1818 slice = slice - 1;
1819 }
1820
1821 tile_mode_index = si_tile_mode_index(rtex, level, false);
1822
1823 desc = util_format_description(surf->base.format);
1824 for (i = 0; i < 4; i++) {
1825 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1826 break;
1827 }
1828 }
1829 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1830 ntype = V_028C70_NUMBER_FLOAT;
1831 } else {
1832 ntype = V_028C70_NUMBER_UNORM;
1833 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1834 ntype = V_028C70_NUMBER_SRGB;
1835 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1836 if (desc->channel[i].pure_integer) {
1837 ntype = V_028C70_NUMBER_SINT;
1838 } else {
1839 assert(desc->channel[i].normalized);
1840 ntype = V_028C70_NUMBER_SNORM;
1841 }
1842 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1843 if (desc->channel[i].pure_integer) {
1844 ntype = V_028C70_NUMBER_UINT;
1845 } else {
1846 assert(desc->channel[i].normalized);
1847 ntype = V_028C70_NUMBER_UNORM;
1848 }
1849 }
1850 }
1851
1852 format = si_translate_colorformat(surf->base.format);
1853 if (format == V_028C70_COLOR_INVALID) {
1854 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1855 }
1856 assert(format != V_028C70_COLOR_INVALID);
1857 swap = r600_translate_colorswap(surf->base.format);
1858 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1859 endian = V_028C70_ENDIAN_NONE;
1860 } else {
1861 endian = si_colorformat_endian_swap(format);
1862 }
1863
1864 /* blend clamp should be set for all NORM/SRGB types */
1865 if (ntype == V_028C70_NUMBER_UNORM ||
1866 ntype == V_028C70_NUMBER_SNORM ||
1867 ntype == V_028C70_NUMBER_SRGB)
1868 blend_clamp = 1;
1869
1870 /* set blend bypass according to docs if SINT/UINT or
1871 8/24 COLOR variants */
1872 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1873 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1874 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1875 blend_clamp = 0;
1876 blend_bypass = 1;
1877 }
1878
1879 color_info = S_028C70_FORMAT(format) |
1880 S_028C70_COMP_SWAP(swap) |
1881 S_028C70_BLEND_CLAMP(blend_clamp) |
1882 S_028C70_BLEND_BYPASS(blend_bypass) |
1883 S_028C70_NUMBER_TYPE(ntype) |
1884 S_028C70_ENDIAN(endian);
1885
1886 color_pitch = S_028C64_TILE_MAX(pitch);
1887
1888 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1889 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1890
1891 if (rtex->resource.b.b.nr_samples > 1) {
1892 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1893
1894 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1895 S_028C74_NUM_FRAGMENTS(log_samples);
1896
1897 if (rtex->fmask.size) {
1898 color_info |= S_028C70_COMPRESSION(1);
1899 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1900
1901 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1902
1903 if (sctx->b.chip_class == SI) {
1904 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1905 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1906 }
1907 if (sctx->b.chip_class >= CIK) {
1908 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1909 }
1910 }
1911 }
1912
1913 offset += rtex->resource.gpu_address;
1914
1915 surf->cb_color_base = offset >> 8;
1916 surf->cb_color_pitch = color_pitch;
1917 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1918 surf->cb_color_view = color_view;
1919 surf->cb_color_info = color_info;
1920 surf->cb_color_attrib = color_attrib;
1921
1922 if (sctx->b.chip_class >= VI)
1923 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1924
1925 if (rtex->fmask.size) {
1926 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1927 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1928 } else {
1929 /* This must be set for fast clear to work without FMASK. */
1930 surf->cb_color_fmask = surf->cb_color_base;
1931 surf->cb_color_fmask_slice = surf->cb_color_slice;
1932 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1933
1934 if (sctx->b.chip_class == SI) {
1935 unsigned bankh = util_logbase2(rtex->surface.bankh);
1936 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1937 }
1938
1939 if (sctx->b.chip_class >= CIK) {
1940 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1941 }
1942 }
1943
1944 /* Determine pixel shader export format */
1945 max_comp_size = si_colorformat_max_comp_size(format);
1946 if (ntype == V_028C70_NUMBER_SRGB ||
1947 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1948 max_comp_size <= 10) ||
1949 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1950 surf->export_16bpc = true;
1951 }
1952
1953 surf->color_initialized = true;
1954 }
1955
1956 static void si_init_depth_surface(struct si_context *sctx,
1957 struct r600_surface *surf)
1958 {
1959 struct si_screen *sscreen = sctx->screen;
1960 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1961 unsigned level = surf->base.u.tex.level;
1962 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1963 unsigned format, tile_mode_index, array_mode;
1964 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1965 uint32_t z_info, s_info, db_depth_info;
1966 uint64_t z_offs, s_offs;
1967 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1968
1969 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1970 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1971 case PIPE_FORMAT_X8Z24_UNORM:
1972 case PIPE_FORMAT_Z24X8_UNORM:
1973 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1974 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1975 break;
1976 case PIPE_FORMAT_Z32_FLOAT:
1977 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1978 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1979 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1980 break;
1981 case PIPE_FORMAT_Z16_UNORM:
1982 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1983 break;
1984 default:
1985 assert(0);
1986 }
1987
1988 format = si_translate_dbformat(rtex->resource.b.b.format);
1989
1990 if (format == V_028040_Z_INVALID) {
1991 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1992 }
1993 assert(format != V_028040_Z_INVALID);
1994
1995 s_offs = z_offs = rtex->resource.gpu_address;
1996 z_offs += rtex->surface.level[level].offset;
1997 s_offs += rtex->surface.stencil_level[level].offset;
1998
1999 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2000
2001 z_info = S_028040_FORMAT(format);
2002 if (rtex->resource.b.b.nr_samples > 1) {
2003 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2004 }
2005
2006 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2007 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2008 else
2009 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2010
2011 if (sctx->b.chip_class >= CIK) {
2012 switch (rtex->surface.level[level].mode) {
2013 case RADEON_SURF_MODE_2D:
2014 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2015 break;
2016 case RADEON_SURF_MODE_1D:
2017 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2018 case RADEON_SURF_MODE_LINEAR:
2019 default:
2020 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2021 break;
2022 }
2023 tile_split = rtex->surface.tile_split;
2024 stile_split = rtex->surface.stencil_tile_split;
2025 macro_aspect = rtex->surface.mtilea;
2026 bankw = rtex->surface.bankw;
2027 bankh = rtex->surface.bankh;
2028 tile_split = cik_tile_split(tile_split);
2029 stile_split = cik_tile_split(stile_split);
2030 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2031 bankw = cik_bank_wh(bankw);
2032 bankh = cik_bank_wh(bankh);
2033 nbanks = si_num_banks(sscreen, rtex);
2034 tile_mode_index = si_tile_mode_index(rtex, level, false);
2035 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2036
2037 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2038 S_02803C_PIPE_CONFIG(pipe_config) |
2039 S_02803C_BANK_WIDTH(bankw) |
2040 S_02803C_BANK_HEIGHT(bankh) |
2041 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2042 S_02803C_NUM_BANKS(nbanks);
2043 z_info |= S_028040_TILE_SPLIT(tile_split);
2044 s_info |= S_028044_TILE_SPLIT(stile_split);
2045 } else {
2046 tile_mode_index = si_tile_mode_index(rtex, level, false);
2047 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2048 tile_mode_index = si_tile_mode_index(rtex, level, true);
2049 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2050 }
2051
2052 /* HiZ aka depth buffer htile */
2053 /* use htile only for first level */
2054 if (rtex->htile_buffer && !level) {
2055 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2056 S_028040_ALLOW_EXPCLEAR(1);
2057
2058 /* Use all of the htile_buffer for depth, because we don't
2059 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2060 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2061
2062 uint64_t va = rtex->htile_buffer->gpu_address;
2063 db_htile_data_base = va >> 8;
2064 db_htile_surface = S_028ABC_FULL_CACHE(1);
2065 } else {
2066 db_htile_data_base = 0;
2067 db_htile_surface = 0;
2068 }
2069
2070 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2071
2072 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2073 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2074 surf->db_htile_data_base = db_htile_data_base;
2075 surf->db_depth_info = db_depth_info;
2076 surf->db_z_info = z_info;
2077 surf->db_stencil_info = s_info;
2078 surf->db_depth_base = z_offs >> 8;
2079 surf->db_stencil_base = s_offs >> 8;
2080 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2081 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2082 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2083 levelinfo->nblk_y) / 64 - 1);
2084 surf->db_htile_surface = db_htile_surface;
2085 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2086
2087 surf->depth_initialized = true;
2088 }
2089
2090 static void si_set_framebuffer_state(struct pipe_context *ctx,
2091 const struct pipe_framebuffer_state *state)
2092 {
2093 struct si_context *sctx = (struct si_context *)ctx;
2094 struct pipe_constant_buffer constbuf = {0};
2095 struct r600_surface *surf = NULL;
2096 struct r600_texture *rtex;
2097 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2098 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2099 int i;
2100
2101 /* Only flush TC when changing the framebuffer state, because
2102 * the only client not using TC that can change textures is
2103 * the framebuffer.
2104 *
2105 * Flush all CB and DB caches here because all buffers can be used
2106 * for write by both TC (with shader image stores) and CB/DB.
2107 */
2108 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2109 SI_CONTEXT_INV_TC_L2 |
2110 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2111
2112 /* Take the maximum of the old and new count. If the new count is lower,
2113 * dirtying is needed to disable the unbound colorbuffers.
2114 */
2115 sctx->framebuffer.dirty_cbufs |=
2116 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2117 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2118
2119 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2120
2121 sctx->framebuffer.export_16bpc = 0;
2122 sctx->framebuffer.compressed_cb_mask = 0;
2123 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2124 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2125 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2126 util_format_is_pure_integer(state->cbufs[0]->format);
2127
2128 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2129 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2130
2131 for (i = 0; i < state->nr_cbufs; i++) {
2132 if (!state->cbufs[i])
2133 continue;
2134
2135 surf = (struct r600_surface*)state->cbufs[i];
2136 rtex = (struct r600_texture*)surf->base.texture;
2137
2138 if (!surf->color_initialized) {
2139 si_initialize_color_surface(sctx, surf);
2140 }
2141
2142 if (surf->export_16bpc) {
2143 sctx->framebuffer.export_16bpc |= 1 << i;
2144 }
2145
2146 if (rtex->fmask.size && rtex->cmask.size) {
2147 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2148 }
2149 r600_context_add_resource_size(ctx, surf->base.texture);
2150 }
2151 /* Set the 16BPC export for possible dual-src blending. */
2152 if (i == 1 && surf && surf->export_16bpc) {
2153 sctx->framebuffer.export_16bpc |= 1 << 1;
2154 }
2155
2156 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2157
2158 if (state->zsbuf) {
2159 surf = (struct r600_surface*)state->zsbuf;
2160
2161 if (!surf->depth_initialized) {
2162 si_init_depth_surface(sctx, surf);
2163 }
2164 r600_context_add_resource_size(ctx, surf->base.texture);
2165 }
2166
2167 si_update_fb_rs_state(sctx);
2168 si_update_fb_blend_state(sctx);
2169
2170 sctx->framebuffer.atom.num_dw = state->nr_cbufs*16 + (8 - state->nr_cbufs)*3;
2171 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2172 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2173 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2174 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2175
2176 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2177 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2178 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2179
2180 /* Set sample locations as fragment shader constants. */
2181 switch (sctx->framebuffer.nr_samples) {
2182 case 1:
2183 constbuf.user_buffer = sctx->b.sample_locations_1x;
2184 break;
2185 case 2:
2186 constbuf.user_buffer = sctx->b.sample_locations_2x;
2187 break;
2188 case 4:
2189 constbuf.user_buffer = sctx->b.sample_locations_4x;
2190 break;
2191 case 8:
2192 constbuf.user_buffer = sctx->b.sample_locations_8x;
2193 break;
2194 case 16:
2195 constbuf.user_buffer = sctx->b.sample_locations_16x;
2196 break;
2197 default:
2198 assert(0);
2199 }
2200 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2201 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2202 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2203
2204 /* Smoothing (only possible with nr_samples == 1) uses the same
2205 * sample locations as the MSAA it simulates.
2206 *
2207 * Therefore, don't update the sample locations when
2208 * transitioning from no AA to smoothing-equivalent AA, and
2209 * vice versa.
2210 */
2211 if ((sctx->framebuffer.nr_samples != 1 ||
2212 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2213 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2214 old_nr_samples != 1))
2215 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2216 }
2217 }
2218
2219 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2220 {
2221 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2222 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2223 unsigned i, nr_cbufs = state->nr_cbufs;
2224 struct r600_texture *tex = NULL;
2225 struct r600_surface *cb = NULL;
2226
2227 /* Colorbuffers. */
2228 for (i = 0; i < nr_cbufs; i++) {
2229 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2230 continue;
2231
2232 cb = (struct r600_surface*)state->cbufs[i];
2233 if (!cb) {
2234 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2235 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2236 continue;
2237 }
2238
2239 tex = (struct r600_texture *)cb->base.texture;
2240 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2241 &tex->resource, RADEON_USAGE_READWRITE,
2242 tex->surface.nsamples > 1 ?
2243 RADEON_PRIO_COLOR_BUFFER_MSAA :
2244 RADEON_PRIO_COLOR_BUFFER);
2245
2246 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2247 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2248 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2249 RADEON_PRIO_COLOR_META);
2250 }
2251
2252 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2253 sctx->b.chip_class >= VI ? 14 : 13);
2254 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2255 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2256 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2257 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2258 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2259 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2260 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2261 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2262 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2263 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2264 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2265 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2266 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2267
2268 if (sctx->b.chip_class >= VI)
2269 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2270 }
2271 /* set CB_COLOR1_INFO for possible dual-src blending */
2272 if (i == 1 && state->cbufs[0] &&
2273 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2274 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2275 cb->cb_color_info | tex->cb_color_info);
2276 i++;
2277 }
2278 for (; i < 8 ; i++)
2279 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2280 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2281
2282 /* ZS buffer. */
2283 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2284 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2285 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2286
2287 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2288 &rtex->resource, RADEON_USAGE_READWRITE,
2289 zb->base.texture->nr_samples > 1 ?
2290 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2291 RADEON_PRIO_DEPTH_BUFFER);
2292
2293 if (zb->db_htile_data_base) {
2294 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2295 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2296 RADEON_PRIO_DEPTH_META);
2297 }
2298
2299 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2300 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2301
2302 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2303 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2304 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2305 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2306 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2307 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2308 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2309 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2310 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2311 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2312 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2313
2314 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2315 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2316 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2317 zb->pa_su_poly_offset_db_fmt_cntl);
2318 } else if (sctx->framebuffer.dirty_zsbuf) {
2319 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2320 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2321 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2322 }
2323
2324 /* Framebuffer dimensions. */
2325 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2326 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2327 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2328
2329 sctx->framebuffer.dirty_cbufs = 0;
2330 sctx->framebuffer.dirty_zsbuf = false;
2331 }
2332
2333 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2334 struct r600_atom *atom)
2335 {
2336 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2337 unsigned nr_samples = sctx->framebuffer.nr_samples;
2338
2339 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2340 SI_NUM_SMOOTH_AA_SAMPLES);
2341 }
2342
2343 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2344 {
2345 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2346
2347 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2348 sctx->ps_iter_samples,
2349 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2350 }
2351
2352
2353 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2354 {
2355 struct si_context *sctx = (struct si_context *)ctx;
2356
2357 if (sctx->ps_iter_samples == min_samples)
2358 return;
2359
2360 sctx->ps_iter_samples = min_samples;
2361
2362 if (sctx->framebuffer.nr_samples > 1)
2363 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2364 }
2365
2366 /*
2367 * Samplers
2368 */
2369
2370 /**
2371 * Create a sampler view.
2372 *
2373 * @param ctx context
2374 * @param texture texture
2375 * @param state sampler view template
2376 * @param width0 width0 override (for compressed textures as int)
2377 * @param height0 height0 override (for compressed textures as int)
2378 * @param force_level set the base address to the level (for compressed textures)
2379 */
2380 struct pipe_sampler_view *
2381 si_create_sampler_view_custom(struct pipe_context *ctx,
2382 struct pipe_resource *texture,
2383 const struct pipe_sampler_view *state,
2384 unsigned width0, unsigned height0,
2385 unsigned force_level)
2386 {
2387 struct si_context *sctx = (struct si_context*)ctx;
2388 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2389 struct r600_texture *tmp = (struct r600_texture*)texture;
2390 const struct util_format_description *desc;
2391 unsigned format, num_format, base_level, first_level, last_level;
2392 uint32_t pitch = 0;
2393 unsigned char state_swizzle[4], swizzle[4];
2394 unsigned height, depth, width;
2395 enum pipe_format pipe_format = state->format;
2396 struct radeon_surf_level *surflevel;
2397 int first_non_void;
2398 uint64_t va;
2399
2400 if (view == NULL)
2401 return NULL;
2402
2403 /* initialize base object */
2404 view->base = *state;
2405 view->base.texture = NULL;
2406 view->base.reference.count = 1;
2407 view->base.context = ctx;
2408
2409 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2410 if (!texture) {
2411 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2412 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2413 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2414 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2415 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2416 return &view->base;
2417 }
2418
2419 pipe_resource_reference(&view->base.texture, texture);
2420 view->resource = &tmp->resource;
2421
2422 /* Buffer resource. */
2423 if (texture->target == PIPE_BUFFER) {
2424 unsigned stride, num_records;
2425
2426 desc = util_format_description(state->format);
2427 first_non_void = util_format_get_first_non_void_channel(state->format);
2428 stride = desc->block.bits / 8;
2429 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2430 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2431 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2432
2433 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2434 num_records = MIN2(num_records, texture->width0 / stride);
2435
2436 if (sctx->b.chip_class >= VI)
2437 num_records *= stride;
2438
2439 view->state[4] = va;
2440 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2441 S_008F04_STRIDE(stride);
2442 view->state[6] = num_records;
2443 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2444 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2445 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2446 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2447 S_008F0C_NUM_FORMAT(num_format) |
2448 S_008F0C_DATA_FORMAT(format);
2449
2450 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2451 return &view->base;
2452 }
2453
2454 state_swizzle[0] = state->swizzle_r;
2455 state_swizzle[1] = state->swizzle_g;
2456 state_swizzle[2] = state->swizzle_b;
2457 state_swizzle[3] = state->swizzle_a;
2458
2459 surflevel = tmp->surface.level;
2460
2461 /* Texturing with separate depth and stencil. */
2462 if (tmp->is_depth && !tmp->is_flushing_texture) {
2463 switch (pipe_format) {
2464 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2465 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2466 break;
2467 case PIPE_FORMAT_X8Z24_UNORM:
2468 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2469 /* Z24 is always stored like this. */
2470 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2471 break;
2472 case PIPE_FORMAT_X24S8_UINT:
2473 case PIPE_FORMAT_S8X24_UINT:
2474 case PIPE_FORMAT_X32_S8X24_UINT:
2475 pipe_format = PIPE_FORMAT_S8_UINT;
2476 surflevel = tmp->surface.stencil_level;
2477 break;
2478 default:;
2479 }
2480 }
2481
2482 desc = util_format_description(pipe_format);
2483
2484 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2485 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2486 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2487
2488 switch (pipe_format) {
2489 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2490 case PIPE_FORMAT_X24S8_UINT:
2491 case PIPE_FORMAT_X32_S8X24_UINT:
2492 case PIPE_FORMAT_X8Z24_UNORM:
2493 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2494 break;
2495 default:
2496 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2497 }
2498 } else {
2499 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2500 }
2501
2502 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2503
2504 switch (pipe_format) {
2505 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2506 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2507 break;
2508 default:
2509 if (first_non_void < 0) {
2510 if (util_format_is_compressed(pipe_format)) {
2511 switch (pipe_format) {
2512 case PIPE_FORMAT_DXT1_SRGB:
2513 case PIPE_FORMAT_DXT1_SRGBA:
2514 case PIPE_FORMAT_DXT3_SRGBA:
2515 case PIPE_FORMAT_DXT5_SRGBA:
2516 case PIPE_FORMAT_BPTC_SRGBA:
2517 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2518 break;
2519 case PIPE_FORMAT_RGTC1_SNORM:
2520 case PIPE_FORMAT_LATC1_SNORM:
2521 case PIPE_FORMAT_RGTC2_SNORM:
2522 case PIPE_FORMAT_LATC2_SNORM:
2523 /* implies float, so use SNORM/UNORM to determine
2524 whether data is signed or not */
2525 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2526 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2527 break;
2528 default:
2529 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2530 break;
2531 }
2532 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2533 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2534 } else {
2535 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2536 }
2537 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2538 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2539 } else {
2540 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2541
2542 switch (desc->channel[first_non_void].type) {
2543 case UTIL_FORMAT_TYPE_FLOAT:
2544 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2545 break;
2546 case UTIL_FORMAT_TYPE_SIGNED:
2547 if (desc->channel[first_non_void].normalized)
2548 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2549 else if (desc->channel[first_non_void].pure_integer)
2550 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2551 else
2552 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2553 break;
2554 case UTIL_FORMAT_TYPE_UNSIGNED:
2555 if (desc->channel[first_non_void].normalized)
2556 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2557 else if (desc->channel[first_non_void].pure_integer)
2558 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2559 else
2560 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2561 }
2562 }
2563 }
2564
2565 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2566 if (format == ~0) {
2567 format = 0;
2568 }
2569
2570 base_level = 0;
2571 first_level = state->u.tex.first_level;
2572 last_level = state->u.tex.last_level;
2573 width = width0;
2574 height = height0;
2575 depth = texture->depth0;
2576
2577 if (force_level) {
2578 assert(force_level == first_level &&
2579 force_level == last_level);
2580 base_level = force_level;
2581 first_level = 0;
2582 last_level = 0;
2583 width = u_minify(width, force_level);
2584 height = u_minify(height, force_level);
2585 depth = u_minify(depth, force_level);
2586 }
2587
2588 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2589
2590 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2591 height = 1;
2592 depth = texture->array_size;
2593 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2594 depth = texture->array_size;
2595 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2596 depth = texture->array_size / 6;
2597
2598 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2599
2600 view->state[0] = va >> 8;
2601 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2602 S_008F14_DATA_FORMAT(format) |
2603 S_008F14_NUM_FORMAT(num_format));
2604 view->state[2] = (S_008F18_WIDTH(width - 1) |
2605 S_008F18_HEIGHT(height - 1));
2606 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2607 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2608 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2609 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2610 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2611 0 : first_level) |
2612 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2613 util_logbase2(texture->nr_samples) :
2614 last_level) |
2615 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2616 S_008F1C_POW2_PAD(texture->last_level > 0) |
2617 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2618 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2619 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2620 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2621 view->state[6] = 0;
2622 view->state[7] = 0;
2623
2624 /* Initialize the sampler view for FMASK. */
2625 if (tmp->fmask.size) {
2626 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2627 uint32_t fmask_format;
2628
2629 switch (texture->nr_samples) {
2630 case 2:
2631 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2632 break;
2633 case 4:
2634 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2635 break;
2636 case 8:
2637 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2638 break;
2639 default:
2640 assert(0);
2641 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2642 }
2643
2644 view->fmask_state[0] = va >> 8;
2645 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2646 S_008F14_DATA_FORMAT(fmask_format) |
2647 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2648 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2649 S_008F18_HEIGHT(height - 1);
2650 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2651 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2652 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2653 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2654 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2655 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2656 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2657 S_008F20_PITCH(tmp->fmask.pitch - 1);
2658 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2659 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2660 view->fmask_state[6] = 0;
2661 view->fmask_state[7] = 0;
2662 }
2663
2664 return &view->base;
2665 }
2666
2667 static struct pipe_sampler_view *
2668 si_create_sampler_view(struct pipe_context *ctx,
2669 struct pipe_resource *texture,
2670 const struct pipe_sampler_view *state)
2671 {
2672 return si_create_sampler_view_custom(ctx, texture, state,
2673 texture ? texture->width0 : 0,
2674 texture ? texture->height0 : 0, 0);
2675 }
2676
2677 static void si_sampler_view_destroy(struct pipe_context *ctx,
2678 struct pipe_sampler_view *state)
2679 {
2680 struct si_sampler_view *view = (struct si_sampler_view *)state;
2681
2682 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2683 LIST_DELINIT(&view->list);
2684
2685 pipe_resource_reference(&state->texture, NULL);
2686 FREE(view);
2687 }
2688
2689 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2690 {
2691 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2692 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2693 (linear_filter &&
2694 (wrap == PIPE_TEX_WRAP_CLAMP ||
2695 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2696 }
2697
2698 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2699 {
2700 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2701 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2702
2703 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2704 state->border_color.ui[2] || state->border_color.ui[3]) &&
2705 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2706 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2707 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2708 }
2709
2710 static void *si_create_sampler_state(struct pipe_context *ctx,
2711 const struct pipe_sampler_state *state)
2712 {
2713 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2714 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2715 unsigned border_color_type;
2716
2717 if (rstate == NULL) {
2718 return NULL;
2719 }
2720
2721 if (sampler_state_needs_border_color(state))
2722 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2723 else
2724 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2725
2726 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2727 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2728 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2729 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2730 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2731 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2732 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2733 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2734 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2735 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2736 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2737 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2738 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2739 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2740
2741 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2742 memcpy(rstate->border_color, state->border_color.ui,
2743 sizeof(rstate->border_color));
2744 }
2745
2746 return rstate;
2747 }
2748
2749 /* Upload border colors and update the pointers in resource descriptors.
2750 * There can only be 4096 border colors per context.
2751 *
2752 * XXX: This is broken if the buffer gets reallocated.
2753 */
2754 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2755 void **states)
2756 {
2757 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2758 uint32_t *border_color_table = NULL;
2759 int i, j;
2760
2761 for (i = 0; i < count; i++) {
2762 if (rstates[i] &&
2763 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2764 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2765 if (!sctx->border_color_table ||
2766 ((sctx->border_color_offset + count - i) &
2767 C_008F3C_BORDER_COLOR_PTR)) {
2768 r600_resource_reference(&sctx->border_color_table, NULL);
2769 sctx->border_color_offset = 0;
2770
2771 sctx->border_color_table =
2772 si_resource_create_custom(&sctx->screen->b.b,
2773 PIPE_USAGE_DYNAMIC,
2774 4096 * 4 * 4);
2775 }
2776
2777 if (!border_color_table) {
2778 border_color_table =
2779 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2780 sctx->b.rings.gfx.cs,
2781 PIPE_TRANSFER_WRITE |
2782 PIPE_TRANSFER_UNSYNCHRONIZED);
2783 }
2784
2785 for (j = 0; j < 4; j++) {
2786 border_color_table[4 * sctx->border_color_offset + j] =
2787 util_le32_to_cpu(rstates[i]->border_color[j]);
2788 }
2789
2790 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2791 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2792 }
2793 }
2794
2795 if (border_color_table) {
2796 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2797
2798 uint64_t va_offset = sctx->border_color_table->gpu_address;
2799
2800 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2801 if (sctx->b.chip_class >= CIK)
2802 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2803 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2804 RADEON_PRIO_SHADER_DATA);
2805 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2806 }
2807 }
2808
2809 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2810 unsigned start, unsigned count,
2811 void **states)
2812 {
2813 struct si_context *sctx = (struct si_context *)ctx;
2814
2815 if (!count || shader >= SI_NUM_SHADERS)
2816 return;
2817
2818 si_set_border_colors(sctx, count, states);
2819 si_set_sampler_descriptors(sctx, shader, start, count, states);
2820 }
2821
2822 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2823 {
2824 struct si_context *sctx = (struct si_context *)ctx;
2825 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2826 struct si_pm4_state *pm4 = &state->pm4;
2827 uint16_t mask = sample_mask;
2828
2829 if (state == NULL)
2830 return;
2831
2832 state->sample_mask = mask;
2833 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2834 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2835
2836 si_pm4_set_state(sctx, sample_mask, state);
2837 }
2838
2839 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2840 {
2841 free(state);
2842 }
2843
2844 /*
2845 * Vertex elements & buffers
2846 */
2847
2848 static void *si_create_vertex_elements(struct pipe_context *ctx,
2849 unsigned count,
2850 const struct pipe_vertex_element *elements)
2851 {
2852 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2853 int i;
2854
2855 assert(count < SI_MAX_ATTRIBS);
2856 if (!v)
2857 return NULL;
2858
2859 v->count = count;
2860 for (i = 0; i < count; ++i) {
2861 const struct util_format_description *desc;
2862 unsigned data_format, num_format;
2863 int first_non_void;
2864
2865 desc = util_format_description(elements[i].src_format);
2866 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2867 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2868 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2869
2870 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2871 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2872 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2873 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2874 S_008F0C_NUM_FORMAT(num_format) |
2875 S_008F0C_DATA_FORMAT(data_format);
2876 v->format_size[i] = desc->block.bits / 8;
2877 }
2878 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2879
2880 return v;
2881 }
2882
2883 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2884 {
2885 struct si_context *sctx = (struct si_context *)ctx;
2886 struct si_vertex_element *v = (struct si_vertex_element*)state;
2887
2888 sctx->vertex_elements = v;
2889 sctx->vertex_buffers_dirty = true;
2890 }
2891
2892 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2893 {
2894 struct si_context *sctx = (struct si_context *)ctx;
2895
2896 if (sctx->vertex_elements == state)
2897 sctx->vertex_elements = NULL;
2898 FREE(state);
2899 }
2900
2901 static void si_set_vertex_buffers(struct pipe_context *ctx,
2902 unsigned start_slot, unsigned count,
2903 const struct pipe_vertex_buffer *buffers)
2904 {
2905 struct si_context *sctx = (struct si_context *)ctx;
2906 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2907 int i;
2908
2909 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2910
2911 if (buffers) {
2912 for (i = 0; i < count; i++) {
2913 const struct pipe_vertex_buffer *src = buffers + i;
2914 struct pipe_vertex_buffer *dsti = dst + i;
2915
2916 pipe_resource_reference(&dsti->buffer, src->buffer);
2917 dsti->buffer_offset = src->buffer_offset;
2918 dsti->stride = src->stride;
2919 r600_context_add_resource_size(ctx, src->buffer);
2920 }
2921 } else {
2922 for (i = 0; i < count; i++) {
2923 pipe_resource_reference(&dst[i].buffer, NULL);
2924 }
2925 }
2926 sctx->vertex_buffers_dirty = true;
2927 }
2928
2929 static void si_set_index_buffer(struct pipe_context *ctx,
2930 const struct pipe_index_buffer *ib)
2931 {
2932 struct si_context *sctx = (struct si_context *)ctx;
2933
2934 if (ib) {
2935 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2936 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2937 r600_context_add_resource_size(ctx, ib->buffer);
2938 } else {
2939 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2940 }
2941 }
2942
2943 /*
2944 * Misc
2945 */
2946 static void si_set_polygon_stipple(struct pipe_context *ctx,
2947 const struct pipe_poly_stipple *state)
2948 {
2949 struct si_context *sctx = (struct si_context *)ctx;
2950 struct pipe_resource *tex;
2951 struct pipe_sampler_view *view;
2952 bool is_zero = true;
2953 bool is_one = true;
2954 int i;
2955
2956 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2957 * the resource is NULL/invalid. Take advantage of this fact and skip
2958 * texture allocation if the stipple pattern is constant.
2959 *
2960 * This is an optimization for the common case when stippling isn't
2961 * used but set_polygon_stipple is still called by st/mesa.
2962 */
2963 for (i = 0; i < Elements(state->stipple); i++) {
2964 is_zero = is_zero && state->stipple[i] == 0;
2965 is_one = is_one && state->stipple[i] == 0xffffffff;
2966 }
2967
2968 if (is_zero || is_one) {
2969 struct pipe_sampler_view templ = {{0}};
2970
2971 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2972 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2973 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2974 /* The pattern should be inverted in the texture. */
2975 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2976
2977 view = ctx->create_sampler_view(ctx, NULL, &templ);
2978 } else {
2979 /* Create a new texture. */
2980 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2981 if (!tex)
2982 return;
2983
2984 view = util_pstipple_create_sampler_view(ctx, tex);
2985 pipe_resource_reference(&tex, NULL);
2986 }
2987
2988 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2989 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2990 pipe_sampler_view_reference(&view, NULL);
2991
2992 /* Bind the sampler state if needed. */
2993 if (!sctx->pstipple_sampler_state) {
2994 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2995 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2996 SI_POLY_STIPPLE_SAMPLER, 1,
2997 &sctx->pstipple_sampler_state);
2998 }
2999 }
3000
3001 static void si_set_tess_state(struct pipe_context *ctx,
3002 const float default_outer_level[4],
3003 const float default_inner_level[2])
3004 {
3005 struct si_context *sctx = (struct si_context *)ctx;
3006 struct pipe_constant_buffer cb;
3007 float array[8];
3008
3009 memcpy(array, default_outer_level, sizeof(float) * 4);
3010 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3011
3012 cb.buffer = NULL;
3013 cb.user_buffer = NULL;
3014 cb.buffer_size = sizeof(array);
3015
3016 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3017 (void*)array, sizeof(array),
3018 &cb.buffer_offset);
3019
3020 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3021 SI_DRIVER_STATE_CONST_BUF, &cb);
3022 pipe_resource_reference(&cb.buffer, NULL);
3023 }
3024
3025 static void si_texture_barrier(struct pipe_context *ctx)
3026 {
3027 struct si_context *sctx = (struct si_context *)ctx;
3028
3029 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3030 SI_CONTEXT_INV_TC_L2 |
3031 SI_CONTEXT_FLUSH_AND_INV_CB;
3032 }
3033
3034 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3035 {
3036 struct pipe_blend_state blend;
3037
3038 memset(&blend, 0, sizeof(blend));
3039 blend.independent_blend_enable = true;
3040 blend.rt[0].colormask = 0xf;
3041 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3042 }
3043
3044 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3045 bool include_draw_vbo)
3046 {
3047 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3048 }
3049
3050 static void si_init_config(struct si_context *sctx);
3051
3052 void si_init_state_functions(struct si_context *sctx)
3053 {
3054 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3055 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3056
3057 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush, 24);
3058 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
3059 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs, 18);
3060 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
3061 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config, 10);
3062 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
3063 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors, 16*4);
3064 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports, 16*8);
3065
3066 sctx->b.b.create_blend_state = si_create_blend_state;
3067 sctx->b.b.bind_blend_state = si_bind_blend_state;
3068 sctx->b.b.delete_blend_state = si_delete_blend_state;
3069 sctx->b.b.set_blend_color = si_set_blend_color;
3070
3071 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3072 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3073 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3074
3075 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3076 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3077 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3078
3079 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3080 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3081 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3082 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3083
3084 sctx->b.b.set_clip_state = si_set_clip_state;
3085 sctx->b.b.set_scissor_states = si_set_scissor_states;
3086 sctx->b.b.set_viewport_states = si_set_viewport_states;
3087 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3088
3089 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3090 sctx->b.b.get_sample_position = cayman_get_sample_position;
3091
3092 sctx->b.b.create_sampler_state = si_create_sampler_state;
3093 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3094 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3095
3096 sctx->b.b.create_sampler_view = si_create_sampler_view;
3097 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3098
3099 sctx->b.b.set_sample_mask = si_set_sample_mask;
3100
3101 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3102 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3103 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3104 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3105 sctx->b.b.set_index_buffer = si_set_index_buffer;
3106
3107 sctx->b.b.texture_barrier = si_texture_barrier;
3108 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3109 sctx->b.b.set_min_samples = si_set_min_samples;
3110 sctx->b.b.set_tess_state = si_set_tess_state;
3111
3112 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3113 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3114
3115 sctx->b.b.draw_vbo = si_draw_vbo;
3116
3117 if (sctx->b.chip_class >= CIK) {
3118 sctx->b.dma_copy = cik_sdma_copy;
3119 } else {
3120 sctx->b.dma_copy = si_dma_copy;
3121 }
3122
3123 si_init_config(sctx);
3124 }
3125
3126 static void
3127 si_write_harvested_raster_configs(struct si_context *sctx,
3128 struct si_pm4_state *pm4,
3129 unsigned raster_config,
3130 unsigned raster_config_1)
3131 {
3132 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3133 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3134 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3135 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3136 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3137 unsigned rb_per_se = num_rb / num_se;
3138 unsigned se_mask[4];
3139 unsigned se;
3140
3141 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3142 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3143 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3144 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3145
3146 assert(num_se == 1 || num_se == 2 || num_se == 4);
3147 assert(sh_per_se == 1 || sh_per_se == 2);
3148 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3149
3150 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3151 * fields are for, so I'm leaving them as their default
3152 * values. */
3153
3154 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3155 (!se_mask[2] && !se_mask[3]))) {
3156 raster_config_1 &= C_028354_SE_PAIR_MAP;
3157
3158 if (!se_mask[0] && !se_mask[1]) {
3159 raster_config_1 |=
3160 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3161 } else {
3162 raster_config_1 |=
3163 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3164 }
3165 }
3166
3167 for (se = 0; se < num_se; se++) {
3168 unsigned raster_config_se = raster_config;
3169 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3170 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3171 int idx = (se / 2) * 2;
3172
3173 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3174 raster_config_se &= C_028350_SE_MAP;
3175
3176 if (!se_mask[idx]) {
3177 raster_config_se |=
3178 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3179 } else {
3180 raster_config_se |=
3181 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3182 }
3183 }
3184
3185 pkr0_mask &= rb_mask;
3186 pkr1_mask &= rb_mask;
3187 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3188 raster_config_se &= C_028350_PKR_MAP;
3189
3190 if (!pkr0_mask) {
3191 raster_config_se |=
3192 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3193 } else {
3194 raster_config_se |=
3195 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3196 }
3197 }
3198
3199 if (rb_per_se >= 2) {
3200 unsigned rb0_mask = 1 << (se * rb_per_se);
3201 unsigned rb1_mask = rb0_mask << 1;
3202
3203 rb0_mask &= rb_mask;
3204 rb1_mask &= rb_mask;
3205 if (!rb0_mask || !rb1_mask) {
3206 raster_config_se &= C_028350_RB_MAP_PKR0;
3207
3208 if (!rb0_mask) {
3209 raster_config_se |=
3210 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3211 } else {
3212 raster_config_se |=
3213 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3214 }
3215 }
3216
3217 if (rb_per_se > 2) {
3218 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3219 rb1_mask = rb0_mask << 1;
3220 rb0_mask &= rb_mask;
3221 rb1_mask &= rb_mask;
3222 if (!rb0_mask || !rb1_mask) {
3223 raster_config_se &= C_028350_RB_MAP_PKR1;
3224
3225 if (!rb0_mask) {
3226 raster_config_se |=
3227 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3228 } else {
3229 raster_config_se |=
3230 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3231 }
3232 }
3233 }
3234 }
3235
3236 /* GRBM_GFX_INDEX is privileged on VI */
3237 if (sctx->b.chip_class <= CIK)
3238 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3239 SE_INDEX(se) | SH_BROADCAST_WRITES |
3240 INSTANCE_BROADCAST_WRITES);
3241 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3242 if (sctx->b.chip_class >= CIK)
3243 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3244 }
3245
3246 /* GRBM_GFX_INDEX is privileged on VI */
3247 if (sctx->b.chip_class <= CIK)
3248 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3249 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3250 INSTANCE_BROADCAST_WRITES);
3251 }
3252
3253 static void si_init_config(struct si_context *sctx)
3254 {
3255 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3256 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3257 unsigned raster_config, raster_config_1;
3258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3259 int i;
3260
3261 if (pm4 == NULL)
3262 return;
3263
3264 si_cmd_context_control(pm4);
3265
3266 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3267 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3268
3269 /* FIXME calculate these values somehow ??? */
3270 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3271 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3272 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3273
3274 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3275 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3276 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3277
3278 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3279 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3280 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3281 if (sctx->b.chip_class < CIK)
3282 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3283 S_008A14_CLIP_VTX_REORDER_ENA(1));
3284
3285 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3286 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3287
3288 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3289
3290 for (i = 0; i < 16; i++) {
3291 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3292 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3293 }
3294
3295 switch (sctx->screen->b.family) {
3296 case CHIP_TAHITI:
3297 case CHIP_PITCAIRN:
3298 raster_config = 0x2a00126a;
3299 raster_config_1 = 0x00000000;
3300 break;
3301 case CHIP_VERDE:
3302 raster_config = 0x0000124a;
3303 raster_config_1 = 0x00000000;
3304 break;
3305 case CHIP_OLAND:
3306 raster_config = 0x00000082;
3307 raster_config_1 = 0x00000000;
3308 break;
3309 case CHIP_HAINAN:
3310 raster_config = 0x00000000;
3311 raster_config_1 = 0x00000000;
3312 break;
3313 case CHIP_BONAIRE:
3314 raster_config = 0x16000012;
3315 raster_config_1 = 0x00000000;
3316 break;
3317 case CHIP_HAWAII:
3318 raster_config = 0x3a00161a;
3319 raster_config_1 = 0x0000002e;
3320 break;
3321 case CHIP_FIJI:
3322 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3323 raster_config = 0x16000012; /* 0x3a00161a */
3324 raster_config_1 = 0x0000002a; /* 0x0000002e */
3325 break;
3326 case CHIP_TONGA:
3327 raster_config = 0x16000012;
3328 raster_config_1 = 0x0000002a;
3329 break;
3330 case CHIP_ICELAND:
3331 raster_config = 0x00000002;
3332 raster_config_1 = 0x00000000;
3333 break;
3334 case CHIP_CARRIZO:
3335 raster_config = 0x00000002;
3336 raster_config_1 = 0x00000000;
3337 break;
3338 case CHIP_KAVERI:
3339 /* KV should be 0x00000002, but that causes problems with radeon */
3340 raster_config = 0x00000000; /* 0x00000002 */
3341 raster_config_1 = 0x00000000;
3342 break;
3343 case CHIP_KABINI:
3344 case CHIP_MULLINS:
3345 raster_config = 0x00000000;
3346 raster_config_1 = 0x00000000;
3347 break;
3348 default:
3349 fprintf(stderr,
3350 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3351 raster_config = 0x00000000;
3352 raster_config_1 = 0x00000000;
3353 break;
3354 }
3355
3356 /* Always use the default config when all backends are enabled
3357 * (or when we failed to determine the enabled backends).
3358 */
3359 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3360 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3361 raster_config);
3362 if (sctx->b.chip_class >= CIK)
3363 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3364 raster_config_1);
3365 } else {
3366 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3367 }
3368
3369 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3370 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3371 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3372 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3373 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3374 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3375 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3376
3377 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3378 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3379 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3380 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3381 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3382 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3383 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3384 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3385 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3386 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3387 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3388 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3389 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3390
3391 /* There is a hang if stencil is used and fast stencil is enabled
3392 * regardless of whether HTILE is depth-only or not.
3393 */
3394 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3395 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3396 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3397 S_02800C_FAST_STENCIL_DISABLE(1));
3398
3399 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3400 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3401 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3402
3403 if (sctx->b.chip_class >= CIK) {
3404 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3405 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3406 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3407 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3408 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3409 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3410 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3411 }
3412
3413 if (sctx->b.chip_class >= VI) {
3414 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3415 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3416 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3417 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3418 }
3419
3420 sctx->init_config = pm4;
3421 }