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radeonsi: import cayman_msaa.c from drivers/radeon
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 /* 12.4 fixed-point */
78 static unsigned si_pack_float_12p4(float x)
79 {
80 return x <= 0 ? 0 :
81 x >= 4096 ? 0xffff : x * 16;
82 }
83
84 /*
85 * Inferred framebuffer and blender state.
86 *
87 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
88 * if there is not enough PS outputs.
89 */
90 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
91 {
92 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
93 struct si_state_blend *blend = sctx->queued.named.blend;
94 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
95 * but you never know. */
96 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
97 unsigned i;
98
99 if (blend)
100 cb_target_mask &= blend->cb_target_mask;
101
102 /* Avoid a hang that happens when dual source blending is enabled
103 * but there is not enough color outputs. This is undefined behavior,
104 * so disable color writes completely.
105 *
106 * Reproducible with Unigine Heaven 4.0 and drirc missing.
107 */
108 if (blend && blend->dual_src_blend &&
109 sctx->ps_shader.cso &&
110 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
111 cb_target_mask = 0;
112
113 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
114
115 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
116 * I think we don't have to do anything between IBs.
117 */
118 if (sctx->screen->dfsm_allowed &&
119 sctx->last_cb_target_mask != cb_target_mask) {
120 sctx->last_cb_target_mask = cb_target_mask;
121
122 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
123 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
124 }
125
126 /* RB+ register settings. */
127 if (sctx->screen->b.rbplus_allowed) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
252 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
253 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
254 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
255 } else if (sctx->screen->b.has_rbplus) {
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 }
261 }
262
263 /*
264 * Blender functions
265 */
266
267 static uint32_t si_translate_blend_function(int blend_func)
268 {
269 switch (blend_func) {
270 case PIPE_BLEND_ADD:
271 return V_028780_COMB_DST_PLUS_SRC;
272 case PIPE_BLEND_SUBTRACT:
273 return V_028780_COMB_SRC_MINUS_DST;
274 case PIPE_BLEND_REVERSE_SUBTRACT:
275 return V_028780_COMB_DST_MINUS_SRC;
276 case PIPE_BLEND_MIN:
277 return V_028780_COMB_MIN_DST_SRC;
278 case PIPE_BLEND_MAX:
279 return V_028780_COMB_MAX_DST_SRC;
280 default:
281 R600_ERR("Unknown blend function %d\n", blend_func);
282 assert(0);
283 break;
284 }
285 return 0;
286 }
287
288 static uint32_t si_translate_blend_factor(int blend_fact)
289 {
290 switch (blend_fact) {
291 case PIPE_BLENDFACTOR_ONE:
292 return V_028780_BLEND_ONE;
293 case PIPE_BLENDFACTOR_SRC_COLOR:
294 return V_028780_BLEND_SRC_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA:
296 return V_028780_BLEND_SRC_ALPHA;
297 case PIPE_BLENDFACTOR_DST_ALPHA:
298 return V_028780_BLEND_DST_ALPHA;
299 case PIPE_BLENDFACTOR_DST_COLOR:
300 return V_028780_BLEND_DST_COLOR;
301 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
302 return V_028780_BLEND_SRC_ALPHA_SATURATE;
303 case PIPE_BLENDFACTOR_CONST_COLOR:
304 return V_028780_BLEND_CONSTANT_COLOR;
305 case PIPE_BLENDFACTOR_CONST_ALPHA:
306 return V_028780_BLEND_CONSTANT_ALPHA;
307 case PIPE_BLENDFACTOR_ZERO:
308 return V_028780_BLEND_ZERO;
309 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
310 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
311 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
312 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
313 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
315 case PIPE_BLENDFACTOR_INV_DST_COLOR:
316 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
317 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
318 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
320 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_SRC1_COLOR:
322 return V_028780_BLEND_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_SRC1_ALPHA:
324 return V_028780_BLEND_SRC1_ALPHA;
325 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
326 return V_028780_BLEND_INV_SRC1_COLOR;
327 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
328 return V_028780_BLEND_INV_SRC1_ALPHA;
329 default:
330 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
331 assert(0);
332 break;
333 }
334 return 0;
335 }
336
337 static uint32_t si_translate_blend_opt_function(int blend_func)
338 {
339 switch (blend_func) {
340 case PIPE_BLEND_ADD:
341 return V_028760_OPT_COMB_ADD;
342 case PIPE_BLEND_SUBTRACT:
343 return V_028760_OPT_COMB_SUBTRACT;
344 case PIPE_BLEND_REVERSE_SUBTRACT:
345 return V_028760_OPT_COMB_REVSUBTRACT;
346 case PIPE_BLEND_MIN:
347 return V_028760_OPT_COMB_MIN;
348 case PIPE_BLEND_MAX:
349 return V_028760_OPT_COMB_MAX;
350 default:
351 return V_028760_OPT_COMB_BLEND_DISABLED;
352 }
353 }
354
355 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
356 {
357 switch (blend_fact) {
358 case PIPE_BLENDFACTOR_ZERO:
359 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
360 case PIPE_BLENDFACTOR_ONE:
361 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
362 case PIPE_BLENDFACTOR_SRC_COLOR:
363 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
364 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
365 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
367 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
368 case PIPE_BLENDFACTOR_SRC_ALPHA:
369 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
370 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
371 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
372 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
374 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
375 default:
376 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
377 }
378 }
379
380 static void si_blend_check_commutativity(struct si_screen *sscreen,
381 struct si_state_blend *blend,
382 enum pipe_blend_func func,
383 enum pipe_blendfactor src,
384 enum pipe_blendfactor dst,
385 unsigned chanmask)
386 {
387 /* Src factor is allowed when it does not depend on Dst */
388 static const uint32_t src_allowed =
389 (1u << PIPE_BLENDFACTOR_ONE) |
390 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
392 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
393 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
397 (1u << PIPE_BLENDFACTOR_ZERO) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
399 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
401 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
403 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
404
405 if (dst == PIPE_BLENDFACTOR_ONE &&
406 (src_allowed & (1u << src))) {
407 /* Addition is commutative, but floating point addition isn't
408 * associative: subtle changes can be introduced via different
409 * rounding.
410 *
411 * Out-of-order is also non-deterministic, which means that
412 * this breaks OpenGL invariance requirements. So only enable
413 * out-of-order additive blending if explicitly allowed by a
414 * setting.
415 */
416 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
417 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
418 blend->commutative_4bit |= chanmask;
419 }
420 }
421
422 /**
423 * Get rid of DST in the blend factors by commuting the operands:
424 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
425 */
426 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
427 unsigned *dst_factor, unsigned expected_dst,
428 unsigned replacement_src)
429 {
430 if (*src_factor == expected_dst &&
431 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
432 *src_factor = PIPE_BLENDFACTOR_ZERO;
433 *dst_factor = replacement_src;
434
435 /* Commuting the operands requires reversing subtractions. */
436 if (*func == PIPE_BLEND_SUBTRACT)
437 *func = PIPE_BLEND_REVERSE_SUBTRACT;
438 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
439 *func = PIPE_BLEND_SUBTRACT;
440 }
441 }
442
443 static bool si_blend_factor_uses_dst(unsigned factor)
444 {
445 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
446 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
447 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
448 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
449 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
450 }
451
452 static void *si_create_blend_state_mode(struct pipe_context *ctx,
453 const struct pipe_blend_state *state,
454 unsigned mode)
455 {
456 struct si_context *sctx = (struct si_context*)ctx;
457 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
458 struct si_pm4_state *pm4 = &blend->pm4;
459 uint32_t sx_mrt_blend_opt[8] = {0};
460 uint32_t color_control = 0;
461
462 if (!blend)
463 return NULL;
464
465 blend->alpha_to_coverage = state->alpha_to_coverage;
466 blend->alpha_to_one = state->alpha_to_one;
467 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
468 blend->logicop_enable = state->logicop_enable;
469
470 if (state->logicop_enable) {
471 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
472 } else {
473 color_control |= S_028808_ROP3(0xcc);
474 }
475
476 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
477 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
478 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
479 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
480 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
481 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < 8; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
506
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i >= 1 && blend->dual_src_blend) {
509 /* Vulkan does this for dual source blending. */
510 if (i == 1)
511 blend_cntl |= S_028780_ENABLE(1);
512
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
519 */
520 if (blend->dual_src_blend &&
521 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
522 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* cb_render_state will disable unused ones */
529 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
530 if (state->rt[j].colormask)
531 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
532
533 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
535 continue;
536 }
537
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
540 si_blend_check_commutativity(sctx->screen, blend,
541 eqA, srcA, dstA, 0x8 << (4 * i));
542
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
545 *
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 */
549 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_COLOR,
554 PIPE_BLENDFACTOR_SRC_COLOR);
555 si_blend_remove_dst(&eqA, &srcA, &dstA,
556 PIPE_BLENDFACTOR_DST_ALPHA,
557 PIPE_BLENDFACTOR_SRC_ALPHA);
558
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
561 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
562 srcA_opt = si_translate_blend_opt_factor(srcA, true);
563 dstA_opt = si_translate_blend_opt_factor(dstA, true);
564
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568 if (si_blend_factor_uses_dst(srcA))
569 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
570
571 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
572 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
574 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
576
577 /* Set the final value. */
578 sx_mrt_blend_opt[i] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt) |
583 S_028760_ALPHA_DST_OPT(dstA_opt) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
585
586 /* Set blend state. */
587 blend_cntl |= S_028780_ENABLE(1);
588 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
589 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
590 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
591
592 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
593 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
595 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
596 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
597 }
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599
600 blend->blend_enable_4bit |= 0xfu << (i * 4);
601
602 /* This is only important for formats without alpha. */
603 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
605 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
607 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
608 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
609 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
610 }
611
612 if (blend->cb_target_mask) {
613 color_control |= S_028808_MODE(mode);
614 } else {
615 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
616 }
617
618 if (sctx->screen->b.has_rbplus) {
619 /* Disable RB+ blend optimizations for dual source blending.
620 * Vulkan does this.
621 */
622 if (blend->dual_src_blend) {
623 for (int i = 0; i < 8; i++) {
624 sx_mrt_blend_opt[i] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
627 }
628 }
629
630 for (int i = 0; i < 8; i++)
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
632 sx_mrt_blend_opt[i]);
633
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend->dual_src_blend || state->logicop_enable ||
636 mode == V_028808_CB_RESOLVE)
637 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
638 }
639
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
641 return blend;
642 }
643
644 static void *si_create_blend_state(struct pipe_context *ctx,
645 const struct pipe_blend_state *state)
646 {
647 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
648 }
649
650 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 struct si_state_blend *old_blend = sctx->queued.named.blend;
654 struct si_state_blend *blend = (struct si_state_blend *)state;
655
656 if (!state)
657 return;
658
659 if (!old_blend ||
660 old_blend->cb_target_mask != blend->cb_target_mask ||
661 old_blend->dual_src_blend != blend->dual_src_blend)
662 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
663
664 si_pm4_bind_state(sctx, blend, state);
665
666 if (!old_blend ||
667 old_blend->cb_target_mask != blend->cb_target_mask ||
668 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
669 old_blend->alpha_to_one != blend->alpha_to_one ||
670 old_blend->dual_src_blend != blend->dual_src_blend ||
671 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
672 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
673 sctx->do_update_shaders = true;
674
675 if (sctx->screen->dpbb_allowed &&
676 (!old_blend ||
677 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
678 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
679 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
680 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
681
682 if (sctx->screen->has_out_of_order_rast &&
683 (!old_blend ||
684 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
685 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
686 old_blend->commutative_4bit != blend->commutative_4bit ||
687 old_blend->logicop_enable != blend->logicop_enable)))
688 si_mark_atom_dirty(sctx, &sctx->msaa_config);
689 }
690
691 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
692 {
693 struct si_context *sctx = (struct si_context *)ctx;
694 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
695 }
696
697 static void si_set_blend_color(struct pipe_context *ctx,
698 const struct pipe_blend_color *state)
699 {
700 struct si_context *sctx = (struct si_context *)ctx;
701 static const struct pipe_blend_color zeros;
702
703 sctx->blend_color.state = *state;
704 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
705 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
706 }
707
708 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
709 {
710 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
711
712 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
713 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
714 }
715
716 /*
717 * Clipping
718 */
719
720 static void si_set_clip_state(struct pipe_context *ctx,
721 const struct pipe_clip_state *state)
722 {
723 struct si_context *sctx = (struct si_context *)ctx;
724 struct pipe_constant_buffer cb;
725 static const struct pipe_clip_state zeros;
726
727 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
728 return;
729
730 sctx->clip_state.state = *state;
731 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
732 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
733
734 cb.buffer = NULL;
735 cb.user_buffer = state->ucp;
736 cb.buffer_offset = 0;
737 cb.buffer_size = 4*4*8;
738 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
739 pipe_resource_reference(&cb.buffer, NULL);
740 }
741
742 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
743 {
744 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
745
746 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
747 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
748 }
749
750 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
751 {
752 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
753 struct si_shader *vs = si_get_vs_state(sctx);
754 struct si_shader_selector *vs_sel = vs->selector;
755 struct tgsi_shader_info *info = &vs_sel->info;
756 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
757 unsigned window_space =
758 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
759 unsigned clipdist_mask = vs_sel->clipdist_mask;
760 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
761 unsigned culldist_mask = vs_sel->culldist_mask;
762 unsigned total_mask;
763
764 if (vs->key.opt.clip_disable) {
765 assert(!info->culldist_writemask);
766 clipdist_mask = 0;
767 culldist_mask = 0;
768 }
769 total_mask = clipdist_mask | culldist_mask;
770
771 /* Clip distances on points have no effect, so need to be implemented
772 * as cull distances. This applies for the clipvertex case as well.
773 *
774 * Setting this for primitives other than points should have no adverse
775 * effects.
776 */
777 clipdist_mask &= rs->clip_plane_enable;
778 culldist_mask |= clipdist_mask;
779
780 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
781 vs_sel->pa_cl_vs_out_cntl |
782 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
783 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
784 clipdist_mask | (culldist_mask << 8));
785 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
786 rs->pa_cl_clip_cntl |
787 ucp_mask |
788 S_028810_CLIP_DISABLE(window_space));
789 }
790
791 /*
792 * inferred state between framebuffer and rasterizer
793 */
794 static void si_update_poly_offset_state(struct si_context *sctx)
795 {
796 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
797
798 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
799 si_pm4_bind_state(sctx, poly_offset, NULL);
800 return;
801 }
802
803 /* Use the user format, not db_render_format, so that the polygon
804 * offset behaves as expected by applications.
805 */
806 switch (sctx->framebuffer.state.zsbuf->texture->format) {
807 case PIPE_FORMAT_Z16_UNORM:
808 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
809 break;
810 default: /* 24-bit */
811 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
812 break;
813 case PIPE_FORMAT_Z32_FLOAT:
814 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
815 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
816 break;
817 }
818 }
819
820 /*
821 * Rasterizer
822 */
823
824 static uint32_t si_translate_fill(uint32_t func)
825 {
826 switch(func) {
827 case PIPE_POLYGON_MODE_FILL:
828 return V_028814_X_DRAW_TRIANGLES;
829 case PIPE_POLYGON_MODE_LINE:
830 return V_028814_X_DRAW_LINES;
831 case PIPE_POLYGON_MODE_POINT:
832 return V_028814_X_DRAW_POINTS;
833 default:
834 assert(0);
835 return V_028814_X_DRAW_POINTS;
836 }
837 }
838
839 static void *si_create_rs_state(struct pipe_context *ctx,
840 const struct pipe_rasterizer_state *state)
841 {
842 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
843 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
844 struct si_pm4_state *pm4 = &rs->pm4;
845 unsigned tmp, i;
846 float psize_min, psize_max;
847
848 if (!rs) {
849 return NULL;
850 }
851
852 rs->scissor_enable = state->scissor;
853 rs->clip_halfz = state->clip_halfz;
854 rs->two_side = state->light_twoside;
855 rs->multisample_enable = state->multisample;
856 rs->force_persample_interp = state->force_persample_interp;
857 rs->clip_plane_enable = state->clip_plane_enable;
858 rs->line_stipple_enable = state->line_stipple_enable;
859 rs->poly_stipple_enable = state->poly_stipple_enable;
860 rs->line_smooth = state->line_smooth;
861 rs->line_width = state->line_width;
862 rs->poly_smooth = state->poly_smooth;
863 rs->uses_poly_offset = state->offset_point || state->offset_line ||
864 state->offset_tri;
865 rs->clamp_fragment_color = state->clamp_fragment_color;
866 rs->clamp_vertex_color = state->clamp_vertex_color;
867 rs->flatshade = state->flatshade;
868 rs->sprite_coord_enable = state->sprite_coord_enable;
869 rs->rasterizer_discard = state->rasterizer_discard;
870 rs->pa_sc_line_stipple = state->line_stipple_enable ?
871 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
872 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
873 rs->pa_cl_clip_cntl =
874 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
875 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
876 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
877 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
878 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
879
880 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
881 S_0286D4_FLAT_SHADE_ENA(1) |
882 S_0286D4_PNT_SPRITE_ENA(1) |
883 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
884 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
885 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
886 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
887 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
888
889 /* point size 12.4 fixed point */
890 tmp = (unsigned)(state->point_size * 8.0);
891 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
892
893 if (state->point_size_per_vertex) {
894 psize_min = util_get_min_point_size(state);
895 psize_max = 8192;
896 } else {
897 /* Force the point size to be as if the vertex output was disabled. */
898 psize_min = state->point_size;
899 psize_max = state->point_size;
900 }
901 rs->max_point_size = psize_max;
902
903 /* Divide by two, because 0.5 = 1 pixel. */
904 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
905 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
906 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
907
908 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
909 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
910 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
911 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
912 S_028A48_MSAA_ENABLE(state->multisample ||
913 state->poly_smooth ||
914 state->line_smooth) |
915 S_028A48_VPORT_SCISSOR_ENABLE(1) |
916 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
917
918 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
919 S_028BE4_PIX_CENTER(state->half_pixel_center) |
920 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
921
922 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
923 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
924 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
925 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
926 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
927 S_028814_FACE(!state->front_ccw) |
928 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
929 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
930 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
931 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
932 state->fill_back != PIPE_POLYGON_MODE_FILL) |
933 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
934 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
935
936 if (!rs->uses_poly_offset)
937 return rs;
938
939 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
940 if (!rs->pm4_poly_offset) {
941 FREE(rs);
942 return NULL;
943 }
944
945 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
946 for (i = 0; i < 3; i++) {
947 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
948 float offset_units = state->offset_units;
949 float offset_scale = state->offset_scale * 16.0f;
950 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
951
952 if (!state->offset_units_unscaled) {
953 switch (i) {
954 case 0: /* 16-bit zbuffer */
955 offset_units *= 4.0f;
956 pa_su_poly_offset_db_fmt_cntl =
957 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
958 break;
959 case 1: /* 24-bit zbuffer */
960 offset_units *= 2.0f;
961 pa_su_poly_offset_db_fmt_cntl =
962 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
963 break;
964 case 2: /* 32-bit zbuffer */
965 offset_units *= 1.0f;
966 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
967 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
968 break;
969 }
970 }
971
972 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
973 fui(offset_scale));
974 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
975 fui(offset_units));
976 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
977 fui(offset_scale));
978 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
979 fui(offset_units));
980 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
981 pa_su_poly_offset_db_fmt_cntl);
982 }
983
984 return rs;
985 }
986
987 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
988 {
989 struct si_context *sctx = (struct si_context *)ctx;
990 struct si_state_rasterizer *old_rs =
991 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
992 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
993
994 if (!state)
995 return;
996
997 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
998 si_mark_atom_dirty(sctx, &sctx->db_render_state);
999
1000 /* Update the small primitive filter workaround if necessary. */
1001 if (sctx->screen->has_msaa_sample_loc_bug &&
1002 sctx->framebuffer.nr_samples > 1)
1003 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1004 }
1005
1006 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1007 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1008
1009 si_pm4_bind_state(sctx, rasterizer, rs);
1010 si_update_poly_offset_state(sctx);
1011
1012 if (!old_rs ||
1013 (old_rs->scissor_enable != rs->scissor_enable ||
1014 old_rs->line_width != rs->line_width ||
1015 old_rs->max_point_size != rs->max_point_size)) {
1016 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1017 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1018 }
1019
1020 if (!old_rs ||
1021 old_rs->clip_halfz != rs->clip_halfz) {
1022 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1023 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1024 }
1025
1026 if (!old_rs ||
1027 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1028 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1029 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1030
1031 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1032 rs->line_stipple_enable;
1033
1034 if (!old_rs ||
1035 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1036 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1037 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1038 old_rs->flatshade != rs->flatshade ||
1039 old_rs->two_side != rs->two_side ||
1040 old_rs->multisample_enable != rs->multisample_enable ||
1041 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1042 old_rs->poly_smooth != rs->poly_smooth ||
1043 old_rs->line_smooth != rs->line_smooth ||
1044 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1045 old_rs->force_persample_interp != rs->force_persample_interp)
1046 sctx->do_update_shaders = true;
1047 }
1048
1049 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1050 {
1051 struct si_context *sctx = (struct si_context *)ctx;
1052 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1053
1054 if (sctx->queued.named.rasterizer == state)
1055 si_pm4_bind_state(sctx, poly_offset, NULL);
1056
1057 FREE(rs->pm4_poly_offset);
1058 si_pm4_delete_state(sctx, rasterizer, rs);
1059 }
1060
1061 /*
1062 * infeered state between dsa and stencil ref
1063 */
1064 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1065 {
1066 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1067 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1068 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1069
1070 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1071 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1072 S_028430_STENCILMASK(dsa->valuemask[0]) |
1073 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1074 S_028430_STENCILOPVAL(1));
1075 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1076 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1077 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1078 S_028434_STENCILOPVAL_BF(1));
1079 }
1080
1081 static void si_set_stencil_ref(struct pipe_context *ctx,
1082 const struct pipe_stencil_ref *state)
1083 {
1084 struct si_context *sctx = (struct si_context *)ctx;
1085
1086 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1087 return;
1088
1089 sctx->stencil_ref.state = *state;
1090 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1091 }
1092
1093
1094 /*
1095 * DSA
1096 */
1097
1098 static uint32_t si_translate_stencil_op(int s_op)
1099 {
1100 switch (s_op) {
1101 case PIPE_STENCIL_OP_KEEP:
1102 return V_02842C_STENCIL_KEEP;
1103 case PIPE_STENCIL_OP_ZERO:
1104 return V_02842C_STENCIL_ZERO;
1105 case PIPE_STENCIL_OP_REPLACE:
1106 return V_02842C_STENCIL_REPLACE_TEST;
1107 case PIPE_STENCIL_OP_INCR:
1108 return V_02842C_STENCIL_ADD_CLAMP;
1109 case PIPE_STENCIL_OP_DECR:
1110 return V_02842C_STENCIL_SUB_CLAMP;
1111 case PIPE_STENCIL_OP_INCR_WRAP:
1112 return V_02842C_STENCIL_ADD_WRAP;
1113 case PIPE_STENCIL_OP_DECR_WRAP:
1114 return V_02842C_STENCIL_SUB_WRAP;
1115 case PIPE_STENCIL_OP_INVERT:
1116 return V_02842C_STENCIL_INVERT;
1117 default:
1118 R600_ERR("Unknown stencil op %d", s_op);
1119 assert(0);
1120 break;
1121 }
1122 return 0;
1123 }
1124
1125 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1126 {
1127 return s->enabled && s->writemask &&
1128 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1129 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1130 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1131 }
1132
1133 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1134 {
1135 /* REPLACE is normally order invariant, except when the stencil
1136 * reference value is written by the fragment shader. Tracking this
1137 * interaction does not seem worth the effort, so be conservative. */
1138 return op != PIPE_STENCIL_OP_INCR &&
1139 op != PIPE_STENCIL_OP_DECR &&
1140 op != PIPE_STENCIL_OP_REPLACE;
1141 }
1142
1143 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1144 * invariant in the sense that the set of passing fragments as well as the
1145 * final stencil buffer result does not depend on the order of fragments. */
1146 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1147 {
1148 return !state->enabled || !state->writemask ||
1149 /* The following assumes that Z writes are disabled. */
1150 (state->func == PIPE_FUNC_ALWAYS &&
1151 si_order_invariant_stencil_op(state->zpass_op) &&
1152 si_order_invariant_stencil_op(state->zfail_op)) ||
1153 (state->func == PIPE_FUNC_NEVER &&
1154 si_order_invariant_stencil_op(state->fail_op));
1155 }
1156
1157 static void *si_create_dsa_state(struct pipe_context *ctx,
1158 const struct pipe_depth_stencil_alpha_state *state)
1159 {
1160 struct si_context *sctx = (struct si_context *)ctx;
1161 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1162 struct si_pm4_state *pm4 = &dsa->pm4;
1163 unsigned db_depth_control;
1164 uint32_t db_stencil_control = 0;
1165
1166 if (!dsa) {
1167 return NULL;
1168 }
1169
1170 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1171 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1172 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1173 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1174
1175 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1176 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1177 S_028800_ZFUNC(state->depth.func) |
1178 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1179
1180 /* stencil */
1181 if (state->stencil[0].enabled) {
1182 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1183 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1184 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1185 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1186 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1187
1188 if (state->stencil[1].enabled) {
1189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1190 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1191 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1192 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1193 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1194 }
1195 }
1196
1197 /* alpha */
1198 if (state->alpha.enabled) {
1199 dsa->alpha_func = state->alpha.func;
1200
1201 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1202 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1203 } else {
1204 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1205 }
1206
1207 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1208 if (state->stencil[0].enabled)
1209 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1210 if (state->depth.bounds_test) {
1211 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1212 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1213 }
1214
1215 dsa->depth_enabled = state->depth.enabled;
1216 dsa->depth_write_enabled = state->depth.enabled &&
1217 state->depth.writemask;
1218 dsa->stencil_enabled = state->stencil[0].enabled;
1219 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1220 (si_dsa_writes_stencil(&state->stencil[0]) ||
1221 si_dsa_writes_stencil(&state->stencil[1]));
1222 dsa->db_can_write = dsa->depth_write_enabled ||
1223 dsa->stencil_write_enabled;
1224
1225 bool zfunc_is_ordered =
1226 state->depth.func == PIPE_FUNC_NEVER ||
1227 state->depth.func == PIPE_FUNC_LESS ||
1228 state->depth.func == PIPE_FUNC_LEQUAL ||
1229 state->depth.func == PIPE_FUNC_GREATER ||
1230 state->depth.func == PIPE_FUNC_GEQUAL;
1231
1232 bool nozwrite_and_order_invariant_stencil =
1233 !dsa->db_can_write ||
1234 (!dsa->depth_write_enabled &&
1235 si_order_invariant_stencil_state(&state->stencil[0]) &&
1236 si_order_invariant_stencil_state(&state->stencil[1]));
1237
1238 dsa->order_invariance[1].zs =
1239 nozwrite_and_order_invariant_stencil ||
1240 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1241 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1242
1243 dsa->order_invariance[1].pass_set =
1244 nozwrite_and_order_invariant_stencil ||
1245 (!dsa->stencil_write_enabled &&
1246 (state->depth.func == PIPE_FUNC_ALWAYS ||
1247 state->depth.func == PIPE_FUNC_NEVER));
1248 dsa->order_invariance[0].pass_set =
1249 !dsa->depth_write_enabled ||
1250 (state->depth.func == PIPE_FUNC_ALWAYS ||
1251 state->depth.func == PIPE_FUNC_NEVER);
1252
1253 dsa->order_invariance[1].pass_last =
1254 sctx->screen->assume_no_z_fights &&
1255 !dsa->stencil_write_enabled &&
1256 dsa->depth_write_enabled && zfunc_is_ordered;
1257 dsa->order_invariance[0].pass_last =
1258 sctx->screen->assume_no_z_fights &&
1259 dsa->depth_write_enabled && zfunc_is_ordered;
1260
1261 return dsa;
1262 }
1263
1264 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1268 struct si_state_dsa *dsa = state;
1269
1270 if (!state)
1271 return;
1272
1273 si_pm4_bind_state(sctx, dsa, dsa);
1274
1275 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1276 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1277 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1278 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1279 }
1280
1281 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1282 sctx->do_update_shaders = true;
1283
1284 if (sctx->screen->dpbb_allowed &&
1285 (!old_dsa ||
1286 (old_dsa->depth_enabled != dsa->depth_enabled ||
1287 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1288 old_dsa->db_can_write != dsa->db_can_write)))
1289 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1290
1291 if (sctx->screen->has_out_of_order_rast &&
1292 (!old_dsa ||
1293 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1294 sizeof(old_dsa->order_invariance))))
1295 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1296 }
1297
1298 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1299 {
1300 struct si_context *sctx = (struct si_context *)ctx;
1301 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1302 }
1303
1304 static void *si_create_db_flush_dsa(struct si_context *sctx)
1305 {
1306 struct pipe_depth_stencil_alpha_state dsa = {};
1307
1308 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1309 }
1310
1311 /* DB RENDER STATE */
1312
1313 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1314 {
1315 struct si_context *sctx = (struct si_context*)ctx;
1316
1317 /* Pipeline stat & streamout queries. */
1318 if (enable) {
1319 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1320 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1321 } else {
1322 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1323 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1324 }
1325
1326 /* Occlusion queries. */
1327 if (sctx->occlusion_queries_disabled != !enable) {
1328 sctx->occlusion_queries_disabled = !enable;
1329 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1330 }
1331 }
1332
1333 static void si_set_occlusion_query_state(struct pipe_context *ctx,
1334 bool old_enable,
1335 bool old_perfect_enable)
1336 {
1337 struct si_context *sctx = (struct si_context*)ctx;
1338
1339 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1340
1341 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
1342
1343 if (perfect_enable != old_perfect_enable)
1344 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1345 }
1346
1347 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1348 {
1349 struct si_context *sctx = (struct si_context*)ctx;
1350
1351 st->saved_compute = sctx->cs_shader_state.program;
1352
1353 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1354 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1355 }
1356
1357 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1358 {
1359 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1360 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1361 unsigned db_shader_control;
1362
1363 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1364
1365 /* DB_RENDER_CONTROL */
1366 if (sctx->dbcb_depth_copy_enabled ||
1367 sctx->dbcb_stencil_copy_enabled) {
1368 radeon_emit(cs,
1369 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1370 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1371 S_028000_COPY_CENTROID(1) |
1372 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1373 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1374 radeon_emit(cs,
1375 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1376 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1377 } else {
1378 radeon_emit(cs,
1379 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1380 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1381 }
1382
1383 /* DB_COUNT_CONTROL (occlusion queries) */
1384 if (sctx->b.num_occlusion_queries > 0 &&
1385 !sctx->occlusion_queries_disabled) {
1386 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1387
1388 if (sctx->b.chip_class >= CIK) {
1389 radeon_emit(cs,
1390 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1391 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1392 S_028004_ZPASS_ENABLE(1) |
1393 S_028004_SLICE_EVEN_ENABLE(1) |
1394 S_028004_SLICE_ODD_ENABLE(1));
1395 } else {
1396 radeon_emit(cs,
1397 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1398 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1399 }
1400 } else {
1401 /* Disable occlusion queries. */
1402 if (sctx->b.chip_class >= CIK) {
1403 radeon_emit(cs, 0);
1404 } else {
1405 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1406 }
1407 }
1408
1409 /* DB_RENDER_OVERRIDE2 */
1410 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1411 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1412 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1413 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1414
1415 db_shader_control = sctx->ps_db_shader_control;
1416
1417 /* Bug workaround for smoothing (overrasterization) on SI. */
1418 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1419 db_shader_control &= C_02880C_Z_ORDER;
1420 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1421 }
1422
1423 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1424 if (!rs || !rs->multisample_enable)
1425 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1426
1427 if (sctx->screen->b.has_rbplus &&
1428 !sctx->screen->b.rbplus_allowed)
1429 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1430
1431 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1432 db_shader_control);
1433 }
1434
1435 /*
1436 * format translation
1437 */
1438 static uint32_t si_translate_colorformat(enum pipe_format format)
1439 {
1440 const struct util_format_description *desc = util_format_description(format);
1441 if (!desc)
1442 return V_028C70_COLOR_INVALID;
1443
1444 #define HAS_SIZE(x,y,z,w) \
1445 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1446 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1447
1448 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1449 return V_028C70_COLOR_10_11_11;
1450
1451 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1452 return V_028C70_COLOR_INVALID;
1453
1454 /* hw cannot support mixed formats (except depth/stencil, since
1455 * stencil is not written to). */
1456 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1457 return V_028C70_COLOR_INVALID;
1458
1459 switch (desc->nr_channels) {
1460 case 1:
1461 switch (desc->channel[0].size) {
1462 case 8:
1463 return V_028C70_COLOR_8;
1464 case 16:
1465 return V_028C70_COLOR_16;
1466 case 32:
1467 return V_028C70_COLOR_32;
1468 }
1469 break;
1470 case 2:
1471 if (desc->channel[0].size == desc->channel[1].size) {
1472 switch (desc->channel[0].size) {
1473 case 8:
1474 return V_028C70_COLOR_8_8;
1475 case 16:
1476 return V_028C70_COLOR_16_16;
1477 case 32:
1478 return V_028C70_COLOR_32_32;
1479 }
1480 } else if (HAS_SIZE(8,24,0,0)) {
1481 return V_028C70_COLOR_24_8;
1482 } else if (HAS_SIZE(24,8,0,0)) {
1483 return V_028C70_COLOR_8_24;
1484 }
1485 break;
1486 case 3:
1487 if (HAS_SIZE(5,6,5,0)) {
1488 return V_028C70_COLOR_5_6_5;
1489 } else if (HAS_SIZE(32,8,24,0)) {
1490 return V_028C70_COLOR_X24_8_32_FLOAT;
1491 }
1492 break;
1493 case 4:
1494 if (desc->channel[0].size == desc->channel[1].size &&
1495 desc->channel[0].size == desc->channel[2].size &&
1496 desc->channel[0].size == desc->channel[3].size) {
1497 switch (desc->channel[0].size) {
1498 case 4:
1499 return V_028C70_COLOR_4_4_4_4;
1500 case 8:
1501 return V_028C70_COLOR_8_8_8_8;
1502 case 16:
1503 return V_028C70_COLOR_16_16_16_16;
1504 case 32:
1505 return V_028C70_COLOR_32_32_32_32;
1506 }
1507 } else if (HAS_SIZE(5,5,5,1)) {
1508 return V_028C70_COLOR_1_5_5_5;
1509 } else if (HAS_SIZE(10,10,10,2)) {
1510 return V_028C70_COLOR_2_10_10_10;
1511 }
1512 break;
1513 }
1514 return V_028C70_COLOR_INVALID;
1515 }
1516
1517 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1518 {
1519 if (SI_BIG_ENDIAN) {
1520 switch(colorformat) {
1521 /* 8-bit buffers. */
1522 case V_028C70_COLOR_8:
1523 return V_028C70_ENDIAN_NONE;
1524
1525 /* 16-bit buffers. */
1526 case V_028C70_COLOR_5_6_5:
1527 case V_028C70_COLOR_1_5_5_5:
1528 case V_028C70_COLOR_4_4_4_4:
1529 case V_028C70_COLOR_16:
1530 case V_028C70_COLOR_8_8:
1531 return V_028C70_ENDIAN_8IN16;
1532
1533 /* 32-bit buffers. */
1534 case V_028C70_COLOR_8_8_8_8:
1535 case V_028C70_COLOR_2_10_10_10:
1536 case V_028C70_COLOR_8_24:
1537 case V_028C70_COLOR_24_8:
1538 case V_028C70_COLOR_16_16:
1539 return V_028C70_ENDIAN_8IN32;
1540
1541 /* 64-bit buffers. */
1542 case V_028C70_COLOR_16_16_16_16:
1543 return V_028C70_ENDIAN_8IN16;
1544
1545 case V_028C70_COLOR_32_32:
1546 return V_028C70_ENDIAN_8IN32;
1547
1548 /* 128-bit buffers. */
1549 case V_028C70_COLOR_32_32_32_32:
1550 return V_028C70_ENDIAN_8IN32;
1551 default:
1552 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1553 }
1554 } else {
1555 return V_028C70_ENDIAN_NONE;
1556 }
1557 }
1558
1559 static uint32_t si_translate_dbformat(enum pipe_format format)
1560 {
1561 switch (format) {
1562 case PIPE_FORMAT_Z16_UNORM:
1563 return V_028040_Z_16;
1564 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1565 case PIPE_FORMAT_X8Z24_UNORM:
1566 case PIPE_FORMAT_Z24X8_UNORM:
1567 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1568 return V_028040_Z_24; /* deprecated on SI */
1569 case PIPE_FORMAT_Z32_FLOAT:
1570 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1571 return V_028040_Z_32_FLOAT;
1572 default:
1573 return V_028040_Z_INVALID;
1574 }
1575 }
1576
1577 /*
1578 * Texture translation
1579 */
1580
1581 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1582 enum pipe_format format,
1583 const struct util_format_description *desc,
1584 int first_non_void)
1585 {
1586 struct si_screen *sscreen = (struct si_screen*)screen;
1587 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1588 sscreen->b.info.drm_minor >= 31) ||
1589 sscreen->b.info.drm_major == 3;
1590 bool uniform = true;
1591 int i;
1592
1593 /* Colorspace (return non-RGB formats directly). */
1594 switch (desc->colorspace) {
1595 /* Depth stencil formats */
1596 case UTIL_FORMAT_COLORSPACE_ZS:
1597 switch (format) {
1598 case PIPE_FORMAT_Z16_UNORM:
1599 return V_008F14_IMG_DATA_FORMAT_16;
1600 case PIPE_FORMAT_X24S8_UINT:
1601 case PIPE_FORMAT_S8X24_UINT:
1602 /*
1603 * Implemented as an 8_8_8_8 data format to fix texture
1604 * gathers in stencil sampling. This affects at least
1605 * GL45-CTS.texture_cube_map_array.sampling on VI.
1606 */
1607 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1608 case PIPE_FORMAT_Z24X8_UNORM:
1609 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1610 return V_008F14_IMG_DATA_FORMAT_8_24;
1611 case PIPE_FORMAT_X8Z24_UNORM:
1612 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1613 return V_008F14_IMG_DATA_FORMAT_24_8;
1614 case PIPE_FORMAT_S8_UINT:
1615 return V_008F14_IMG_DATA_FORMAT_8;
1616 case PIPE_FORMAT_Z32_FLOAT:
1617 return V_008F14_IMG_DATA_FORMAT_32;
1618 case PIPE_FORMAT_X32_S8X24_UINT:
1619 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1620 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1621 default:
1622 goto out_unknown;
1623 }
1624
1625 case UTIL_FORMAT_COLORSPACE_YUV:
1626 goto out_unknown; /* TODO */
1627
1628 case UTIL_FORMAT_COLORSPACE_SRGB:
1629 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1630 goto out_unknown;
1631 break;
1632
1633 default:
1634 break;
1635 }
1636
1637 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1638 if (!enable_compressed_formats)
1639 goto out_unknown;
1640
1641 switch (format) {
1642 case PIPE_FORMAT_RGTC1_SNORM:
1643 case PIPE_FORMAT_LATC1_SNORM:
1644 case PIPE_FORMAT_RGTC1_UNORM:
1645 case PIPE_FORMAT_LATC1_UNORM:
1646 return V_008F14_IMG_DATA_FORMAT_BC4;
1647 case PIPE_FORMAT_RGTC2_SNORM:
1648 case PIPE_FORMAT_LATC2_SNORM:
1649 case PIPE_FORMAT_RGTC2_UNORM:
1650 case PIPE_FORMAT_LATC2_UNORM:
1651 return V_008F14_IMG_DATA_FORMAT_BC5;
1652 default:
1653 goto out_unknown;
1654 }
1655 }
1656
1657 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1658 (sscreen->b.family == CHIP_STONEY ||
1659 sscreen->b.chip_class >= GFX9)) {
1660 switch (format) {
1661 case PIPE_FORMAT_ETC1_RGB8:
1662 case PIPE_FORMAT_ETC2_RGB8:
1663 case PIPE_FORMAT_ETC2_SRGB8:
1664 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1665 case PIPE_FORMAT_ETC2_RGB8A1:
1666 case PIPE_FORMAT_ETC2_SRGB8A1:
1667 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1668 case PIPE_FORMAT_ETC2_RGBA8:
1669 case PIPE_FORMAT_ETC2_SRGBA8:
1670 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1671 case PIPE_FORMAT_ETC2_R11_UNORM:
1672 case PIPE_FORMAT_ETC2_R11_SNORM:
1673 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1674 case PIPE_FORMAT_ETC2_RG11_UNORM:
1675 case PIPE_FORMAT_ETC2_RG11_SNORM:
1676 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1677 default:
1678 goto out_unknown;
1679 }
1680 }
1681
1682 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1683 if (!enable_compressed_formats)
1684 goto out_unknown;
1685
1686 switch (format) {
1687 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1688 case PIPE_FORMAT_BPTC_SRGBA:
1689 return V_008F14_IMG_DATA_FORMAT_BC7;
1690 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1691 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1692 return V_008F14_IMG_DATA_FORMAT_BC6;
1693 default:
1694 goto out_unknown;
1695 }
1696 }
1697
1698 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1699 switch (format) {
1700 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1701 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1702 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1703 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1704 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1705 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1706 default:
1707 goto out_unknown;
1708 }
1709 }
1710
1711 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1712 if (!enable_compressed_formats)
1713 goto out_unknown;
1714
1715 switch (format) {
1716 case PIPE_FORMAT_DXT1_RGB:
1717 case PIPE_FORMAT_DXT1_RGBA:
1718 case PIPE_FORMAT_DXT1_SRGB:
1719 case PIPE_FORMAT_DXT1_SRGBA:
1720 return V_008F14_IMG_DATA_FORMAT_BC1;
1721 case PIPE_FORMAT_DXT3_RGBA:
1722 case PIPE_FORMAT_DXT3_SRGBA:
1723 return V_008F14_IMG_DATA_FORMAT_BC2;
1724 case PIPE_FORMAT_DXT5_RGBA:
1725 case PIPE_FORMAT_DXT5_SRGBA:
1726 return V_008F14_IMG_DATA_FORMAT_BC3;
1727 default:
1728 goto out_unknown;
1729 }
1730 }
1731
1732 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1733 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1734 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1735 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1736 }
1737
1738 /* R8G8Bx_SNORM - TODO CxV8U8 */
1739
1740 /* hw cannot support mixed formats (except depth/stencil, since only
1741 * depth is read).*/
1742 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1743 goto out_unknown;
1744
1745 /* See whether the components are of the same size. */
1746 for (i = 1; i < desc->nr_channels; i++) {
1747 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1748 }
1749
1750 /* Non-uniform formats. */
1751 if (!uniform) {
1752 switch(desc->nr_channels) {
1753 case 3:
1754 if (desc->channel[0].size == 5 &&
1755 desc->channel[1].size == 6 &&
1756 desc->channel[2].size == 5) {
1757 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1758 }
1759 goto out_unknown;
1760 case 4:
1761 if (desc->channel[0].size == 5 &&
1762 desc->channel[1].size == 5 &&
1763 desc->channel[2].size == 5 &&
1764 desc->channel[3].size == 1) {
1765 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1766 }
1767 if (desc->channel[0].size == 10 &&
1768 desc->channel[1].size == 10 &&
1769 desc->channel[2].size == 10 &&
1770 desc->channel[3].size == 2) {
1771 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1772 }
1773 goto out_unknown;
1774 }
1775 goto out_unknown;
1776 }
1777
1778 if (first_non_void < 0 || first_non_void > 3)
1779 goto out_unknown;
1780
1781 /* uniform formats */
1782 switch (desc->channel[first_non_void].size) {
1783 case 4:
1784 switch (desc->nr_channels) {
1785 #if 0 /* Not supported for render targets */
1786 case 2:
1787 return V_008F14_IMG_DATA_FORMAT_4_4;
1788 #endif
1789 case 4:
1790 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1791 }
1792 break;
1793 case 8:
1794 switch (desc->nr_channels) {
1795 case 1:
1796 return V_008F14_IMG_DATA_FORMAT_8;
1797 case 2:
1798 return V_008F14_IMG_DATA_FORMAT_8_8;
1799 case 4:
1800 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1801 }
1802 break;
1803 case 16:
1804 switch (desc->nr_channels) {
1805 case 1:
1806 return V_008F14_IMG_DATA_FORMAT_16;
1807 case 2:
1808 return V_008F14_IMG_DATA_FORMAT_16_16;
1809 case 4:
1810 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1811 }
1812 break;
1813 case 32:
1814 switch (desc->nr_channels) {
1815 case 1:
1816 return V_008F14_IMG_DATA_FORMAT_32;
1817 case 2:
1818 return V_008F14_IMG_DATA_FORMAT_32_32;
1819 #if 0 /* Not supported for render targets */
1820 case 3:
1821 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1822 #endif
1823 case 4:
1824 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1825 }
1826 }
1827
1828 out_unknown:
1829 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1830 return ~0;
1831 }
1832
1833 static unsigned si_tex_wrap(unsigned wrap)
1834 {
1835 switch (wrap) {
1836 default:
1837 case PIPE_TEX_WRAP_REPEAT:
1838 return V_008F30_SQ_TEX_WRAP;
1839 case PIPE_TEX_WRAP_CLAMP:
1840 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1841 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1842 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1843 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1844 return V_008F30_SQ_TEX_CLAMP_BORDER;
1845 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1846 return V_008F30_SQ_TEX_MIRROR;
1847 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1848 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1849 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1850 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1851 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1852 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1853 }
1854 }
1855
1856 static unsigned si_tex_mipfilter(unsigned filter)
1857 {
1858 switch (filter) {
1859 case PIPE_TEX_MIPFILTER_NEAREST:
1860 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1861 case PIPE_TEX_MIPFILTER_LINEAR:
1862 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1863 default:
1864 case PIPE_TEX_MIPFILTER_NONE:
1865 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1866 }
1867 }
1868
1869 static unsigned si_tex_compare(unsigned compare)
1870 {
1871 switch (compare) {
1872 default:
1873 case PIPE_FUNC_NEVER:
1874 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1875 case PIPE_FUNC_LESS:
1876 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1877 case PIPE_FUNC_EQUAL:
1878 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1879 case PIPE_FUNC_LEQUAL:
1880 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1881 case PIPE_FUNC_GREATER:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1883 case PIPE_FUNC_NOTEQUAL:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1885 case PIPE_FUNC_GEQUAL:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1887 case PIPE_FUNC_ALWAYS:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1889 }
1890 }
1891
1892 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1893 unsigned view_target, unsigned nr_samples)
1894 {
1895 unsigned res_target = rtex->resource.b.b.target;
1896
1897 if (view_target == PIPE_TEXTURE_CUBE ||
1898 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1899 res_target = view_target;
1900 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1901 else if (res_target == PIPE_TEXTURE_CUBE ||
1902 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1903 res_target = PIPE_TEXTURE_2D_ARRAY;
1904
1905 /* GFX9 allocates 1D textures as 2D. */
1906 if ((res_target == PIPE_TEXTURE_1D ||
1907 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1908 sscreen->b.chip_class >= GFX9 &&
1909 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1910 if (res_target == PIPE_TEXTURE_1D)
1911 res_target = PIPE_TEXTURE_2D;
1912 else
1913 res_target = PIPE_TEXTURE_2D_ARRAY;
1914 }
1915
1916 switch (res_target) {
1917 default:
1918 case PIPE_TEXTURE_1D:
1919 return V_008F1C_SQ_RSRC_IMG_1D;
1920 case PIPE_TEXTURE_1D_ARRAY:
1921 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1922 case PIPE_TEXTURE_2D:
1923 case PIPE_TEXTURE_RECT:
1924 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1925 V_008F1C_SQ_RSRC_IMG_2D;
1926 case PIPE_TEXTURE_2D_ARRAY:
1927 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1928 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1929 case PIPE_TEXTURE_3D:
1930 return V_008F1C_SQ_RSRC_IMG_3D;
1931 case PIPE_TEXTURE_CUBE:
1932 case PIPE_TEXTURE_CUBE_ARRAY:
1933 return V_008F1C_SQ_RSRC_IMG_CUBE;
1934 }
1935 }
1936
1937 /*
1938 * Format support testing
1939 */
1940
1941 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1942 {
1943 const struct util_format_description *desc = util_format_description(format);
1944 if (!desc)
1945 return false;
1946
1947 return si_translate_texformat(screen, format, desc,
1948 util_format_get_first_non_void_channel(format)) != ~0U;
1949 }
1950
1951 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1952 const struct util_format_description *desc,
1953 int first_non_void)
1954 {
1955 int i;
1956
1957 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1958 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1959
1960 assert(first_non_void >= 0);
1961
1962 if (desc->nr_channels == 4 &&
1963 desc->channel[0].size == 10 &&
1964 desc->channel[1].size == 10 &&
1965 desc->channel[2].size == 10 &&
1966 desc->channel[3].size == 2)
1967 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1968
1969 /* See whether the components are of the same size. */
1970 for (i = 0; i < desc->nr_channels; i++) {
1971 if (desc->channel[first_non_void].size != desc->channel[i].size)
1972 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1973 }
1974
1975 switch (desc->channel[first_non_void].size) {
1976 case 8:
1977 switch (desc->nr_channels) {
1978 case 1:
1979 case 3: /* 3 loads */
1980 return V_008F0C_BUF_DATA_FORMAT_8;
1981 case 2:
1982 return V_008F0C_BUF_DATA_FORMAT_8_8;
1983 case 4:
1984 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1985 }
1986 break;
1987 case 16:
1988 switch (desc->nr_channels) {
1989 case 1:
1990 case 3: /* 3 loads */
1991 return V_008F0C_BUF_DATA_FORMAT_16;
1992 case 2:
1993 return V_008F0C_BUF_DATA_FORMAT_16_16;
1994 case 4:
1995 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1996 }
1997 break;
1998 case 32:
1999 switch (desc->nr_channels) {
2000 case 1:
2001 return V_008F0C_BUF_DATA_FORMAT_32;
2002 case 2:
2003 return V_008F0C_BUF_DATA_FORMAT_32_32;
2004 case 3:
2005 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2006 case 4:
2007 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2008 }
2009 break;
2010 case 64:
2011 /* Legacy double formats. */
2012 switch (desc->nr_channels) {
2013 case 1: /* 1 load */
2014 return V_008F0C_BUF_DATA_FORMAT_32_32;
2015 case 2: /* 1 load */
2016 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2017 case 3: /* 3 loads */
2018 return V_008F0C_BUF_DATA_FORMAT_32_32;
2019 case 4: /* 2 loads */
2020 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2021 }
2022 break;
2023 }
2024
2025 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2026 }
2027
2028 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2029 const struct util_format_description *desc,
2030 int first_non_void)
2031 {
2032 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2033 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2034
2035 assert(first_non_void >= 0);
2036
2037 switch (desc->channel[first_non_void].type) {
2038 case UTIL_FORMAT_TYPE_SIGNED:
2039 case UTIL_FORMAT_TYPE_FIXED:
2040 if (desc->channel[first_non_void].size >= 32 ||
2041 desc->channel[first_non_void].pure_integer)
2042 return V_008F0C_BUF_NUM_FORMAT_SINT;
2043 else if (desc->channel[first_non_void].normalized)
2044 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2045 else
2046 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2047 break;
2048 case UTIL_FORMAT_TYPE_UNSIGNED:
2049 if (desc->channel[first_non_void].size >= 32 ||
2050 desc->channel[first_non_void].pure_integer)
2051 return V_008F0C_BUF_NUM_FORMAT_UINT;
2052 else if (desc->channel[first_non_void].normalized)
2053 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2054 else
2055 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2056 break;
2057 case UTIL_FORMAT_TYPE_FLOAT:
2058 default:
2059 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2060 }
2061 }
2062
2063 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2064 enum pipe_format format,
2065 unsigned usage)
2066 {
2067 const struct util_format_description *desc;
2068 int first_non_void;
2069 unsigned data_format;
2070
2071 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2072 PIPE_BIND_SAMPLER_VIEW |
2073 PIPE_BIND_VERTEX_BUFFER)) == 0);
2074
2075 desc = util_format_description(format);
2076 if (!desc)
2077 return 0;
2078
2079 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2080 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2081 * for read-only access (with caveats surrounding bounds checks), but
2082 * obviously fails for write access which we have to implement for
2083 * shader images. Luckily, OpenGL doesn't expect this to be supported
2084 * anyway, and so the only impact is on PBO uploads / downloads, which
2085 * shouldn't be expected to be fast for GL_RGB anyway.
2086 */
2087 if (desc->block.bits == 3 * 8 ||
2088 desc->block.bits == 3 * 16) {
2089 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2090 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2091 if (!usage)
2092 return 0;
2093 }
2094 }
2095
2096 first_non_void = util_format_get_first_non_void_channel(format);
2097 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2098 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2099 return 0;
2100
2101 return usage;
2102 }
2103
2104 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2105 {
2106 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2107 si_translate_colorswap(format, false) != ~0U;
2108 }
2109
2110 static bool si_is_zs_format_supported(enum pipe_format format)
2111 {
2112 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2113 }
2114
2115 static boolean si_is_format_supported(struct pipe_screen *screen,
2116 enum pipe_format format,
2117 enum pipe_texture_target target,
2118 unsigned sample_count,
2119 unsigned usage)
2120 {
2121 unsigned retval = 0;
2122
2123 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2124 R600_ERR("r600: unsupported texture type %d\n", target);
2125 return false;
2126 }
2127
2128 if (!util_format_is_supported(format, usage))
2129 return false;
2130
2131 if (sample_count > 1) {
2132 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2133 return false;
2134
2135 if (usage & PIPE_BIND_SHADER_IMAGE)
2136 return false;
2137
2138 switch (sample_count) {
2139 case 2:
2140 case 4:
2141 case 8:
2142 break;
2143 case 16:
2144 if (format == PIPE_FORMAT_NONE)
2145 return true;
2146 else
2147 return false;
2148 default:
2149 return false;
2150 }
2151 }
2152
2153 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2154 PIPE_BIND_SHADER_IMAGE)) {
2155 if (target == PIPE_BUFFER) {
2156 retval |= si_is_vertex_format_supported(
2157 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2158 PIPE_BIND_SHADER_IMAGE));
2159 } else {
2160 if (si_is_sampler_format_supported(screen, format))
2161 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2162 PIPE_BIND_SHADER_IMAGE);
2163 }
2164 }
2165
2166 if ((usage & (PIPE_BIND_RENDER_TARGET |
2167 PIPE_BIND_DISPLAY_TARGET |
2168 PIPE_BIND_SCANOUT |
2169 PIPE_BIND_SHARED |
2170 PIPE_BIND_BLENDABLE)) &&
2171 si_is_colorbuffer_format_supported(format)) {
2172 retval |= usage &
2173 (PIPE_BIND_RENDER_TARGET |
2174 PIPE_BIND_DISPLAY_TARGET |
2175 PIPE_BIND_SCANOUT |
2176 PIPE_BIND_SHARED);
2177 if (!util_format_is_pure_integer(format) &&
2178 !util_format_is_depth_or_stencil(format))
2179 retval |= usage & PIPE_BIND_BLENDABLE;
2180 }
2181
2182 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2183 si_is_zs_format_supported(format)) {
2184 retval |= PIPE_BIND_DEPTH_STENCIL;
2185 }
2186
2187 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2188 retval |= si_is_vertex_format_supported(screen, format,
2189 PIPE_BIND_VERTEX_BUFFER);
2190 }
2191
2192 if ((usage & PIPE_BIND_LINEAR) &&
2193 !util_format_is_compressed(format) &&
2194 !(usage & PIPE_BIND_DEPTH_STENCIL))
2195 retval |= PIPE_BIND_LINEAR;
2196
2197 return retval == usage;
2198 }
2199
2200 /*
2201 * framebuffer handling
2202 */
2203
2204 static void si_choose_spi_color_formats(struct r600_surface *surf,
2205 unsigned format, unsigned swap,
2206 unsigned ntype, bool is_depth)
2207 {
2208 /* Alpha is needed for alpha-to-coverage.
2209 * Blending may be with or without alpha.
2210 */
2211 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2212 unsigned alpha = 0; /* exports alpha, but may not support blending */
2213 unsigned blend = 0; /* supports blending, but may not export alpha */
2214 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2215
2216 /* Choose the SPI color formats. These are required values for RB+.
2217 * Other chips have multiple choices, though they are not necessarily better.
2218 */
2219 switch (format) {
2220 case V_028C70_COLOR_5_6_5:
2221 case V_028C70_COLOR_1_5_5_5:
2222 case V_028C70_COLOR_5_5_5_1:
2223 case V_028C70_COLOR_4_4_4_4:
2224 case V_028C70_COLOR_10_11_11:
2225 case V_028C70_COLOR_11_11_10:
2226 case V_028C70_COLOR_8:
2227 case V_028C70_COLOR_8_8:
2228 case V_028C70_COLOR_8_8_8_8:
2229 case V_028C70_COLOR_10_10_10_2:
2230 case V_028C70_COLOR_2_10_10_10:
2231 if (ntype == V_028C70_NUMBER_UINT)
2232 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2233 else if (ntype == V_028C70_NUMBER_SINT)
2234 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2235 else
2236 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2237 break;
2238
2239 case V_028C70_COLOR_16:
2240 case V_028C70_COLOR_16_16:
2241 case V_028C70_COLOR_16_16_16_16:
2242 if (ntype == V_028C70_NUMBER_UNORM ||
2243 ntype == V_028C70_NUMBER_SNORM) {
2244 /* UNORM16 and SNORM16 don't support blending */
2245 if (ntype == V_028C70_NUMBER_UNORM)
2246 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2247 else
2248 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2249
2250 /* Use 32 bits per channel for blending. */
2251 if (format == V_028C70_COLOR_16) {
2252 if (swap == V_028C70_SWAP_STD) { /* R */
2253 blend = V_028714_SPI_SHADER_32_R;
2254 blend_alpha = V_028714_SPI_SHADER_32_AR;
2255 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2256 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2257 else
2258 assert(0);
2259 } else if (format == V_028C70_COLOR_16_16) {
2260 if (swap == V_028C70_SWAP_STD) { /* RG */
2261 blend = V_028714_SPI_SHADER_32_GR;
2262 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2263 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2264 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2265 else
2266 assert(0);
2267 } else /* 16_16_16_16 */
2268 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2269 } else if (ntype == V_028C70_NUMBER_UINT)
2270 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2271 else if (ntype == V_028C70_NUMBER_SINT)
2272 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2273 else if (ntype == V_028C70_NUMBER_FLOAT)
2274 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2275 else
2276 assert(0);
2277 break;
2278
2279 case V_028C70_COLOR_32:
2280 if (swap == V_028C70_SWAP_STD) { /* R */
2281 blend = normal = V_028714_SPI_SHADER_32_R;
2282 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2283 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2284 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2285 else
2286 assert(0);
2287 break;
2288
2289 case V_028C70_COLOR_32_32:
2290 if (swap == V_028C70_SWAP_STD) { /* RG */
2291 blend = normal = V_028714_SPI_SHADER_32_GR;
2292 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2293 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2295 else
2296 assert(0);
2297 break;
2298
2299 case V_028C70_COLOR_32_32_32_32:
2300 case V_028C70_COLOR_8_24:
2301 case V_028C70_COLOR_24_8:
2302 case V_028C70_COLOR_X24_8_32_FLOAT:
2303 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2304 break;
2305
2306 default:
2307 assert(0);
2308 return;
2309 }
2310
2311 /* The DB->CB copy needs 32_ABGR. */
2312 if (is_depth)
2313 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2314
2315 surf->spi_shader_col_format = normal;
2316 surf->spi_shader_col_format_alpha = alpha;
2317 surf->spi_shader_col_format_blend = blend;
2318 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2319 }
2320
2321 static void si_initialize_color_surface(struct si_context *sctx,
2322 struct r600_surface *surf)
2323 {
2324 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2325 unsigned color_info, color_attrib, color_view;
2326 unsigned format, swap, ntype, endian;
2327 const struct util_format_description *desc;
2328 int firstchan;
2329 unsigned blend_clamp = 0, blend_bypass = 0;
2330
2331 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2332 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2333
2334 desc = util_format_description(surf->base.format);
2335 for (firstchan = 0; firstchan < 4; firstchan++) {
2336 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2337 break;
2338 }
2339 }
2340 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2341 ntype = V_028C70_NUMBER_FLOAT;
2342 } else {
2343 ntype = V_028C70_NUMBER_UNORM;
2344 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2345 ntype = V_028C70_NUMBER_SRGB;
2346 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2347 if (desc->channel[firstchan].pure_integer) {
2348 ntype = V_028C70_NUMBER_SINT;
2349 } else {
2350 assert(desc->channel[firstchan].normalized);
2351 ntype = V_028C70_NUMBER_SNORM;
2352 }
2353 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2354 if (desc->channel[firstchan].pure_integer) {
2355 ntype = V_028C70_NUMBER_UINT;
2356 } else {
2357 assert(desc->channel[firstchan].normalized);
2358 ntype = V_028C70_NUMBER_UNORM;
2359 }
2360 }
2361 }
2362
2363 format = si_translate_colorformat(surf->base.format);
2364 if (format == V_028C70_COLOR_INVALID) {
2365 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2366 }
2367 assert(format != V_028C70_COLOR_INVALID);
2368 swap = si_translate_colorswap(surf->base.format, false);
2369 endian = si_colorformat_endian_swap(format);
2370
2371 /* blend clamp should be set for all NORM/SRGB types */
2372 if (ntype == V_028C70_NUMBER_UNORM ||
2373 ntype == V_028C70_NUMBER_SNORM ||
2374 ntype == V_028C70_NUMBER_SRGB)
2375 blend_clamp = 1;
2376
2377 /* set blend bypass according to docs if SINT/UINT or
2378 8/24 COLOR variants */
2379 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2380 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2381 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2382 blend_clamp = 0;
2383 blend_bypass = 1;
2384 }
2385
2386 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2387 if (format == V_028C70_COLOR_8 ||
2388 format == V_028C70_COLOR_8_8 ||
2389 format == V_028C70_COLOR_8_8_8_8)
2390 surf->color_is_int8 = true;
2391 else if (format == V_028C70_COLOR_10_10_10_2 ||
2392 format == V_028C70_COLOR_2_10_10_10)
2393 surf->color_is_int10 = true;
2394 }
2395
2396 color_info = S_028C70_FORMAT(format) |
2397 S_028C70_COMP_SWAP(swap) |
2398 S_028C70_BLEND_CLAMP(blend_clamp) |
2399 S_028C70_BLEND_BYPASS(blend_bypass) |
2400 S_028C70_SIMPLE_FLOAT(1) |
2401 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2402 ntype != V_028C70_NUMBER_SNORM &&
2403 ntype != V_028C70_NUMBER_SRGB &&
2404 format != V_028C70_COLOR_8_24 &&
2405 format != V_028C70_COLOR_24_8) |
2406 S_028C70_NUMBER_TYPE(ntype) |
2407 S_028C70_ENDIAN(endian);
2408
2409 /* Intensity is implemented as Red, so treat it that way. */
2410 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2411 util_format_is_intensity(surf->base.format));
2412
2413 if (rtex->resource.b.b.nr_samples > 1) {
2414 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2415
2416 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2417 S_028C74_NUM_FRAGMENTS(log_samples);
2418
2419 if (rtex->fmask.size) {
2420 color_info |= S_028C70_COMPRESSION(1);
2421 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2422
2423 if (sctx->b.chip_class == SI) {
2424 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2425 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2426 }
2427 }
2428 }
2429
2430 surf->cb_color_view = color_view;
2431 surf->cb_color_info = color_info;
2432 surf->cb_color_attrib = color_attrib;
2433
2434 if (sctx->b.chip_class >= VI) {
2435 unsigned max_uncompressed_block_size = 2;
2436
2437 if (rtex->resource.b.b.nr_samples > 1) {
2438 if (rtex->surface.bpe == 1)
2439 max_uncompressed_block_size = 0;
2440 else if (rtex->surface.bpe == 2)
2441 max_uncompressed_block_size = 1;
2442 }
2443
2444 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2445 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2446 }
2447
2448 /* This must be set for fast clear to work without FMASK. */
2449 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2450 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2451 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2452 }
2453
2454 if (sctx->b.chip_class >= GFX9) {
2455 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2456
2457 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2458 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2459 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2460 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2461 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2462 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2463 }
2464
2465 /* Determine pixel shader export format */
2466 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2467
2468 surf->color_initialized = true;
2469 }
2470
2471 static void si_init_depth_surface(struct si_context *sctx,
2472 struct r600_surface *surf)
2473 {
2474 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2475 unsigned level = surf->base.u.tex.level;
2476 unsigned format, stencil_format;
2477 uint32_t z_info, s_info;
2478
2479 format = si_translate_dbformat(rtex->db_render_format);
2480 stencil_format = rtex->surface.has_stencil ?
2481 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2482
2483 assert(format != V_028040_Z_INVALID);
2484 if (format == V_028040_Z_INVALID)
2485 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2486
2487 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2488 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2489 surf->db_htile_data_base = 0;
2490 surf->db_htile_surface = 0;
2491
2492 if (sctx->b.chip_class >= GFX9) {
2493 assert(rtex->surface.u.gfx9.surf_offset == 0);
2494 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2495 surf->db_stencil_base = (rtex->resource.gpu_address +
2496 rtex->surface.u.gfx9.stencil_offset) >> 8;
2497 z_info = S_028038_FORMAT(format) |
2498 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2499 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2500 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2501 s_info = S_02803C_FORMAT(stencil_format) |
2502 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2503 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2504 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2505 surf->db_depth_view |= S_028008_MIPID(level);
2506 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2507 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2508
2509 if (r600_htile_enabled(rtex, level)) {
2510 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2511 S_028038_ALLOW_EXPCLEAR(1);
2512
2513 if (rtex->tc_compatible_htile) {
2514 unsigned max_zplanes = 4;
2515
2516 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2517 rtex->resource.b.b.nr_samples > 1)
2518 max_zplanes = 2;
2519
2520 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2521 S_028038_ITERATE_FLUSH(1);
2522 s_info |= S_02803C_ITERATE_FLUSH(1);
2523 }
2524
2525 if (rtex->surface.has_stencil) {
2526 /* Stencil buffer workaround ported from the SI-CI-VI code.
2527 * See that for explanation.
2528 */
2529 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2530 } else {
2531 /* Use all HTILE for depth if there's no stencil. */
2532 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2533 }
2534
2535 surf->db_htile_data_base = (rtex->resource.gpu_address +
2536 rtex->htile_offset) >> 8;
2537 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2538 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2539 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2540 }
2541 } else {
2542 /* SI-CI-VI */
2543 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2544
2545 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2546
2547 surf->db_depth_base = (rtex->resource.gpu_address +
2548 rtex->surface.u.legacy.level[level].offset) >> 8;
2549 surf->db_stencil_base = (rtex->resource.gpu_address +
2550 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2551
2552 z_info = S_028040_FORMAT(format) |
2553 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2554 s_info = S_028044_FORMAT(stencil_format);
2555 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2556
2557 if (sctx->b.chip_class >= CIK) {
2558 struct radeon_info *info = &sctx->screen->b.info;
2559 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2560 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2561 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2562 unsigned tile_mode = info->si_tile_mode_array[index];
2563 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2564 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2565
2566 surf->db_depth_info |=
2567 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2568 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2569 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2570 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2571 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2572 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2573 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2574 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2575 } else {
2576 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2577 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2578 tile_mode_index = si_tile_mode_index(rtex, level, true);
2579 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2580 }
2581
2582 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2583 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2584 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2585 levelinfo->nblk_y) / 64 - 1);
2586
2587 if (r600_htile_enabled(rtex, level)) {
2588 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2589 S_028040_ALLOW_EXPCLEAR(1);
2590
2591 if (rtex->surface.has_stencil) {
2592 /* Workaround: For a not yet understood reason, the
2593 * combination of MSAA, fast stencil clear and stencil
2594 * decompress messes with subsequent stencil buffer
2595 * uses. Problem was reproduced on Verde, Bonaire,
2596 * Tonga, and Carrizo.
2597 *
2598 * Disabling EXPCLEAR works around the problem.
2599 *
2600 * Check piglit's arb_texture_multisample-stencil-clear
2601 * test if you want to try changing this.
2602 */
2603 if (rtex->resource.b.b.nr_samples <= 1)
2604 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2605 } else if (!rtex->tc_compatible_htile) {
2606 /* Use all of the htile_buffer for depth if there's no stencil.
2607 * This must not be set when TC-compatible HTILE is enabled
2608 * due to a hw bug.
2609 */
2610 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2611 }
2612
2613 surf->db_htile_data_base = (rtex->resource.gpu_address +
2614 rtex->htile_offset) >> 8;
2615 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2616
2617 if (rtex->tc_compatible_htile) {
2618 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2619
2620 if (rtex->resource.b.b.nr_samples <= 1)
2621 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2622 else if (rtex->resource.b.b.nr_samples <= 4)
2623 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2624 else
2625 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2626 }
2627 }
2628 }
2629
2630 surf->db_z_info = z_info;
2631 surf->db_stencil_info = s_info;
2632
2633 surf->depth_initialized = true;
2634 }
2635
2636 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2637 {
2638 if (sctx->decompression_enabled)
2639 return;
2640
2641 if (sctx->framebuffer.state.zsbuf) {
2642 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2643 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2644
2645 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2646
2647 if (rtex->surface.has_stencil)
2648 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2649 }
2650
2651 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2652 while (compressed_cb_mask) {
2653 unsigned i = u_bit_scan(&compressed_cb_mask);
2654 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2655 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2656
2657 if (rtex->fmask.size)
2658 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2659 if (rtex->dcc_gather_statistics)
2660 rtex->separate_dcc_dirty = true;
2661 }
2662 }
2663
2664 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2665 {
2666 for (int i = 0; i < state->nr_cbufs; ++i) {
2667 struct r600_surface *surf = NULL;
2668 struct r600_texture *rtex;
2669
2670 if (!state->cbufs[i])
2671 continue;
2672 surf = (struct r600_surface*)state->cbufs[i];
2673 rtex = (struct r600_texture*)surf->base.texture;
2674
2675 p_atomic_dec(&rtex->framebuffers_bound);
2676 }
2677 }
2678
2679 static void si_set_framebuffer_state(struct pipe_context *ctx,
2680 const struct pipe_framebuffer_state *state)
2681 {
2682 struct si_context *sctx = (struct si_context *)ctx;
2683 struct pipe_constant_buffer constbuf = {0};
2684 struct r600_surface *surf = NULL;
2685 struct r600_texture *rtex;
2686 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2687 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2688 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2689 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2690 bool old_has_stencil =
2691 old_has_zsbuf &&
2692 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2693 bool unbound = false;
2694 int i;
2695
2696 si_update_fb_dirtiness_after_rendering(sctx);
2697
2698 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2699 if (!sctx->framebuffer.state.cbufs[i])
2700 continue;
2701
2702 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2703 if (rtex->dcc_gather_statistics)
2704 vi_separate_dcc_stop_query(ctx, rtex);
2705 }
2706
2707 /* Disable DCC if the formats are incompatible. */
2708 for (i = 0; i < state->nr_cbufs; i++) {
2709 if (!state->cbufs[i])
2710 continue;
2711
2712 surf = (struct r600_surface*)state->cbufs[i];
2713 rtex = (struct r600_texture*)surf->base.texture;
2714
2715 if (!surf->dcc_incompatible)
2716 continue;
2717
2718 /* Since the DCC decompression calls back into set_framebuffer-
2719 * _state, we need to unbind the framebuffer, so that
2720 * vi_separate_dcc_stop_query isn't called twice with the same
2721 * color buffer.
2722 */
2723 if (!unbound) {
2724 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2725 unbound = true;
2726 }
2727
2728 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2729 if (!si_texture_disable_dcc(&sctx->b, rtex))
2730 sctx->b.decompress_dcc(ctx, rtex);
2731
2732 surf->dcc_incompatible = false;
2733 }
2734
2735 /* Only flush TC when changing the framebuffer state, because
2736 * the only client not using TC that can change textures is
2737 * the framebuffer.
2738 *
2739 * Wait for compute shaders because of possible transitions:
2740 * - FB write -> shader read
2741 * - shader write -> FB read
2742 *
2743 * DB caches are flushed on demand (using si_decompress_textures).
2744 *
2745 * When MSAA is enabled, CB and TC caches are flushed on demand
2746 * (after FMASK decompression). Shader write -> FB read transitions
2747 * cannot happen for MSAA textures, because MSAA shader images are
2748 * not supported.
2749 *
2750 * Only flush and wait for CB if there is actually a bound color buffer.
2751 */
2752 if (sctx->framebuffer.nr_samples <= 1 &&
2753 sctx->framebuffer.state.nr_cbufs)
2754 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2755 sctx->framebuffer.CB_has_shader_readable_metadata);
2756
2757 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2758
2759 /* u_blitter doesn't invoke depth decompression when it does multiple
2760 * blits in a row, but the only case when it matters for DB is when
2761 * doing generate_mipmap. So here we flush DB manually between
2762 * individual generate_mipmap blits.
2763 * Note that lower mipmap levels aren't compressed.
2764 */
2765 if (sctx->generate_mipmap_for_depth) {
2766 si_make_DB_shader_coherent(sctx, 1, false,
2767 sctx->framebuffer.DB_has_shader_readable_metadata);
2768 } else if (sctx->b.chip_class == GFX9) {
2769 /* It appears that DB metadata "leaks" in a sequence of:
2770 * - depth clear
2771 * - DCC decompress for shader image writes (with DB disabled)
2772 * - render with DEPTH_BEFORE_SHADER=1
2773 * Flushing DB metadata works around the problem.
2774 */
2775 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2776 }
2777
2778 /* Take the maximum of the old and new count. If the new count is lower,
2779 * dirtying is needed to disable the unbound colorbuffers.
2780 */
2781 sctx->framebuffer.dirty_cbufs |=
2782 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2783 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2784
2785 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2786 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2787
2788 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2789 sctx->framebuffer.spi_shader_col_format = 0;
2790 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2791 sctx->framebuffer.spi_shader_col_format_blend = 0;
2792 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2793 sctx->framebuffer.color_is_int8 = 0;
2794 sctx->framebuffer.color_is_int10 = 0;
2795
2796 sctx->framebuffer.compressed_cb_mask = 0;
2797 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2798 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2799 sctx->framebuffer.any_dst_linear = false;
2800 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2801 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2802
2803 for (i = 0; i < state->nr_cbufs; i++) {
2804 if (!state->cbufs[i])
2805 continue;
2806
2807 surf = (struct r600_surface*)state->cbufs[i];
2808 rtex = (struct r600_texture*)surf->base.texture;
2809
2810 if (!surf->color_initialized) {
2811 si_initialize_color_surface(sctx, surf);
2812 }
2813
2814 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2815 sctx->framebuffer.spi_shader_col_format |=
2816 surf->spi_shader_col_format << (i * 4);
2817 sctx->framebuffer.spi_shader_col_format_alpha |=
2818 surf->spi_shader_col_format_alpha << (i * 4);
2819 sctx->framebuffer.spi_shader_col_format_blend |=
2820 surf->spi_shader_col_format_blend << (i * 4);
2821 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2822 surf->spi_shader_col_format_blend_alpha << (i * 4);
2823
2824 if (surf->color_is_int8)
2825 sctx->framebuffer.color_is_int8 |= 1 << i;
2826 if (surf->color_is_int10)
2827 sctx->framebuffer.color_is_int10 |= 1 << i;
2828
2829 if (rtex->fmask.size) {
2830 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2831 }
2832
2833 if (rtex->surface.is_linear)
2834 sctx->framebuffer.any_dst_linear = true;
2835
2836 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2837 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2838
2839 r600_context_add_resource_size(ctx, surf->base.texture);
2840
2841 p_atomic_inc(&rtex->framebuffers_bound);
2842
2843 if (rtex->dcc_gather_statistics) {
2844 /* Dirty tracking must be enabled for DCC usage analysis. */
2845 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2846 vi_separate_dcc_start_query(ctx, rtex);
2847 }
2848 }
2849
2850 struct r600_texture *zstex = NULL;
2851
2852 if (state->zsbuf) {
2853 surf = (struct r600_surface*)state->zsbuf;
2854 zstex = (struct r600_texture*)surf->base.texture;
2855
2856 if (!surf->depth_initialized) {
2857 si_init_depth_surface(sctx, surf);
2858 }
2859
2860 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2861 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2862
2863 r600_context_add_resource_size(ctx, surf->base.texture);
2864 }
2865
2866 si_update_poly_offset_state(sctx);
2867 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2868 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2869
2870 if (sctx->screen->dpbb_allowed)
2871 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2872
2873 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2874 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2875
2876 if (sctx->screen->has_out_of_order_rast &&
2877 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2878 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2879 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2880 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2881
2882 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2883 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2884 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2885
2886 /* Set sample locations as fragment shader constants. */
2887 switch (sctx->framebuffer.nr_samples) {
2888 case 1:
2889 constbuf.user_buffer = sctx->sample_locations_1x;
2890 break;
2891 case 2:
2892 constbuf.user_buffer = sctx->sample_locations_2x;
2893 break;
2894 case 4:
2895 constbuf.user_buffer = sctx->sample_locations_4x;
2896 break;
2897 case 8:
2898 constbuf.user_buffer = sctx->sample_locations_8x;
2899 break;
2900 case 16:
2901 constbuf.user_buffer = sctx->sample_locations_16x;
2902 break;
2903 default:
2904 R600_ERR("Requested an invalid number of samples %i.\n",
2905 sctx->framebuffer.nr_samples);
2906 assert(0);
2907 }
2908 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2909 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2910
2911 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2912 }
2913
2914 sctx->do_update_shaders = true;
2915
2916 if (!sctx->decompression_enabled) {
2917 /* Prevent textures decompression when the framebuffer state
2918 * changes come from the decompression passes themselves.
2919 */
2920 sctx->need_check_render_feedback = true;
2921 }
2922 }
2923
2924 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2925 {
2926 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2927 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2928 unsigned i, nr_cbufs = state->nr_cbufs;
2929 struct r600_texture *tex = NULL;
2930 struct r600_surface *cb = NULL;
2931 unsigned cb_color_info = 0;
2932
2933 /* Colorbuffers. */
2934 for (i = 0; i < nr_cbufs; i++) {
2935 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2936 unsigned cb_color_attrib;
2937
2938 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2939 continue;
2940
2941 cb = (struct r600_surface*)state->cbufs[i];
2942 if (!cb) {
2943 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2944 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2945 continue;
2946 }
2947
2948 tex = (struct r600_texture *)cb->base.texture;
2949 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2950 &tex->resource, RADEON_USAGE_READWRITE,
2951 tex->resource.b.b.nr_samples > 1 ?
2952 RADEON_PRIO_COLOR_BUFFER_MSAA :
2953 RADEON_PRIO_COLOR_BUFFER);
2954
2955 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2956 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2957 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2958 RADEON_PRIO_CMASK);
2959 }
2960
2961 if (tex->dcc_separate_buffer)
2962 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2963 tex->dcc_separate_buffer,
2964 RADEON_USAGE_READWRITE,
2965 RADEON_PRIO_DCC);
2966
2967 /* Compute mutable surface parameters. */
2968 cb_color_base = tex->resource.gpu_address >> 8;
2969 cb_color_fmask = 0;
2970 cb_dcc_base = 0;
2971 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2972 cb_color_attrib = cb->cb_color_attrib;
2973
2974 if (tex->fmask.size) {
2975 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2976 cb_color_fmask |= tex->fmask.tile_swizzle;
2977 }
2978
2979 /* Set up DCC. */
2980 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2981 bool is_msaa_resolve_dst = state->cbufs[0] &&
2982 state->cbufs[0]->texture->nr_samples > 1 &&
2983 state->cbufs[1] == &cb->base &&
2984 state->cbufs[1]->texture->nr_samples <= 1;
2985
2986 if (!is_msaa_resolve_dst)
2987 cb_color_info |= S_028C70_DCC_ENABLE(1);
2988
2989 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2990 tex->dcc_offset) >> 8;
2991 cb_dcc_base |= tex->surface.tile_swizzle;
2992 }
2993
2994 if (sctx->b.chip_class >= GFX9) {
2995 struct gfx9_surf_meta_flags meta;
2996
2997 if (tex->dcc_offset)
2998 meta = tex->surface.u.gfx9.dcc;
2999 else
3000 meta = tex->surface.u.gfx9.cmask;
3001
3002 /* Set mutable surface parameters. */
3003 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3004 cb_color_base |= tex->surface.tile_swizzle;
3005 if (!tex->fmask.size)
3006 cb_color_fmask = cb_color_base;
3007 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3008 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3009 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3010 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3011
3012 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3013 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3014 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
3015 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3016 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3017 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3018 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3019 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3020 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3021 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
3022 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3023 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
3024 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3025 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3026 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3027 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
3028
3029 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3030 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3031 } else {
3032 /* Compute mutable surface parameters (SI-CI-VI). */
3033 const struct legacy_surf_level *level_info =
3034 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3035 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3036 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3037
3038 cb_color_base += level_info->offset >> 8;
3039 /* Only macrotiled modes can set tile swizzle. */
3040 if (level_info->mode == RADEON_SURF_MODE_2D)
3041 cb_color_base |= tex->surface.tile_swizzle;
3042
3043 if (!tex->fmask.size)
3044 cb_color_fmask = cb_color_base;
3045 if (cb_dcc_base)
3046 cb_dcc_base += level_info->dcc_offset >> 8;
3047
3048 pitch_tile_max = level_info->nblk_x / 8 - 1;
3049 slice_tile_max = level_info->nblk_x *
3050 level_info->nblk_y / 64 - 1;
3051 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3052
3053 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3054 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3055 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3056
3057 if (tex->fmask.size) {
3058 if (sctx->b.chip_class >= CIK)
3059 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3060 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3061 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3062 } else {
3063 /* This must be set for fast clear to work without FMASK. */
3064 if (sctx->b.chip_class >= CIK)
3065 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3066 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3067 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3068 }
3069
3070 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3071 sctx->b.chip_class >= VI ? 14 : 13);
3072 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3073 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3074 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3075 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3076 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3077 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3078 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3079 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3080 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3081 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3082 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3083 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3084 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3085
3086 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3087 radeon_emit(cs, cb_dcc_base);
3088 }
3089 }
3090 for (; i < 8 ; i++)
3091 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3092 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3093
3094 /* ZS buffer. */
3095 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3096 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3097 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3098
3099 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3100 &rtex->resource, RADEON_USAGE_READWRITE,
3101 zb->base.texture->nr_samples > 1 ?
3102 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3103 RADEON_PRIO_DEPTH_BUFFER);
3104
3105 if (sctx->b.chip_class >= GFX9) {
3106 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3107 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3108 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3109 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3110
3111 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3112 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3113 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3114 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3115 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3116 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3117 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3118 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3119 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3120 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3121 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3122 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3123
3124 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3125 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3126 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3127 } else {
3128 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3129
3130 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3131 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3132 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3133 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3134 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3135 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3136 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3137 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3138 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3139 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3140 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3141 }
3142
3143 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3144 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3145 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3146
3147 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3148 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3149 } else if (sctx->framebuffer.dirty_zsbuf) {
3150 if (sctx->b.chip_class >= GFX9)
3151 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3152 else
3153 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3154
3155 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3156 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3157 }
3158
3159 /* Framebuffer dimensions. */
3160 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3161 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3162 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3163
3164 if (sctx->screen->dfsm_allowed) {
3165 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3166 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3167 }
3168
3169 sctx->framebuffer.dirty_cbufs = 0;
3170 sctx->framebuffer.dirty_zsbuf = false;
3171 }
3172
3173 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3174 struct r600_atom *atom)
3175 {
3176 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3177 unsigned nr_samples = sctx->framebuffer.nr_samples;
3178 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3179
3180 /* Smoothing (only possible with nr_samples == 1) uses the same
3181 * sample locations as the MSAA it simulates.
3182 */
3183 if (nr_samples <= 1 && sctx->smoothing_enabled)
3184 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3185
3186 /* On Polaris, the small primitive filter uses the sample locations
3187 * even when MSAA is off, so we need to make sure they're set to 0.
3188 */
3189 if (has_msaa_sample_loc_bug)
3190 nr_samples = MAX2(nr_samples, 1);
3191
3192 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3193 sctx->msaa_sample_locs.nr_samples = nr_samples;
3194 si_emit_sample_locations(cs, nr_samples);
3195 }
3196
3197 if (sctx->b.family >= CHIP_POLARIS10) {
3198 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3199 unsigned small_prim_filter_cntl =
3200 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3201 /* line bug */
3202 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3203
3204 /* The alternative of setting sample locations to 0 would
3205 * require a DB flush to avoid Z errors, see
3206 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3207 */
3208 if (has_msaa_sample_loc_bug &&
3209 sctx->framebuffer.nr_samples > 1 &&
3210 rs && !rs->multisample_enable)
3211 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3212
3213 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3214 small_prim_filter_cntl);
3215 }
3216 }
3217
3218 static bool si_out_of_order_rasterization(struct si_context *sctx)
3219 {
3220 struct si_state_blend *blend = sctx->queued.named.blend;
3221 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3222
3223 if (!sctx->screen->has_out_of_order_rast)
3224 return false;
3225
3226 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3227
3228 if (blend) {
3229 colormask &= blend->cb_target_enabled_4bit;
3230 } else {
3231 colormask = 0;
3232 }
3233
3234 /* Conservative: No logic op. */
3235 if (colormask && blend->logicop_enable)
3236 return false;
3237
3238 struct si_dsa_order_invariance dsa_order_invariant = {
3239 .zs = true, .pass_set = true, .pass_last = false
3240 };
3241
3242 if (sctx->framebuffer.state.zsbuf) {
3243 struct r600_texture *zstex =
3244 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3245 bool has_stencil = zstex->surface.has_stencil;
3246 dsa_order_invariant = dsa->order_invariance[has_stencil];
3247 if (!dsa_order_invariant.zs)
3248 return false;
3249
3250 /* The set of PS invocations is always order invariant,
3251 * except when early Z/S tests are requested. */
3252 if (sctx->ps_shader.cso &&
3253 sctx->ps_shader.cso->info.writes_memory &&
3254 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3255 !dsa_order_invariant.pass_set)
3256 return false;
3257
3258 if (sctx->b.num_perfect_occlusion_queries != 0 &&
3259 !dsa_order_invariant.pass_set)
3260 return false;
3261 }
3262
3263 if (!colormask)
3264 return true;
3265
3266 unsigned blendmask = colormask & blend->blend_enable_4bit;
3267
3268 if (blendmask) {
3269 /* Only commutative blending. */
3270 if (blendmask & ~blend->commutative_4bit)
3271 return false;
3272
3273 if (!dsa_order_invariant.pass_set)
3274 return false;
3275 }
3276
3277 if (colormask & ~blendmask) {
3278 if (!dsa_order_invariant.pass_last)
3279 return false;
3280 }
3281
3282 return true;
3283 }
3284
3285 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3286 {
3287 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3288 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
3289 /* 33% faster rendering to linear color buffers */
3290 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3291 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3292 unsigned sc_mode_cntl_1 =
3293 S_028A4C_WALK_SIZE(dst_is_linear) |
3294 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3295 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3296 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3297 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3298 /* always 1: */
3299 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3300 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3301 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3302 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3303 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3304 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3305
3306 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3307 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3308
3309 /* Required by OpenGL line rasterization.
3310 *
3311 * TODO: We should also enable perpendicular endcaps for AA lines,
3312 * but that requires implementing line stippling in the pixel
3313 * shader. SC can only do line stippling with axis-aligned
3314 * endcaps.
3315 */
3316 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3317
3318 if (setup_samples > 1) {
3319 /* distance from the pixel center, indexed by log2(nr_samples) */
3320 static unsigned max_dist[] = {
3321 0, /* unused */
3322 4, /* 2x MSAA */
3323 6, /* 4x MSAA */
3324 7, /* 8x MSAA */
3325 8, /* 16x MSAA */
3326 };
3327 unsigned log_samples = util_logbase2(setup_samples);
3328 unsigned log_ps_iter_samples =
3329 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
3330
3331 radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
3332 radeon_emit(cs, sc_line_cntl |
3333 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3334 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3335 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3336 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3337
3338 if (sctx->framebuffer.nr_samples > 1) {
3339 radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
3340 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3341 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3342 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3343 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3344 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3345 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3346 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
3347 EG_S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
3348 sc_mode_cntl_1);
3349 } else if (sctx->smoothing_enabled) {
3350 radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
3351 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3352 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3353 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3354 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
3355 sc_mode_cntl_1);
3356 }
3357 } else {
3358 radeon_set_context_reg_seq(cs, CM_R_028BDC_PA_SC_LINE_CNTL, 2);
3359 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3360 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3361
3362 radeon_set_context_reg(cs, CM_R_028804_DB_EQAA,
3363 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3364 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3365 radeon_set_context_reg(cs, EG_R_028A4C_PA_SC_MODE_CNTL_1,
3366 sc_mode_cntl_1);
3367 }
3368
3369 /* GFX9: Flush DFSM when the AA mode changes. */
3370 if (sctx->screen->dfsm_allowed) {
3371 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3372 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3373 }
3374 }
3375
3376 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3377 {
3378 struct si_context *sctx = (struct si_context *)ctx;
3379
3380 if (sctx->ps_iter_samples == min_samples)
3381 return;
3382
3383 sctx->ps_iter_samples = min_samples;
3384 sctx->do_update_shaders = true;
3385
3386 if (sctx->framebuffer.nr_samples > 1)
3387 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3388 if (sctx->screen->dpbb_allowed)
3389 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3390 }
3391
3392 /*
3393 * Samplers
3394 */
3395
3396 /**
3397 * Build the sampler view descriptor for a buffer texture.
3398 * @param state 256-bit descriptor; only the high 128 bits are filled in
3399 */
3400 void
3401 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3402 enum pipe_format format,
3403 unsigned offset, unsigned size,
3404 uint32_t *state)
3405 {
3406 const struct util_format_description *desc;
3407 int first_non_void;
3408 unsigned stride;
3409 unsigned num_records;
3410 unsigned num_format, data_format;
3411
3412 desc = util_format_description(format);
3413 first_non_void = util_format_get_first_non_void_channel(format);
3414 stride = desc->block.bits / 8;
3415 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3416 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3417
3418 num_records = size / stride;
3419 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3420
3421 /* The NUM_RECORDS field has a different meaning depending on the chip,
3422 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3423 *
3424 * SI-CIK:
3425 * - If STRIDE == 0, it's in byte units.
3426 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3427 *
3428 * VI:
3429 * - For SMEM and STRIDE == 0, it's in byte units.
3430 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3431 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3432 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3433 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3434 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3435 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3436 * That way the same descriptor can be used by both SMEM and VMEM.
3437 *
3438 * GFX9:
3439 * - For SMEM and STRIDE == 0, it's in byte units.
3440 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3441 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3442 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3443 */
3444 if (screen->b.chip_class >= GFX9)
3445 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3446 * from STRIDE to bytes. This works around it by setting
3447 * NUM_RECORDS to at least the size of one element, so that
3448 * the first element is readable when IDXEN == 0.
3449 *
3450 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3451 * IDXEN is enforced?
3452 */
3453 num_records = num_records ? MAX2(num_records, stride) : 0;
3454 else if (screen->b.chip_class == VI)
3455 num_records *= stride;
3456
3457 state[4] = 0;
3458 state[5] = S_008F04_STRIDE(stride);
3459 state[6] = num_records;
3460 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3461 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3462 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3463 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3464 S_008F0C_NUM_FORMAT(num_format) |
3465 S_008F0C_DATA_FORMAT(data_format);
3466 }
3467
3468 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3469 {
3470 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3471
3472 if (swizzle[3] == PIPE_SWIZZLE_X) {
3473 /* For the pre-defined border color values (white, opaque
3474 * black, transparent black), the only thing that matters is
3475 * that the alpha channel winds up in the correct place
3476 * (because the RGB channels are all the same) so either of
3477 * these enumerations will work.
3478 */
3479 if (swizzle[2] == PIPE_SWIZZLE_Y)
3480 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3481 else
3482 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3483 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3484 if (swizzle[1] == PIPE_SWIZZLE_Y)
3485 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3486 else
3487 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3488 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3489 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3490 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3491 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3492 }
3493
3494 return bc_swizzle;
3495 }
3496
3497 /**
3498 * Build the sampler view descriptor for a texture.
3499 */
3500 void
3501 si_make_texture_descriptor(struct si_screen *screen,
3502 struct r600_texture *tex,
3503 bool sampler,
3504 enum pipe_texture_target target,
3505 enum pipe_format pipe_format,
3506 const unsigned char state_swizzle[4],
3507 unsigned first_level, unsigned last_level,
3508 unsigned first_layer, unsigned last_layer,
3509 unsigned width, unsigned height, unsigned depth,
3510 uint32_t *state,
3511 uint32_t *fmask_state)
3512 {
3513 struct pipe_resource *res = &tex->resource.b.b;
3514 const struct util_format_description *desc;
3515 unsigned char swizzle[4];
3516 int first_non_void;
3517 unsigned num_format, data_format, type;
3518 uint64_t va;
3519
3520 desc = util_format_description(pipe_format);
3521
3522 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3523 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3524 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3525 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3526
3527 switch (pipe_format) {
3528 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3529 case PIPE_FORMAT_X32_S8X24_UINT:
3530 case PIPE_FORMAT_X8Z24_UNORM:
3531 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3532 break;
3533 case PIPE_FORMAT_X24S8_UINT:
3534 /*
3535 * X24S8 is implemented as an 8_8_8_8 data format, to
3536 * fix texture gathers. This affects at least
3537 * GL45-CTS.texture_cube_map_array.sampling on VI.
3538 */
3539 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3540 break;
3541 default:
3542 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3543 }
3544 } else {
3545 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3546 }
3547
3548 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3549
3550 switch (pipe_format) {
3551 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3552 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3553 break;
3554 default:
3555 if (first_non_void < 0) {
3556 if (util_format_is_compressed(pipe_format)) {
3557 switch (pipe_format) {
3558 case PIPE_FORMAT_DXT1_SRGB:
3559 case PIPE_FORMAT_DXT1_SRGBA:
3560 case PIPE_FORMAT_DXT3_SRGBA:
3561 case PIPE_FORMAT_DXT5_SRGBA:
3562 case PIPE_FORMAT_BPTC_SRGBA:
3563 case PIPE_FORMAT_ETC2_SRGB8:
3564 case PIPE_FORMAT_ETC2_SRGB8A1:
3565 case PIPE_FORMAT_ETC2_SRGBA8:
3566 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3567 break;
3568 case PIPE_FORMAT_RGTC1_SNORM:
3569 case PIPE_FORMAT_LATC1_SNORM:
3570 case PIPE_FORMAT_RGTC2_SNORM:
3571 case PIPE_FORMAT_LATC2_SNORM:
3572 case PIPE_FORMAT_ETC2_R11_SNORM:
3573 case PIPE_FORMAT_ETC2_RG11_SNORM:
3574 /* implies float, so use SNORM/UNORM to determine
3575 whether data is signed or not */
3576 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3577 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3578 break;
3579 default:
3580 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3581 break;
3582 }
3583 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3584 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3585 } else {
3586 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3587 }
3588 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3589 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3590 } else {
3591 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3592
3593 switch (desc->channel[first_non_void].type) {
3594 case UTIL_FORMAT_TYPE_FLOAT:
3595 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3596 break;
3597 case UTIL_FORMAT_TYPE_SIGNED:
3598 if (desc->channel[first_non_void].normalized)
3599 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3600 else if (desc->channel[first_non_void].pure_integer)
3601 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3602 else
3603 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3604 break;
3605 case UTIL_FORMAT_TYPE_UNSIGNED:
3606 if (desc->channel[first_non_void].normalized)
3607 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3608 else if (desc->channel[first_non_void].pure_integer)
3609 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3610 else
3611 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3612 }
3613 }
3614 }
3615
3616 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3617 if (data_format == ~0) {
3618 data_format = 0;
3619 }
3620
3621 /* S8 with Z32 HTILE needs a special format. */
3622 if (screen->b.chip_class >= GFX9 &&
3623 pipe_format == PIPE_FORMAT_S8_UINT &&
3624 tex->tc_compatible_htile)
3625 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3626
3627 if (!sampler &&
3628 (res->target == PIPE_TEXTURE_CUBE ||
3629 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3630 (screen->b.chip_class <= VI &&
3631 res->target == PIPE_TEXTURE_3D))) {
3632 /* For the purpose of shader images, treat cube maps and 3D
3633 * textures as 2D arrays. For 3D textures, the address
3634 * calculations for mipmaps are different, so we rely on the
3635 * caller to effectively disable mipmaps.
3636 */
3637 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3638
3639 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3640 } else {
3641 type = si_tex_dim(screen, tex, target, res->nr_samples);
3642 }
3643
3644 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3645 height = 1;
3646 depth = res->array_size;
3647 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3648 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3649 if (sampler || res->target != PIPE_TEXTURE_3D)
3650 depth = res->array_size;
3651 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3652 depth = res->array_size / 6;
3653
3654 state[0] = 0;
3655 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3656 S_008F14_NUM_FORMAT_GFX6(num_format));
3657 state[2] = (S_008F18_WIDTH(width - 1) |
3658 S_008F18_HEIGHT(height - 1) |
3659 S_008F18_PERF_MOD(4));
3660 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3661 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3662 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3663 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3664 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3665 0 : first_level) |
3666 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3667 util_logbase2(res->nr_samples) :
3668 last_level) |
3669 S_008F1C_TYPE(type));
3670 state[4] = 0;
3671 state[5] = S_008F24_BASE_ARRAY(first_layer);
3672 state[6] = 0;
3673 state[7] = 0;
3674
3675 if (screen->b.chip_class >= GFX9) {
3676 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3677
3678 /* Depth is the the last accessible layer on Gfx9.
3679 * The hw doesn't need to know the total number of layers.
3680 */
3681 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3682 state[4] |= S_008F20_DEPTH(depth - 1);
3683 else
3684 state[4] |= S_008F20_DEPTH(last_layer);
3685
3686 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3687 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3688 util_logbase2(res->nr_samples) :
3689 tex->resource.b.b.last_level);
3690 } else {
3691 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3692 state[4] |= S_008F20_DEPTH(depth - 1);
3693 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3694 }
3695
3696 if (tex->dcc_offset) {
3697 unsigned swap = si_translate_colorswap(pipe_format, false);
3698
3699 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3700 } else {
3701 /* The last dword is unused by hw. The shader uses it to clear
3702 * bits in the first dword of sampler state.
3703 */
3704 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3705 if (first_level == last_level)
3706 state[7] = C_008F30_MAX_ANISO_RATIO;
3707 else
3708 state[7] = 0xffffffff;
3709 }
3710 }
3711
3712 /* Initialize the sampler view for FMASK. */
3713 if (tex->fmask.size) {
3714 uint32_t data_format, num_format;
3715
3716 va = tex->resource.gpu_address + tex->fmask.offset;
3717
3718 if (screen->b.chip_class >= GFX9) {
3719 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3720 switch (res->nr_samples) {
3721 case 2:
3722 num_format = V_008F14_IMG_FMASK_8_2_2;
3723 break;
3724 case 4:
3725 num_format = V_008F14_IMG_FMASK_8_4_4;
3726 break;
3727 case 8:
3728 num_format = V_008F14_IMG_FMASK_32_8_8;
3729 break;
3730 default:
3731 unreachable("invalid nr_samples");
3732 }
3733 } else {
3734 switch (res->nr_samples) {
3735 case 2:
3736 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3737 break;
3738 case 4:
3739 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3740 break;
3741 case 8:
3742 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3743 break;
3744 default:
3745 unreachable("invalid nr_samples");
3746 }
3747 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3748 }
3749
3750 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3751 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3752 S_008F14_DATA_FORMAT_GFX6(data_format) |
3753 S_008F14_NUM_FORMAT_GFX6(num_format);
3754 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3755 S_008F18_HEIGHT(height - 1);
3756 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3757 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3758 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3759 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3760 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3761 fmask_state[4] = 0;
3762 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3763 fmask_state[6] = 0;
3764 fmask_state[7] = 0;
3765
3766 if (screen->b.chip_class >= GFX9) {
3767 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3768 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3769 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3770 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3771 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3772 } else {
3773 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3774 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3775 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3776 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3777 }
3778 }
3779 }
3780
3781 /**
3782 * Create a sampler view.
3783 *
3784 * @param ctx context
3785 * @param texture texture
3786 * @param state sampler view template
3787 * @param width0 width0 override (for compressed textures as int)
3788 * @param height0 height0 override (for compressed textures as int)
3789 * @param force_level set the base address to the level (for compressed textures)
3790 */
3791 struct pipe_sampler_view *
3792 si_create_sampler_view_custom(struct pipe_context *ctx,
3793 struct pipe_resource *texture,
3794 const struct pipe_sampler_view *state,
3795 unsigned width0, unsigned height0,
3796 unsigned force_level)
3797 {
3798 struct si_context *sctx = (struct si_context*)ctx;
3799 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3800 struct r600_texture *tmp = (struct r600_texture*)texture;
3801 unsigned base_level, first_level, last_level;
3802 unsigned char state_swizzle[4];
3803 unsigned height, depth, width;
3804 unsigned last_layer = state->u.tex.last_layer;
3805 enum pipe_format pipe_format;
3806 const struct legacy_surf_level *surflevel;
3807
3808 if (!view)
3809 return NULL;
3810
3811 /* initialize base object */
3812 view->base = *state;
3813 view->base.texture = NULL;
3814 view->base.reference.count = 1;
3815 view->base.context = ctx;
3816
3817 assert(texture);
3818 pipe_resource_reference(&view->base.texture, texture);
3819
3820 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3821 state->format == PIPE_FORMAT_S8X24_UINT ||
3822 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3823 state->format == PIPE_FORMAT_S8_UINT)
3824 view->is_stencil_sampler = true;
3825
3826 /* Buffer resource. */
3827 if (texture->target == PIPE_BUFFER) {
3828 si_make_buffer_descriptor(sctx->screen,
3829 (struct r600_resource *)texture,
3830 state->format,
3831 state->u.buf.offset,
3832 state->u.buf.size,
3833 view->state);
3834 return &view->base;
3835 }
3836
3837 state_swizzle[0] = state->swizzle_r;
3838 state_swizzle[1] = state->swizzle_g;
3839 state_swizzle[2] = state->swizzle_b;
3840 state_swizzle[3] = state->swizzle_a;
3841
3842 base_level = 0;
3843 first_level = state->u.tex.first_level;
3844 last_level = state->u.tex.last_level;
3845 width = width0;
3846 height = height0;
3847 depth = texture->depth0;
3848
3849 if (sctx->b.chip_class <= VI && force_level) {
3850 assert(force_level == first_level &&
3851 force_level == last_level);
3852 base_level = force_level;
3853 first_level = 0;
3854 last_level = 0;
3855 width = u_minify(width, force_level);
3856 height = u_minify(height, force_level);
3857 depth = u_minify(depth, force_level);
3858 }
3859
3860 /* This is not needed if state trackers set last_layer correctly. */
3861 if (state->target == PIPE_TEXTURE_1D ||
3862 state->target == PIPE_TEXTURE_2D ||
3863 state->target == PIPE_TEXTURE_RECT ||
3864 state->target == PIPE_TEXTURE_CUBE)
3865 last_layer = state->u.tex.first_layer;
3866
3867 /* Texturing with separate depth and stencil. */
3868 pipe_format = state->format;
3869
3870 /* Depth/stencil texturing sometimes needs separate texture. */
3871 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3872 if (!tmp->flushed_depth_texture &&
3873 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3874 pipe_resource_reference(&view->base.texture, NULL);
3875 FREE(view);
3876 return NULL;
3877 }
3878
3879 assert(tmp->flushed_depth_texture);
3880
3881 /* Override format for the case where the flushed texture
3882 * contains only Z or only S.
3883 */
3884 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3885 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3886
3887 tmp = tmp->flushed_depth_texture;
3888 }
3889
3890 surflevel = tmp->surface.u.legacy.level;
3891
3892 if (tmp->db_compatible) {
3893 if (!view->is_stencil_sampler)
3894 pipe_format = tmp->db_render_format;
3895
3896 switch (pipe_format) {
3897 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3898 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3899 break;
3900 case PIPE_FORMAT_X8Z24_UNORM:
3901 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3902 /* Z24 is always stored like this for DB
3903 * compatibility.
3904 */
3905 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3906 break;
3907 case PIPE_FORMAT_X24S8_UINT:
3908 case PIPE_FORMAT_S8X24_UINT:
3909 case PIPE_FORMAT_X32_S8X24_UINT:
3910 pipe_format = PIPE_FORMAT_S8_UINT;
3911 surflevel = tmp->surface.u.legacy.stencil_level;
3912 break;
3913 default:;
3914 }
3915 }
3916
3917 view->dcc_incompatible =
3918 vi_dcc_formats_are_incompatible(texture,
3919 state->u.tex.first_level,
3920 state->format);
3921
3922 si_make_texture_descriptor(sctx->screen, tmp, true,
3923 state->target, pipe_format, state_swizzle,
3924 first_level, last_level,
3925 state->u.tex.first_layer, last_layer,
3926 width, height, depth,
3927 view->state, view->fmask_state);
3928
3929 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3930 view->is_integer =
3931 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3932 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3933 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3934 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3935 view->base_level_info = &surflevel[base_level];
3936 view->base_level = base_level;
3937 view->block_width = util_format_get_blockwidth(pipe_format);
3938 return &view->base;
3939 }
3940
3941 static struct pipe_sampler_view *
3942 si_create_sampler_view(struct pipe_context *ctx,
3943 struct pipe_resource *texture,
3944 const struct pipe_sampler_view *state)
3945 {
3946 return si_create_sampler_view_custom(ctx, texture, state,
3947 texture ? texture->width0 : 0,
3948 texture ? texture->height0 : 0, 0);
3949 }
3950
3951 static void si_sampler_view_destroy(struct pipe_context *ctx,
3952 struct pipe_sampler_view *state)
3953 {
3954 struct si_sampler_view *view = (struct si_sampler_view *)state;
3955
3956 pipe_resource_reference(&state->texture, NULL);
3957 FREE(view);
3958 }
3959
3960 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3961 {
3962 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3963 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3964 (linear_filter &&
3965 (wrap == PIPE_TEX_WRAP_CLAMP ||
3966 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3967 }
3968
3969 static uint32_t si_translate_border_color(struct si_context *sctx,
3970 const struct pipe_sampler_state *state,
3971 const union pipe_color_union *color,
3972 bool is_integer)
3973 {
3974 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3975 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3976
3977 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
3978 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
3979 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
3980 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
3981
3982 #define simple_border_types(elt) \
3983 do { \
3984 if (color->elt[0] == 0 && color->elt[1] == 0 && \
3985 color->elt[2] == 0 && color->elt[3] == 0) \
3986 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
3987 if (color->elt[0] == 0 && color->elt[1] == 0 && \
3988 color->elt[2] == 0 && color->elt[3] == 1) \
3989 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
3990 if (color->elt[0] == 1 && color->elt[1] == 1 && \
3991 color->elt[2] == 1 && color->elt[3] == 1) \
3992 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
3993 } while (false)
3994
3995 if (is_integer)
3996 simple_border_types(ui);
3997 else
3998 simple_border_types(f);
3999
4000 #undef simple_border_types
4001
4002 int i;
4003
4004 /* Check if the border has been uploaded already. */
4005 for (i = 0; i < sctx->border_color_count; i++)
4006 if (memcmp(&sctx->border_color_table[i], color,
4007 sizeof(*color)) == 0)
4008 break;
4009
4010 if (i >= SI_MAX_BORDER_COLORS) {
4011 /* Getting 4096 unique border colors is very unlikely. */
4012 fprintf(stderr, "radeonsi: The border color table is full. "
4013 "Any new border colors will be just black. "
4014 "Please file a bug.\n");
4015 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4016 }
4017
4018 if (i == sctx->border_color_count) {
4019 /* Upload a new border color. */
4020 memcpy(&sctx->border_color_table[i], color,
4021 sizeof(*color));
4022 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4023 color, sizeof(*color));
4024 sctx->border_color_count++;
4025 }
4026
4027 return S_008F3C_BORDER_COLOR_PTR(i) |
4028 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4029 }
4030
4031 static void *si_create_sampler_state(struct pipe_context *ctx,
4032 const struct pipe_sampler_state *state)
4033 {
4034 struct si_context *sctx = (struct si_context *)ctx;
4035 struct r600_common_screen *rscreen = sctx->b.screen;
4036 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4037 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
4038 : state->max_anisotropy;
4039 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
4040 union pipe_color_union clamped_border_color;
4041
4042 if (!rstate) {
4043 return NULL;
4044 }
4045
4046 #ifdef DEBUG
4047 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4048 #endif
4049 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4050 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4051 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4052 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4053 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4054 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4055 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4056 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4057 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4058 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
4059 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4060 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4061 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4062 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4063 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
4064 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
4065 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4066 S_008F38_MIP_POINT_PRECLAMP(0) |
4067 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
4068 S_008F38_FILTER_PREC_FIX(1) |
4069 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
4070 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4071
4072 /* Create sampler resource for integer textures. */
4073 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4074 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4075
4076 /* Create sampler resource for upgraded depth textures. */
4077 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4078
4079 for (unsigned i = 0; i < 4; ++i) {
4080 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4081 * when the border color is 1.0. */
4082 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4083 }
4084
4085 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4086 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4087 else
4088 rstate->upgraded_depth_val[3] =
4089 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4090 S_008F3C_UPGRADED_DEPTH(1);
4091
4092 return rstate;
4093 }
4094
4095 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4096 {
4097 struct si_context *sctx = (struct si_context *)ctx;
4098
4099 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4100 return;
4101
4102 sctx->sample_mask.sample_mask = sample_mask;
4103 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4104 }
4105
4106 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4107 {
4108 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
4109 unsigned mask = sctx->sample_mask.sample_mask;
4110
4111 /* Needed for line and polygon smoothing as well as for the Polaris
4112 * small primitive filter. We expect the state tracker to take care of
4113 * this for us.
4114 */
4115 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4116 (mask & 1 && sctx->blitter->running));
4117
4118 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4119 radeon_emit(cs, mask | (mask << 16));
4120 radeon_emit(cs, mask | (mask << 16));
4121 }
4122
4123 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4124 {
4125 #ifdef DEBUG
4126 struct si_sampler_state *s = state;
4127
4128 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4129 s->magic = 0;
4130 #endif
4131 free(state);
4132 }
4133
4134 /*
4135 * Vertex elements & buffers
4136 */
4137
4138 static void *si_create_vertex_elements(struct pipe_context *ctx,
4139 unsigned count,
4140 const struct pipe_vertex_element *elements)
4141 {
4142 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4143 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4144 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4145 int i;
4146
4147 assert(count <= SI_MAX_ATTRIBS);
4148 if (!v)
4149 return NULL;
4150
4151 v->count = count;
4152 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4153
4154 for (i = 0; i < count; ++i) {
4155 const struct util_format_description *desc;
4156 const struct util_format_channel_description *channel;
4157 unsigned data_format, num_format;
4158 int first_non_void;
4159 unsigned vbo_index = elements[i].vertex_buffer_index;
4160 unsigned char swizzle[4];
4161
4162 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4163 FREE(v);
4164 return NULL;
4165 }
4166
4167 if (elements[i].instance_divisor) {
4168 v->uses_instance_divisors = true;
4169 v->instance_divisors[i] = elements[i].instance_divisor;
4170
4171 if (v->instance_divisors[i] == 1)
4172 v->instance_divisor_is_one |= 1u << i;
4173 else
4174 v->instance_divisor_is_fetched |= 1u << i;
4175 }
4176
4177 if (!used[vbo_index]) {
4178 v->first_vb_use_mask |= 1 << i;
4179 used[vbo_index] = true;
4180 }
4181
4182 desc = util_format_description(elements[i].src_format);
4183 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4184 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4185 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4186 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4187 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4188
4189 v->format_size[i] = desc->block.bits / 8;
4190 v->src_offset[i] = elements[i].src_offset;
4191 v->vertex_buffer_index[i] = vbo_index;
4192
4193 /* The hardware always treats the 2-bit alpha channel as
4194 * unsigned, so a shader workaround is needed. The affected
4195 * chips are VI and older except Stoney (GFX8.1).
4196 */
4197 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4198 sscreen->b.chip_class <= VI &&
4199 sscreen->b.family != CHIP_STONEY) {
4200 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4201 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4202 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4203 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4204 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4205 /* This isn't actually used in OpenGL. */
4206 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4207 }
4208 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4209 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4210 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4211 else
4212 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4213 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4214 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4215 if (channel->normalized) {
4216 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4217 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4218 else
4219 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4220 } else {
4221 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4222 }
4223 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4224 if (channel->normalized) {
4225 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4226 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4227 else
4228 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4229 } else {
4230 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4231 }
4232 }
4233 } else if (channel && channel->size == 64 &&
4234 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4235 switch (desc->nr_channels) {
4236 case 1:
4237 case 2:
4238 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4239 swizzle[0] = PIPE_SWIZZLE_X;
4240 swizzle[1] = PIPE_SWIZZLE_Y;
4241 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4242 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4243 break;
4244 case 3:
4245 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4246 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4247 swizzle[1] = PIPE_SWIZZLE_Y;
4248 swizzle[2] = PIPE_SWIZZLE_0;
4249 swizzle[3] = PIPE_SWIZZLE_0;
4250 break;
4251 case 4:
4252 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4253 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4254 swizzle[1] = PIPE_SWIZZLE_Y;
4255 swizzle[2] = PIPE_SWIZZLE_Z;
4256 swizzle[3] = PIPE_SWIZZLE_W;
4257 break;
4258 default:
4259 assert(0);
4260 }
4261 } else if (channel && desc->nr_channels == 3) {
4262 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4263
4264 if (channel->size == 8) {
4265 if (channel->pure_integer)
4266 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4267 else
4268 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4269 } else if (channel->size == 16) {
4270 if (channel->pure_integer)
4271 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4272 else
4273 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4274 }
4275 }
4276
4277 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4278 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4279 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4280 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4281 S_008F0C_NUM_FORMAT(num_format) |
4282 S_008F0C_DATA_FORMAT(data_format);
4283 }
4284 return v;
4285 }
4286
4287 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4288 {
4289 struct si_context *sctx = (struct si_context *)ctx;
4290 struct si_vertex_elements *old = sctx->vertex_elements;
4291 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4292
4293 sctx->vertex_elements = v;
4294 sctx->vertex_buffers_dirty = true;
4295
4296 if (v &&
4297 (!old ||
4298 old->count != v->count ||
4299 old->uses_instance_divisors != v->uses_instance_divisors ||
4300 v->uses_instance_divisors || /* we don't check which divisors changed */
4301 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4302 sctx->do_update_shaders = true;
4303
4304 if (v && v->instance_divisor_is_fetched) {
4305 struct pipe_constant_buffer cb;
4306
4307 cb.buffer = NULL;
4308 cb.user_buffer = v->instance_divisors;
4309 cb.buffer_offset = 0;
4310 cb.buffer_size = sizeof(uint32_t) * v->count;
4311 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4312 }
4313 }
4314
4315 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4316 {
4317 struct si_context *sctx = (struct si_context *)ctx;
4318
4319 if (sctx->vertex_elements == state)
4320 sctx->vertex_elements = NULL;
4321 FREE(state);
4322 }
4323
4324 static void si_set_vertex_buffers(struct pipe_context *ctx,
4325 unsigned start_slot, unsigned count,
4326 const struct pipe_vertex_buffer *buffers)
4327 {
4328 struct si_context *sctx = (struct si_context *)ctx;
4329 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4330 int i;
4331
4332 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4333
4334 if (buffers) {
4335 for (i = 0; i < count; i++) {
4336 const struct pipe_vertex_buffer *src = buffers + i;
4337 struct pipe_vertex_buffer *dsti = dst + i;
4338 struct pipe_resource *buf = src->buffer.resource;
4339
4340 pipe_resource_reference(&dsti->buffer.resource, buf);
4341 dsti->buffer_offset = src->buffer_offset;
4342 dsti->stride = src->stride;
4343 r600_context_add_resource_size(ctx, buf);
4344 if (buf)
4345 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4346 }
4347 } else {
4348 for (i = 0; i < count; i++) {
4349 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4350 }
4351 }
4352 sctx->vertex_buffers_dirty = true;
4353 }
4354
4355 /*
4356 * Misc
4357 */
4358
4359 static void si_set_tess_state(struct pipe_context *ctx,
4360 const float default_outer_level[4],
4361 const float default_inner_level[2])
4362 {
4363 struct si_context *sctx = (struct si_context *)ctx;
4364 struct pipe_constant_buffer cb;
4365 float array[8];
4366
4367 memcpy(array, default_outer_level, sizeof(float) * 4);
4368 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4369
4370 cb.buffer = NULL;
4371 cb.user_buffer = NULL;
4372 cb.buffer_size = sizeof(array);
4373
4374 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4375 (void*)array, sizeof(array),
4376 &cb.buffer_offset);
4377
4378 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4379 pipe_resource_reference(&cb.buffer, NULL);
4380 }
4381
4382 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4383 {
4384 struct si_context *sctx = (struct si_context *)ctx;
4385
4386 si_update_fb_dirtiness_after_rendering(sctx);
4387
4388 /* Multisample surfaces are flushed in si_decompress_textures. */
4389 if (sctx->framebuffer.nr_samples <= 1 &&
4390 sctx->framebuffer.state.nr_cbufs)
4391 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4392 sctx->framebuffer.CB_has_shader_readable_metadata);
4393 }
4394
4395 /* This only ensures coherency for shader image/buffer stores. */
4396 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4397 {
4398 struct si_context *sctx = (struct si_context *)ctx;
4399
4400 /* Subsequent commands must wait for all shader invocations to
4401 * complete. */
4402 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4403 SI_CONTEXT_CS_PARTIAL_FLUSH;
4404
4405 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4406 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4407 SI_CONTEXT_INV_VMEM_L1;
4408
4409 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4410 PIPE_BARRIER_SHADER_BUFFER |
4411 PIPE_BARRIER_TEXTURE |
4412 PIPE_BARRIER_IMAGE |
4413 PIPE_BARRIER_STREAMOUT_BUFFER |
4414 PIPE_BARRIER_GLOBAL_BUFFER)) {
4415 /* As far as I can tell, L1 contents are written back to L2
4416 * automatically at end of shader, but the contents of other
4417 * L1 caches might still be stale. */
4418 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4419 }
4420
4421 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4422 /* Indices are read through TC L2 since VI.
4423 * L1 isn't used.
4424 */
4425 if (sctx->screen->b.chip_class <= CIK)
4426 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4427 }
4428
4429 /* MSAA color, any depth and any stencil are flushed in
4430 * si_decompress_textures when needed.
4431 */
4432 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4433 sctx->framebuffer.nr_samples <= 1 &&
4434 sctx->framebuffer.state.nr_cbufs) {
4435 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4436
4437 if (sctx->b.chip_class <= VI)
4438 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4439 }
4440
4441 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4442 if (sctx->screen->b.chip_class <= VI &&
4443 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4444 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4445 }
4446
4447 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4448 {
4449 struct pipe_blend_state blend;
4450
4451 memset(&blend, 0, sizeof(blend));
4452 blend.independent_blend_enable = true;
4453 blend.rt[0].colormask = 0xf;
4454 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4455 }
4456
4457 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4458 bool include_draw_vbo)
4459 {
4460 si_need_cs_space((struct si_context*)ctx);
4461 }
4462
4463 static void si_init_config(struct si_context *sctx);
4464
4465 void si_init_state_functions(struct si_context *sctx)
4466 {
4467 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4468 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4469 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4470 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4471 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4472
4473 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4474 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4475 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4476 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4477 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4478 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4479 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4480 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4481 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4482 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4483 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4484
4485 sctx->b.b.create_blend_state = si_create_blend_state;
4486 sctx->b.b.bind_blend_state = si_bind_blend_state;
4487 sctx->b.b.delete_blend_state = si_delete_blend_state;
4488 sctx->b.b.set_blend_color = si_set_blend_color;
4489
4490 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4491 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4492 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4493
4494 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4495 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4496 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4497
4498 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4499 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4500 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4501 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4502 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4503
4504 sctx->b.b.set_clip_state = si_set_clip_state;
4505 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4506
4507 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4508
4509 sctx->b.b.create_sampler_state = si_create_sampler_state;
4510 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4511
4512 sctx->b.b.create_sampler_view = si_create_sampler_view;
4513 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4514
4515 sctx->b.b.set_sample_mask = si_set_sample_mask;
4516
4517 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4518 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4519 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4520 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4521
4522 sctx->b.b.texture_barrier = si_texture_barrier;
4523 sctx->b.b.memory_barrier = si_memory_barrier;
4524 sctx->b.b.set_min_samples = si_set_min_samples;
4525 sctx->b.b.set_tess_state = si_set_tess_state;
4526
4527 sctx->b.b.set_active_query_state = si_set_active_query_state;
4528 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4529 sctx->b.save_qbo_state = si_save_qbo_state;
4530 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4531
4532 sctx->b.b.draw_vbo = si_draw_vbo;
4533
4534 si_init_config(sctx);
4535 }
4536
4537 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4538 {
4539 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4540 }
4541
4542 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4543 struct r600_texture *rtex,
4544 struct radeon_bo_metadata *md)
4545 {
4546 struct si_screen *sscreen = (struct si_screen*)rscreen;
4547 struct pipe_resource *res = &rtex->resource.b.b;
4548 static const unsigned char swizzle[] = {
4549 PIPE_SWIZZLE_X,
4550 PIPE_SWIZZLE_Y,
4551 PIPE_SWIZZLE_Z,
4552 PIPE_SWIZZLE_W
4553 };
4554 uint32_t desc[8], i;
4555 bool is_array = util_resource_is_array_texture(res);
4556
4557 /* DRM 2.x.x doesn't support this. */
4558 if (rscreen->info.drm_major != 3)
4559 return;
4560
4561 assert(rtex->dcc_separate_buffer == NULL);
4562 assert(rtex->fmask.size == 0);
4563
4564 /* Metadata image format format version 1:
4565 * [0] = 1 (metadata format identifier)
4566 * [1] = (VENDOR_ID << 16) | PCI_ID
4567 * [2:9] = image descriptor for the whole resource
4568 * [2] is always 0, because the base address is cleared
4569 * [9] is the DCC offset bits [39:8] from the beginning of
4570 * the buffer
4571 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4572 */
4573
4574 md->metadata[0] = 1; /* metadata image format version 1 */
4575
4576 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4577 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4578
4579 si_make_texture_descriptor(sscreen, rtex, true,
4580 res->target, res->format,
4581 swizzle, 0, res->last_level, 0,
4582 is_array ? res->array_size - 1 : 0,
4583 res->width0, res->height0, res->depth0,
4584 desc, NULL);
4585
4586 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4587 0, 0, rtex->surface.blk_w, false, desc);
4588
4589 /* Clear the base address and set the relative DCC offset. */
4590 desc[0] = 0;
4591 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4592 desc[7] = rtex->dcc_offset >> 8;
4593
4594 /* Dwords [2:9] contain the image descriptor. */
4595 memcpy(&md->metadata[2], desc, sizeof(desc));
4596 md->size_metadata = 10 * 4;
4597
4598 /* Dwords [10:..] contain the mipmap level offsets. */
4599 if (rscreen->chip_class <= VI) {
4600 for (i = 0; i <= res->last_level; i++)
4601 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4602
4603 md->size_metadata += (1 + res->last_level) * 4;
4604 }
4605 }
4606
4607 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4608 struct r600_texture *rtex,
4609 struct radeon_bo_metadata *md)
4610 {
4611 uint32_t *desc = &md->metadata[2];
4612
4613 if (rscreen->chip_class < VI)
4614 return;
4615
4616 /* Return if DCC is enabled. The texture should be set up with it
4617 * already.
4618 */
4619 if (md->size_metadata >= 11 * 4 &&
4620 md->metadata[0] != 0 &&
4621 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4622 G_008F28_COMPRESSION_EN(desc[6])) {
4623 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4624 return;
4625 }
4626
4627 /* Disable DCC. These are always set by texture_from_handle and must
4628 * be cleared here.
4629 */
4630 rtex->dcc_offset = 0;
4631 }
4632
4633 void si_init_screen_state_functions(struct si_screen *sscreen)
4634 {
4635 sscreen->b.b.is_format_supported = si_is_format_supported;
4636 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4637 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4638 }
4639
4640 static void si_set_grbm_gfx_index(struct si_context *sctx,
4641 struct si_pm4_state *pm4, unsigned value)
4642 {
4643 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4644 GRBM_GFX_INDEX;
4645 si_pm4_set_reg(pm4, reg, value);
4646 }
4647
4648 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4649 struct si_pm4_state *pm4, unsigned se)
4650 {
4651 assert(se == ~0 || se < sctx->screen->b.info.max_se);
4652 si_set_grbm_gfx_index(sctx, pm4,
4653 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4654 S_030800_SE_INDEX(se)) |
4655 S_030800_SH_BROADCAST_WRITES(1) |
4656 S_030800_INSTANCE_BROADCAST_WRITES(1));
4657 }
4658
4659 static void
4660 si_write_harvested_raster_configs(struct si_context *sctx,
4661 struct si_pm4_state *pm4,
4662 unsigned raster_config,
4663 unsigned raster_config_1)
4664 {
4665 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4666 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4667 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4668 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4669 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4670 unsigned rb_per_se = num_rb / num_se;
4671 unsigned se_mask[4];
4672 unsigned se;
4673
4674 se_mask[0] = ((1 << rb_per_se) - 1);
4675 se_mask[1] = (se_mask[0] << rb_per_se);
4676 se_mask[2] = (se_mask[1] << rb_per_se);
4677 se_mask[3] = (se_mask[2] << rb_per_se);
4678
4679 se_mask[0] &= rb_mask;
4680 se_mask[1] &= rb_mask;
4681 se_mask[2] &= rb_mask;
4682 se_mask[3] &= rb_mask;
4683
4684 assert(num_se == 1 || num_se == 2 || num_se == 4);
4685 assert(sh_per_se == 1 || sh_per_se == 2);
4686 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4687
4688 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4689 * fields are for, so I'm leaving them as their default
4690 * values. */
4691
4692 for (se = 0; se < num_se; se++) {
4693 unsigned raster_config_se = raster_config;
4694 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4695 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4696 int idx = (se / 2) * 2;
4697
4698 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4699 raster_config_se &= C_028350_SE_MAP;
4700
4701 if (!se_mask[idx]) {
4702 raster_config_se |=
4703 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4704 } else {
4705 raster_config_se |=
4706 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4707 }
4708 }
4709
4710 pkr0_mask &= rb_mask;
4711 pkr1_mask &= rb_mask;
4712 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4713 raster_config_se &= C_028350_PKR_MAP;
4714
4715 if (!pkr0_mask) {
4716 raster_config_se |=
4717 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4718 } else {
4719 raster_config_se |=
4720 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4721 }
4722 }
4723
4724 if (rb_per_se >= 2) {
4725 unsigned rb0_mask = 1 << (se * rb_per_se);
4726 unsigned rb1_mask = rb0_mask << 1;
4727
4728 rb0_mask &= rb_mask;
4729 rb1_mask &= rb_mask;
4730 if (!rb0_mask || !rb1_mask) {
4731 raster_config_se &= C_028350_RB_MAP_PKR0;
4732
4733 if (!rb0_mask) {
4734 raster_config_se |=
4735 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4736 } else {
4737 raster_config_se |=
4738 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4739 }
4740 }
4741
4742 if (rb_per_se > 2) {
4743 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4744 rb1_mask = rb0_mask << 1;
4745 rb0_mask &= rb_mask;
4746 rb1_mask &= rb_mask;
4747 if (!rb0_mask || !rb1_mask) {
4748 raster_config_se &= C_028350_RB_MAP_PKR1;
4749
4750 if (!rb0_mask) {
4751 raster_config_se |=
4752 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4753 } else {
4754 raster_config_se |=
4755 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4756 }
4757 }
4758 }
4759 }
4760
4761 si_set_grbm_gfx_index_se(sctx, pm4, se);
4762 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4763 }
4764 si_set_grbm_gfx_index(sctx, pm4, ~0);
4765
4766 if (sctx->b.chip_class >= CIK) {
4767 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4768 (!se_mask[2] && !se_mask[3]))) {
4769 raster_config_1 &= C_028354_SE_PAIR_MAP;
4770
4771 if (!se_mask[0] && !se_mask[1]) {
4772 raster_config_1 |=
4773 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4774 } else {
4775 raster_config_1 |=
4776 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4777 }
4778 }
4779
4780 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4781 }
4782 }
4783
4784 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4785 {
4786 struct si_screen *sscreen = sctx->screen;
4787 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4788 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4789 unsigned raster_config, raster_config_1;
4790
4791 switch (sctx->b.family) {
4792 case CHIP_TAHITI:
4793 case CHIP_PITCAIRN:
4794 raster_config = 0x2a00126a;
4795 raster_config_1 = 0x00000000;
4796 break;
4797 case CHIP_VERDE:
4798 raster_config = 0x0000124a;
4799 raster_config_1 = 0x00000000;
4800 break;
4801 case CHIP_OLAND:
4802 raster_config = 0x00000082;
4803 raster_config_1 = 0x00000000;
4804 break;
4805 case CHIP_HAINAN:
4806 raster_config = 0x00000000;
4807 raster_config_1 = 0x00000000;
4808 break;
4809 case CHIP_BONAIRE:
4810 raster_config = 0x16000012;
4811 raster_config_1 = 0x00000000;
4812 break;
4813 case CHIP_HAWAII:
4814 raster_config = 0x3a00161a;
4815 raster_config_1 = 0x0000002e;
4816 break;
4817 case CHIP_FIJI:
4818 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4819 /* old kernels with old tiling config */
4820 raster_config = 0x16000012;
4821 raster_config_1 = 0x0000002a;
4822 } else {
4823 raster_config = 0x3a00161a;
4824 raster_config_1 = 0x0000002e;
4825 }
4826 break;
4827 case CHIP_POLARIS10:
4828 raster_config = 0x16000012;
4829 raster_config_1 = 0x0000002a;
4830 break;
4831 case CHIP_POLARIS11:
4832 case CHIP_POLARIS12:
4833 raster_config = 0x16000012;
4834 raster_config_1 = 0x00000000;
4835 break;
4836 case CHIP_TONGA:
4837 raster_config = 0x16000012;
4838 raster_config_1 = 0x0000002a;
4839 break;
4840 case CHIP_ICELAND:
4841 if (num_rb == 1)
4842 raster_config = 0x00000000;
4843 else
4844 raster_config = 0x00000002;
4845 raster_config_1 = 0x00000000;
4846 break;
4847 case CHIP_CARRIZO:
4848 raster_config = 0x00000002;
4849 raster_config_1 = 0x00000000;
4850 break;
4851 case CHIP_KAVERI:
4852 /* KV should be 0x00000002, but that causes problems with radeon */
4853 raster_config = 0x00000000; /* 0x00000002 */
4854 raster_config_1 = 0x00000000;
4855 break;
4856 case CHIP_KABINI:
4857 case CHIP_MULLINS:
4858 case CHIP_STONEY:
4859 raster_config = 0x00000000;
4860 raster_config_1 = 0x00000000;
4861 break;
4862 default:
4863 fprintf(stderr,
4864 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4865 raster_config = 0x00000000;
4866 raster_config_1 = 0x00000000;
4867 }
4868
4869 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4870 /* Always use the default config when all backends are enabled
4871 * (or when we failed to determine the enabled backends).
4872 */
4873 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4874 raster_config);
4875 if (sctx->b.chip_class >= CIK)
4876 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4877 raster_config_1);
4878 } else {
4879 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4880 }
4881 }
4882
4883 static void si_init_config(struct si_context *sctx)
4884 {
4885 struct si_screen *sscreen = sctx->screen;
4886 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4887 bool has_clear_state = sscreen->has_clear_state;
4888 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4889
4890 /* Only SI can disable CLEAR_STATE for now. */
4891 assert(has_clear_state || sscreen->b.chip_class == SI);
4892
4893 if (!pm4)
4894 return;
4895
4896 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4897 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4898 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4899 si_pm4_cmd_end(pm4, false);
4900
4901 if (has_clear_state) {
4902 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4903 si_pm4_cmd_add(pm4, 0);
4904 si_pm4_cmd_end(pm4, false);
4905 }
4906
4907 if (sctx->b.chip_class <= VI)
4908 si_set_raster_config(sctx, pm4);
4909
4910 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4911 if (!has_clear_state)
4912 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4913
4914 /* FIXME calculate these values somehow ??? */
4915 if (sctx->b.chip_class <= VI) {
4916 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4917 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4918 }
4919
4920 if (!has_clear_state) {
4921 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4922 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4923 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4924 }
4925
4926 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4927 if (!has_clear_state)
4928 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4929 if (sctx->b.chip_class < CIK)
4930 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4931 S_008A14_CLIP_VTX_REORDER_ENA(1));
4932
4933 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4934 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4935
4936 if (!has_clear_state)
4937 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4938
4939 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4940 * I don't know why. Deduced by trial and error.
4941 */
4942 if (sctx->b.chip_class <= CIK) {
4943 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4944 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4945 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4946 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4947 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4948 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4949 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4950 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4951 }
4952
4953 if (!has_clear_state) {
4954 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4955 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4956 S_028230_ER_TRI(0xA) |
4957 S_028230_ER_POINT(0xA) |
4958 S_028230_ER_RECT(0xA) |
4959 /* Required by DX10_DIAMOND_TEST_ENA: */
4960 S_028230_ER_LINE_LR(0x1A) |
4961 S_028230_ER_LINE_RL(0x26) |
4962 S_028230_ER_LINE_TB(0xA) |
4963 S_028230_ER_LINE_BT(0xA));
4964 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4965 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4966 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4967 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4968 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4969 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4970 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4971 }
4972
4973 if (sctx->b.chip_class >= GFX9) {
4974 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4975 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4976 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4977 } else {
4978 /* These registers, when written, also overwrite the CLEAR_STATE
4979 * context, so we can't rely on CLEAR_STATE setting them.
4980 * It would be an issue if there was another UMD changing them.
4981 */
4982 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4983 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4984 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4985 }
4986
4987 if (sctx->b.chip_class >= CIK) {
4988 if (sctx->b.chip_class >= GFX9) {
4989 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4990 } else {
4991 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4992 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4993 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4994
4995 /* If this is 0, Bonaire can hang even if GS isn't being used.
4996 * Other chips are unaffected. These are suboptimal values,
4997 * but we don't use on-chip GS.
4998 */
4999 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5000 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5001 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5002 }
5003 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
5004
5005 /* Compute LATE_ALLOC_VS.LIMIT. */
5006 unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
5007 (sscreen->b.info.max_se *
5008 sscreen->b.info.max_sh_per_se);
5009 unsigned late_alloc_limit; /* The limit is per SH. */
5010
5011 if (sctx->b.family == CHIP_KABINI) {
5012 late_alloc_limit = 0; /* Potential hang on Kabini. */
5013 } else if (num_cu_per_sh <= 4) {
5014 /* Too few available compute units per SH. Disallowing
5015 * VS to run on one CU could hurt us more than late VS
5016 * allocation would help.
5017 *
5018 * 2 is the highest safe number that allows us to keep
5019 * all CUs enabled.
5020 */
5021 late_alloc_limit = 2;
5022 } else {
5023 /* This is a good initial value, allowing 1 late_alloc
5024 * wave per SIMD on num_cu - 2.
5025 */
5026 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5027
5028 /* The limit is 0-based, so 0 means 1. */
5029 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5030 late_alloc_limit -= 1;
5031 }
5032
5033 /* VS can't execute on one CU if the limit is > 2. */
5034 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5035 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff));
5036 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5037 S_00B11C_LIMIT(late_alloc_limit));
5038 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
5039 }
5040
5041 if (sctx->b.chip_class >= VI) {
5042 unsigned vgt_tess_distribution;
5043
5044 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
5045 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
5046 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
5047
5048 vgt_tess_distribution =
5049 S_028B50_ACCUM_ISOLINE(32) |
5050 S_028B50_ACCUM_TRI(11) |
5051 S_028B50_ACCUM_QUAD(11) |
5052 S_028B50_DONUT_SPLIT(16);
5053
5054 /* Testing with Unigine Heaven extreme tesselation yielded best results
5055 * with TRAP_SPLIT = 3.
5056 */
5057 if (sctx->b.family == CHIP_FIJI ||
5058 sctx->b.family >= CHIP_POLARIS10)
5059 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5060
5061 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5062 } else if (!has_clear_state) {
5063 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5064 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5065 }
5066
5067 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5068 if (sctx->b.chip_class >= CIK)
5069 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
5070 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5071 RADEON_PRIO_BORDER_COLORS);
5072
5073 if (sctx->b.chip_class >= GFX9) {
5074 unsigned num_se = sscreen->b.info.max_se;
5075 unsigned pc_lines = 0;
5076
5077 switch (sctx->b.family) {
5078 case CHIP_VEGA10:
5079 pc_lines = 4096;
5080 break;
5081 case CHIP_RAVEN:
5082 pc_lines = 1024;
5083 break;
5084 default:
5085 assert(0);
5086 }
5087
5088 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5089 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5090 S_028C48_MAX_PRIM_PER_BATCH(1023));
5091 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5092 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5093 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5094 }
5095
5096 si_pm4_upload_indirect_buffer(sctx, pm4);
5097 sctx->init_config = pm4;
5098 }