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radeonsi/gfx10: generate gfx10_format_table.h
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 struct gfx10_format {
38 unsigned img_format:9;
39
40 /* Various formats are only supported with workarounds for vertex fetch,
41 * and some 32_32_32 formats are supported natively, but only for buffers
42 * (possibly with some image support, actually, but no filtering). */
43 bool buffers_only:1;
44 };
45
46 #include "gfx10_format_table.h"
47
48 static unsigned si_map_swizzle(unsigned swizzle)
49 {
50 switch (swizzle) {
51 case PIPE_SWIZZLE_Y:
52 return V_008F0C_SQ_SEL_Y;
53 case PIPE_SWIZZLE_Z:
54 return V_008F0C_SQ_SEL_Z;
55 case PIPE_SWIZZLE_W:
56 return V_008F0C_SQ_SEL_W;
57 case PIPE_SWIZZLE_0:
58 return V_008F0C_SQ_SEL_0;
59 case PIPE_SWIZZLE_1:
60 return V_008F0C_SQ_SEL_1;
61 default: /* PIPE_SWIZZLE_X */
62 return V_008F0C_SQ_SEL_X;
63 }
64 }
65
66 /* 12.4 fixed-point */
67 static unsigned si_pack_float_12p4(float x)
68 {
69 return x <= 0 ? 0 :
70 x >= 4096 ? 0xffff : x * 16;
71 }
72
73 /*
74 * Inferred framebuffer and blender state.
75 *
76 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
77 * if there is not enough PS outputs.
78 */
79 static void si_emit_cb_render_state(struct si_context *sctx)
80 {
81 struct radeon_cmdbuf *cs = sctx->gfx_cs;
82 struct si_state_blend *blend = sctx->queued.named.blend;
83 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
84 * but you never know. */
85 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
86 unsigned i;
87
88 if (blend)
89 cb_target_mask &= blend->cb_target_mask;
90
91 /* Avoid a hang that happens when dual source blending is enabled
92 * but there is not enough color outputs. This is undefined behavior,
93 * so disable color writes completely.
94 *
95 * Reproducible with Unigine Heaven 4.0 and drirc missing.
96 */
97 if (blend && blend->dual_src_blend &&
98 sctx->ps_shader.cso &&
99 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
100 cb_target_mask = 0;
101
102 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
103 * I think we don't have to do anything between IBs.
104 */
105 if (sctx->screen->dfsm_allowed &&
106 sctx->last_cb_target_mask != cb_target_mask) {
107 sctx->last_cb_target_mask = cb_target_mask;
108
109 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
110 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
111 }
112
113 unsigned initial_cdw = cs->current.cdw;
114 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
115 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
116
117 if (sctx->chip_class >= GFX8) {
118 /* DCC MSAA workaround for blending.
119 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
120 * COMBINER_DISABLE, but that would be more complicated.
121 */
122 bool oc_disable = (sctx->chip_class == GFX8 ||
123 sctx->chip_class == GFX9) &&
124 blend &&
125 blend->blend_enable_4bit & cb_target_mask &&
126 sctx->framebuffer.nr_samples >= 2;
127 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
128
129 radeon_opt_set_context_reg(
130 sctx, R_028424_CB_DCC_CONTROL,
131 SI_TRACKED_CB_DCC_CONTROL,
132 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
133 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
134 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
135 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
136 }
137
138 /* RB+ register settings. */
139 if (sctx->screen->rbplus_allowed) {
140 unsigned spi_shader_col_format =
141 sctx->ps_shader.cso ?
142 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
143 unsigned sx_ps_downconvert = 0;
144 unsigned sx_blend_opt_epsilon = 0;
145 unsigned sx_blend_opt_control = 0;
146
147 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
148 struct si_surface *surf =
149 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
150 unsigned format, swap, spi_format, colormask;
151 bool has_alpha, has_rgb;
152
153 if (!surf)
154 continue;
155
156 format = G_028C70_FORMAT(surf->cb_color_info);
157 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
158 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
159 colormask = (cb_target_mask >> (i * 4)) & 0xf;
160
161 /* Set if RGB and A are present. */
162 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
163
164 if (format == V_028C70_COLOR_8 ||
165 format == V_028C70_COLOR_16 ||
166 format == V_028C70_COLOR_32)
167 has_rgb = !has_alpha;
168 else
169 has_rgb = true;
170
171 /* Check the colormask and export format. */
172 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
173 has_rgb = false;
174 if (!(colormask & PIPE_MASK_A))
175 has_alpha = false;
176
177 if (spi_format == V_028714_SPI_SHADER_ZERO) {
178 has_rgb = false;
179 has_alpha = false;
180 }
181
182 /* Disable value checking for disabled channels. */
183 if (!has_rgb)
184 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
185 if (!has_alpha)
186 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
187
188 /* Enable down-conversion for 32bpp and smaller formats. */
189 switch (format) {
190 case V_028C70_COLOR_8:
191 case V_028C70_COLOR_8_8:
192 case V_028C70_COLOR_8_8_8_8:
193 /* For 1 and 2-channel formats, use the superset thereof. */
194 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
195 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
196 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_5_6_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_1_5_5_5:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_4_4_4_4:
217 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
219 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
220 }
221 break;
222
223 case V_028C70_COLOR_32:
224 if (swap == V_028C70_SWAP_STD &&
225 spi_format == V_028714_SPI_SHADER_32_R)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
227 else if (swap == V_028C70_SWAP_ALT_REV &&
228 spi_format == V_028714_SPI_SHADER_32_AR)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
230 break;
231
232 case V_028C70_COLOR_16:
233 case V_028C70_COLOR_16_16:
234 /* For 1-channel formats, use the superset thereof. */
235 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
236 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
237 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
239 if (swap == V_028C70_SWAP_STD ||
240 swap == V_028C70_SWAP_STD_REV)
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
242 else
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_10_11_11:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
251 }
252 break;
253
254 case V_028C70_COLOR_2_10_10_10:
255 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
256 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
257 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
258 }
259 break;
260 }
261 }
262
263 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
264 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
265 SI_TRACKED_SX_PS_DOWNCONVERT,
266 sx_ps_downconvert, sx_blend_opt_epsilon,
267 sx_blend_opt_control);
268 }
269 if (initial_cdw != cs->current.cdw)
270 sctx->context_roll = true;
271 }
272
273 /*
274 * Blender functions
275 */
276
277 static uint32_t si_translate_blend_function(int blend_func)
278 {
279 switch (blend_func) {
280 case PIPE_BLEND_ADD:
281 return V_028780_COMB_DST_PLUS_SRC;
282 case PIPE_BLEND_SUBTRACT:
283 return V_028780_COMB_SRC_MINUS_DST;
284 case PIPE_BLEND_REVERSE_SUBTRACT:
285 return V_028780_COMB_DST_MINUS_SRC;
286 case PIPE_BLEND_MIN:
287 return V_028780_COMB_MIN_DST_SRC;
288 case PIPE_BLEND_MAX:
289 return V_028780_COMB_MAX_DST_SRC;
290 default:
291 PRINT_ERR("Unknown blend function %d\n", blend_func);
292 assert(0);
293 break;
294 }
295 return 0;
296 }
297
298 static uint32_t si_translate_blend_factor(int blend_fact)
299 {
300 switch (blend_fact) {
301 case PIPE_BLENDFACTOR_ONE:
302 return V_028780_BLEND_ONE;
303 case PIPE_BLENDFACTOR_SRC_COLOR:
304 return V_028780_BLEND_SRC_COLOR;
305 case PIPE_BLENDFACTOR_SRC_ALPHA:
306 return V_028780_BLEND_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_DST_ALPHA:
308 return V_028780_BLEND_DST_ALPHA;
309 case PIPE_BLENDFACTOR_DST_COLOR:
310 return V_028780_BLEND_DST_COLOR;
311 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
312 return V_028780_BLEND_SRC_ALPHA_SATURATE;
313 case PIPE_BLENDFACTOR_CONST_COLOR:
314 return V_028780_BLEND_CONSTANT_COLOR;
315 case PIPE_BLENDFACTOR_CONST_ALPHA:
316 return V_028780_BLEND_CONSTANT_ALPHA;
317 case PIPE_BLENDFACTOR_ZERO:
318 return V_028780_BLEND_ZERO;
319 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
320 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
322 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
323 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
324 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
325 case PIPE_BLENDFACTOR_INV_DST_COLOR:
326 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
327 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
328 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
329 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
331 case PIPE_BLENDFACTOR_SRC1_COLOR:
332 return V_028780_BLEND_SRC1_COLOR;
333 case PIPE_BLENDFACTOR_SRC1_ALPHA:
334 return V_028780_BLEND_SRC1_ALPHA;
335 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
336 return V_028780_BLEND_INV_SRC1_COLOR;
337 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
338 return V_028780_BLEND_INV_SRC1_ALPHA;
339 default:
340 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
341 assert(0);
342 break;
343 }
344 return 0;
345 }
346
347 static uint32_t si_translate_blend_opt_function(int blend_func)
348 {
349 switch (blend_func) {
350 case PIPE_BLEND_ADD:
351 return V_028760_OPT_COMB_ADD;
352 case PIPE_BLEND_SUBTRACT:
353 return V_028760_OPT_COMB_SUBTRACT;
354 case PIPE_BLEND_REVERSE_SUBTRACT:
355 return V_028760_OPT_COMB_REVSUBTRACT;
356 case PIPE_BLEND_MIN:
357 return V_028760_OPT_COMB_MIN;
358 case PIPE_BLEND_MAX:
359 return V_028760_OPT_COMB_MAX;
360 default:
361 return V_028760_OPT_COMB_BLEND_DISABLED;
362 }
363 }
364
365 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
366 {
367 switch (blend_fact) {
368 case PIPE_BLENDFACTOR_ZERO:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
370 case PIPE_BLENDFACTOR_ONE:
371 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
372 case PIPE_BLENDFACTOR_SRC_COLOR:
373 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
374 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
375 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
376 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
377 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
378 case PIPE_BLENDFACTOR_SRC_ALPHA:
379 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
380 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
381 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
382 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
383 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
384 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
385 default:
386 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
387 }
388 }
389
390 static void si_blend_check_commutativity(struct si_screen *sscreen,
391 struct si_state_blend *blend,
392 enum pipe_blend_func func,
393 enum pipe_blendfactor src,
394 enum pipe_blendfactor dst,
395 unsigned chanmask)
396 {
397 /* Src factor is allowed when it does not depend on Dst */
398 static const uint32_t src_allowed =
399 (1u << PIPE_BLENDFACTOR_ONE) |
400 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
401 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
402 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
403 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
404 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
405 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
406 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
407 (1u << PIPE_BLENDFACTOR_ZERO) |
408 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
409 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
410 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
411 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
414
415 if (dst == PIPE_BLENDFACTOR_ONE &&
416 (src_allowed & (1u << src))) {
417 /* Addition is commutative, but floating point addition isn't
418 * associative: subtle changes can be introduced via different
419 * rounding.
420 *
421 * Out-of-order is also non-deterministic, which means that
422 * this breaks OpenGL invariance requirements. So only enable
423 * out-of-order additive blending if explicitly allowed by a
424 * setting.
425 */
426 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
427 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
428 blend->commutative_4bit |= chanmask;
429 }
430 }
431
432 /**
433 * Get rid of DST in the blend factors by commuting the operands:
434 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
435 */
436 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
437 unsigned *dst_factor, unsigned expected_dst,
438 unsigned replacement_src)
439 {
440 if (*src_factor == expected_dst &&
441 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
442 *src_factor = PIPE_BLENDFACTOR_ZERO;
443 *dst_factor = replacement_src;
444
445 /* Commuting the operands requires reversing subtractions. */
446 if (*func == PIPE_BLEND_SUBTRACT)
447 *func = PIPE_BLEND_REVERSE_SUBTRACT;
448 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
449 *func = PIPE_BLEND_SUBTRACT;
450 }
451 }
452
453 static bool si_blend_factor_uses_dst(unsigned factor)
454 {
455 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
456 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
457 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
458 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
459 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
460 }
461
462 static void *si_create_blend_state_mode(struct pipe_context *ctx,
463 const struct pipe_blend_state *state,
464 unsigned mode)
465 {
466 struct si_context *sctx = (struct si_context*)ctx;
467 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
468 struct si_pm4_state *pm4 = &blend->pm4;
469 uint32_t sx_mrt_blend_opt[8] = {0};
470 uint32_t color_control = 0;
471
472 if (!blend)
473 return NULL;
474
475 blend->alpha_to_coverage = state->alpha_to_coverage;
476 blend->alpha_to_one = state->alpha_to_one;
477 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
478 blend->logicop_enable = state->logicop_enable;
479
480 if (state->logicop_enable) {
481 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
482 } else {
483 color_control |= S_028808_ROP3(0xcc);
484 }
485
486 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
487 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
488 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
489 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
490 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
491 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
492 S_028B70_OFFSET_ROUND(1));
493
494 if (state->alpha_to_coverage)
495 blend->need_src_alpha_4bit |= 0xf;
496
497 blend->cb_target_mask = 0;
498 blend->cb_target_enabled_4bit = 0;
499
500 for (int i = 0; i < 8; i++) {
501 /* state->rt entries > 0 only written if independent blending */
502 const int j = state->independent_blend_enable ? i : 0;
503
504 unsigned eqRGB = state->rt[j].rgb_func;
505 unsigned srcRGB = state->rt[j].rgb_src_factor;
506 unsigned dstRGB = state->rt[j].rgb_dst_factor;
507 unsigned eqA = state->rt[j].alpha_func;
508 unsigned srcA = state->rt[j].alpha_src_factor;
509 unsigned dstA = state->rt[j].alpha_dst_factor;
510
511 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
512 unsigned blend_cntl = 0;
513
514 sx_mrt_blend_opt[i] =
515 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
516 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
517
518 /* Only set dual source blending for MRT0 to avoid a hang. */
519 if (i >= 1 && blend->dual_src_blend) {
520 /* Vulkan does this for dual source blending. */
521 if (i == 1)
522 blend_cntl |= S_028780_ENABLE(1);
523
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* Only addition and subtraction equations are supported with
529 * dual source blending.
530 */
531 if (blend->dual_src_blend &&
532 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
533 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
534 assert(!"Unsupported equation for dual source blending");
535 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
536 continue;
537 }
538
539 /* cb_render_state will disable unused ones */
540 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
541 if (state->rt[j].colormask)
542 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
543
544 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
545 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
546 continue;
547 }
548
549 si_blend_check_commutativity(sctx->screen, blend,
550 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
551 si_blend_check_commutativity(sctx->screen, blend,
552 eqA, srcA, dstA, 0x8 << (4 * i));
553
554 /* Blending optimizations for RB+.
555 * These transformations don't change the behavior.
556 *
557 * First, get rid of DST in the blend factors:
558 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
559 */
560 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
561 PIPE_BLENDFACTOR_DST_COLOR,
562 PIPE_BLENDFACTOR_SRC_COLOR);
563 si_blend_remove_dst(&eqA, &srcA, &dstA,
564 PIPE_BLENDFACTOR_DST_COLOR,
565 PIPE_BLENDFACTOR_SRC_COLOR);
566 si_blend_remove_dst(&eqA, &srcA, &dstA,
567 PIPE_BLENDFACTOR_DST_ALPHA,
568 PIPE_BLENDFACTOR_SRC_ALPHA);
569
570 /* Look up the ideal settings from tables. */
571 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
572 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
573 srcA_opt = si_translate_blend_opt_factor(srcA, true);
574 dstA_opt = si_translate_blend_opt_factor(dstA, true);
575
576 /* Handle interdependencies. */
577 if (si_blend_factor_uses_dst(srcRGB))
578 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
579 if (si_blend_factor_uses_dst(srcA))
580 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
581
582 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
583 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
584 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
585 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
586 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
587
588 /* Set the final value. */
589 sx_mrt_blend_opt[i] =
590 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
591 S_028760_COLOR_DST_OPT(dstRGB_opt) |
592 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
593 S_028760_ALPHA_SRC_OPT(srcA_opt) |
594 S_028760_ALPHA_DST_OPT(dstA_opt) |
595 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
596
597 /* Set blend state. */
598 blend_cntl |= S_028780_ENABLE(1);
599 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
600 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
601 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
602
603 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
604 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
605 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
606 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
607 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
608 }
609 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
610
611 blend->blend_enable_4bit |= 0xfu << (i * 4);
612
613 /* This is only important for formats without alpha. */
614 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
615 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
616 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
617 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
618 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
619 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
620 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
621 }
622
623 if (blend->cb_target_mask) {
624 color_control |= S_028808_MODE(mode);
625 } else {
626 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
627 }
628
629 if (sctx->screen->rbplus_allowed) {
630 /* Disable RB+ blend optimizations for dual source blending.
631 * Vulkan does this.
632 */
633 if (blend->dual_src_blend) {
634 for (int i = 0; i < 8; i++) {
635 sx_mrt_blend_opt[i] =
636 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
637 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
638 }
639 }
640
641 for (int i = 0; i < 8; i++)
642 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
643 sx_mrt_blend_opt[i]);
644
645 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
646 if (blend->dual_src_blend || state->logicop_enable ||
647 mode == V_028808_CB_RESOLVE)
648 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
649 }
650
651 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
652 return blend;
653 }
654
655 static void *si_create_blend_state(struct pipe_context *ctx,
656 const struct pipe_blend_state *state)
657 {
658 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
659 }
660
661 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
662 {
663 struct si_context *sctx = (struct si_context *)ctx;
664 struct si_state_blend *old_blend = sctx->queued.named.blend;
665 struct si_state_blend *blend = (struct si_state_blend *)state;
666
667 if (!state)
668 return;
669
670 si_pm4_bind_state(sctx, blend, state);
671
672 if (!old_blend ||
673 old_blend->cb_target_mask != blend->cb_target_mask ||
674 old_blend->dual_src_blend != blend->dual_src_blend ||
675 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
676 sctx->framebuffer.nr_samples >= 2 &&
677 sctx->screen->dcc_msaa_allowed))
678 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
679
680 if (!old_blend ||
681 old_blend->cb_target_mask != blend->cb_target_mask ||
682 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
683 old_blend->alpha_to_one != blend->alpha_to_one ||
684 old_blend->dual_src_blend != blend->dual_src_blend ||
685 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
686 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
687 sctx->do_update_shaders = true;
688
689 if (sctx->screen->dpbb_allowed &&
690 (!old_blend ||
691 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
692 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
693 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
694 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
695
696 if (sctx->screen->has_out_of_order_rast &&
697 (!old_blend ||
698 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
699 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
700 old_blend->commutative_4bit != blend->commutative_4bit ||
701 old_blend->logicop_enable != blend->logicop_enable)))
702 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
703 }
704
705 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
706 {
707 struct si_context *sctx = (struct si_context *)ctx;
708 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
709 }
710
711 static void si_set_blend_color(struct pipe_context *ctx,
712 const struct pipe_blend_color *state)
713 {
714 struct si_context *sctx = (struct si_context *)ctx;
715 static const struct pipe_blend_color zeros;
716
717 sctx->blend_color.state = *state;
718 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
719 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
720 }
721
722 static void si_emit_blend_color(struct si_context *sctx)
723 {
724 struct radeon_cmdbuf *cs = sctx->gfx_cs;
725
726 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
727 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
728 }
729
730 /*
731 * Clipping
732 */
733
734 static void si_set_clip_state(struct pipe_context *ctx,
735 const struct pipe_clip_state *state)
736 {
737 struct si_context *sctx = (struct si_context *)ctx;
738 struct pipe_constant_buffer cb;
739 static const struct pipe_clip_state zeros;
740
741 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
742 return;
743
744 sctx->clip_state.state = *state;
745 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
746 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
747
748 cb.buffer = NULL;
749 cb.user_buffer = state->ucp;
750 cb.buffer_offset = 0;
751 cb.buffer_size = 4*4*8;
752 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
753 pipe_resource_reference(&cb.buffer, NULL);
754 }
755
756 static void si_emit_clip_state(struct si_context *sctx)
757 {
758 struct radeon_cmdbuf *cs = sctx->gfx_cs;
759
760 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
761 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
762 }
763
764 static void si_emit_clip_regs(struct si_context *sctx)
765 {
766 struct si_shader *vs = si_get_vs_state(sctx);
767 struct si_shader_selector *vs_sel = vs->selector;
768 struct tgsi_shader_info *info = &vs_sel->info;
769 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
770 unsigned window_space =
771 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
772 unsigned clipdist_mask = vs_sel->clipdist_mask;
773 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
774 unsigned culldist_mask = vs_sel->culldist_mask;
775 unsigned total_mask;
776
777 if (vs->key.opt.clip_disable) {
778 assert(!info->culldist_writemask);
779 clipdist_mask = 0;
780 culldist_mask = 0;
781 }
782 total_mask = clipdist_mask | culldist_mask;
783
784 /* Clip distances on points have no effect, so need to be implemented
785 * as cull distances. This applies for the clipvertex case as well.
786 *
787 * Setting this for primitives other than points should have no adverse
788 * effects.
789 */
790 clipdist_mask &= rs->clip_plane_enable;
791 culldist_mask |= clipdist_mask;
792
793 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
794 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
795 SI_TRACKED_PA_CL_VS_OUT_CNTL,
796 vs_sel->pa_cl_vs_out_cntl |
797 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
798 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
799 clipdist_mask | (culldist_mask << 8));
800 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
801 SI_TRACKED_PA_CL_CLIP_CNTL,
802 rs->pa_cl_clip_cntl |
803 ucp_mask |
804 S_028810_CLIP_DISABLE(window_space));
805
806 if (initial_cdw != sctx->gfx_cs->current.cdw)
807 sctx->context_roll = true;
808 }
809
810 /*
811 * inferred state between framebuffer and rasterizer
812 */
813 static void si_update_poly_offset_state(struct si_context *sctx)
814 {
815 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
816
817 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
818 si_pm4_bind_state(sctx, poly_offset, NULL);
819 return;
820 }
821
822 /* Use the user format, not db_render_format, so that the polygon
823 * offset behaves as expected by applications.
824 */
825 switch (sctx->framebuffer.state.zsbuf->texture->format) {
826 case PIPE_FORMAT_Z16_UNORM:
827 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
828 break;
829 default: /* 24-bit */
830 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
831 break;
832 case PIPE_FORMAT_Z32_FLOAT:
833 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
834 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
835 break;
836 }
837 }
838
839 /*
840 * Rasterizer
841 */
842
843 static uint32_t si_translate_fill(uint32_t func)
844 {
845 switch(func) {
846 case PIPE_POLYGON_MODE_FILL:
847 return V_028814_X_DRAW_TRIANGLES;
848 case PIPE_POLYGON_MODE_LINE:
849 return V_028814_X_DRAW_LINES;
850 case PIPE_POLYGON_MODE_POINT:
851 return V_028814_X_DRAW_POINTS;
852 default:
853 assert(0);
854 return V_028814_X_DRAW_POINTS;
855 }
856 }
857
858 static void *si_create_rs_state(struct pipe_context *ctx,
859 const struct pipe_rasterizer_state *state)
860 {
861 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
862 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
863 struct si_pm4_state *pm4 = &rs->pm4;
864 unsigned tmp, i;
865 float psize_min, psize_max;
866
867 if (!rs) {
868 return NULL;
869 }
870
871 if (!state->front_ccw) {
872 rs->cull_front = !!(state->cull_face & PIPE_FACE_FRONT);
873 rs->cull_back = !!(state->cull_face & PIPE_FACE_BACK);
874 } else {
875 rs->cull_back = !!(state->cull_face & PIPE_FACE_FRONT);
876 rs->cull_front = !!(state->cull_face & PIPE_FACE_BACK);
877 }
878 rs->depth_clamp_any = !state->depth_clip_near || !state->depth_clip_far;
879 rs->provoking_vertex_first = state->flatshade_first;
880 rs->scissor_enable = state->scissor;
881 rs->clip_halfz = state->clip_halfz;
882 rs->two_side = state->light_twoside;
883 rs->multisample_enable = state->multisample;
884 rs->force_persample_interp = state->force_persample_interp;
885 rs->clip_plane_enable = state->clip_plane_enable;
886 rs->half_pixel_center = state->half_pixel_center;
887 rs->line_stipple_enable = state->line_stipple_enable;
888 rs->poly_stipple_enable = state->poly_stipple_enable;
889 rs->line_smooth = state->line_smooth;
890 rs->line_width = state->line_width;
891 rs->poly_smooth = state->poly_smooth;
892 rs->uses_poly_offset = state->offset_point || state->offset_line ||
893 state->offset_tri;
894 rs->clamp_fragment_color = state->clamp_fragment_color;
895 rs->clamp_vertex_color = state->clamp_vertex_color;
896 rs->flatshade = state->flatshade;
897 rs->sprite_coord_enable = state->sprite_coord_enable;
898 rs->rasterizer_discard = state->rasterizer_discard;
899 rs->pa_sc_line_stipple = state->line_stipple_enable ?
900 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
901 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
902 rs->pa_cl_clip_cntl =
903 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
904 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
905 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
906 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
907 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
908
909 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
910 S_0286D4_FLAT_SHADE_ENA(1) |
911 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
912 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
913 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
914 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
915 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
916 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
917
918 /* point size 12.4 fixed point */
919 tmp = (unsigned)(state->point_size * 8.0);
920 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
921
922 if (state->point_size_per_vertex) {
923 psize_min = util_get_min_point_size(state);
924 psize_max = SI_MAX_POINT_SIZE;
925 } else {
926 /* Force the point size to be as if the vertex output was disabled. */
927 psize_min = state->point_size;
928 psize_max = state->point_size;
929 }
930 rs->max_point_size = psize_max;
931
932 /* Divide by two, because 0.5 = 1 pixel. */
933 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
934 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
935 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
936
937 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
938 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
939 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
940 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
941 S_028A48_MSAA_ENABLE(state->multisample ||
942 state->poly_smooth ||
943 state->line_smooth) |
944 S_028A48_VPORT_SCISSOR_ENABLE(1) |
945 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
946
947 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
948 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
949 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
950 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
951 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
952 S_028814_FACE(!state->front_ccw) |
953 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
954 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
955 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
956 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
957 state->fill_back != PIPE_POLYGON_MODE_FILL) |
958 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
959 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
960
961 if (!rs->uses_poly_offset)
962 return rs;
963
964 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
965 if (!rs->pm4_poly_offset) {
966 FREE(rs);
967 return NULL;
968 }
969
970 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
971 for (i = 0; i < 3; i++) {
972 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
973 float offset_units = state->offset_units;
974 float offset_scale = state->offset_scale * 16.0f;
975 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
976
977 if (!state->offset_units_unscaled) {
978 switch (i) {
979 case 0: /* 16-bit zbuffer */
980 offset_units *= 4.0f;
981 pa_su_poly_offset_db_fmt_cntl =
982 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
983 break;
984 case 1: /* 24-bit zbuffer */
985 offset_units *= 2.0f;
986 pa_su_poly_offset_db_fmt_cntl =
987 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
988 break;
989 case 2: /* 32-bit zbuffer */
990 offset_units *= 1.0f;
991 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
992 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
993 break;
994 }
995 }
996
997 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
998 fui(offset_scale));
999 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
1000 fui(offset_units));
1001 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
1002 fui(offset_scale));
1003 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
1004 fui(offset_units));
1005 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
1006 pa_su_poly_offset_db_fmt_cntl);
1007 }
1008
1009 return rs;
1010 }
1011
1012 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1013 {
1014 struct si_context *sctx = (struct si_context *)ctx;
1015 struct si_state_rasterizer *old_rs =
1016 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1017 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1018
1019 if (!state)
1020 return;
1021
1022 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1023 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1024
1025 /* Update the small primitive filter workaround if necessary. */
1026 if (sctx->screen->has_msaa_sample_loc_bug &&
1027 sctx->framebuffer.nr_samples > 1)
1028 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1029 }
1030
1031 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1032 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1033
1034 si_pm4_bind_state(sctx, rasterizer, rs);
1035 si_update_poly_offset_state(sctx);
1036
1037 if (!old_rs ||
1038 old_rs->scissor_enable != rs->scissor_enable)
1039 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1040
1041 if (!old_rs ||
1042 old_rs->line_width != rs->line_width ||
1043 old_rs->max_point_size != rs->max_point_size ||
1044 old_rs->half_pixel_center != rs->half_pixel_center)
1045 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1046
1047 if (!old_rs ||
1048 old_rs->clip_halfz != rs->clip_halfz)
1049 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1050
1051 if (!old_rs ||
1052 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1053 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1054 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1055
1056 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1057 rs->line_stipple_enable;
1058
1059 if (!old_rs ||
1060 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1061 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1062 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1063 old_rs->flatshade != rs->flatshade ||
1064 old_rs->two_side != rs->two_side ||
1065 old_rs->multisample_enable != rs->multisample_enable ||
1066 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1067 old_rs->poly_smooth != rs->poly_smooth ||
1068 old_rs->line_smooth != rs->line_smooth ||
1069 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1070 old_rs->force_persample_interp != rs->force_persample_interp)
1071 sctx->do_update_shaders = true;
1072 }
1073
1074 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1075 {
1076 struct si_context *sctx = (struct si_context *)ctx;
1077 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1078
1079 if (sctx->queued.named.rasterizer == state)
1080 si_pm4_bind_state(sctx, poly_offset, NULL);
1081
1082 FREE(rs->pm4_poly_offset);
1083 si_pm4_delete_state(sctx, rasterizer, rs);
1084 }
1085
1086 /*
1087 * infeered state between dsa and stencil ref
1088 */
1089 static void si_emit_stencil_ref(struct si_context *sctx)
1090 {
1091 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1092 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1093 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1094
1095 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1096 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1097 S_028430_STENCILMASK(dsa->valuemask[0]) |
1098 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1099 S_028430_STENCILOPVAL(1));
1100 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1101 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1102 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1103 S_028434_STENCILOPVAL_BF(1));
1104 }
1105
1106 static void si_set_stencil_ref(struct pipe_context *ctx,
1107 const struct pipe_stencil_ref *state)
1108 {
1109 struct si_context *sctx = (struct si_context *)ctx;
1110
1111 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1112 return;
1113
1114 sctx->stencil_ref.state = *state;
1115 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1116 }
1117
1118
1119 /*
1120 * DSA
1121 */
1122
1123 static uint32_t si_translate_stencil_op(int s_op)
1124 {
1125 switch (s_op) {
1126 case PIPE_STENCIL_OP_KEEP:
1127 return V_02842C_STENCIL_KEEP;
1128 case PIPE_STENCIL_OP_ZERO:
1129 return V_02842C_STENCIL_ZERO;
1130 case PIPE_STENCIL_OP_REPLACE:
1131 return V_02842C_STENCIL_REPLACE_TEST;
1132 case PIPE_STENCIL_OP_INCR:
1133 return V_02842C_STENCIL_ADD_CLAMP;
1134 case PIPE_STENCIL_OP_DECR:
1135 return V_02842C_STENCIL_SUB_CLAMP;
1136 case PIPE_STENCIL_OP_INCR_WRAP:
1137 return V_02842C_STENCIL_ADD_WRAP;
1138 case PIPE_STENCIL_OP_DECR_WRAP:
1139 return V_02842C_STENCIL_SUB_WRAP;
1140 case PIPE_STENCIL_OP_INVERT:
1141 return V_02842C_STENCIL_INVERT;
1142 default:
1143 PRINT_ERR("Unknown stencil op %d", s_op);
1144 assert(0);
1145 break;
1146 }
1147 return 0;
1148 }
1149
1150 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1151 {
1152 return s->enabled && s->writemask &&
1153 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1154 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1155 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1156 }
1157
1158 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1159 {
1160 /* REPLACE is normally order invariant, except when the stencil
1161 * reference value is written by the fragment shader. Tracking this
1162 * interaction does not seem worth the effort, so be conservative. */
1163 return op != PIPE_STENCIL_OP_INCR &&
1164 op != PIPE_STENCIL_OP_DECR &&
1165 op != PIPE_STENCIL_OP_REPLACE;
1166 }
1167
1168 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1169 * invariant in the sense that the set of passing fragments as well as the
1170 * final stencil buffer result does not depend on the order of fragments. */
1171 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1172 {
1173 return !state->enabled || !state->writemask ||
1174 /* The following assumes that Z writes are disabled. */
1175 (state->func == PIPE_FUNC_ALWAYS &&
1176 si_order_invariant_stencil_op(state->zpass_op) &&
1177 si_order_invariant_stencil_op(state->zfail_op)) ||
1178 (state->func == PIPE_FUNC_NEVER &&
1179 si_order_invariant_stencil_op(state->fail_op));
1180 }
1181
1182 static void *si_create_dsa_state(struct pipe_context *ctx,
1183 const struct pipe_depth_stencil_alpha_state *state)
1184 {
1185 struct si_context *sctx = (struct si_context *)ctx;
1186 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1187 struct si_pm4_state *pm4 = &dsa->pm4;
1188 unsigned db_depth_control;
1189 uint32_t db_stencil_control = 0;
1190
1191 if (!dsa) {
1192 return NULL;
1193 }
1194
1195 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1196 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1197 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1198 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1199
1200 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1201 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1202 S_028800_ZFUNC(state->depth.func) |
1203 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1204
1205 /* stencil */
1206 if (state->stencil[0].enabled) {
1207 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1208 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1209 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1210 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1211 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1212
1213 if (state->stencil[1].enabled) {
1214 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1215 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1216 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1217 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1218 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1219 }
1220 }
1221
1222 /* alpha */
1223 if (state->alpha.enabled) {
1224 dsa->alpha_func = state->alpha.func;
1225
1226 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1227 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1228 } else {
1229 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1230 }
1231
1232 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1233 if (state->stencil[0].enabled)
1234 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1235 if (state->depth.bounds_test) {
1236 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1237 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1238 }
1239
1240 dsa->depth_enabled = state->depth.enabled;
1241 dsa->depth_write_enabled = state->depth.enabled &&
1242 state->depth.writemask;
1243 dsa->stencil_enabled = state->stencil[0].enabled;
1244 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1245 (si_dsa_writes_stencil(&state->stencil[0]) ||
1246 si_dsa_writes_stencil(&state->stencil[1]));
1247 dsa->db_can_write = dsa->depth_write_enabled ||
1248 dsa->stencil_write_enabled;
1249
1250 bool zfunc_is_ordered =
1251 state->depth.func == PIPE_FUNC_NEVER ||
1252 state->depth.func == PIPE_FUNC_LESS ||
1253 state->depth.func == PIPE_FUNC_LEQUAL ||
1254 state->depth.func == PIPE_FUNC_GREATER ||
1255 state->depth.func == PIPE_FUNC_GEQUAL;
1256
1257 bool nozwrite_and_order_invariant_stencil =
1258 !dsa->db_can_write ||
1259 (!dsa->depth_write_enabled &&
1260 si_order_invariant_stencil_state(&state->stencil[0]) &&
1261 si_order_invariant_stencil_state(&state->stencil[1]));
1262
1263 dsa->order_invariance[1].zs =
1264 nozwrite_and_order_invariant_stencil ||
1265 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1266 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1267
1268 dsa->order_invariance[1].pass_set =
1269 nozwrite_and_order_invariant_stencil ||
1270 (!dsa->stencil_write_enabled &&
1271 (state->depth.func == PIPE_FUNC_ALWAYS ||
1272 state->depth.func == PIPE_FUNC_NEVER));
1273 dsa->order_invariance[0].pass_set =
1274 !dsa->depth_write_enabled ||
1275 (state->depth.func == PIPE_FUNC_ALWAYS ||
1276 state->depth.func == PIPE_FUNC_NEVER);
1277
1278 dsa->order_invariance[1].pass_last =
1279 sctx->screen->assume_no_z_fights &&
1280 !dsa->stencil_write_enabled &&
1281 dsa->depth_write_enabled && zfunc_is_ordered;
1282 dsa->order_invariance[0].pass_last =
1283 sctx->screen->assume_no_z_fights &&
1284 dsa->depth_write_enabled && zfunc_is_ordered;
1285
1286 return dsa;
1287 }
1288
1289 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1290 {
1291 struct si_context *sctx = (struct si_context *)ctx;
1292 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1293 struct si_state_dsa *dsa = state;
1294
1295 if (!state)
1296 return;
1297
1298 si_pm4_bind_state(sctx, dsa, dsa);
1299
1300 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1301 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1302 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1303 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1304 }
1305
1306 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1307 sctx->do_update_shaders = true;
1308
1309 if (sctx->screen->dpbb_allowed &&
1310 (!old_dsa ||
1311 (old_dsa->depth_enabled != dsa->depth_enabled ||
1312 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1313 old_dsa->db_can_write != dsa->db_can_write)))
1314 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1315
1316 if (sctx->screen->has_out_of_order_rast &&
1317 (!old_dsa ||
1318 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1319 sizeof(old_dsa->order_invariance))))
1320 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1321 }
1322
1323 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1324 {
1325 struct si_context *sctx = (struct si_context *)ctx;
1326 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1327 }
1328
1329 static void *si_create_db_flush_dsa(struct si_context *sctx)
1330 {
1331 struct pipe_depth_stencil_alpha_state dsa = {};
1332
1333 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1334 }
1335
1336 /* DB RENDER STATE */
1337
1338 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1339 {
1340 struct si_context *sctx = (struct si_context*)ctx;
1341
1342 /* Pipeline stat & streamout queries. */
1343 if (enable) {
1344 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1345 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1346 } else {
1347 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1348 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1349 }
1350
1351 /* Occlusion queries. */
1352 if (sctx->occlusion_queries_disabled != !enable) {
1353 sctx->occlusion_queries_disabled = !enable;
1354 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1355 }
1356 }
1357
1358 void si_set_occlusion_query_state(struct si_context *sctx,
1359 bool old_perfect_enable)
1360 {
1361 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1362
1363 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1364
1365 if (perfect_enable != old_perfect_enable)
1366 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1367 }
1368
1369 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1370 {
1371 st->saved_compute = sctx->cs_shader_state.program;
1372
1373 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1374 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1375
1376 st->saved_ssbo_writable_mask = 0;
1377
1378 for (unsigned i = 0; i < 3; i++) {
1379 if (sctx->const_and_shader_buffers[PIPE_SHADER_COMPUTE].writable_mask &
1380 (1u << si_get_shaderbuf_slot(i)))
1381 st->saved_ssbo_writable_mask |= 1 << i;
1382 }
1383 }
1384
1385 void si_restore_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1386 {
1387 sctx->b.bind_compute_state(&sctx->b, st->saved_compute);
1388
1389 sctx->b.set_constant_buffer(&sctx->b, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1390 pipe_resource_reference(&st->saved_const0.buffer, NULL);
1391
1392 sctx->b.set_shader_buffers(&sctx->b, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo,
1393 st->saved_ssbo_writable_mask);
1394 for (unsigned i = 0; i < 3; ++i)
1395 pipe_resource_reference(&st->saved_ssbo[i].buffer, NULL);
1396 }
1397
1398 static void si_emit_db_render_state(struct si_context *sctx)
1399 {
1400 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1401 unsigned db_shader_control, db_render_control, db_count_control;
1402 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1403
1404 /* DB_RENDER_CONTROL */
1405 if (sctx->dbcb_depth_copy_enabled ||
1406 sctx->dbcb_stencil_copy_enabled) {
1407 db_render_control =
1408 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1409 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1410 S_028000_COPY_CENTROID(1) |
1411 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1412 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1413 db_render_control =
1414 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1415 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1416 } else {
1417 db_render_control =
1418 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1419 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1420 }
1421
1422 /* DB_COUNT_CONTROL (occlusion queries) */
1423 if (sctx->num_occlusion_queries > 0 &&
1424 !sctx->occlusion_queries_disabled) {
1425 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1426
1427 if (sctx->chip_class >= GFX7) {
1428 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1429
1430 /* Stoney doesn't increment occlusion query counters
1431 * if the sample rate is 16x. Use 8x sample rate instead.
1432 */
1433 if (sctx->family == CHIP_STONEY)
1434 log_sample_rate = MIN2(log_sample_rate, 3);
1435
1436 db_count_control =
1437 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1438 S_028004_SAMPLE_RATE(log_sample_rate) |
1439 S_028004_ZPASS_ENABLE(1) |
1440 S_028004_SLICE_EVEN_ENABLE(1) |
1441 S_028004_SLICE_ODD_ENABLE(1);
1442 } else {
1443 db_count_control =
1444 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1445 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1446 }
1447 } else {
1448 /* Disable occlusion queries. */
1449 if (sctx->chip_class >= GFX7) {
1450 db_count_control = 0;
1451 } else {
1452 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1453 }
1454 }
1455
1456 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1457 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1458 db_count_control);
1459
1460 /* DB_RENDER_OVERRIDE2 */
1461 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1462 SI_TRACKED_DB_RENDER_OVERRIDE2,
1463 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1464 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1465 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1466
1467 db_shader_control = sctx->ps_db_shader_control;
1468
1469 /* Bug workaround for smoothing (overrasterization) on GFX6. */
1470 if (sctx->chip_class == GFX6 && sctx->smoothing_enabled) {
1471 db_shader_control &= C_02880C_Z_ORDER;
1472 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1473 }
1474
1475 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1476 if (!rs->multisample_enable)
1477 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1478
1479 if (sctx->screen->has_rbplus &&
1480 !sctx->screen->rbplus_allowed)
1481 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1482
1483 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1484 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1485
1486 if (initial_cdw != sctx->gfx_cs->current.cdw)
1487 sctx->context_roll = true;
1488 }
1489
1490 /*
1491 * format translation
1492 */
1493 static uint32_t si_translate_colorformat(enum pipe_format format)
1494 {
1495 const struct util_format_description *desc = util_format_description(format);
1496 if (!desc)
1497 return V_028C70_COLOR_INVALID;
1498
1499 #define HAS_SIZE(x,y,z,w) \
1500 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1501 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1502
1503 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1504 return V_028C70_COLOR_10_11_11;
1505
1506 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1507 return V_028C70_COLOR_INVALID;
1508
1509 /* hw cannot support mixed formats (except depth/stencil, since
1510 * stencil is not written to). */
1511 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1512 return V_028C70_COLOR_INVALID;
1513
1514 switch (desc->nr_channels) {
1515 case 1:
1516 switch (desc->channel[0].size) {
1517 case 8:
1518 return V_028C70_COLOR_8;
1519 case 16:
1520 return V_028C70_COLOR_16;
1521 case 32:
1522 return V_028C70_COLOR_32;
1523 }
1524 break;
1525 case 2:
1526 if (desc->channel[0].size == desc->channel[1].size) {
1527 switch (desc->channel[0].size) {
1528 case 8:
1529 return V_028C70_COLOR_8_8;
1530 case 16:
1531 return V_028C70_COLOR_16_16;
1532 case 32:
1533 return V_028C70_COLOR_32_32;
1534 }
1535 } else if (HAS_SIZE(8,24,0,0)) {
1536 return V_028C70_COLOR_24_8;
1537 } else if (HAS_SIZE(24,8,0,0)) {
1538 return V_028C70_COLOR_8_24;
1539 }
1540 break;
1541 case 3:
1542 if (HAS_SIZE(5,6,5,0)) {
1543 return V_028C70_COLOR_5_6_5;
1544 } else if (HAS_SIZE(32,8,24,0)) {
1545 return V_028C70_COLOR_X24_8_32_FLOAT;
1546 }
1547 break;
1548 case 4:
1549 if (desc->channel[0].size == desc->channel[1].size &&
1550 desc->channel[0].size == desc->channel[2].size &&
1551 desc->channel[0].size == desc->channel[3].size) {
1552 switch (desc->channel[0].size) {
1553 case 4:
1554 return V_028C70_COLOR_4_4_4_4;
1555 case 8:
1556 return V_028C70_COLOR_8_8_8_8;
1557 case 16:
1558 return V_028C70_COLOR_16_16_16_16;
1559 case 32:
1560 return V_028C70_COLOR_32_32_32_32;
1561 }
1562 } else if (HAS_SIZE(5,5,5,1)) {
1563 return V_028C70_COLOR_1_5_5_5;
1564 } else if (HAS_SIZE(1,5,5,5)) {
1565 return V_028C70_COLOR_5_5_5_1;
1566 } else if (HAS_SIZE(10,10,10,2)) {
1567 return V_028C70_COLOR_2_10_10_10;
1568 }
1569 break;
1570 }
1571 return V_028C70_COLOR_INVALID;
1572 }
1573
1574 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1575 {
1576 if (SI_BIG_ENDIAN) {
1577 switch(colorformat) {
1578 /* 8-bit buffers. */
1579 case V_028C70_COLOR_8:
1580 return V_028C70_ENDIAN_NONE;
1581
1582 /* 16-bit buffers. */
1583 case V_028C70_COLOR_5_6_5:
1584 case V_028C70_COLOR_1_5_5_5:
1585 case V_028C70_COLOR_4_4_4_4:
1586 case V_028C70_COLOR_16:
1587 case V_028C70_COLOR_8_8:
1588 return V_028C70_ENDIAN_8IN16;
1589
1590 /* 32-bit buffers. */
1591 case V_028C70_COLOR_8_8_8_8:
1592 case V_028C70_COLOR_2_10_10_10:
1593 case V_028C70_COLOR_8_24:
1594 case V_028C70_COLOR_24_8:
1595 case V_028C70_COLOR_16_16:
1596 return V_028C70_ENDIAN_8IN32;
1597
1598 /* 64-bit buffers. */
1599 case V_028C70_COLOR_16_16_16_16:
1600 return V_028C70_ENDIAN_8IN16;
1601
1602 case V_028C70_COLOR_32_32:
1603 return V_028C70_ENDIAN_8IN32;
1604
1605 /* 128-bit buffers. */
1606 case V_028C70_COLOR_32_32_32_32:
1607 return V_028C70_ENDIAN_8IN32;
1608 default:
1609 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1610 }
1611 } else {
1612 return V_028C70_ENDIAN_NONE;
1613 }
1614 }
1615
1616 static uint32_t si_translate_dbformat(enum pipe_format format)
1617 {
1618 switch (format) {
1619 case PIPE_FORMAT_Z16_UNORM:
1620 return V_028040_Z_16;
1621 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1622 case PIPE_FORMAT_X8Z24_UNORM:
1623 case PIPE_FORMAT_Z24X8_UNORM:
1624 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1625 return V_028040_Z_24; /* deprecated on AMD GCN */
1626 case PIPE_FORMAT_Z32_FLOAT:
1627 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1628 return V_028040_Z_32_FLOAT;
1629 default:
1630 return V_028040_Z_INVALID;
1631 }
1632 }
1633
1634 /*
1635 * Texture translation
1636 */
1637
1638 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1639 enum pipe_format format,
1640 const struct util_format_description *desc,
1641 int first_non_void)
1642 {
1643 struct si_screen *sscreen = (struct si_screen*)screen;
1644 bool uniform = true;
1645 int i;
1646
1647 assert(sscreen->info.chip_class <= GFX9);
1648
1649 /* Colorspace (return non-RGB formats directly). */
1650 switch (desc->colorspace) {
1651 /* Depth stencil formats */
1652 case UTIL_FORMAT_COLORSPACE_ZS:
1653 switch (format) {
1654 case PIPE_FORMAT_Z16_UNORM:
1655 return V_008F14_IMG_DATA_FORMAT_16;
1656 case PIPE_FORMAT_X24S8_UINT:
1657 case PIPE_FORMAT_S8X24_UINT:
1658 /*
1659 * Implemented as an 8_8_8_8 data format to fix texture
1660 * gathers in stencil sampling. This affects at least
1661 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
1662 */
1663 if (sscreen->info.chip_class <= GFX8)
1664 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1665
1666 if (format == PIPE_FORMAT_X24S8_UINT)
1667 return V_008F14_IMG_DATA_FORMAT_8_24;
1668 else
1669 return V_008F14_IMG_DATA_FORMAT_24_8;
1670 case PIPE_FORMAT_Z24X8_UNORM:
1671 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1672 return V_008F14_IMG_DATA_FORMAT_8_24;
1673 case PIPE_FORMAT_X8Z24_UNORM:
1674 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1675 return V_008F14_IMG_DATA_FORMAT_24_8;
1676 case PIPE_FORMAT_S8_UINT:
1677 return V_008F14_IMG_DATA_FORMAT_8;
1678 case PIPE_FORMAT_Z32_FLOAT:
1679 return V_008F14_IMG_DATA_FORMAT_32;
1680 case PIPE_FORMAT_X32_S8X24_UINT:
1681 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1682 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1683 default:
1684 goto out_unknown;
1685 }
1686
1687 case UTIL_FORMAT_COLORSPACE_YUV:
1688 goto out_unknown; /* TODO */
1689
1690 case UTIL_FORMAT_COLORSPACE_SRGB:
1691 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1692 goto out_unknown;
1693 break;
1694
1695 default:
1696 break;
1697 }
1698
1699 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1700 if (!sscreen->info.has_format_bc1_through_bc7)
1701 goto out_unknown;
1702
1703 switch (format) {
1704 case PIPE_FORMAT_RGTC1_SNORM:
1705 case PIPE_FORMAT_LATC1_SNORM:
1706 case PIPE_FORMAT_RGTC1_UNORM:
1707 case PIPE_FORMAT_LATC1_UNORM:
1708 return V_008F14_IMG_DATA_FORMAT_BC4;
1709 case PIPE_FORMAT_RGTC2_SNORM:
1710 case PIPE_FORMAT_LATC2_SNORM:
1711 case PIPE_FORMAT_RGTC2_UNORM:
1712 case PIPE_FORMAT_LATC2_UNORM:
1713 return V_008F14_IMG_DATA_FORMAT_BC5;
1714 default:
1715 goto out_unknown;
1716 }
1717 }
1718
1719 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1720 (sscreen->info.family == CHIP_STONEY ||
1721 sscreen->info.family == CHIP_VEGA10 ||
1722 sscreen->info.family == CHIP_RAVEN)) {
1723 switch (format) {
1724 case PIPE_FORMAT_ETC1_RGB8:
1725 case PIPE_FORMAT_ETC2_RGB8:
1726 case PIPE_FORMAT_ETC2_SRGB8:
1727 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1728 case PIPE_FORMAT_ETC2_RGB8A1:
1729 case PIPE_FORMAT_ETC2_SRGB8A1:
1730 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1731 case PIPE_FORMAT_ETC2_RGBA8:
1732 case PIPE_FORMAT_ETC2_SRGBA8:
1733 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1734 case PIPE_FORMAT_ETC2_R11_UNORM:
1735 case PIPE_FORMAT_ETC2_R11_SNORM:
1736 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1737 case PIPE_FORMAT_ETC2_RG11_UNORM:
1738 case PIPE_FORMAT_ETC2_RG11_SNORM:
1739 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1740 default:
1741 goto out_unknown;
1742 }
1743 }
1744
1745 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1746 if (!sscreen->info.has_format_bc1_through_bc7)
1747 goto out_unknown;
1748
1749 switch (format) {
1750 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1751 case PIPE_FORMAT_BPTC_SRGBA:
1752 return V_008F14_IMG_DATA_FORMAT_BC7;
1753 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1754 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1755 return V_008F14_IMG_DATA_FORMAT_BC6;
1756 default:
1757 goto out_unknown;
1758 }
1759 }
1760
1761 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1762 switch (format) {
1763 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1764 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1765 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1766 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1767 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1768 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1769 default:
1770 goto out_unknown;
1771 }
1772 }
1773
1774 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1775 if (!sscreen->info.has_format_bc1_through_bc7)
1776 goto out_unknown;
1777
1778 switch (format) {
1779 case PIPE_FORMAT_DXT1_RGB:
1780 case PIPE_FORMAT_DXT1_RGBA:
1781 case PIPE_FORMAT_DXT1_SRGB:
1782 case PIPE_FORMAT_DXT1_SRGBA:
1783 return V_008F14_IMG_DATA_FORMAT_BC1;
1784 case PIPE_FORMAT_DXT3_RGBA:
1785 case PIPE_FORMAT_DXT3_SRGBA:
1786 return V_008F14_IMG_DATA_FORMAT_BC2;
1787 case PIPE_FORMAT_DXT5_RGBA:
1788 case PIPE_FORMAT_DXT5_SRGBA:
1789 return V_008F14_IMG_DATA_FORMAT_BC3;
1790 default:
1791 goto out_unknown;
1792 }
1793 }
1794
1795 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1796 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1797 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1798 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1799 }
1800
1801 /* R8G8Bx_SNORM - TODO CxV8U8 */
1802
1803 /* hw cannot support mixed formats (except depth/stencil, since only
1804 * depth is read).*/
1805 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1806 goto out_unknown;
1807
1808 /* See whether the components are of the same size. */
1809 for (i = 1; i < desc->nr_channels; i++) {
1810 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1811 }
1812
1813 /* Non-uniform formats. */
1814 if (!uniform) {
1815 switch(desc->nr_channels) {
1816 case 3:
1817 if (desc->channel[0].size == 5 &&
1818 desc->channel[1].size == 6 &&
1819 desc->channel[2].size == 5) {
1820 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1821 }
1822 goto out_unknown;
1823 case 4:
1824 if (desc->channel[0].size == 5 &&
1825 desc->channel[1].size == 5 &&
1826 desc->channel[2].size == 5 &&
1827 desc->channel[3].size == 1) {
1828 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1829 }
1830 if (desc->channel[0].size == 1 &&
1831 desc->channel[1].size == 5 &&
1832 desc->channel[2].size == 5 &&
1833 desc->channel[3].size == 5) {
1834 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1835 }
1836 if (desc->channel[0].size == 10 &&
1837 desc->channel[1].size == 10 &&
1838 desc->channel[2].size == 10 &&
1839 desc->channel[3].size == 2) {
1840 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1841 }
1842 goto out_unknown;
1843 }
1844 goto out_unknown;
1845 }
1846
1847 if (first_non_void < 0 || first_non_void > 3)
1848 goto out_unknown;
1849
1850 /* uniform formats */
1851 switch (desc->channel[first_non_void].size) {
1852 case 4:
1853 switch (desc->nr_channels) {
1854 #if 0 /* Not supported for render targets */
1855 case 2:
1856 return V_008F14_IMG_DATA_FORMAT_4_4;
1857 #endif
1858 case 4:
1859 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1860 }
1861 break;
1862 case 8:
1863 switch (desc->nr_channels) {
1864 case 1:
1865 return V_008F14_IMG_DATA_FORMAT_8;
1866 case 2:
1867 return V_008F14_IMG_DATA_FORMAT_8_8;
1868 case 4:
1869 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1870 }
1871 break;
1872 case 16:
1873 switch (desc->nr_channels) {
1874 case 1:
1875 return V_008F14_IMG_DATA_FORMAT_16;
1876 case 2:
1877 return V_008F14_IMG_DATA_FORMAT_16_16;
1878 case 4:
1879 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1880 }
1881 break;
1882 case 32:
1883 switch (desc->nr_channels) {
1884 case 1:
1885 return V_008F14_IMG_DATA_FORMAT_32;
1886 case 2:
1887 return V_008F14_IMG_DATA_FORMAT_32_32;
1888 #if 0 /* Not supported for render targets */
1889 case 3:
1890 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1891 #endif
1892 case 4:
1893 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1894 }
1895 }
1896
1897 out_unknown:
1898 return ~0;
1899 }
1900
1901 static unsigned si_tex_wrap(unsigned wrap)
1902 {
1903 switch (wrap) {
1904 default:
1905 case PIPE_TEX_WRAP_REPEAT:
1906 return V_008F30_SQ_TEX_WRAP;
1907 case PIPE_TEX_WRAP_CLAMP:
1908 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1909 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1910 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1911 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1912 return V_008F30_SQ_TEX_CLAMP_BORDER;
1913 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1914 return V_008F30_SQ_TEX_MIRROR;
1915 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1916 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1917 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1918 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1919 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1920 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1921 }
1922 }
1923
1924 static unsigned si_tex_mipfilter(unsigned filter)
1925 {
1926 switch (filter) {
1927 case PIPE_TEX_MIPFILTER_NEAREST:
1928 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1929 case PIPE_TEX_MIPFILTER_LINEAR:
1930 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1931 default:
1932 case PIPE_TEX_MIPFILTER_NONE:
1933 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1934 }
1935 }
1936
1937 static unsigned si_tex_compare(unsigned compare)
1938 {
1939 switch (compare) {
1940 default:
1941 case PIPE_FUNC_NEVER:
1942 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1943 case PIPE_FUNC_LESS:
1944 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1945 case PIPE_FUNC_EQUAL:
1946 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1947 case PIPE_FUNC_LEQUAL:
1948 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1949 case PIPE_FUNC_GREATER:
1950 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1951 case PIPE_FUNC_NOTEQUAL:
1952 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1953 case PIPE_FUNC_GEQUAL:
1954 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1955 case PIPE_FUNC_ALWAYS:
1956 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1957 }
1958 }
1959
1960 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1961 unsigned view_target, unsigned nr_samples)
1962 {
1963 unsigned res_target = tex->buffer.b.b.target;
1964
1965 if (view_target == PIPE_TEXTURE_CUBE ||
1966 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1967 res_target = view_target;
1968 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1969 else if (res_target == PIPE_TEXTURE_CUBE ||
1970 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1971 res_target = PIPE_TEXTURE_2D_ARRAY;
1972
1973 /* GFX9 allocates 1D textures as 2D. */
1974 if ((res_target == PIPE_TEXTURE_1D ||
1975 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1976 sscreen->info.chip_class >= GFX9 &&
1977 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1978 if (res_target == PIPE_TEXTURE_1D)
1979 res_target = PIPE_TEXTURE_2D;
1980 else
1981 res_target = PIPE_TEXTURE_2D_ARRAY;
1982 }
1983
1984 switch (res_target) {
1985 default:
1986 case PIPE_TEXTURE_1D:
1987 return V_008F1C_SQ_RSRC_IMG_1D;
1988 case PIPE_TEXTURE_1D_ARRAY:
1989 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1990 case PIPE_TEXTURE_2D:
1991 case PIPE_TEXTURE_RECT:
1992 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1993 V_008F1C_SQ_RSRC_IMG_2D;
1994 case PIPE_TEXTURE_2D_ARRAY:
1995 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1996 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1997 case PIPE_TEXTURE_3D:
1998 return V_008F1C_SQ_RSRC_IMG_3D;
1999 case PIPE_TEXTURE_CUBE:
2000 case PIPE_TEXTURE_CUBE_ARRAY:
2001 return V_008F1C_SQ_RSRC_IMG_CUBE;
2002 }
2003 }
2004
2005 /*
2006 * Format support testing
2007 */
2008
2009 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
2010 {
2011 const struct util_format_description *desc = util_format_description(format);
2012 if (!desc)
2013 return false;
2014
2015 return si_translate_texformat(screen, format, desc,
2016 util_format_get_first_non_void_channel(format)) != ~0U;
2017 }
2018
2019 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
2020 const struct util_format_description *desc,
2021 int first_non_void)
2022 {
2023 int i;
2024
2025 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2026
2027 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2028 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
2029
2030 assert(first_non_void >= 0);
2031
2032 if (desc->nr_channels == 4 &&
2033 desc->channel[0].size == 10 &&
2034 desc->channel[1].size == 10 &&
2035 desc->channel[2].size == 10 &&
2036 desc->channel[3].size == 2)
2037 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
2038
2039 /* See whether the components are of the same size. */
2040 for (i = 0; i < desc->nr_channels; i++) {
2041 if (desc->channel[first_non_void].size != desc->channel[i].size)
2042 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2043 }
2044
2045 switch (desc->channel[first_non_void].size) {
2046 case 8:
2047 switch (desc->nr_channels) {
2048 case 1:
2049 case 3: /* 3 loads */
2050 return V_008F0C_BUF_DATA_FORMAT_8;
2051 case 2:
2052 return V_008F0C_BUF_DATA_FORMAT_8_8;
2053 case 4:
2054 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2055 }
2056 break;
2057 case 16:
2058 switch (desc->nr_channels) {
2059 case 1:
2060 case 3: /* 3 loads */
2061 return V_008F0C_BUF_DATA_FORMAT_16;
2062 case 2:
2063 return V_008F0C_BUF_DATA_FORMAT_16_16;
2064 case 4:
2065 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2066 }
2067 break;
2068 case 32:
2069 switch (desc->nr_channels) {
2070 case 1:
2071 return V_008F0C_BUF_DATA_FORMAT_32;
2072 case 2:
2073 return V_008F0C_BUF_DATA_FORMAT_32_32;
2074 case 3:
2075 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2076 case 4:
2077 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2078 }
2079 break;
2080 case 64:
2081 /* Legacy double formats. */
2082 switch (desc->nr_channels) {
2083 case 1: /* 1 load */
2084 return V_008F0C_BUF_DATA_FORMAT_32_32;
2085 case 2: /* 1 load */
2086 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2087 case 3: /* 3 loads */
2088 return V_008F0C_BUF_DATA_FORMAT_32_32;
2089 case 4: /* 2 loads */
2090 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2091 }
2092 break;
2093 }
2094
2095 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2096 }
2097
2098 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2099 const struct util_format_description *desc,
2100 int first_non_void)
2101 {
2102 assert(((struct si_screen *)screen)->info.chip_class <= GFX9);
2103
2104 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2105 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2106
2107 assert(first_non_void >= 0);
2108
2109 switch (desc->channel[first_non_void].type) {
2110 case UTIL_FORMAT_TYPE_SIGNED:
2111 case UTIL_FORMAT_TYPE_FIXED:
2112 if (desc->channel[first_non_void].size >= 32 ||
2113 desc->channel[first_non_void].pure_integer)
2114 return V_008F0C_BUF_NUM_FORMAT_SINT;
2115 else if (desc->channel[first_non_void].normalized)
2116 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2117 else
2118 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2119 break;
2120 case UTIL_FORMAT_TYPE_UNSIGNED:
2121 if (desc->channel[first_non_void].size >= 32 ||
2122 desc->channel[first_non_void].pure_integer)
2123 return V_008F0C_BUF_NUM_FORMAT_UINT;
2124 else if (desc->channel[first_non_void].normalized)
2125 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2126 else
2127 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2128 break;
2129 case UTIL_FORMAT_TYPE_FLOAT:
2130 default:
2131 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2132 }
2133 }
2134
2135 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2136 enum pipe_format format,
2137 unsigned usage)
2138 {
2139 const struct util_format_description *desc;
2140 int first_non_void;
2141 unsigned data_format;
2142
2143 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2144 PIPE_BIND_SAMPLER_VIEW |
2145 PIPE_BIND_VERTEX_BUFFER)) == 0);
2146
2147 desc = util_format_description(format);
2148 if (!desc)
2149 return 0;
2150
2151 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2152 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2153 * for read-only access (with caveats surrounding bounds checks), but
2154 * obviously fails for write access which we have to implement for
2155 * shader images. Luckily, OpenGL doesn't expect this to be supported
2156 * anyway, and so the only impact is on PBO uploads / downloads, which
2157 * shouldn't be expected to be fast for GL_RGB anyway.
2158 */
2159 if (desc->block.bits == 3 * 8 ||
2160 desc->block.bits == 3 * 16) {
2161 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2162 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2163 if (!usage)
2164 return 0;
2165 }
2166 }
2167
2168 first_non_void = util_format_get_first_non_void_channel(format);
2169 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2170 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2171 return 0;
2172
2173 return usage;
2174 }
2175
2176 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2177 {
2178 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2179 si_translate_colorswap(format, false) != ~0U;
2180 }
2181
2182 static bool si_is_zs_format_supported(enum pipe_format format)
2183 {
2184 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2185 }
2186
2187 static boolean si_is_format_supported(struct pipe_screen *screen,
2188 enum pipe_format format,
2189 enum pipe_texture_target target,
2190 unsigned sample_count,
2191 unsigned storage_sample_count,
2192 unsigned usage)
2193 {
2194 struct si_screen *sscreen = (struct si_screen *)screen;
2195 unsigned retval = 0;
2196
2197 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2198 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2199 return false;
2200 }
2201
2202 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2203 return false;
2204
2205 if (sample_count > 1) {
2206 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2207 return false;
2208
2209 if (usage & PIPE_BIND_SHADER_IMAGE)
2210 return false;
2211
2212 /* Only power-of-two sample counts are supported. */
2213 if (!util_is_power_of_two_or_zero(sample_count) ||
2214 !util_is_power_of_two_or_zero(storage_sample_count))
2215 return false;
2216
2217 /* MSAA support without framebuffer attachments. */
2218 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2219 return true;
2220
2221 if (!sscreen->info.has_eqaa_surface_allocator ||
2222 util_format_is_depth_or_stencil(format)) {
2223 /* Color without EQAA or depth/stencil. */
2224 if (sample_count > 8 ||
2225 sample_count != storage_sample_count)
2226 return false;
2227 } else {
2228 /* Color with EQAA. */
2229 if (sample_count > 16 ||
2230 storage_sample_count > 8)
2231 return false;
2232 }
2233 }
2234
2235 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2236 PIPE_BIND_SHADER_IMAGE)) {
2237 if (target == PIPE_BUFFER) {
2238 retval |= si_is_vertex_format_supported(
2239 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2240 PIPE_BIND_SHADER_IMAGE));
2241 } else {
2242 if (si_is_sampler_format_supported(screen, format))
2243 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2244 PIPE_BIND_SHADER_IMAGE);
2245 }
2246 }
2247
2248 if ((usage & (PIPE_BIND_RENDER_TARGET |
2249 PIPE_BIND_DISPLAY_TARGET |
2250 PIPE_BIND_SCANOUT |
2251 PIPE_BIND_SHARED |
2252 PIPE_BIND_BLENDABLE)) &&
2253 si_is_colorbuffer_format_supported(format)) {
2254 retval |= usage &
2255 (PIPE_BIND_RENDER_TARGET |
2256 PIPE_BIND_DISPLAY_TARGET |
2257 PIPE_BIND_SCANOUT |
2258 PIPE_BIND_SHARED);
2259 if (!util_format_is_pure_integer(format) &&
2260 !util_format_is_depth_or_stencil(format))
2261 retval |= usage & PIPE_BIND_BLENDABLE;
2262 }
2263
2264 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2265 si_is_zs_format_supported(format)) {
2266 retval |= PIPE_BIND_DEPTH_STENCIL;
2267 }
2268
2269 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2270 retval |= si_is_vertex_format_supported(screen, format,
2271 PIPE_BIND_VERTEX_BUFFER);
2272 }
2273
2274 if ((usage & PIPE_BIND_LINEAR) &&
2275 !util_format_is_compressed(format) &&
2276 !(usage & PIPE_BIND_DEPTH_STENCIL))
2277 retval |= PIPE_BIND_LINEAR;
2278
2279 return retval == usage;
2280 }
2281
2282 /*
2283 * framebuffer handling
2284 */
2285
2286 static void si_choose_spi_color_formats(struct si_surface *surf,
2287 unsigned format, unsigned swap,
2288 unsigned ntype, bool is_depth)
2289 {
2290 /* Alpha is needed for alpha-to-coverage.
2291 * Blending may be with or without alpha.
2292 */
2293 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2294 unsigned alpha = 0; /* exports alpha, but may not support blending */
2295 unsigned blend = 0; /* supports blending, but may not export alpha */
2296 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2297
2298 /* Choose the SPI color formats. These are required values for RB+.
2299 * Other chips have multiple choices, though they are not necessarily better.
2300 */
2301 switch (format) {
2302 case V_028C70_COLOR_5_6_5:
2303 case V_028C70_COLOR_1_5_5_5:
2304 case V_028C70_COLOR_5_5_5_1:
2305 case V_028C70_COLOR_4_4_4_4:
2306 case V_028C70_COLOR_10_11_11:
2307 case V_028C70_COLOR_11_11_10:
2308 case V_028C70_COLOR_8:
2309 case V_028C70_COLOR_8_8:
2310 case V_028C70_COLOR_8_8_8_8:
2311 case V_028C70_COLOR_10_10_10_2:
2312 case V_028C70_COLOR_2_10_10_10:
2313 if (ntype == V_028C70_NUMBER_UINT)
2314 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2315 else if (ntype == V_028C70_NUMBER_SINT)
2316 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2317 else
2318 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2319 break;
2320
2321 case V_028C70_COLOR_16:
2322 case V_028C70_COLOR_16_16:
2323 case V_028C70_COLOR_16_16_16_16:
2324 if (ntype == V_028C70_NUMBER_UNORM ||
2325 ntype == V_028C70_NUMBER_SNORM) {
2326 /* UNORM16 and SNORM16 don't support blending */
2327 if (ntype == V_028C70_NUMBER_UNORM)
2328 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2329 else
2330 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2331
2332 /* Use 32 bits per channel for blending. */
2333 if (format == V_028C70_COLOR_16) {
2334 if (swap == V_028C70_SWAP_STD) { /* R */
2335 blend = V_028714_SPI_SHADER_32_R;
2336 blend_alpha = V_028714_SPI_SHADER_32_AR;
2337 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2338 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2339 else
2340 assert(0);
2341 } else if (format == V_028C70_COLOR_16_16) {
2342 if (swap == V_028C70_SWAP_STD) { /* RG */
2343 blend = V_028714_SPI_SHADER_32_GR;
2344 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2345 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2346 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2347 else
2348 assert(0);
2349 } else /* 16_16_16_16 */
2350 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2351 } else if (ntype == V_028C70_NUMBER_UINT)
2352 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2353 else if (ntype == V_028C70_NUMBER_SINT)
2354 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2355 else if (ntype == V_028C70_NUMBER_FLOAT)
2356 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2357 else
2358 assert(0);
2359 break;
2360
2361 case V_028C70_COLOR_32:
2362 if (swap == V_028C70_SWAP_STD) { /* R */
2363 blend = normal = V_028714_SPI_SHADER_32_R;
2364 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2365 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2366 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2367 else
2368 assert(0);
2369 break;
2370
2371 case V_028C70_COLOR_32_32:
2372 if (swap == V_028C70_SWAP_STD) { /* RG */
2373 blend = normal = V_028714_SPI_SHADER_32_GR;
2374 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2375 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2376 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2377 else
2378 assert(0);
2379 break;
2380
2381 case V_028C70_COLOR_32_32_32_32:
2382 case V_028C70_COLOR_8_24:
2383 case V_028C70_COLOR_24_8:
2384 case V_028C70_COLOR_X24_8_32_FLOAT:
2385 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2386 break;
2387
2388 default:
2389 assert(0);
2390 return;
2391 }
2392
2393 /* The DB->CB copy needs 32_ABGR. */
2394 if (is_depth)
2395 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2396
2397 surf->spi_shader_col_format = normal;
2398 surf->spi_shader_col_format_alpha = alpha;
2399 surf->spi_shader_col_format_blend = blend;
2400 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2401 }
2402
2403 static void si_initialize_color_surface(struct si_context *sctx,
2404 struct si_surface *surf)
2405 {
2406 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2407 unsigned color_info, color_attrib;
2408 unsigned format, swap, ntype, endian;
2409 const struct util_format_description *desc;
2410 int firstchan;
2411 unsigned blend_clamp = 0, blend_bypass = 0;
2412
2413 desc = util_format_description(surf->base.format);
2414 for (firstchan = 0; firstchan < 4; firstchan++) {
2415 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2416 break;
2417 }
2418 }
2419 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2420 ntype = V_028C70_NUMBER_FLOAT;
2421 } else {
2422 ntype = V_028C70_NUMBER_UNORM;
2423 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2424 ntype = V_028C70_NUMBER_SRGB;
2425 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2426 if (desc->channel[firstchan].pure_integer) {
2427 ntype = V_028C70_NUMBER_SINT;
2428 } else {
2429 assert(desc->channel[firstchan].normalized);
2430 ntype = V_028C70_NUMBER_SNORM;
2431 }
2432 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2433 if (desc->channel[firstchan].pure_integer) {
2434 ntype = V_028C70_NUMBER_UINT;
2435 } else {
2436 assert(desc->channel[firstchan].normalized);
2437 ntype = V_028C70_NUMBER_UNORM;
2438 }
2439 }
2440 }
2441
2442 format = si_translate_colorformat(surf->base.format);
2443 if (format == V_028C70_COLOR_INVALID) {
2444 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2445 }
2446 assert(format != V_028C70_COLOR_INVALID);
2447 swap = si_translate_colorswap(surf->base.format, false);
2448 endian = si_colorformat_endian_swap(format);
2449
2450 /* blend clamp should be set for all NORM/SRGB types */
2451 if (ntype == V_028C70_NUMBER_UNORM ||
2452 ntype == V_028C70_NUMBER_SNORM ||
2453 ntype == V_028C70_NUMBER_SRGB)
2454 blend_clamp = 1;
2455
2456 /* set blend bypass according to docs if SINT/UINT or
2457 8/24 COLOR variants */
2458 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2459 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2460 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2461 blend_clamp = 0;
2462 blend_bypass = 1;
2463 }
2464
2465 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2466 if (format == V_028C70_COLOR_8 ||
2467 format == V_028C70_COLOR_8_8 ||
2468 format == V_028C70_COLOR_8_8_8_8)
2469 surf->color_is_int8 = true;
2470 else if (format == V_028C70_COLOR_10_10_10_2 ||
2471 format == V_028C70_COLOR_2_10_10_10)
2472 surf->color_is_int10 = true;
2473 }
2474
2475 color_info = S_028C70_FORMAT(format) |
2476 S_028C70_COMP_SWAP(swap) |
2477 S_028C70_BLEND_CLAMP(blend_clamp) |
2478 S_028C70_BLEND_BYPASS(blend_bypass) |
2479 S_028C70_SIMPLE_FLOAT(1) |
2480 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2481 ntype != V_028C70_NUMBER_SNORM &&
2482 ntype != V_028C70_NUMBER_SRGB &&
2483 format != V_028C70_COLOR_8_24 &&
2484 format != V_028C70_COLOR_24_8) |
2485 S_028C70_NUMBER_TYPE(ntype) |
2486 S_028C70_ENDIAN(endian);
2487
2488 /* Intensity is implemented as Red, so treat it that way. */
2489 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2490 util_format_is_intensity(surf->base.format));
2491
2492 if (tex->buffer.b.b.nr_samples > 1) {
2493 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2494 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2495
2496 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2497 S_028C74_NUM_FRAGMENTS(log_fragments);
2498
2499 if (tex->fmask_offset) {
2500 color_info |= S_028C70_COMPRESSION(1);
2501 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2502
2503 if (sctx->chip_class == GFX6) {
2504 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on GFX6 too */
2505 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2506 }
2507 }
2508 }
2509
2510 if (sctx->chip_class >= GFX8) {
2511 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2512 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2513
2514 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2515 64 for APU because all of our APUs to date use DIMMs which have
2516 a request granularity size of 64B while all other chips have a
2517 32B request size */
2518 if (!sctx->screen->info.has_dedicated_vram)
2519 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2520
2521 if (tex->buffer.b.b.nr_storage_samples > 1) {
2522 if (tex->surface.bpe == 1)
2523 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2524 else if (tex->surface.bpe == 2)
2525 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2526 }
2527
2528 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2529 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2530 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2531 }
2532
2533 /* This must be set for fast clear to work without FMASK. */
2534 if (!tex->surface.fmask_size && sctx->chip_class == GFX6) {
2535 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2536 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2537 }
2538
2539 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2540 S_028C6C_SLICE_MAX_GFX6(surf->base.u.tex.last_layer);
2541
2542 if (sctx->chip_class >= GFX9) {
2543 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2544
2545 color_view |= S_028C6C_MIP_LEVEL_GFX9(surf->base.u.tex.level);
2546 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2547 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2548 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2549 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2550 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2551 }
2552
2553 surf->cb_color_view = color_view;
2554 surf->cb_color_info = color_info;
2555 surf->cb_color_attrib = color_attrib;
2556
2557 /* Determine pixel shader export format */
2558 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2559
2560 surf->color_initialized = true;
2561 }
2562
2563 static void si_init_depth_surface(struct si_context *sctx,
2564 struct si_surface *surf)
2565 {
2566 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2567 unsigned level = surf->base.u.tex.level;
2568 unsigned format, stencil_format;
2569 uint32_t z_info, s_info;
2570
2571 format = si_translate_dbformat(tex->db_render_format);
2572 stencil_format = tex->surface.has_stencil ?
2573 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2574
2575 assert(format != V_028040_Z_INVALID);
2576 if (format == V_028040_Z_INVALID)
2577 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2578
2579 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2580 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2581 surf->db_htile_data_base = 0;
2582 surf->db_htile_surface = 0;
2583
2584 if (sctx->chip_class >= GFX9) {
2585 assert(tex->surface.u.gfx9.surf_offset == 0);
2586 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2587 surf->db_stencil_base = (tex->buffer.gpu_address +
2588 tex->surface.u.gfx9.stencil_offset) >> 8;
2589 z_info = S_028038_FORMAT(format) |
2590 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2591 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2592 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2593 s_info = S_02803C_FORMAT(stencil_format) |
2594 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2595 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2596 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2597 surf->db_depth_view |= S_028008_MIPID(level);
2598 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2599 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2600
2601 if (si_htile_enabled(tex, level)) {
2602 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2603 S_028038_ALLOW_EXPCLEAR(1);
2604
2605 if (tex->tc_compatible_htile) {
2606 unsigned max_zplanes = 4;
2607
2608 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2609 tex->buffer.b.b.nr_samples > 1)
2610 max_zplanes = 2;
2611
2612 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2613 S_028038_ITERATE_FLUSH(1);
2614 s_info |= S_02803C_ITERATE_FLUSH(1);
2615 }
2616
2617 if (tex->surface.has_stencil) {
2618 /* Stencil buffer workaround ported from the GFX6-GFX8 code.
2619 * See that for explanation.
2620 */
2621 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2622 } else {
2623 /* Use all HTILE for depth if there's no stencil. */
2624 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2625 }
2626
2627 surf->db_htile_data_base = (tex->buffer.gpu_address +
2628 tex->htile_offset) >> 8;
2629 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2630 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2631 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2632 }
2633 } else {
2634 /* GFX6-GFX8 */
2635 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2636
2637 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2638
2639 surf->db_depth_base = (tex->buffer.gpu_address +
2640 tex->surface.u.legacy.level[level].offset) >> 8;
2641 surf->db_stencil_base = (tex->buffer.gpu_address +
2642 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2643
2644 z_info = S_028040_FORMAT(format) |
2645 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2646 s_info = S_028044_FORMAT(stencil_format);
2647 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2648
2649 if (sctx->chip_class >= GFX7) {
2650 struct radeon_info *info = &sctx->screen->info;
2651 unsigned index = tex->surface.u.legacy.tiling_index[level];
2652 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2653 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2654 unsigned tile_mode = info->si_tile_mode_array[index];
2655 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2656 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2657
2658 surf->db_depth_info |=
2659 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2660 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2661 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2662 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2663 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2664 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2665 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2666 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2667 } else {
2668 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2669 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2670 tile_mode_index = si_tile_mode_index(tex, level, true);
2671 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2672 }
2673
2674 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2675 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2676 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2677 levelinfo->nblk_y) / 64 - 1);
2678
2679 if (si_htile_enabled(tex, level)) {
2680 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2681 S_028040_ALLOW_EXPCLEAR(1);
2682
2683 if (tex->surface.has_stencil) {
2684 /* Workaround: For a not yet understood reason, the
2685 * combination of MSAA, fast stencil clear and stencil
2686 * decompress messes with subsequent stencil buffer
2687 * uses. Problem was reproduced on Verde, Bonaire,
2688 * Tonga, and Carrizo.
2689 *
2690 * Disabling EXPCLEAR works around the problem.
2691 *
2692 * Check piglit's arb_texture_multisample-stencil-clear
2693 * test if you want to try changing this.
2694 */
2695 if (tex->buffer.b.b.nr_samples <= 1)
2696 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2697 } else if (!tex->tc_compatible_htile) {
2698 /* Use all of the htile_buffer for depth if there's no stencil.
2699 * This must not be set when TC-compatible HTILE is enabled
2700 * due to a hw bug.
2701 */
2702 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2703 }
2704
2705 surf->db_htile_data_base = (tex->buffer.gpu_address +
2706 tex->htile_offset) >> 8;
2707 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2708
2709 if (tex->tc_compatible_htile) {
2710 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2711
2712 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2713 if (tex->buffer.b.b.nr_samples <= 1)
2714 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2715 else if (tex->buffer.b.b.nr_samples <= 4)
2716 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2717 else
2718 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2719 }
2720 }
2721 }
2722
2723 surf->db_z_info = z_info;
2724 surf->db_stencil_info = s_info;
2725
2726 surf->depth_initialized = true;
2727 }
2728
2729 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2730 {
2731 if (sctx->decompression_enabled)
2732 return;
2733
2734 if (sctx->framebuffer.state.zsbuf) {
2735 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2736 struct si_texture *tex = (struct si_texture *)surf->texture;
2737
2738 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2739
2740 if (tex->surface.has_stencil)
2741 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2742 }
2743
2744 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2745 while (compressed_cb_mask) {
2746 unsigned i = u_bit_scan(&compressed_cb_mask);
2747 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2748 struct si_texture *tex = (struct si_texture*)surf->texture;
2749
2750 if (tex->fmask_offset)
2751 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2752 if (tex->dcc_gather_statistics)
2753 tex->separate_dcc_dirty = true;
2754 }
2755 }
2756
2757 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2758 {
2759 for (int i = 0; i < state->nr_cbufs; ++i) {
2760 struct si_surface *surf = NULL;
2761 struct si_texture *tex;
2762
2763 if (!state->cbufs[i])
2764 continue;
2765 surf = (struct si_surface*)state->cbufs[i];
2766 tex = (struct si_texture*)surf->base.texture;
2767
2768 p_atomic_dec(&tex->framebuffers_bound);
2769 }
2770 }
2771
2772 static void si_set_framebuffer_state(struct pipe_context *ctx,
2773 const struct pipe_framebuffer_state *state)
2774 {
2775 struct si_context *sctx = (struct si_context *)ctx;
2776 struct si_surface *surf = NULL;
2777 struct si_texture *tex;
2778 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2779 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2780 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2781 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2782 bool old_has_stencil =
2783 old_has_zsbuf &&
2784 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2785 bool unbound = false;
2786 int i;
2787
2788 /* Reject zero-sized framebuffers due to a hw bug on GFX6 that occurs
2789 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2790 * We could implement the full workaround here, but it's a useless case.
2791 */
2792 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2793 unreachable("the framebuffer shouldn't have zero area");
2794 return;
2795 }
2796
2797 si_update_fb_dirtiness_after_rendering(sctx);
2798
2799 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2800 if (!sctx->framebuffer.state.cbufs[i])
2801 continue;
2802
2803 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2804 if (tex->dcc_gather_statistics)
2805 vi_separate_dcc_stop_query(sctx, tex);
2806 }
2807
2808 /* Disable DCC if the formats are incompatible. */
2809 for (i = 0; i < state->nr_cbufs; i++) {
2810 if (!state->cbufs[i])
2811 continue;
2812
2813 surf = (struct si_surface*)state->cbufs[i];
2814 tex = (struct si_texture*)surf->base.texture;
2815
2816 if (!surf->dcc_incompatible)
2817 continue;
2818
2819 /* Since the DCC decompression calls back into set_framebuffer-
2820 * _state, we need to unbind the framebuffer, so that
2821 * vi_separate_dcc_stop_query isn't called twice with the same
2822 * color buffer.
2823 */
2824 if (!unbound) {
2825 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2826 unbound = true;
2827 }
2828
2829 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2830 if (!si_texture_disable_dcc(sctx, tex))
2831 si_decompress_dcc(sctx, tex);
2832
2833 surf->dcc_incompatible = false;
2834 }
2835
2836 /* Only flush TC when changing the framebuffer state, because
2837 * the only client not using TC that can change textures is
2838 * the framebuffer.
2839 *
2840 * Wait for compute shaders because of possible transitions:
2841 * - FB write -> shader read
2842 * - shader write -> FB read
2843 *
2844 * DB caches are flushed on demand (using si_decompress_textures).
2845 *
2846 * When MSAA is enabled, CB and TC caches are flushed on demand
2847 * (after FMASK decompression). Shader write -> FB read transitions
2848 * cannot happen for MSAA textures, because MSAA shader images are
2849 * not supported.
2850 *
2851 * Only flush and wait for CB if there is actually a bound color buffer.
2852 */
2853 if (sctx->framebuffer.uncompressed_cb_mask) {
2854 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2855 sctx->framebuffer.CB_has_shader_readable_metadata,
2856 sctx->framebuffer.all_DCC_pipe_aligned);
2857 }
2858
2859 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2860
2861 /* u_blitter doesn't invoke depth decompression when it does multiple
2862 * blits in a row, but the only case when it matters for DB is when
2863 * doing generate_mipmap. So here we flush DB manually between
2864 * individual generate_mipmap blits.
2865 * Note that lower mipmap levels aren't compressed.
2866 */
2867 if (sctx->generate_mipmap_for_depth) {
2868 si_make_DB_shader_coherent(sctx, 1, false,
2869 sctx->framebuffer.DB_has_shader_readable_metadata);
2870 } else if (sctx->chip_class == GFX9) {
2871 /* It appears that DB metadata "leaks" in a sequence of:
2872 * - depth clear
2873 * - DCC decompress for shader image writes (with DB disabled)
2874 * - render with DEPTH_BEFORE_SHADER=1
2875 * Flushing DB metadata works around the problem.
2876 */
2877 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2878 }
2879
2880 /* Take the maximum of the old and new count. If the new count is lower,
2881 * dirtying is needed to disable the unbound colorbuffers.
2882 */
2883 sctx->framebuffer.dirty_cbufs |=
2884 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2885 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2886
2887 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2888 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2889
2890 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2891 sctx->framebuffer.spi_shader_col_format = 0;
2892 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2893 sctx->framebuffer.spi_shader_col_format_blend = 0;
2894 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2895 sctx->framebuffer.color_is_int8 = 0;
2896 sctx->framebuffer.color_is_int10 = 0;
2897
2898 sctx->framebuffer.compressed_cb_mask = 0;
2899 sctx->framebuffer.uncompressed_cb_mask = 0;
2900 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2901 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2902 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2903 sctx->framebuffer.any_dst_linear = false;
2904 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2905 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2906 sctx->framebuffer.all_DCC_pipe_aligned = true;
2907 unsigned num_bpp64_colorbufs = 0;
2908
2909 for (i = 0; i < state->nr_cbufs; i++) {
2910 if (!state->cbufs[i])
2911 continue;
2912
2913 surf = (struct si_surface*)state->cbufs[i];
2914 tex = (struct si_texture*)surf->base.texture;
2915
2916 if (!surf->color_initialized) {
2917 si_initialize_color_surface(sctx, surf);
2918 }
2919
2920 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2921 sctx->framebuffer.spi_shader_col_format |=
2922 surf->spi_shader_col_format << (i * 4);
2923 sctx->framebuffer.spi_shader_col_format_alpha |=
2924 surf->spi_shader_col_format_alpha << (i * 4);
2925 sctx->framebuffer.spi_shader_col_format_blend |=
2926 surf->spi_shader_col_format_blend << (i * 4);
2927 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2928 surf->spi_shader_col_format_blend_alpha << (i * 4);
2929
2930 if (surf->color_is_int8)
2931 sctx->framebuffer.color_is_int8 |= 1 << i;
2932 if (surf->color_is_int10)
2933 sctx->framebuffer.color_is_int10 |= 1 << i;
2934
2935 if (tex->fmask_offset)
2936 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2937 else
2938 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2939
2940 /* Don't update nr_color_samples for non-AA buffers.
2941 * (e.g. destination of MSAA resolve)
2942 */
2943 if (tex->buffer.b.b.nr_samples >= 2 &&
2944 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2945 sctx->framebuffer.nr_color_samples =
2946 MIN2(sctx->framebuffer.nr_color_samples,
2947 tex->buffer.b.b.nr_storage_samples);
2948 sctx->framebuffer.nr_color_samples =
2949 MAX2(1, sctx->framebuffer.nr_color_samples);
2950 }
2951
2952 if (tex->surface.is_linear)
2953 sctx->framebuffer.any_dst_linear = true;
2954 if (tex->surface.bpe >= 8)
2955 num_bpp64_colorbufs++;
2956
2957 if (vi_dcc_enabled(tex, surf->base.u.tex.level)) {
2958 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2959
2960 if (sctx->chip_class >= GFX9 &&
2961 !tex->surface.u.gfx9.dcc.pipe_aligned)
2962 sctx->framebuffer.all_DCC_pipe_aligned = false;
2963 }
2964
2965 si_context_add_resource_size(sctx, surf->base.texture);
2966
2967 p_atomic_inc(&tex->framebuffers_bound);
2968
2969 if (tex->dcc_gather_statistics) {
2970 /* Dirty tracking must be enabled for DCC usage analysis. */
2971 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2972 vi_separate_dcc_start_query(sctx, tex);
2973 }
2974 }
2975
2976 /* For optimal DCC performance. */
2977 if (sctx->chip_class == GFX8)
2978 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2979 else if (num_bpp64_colorbufs >= 5)
2980 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2981 else
2982 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2983
2984 struct si_texture *zstex = NULL;
2985
2986 if (state->zsbuf) {
2987 surf = (struct si_surface*)state->zsbuf;
2988 zstex = (struct si_texture*)surf->base.texture;
2989
2990 if (!surf->depth_initialized) {
2991 si_init_depth_surface(sctx, surf);
2992 }
2993
2994 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2995 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2996
2997 si_context_add_resource_size(sctx, surf->base.texture);
2998 }
2999
3000 si_update_ps_colorbuf0_slot(sctx);
3001 si_update_poly_offset_state(sctx);
3002 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3003 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
3004
3005 if (sctx->screen->dpbb_allowed)
3006 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3007
3008 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
3009 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3010
3011 if (sctx->screen->has_out_of_order_rast &&
3012 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
3013 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
3014 (zstex && zstex->surface.has_stencil != old_has_stencil)))
3015 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3016
3017 if (sctx->framebuffer.nr_samples != old_nr_samples) {
3018 struct pipe_constant_buffer constbuf = {0};
3019
3020 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3021 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3022
3023 constbuf.buffer = sctx->sample_pos_buffer;
3024
3025 /* Set sample locations as fragment shader constants. */
3026 switch (sctx->framebuffer.nr_samples) {
3027 case 1:
3028 constbuf.buffer_offset = 0;
3029 break;
3030 case 2:
3031 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
3032 (ubyte*)sctx->sample_positions.x1;
3033 break;
3034 case 4:
3035 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
3036 (ubyte*)sctx->sample_positions.x1;
3037 break;
3038 case 8:
3039 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
3040 (ubyte*)sctx->sample_positions.x1;
3041 break;
3042 case 16:
3043 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
3044 (ubyte*)sctx->sample_positions.x1;
3045 break;
3046 default:
3047 PRINT_ERR("Requested an invalid number of samples %i.\n",
3048 sctx->framebuffer.nr_samples);
3049 assert(0);
3050 }
3051 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3052 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3053
3054 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3055 }
3056
3057 sctx->do_update_shaders = true;
3058
3059 if (!sctx->decompression_enabled) {
3060 /* Prevent textures decompression when the framebuffer state
3061 * changes come from the decompression passes themselves.
3062 */
3063 sctx->need_check_render_feedback = true;
3064 }
3065 }
3066
3067 static void si_emit_framebuffer_state(struct si_context *sctx)
3068 {
3069 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3070 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3071 unsigned i, nr_cbufs = state->nr_cbufs;
3072 struct si_texture *tex = NULL;
3073 struct si_surface *cb = NULL;
3074 unsigned cb_color_info = 0;
3075
3076 /* Colorbuffers. */
3077 for (i = 0; i < nr_cbufs; i++) {
3078 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3079 unsigned cb_color_attrib;
3080
3081 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3082 continue;
3083
3084 cb = (struct si_surface*)state->cbufs[i];
3085 if (!cb) {
3086 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3087 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3088 continue;
3089 }
3090
3091 tex = (struct si_texture *)cb->base.texture;
3092 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3093 &tex->buffer, RADEON_USAGE_READWRITE,
3094 tex->buffer.b.b.nr_samples > 1 ?
3095 RADEON_PRIO_COLOR_BUFFER_MSAA :
3096 RADEON_PRIO_COLOR_BUFFER);
3097
3098 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3099 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3100 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3101 RADEON_PRIO_SEPARATE_META);
3102 }
3103
3104 if (tex->dcc_separate_buffer)
3105 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3106 tex->dcc_separate_buffer,
3107 RADEON_USAGE_READWRITE,
3108 RADEON_PRIO_SEPARATE_META);
3109
3110 /* Compute mutable surface parameters. */
3111 cb_color_base = tex->buffer.gpu_address >> 8;
3112 cb_color_fmask = 0;
3113 cb_color_cmask = tex->cmask_base_address_reg;
3114 cb_dcc_base = 0;
3115 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3116 cb_color_attrib = cb->cb_color_attrib;
3117
3118 if (cb->base.u.tex.level > 0)
3119 cb_color_info &= C_028C70_FAST_CLEAR;
3120
3121 if (tex->fmask_offset) {
3122 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3123 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3124 }
3125
3126 /* Set up DCC. */
3127 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3128 bool is_msaa_resolve_dst = state->cbufs[0] &&
3129 state->cbufs[0]->texture->nr_samples > 1 &&
3130 state->cbufs[1] == &cb->base &&
3131 state->cbufs[1]->texture->nr_samples <= 1;
3132
3133 if (!is_msaa_resolve_dst)
3134 cb_color_info |= S_028C70_DCC_ENABLE(1);
3135
3136 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3137 tex->dcc_offset) >> 8;
3138 cb_dcc_base |= tex->surface.tile_swizzle;
3139 }
3140
3141 if (sctx->chip_class >= GFX9) {
3142 struct gfx9_surf_meta_flags meta;
3143
3144 if (tex->dcc_offset)
3145 meta = tex->surface.u.gfx9.dcc;
3146 else
3147 meta = tex->surface.u.gfx9.cmask;
3148
3149 /* Set mutable surface parameters. */
3150 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3151 cb_color_base |= tex->surface.tile_swizzle;
3152 if (!tex->fmask_offset)
3153 cb_color_fmask = cb_color_base;
3154 if (cb->base.u.tex.level > 0)
3155 cb_color_cmask = cb_color_base;
3156 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3157 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3158 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3159 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3160
3161 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3162 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3163 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3164 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3165 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3166 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3167 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3168 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3169 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3170 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3171 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3172 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3173 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3174 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3175 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3176 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3177
3178 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3179 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3180 } else {
3181 /* Compute mutable surface parameters (GFX6-GFX8). */
3182 const struct legacy_surf_level *level_info =
3183 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3184 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3185 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3186
3187 cb_color_base += level_info->offset >> 8;
3188 /* Only macrotiled modes can set tile swizzle. */
3189 if (level_info->mode == RADEON_SURF_MODE_2D)
3190 cb_color_base |= tex->surface.tile_swizzle;
3191
3192 if (!tex->fmask_offset)
3193 cb_color_fmask = cb_color_base;
3194 if (cb->base.u.tex.level > 0)
3195 cb_color_cmask = cb_color_base;
3196 if (cb_dcc_base)
3197 cb_dcc_base += level_info->dcc_offset >> 8;
3198
3199 pitch_tile_max = level_info->nblk_x / 8 - 1;
3200 slice_tile_max = level_info->nblk_x *
3201 level_info->nblk_y / 64 - 1;
3202 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3203
3204 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3205 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3206 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3207
3208 if (tex->fmask_offset) {
3209 if (sctx->chip_class >= GFX7)
3210 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3211 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3212 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3213 } else {
3214 /* This must be set for fast clear to work without FMASK. */
3215 if (sctx->chip_class >= GFX7)
3216 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3217 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3218 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3219 }
3220
3221 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3222 sctx->chip_class >= GFX8 ? 14 : 13);
3223 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3224 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3225 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3226 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3227 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3228 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3229 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3230 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3231 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3232 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3233 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3234 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3235 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3236
3237 if (sctx->chip_class >= GFX8) /* R_028C94_CB_COLOR0_DCC_BASE */
3238 radeon_emit(cs, cb_dcc_base);
3239 }
3240 }
3241 for (; i < 8 ; i++)
3242 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3243 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3244
3245 /* ZS buffer. */
3246 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3247 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3248 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3249
3250 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3251 &tex->buffer, RADEON_USAGE_READWRITE,
3252 zb->base.texture->nr_samples > 1 ?
3253 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3254 RADEON_PRIO_DEPTH_BUFFER);
3255
3256 if (sctx->chip_class >= GFX9) {
3257 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3258 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3259 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3260 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3261
3262 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3263 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3264 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3265 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3266 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3267 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3268 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3269 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3270 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3271 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3272 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3273 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3274
3275 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3276 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3277 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3278 } else {
3279 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3280
3281 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3282 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3283 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3284 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3285 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3286 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3287 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3288 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3289 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3290 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3291 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3292 }
3293
3294 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3295 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3296 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3297
3298 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3299 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3300 } else if (sctx->framebuffer.dirty_zsbuf) {
3301 if (sctx->chip_class >= GFX9)
3302 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3303 else
3304 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3305
3306 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3307 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3308 }
3309
3310 /* Framebuffer dimensions. */
3311 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3312 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3313 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3314
3315 if (sctx->screen->dfsm_allowed) {
3316 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3317 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3318 }
3319
3320 sctx->framebuffer.dirty_cbufs = 0;
3321 sctx->framebuffer.dirty_zsbuf = false;
3322 }
3323
3324 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3325 {
3326 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3327 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3328 unsigned nr_samples = sctx->framebuffer.nr_samples;
3329 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3330
3331 /* Smoothing (only possible with nr_samples == 1) uses the same
3332 * sample locations as the MSAA it simulates.
3333 */
3334 if (nr_samples <= 1 && sctx->smoothing_enabled)
3335 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3336
3337 /* On Polaris, the small primitive filter uses the sample locations
3338 * even when MSAA is off, so we need to make sure they're set to 0.
3339 */
3340 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3341 nr_samples != sctx->sample_locs_num_samples) {
3342 sctx->sample_locs_num_samples = nr_samples;
3343 si_emit_sample_locations(cs, nr_samples);
3344 }
3345
3346 if (sctx->family >= CHIP_POLARIS10) {
3347 unsigned small_prim_filter_cntl =
3348 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3349 /* line bug */
3350 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3351
3352 /* The alternative of setting sample locations to 0 would
3353 * require a DB flush to avoid Z errors, see
3354 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3355 */
3356 if (has_msaa_sample_loc_bug &&
3357 sctx->framebuffer.nr_samples > 1 &&
3358 !rs->multisample_enable)
3359 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3360
3361 radeon_opt_set_context_reg(sctx,
3362 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3363 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3364 small_prim_filter_cntl);
3365 }
3366
3367 /* The exclusion bits can be set to improve rasterization efficiency
3368 * if no sample lies on the pixel boundary (-8 sample offset).
3369 */
3370 bool exclusion = sctx->chip_class >= GFX7 &&
3371 (!rs->multisample_enable || nr_samples != 16);
3372 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3373 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3374 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3375 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3376 }
3377
3378 static bool si_out_of_order_rasterization(struct si_context *sctx)
3379 {
3380 struct si_state_blend *blend = sctx->queued.named.blend;
3381 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3382
3383 if (!sctx->screen->has_out_of_order_rast)
3384 return false;
3385
3386 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3387
3388 if (blend) {
3389 colormask &= blend->cb_target_enabled_4bit;
3390 } else {
3391 colormask = 0;
3392 }
3393
3394 /* Conservative: No logic op. */
3395 if (colormask && blend->logicop_enable)
3396 return false;
3397
3398 struct si_dsa_order_invariance dsa_order_invariant = {
3399 .zs = true, .pass_set = true, .pass_last = false
3400 };
3401
3402 if (sctx->framebuffer.state.zsbuf) {
3403 struct si_texture *zstex =
3404 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3405 bool has_stencil = zstex->surface.has_stencil;
3406 dsa_order_invariant = dsa->order_invariance[has_stencil];
3407 if (!dsa_order_invariant.zs)
3408 return false;
3409
3410 /* The set of PS invocations is always order invariant,
3411 * except when early Z/S tests are requested. */
3412 if (sctx->ps_shader.cso &&
3413 sctx->ps_shader.cso->info.writes_memory &&
3414 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3415 !dsa_order_invariant.pass_set)
3416 return false;
3417
3418 if (sctx->num_perfect_occlusion_queries != 0 &&
3419 !dsa_order_invariant.pass_set)
3420 return false;
3421 }
3422
3423 if (!colormask)
3424 return true;
3425
3426 unsigned blendmask = colormask & blend->blend_enable_4bit;
3427
3428 if (blendmask) {
3429 /* Only commutative blending. */
3430 if (blendmask & ~blend->commutative_4bit)
3431 return false;
3432
3433 if (!dsa_order_invariant.pass_set)
3434 return false;
3435 }
3436
3437 if (colormask & ~blendmask) {
3438 if (!dsa_order_invariant.pass_last)
3439 return false;
3440 }
3441
3442 return true;
3443 }
3444
3445 static void si_emit_msaa_config(struct si_context *sctx)
3446 {
3447 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3448 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3449 /* 33% faster rendering to linear color buffers */
3450 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3451 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3452 unsigned sc_mode_cntl_1 =
3453 S_028A4C_WALK_SIZE(dst_is_linear) |
3454 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3455 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3456 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3457 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3458 /* always 1: */
3459 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3460 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3461 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3462 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3463 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3464 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3465 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3466 S_028804_INCOHERENT_EQAA_READS(1) |
3467 S_028804_INTERPOLATE_COMP_Z(1) |
3468 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3469 unsigned coverage_samples, color_samples, z_samples;
3470 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3471
3472 /* S: Coverage samples (up to 16x):
3473 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3474 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3475 *
3476 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3477 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3478 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3479 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3480 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3481 * # Z samples).
3482 *
3483 * F: Color samples (up to 8x, must be <= coverage samples):
3484 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3485 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3486 *
3487 * Can be anything between coverage and color samples:
3488 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3489 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3490 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3491 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3492 * # All are currently set the same as coverage samples.
3493 *
3494 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3495 * flag for undefined color samples. A shader-based resolve must handle unknowns
3496 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3497 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3498 * useful. The CB resolve always drops unknowns.
3499 *
3500 * Sensible AA configurations:
3501 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3502 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3503 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3504 * EQAA 8s 8z 8f = 8x MSAA
3505 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3506 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3507 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3508 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3509 * EQAA 4s 4z 4f = 4x MSAA
3510 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3511 * EQAA 2s 2z 2f = 2x MSAA
3512 */
3513 if (sctx->framebuffer.nr_samples > 1 && rs->multisample_enable) {
3514 coverage_samples = sctx->framebuffer.nr_samples;
3515 color_samples = sctx->framebuffer.nr_color_samples;
3516
3517 if (sctx->framebuffer.state.zsbuf) {
3518 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3519 z_samples = MAX2(1, z_samples);
3520 } else {
3521 z_samples = coverage_samples;
3522 }
3523 } else if (sctx->smoothing_enabled) {
3524 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3525 } else {
3526 coverage_samples = color_samples = z_samples = 1;
3527 }
3528
3529 /* Required by OpenGL line rasterization.
3530 *
3531 * TODO: We should also enable perpendicular endcaps for AA lines,
3532 * but that requires implementing line stippling in the pixel
3533 * shader. SC can only do line stippling with axis-aligned
3534 * endcaps.
3535 */
3536 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3537 unsigned sc_aa_config = 0;
3538
3539 if (coverage_samples > 1) {
3540 /* distance from the pixel center, indexed by log2(nr_samples) */
3541 static unsigned max_dist[] = {
3542 0, /* unused */
3543 4, /* 2x MSAA */
3544 6, /* 4x MSAA */
3545 7, /* 8x MSAA */
3546 8, /* 16x MSAA */
3547 };
3548 unsigned log_samples = util_logbase2(coverage_samples);
3549 unsigned log_z_samples = util_logbase2(z_samples);
3550 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3551 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3552
3553 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3554 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3555 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3556 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3557
3558 if (sctx->framebuffer.nr_samples > 1) {
3559 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3560 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3561 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3562 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3563 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3564 } else if (sctx->smoothing_enabled) {
3565 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3566 }
3567 }
3568
3569 unsigned initial_cdw = cs->current.cdw;
3570
3571 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3572 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3573 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3574 sc_aa_config);
3575 /* R_028804_DB_EQAA */
3576 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3577 db_eqaa);
3578 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3579 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3580 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3581
3582 if (initial_cdw != cs->current.cdw) {
3583 sctx->context_roll = true;
3584
3585 /* GFX9: Flush DFSM when the AA mode changes. */
3586 if (sctx->screen->dfsm_allowed) {
3587 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3588 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3589 }
3590 }
3591 }
3592
3593 void si_update_ps_iter_samples(struct si_context *sctx)
3594 {
3595 if (sctx->framebuffer.nr_samples > 1)
3596 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3597 if (sctx->screen->dpbb_allowed)
3598 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3599 }
3600
3601 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3602 {
3603 struct si_context *sctx = (struct si_context *)ctx;
3604
3605 /* The hardware can only do sample shading with 2^n samples. */
3606 min_samples = util_next_power_of_two(min_samples);
3607
3608 if (sctx->ps_iter_samples == min_samples)
3609 return;
3610
3611 sctx->ps_iter_samples = min_samples;
3612 sctx->do_update_shaders = true;
3613
3614 si_update_ps_iter_samples(sctx);
3615 }
3616
3617 /*
3618 * Samplers
3619 */
3620
3621 /**
3622 * Build the sampler view descriptor for a buffer texture.
3623 * @param state 256-bit descriptor; only the high 128 bits are filled in
3624 */
3625 void
3626 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3627 enum pipe_format format,
3628 unsigned offset, unsigned size,
3629 uint32_t *state)
3630 {
3631 const struct util_format_description *desc;
3632 int first_non_void;
3633 unsigned stride;
3634 unsigned num_records;
3635 unsigned num_format, data_format;
3636
3637 desc = util_format_description(format);
3638 first_non_void = util_format_get_first_non_void_channel(format);
3639 stride = desc->block.bits / 8;
3640 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3641 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3642
3643 num_records = size / stride;
3644 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3645
3646 /* The NUM_RECORDS field has a different meaning depending on the chip,
3647 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3648 *
3649 * GFX6-GFX7:
3650 * - If STRIDE == 0, it's in byte units.
3651 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3652 *
3653 * GFX8:
3654 * - For SMEM and STRIDE == 0, it's in byte units.
3655 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3656 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3657 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3658 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3659 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3660 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3661 * That way the same descriptor can be used by both SMEM and VMEM.
3662 *
3663 * GFX9:
3664 * - For SMEM and STRIDE == 0, it's in byte units.
3665 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3666 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3667 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3668 */
3669 if (screen->info.chip_class >= GFX9 && HAVE_LLVM < 0x0800)
3670 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3671 * from STRIDE to bytes. This works around it by setting
3672 * NUM_RECORDS to at least the size of one element, so that
3673 * the first element is readable when IDXEN == 0.
3674 */
3675 num_records = num_records ? MAX2(num_records, stride) : 0;
3676 else if (screen->info.chip_class == GFX8)
3677 num_records *= stride;
3678
3679 state[4] = 0;
3680 state[5] = S_008F04_STRIDE(stride);
3681 state[6] = num_records;
3682 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3683 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3684 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3685 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3686 S_008F0C_NUM_FORMAT(num_format) |
3687 S_008F0C_DATA_FORMAT(data_format);
3688 }
3689
3690 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3691 {
3692 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3693
3694 if (swizzle[3] == PIPE_SWIZZLE_X) {
3695 /* For the pre-defined border color values (white, opaque
3696 * black, transparent black), the only thing that matters is
3697 * that the alpha channel winds up in the correct place
3698 * (because the RGB channels are all the same) so either of
3699 * these enumerations will work.
3700 */
3701 if (swizzle[2] == PIPE_SWIZZLE_Y)
3702 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3703 else
3704 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3705 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3706 if (swizzle[1] == PIPE_SWIZZLE_Y)
3707 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3708 else
3709 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3710 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3711 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3712 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3713 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3714 }
3715
3716 return bc_swizzle;
3717 }
3718
3719 /**
3720 * Build the sampler view descriptor for a texture.
3721 */
3722 void
3723 si_make_texture_descriptor(struct si_screen *screen,
3724 struct si_texture *tex,
3725 bool sampler,
3726 enum pipe_texture_target target,
3727 enum pipe_format pipe_format,
3728 const unsigned char state_swizzle[4],
3729 unsigned first_level, unsigned last_level,
3730 unsigned first_layer, unsigned last_layer,
3731 unsigned width, unsigned height, unsigned depth,
3732 uint32_t *state,
3733 uint32_t *fmask_state)
3734 {
3735 struct pipe_resource *res = &tex->buffer.b.b;
3736 const struct util_format_description *desc;
3737 unsigned char swizzle[4];
3738 int first_non_void;
3739 unsigned num_format, data_format, type, num_samples;
3740 uint64_t va;
3741
3742 desc = util_format_description(pipe_format);
3743
3744 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3745 MAX2(1, res->nr_samples) :
3746 MAX2(1, res->nr_storage_samples);
3747
3748 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3749 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3750 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3751 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3752
3753 switch (pipe_format) {
3754 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3755 case PIPE_FORMAT_X32_S8X24_UINT:
3756 case PIPE_FORMAT_X8Z24_UNORM:
3757 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3758 break;
3759 case PIPE_FORMAT_X24S8_UINT:
3760 /*
3761 * X24S8 is implemented as an 8_8_8_8 data format, to
3762 * fix texture gathers. This affects at least
3763 * GL45-CTS.texture_cube_map_array.sampling on GFX8.
3764 */
3765 if (screen->info.chip_class <= GFX8)
3766 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3767 else
3768 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3769 break;
3770 default:
3771 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3772 }
3773 } else {
3774 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3775 }
3776
3777 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3778
3779 switch (pipe_format) {
3780 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3781 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3782 break;
3783 default:
3784 if (first_non_void < 0) {
3785 if (util_format_is_compressed(pipe_format)) {
3786 switch (pipe_format) {
3787 case PIPE_FORMAT_DXT1_SRGB:
3788 case PIPE_FORMAT_DXT1_SRGBA:
3789 case PIPE_FORMAT_DXT3_SRGBA:
3790 case PIPE_FORMAT_DXT5_SRGBA:
3791 case PIPE_FORMAT_BPTC_SRGBA:
3792 case PIPE_FORMAT_ETC2_SRGB8:
3793 case PIPE_FORMAT_ETC2_SRGB8A1:
3794 case PIPE_FORMAT_ETC2_SRGBA8:
3795 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3796 break;
3797 case PIPE_FORMAT_RGTC1_SNORM:
3798 case PIPE_FORMAT_LATC1_SNORM:
3799 case PIPE_FORMAT_RGTC2_SNORM:
3800 case PIPE_FORMAT_LATC2_SNORM:
3801 case PIPE_FORMAT_ETC2_R11_SNORM:
3802 case PIPE_FORMAT_ETC2_RG11_SNORM:
3803 /* implies float, so use SNORM/UNORM to determine
3804 whether data is signed or not */
3805 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3806 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3807 break;
3808 default:
3809 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3810 break;
3811 }
3812 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3813 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3814 } else {
3815 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3816 }
3817 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3818 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3819 } else {
3820 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3821
3822 switch (desc->channel[first_non_void].type) {
3823 case UTIL_FORMAT_TYPE_FLOAT:
3824 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3825 break;
3826 case UTIL_FORMAT_TYPE_SIGNED:
3827 if (desc->channel[first_non_void].normalized)
3828 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3829 else if (desc->channel[first_non_void].pure_integer)
3830 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3831 else
3832 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3833 break;
3834 case UTIL_FORMAT_TYPE_UNSIGNED:
3835 if (desc->channel[first_non_void].normalized)
3836 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3837 else if (desc->channel[first_non_void].pure_integer)
3838 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3839 else
3840 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3841 }
3842 }
3843 }
3844
3845 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3846 if (data_format == ~0) {
3847 data_format = 0;
3848 }
3849
3850 /* S8 with Z32 HTILE needs a special format. */
3851 if (screen->info.chip_class >= GFX9 &&
3852 pipe_format == PIPE_FORMAT_S8_UINT &&
3853 tex->tc_compatible_htile)
3854 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3855
3856 if (!sampler &&
3857 (res->target == PIPE_TEXTURE_CUBE ||
3858 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3859 (screen->info.chip_class <= GFX8 &&
3860 res->target == PIPE_TEXTURE_3D))) {
3861 /* For the purpose of shader images, treat cube maps and 3D
3862 * textures as 2D arrays. For 3D textures, the address
3863 * calculations for mipmaps are different, so we rely on the
3864 * caller to effectively disable mipmaps.
3865 */
3866 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3867
3868 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3869 } else {
3870 type = si_tex_dim(screen, tex, target, num_samples);
3871 }
3872
3873 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3874 height = 1;
3875 depth = res->array_size;
3876 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3877 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3878 if (sampler || res->target != PIPE_TEXTURE_3D)
3879 depth = res->array_size;
3880 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3881 depth = res->array_size / 6;
3882
3883 state[0] = 0;
3884 state[1] = (S_008F14_DATA_FORMAT(data_format) |
3885 S_008F14_NUM_FORMAT(num_format));
3886 state[2] = (S_008F18_WIDTH(width - 1) |
3887 S_008F18_HEIGHT(height - 1) |
3888 S_008F18_PERF_MOD(4));
3889 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3890 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3891 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3892 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3893 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3894 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3895 util_logbase2(num_samples) :
3896 last_level) |
3897 S_008F1C_TYPE(type));
3898 state[4] = 0;
3899 state[5] = S_008F24_BASE_ARRAY(first_layer);
3900 state[6] = 0;
3901 state[7] = 0;
3902
3903 if (screen->info.chip_class >= GFX9) {
3904 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3905
3906 /* Depth is the the last accessible layer on Gfx9.
3907 * The hw doesn't need to know the total number of layers.
3908 */
3909 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3910 state[4] |= S_008F20_DEPTH(depth - 1);
3911 else
3912 state[4] |= S_008F20_DEPTH(last_layer);
3913
3914 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3915 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3916 util_logbase2(num_samples) :
3917 tex->buffer.b.b.last_level);
3918 } else {
3919 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3920 state[4] |= S_008F20_DEPTH(depth - 1);
3921 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3922 }
3923
3924 if (tex->dcc_offset) {
3925 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3926 } else {
3927 /* The last dword is unused by hw. The shader uses it to clear
3928 * bits in the first dword of sampler state.
3929 */
3930 if (screen->info.chip_class <= GFX7 && res->nr_samples <= 1) {
3931 if (first_level == last_level)
3932 state[7] = C_008F30_MAX_ANISO_RATIO;
3933 else
3934 state[7] = 0xffffffff;
3935 }
3936 }
3937
3938 /* Initialize the sampler view for FMASK. */
3939 if (tex->fmask_offset) {
3940 uint32_t data_format, num_format;
3941
3942 va = tex->buffer.gpu_address + tex->fmask_offset;
3943
3944 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3945 if (screen->info.chip_class >= GFX9) {
3946 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3947 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3948 case FMASK(2,1):
3949 num_format = V_008F14_IMG_FMASK_8_2_1;
3950 break;
3951 case FMASK(2,2):
3952 num_format = V_008F14_IMG_FMASK_8_2_2;
3953 break;
3954 case FMASK(4,1):
3955 num_format = V_008F14_IMG_FMASK_8_4_1;
3956 break;
3957 case FMASK(4,2):
3958 num_format = V_008F14_IMG_FMASK_8_4_2;
3959 break;
3960 case FMASK(4,4):
3961 num_format = V_008F14_IMG_FMASK_8_4_4;
3962 break;
3963 case FMASK(8,1):
3964 num_format = V_008F14_IMG_FMASK_8_8_1;
3965 break;
3966 case FMASK(8,2):
3967 num_format = V_008F14_IMG_FMASK_16_8_2;
3968 break;
3969 case FMASK(8,4):
3970 num_format = V_008F14_IMG_FMASK_32_8_4;
3971 break;
3972 case FMASK(8,8):
3973 num_format = V_008F14_IMG_FMASK_32_8_8;
3974 break;
3975 case FMASK(16,1):
3976 num_format = V_008F14_IMG_FMASK_16_16_1;
3977 break;
3978 case FMASK(16,2):
3979 num_format = V_008F14_IMG_FMASK_32_16_2;
3980 break;
3981 case FMASK(16,4):
3982 num_format = V_008F14_IMG_FMASK_64_16_4;
3983 break;
3984 case FMASK(16,8):
3985 num_format = V_008F14_IMG_FMASK_64_16_8;
3986 break;
3987 default:
3988 unreachable("invalid nr_samples");
3989 }
3990 } else {
3991 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3992 case FMASK(2,1):
3993 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3994 break;
3995 case FMASK(2,2):
3996 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3997 break;
3998 case FMASK(4,1):
3999 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
4000 break;
4001 case FMASK(4,2):
4002 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
4003 break;
4004 case FMASK(4,4):
4005 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
4006 break;
4007 case FMASK(8,1):
4008 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
4009 break;
4010 case FMASK(8,2):
4011 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
4012 break;
4013 case FMASK(8,4):
4014 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
4015 break;
4016 case FMASK(8,8):
4017 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
4018 break;
4019 case FMASK(16,1):
4020 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
4021 break;
4022 case FMASK(16,2):
4023 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
4024 break;
4025 case FMASK(16,4):
4026 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
4027 break;
4028 case FMASK(16,8):
4029 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
4030 break;
4031 default:
4032 unreachable("invalid nr_samples");
4033 }
4034 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
4035 }
4036 #undef FMASK
4037
4038 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
4039 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
4040 S_008F14_DATA_FORMAT(data_format) |
4041 S_008F14_NUM_FORMAT(num_format);
4042 fmask_state[2] = S_008F18_WIDTH(width - 1) |
4043 S_008F18_HEIGHT(height - 1);
4044 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
4045 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
4046 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
4047 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
4048 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
4049 fmask_state[4] = 0;
4050 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
4051 fmask_state[6] = 0;
4052 fmask_state[7] = 0;
4053
4054 if (screen->info.chip_class >= GFX9) {
4055 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4056 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4057 S_008F20_PITCH(tex->surface.u.gfx9.fmask.epitch);
4058 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4059 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4060 } else {
4061 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4062 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4063 S_008F20_PITCH(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4064 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4065 }
4066 }
4067 }
4068
4069 /**
4070 * Create a sampler view.
4071 *
4072 * @param ctx context
4073 * @param texture texture
4074 * @param state sampler view template
4075 * @param width0 width0 override (for compressed textures as int)
4076 * @param height0 height0 override (for compressed textures as int)
4077 * @param force_level set the base address to the level (for compressed textures)
4078 */
4079 struct pipe_sampler_view *
4080 si_create_sampler_view_custom(struct pipe_context *ctx,
4081 struct pipe_resource *texture,
4082 const struct pipe_sampler_view *state,
4083 unsigned width0, unsigned height0,
4084 unsigned force_level)
4085 {
4086 struct si_context *sctx = (struct si_context*)ctx;
4087 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4088 struct si_texture *tex = (struct si_texture*)texture;
4089 unsigned base_level, first_level, last_level;
4090 unsigned char state_swizzle[4];
4091 unsigned height, depth, width;
4092 unsigned last_layer = state->u.tex.last_layer;
4093 enum pipe_format pipe_format;
4094 const struct legacy_surf_level *surflevel;
4095
4096 if (!view)
4097 return NULL;
4098
4099 /* initialize base object */
4100 view->base = *state;
4101 view->base.texture = NULL;
4102 view->base.reference.count = 1;
4103 view->base.context = ctx;
4104
4105 assert(texture);
4106 pipe_resource_reference(&view->base.texture, texture);
4107
4108 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4109 state->format == PIPE_FORMAT_S8X24_UINT ||
4110 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4111 state->format == PIPE_FORMAT_S8_UINT)
4112 view->is_stencil_sampler = true;
4113
4114 /* Buffer resource. */
4115 if (texture->target == PIPE_BUFFER) {
4116 si_make_buffer_descriptor(sctx->screen,
4117 si_resource(texture),
4118 state->format,
4119 state->u.buf.offset,
4120 state->u.buf.size,
4121 view->state);
4122 return &view->base;
4123 }
4124
4125 state_swizzle[0] = state->swizzle_r;
4126 state_swizzle[1] = state->swizzle_g;
4127 state_swizzle[2] = state->swizzle_b;
4128 state_swizzle[3] = state->swizzle_a;
4129
4130 base_level = 0;
4131 first_level = state->u.tex.first_level;
4132 last_level = state->u.tex.last_level;
4133 width = width0;
4134 height = height0;
4135 depth = texture->depth0;
4136
4137 if (sctx->chip_class <= GFX8 && force_level) {
4138 assert(force_level == first_level &&
4139 force_level == last_level);
4140 base_level = force_level;
4141 first_level = 0;
4142 last_level = 0;
4143 width = u_minify(width, force_level);
4144 height = u_minify(height, force_level);
4145 depth = u_minify(depth, force_level);
4146 }
4147
4148 /* This is not needed if state trackers set last_layer correctly. */
4149 if (state->target == PIPE_TEXTURE_1D ||
4150 state->target == PIPE_TEXTURE_2D ||
4151 state->target == PIPE_TEXTURE_RECT ||
4152 state->target == PIPE_TEXTURE_CUBE)
4153 last_layer = state->u.tex.first_layer;
4154
4155 /* Texturing with separate depth and stencil. */
4156 pipe_format = state->format;
4157
4158 /* Depth/stencil texturing sometimes needs separate texture. */
4159 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4160 if (!tex->flushed_depth_texture &&
4161 !si_init_flushed_depth_texture(ctx, texture)) {
4162 pipe_resource_reference(&view->base.texture, NULL);
4163 FREE(view);
4164 return NULL;
4165 }
4166
4167 assert(tex->flushed_depth_texture);
4168
4169 /* Override format for the case where the flushed texture
4170 * contains only Z or only S.
4171 */
4172 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4173 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4174
4175 tex = tex->flushed_depth_texture;
4176 }
4177
4178 surflevel = tex->surface.u.legacy.level;
4179
4180 if (tex->db_compatible) {
4181 if (!view->is_stencil_sampler)
4182 pipe_format = tex->db_render_format;
4183
4184 switch (pipe_format) {
4185 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4186 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4187 break;
4188 case PIPE_FORMAT_X8Z24_UNORM:
4189 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4190 /* Z24 is always stored like this for DB
4191 * compatibility.
4192 */
4193 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4194 break;
4195 case PIPE_FORMAT_X24S8_UINT:
4196 case PIPE_FORMAT_S8X24_UINT:
4197 case PIPE_FORMAT_X32_S8X24_UINT:
4198 pipe_format = PIPE_FORMAT_S8_UINT;
4199 surflevel = tex->surface.u.legacy.stencil_level;
4200 break;
4201 default:;
4202 }
4203 }
4204
4205 view->dcc_incompatible =
4206 vi_dcc_formats_are_incompatible(texture,
4207 state->u.tex.first_level,
4208 state->format);
4209
4210 si_make_texture_descriptor(sctx->screen, tex, true,
4211 state->target, pipe_format, state_swizzle,
4212 first_level, last_level,
4213 state->u.tex.first_layer, last_layer,
4214 width, height, depth,
4215 view->state, view->fmask_state);
4216
4217 unsigned num_format = G_008F14_NUM_FORMAT(view->state[1]);
4218 view->is_integer =
4219 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4220 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4221 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4222 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4223 view->base_level_info = &surflevel[base_level];
4224 view->base_level = base_level;
4225 view->block_width = util_format_get_blockwidth(pipe_format);
4226 return &view->base;
4227 }
4228
4229 static struct pipe_sampler_view *
4230 si_create_sampler_view(struct pipe_context *ctx,
4231 struct pipe_resource *texture,
4232 const struct pipe_sampler_view *state)
4233 {
4234 return si_create_sampler_view_custom(ctx, texture, state,
4235 texture ? texture->width0 : 0,
4236 texture ? texture->height0 : 0, 0);
4237 }
4238
4239 static void si_sampler_view_destroy(struct pipe_context *ctx,
4240 struct pipe_sampler_view *state)
4241 {
4242 struct si_sampler_view *view = (struct si_sampler_view *)state;
4243
4244 pipe_resource_reference(&state->texture, NULL);
4245 FREE(view);
4246 }
4247
4248 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4249 {
4250 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4251 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4252 (linear_filter &&
4253 (wrap == PIPE_TEX_WRAP_CLAMP ||
4254 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4255 }
4256
4257 static uint32_t si_translate_border_color(struct si_context *sctx,
4258 const struct pipe_sampler_state *state,
4259 const union pipe_color_union *color,
4260 bool is_integer)
4261 {
4262 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4263 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4264
4265 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4266 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4267 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4268 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4269
4270 #define simple_border_types(elt) \
4271 do { \
4272 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4273 color->elt[2] == 0 && color->elt[3] == 0) \
4274 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4275 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4276 color->elt[2] == 0 && color->elt[3] == 1) \
4277 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4278 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4279 color->elt[2] == 1 && color->elt[3] == 1) \
4280 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4281 } while (false)
4282
4283 if (is_integer)
4284 simple_border_types(ui);
4285 else
4286 simple_border_types(f);
4287
4288 #undef simple_border_types
4289
4290 int i;
4291
4292 /* Check if the border has been uploaded already. */
4293 for (i = 0; i < sctx->border_color_count; i++)
4294 if (memcmp(&sctx->border_color_table[i], color,
4295 sizeof(*color)) == 0)
4296 break;
4297
4298 if (i >= SI_MAX_BORDER_COLORS) {
4299 /* Getting 4096 unique border colors is very unlikely. */
4300 fprintf(stderr, "radeonsi: The border color table is full. "
4301 "Any new border colors will be just black. "
4302 "Please file a bug.\n");
4303 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4304 }
4305
4306 if (i == sctx->border_color_count) {
4307 /* Upload a new border color. */
4308 memcpy(&sctx->border_color_table[i], color,
4309 sizeof(*color));
4310 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4311 color, sizeof(*color));
4312 sctx->border_color_count++;
4313 }
4314
4315 return S_008F3C_BORDER_COLOR_PTR(i) |
4316 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4317 }
4318
4319 static inline int S_FIXED(float value, unsigned frac_bits)
4320 {
4321 return value * (1 << frac_bits);
4322 }
4323
4324 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4325 {
4326 if (filter == PIPE_TEX_FILTER_LINEAR)
4327 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4328 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4329 else
4330 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4331 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4332 }
4333
4334 static inline unsigned si_tex_aniso_filter(unsigned filter)
4335 {
4336 if (filter < 2)
4337 return 0;
4338 if (filter < 4)
4339 return 1;
4340 if (filter < 8)
4341 return 2;
4342 if (filter < 16)
4343 return 3;
4344 return 4;
4345 }
4346
4347 static void *si_create_sampler_state(struct pipe_context *ctx,
4348 const struct pipe_sampler_state *state)
4349 {
4350 struct si_context *sctx = (struct si_context *)ctx;
4351 struct si_screen *sscreen = sctx->screen;
4352 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4353 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4354 : state->max_anisotropy;
4355 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4356 union pipe_color_union clamped_border_color;
4357
4358 if (!rstate) {
4359 return NULL;
4360 }
4361
4362 #ifndef NDEBUG
4363 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4364 #endif
4365 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4366 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4367 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4368 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4369 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4370 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4371 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4372 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4373 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4374 S_008F30_COMPAT_MODE(sctx->chip_class >= GFX8));
4375 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4376 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4377 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4378 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4379 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4380 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4381 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4382 S_008F38_MIP_POINT_PRECLAMP(0) |
4383 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= GFX8) |
4384 S_008F38_FILTER_PREC_FIX(1) |
4385 S_008F38_ANISO_OVERRIDE_GFX6(sctx->chip_class >= GFX8));
4386 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4387
4388 /* Create sampler resource for integer textures. */
4389 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4390 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4391
4392 /* Create sampler resource for upgraded depth textures. */
4393 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4394
4395 for (unsigned i = 0; i < 4; ++i) {
4396 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4397 * when the border color is 1.0. */
4398 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4399 }
4400
4401 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4402 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4403 else
4404 rstate->upgraded_depth_val[3] =
4405 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4406 S_008F3C_UPGRADED_DEPTH(1);
4407
4408 return rstate;
4409 }
4410
4411 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4412 {
4413 struct si_context *sctx = (struct si_context *)ctx;
4414
4415 if (sctx->sample_mask == (uint16_t)sample_mask)
4416 return;
4417
4418 sctx->sample_mask = sample_mask;
4419 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4420 }
4421
4422 static void si_emit_sample_mask(struct si_context *sctx)
4423 {
4424 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4425 unsigned mask = sctx->sample_mask;
4426
4427 /* Needed for line and polygon smoothing as well as for the Polaris
4428 * small primitive filter. We expect the state tracker to take care of
4429 * this for us.
4430 */
4431 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4432 (mask & 1 && sctx->blitter->running));
4433
4434 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4435 radeon_emit(cs, mask | (mask << 16));
4436 radeon_emit(cs, mask | (mask << 16));
4437 }
4438
4439 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4440 {
4441 #ifndef NDEBUG
4442 struct si_sampler_state *s = state;
4443
4444 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4445 s->magic = 0;
4446 #endif
4447 free(state);
4448 }
4449
4450 /*
4451 * Vertex elements & buffers
4452 */
4453
4454 struct si_fast_udiv_info32
4455 si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4456 {
4457 struct util_fast_udiv_info info =
4458 util_compute_fast_udiv_info(D, num_bits, 32);
4459
4460 struct si_fast_udiv_info32 result = {
4461 info.multiplier,
4462 info.pre_shift,
4463 info.post_shift,
4464 info.increment,
4465 };
4466 return result;
4467 }
4468
4469 static void *si_create_vertex_elements(struct pipe_context *ctx,
4470 unsigned count,
4471 const struct pipe_vertex_element *elements)
4472 {
4473 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4474 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4475 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4476 struct si_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4477 STATIC_ASSERT(sizeof(struct si_fast_udiv_info32) == 16);
4478 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4479 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4480 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4481 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4482 int i;
4483
4484 assert(count <= SI_MAX_ATTRIBS);
4485 if (!v)
4486 return NULL;
4487
4488 v->count = count;
4489 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4490
4491 for (i = 0; i < count; ++i) {
4492 const struct util_format_description *desc;
4493 const struct util_format_channel_description *channel;
4494 int first_non_void;
4495 unsigned vbo_index = elements[i].vertex_buffer_index;
4496
4497 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4498 FREE(v);
4499 return NULL;
4500 }
4501
4502 unsigned instance_divisor = elements[i].instance_divisor;
4503 if (instance_divisor) {
4504 v->uses_instance_divisors = true;
4505
4506 if (instance_divisor == 1) {
4507 v->instance_divisor_is_one |= 1u << i;
4508 } else {
4509 v->instance_divisor_is_fetched |= 1u << i;
4510 divisor_factors[i] =
4511 si_compute_fast_udiv_info32(instance_divisor, 32);
4512 }
4513 }
4514
4515 if (!used[vbo_index]) {
4516 v->first_vb_use_mask |= 1 << i;
4517 used[vbo_index] = true;
4518 }
4519
4520 desc = util_format_description(elements[i].src_format);
4521 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4522 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4523
4524 v->format_size[i] = desc->block.bits / 8;
4525 v->src_offset[i] = elements[i].src_offset;
4526 v->vertex_buffer_index[i] = vbo_index;
4527
4528 bool always_fix = false;
4529 union si_vs_fix_fetch fix_fetch;
4530 unsigned log_hw_load_size; /* the load element size as seen by the hardware */
4531
4532 fix_fetch.bits = 0;
4533 log_hw_load_size = MIN2(2, util_logbase2(desc->block.bits) - 3);
4534
4535 if (channel) {
4536 switch (channel->type) {
4537 case UTIL_FORMAT_TYPE_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4538 case UTIL_FORMAT_TYPE_FIXED: fix_fetch.u.format = AC_FETCH_FORMAT_FIXED; break;
4539 case UTIL_FORMAT_TYPE_SIGNED: {
4540 if (channel->pure_integer)
4541 fix_fetch.u.format = AC_FETCH_FORMAT_SINT;
4542 else if (channel->normalized)
4543 fix_fetch.u.format = AC_FETCH_FORMAT_SNORM;
4544 else
4545 fix_fetch.u.format = AC_FETCH_FORMAT_SSCALED;
4546 break;
4547 }
4548 case UTIL_FORMAT_TYPE_UNSIGNED: {
4549 if (channel->pure_integer)
4550 fix_fetch.u.format = AC_FETCH_FORMAT_UINT;
4551 else if (channel->normalized)
4552 fix_fetch.u.format = AC_FETCH_FORMAT_UNORM;
4553 else
4554 fix_fetch.u.format = AC_FETCH_FORMAT_USCALED;
4555 break;
4556 }
4557 default: unreachable("bad format type");
4558 }
4559 } else {
4560 switch (elements[i].src_format) {
4561 case PIPE_FORMAT_R11G11B10_FLOAT: fix_fetch.u.format = AC_FETCH_FORMAT_FLOAT; break;
4562 default: unreachable("bad other format");
4563 }
4564 }
4565
4566 if (desc->channel[0].size == 10) {
4567 fix_fetch.u.log_size = 3; /* special encoding for 2_10_10_10 */
4568 log_hw_load_size = 2;
4569
4570 /* The hardware always treats the 2-bit alpha channel as
4571 * unsigned, so a shader workaround is needed. The affected
4572 * chips are GFX8 and older except Stoney (GFX8.1).
4573 */
4574 always_fix = sscreen->info.chip_class <= GFX8 &&
4575 sscreen->info.family != CHIP_STONEY &&
4576 channel->type == UTIL_FORMAT_TYPE_SIGNED;
4577 } else if (elements[i].src_format == PIPE_FORMAT_R11G11B10_FLOAT) {
4578 fix_fetch.u.log_size = 3; /* special encoding */
4579 fix_fetch.u.format = AC_FETCH_FORMAT_FIXED;
4580 log_hw_load_size = 2;
4581 } else {
4582 fix_fetch.u.log_size = util_logbase2(channel->size) - 3;
4583 fix_fetch.u.num_channels_m1 = desc->nr_channels - 1;
4584
4585 /* Always fix up:
4586 * - doubles (multiple loads + truncate to float)
4587 * - 32-bit requiring a conversion
4588 */
4589 always_fix =
4590 (fix_fetch.u.log_size == 3) ||
4591 (fix_fetch.u.log_size == 2 &&
4592 fix_fetch.u.format != AC_FETCH_FORMAT_FLOAT &&
4593 fix_fetch.u.format != AC_FETCH_FORMAT_UINT &&
4594 fix_fetch.u.format != AC_FETCH_FORMAT_SINT);
4595
4596 /* Also fixup 8_8_8 and 16_16_16. */
4597 if (desc->nr_channels == 3 && fix_fetch.u.log_size <= 1) {
4598 always_fix = true;
4599 log_hw_load_size = fix_fetch.u.log_size;
4600 }
4601 }
4602
4603 if (desc->swizzle[0] != PIPE_SWIZZLE_X) {
4604 assert(desc->swizzle[0] == PIPE_SWIZZLE_Z &&
4605 (desc->swizzle[2] == PIPE_SWIZZLE_X || desc->swizzle[2] == PIPE_SWIZZLE_0));
4606 fix_fetch.u.reverse = 1;
4607 }
4608
4609 /* Force the workaround for unaligned access here already if the
4610 * offset relative to the vertex buffer base is unaligned.
4611 *
4612 * There is a theoretical case in which this is too conservative:
4613 * if the vertex buffer's offset is also unaligned in just the
4614 * right way, we end up with an aligned address after all.
4615 * However, this case should be extremely rare in practice (it
4616 * won't happen in well-behaved applications), and taking it
4617 * into account would complicate the fast path (where everything
4618 * is nicely aligned).
4619 */
4620 bool check_alignment = log_hw_load_size >= 1 && sscreen->info.chip_class == GFX6;
4621 bool opencode = sscreen->options.vs_fetch_always_opencode;
4622
4623 if (check_alignment &&
4624 (elements[i].src_offset & ((1 << log_hw_load_size) - 1)) != 0)
4625 opencode = true;
4626
4627 if (always_fix || check_alignment || opencode)
4628 v->fix_fetch[i] = fix_fetch.bits;
4629
4630 if (opencode)
4631 v->fix_fetch_opencode |= 1 << i;
4632 if (opencode || always_fix)
4633 v->fix_fetch_always |= 1 << i;
4634
4635 if (check_alignment && !opencode) {
4636 assert(log_hw_load_size == 1 || log_hw_load_size == 2);
4637
4638 v->fix_fetch_unaligned |= 1 << i;
4639 v->hw_load_is_dword |= (log_hw_load_size - 1) << i;
4640 v->vb_alignment_check_mask |= 1 << vbo_index;
4641 }
4642
4643 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
4644 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
4645 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
4646 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3]));
4647
4648 unsigned data_format, num_format;
4649 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4650 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4651 v->rsrc_word3[i] |= S_008F0C_NUM_FORMAT(num_format) |
4652 S_008F0C_DATA_FORMAT(data_format);
4653 }
4654
4655 if (v->instance_divisor_is_fetched) {
4656 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4657
4658 v->instance_divisor_factor_buffer =
4659 (struct si_resource*)
4660 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4661 num_divisors * sizeof(divisor_factors[0]));
4662 if (!v->instance_divisor_factor_buffer) {
4663 FREE(v);
4664 return NULL;
4665 }
4666 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4667 NULL, PIPE_TRANSFER_WRITE);
4668 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4669 }
4670 return v;
4671 }
4672
4673 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4674 {
4675 struct si_context *sctx = (struct si_context *)ctx;
4676 struct si_vertex_elements *old = sctx->vertex_elements;
4677 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4678
4679 sctx->vertex_elements = v;
4680 sctx->vertex_buffers_dirty = true;
4681
4682 if (v &&
4683 (!old ||
4684 old->count != v->count ||
4685 old->uses_instance_divisors != v->uses_instance_divisors ||
4686 /* we don't check which divisors changed */
4687 v->uses_instance_divisors ||
4688 (old->vb_alignment_check_mask ^ v->vb_alignment_check_mask) & sctx->vertex_buffer_unaligned ||
4689 ((v->vb_alignment_check_mask & sctx->vertex_buffer_unaligned) &&
4690 memcmp(old->vertex_buffer_index, v->vertex_buffer_index,
4691 sizeof(v->vertex_buffer_index[0]) * v->count)) ||
4692 /* fix_fetch_{always,opencode,unaligned} and hw_load_is_dword are
4693 * functions of fix_fetch and the src_offset alignment.
4694 * If they change and fix_fetch doesn't, it must be due to different
4695 * src_offset alignment, which is reflected in fix_fetch_opencode. */
4696 old->fix_fetch_opencode != v->fix_fetch_opencode ||
4697 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4698 sctx->do_update_shaders = true;
4699
4700 if (v && v->instance_divisor_is_fetched) {
4701 struct pipe_constant_buffer cb;
4702
4703 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4704 cb.user_buffer = NULL;
4705 cb.buffer_offset = 0;
4706 cb.buffer_size = 0xffffffff;
4707 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4708 }
4709 }
4710
4711 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4712 {
4713 struct si_context *sctx = (struct si_context *)ctx;
4714 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4715
4716 if (sctx->vertex_elements == state)
4717 sctx->vertex_elements = NULL;
4718 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4719 FREE(state);
4720 }
4721
4722 static void si_set_vertex_buffers(struct pipe_context *ctx,
4723 unsigned start_slot, unsigned count,
4724 const struct pipe_vertex_buffer *buffers)
4725 {
4726 struct si_context *sctx = (struct si_context *)ctx;
4727 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4728 uint32_t orig_unaligned = sctx->vertex_buffer_unaligned;
4729 uint32_t unaligned = orig_unaligned;
4730 int i;
4731
4732 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4733
4734 if (buffers) {
4735 for (i = 0; i < count; i++) {
4736 const struct pipe_vertex_buffer *src = buffers + i;
4737 struct pipe_vertex_buffer *dsti = dst + i;
4738 struct pipe_resource *buf = src->buffer.resource;
4739
4740 pipe_resource_reference(&dsti->buffer.resource, buf);
4741 dsti->buffer_offset = src->buffer_offset;
4742 dsti->stride = src->stride;
4743 if (dsti->buffer_offset & 3 || dsti->stride & 3)
4744 unaligned |= 1 << (start_slot + i);
4745 else
4746 unaligned &= ~(1 << (start_slot + i));
4747
4748 si_context_add_resource_size(sctx, buf);
4749 if (buf)
4750 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4751 }
4752 } else {
4753 for (i = 0; i < count; i++) {
4754 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4755 }
4756 unaligned &= ~u_bit_consecutive(start_slot, count);
4757 }
4758 sctx->vertex_buffers_dirty = true;
4759 sctx->vertex_buffer_unaligned = unaligned;
4760
4761 /* Check whether alignment may have changed in a way that requires
4762 * shader changes. This check is conservative: a vertex buffer can only
4763 * trigger a shader change if the misalignment amount changes (e.g.
4764 * from byte-aligned to short-aligned), but we only keep track of
4765 * whether buffers are at least dword-aligned, since that should always
4766 * be the case in well-behaved applications anyway.
4767 */
4768 if (sctx->vertex_elements &&
4769 (sctx->vertex_elements->vb_alignment_check_mask &
4770 (unaligned | orig_unaligned) & u_bit_consecutive(start_slot, count)))
4771 sctx->do_update_shaders = true;
4772 }
4773
4774 /*
4775 * Misc
4776 */
4777
4778 static void si_set_tess_state(struct pipe_context *ctx,
4779 const float default_outer_level[4],
4780 const float default_inner_level[2])
4781 {
4782 struct si_context *sctx = (struct si_context *)ctx;
4783 struct pipe_constant_buffer cb;
4784 float array[8];
4785
4786 memcpy(array, default_outer_level, sizeof(float) * 4);
4787 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4788
4789 cb.buffer = NULL;
4790 cb.user_buffer = NULL;
4791 cb.buffer_size = sizeof(array);
4792
4793 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
4794 (void*)array, sizeof(array),
4795 &cb.buffer_offset);
4796
4797 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4798 pipe_resource_reference(&cb.buffer, NULL);
4799 }
4800
4801 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4802 {
4803 struct si_context *sctx = (struct si_context *)ctx;
4804
4805 si_update_fb_dirtiness_after_rendering(sctx);
4806
4807 /* Multisample surfaces are flushed in si_decompress_textures. */
4808 if (sctx->framebuffer.uncompressed_cb_mask) {
4809 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4810 sctx->framebuffer.CB_has_shader_readable_metadata,
4811 sctx->framebuffer.all_DCC_pipe_aligned);
4812 }
4813 }
4814
4815 /* This only ensures coherency for shader image/buffer stores. */
4816 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4817 {
4818 struct si_context *sctx = (struct si_context *)ctx;
4819
4820 if (!(flags & ~PIPE_BARRIER_UPDATE))
4821 return;
4822
4823 /* Subsequent commands must wait for all shader invocations to
4824 * complete. */
4825 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4826 SI_CONTEXT_CS_PARTIAL_FLUSH;
4827
4828 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4829 sctx->flags |= SI_CONTEXT_INV_SCACHE |
4830 SI_CONTEXT_INV_VCACHE;
4831
4832 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4833 PIPE_BARRIER_SHADER_BUFFER |
4834 PIPE_BARRIER_TEXTURE |
4835 PIPE_BARRIER_IMAGE |
4836 PIPE_BARRIER_STREAMOUT_BUFFER |
4837 PIPE_BARRIER_GLOBAL_BUFFER)) {
4838 /* As far as I can tell, L1 contents are written back to L2
4839 * automatically at end of shader, but the contents of other
4840 * L1 caches might still be stale. */
4841 sctx->flags |= SI_CONTEXT_INV_VCACHE;
4842 }
4843
4844 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4845 /* Indices are read through TC L2 since GFX8.
4846 * L1 isn't used.
4847 */
4848 if (sctx->screen->info.chip_class <= GFX7)
4849 sctx->flags |= SI_CONTEXT_WB_L2;
4850 }
4851
4852 /* MSAA color, any depth and any stencil are flushed in
4853 * si_decompress_textures when needed.
4854 */
4855 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4856 sctx->framebuffer.uncompressed_cb_mask) {
4857 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4858
4859 if (sctx->chip_class <= GFX8)
4860 sctx->flags |= SI_CONTEXT_WB_L2;
4861 }
4862
4863 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4864 if (sctx->screen->info.chip_class <= GFX8 &&
4865 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4866 sctx->flags |= SI_CONTEXT_WB_L2;
4867 }
4868
4869 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4870 {
4871 struct pipe_blend_state blend;
4872
4873 memset(&blend, 0, sizeof(blend));
4874 blend.independent_blend_enable = true;
4875 blend.rt[0].colormask = 0xf;
4876 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4877 }
4878
4879 static void si_init_config(struct si_context *sctx);
4880
4881 void si_init_state_compute_functions(struct si_context *sctx)
4882 {
4883 sctx->b.create_sampler_state = si_create_sampler_state;
4884 sctx->b.delete_sampler_state = si_delete_sampler_state;
4885 sctx->b.create_sampler_view = si_create_sampler_view;
4886 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4887 sctx->b.memory_barrier = si_memory_barrier;
4888 }
4889
4890 void si_init_state_functions(struct si_context *sctx)
4891 {
4892 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4893 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4894 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4895 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4896 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4897 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4898 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4899 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4900 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4901 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4902 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4903
4904 sctx->b.create_blend_state = si_create_blend_state;
4905 sctx->b.bind_blend_state = si_bind_blend_state;
4906 sctx->b.delete_blend_state = si_delete_blend_state;
4907 sctx->b.set_blend_color = si_set_blend_color;
4908
4909 sctx->b.create_rasterizer_state = si_create_rs_state;
4910 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4911 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4912
4913 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4914 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4915 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4916
4917 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4918 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4919 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4920 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4921 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4922
4923 sctx->b.set_clip_state = si_set_clip_state;
4924 sctx->b.set_stencil_ref = si_set_stencil_ref;
4925
4926 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4927
4928 sctx->b.set_sample_mask = si_set_sample_mask;
4929
4930 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4931 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4932 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4933 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4934
4935 sctx->b.texture_barrier = si_texture_barrier;
4936 sctx->b.set_min_samples = si_set_min_samples;
4937 sctx->b.set_tess_state = si_set_tess_state;
4938
4939 sctx->b.set_active_query_state = si_set_active_query_state;
4940
4941 si_init_config(sctx);
4942 }
4943
4944 void si_init_screen_state_functions(struct si_screen *sscreen)
4945 {
4946 sscreen->b.is_format_supported = si_is_format_supported;
4947 }
4948
4949 static void si_set_grbm_gfx_index(struct si_context *sctx,
4950 struct si_pm4_state *pm4, unsigned value)
4951 {
4952 unsigned reg = sctx->chip_class >= GFX7 ? R_030800_GRBM_GFX_INDEX :
4953 R_00802C_GRBM_GFX_INDEX;
4954 si_pm4_set_reg(pm4, reg, value);
4955 }
4956
4957 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4958 struct si_pm4_state *pm4, unsigned se)
4959 {
4960 assert(se == ~0 || se < sctx->screen->info.max_se);
4961 si_set_grbm_gfx_index(sctx, pm4,
4962 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4963 S_030800_SE_INDEX(se)) |
4964 S_030800_SH_BROADCAST_WRITES(1) |
4965 S_030800_INSTANCE_BROADCAST_WRITES(1));
4966 }
4967
4968 static void
4969 si_write_harvested_raster_configs(struct si_context *sctx,
4970 struct si_pm4_state *pm4,
4971 unsigned raster_config,
4972 unsigned raster_config_1)
4973 {
4974 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4975 unsigned raster_config_se[4];
4976 unsigned se;
4977
4978 ac_get_harvested_configs(&sctx->screen->info,
4979 raster_config,
4980 &raster_config_1,
4981 raster_config_se);
4982
4983 for (se = 0; se < num_se; se++) {
4984 si_set_grbm_gfx_index_se(sctx, pm4, se);
4985 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4986 }
4987 si_set_grbm_gfx_index(sctx, pm4, ~0);
4988
4989 if (sctx->chip_class >= GFX7) {
4990 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4991 }
4992 }
4993
4994 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4995 {
4996 struct si_screen *sscreen = sctx->screen;
4997 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4998 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4999 unsigned raster_config = sscreen->pa_sc_raster_config;
5000 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
5001
5002 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
5003 /* Always use the default config when all backends are enabled
5004 * (or when we failed to determine the enabled backends).
5005 */
5006 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
5007 raster_config);
5008 if (sctx->chip_class >= GFX7)
5009 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
5010 raster_config_1);
5011 } else {
5012 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
5013 }
5014 }
5015
5016 static void si_init_config(struct si_context *sctx)
5017 {
5018 struct si_screen *sscreen = sctx->screen;
5019 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
5020 bool has_clear_state = sscreen->has_clear_state;
5021 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
5022
5023 /* GFX6, radeon kernel disabled CLEAR_STATE. */
5024 assert(has_clear_state || sscreen->info.chip_class == GFX6 ||
5025 !sscreen->info.is_amdgpu);
5026
5027 if (!pm4)
5028 return;
5029
5030 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
5031 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
5032 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
5033 si_pm4_cmd_end(pm4, false);
5034
5035 if (has_clear_state) {
5036 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
5037 si_pm4_cmd_add(pm4, 0);
5038 si_pm4_cmd_end(pm4, false);
5039 }
5040
5041 if (sctx->chip_class <= GFX8)
5042 si_set_raster_config(sctx, pm4);
5043
5044 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
5045 if (!has_clear_state)
5046 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
5047
5048 /* FIXME calculate these values somehow ??? */
5049 if (sctx->chip_class <= GFX8) {
5050 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
5051 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
5052 }
5053
5054 if (!has_clear_state) {
5055 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
5056 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
5057 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
5058 }
5059
5060 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
5061 if (!has_clear_state)
5062 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
5063 if (sctx->chip_class < GFX7)
5064 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
5065 S_008A14_CLIP_VTX_REORDER_ENA(1));
5066
5067 /* CLEAR_STATE doesn't clear these correctly on certain generations.
5068 * I don't know why. Deduced by trial and error.
5069 */
5070 if (sctx->chip_class <= GFX7) {
5071 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
5072 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
5073 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
5074 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
5075 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
5076 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
5077 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
5078 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
5079 }
5080
5081 if (!has_clear_state) {
5082 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
5083 S_028230_ER_TRI(0xA) |
5084 S_028230_ER_POINT(0xA) |
5085 S_028230_ER_RECT(0xA) |
5086 /* Required by DX10_DIAMOND_TEST_ENA: */
5087 S_028230_ER_LINE_LR(0x1A) |
5088 S_028230_ER_LINE_RL(0x26) |
5089 S_028230_ER_LINE_TB(0xA) |
5090 S_028230_ER_LINE_BT(0xA));
5091 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
5092 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
5093 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
5094 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
5095 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
5096 }
5097
5098 if (sctx->chip_class >= GFX9) {
5099 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
5100 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5101 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5102 } else {
5103 /* These registers, when written, also overwrite the CLEAR_STATE
5104 * context, so we can't rely on CLEAR_STATE setting them.
5105 * It would be an issue if there was another UMD changing them.
5106 */
5107 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5108 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5109 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5110 }
5111
5112 if (sctx->chip_class >= GFX7) {
5113 if (sctx->chip_class >= GFX9) {
5114 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5115 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5116 } else {
5117 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5118 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5119 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5120 S_00B41C_WAVE_LIMIT(0x3F));
5121 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5122 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5123
5124 /* If this is 0, Bonaire can hang even if GS isn't being used.
5125 * Other chips are unaffected. These are suboptimal values,
5126 * but we don't use on-chip GS.
5127 */
5128 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5129 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5130 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5131 }
5132 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5133 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5134
5135 /* Compute LATE_ALLOC_VS.LIMIT. */
5136 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5137 unsigned late_alloc_limit; /* The limit is per SH. */
5138
5139 if (sctx->family == CHIP_KABINI) {
5140 late_alloc_limit = 0; /* Potential hang on Kabini. */
5141 } else if (num_cu_per_sh <= 4) {
5142 /* Too few available compute units per SH. Disallowing
5143 * VS to run on one CU could hurt us more than late VS
5144 * allocation would help.
5145 *
5146 * 2 is the highest safe number that allows us to keep
5147 * all CUs enabled.
5148 */
5149 late_alloc_limit = 2;
5150 } else {
5151 /* This is a good initial value, allowing 1 late_alloc
5152 * wave per SIMD on num_cu - 2.
5153 */
5154 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5155
5156 /* The limit is 0-based, so 0 means 1. */
5157 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5158 late_alloc_limit -= 1;
5159 }
5160
5161 /* VS can't execute on one CU if the limit is > 2. */
5162 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5163 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5164 S_00B118_WAVE_LIMIT(0x3F));
5165 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5166 S_00B11C_LIMIT(late_alloc_limit));
5167 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5168 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5169 }
5170
5171 if (sctx->chip_class >= GFX8) {
5172 unsigned vgt_tess_distribution;
5173
5174 vgt_tess_distribution =
5175 S_028B50_ACCUM_ISOLINE(32) |
5176 S_028B50_ACCUM_TRI(11) |
5177 S_028B50_ACCUM_QUAD(11) |
5178 S_028B50_DONUT_SPLIT(16);
5179
5180 /* Testing with Unigine Heaven extreme tesselation yielded best results
5181 * with TRAP_SPLIT = 3.
5182 */
5183 if (sctx->family == CHIP_FIJI ||
5184 sctx->family >= CHIP_POLARIS10)
5185 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5186
5187 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5188 } else if (!has_clear_state) {
5189 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5190 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5191 }
5192
5193 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5194 if (sctx->chip_class >= GFX7) {
5195 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5196 S_028084_ADDRESS(border_color_va >> 40));
5197 }
5198 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5199 RADEON_PRIO_BORDER_COLORS);
5200
5201 if (sctx->chip_class >= GFX9) {
5202 unsigned num_se = sscreen->info.max_se;
5203 unsigned pc_lines = 0;
5204 unsigned max_alloc_count = 0;
5205
5206 switch (sctx->family) {
5207 case CHIP_VEGA10:
5208 case CHIP_VEGA12:
5209 case CHIP_VEGA20:
5210 pc_lines = 2048;
5211 break;
5212 case CHIP_RAVEN:
5213 case CHIP_RAVEN2:
5214 case CHIP_NAVI10:
5215 case CHIP_NAVI12:
5216 pc_lines = 1024;
5217 break;
5218 case CHIP_NAVI14:
5219 pc_lines = 512;
5220 break;
5221 default:
5222 assert(0);
5223 }
5224
5225 if (sctx->chip_class >= GFX10) {
5226 max_alloc_count = pc_lines / 3;
5227 } else {
5228 max_alloc_count = MIN2(128, pc_lines / (4 * num_se));
5229 }
5230
5231 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5232 S_028C48_MAX_ALLOC_COUNT(max_alloc_count) |
5233 S_028C48_MAX_PRIM_PER_BATCH(1023));
5234 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5235 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5236 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5237 }
5238
5239 si_pm4_upload_indirect_buffer(sctx, pm4);
5240 sctx->init_config = pm4;
5241 }