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radeonsi: convert clip state into an atom
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state),
51 unsigned num_dw)
52 {
53 atom->emit = (void*)emit_func;
54 atom->num_dw = num_dw;
55 atom->dirty = false;
56 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
57 *list_elem = atom;
58 }
59
60 unsigned si_array_mode(unsigned mode)
61 {
62 switch (mode) {
63 case RADEON_SURF_MODE_LINEAR_ALIGNED:
64 return V_009910_ARRAY_LINEAR_ALIGNED;
65 case RADEON_SURF_MODE_1D:
66 return V_009910_ARRAY_1D_TILED_THIN1;
67 case RADEON_SURF_MODE_2D:
68 return V_009910_ARRAY_2D_TILED_THIN1;
69 default:
70 case RADEON_SURF_MODE_LINEAR:
71 return V_009910_ARRAY_LINEAR_GENERAL;
72 }
73 }
74
75 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
76 {
77 if (sscreen->b.chip_class >= CIK &&
78 sscreen->b.info.cik_macrotile_mode_array_valid) {
79 unsigned index, tileb;
80
81 tileb = 8 * 8 * tex->surface.bpe;
82 tileb = MIN2(tex->surface.tile_split, tileb);
83
84 for (index = 0; tileb > 64; index++) {
85 tileb >>= 1;
86 }
87 assert(index < 16);
88
89 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
90 }
91
92 if (sscreen->b.chip_class == SI &&
93 sscreen->b.info.si_tile_mode_array_valid) {
94 /* Don't use stencil_tiling_index, because num_banks is always
95 * read from the depth mode. */
96 unsigned tile_mode_index = tex->surface.tiling_index[0];
97 assert(tile_mode_index < 32);
98
99 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
100 }
101
102 /* The old way. */
103 switch (sscreen->b.tiling_info.num_banks) {
104 case 2:
105 return V_02803C_ADDR_SURF_2_BANK;
106 case 4:
107 return V_02803C_ADDR_SURF_4_BANK;
108 case 8:
109 default:
110 return V_02803C_ADDR_SURF_8_BANK;
111 case 16:
112 return V_02803C_ADDR_SURF_16_BANK;
113 }
114 }
115
116 unsigned cik_tile_split(unsigned tile_split)
117 {
118 switch (tile_split) {
119 case 64:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
121 break;
122 case 128:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
124 break;
125 case 256:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
127 break;
128 case 512:
129 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
130 break;
131 default:
132 case 1024:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
134 break;
135 case 2048:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
137 break;
138 case 4096:
139 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
140 break;
141 }
142 return tile_split;
143 }
144
145 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
146 {
147 switch (macro_tile_aspect) {
148 default:
149 case 1:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
151 break;
152 case 2:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
154 break;
155 case 4:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
157 break;
158 case 8:
159 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
160 break;
161 }
162 return macro_tile_aspect;
163 }
164
165 unsigned cik_bank_wh(unsigned bankwh)
166 {
167 switch (bankwh) {
168 default:
169 case 1:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
171 break;
172 case 2:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
174 break;
175 case 4:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
177 break;
178 case 8:
179 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
180 break;
181 }
182 return bankwh;
183 }
184
185 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
186 {
187 if (sscreen->b.info.si_tile_mode_array_valid) {
188 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
189
190 return G_009910_PIPE_CONFIG(gb_tile_mode);
191 }
192
193 /* This is probably broken for a lot of chips, but it's only used
194 * if the kernel cannot return the tile mode array for CIK. */
195 switch (sscreen->b.info.r600_num_tile_pipes) {
196 case 16:
197 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
198 case 8:
199 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
200 case 4:
201 default:
202 if (sscreen->b.info.r600_num_backends == 4)
203 return V_02803C_X_ADDR_SURF_P4_16X16;
204 else
205 return V_02803C_X_ADDR_SURF_P4_8X16;
206 case 2:
207 return V_02803C_ADDR_SURF_P2;
208 }
209 }
210
211 static unsigned si_map_swizzle(unsigned swizzle)
212 {
213 switch (swizzle) {
214 case UTIL_FORMAT_SWIZZLE_Y:
215 return V_008F0C_SQ_SEL_Y;
216 case UTIL_FORMAT_SWIZZLE_Z:
217 return V_008F0C_SQ_SEL_Z;
218 case UTIL_FORMAT_SWIZZLE_W:
219 return V_008F0C_SQ_SEL_W;
220 case UTIL_FORMAT_SWIZZLE_0:
221 return V_008F0C_SQ_SEL_0;
222 case UTIL_FORMAT_SWIZZLE_1:
223 return V_008F0C_SQ_SEL_1;
224 default: /* UTIL_FORMAT_SWIZZLE_X */
225 return V_008F0C_SQ_SEL_X;
226 }
227 }
228
229 static uint32_t S_FIXED(float value, uint32_t frac_bits)
230 {
231 return value * (1 << frac_bits);
232 }
233
234 /* 12.4 fixed-point */
235 static unsigned si_pack_float_12p4(float x)
236 {
237 return x <= 0 ? 0 :
238 x >= 4096 ? 0xffff : x * 16;
239 }
240
241 /*
242 * Inferred framebuffer and blender state.
243 *
244 * One of the reasons this must be derived from the framebuffer state is that:
245 * - The blend state mask is 0xf most of the time.
246 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
247 * so COLOR1 is enabled pretty much all the time.
248 * So CB_TARGET_MASK is the only register that can disable COLOR1.
249 *
250 * Another reason is to avoid a hang with dual source blending.
251 */
252 void si_update_fb_blend_state(struct si_context *sctx)
253 {
254 struct si_pm4_state *pm4;
255 struct si_state_blend *blend = sctx->queued.named.blend;
256 uint32_t mask = 0, i;
257
258 if (blend == NULL)
259 return;
260
261 pm4 = CALLOC_STRUCT(si_pm4_state);
262 if (pm4 == NULL)
263 return;
264
265 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
266 if (sctx->framebuffer.state.cbufs[i])
267 mask |= 0xf << (4*i);
268 mask &= blend->cb_target_mask;
269
270 /* Avoid a hang that happens when dual source blending is enabled
271 * but there is not enough color outputs. This is undefined behavior,
272 * so disable color writes completely.
273 *
274 * Reproducible with Unigine Heaven 4.0 and drirc missing.
275 */
276 if (blend->dual_src_blend &&
277 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
278 mask = 0;
279
280 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
281 si_pm4_set_state(sctx, fb_blend, pm4);
282 }
283
284 /*
285 * Blender functions
286 */
287
288 static uint32_t si_translate_blend_function(int blend_func)
289 {
290 switch (blend_func) {
291 case PIPE_BLEND_ADD:
292 return V_028780_COMB_DST_PLUS_SRC;
293 case PIPE_BLEND_SUBTRACT:
294 return V_028780_COMB_SRC_MINUS_DST;
295 case PIPE_BLEND_REVERSE_SUBTRACT:
296 return V_028780_COMB_DST_MINUS_SRC;
297 case PIPE_BLEND_MIN:
298 return V_028780_COMB_MIN_DST_SRC;
299 case PIPE_BLEND_MAX:
300 return V_028780_COMB_MAX_DST_SRC;
301 default:
302 R600_ERR("Unknown blend function %d\n", blend_func);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
309 static uint32_t si_translate_blend_factor(int blend_fact)
310 {
311 switch (blend_fact) {
312 case PIPE_BLENDFACTOR_ONE:
313 return V_028780_BLEND_ONE;
314 case PIPE_BLENDFACTOR_SRC_COLOR:
315 return V_028780_BLEND_SRC_COLOR;
316 case PIPE_BLENDFACTOR_SRC_ALPHA:
317 return V_028780_BLEND_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_DST_ALPHA:
319 return V_028780_BLEND_DST_ALPHA;
320 case PIPE_BLENDFACTOR_DST_COLOR:
321 return V_028780_BLEND_DST_COLOR;
322 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
323 return V_028780_BLEND_SRC_ALPHA_SATURATE;
324 case PIPE_BLENDFACTOR_CONST_COLOR:
325 return V_028780_BLEND_CONSTANT_COLOR;
326 case PIPE_BLENDFACTOR_CONST_ALPHA:
327 return V_028780_BLEND_CONSTANT_ALPHA;
328 case PIPE_BLENDFACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
331 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
334 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
335 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
336 case PIPE_BLENDFACTOR_INV_DST_COLOR:
337 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
338 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
340 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
342 case PIPE_BLENDFACTOR_SRC1_COLOR:
343 return V_028780_BLEND_SRC1_COLOR;
344 case PIPE_BLENDFACTOR_SRC1_ALPHA:
345 return V_028780_BLEND_SRC1_ALPHA;
346 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
347 return V_028780_BLEND_INV_SRC1_COLOR;
348 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
349 return V_028780_BLEND_INV_SRC1_ALPHA;
350 default:
351 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
352 assert(0);
353 break;
354 }
355 return 0;
356 }
357
358 static void *si_create_blend_state_mode(struct pipe_context *ctx,
359 const struct pipe_blend_state *state,
360 unsigned mode)
361 {
362 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
363 struct si_pm4_state *pm4 = &blend->pm4;
364
365 uint32_t color_control = 0;
366
367 if (blend == NULL)
368 return NULL;
369
370 blend->alpha_to_one = state->alpha_to_one;
371 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
372
373 if (state->logicop_enable) {
374 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
375 } else {
376 color_control |= S_028808_ROP3(0xcc);
377 }
378
379 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
380 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
381 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
382 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
383 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
384 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
385
386 blend->cb_target_mask = 0;
387 for (int i = 0; i < 8; i++) {
388 /* state->rt entries > 0 only written if independent blending */
389 const int j = state->independent_blend_enable ? i : 0;
390
391 unsigned eqRGB = state->rt[j].rgb_func;
392 unsigned srcRGB = state->rt[j].rgb_src_factor;
393 unsigned dstRGB = state->rt[j].rgb_dst_factor;
394 unsigned eqA = state->rt[j].alpha_func;
395 unsigned srcA = state->rt[j].alpha_src_factor;
396 unsigned dstA = state->rt[j].alpha_dst_factor;
397
398 unsigned blend_cntl = 0;
399
400 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
401 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
402
403 if (!state->rt[j].blend_enable) {
404 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
405 continue;
406 }
407
408 blend_cntl |= S_028780_ENABLE(1);
409 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
410 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
411 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
412
413 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
414 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
415 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
416 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
417 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
418 }
419 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
420 }
421
422 if (blend->cb_target_mask) {
423 color_control |= S_028808_MODE(mode);
424 } else {
425 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
426 }
427 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
428
429 return blend;
430 }
431
432 static void *si_create_blend_state(struct pipe_context *ctx,
433 const struct pipe_blend_state *state)
434 {
435 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
436 }
437
438 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
439 {
440 struct si_context *sctx = (struct si_context *)ctx;
441 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
442 si_update_fb_blend_state(sctx);
443 }
444
445 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
446 {
447 struct si_context *sctx = (struct si_context *)ctx;
448 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
449 }
450
451 static void si_set_blend_color(struct pipe_context *ctx,
452 const struct pipe_blend_color *state)
453 {
454 struct si_context *sctx = (struct si_context *)ctx;
455 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
456
457 if (pm4 == NULL)
458 return;
459
460 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
461 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
462 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
463 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
464
465 si_pm4_set_state(sctx, blend_color, pm4);
466 }
467
468 /*
469 * Clipping, scissors and viewport
470 */
471
472 static void si_set_clip_state(struct pipe_context *ctx,
473 const struct pipe_clip_state *state)
474 {
475 struct si_context *sctx = (struct si_context *)ctx;
476 struct pipe_constant_buffer cb;
477
478 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
479 return;
480
481 sctx->clip_state.state = *state;
482 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
483
484 cb.buffer = NULL;
485 cb.user_buffer = state->ucp;
486 cb.buffer_offset = 0;
487 cb.buffer_size = 4*4*8;
488 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
489 pipe_resource_reference(&cb.buffer, NULL);
490 }
491
492 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
493 {
494 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
495
496 r600_write_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
497 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
498 }
499
500 #define SIX_BITS 0x3F
501
502 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
503 {
504 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
505 struct tgsi_shader_info *info = si_get_vs_info(sctx);
506 unsigned window_space =
507 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
508 unsigned clipdist_mask =
509 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
510
511 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
512 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
513 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
514 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
515 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
516 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
517 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
518 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
519 info->writes_edgeflag ||
520 info->writes_layer ||
521 info->writes_viewport_index) |
522 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
523 (sctx->queued.named.rasterizer->clip_plane_enable &
524 clipdist_mask));
525 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
526 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
527 (clipdist_mask ? 0 :
528 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
529 S_028810_CLIP_DISABLE(window_space));
530 }
531
532 static void si_set_scissor_states(struct pipe_context *ctx,
533 unsigned start_slot,
534 unsigned num_scissors,
535 const struct pipe_scissor_state *state)
536 {
537 struct si_context *sctx = (struct si_context *)ctx;
538 int i;
539
540 for (i = 0; i < num_scissors; i++)
541 sctx->scissors.states[start_slot + i] = state[i];
542
543 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
544 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
545 }
546
547 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
548 {
549 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
550 struct pipe_scissor_state *states = sctx->scissors.states;
551 unsigned mask = sctx->scissors.dirty_mask;
552
553 /* The simple case: Only 1 viewport is active. */
554 if (mask & 1 &&
555 !si_get_vs_info(sctx)->writes_viewport_index) {
556 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
557 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
558 S_028250_TL_Y(states[0].miny) |
559 S_028250_WINDOW_OFFSET_DISABLE(1));
560 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
561 S_028254_BR_Y(states[0].maxy));
562 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
563 return;
564 }
565
566 while (mask) {
567 int start, count, i;
568
569 u_bit_scan_consecutive_range(&mask, &start, &count);
570
571 r600_write_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
572 start * 4 * 2, count * 2);
573 for (i = start; i < start+count; i++) {
574 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
575 S_028250_TL_Y(states[i].miny) |
576 S_028250_WINDOW_OFFSET_DISABLE(1));
577 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
578 S_028254_BR_Y(states[i].maxy));
579 }
580 }
581 sctx->scissors.dirty_mask = 0;
582 }
583
584 static void si_set_viewport_states(struct pipe_context *ctx,
585 unsigned start_slot,
586 unsigned num_viewports,
587 const struct pipe_viewport_state *state)
588 {
589 struct si_context *sctx = (struct si_context *)ctx;
590 int i;
591
592 for (i = 0; i < num_viewports; i++)
593 sctx->viewports.states[start_slot + i] = state[i];
594
595 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
596 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
597 }
598
599 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
600 {
601 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
602 struct pipe_viewport_state *states = sctx->viewports.states;
603 unsigned mask = sctx->viewports.dirty_mask;
604
605 /* The simple case: Only 1 viewport is active. */
606 if (mask & 1 &&
607 !si_get_vs_info(sctx)->writes_viewport_index) {
608 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
609 radeon_emit(cs, fui(states[0].scale[0]));
610 radeon_emit(cs, fui(states[0].translate[0]));
611 radeon_emit(cs, fui(states[0].scale[1]));
612 radeon_emit(cs, fui(states[0].translate[1]));
613 radeon_emit(cs, fui(states[0].scale[2]));
614 radeon_emit(cs, fui(states[0].translate[2]));
615 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
616 return;
617 }
618
619 while (mask) {
620 int start, count, i;
621
622 u_bit_scan_consecutive_range(&mask, &start, &count);
623
624 r600_write_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
625 start * 4 * 6, count * 6);
626 for (i = start; i < start+count; i++) {
627 radeon_emit(cs, fui(states[i].scale[0]));
628 radeon_emit(cs, fui(states[i].translate[0]));
629 radeon_emit(cs, fui(states[i].scale[1]));
630 radeon_emit(cs, fui(states[i].translate[1]));
631 radeon_emit(cs, fui(states[i].scale[2]));
632 radeon_emit(cs, fui(states[i].translate[2]));
633 }
634 }
635 sctx->viewports.dirty_mask = 0;
636 }
637
638 /*
639 * inferred state between framebuffer and rasterizer
640 */
641 static void si_update_fb_rs_state(struct si_context *sctx)
642 {
643 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
644 struct si_pm4_state *pm4;
645 float offset_units;
646
647 if (!rs || !sctx->framebuffer.state.zsbuf)
648 return;
649
650 offset_units = sctx->queued.named.rasterizer->offset_units;
651 switch (sctx->framebuffer.state.zsbuf->texture->format) {
652 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
653 case PIPE_FORMAT_X8Z24_UNORM:
654 case PIPE_FORMAT_Z24X8_UNORM:
655 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
656 offset_units *= 2.0f;
657 break;
658 case PIPE_FORMAT_Z32_FLOAT:
659 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
660 offset_units *= 1.0f;
661 break;
662 case PIPE_FORMAT_Z16_UNORM:
663 offset_units *= 4.0f;
664 break;
665 default:
666 return;
667 }
668
669 pm4 = CALLOC_STRUCT(si_pm4_state);
670
671 if (pm4 == NULL)
672 return;
673
674 /* FIXME some of those reg can be computed with cso */
675 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
676 fui(sctx->queued.named.rasterizer->offset_scale));
677 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
678 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
679 fui(sctx->queued.named.rasterizer->offset_scale));
680 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
681
682 si_pm4_set_state(sctx, fb_rs, pm4);
683 }
684
685 /*
686 * Rasterizer
687 */
688
689 static uint32_t si_translate_fill(uint32_t func)
690 {
691 switch(func) {
692 case PIPE_POLYGON_MODE_FILL:
693 return V_028814_X_DRAW_TRIANGLES;
694 case PIPE_POLYGON_MODE_LINE:
695 return V_028814_X_DRAW_LINES;
696 case PIPE_POLYGON_MODE_POINT:
697 return V_028814_X_DRAW_POINTS;
698 default:
699 assert(0);
700 return V_028814_X_DRAW_POINTS;
701 }
702 }
703
704 static void *si_create_rs_state(struct pipe_context *ctx,
705 const struct pipe_rasterizer_state *state)
706 {
707 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
708 struct si_pm4_state *pm4 = &rs->pm4;
709 unsigned tmp;
710 float psize_min, psize_max;
711
712 if (rs == NULL) {
713 return NULL;
714 }
715
716 rs->two_side = state->light_twoside;
717 rs->multisample_enable = state->multisample;
718 rs->clip_plane_enable = state->clip_plane_enable;
719 rs->line_stipple_enable = state->line_stipple_enable;
720 rs->poly_stipple_enable = state->poly_stipple_enable;
721 rs->line_smooth = state->line_smooth;
722 rs->poly_smooth = state->poly_smooth;
723
724 rs->flatshade = state->flatshade;
725 rs->sprite_coord_enable = state->sprite_coord_enable;
726 rs->pa_sc_line_stipple = state->line_stipple_enable ?
727 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
728 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
729 rs->pa_cl_clip_cntl =
730 S_028810_PS_UCP_MODE(3) |
731 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
732 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
733 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
734 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
735 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
736
737 /* offset */
738 rs->offset_units = state->offset_units;
739 rs->offset_scale = state->offset_scale * 16.0f;
740
741 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
742 S_0286D4_FLAT_SHADE_ENA(1) |
743 S_0286D4_PNT_SPRITE_ENA(1) |
744 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
745 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
746 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
747 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
748 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
749
750 /* point size 12.4 fixed point */
751 tmp = (unsigned)(state->point_size * 8.0);
752 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
753
754 if (state->point_size_per_vertex) {
755 psize_min = util_get_min_point_size(state);
756 psize_max = 8192;
757 } else {
758 /* Force the point size to be as if the vertex output was disabled. */
759 psize_min = state->point_size;
760 psize_max = state->point_size;
761 }
762 /* Divide by two, because 0.5 = 1 pixel. */
763 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
764 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
765 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
766
767 tmp = (unsigned)state->line_width * 8;
768 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
769 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
770 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
771 S_028A48_MSAA_ENABLE(state->multisample ||
772 state->poly_smooth ||
773 state->line_smooth) |
774 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
775
776 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
777 S_028BE4_PIX_CENTER(state->half_pixel_center) |
778 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
779
780 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
781 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
782 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
783 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
784 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
785 S_028814_FACE(!state->front_ccw) |
786 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
787 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
788 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
789 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
790 state->fill_back != PIPE_POLYGON_MODE_FILL) |
791 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
792 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
793 return rs;
794 }
795
796 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
797 {
798 struct si_context *sctx = (struct si_context *)ctx;
799 struct si_state_rasterizer *old_rs =
800 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
801 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
802
803 if (state == NULL)
804 return;
805
806 if (sctx->framebuffer.nr_samples > 1 &&
807 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
808 si_mark_atom_dirty(sctx, &sctx->db_render_state);
809
810 si_pm4_bind_state(sctx, rasterizer, rs);
811 si_update_fb_rs_state(sctx);
812
813 si_mark_atom_dirty(sctx, &sctx->clip_regs);
814 }
815
816 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
817 {
818 struct si_context *sctx = (struct si_context *)ctx;
819 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
820 }
821
822 /*
823 * infeered state between dsa and stencil ref
824 */
825 static void si_update_dsa_stencil_ref(struct si_context *sctx)
826 {
827 struct si_pm4_state *pm4;
828 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
829 struct si_state_dsa *dsa = sctx->queued.named.dsa;
830
831 if (!dsa)
832 return;
833
834 pm4 = CALLOC_STRUCT(si_pm4_state);
835 if (pm4 == NULL)
836 return;
837
838 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
839 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
840 S_028430_STENCILMASK(dsa->valuemask[0]) |
841 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
842 S_028430_STENCILOPVAL(1));
843 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
844 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
845 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
846 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
847 S_028434_STENCILOPVAL_BF(1));
848
849 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
850 }
851
852 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
853 const struct pipe_stencil_ref *state)
854 {
855 struct si_context *sctx = (struct si_context *)ctx;
856 sctx->stencil_ref = *state;
857 si_update_dsa_stencil_ref(sctx);
858 }
859
860
861 /*
862 * DSA
863 */
864
865 static uint32_t si_translate_stencil_op(int s_op)
866 {
867 switch (s_op) {
868 case PIPE_STENCIL_OP_KEEP:
869 return V_02842C_STENCIL_KEEP;
870 case PIPE_STENCIL_OP_ZERO:
871 return V_02842C_STENCIL_ZERO;
872 case PIPE_STENCIL_OP_REPLACE:
873 return V_02842C_STENCIL_REPLACE_TEST;
874 case PIPE_STENCIL_OP_INCR:
875 return V_02842C_STENCIL_ADD_CLAMP;
876 case PIPE_STENCIL_OP_DECR:
877 return V_02842C_STENCIL_SUB_CLAMP;
878 case PIPE_STENCIL_OP_INCR_WRAP:
879 return V_02842C_STENCIL_ADD_WRAP;
880 case PIPE_STENCIL_OP_DECR_WRAP:
881 return V_02842C_STENCIL_SUB_WRAP;
882 case PIPE_STENCIL_OP_INVERT:
883 return V_02842C_STENCIL_INVERT;
884 default:
885 R600_ERR("Unknown stencil op %d", s_op);
886 assert(0);
887 break;
888 }
889 return 0;
890 }
891
892 static void *si_create_dsa_state(struct pipe_context *ctx,
893 const struct pipe_depth_stencil_alpha_state *state)
894 {
895 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
896 struct si_pm4_state *pm4 = &dsa->pm4;
897 unsigned db_depth_control;
898 uint32_t db_stencil_control = 0;
899
900 if (dsa == NULL) {
901 return NULL;
902 }
903
904 dsa->valuemask[0] = state->stencil[0].valuemask;
905 dsa->valuemask[1] = state->stencil[1].valuemask;
906 dsa->writemask[0] = state->stencil[0].writemask;
907 dsa->writemask[1] = state->stencil[1].writemask;
908
909 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
910 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
911 S_028800_ZFUNC(state->depth.func) |
912 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
913
914 /* stencil */
915 if (state->stencil[0].enabled) {
916 db_depth_control |= S_028800_STENCIL_ENABLE(1);
917 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
918 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
919 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
920 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
921
922 if (state->stencil[1].enabled) {
923 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
924 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
925 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
926 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
927 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
928 }
929 }
930
931 /* alpha */
932 if (state->alpha.enabled) {
933 dsa->alpha_func = state->alpha.func;
934
935 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
936 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
937 } else {
938 dsa->alpha_func = PIPE_FUNC_ALWAYS;
939 }
940
941 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
942 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
943 if (state->depth.bounds_test) {
944 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
945 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
946 }
947
948 return dsa;
949 }
950
951 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
952 {
953 struct si_context *sctx = (struct si_context *)ctx;
954 struct si_state_dsa *dsa = state;
955
956 if (state == NULL)
957 return;
958
959 si_pm4_bind_state(sctx, dsa, dsa);
960 si_update_dsa_stencil_ref(sctx);
961 }
962
963 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
964 {
965 struct si_context *sctx = (struct si_context *)ctx;
966 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
967 }
968
969 static void *si_create_db_flush_dsa(struct si_context *sctx)
970 {
971 struct pipe_depth_stencil_alpha_state dsa = {};
972
973 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
974 }
975
976 /* DB RENDER STATE */
977
978 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
979 {
980 struct si_context *sctx = (struct si_context*)ctx;
981
982 si_mark_atom_dirty(sctx, &sctx->db_render_state);
983 }
984
985 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
986 {
987 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
988 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
989 unsigned db_shader_control;
990
991 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
992
993 /* DB_RENDER_CONTROL */
994 if (sctx->dbcb_depth_copy_enabled ||
995 sctx->dbcb_stencil_copy_enabled) {
996 radeon_emit(cs,
997 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
998 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
999 S_028000_COPY_CENTROID(1) |
1000 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1001 } else if (sctx->db_inplace_flush_enabled) {
1002 radeon_emit(cs,
1003 S_028000_DEPTH_COMPRESS_DISABLE(1) |
1004 S_028000_STENCIL_COMPRESS_DISABLE(1));
1005 } else if (sctx->db_depth_clear) {
1006 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1007 } else {
1008 radeon_emit(cs, 0);
1009 }
1010
1011 /* DB_COUNT_CONTROL (occlusion queries) */
1012 if (sctx->b.num_occlusion_queries > 0) {
1013 if (sctx->b.chip_class >= CIK) {
1014 radeon_emit(cs,
1015 S_028004_PERFECT_ZPASS_COUNTS(1) |
1016 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1017 S_028004_ZPASS_ENABLE(1) |
1018 S_028004_SLICE_EVEN_ENABLE(1) |
1019 S_028004_SLICE_ODD_ENABLE(1));
1020 } else {
1021 radeon_emit(cs,
1022 S_028004_PERFECT_ZPASS_COUNTS(1) |
1023 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1024 }
1025 } else {
1026 /* Disable occlusion queries. */
1027 if (sctx->b.chip_class >= CIK) {
1028 radeon_emit(cs, 0);
1029 } else {
1030 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1031 }
1032 }
1033
1034 /* DB_RENDER_OVERRIDE2 */
1035 if (sctx->db_depth_disable_expclear) {
1036 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1037 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1038 } else {
1039 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1040 }
1041
1042 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1043 sctx->ps_db_shader_control;
1044
1045 /* Bug workaround for smoothing (overrasterization) on SI. */
1046 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1047 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1048 else
1049 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1050
1051 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1052 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1053 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1054
1055 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1056 db_shader_control);
1057 }
1058
1059 /*
1060 * format translation
1061 */
1062 static uint32_t si_translate_colorformat(enum pipe_format format)
1063 {
1064 const struct util_format_description *desc = util_format_description(format);
1065
1066 #define HAS_SIZE(x,y,z,w) \
1067 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1068 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1069
1070 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1071 return V_028C70_COLOR_10_11_11;
1072
1073 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1074 return V_028C70_COLOR_INVALID;
1075
1076 switch (desc->nr_channels) {
1077 case 1:
1078 switch (desc->channel[0].size) {
1079 case 8:
1080 return V_028C70_COLOR_8;
1081 case 16:
1082 return V_028C70_COLOR_16;
1083 case 32:
1084 return V_028C70_COLOR_32;
1085 }
1086 break;
1087 case 2:
1088 if (desc->channel[0].size == desc->channel[1].size) {
1089 switch (desc->channel[0].size) {
1090 case 8:
1091 return V_028C70_COLOR_8_8;
1092 case 16:
1093 return V_028C70_COLOR_16_16;
1094 case 32:
1095 return V_028C70_COLOR_32_32;
1096 }
1097 } else if (HAS_SIZE(8,24,0,0)) {
1098 return V_028C70_COLOR_24_8;
1099 } else if (HAS_SIZE(24,8,0,0)) {
1100 return V_028C70_COLOR_8_24;
1101 }
1102 break;
1103 case 3:
1104 if (HAS_SIZE(5,6,5,0)) {
1105 return V_028C70_COLOR_5_6_5;
1106 } else if (HAS_SIZE(32,8,24,0)) {
1107 return V_028C70_COLOR_X24_8_32_FLOAT;
1108 }
1109 break;
1110 case 4:
1111 if (desc->channel[0].size == desc->channel[1].size &&
1112 desc->channel[0].size == desc->channel[2].size &&
1113 desc->channel[0].size == desc->channel[3].size) {
1114 switch (desc->channel[0].size) {
1115 case 4:
1116 return V_028C70_COLOR_4_4_4_4;
1117 case 8:
1118 return V_028C70_COLOR_8_8_8_8;
1119 case 16:
1120 return V_028C70_COLOR_16_16_16_16;
1121 case 32:
1122 return V_028C70_COLOR_32_32_32_32;
1123 }
1124 } else if (HAS_SIZE(5,5,5,1)) {
1125 return V_028C70_COLOR_1_5_5_5;
1126 } else if (HAS_SIZE(10,10,10,2)) {
1127 return V_028C70_COLOR_2_10_10_10;
1128 }
1129 break;
1130 }
1131 return V_028C70_COLOR_INVALID;
1132 }
1133
1134 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1135 {
1136 if (SI_BIG_ENDIAN) {
1137 switch(colorformat) {
1138 /* 8-bit buffers. */
1139 case V_028C70_COLOR_8:
1140 return V_028C70_ENDIAN_NONE;
1141
1142 /* 16-bit buffers. */
1143 case V_028C70_COLOR_5_6_5:
1144 case V_028C70_COLOR_1_5_5_5:
1145 case V_028C70_COLOR_4_4_4_4:
1146 case V_028C70_COLOR_16:
1147 case V_028C70_COLOR_8_8:
1148 return V_028C70_ENDIAN_8IN16;
1149
1150 /* 32-bit buffers. */
1151 case V_028C70_COLOR_8_8_8_8:
1152 case V_028C70_COLOR_2_10_10_10:
1153 case V_028C70_COLOR_8_24:
1154 case V_028C70_COLOR_24_8:
1155 case V_028C70_COLOR_16_16:
1156 return V_028C70_ENDIAN_8IN32;
1157
1158 /* 64-bit buffers. */
1159 case V_028C70_COLOR_16_16_16_16:
1160 return V_028C70_ENDIAN_8IN16;
1161
1162 case V_028C70_COLOR_32_32:
1163 return V_028C70_ENDIAN_8IN32;
1164
1165 /* 128-bit buffers. */
1166 case V_028C70_COLOR_32_32_32_32:
1167 return V_028C70_ENDIAN_8IN32;
1168 default:
1169 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1170 }
1171 } else {
1172 return V_028C70_ENDIAN_NONE;
1173 }
1174 }
1175
1176 /* Returns the size in bits of the widest component of a CB format */
1177 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1178 {
1179 switch(colorformat) {
1180 case V_028C70_COLOR_4_4_4_4:
1181 return 4;
1182
1183 case V_028C70_COLOR_1_5_5_5:
1184 case V_028C70_COLOR_5_5_5_1:
1185 return 5;
1186
1187 case V_028C70_COLOR_5_6_5:
1188 return 6;
1189
1190 case V_028C70_COLOR_8:
1191 case V_028C70_COLOR_8_8:
1192 case V_028C70_COLOR_8_8_8_8:
1193 return 8;
1194
1195 case V_028C70_COLOR_10_10_10_2:
1196 case V_028C70_COLOR_2_10_10_10:
1197 return 10;
1198
1199 case V_028C70_COLOR_10_11_11:
1200 case V_028C70_COLOR_11_11_10:
1201 return 11;
1202
1203 case V_028C70_COLOR_16:
1204 case V_028C70_COLOR_16_16:
1205 case V_028C70_COLOR_16_16_16_16:
1206 return 16;
1207
1208 case V_028C70_COLOR_8_24:
1209 case V_028C70_COLOR_24_8:
1210 return 24;
1211
1212 case V_028C70_COLOR_32:
1213 case V_028C70_COLOR_32_32:
1214 case V_028C70_COLOR_32_32_32_32:
1215 case V_028C70_COLOR_X24_8_32_FLOAT:
1216 return 32;
1217 }
1218
1219 assert(!"Unknown maximum component size");
1220 return 0;
1221 }
1222
1223 static uint32_t si_translate_dbformat(enum pipe_format format)
1224 {
1225 switch (format) {
1226 case PIPE_FORMAT_Z16_UNORM:
1227 return V_028040_Z_16;
1228 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1229 case PIPE_FORMAT_X8Z24_UNORM:
1230 case PIPE_FORMAT_Z24X8_UNORM:
1231 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1232 return V_028040_Z_24; /* deprecated on SI */
1233 case PIPE_FORMAT_Z32_FLOAT:
1234 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1235 return V_028040_Z_32_FLOAT;
1236 default:
1237 return V_028040_Z_INVALID;
1238 }
1239 }
1240
1241 /*
1242 * Texture translation
1243 */
1244
1245 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1246 enum pipe_format format,
1247 const struct util_format_description *desc,
1248 int first_non_void)
1249 {
1250 struct si_screen *sscreen = (struct si_screen*)screen;
1251 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1252 sscreen->b.info.drm_minor >= 31) ||
1253 sscreen->b.info.drm_major == 3;
1254 boolean uniform = TRUE;
1255 int i;
1256
1257 /* Colorspace (return non-RGB formats directly). */
1258 switch (desc->colorspace) {
1259 /* Depth stencil formats */
1260 case UTIL_FORMAT_COLORSPACE_ZS:
1261 switch (format) {
1262 case PIPE_FORMAT_Z16_UNORM:
1263 return V_008F14_IMG_DATA_FORMAT_16;
1264 case PIPE_FORMAT_X24S8_UINT:
1265 case PIPE_FORMAT_Z24X8_UNORM:
1266 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1267 return V_008F14_IMG_DATA_FORMAT_8_24;
1268 case PIPE_FORMAT_X8Z24_UNORM:
1269 case PIPE_FORMAT_S8X24_UINT:
1270 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1271 return V_008F14_IMG_DATA_FORMAT_24_8;
1272 case PIPE_FORMAT_S8_UINT:
1273 return V_008F14_IMG_DATA_FORMAT_8;
1274 case PIPE_FORMAT_Z32_FLOAT:
1275 return V_008F14_IMG_DATA_FORMAT_32;
1276 case PIPE_FORMAT_X32_S8X24_UINT:
1277 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1278 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1279 default:
1280 goto out_unknown;
1281 }
1282
1283 case UTIL_FORMAT_COLORSPACE_YUV:
1284 goto out_unknown; /* TODO */
1285
1286 case UTIL_FORMAT_COLORSPACE_SRGB:
1287 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1288 goto out_unknown;
1289 break;
1290
1291 default:
1292 break;
1293 }
1294
1295 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1296 if (!enable_compressed_formats)
1297 goto out_unknown;
1298
1299 switch (format) {
1300 case PIPE_FORMAT_RGTC1_SNORM:
1301 case PIPE_FORMAT_LATC1_SNORM:
1302 case PIPE_FORMAT_RGTC1_UNORM:
1303 case PIPE_FORMAT_LATC1_UNORM:
1304 return V_008F14_IMG_DATA_FORMAT_BC4;
1305 case PIPE_FORMAT_RGTC2_SNORM:
1306 case PIPE_FORMAT_LATC2_SNORM:
1307 case PIPE_FORMAT_RGTC2_UNORM:
1308 case PIPE_FORMAT_LATC2_UNORM:
1309 return V_008F14_IMG_DATA_FORMAT_BC5;
1310 default:
1311 goto out_unknown;
1312 }
1313 }
1314
1315 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1316 if (!enable_compressed_formats)
1317 goto out_unknown;
1318
1319 switch (format) {
1320 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1321 case PIPE_FORMAT_BPTC_SRGBA:
1322 return V_008F14_IMG_DATA_FORMAT_BC7;
1323 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1324 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1325 return V_008F14_IMG_DATA_FORMAT_BC6;
1326 default:
1327 goto out_unknown;
1328 }
1329 }
1330
1331 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1332 switch (format) {
1333 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1334 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1335 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1336 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1337 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1338 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1339 default:
1340 goto out_unknown;
1341 }
1342 }
1343
1344 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1345 if (!enable_compressed_formats)
1346 goto out_unknown;
1347
1348 if (!util_format_s3tc_enabled) {
1349 goto out_unknown;
1350 }
1351
1352 switch (format) {
1353 case PIPE_FORMAT_DXT1_RGB:
1354 case PIPE_FORMAT_DXT1_RGBA:
1355 case PIPE_FORMAT_DXT1_SRGB:
1356 case PIPE_FORMAT_DXT1_SRGBA:
1357 return V_008F14_IMG_DATA_FORMAT_BC1;
1358 case PIPE_FORMAT_DXT3_RGBA:
1359 case PIPE_FORMAT_DXT3_SRGBA:
1360 return V_008F14_IMG_DATA_FORMAT_BC2;
1361 case PIPE_FORMAT_DXT5_RGBA:
1362 case PIPE_FORMAT_DXT5_SRGBA:
1363 return V_008F14_IMG_DATA_FORMAT_BC3;
1364 default:
1365 goto out_unknown;
1366 }
1367 }
1368
1369 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1370 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1371 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1372 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1373 }
1374
1375 /* R8G8Bx_SNORM - TODO CxV8U8 */
1376
1377 /* See whether the components are of the same size. */
1378 for (i = 1; i < desc->nr_channels; i++) {
1379 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1380 }
1381
1382 /* Non-uniform formats. */
1383 if (!uniform) {
1384 switch(desc->nr_channels) {
1385 case 3:
1386 if (desc->channel[0].size == 5 &&
1387 desc->channel[1].size == 6 &&
1388 desc->channel[2].size == 5) {
1389 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1390 }
1391 goto out_unknown;
1392 case 4:
1393 if (desc->channel[0].size == 5 &&
1394 desc->channel[1].size == 5 &&
1395 desc->channel[2].size == 5 &&
1396 desc->channel[3].size == 1) {
1397 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1398 }
1399 if (desc->channel[0].size == 10 &&
1400 desc->channel[1].size == 10 &&
1401 desc->channel[2].size == 10 &&
1402 desc->channel[3].size == 2) {
1403 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1404 }
1405 goto out_unknown;
1406 }
1407 goto out_unknown;
1408 }
1409
1410 if (first_non_void < 0 || first_non_void > 3)
1411 goto out_unknown;
1412
1413 /* uniform formats */
1414 switch (desc->channel[first_non_void].size) {
1415 case 4:
1416 switch (desc->nr_channels) {
1417 #if 0 /* Not supported for render targets */
1418 case 2:
1419 return V_008F14_IMG_DATA_FORMAT_4_4;
1420 #endif
1421 case 4:
1422 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1423 }
1424 break;
1425 case 8:
1426 switch (desc->nr_channels) {
1427 case 1:
1428 return V_008F14_IMG_DATA_FORMAT_8;
1429 case 2:
1430 return V_008F14_IMG_DATA_FORMAT_8_8;
1431 case 4:
1432 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1433 }
1434 break;
1435 case 16:
1436 switch (desc->nr_channels) {
1437 case 1:
1438 return V_008F14_IMG_DATA_FORMAT_16;
1439 case 2:
1440 return V_008F14_IMG_DATA_FORMAT_16_16;
1441 case 4:
1442 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1443 }
1444 break;
1445 case 32:
1446 switch (desc->nr_channels) {
1447 case 1:
1448 return V_008F14_IMG_DATA_FORMAT_32;
1449 case 2:
1450 return V_008F14_IMG_DATA_FORMAT_32_32;
1451 #if 0 /* Not supported for render targets */
1452 case 3:
1453 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1454 #endif
1455 case 4:
1456 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1457 }
1458 }
1459
1460 out_unknown:
1461 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1462 return ~0;
1463 }
1464
1465 static unsigned si_tex_wrap(unsigned wrap)
1466 {
1467 switch (wrap) {
1468 default:
1469 case PIPE_TEX_WRAP_REPEAT:
1470 return V_008F30_SQ_TEX_WRAP;
1471 case PIPE_TEX_WRAP_CLAMP:
1472 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1473 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1474 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1475 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1476 return V_008F30_SQ_TEX_CLAMP_BORDER;
1477 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1478 return V_008F30_SQ_TEX_MIRROR;
1479 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1480 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1481 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1482 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1483 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1484 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1485 }
1486 }
1487
1488 static unsigned si_tex_filter(unsigned filter)
1489 {
1490 switch (filter) {
1491 default:
1492 case PIPE_TEX_FILTER_NEAREST:
1493 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1494 case PIPE_TEX_FILTER_LINEAR:
1495 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1496 }
1497 }
1498
1499 static unsigned si_tex_mipfilter(unsigned filter)
1500 {
1501 switch (filter) {
1502 case PIPE_TEX_MIPFILTER_NEAREST:
1503 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1504 case PIPE_TEX_MIPFILTER_LINEAR:
1505 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1506 default:
1507 case PIPE_TEX_MIPFILTER_NONE:
1508 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1509 }
1510 }
1511
1512 static unsigned si_tex_compare(unsigned compare)
1513 {
1514 switch (compare) {
1515 default:
1516 case PIPE_FUNC_NEVER:
1517 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1518 case PIPE_FUNC_LESS:
1519 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1520 case PIPE_FUNC_EQUAL:
1521 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1522 case PIPE_FUNC_LEQUAL:
1523 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1524 case PIPE_FUNC_GREATER:
1525 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1526 case PIPE_FUNC_NOTEQUAL:
1527 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1528 case PIPE_FUNC_GEQUAL:
1529 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1530 case PIPE_FUNC_ALWAYS:
1531 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1532 }
1533 }
1534
1535 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1536 {
1537 switch (dim) {
1538 default:
1539 case PIPE_TEXTURE_1D:
1540 return V_008F1C_SQ_RSRC_IMG_1D;
1541 case PIPE_TEXTURE_1D_ARRAY:
1542 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1543 case PIPE_TEXTURE_2D:
1544 case PIPE_TEXTURE_RECT:
1545 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1546 V_008F1C_SQ_RSRC_IMG_2D;
1547 case PIPE_TEXTURE_2D_ARRAY:
1548 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1549 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1550 case PIPE_TEXTURE_3D:
1551 return V_008F1C_SQ_RSRC_IMG_3D;
1552 case PIPE_TEXTURE_CUBE:
1553 case PIPE_TEXTURE_CUBE_ARRAY:
1554 return V_008F1C_SQ_RSRC_IMG_CUBE;
1555 }
1556 }
1557
1558 /*
1559 * Format support testing
1560 */
1561
1562 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1563 {
1564 return si_translate_texformat(screen, format, util_format_description(format),
1565 util_format_get_first_non_void_channel(format)) != ~0U;
1566 }
1567
1568 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1569 const struct util_format_description *desc,
1570 int first_non_void)
1571 {
1572 unsigned type = desc->channel[first_non_void].type;
1573 int i;
1574
1575 if (type == UTIL_FORMAT_TYPE_FIXED)
1576 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1577
1578 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1579 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1580
1581 if (desc->nr_channels == 4 &&
1582 desc->channel[0].size == 10 &&
1583 desc->channel[1].size == 10 &&
1584 desc->channel[2].size == 10 &&
1585 desc->channel[3].size == 2)
1586 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1587
1588 /* See whether the components are of the same size. */
1589 for (i = 0; i < desc->nr_channels; i++) {
1590 if (desc->channel[first_non_void].size != desc->channel[i].size)
1591 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1592 }
1593
1594 switch (desc->channel[first_non_void].size) {
1595 case 8:
1596 switch (desc->nr_channels) {
1597 case 1:
1598 return V_008F0C_BUF_DATA_FORMAT_8;
1599 case 2:
1600 return V_008F0C_BUF_DATA_FORMAT_8_8;
1601 case 3:
1602 case 4:
1603 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1604 }
1605 break;
1606 case 16:
1607 switch (desc->nr_channels) {
1608 case 1:
1609 return V_008F0C_BUF_DATA_FORMAT_16;
1610 case 2:
1611 return V_008F0C_BUF_DATA_FORMAT_16_16;
1612 case 3:
1613 case 4:
1614 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1615 }
1616 break;
1617 case 32:
1618 /* From the Southern Islands ISA documentation about MTBUF:
1619 * 'Memory reads of data in memory that is 32 or 64 bits do not
1620 * undergo any format conversion.'
1621 */
1622 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1623 !desc->channel[first_non_void].pure_integer)
1624 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1625
1626 switch (desc->nr_channels) {
1627 case 1:
1628 return V_008F0C_BUF_DATA_FORMAT_32;
1629 case 2:
1630 return V_008F0C_BUF_DATA_FORMAT_32_32;
1631 case 3:
1632 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1633 case 4:
1634 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1635 }
1636 break;
1637 }
1638
1639 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1640 }
1641
1642 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1643 const struct util_format_description *desc,
1644 int first_non_void)
1645 {
1646 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1647 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1648
1649 switch (desc->channel[first_non_void].type) {
1650 case UTIL_FORMAT_TYPE_SIGNED:
1651 if (desc->channel[first_non_void].normalized)
1652 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1653 else if (desc->channel[first_non_void].pure_integer)
1654 return V_008F0C_BUF_NUM_FORMAT_SINT;
1655 else
1656 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1657 break;
1658 case UTIL_FORMAT_TYPE_UNSIGNED:
1659 if (desc->channel[first_non_void].normalized)
1660 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1661 else if (desc->channel[first_non_void].pure_integer)
1662 return V_008F0C_BUF_NUM_FORMAT_UINT;
1663 else
1664 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1665 break;
1666 case UTIL_FORMAT_TYPE_FLOAT:
1667 default:
1668 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1669 }
1670 }
1671
1672 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1673 {
1674 const struct util_format_description *desc;
1675 int first_non_void;
1676 unsigned data_format;
1677
1678 desc = util_format_description(format);
1679 first_non_void = util_format_get_first_non_void_channel(format);
1680 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1681 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1682 }
1683
1684 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1685 {
1686 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1687 r600_translate_colorswap(format) != ~0U;
1688 }
1689
1690 static bool si_is_zs_format_supported(enum pipe_format format)
1691 {
1692 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1693 }
1694
1695 boolean si_is_format_supported(struct pipe_screen *screen,
1696 enum pipe_format format,
1697 enum pipe_texture_target target,
1698 unsigned sample_count,
1699 unsigned usage)
1700 {
1701 unsigned retval = 0;
1702
1703 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1704 R600_ERR("r600: unsupported texture type %d\n", target);
1705 return FALSE;
1706 }
1707
1708 if (!util_format_is_supported(format, usage))
1709 return FALSE;
1710
1711 if (sample_count > 1) {
1712 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1713 return FALSE;
1714
1715 switch (sample_count) {
1716 case 2:
1717 case 4:
1718 case 8:
1719 break;
1720 default:
1721 return FALSE;
1722 }
1723 }
1724
1725 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1726 if (target == PIPE_BUFFER) {
1727 if (si_is_vertex_format_supported(screen, format))
1728 retval |= PIPE_BIND_SAMPLER_VIEW;
1729 } else {
1730 if (si_is_sampler_format_supported(screen, format))
1731 retval |= PIPE_BIND_SAMPLER_VIEW;
1732 }
1733 }
1734
1735 if ((usage & (PIPE_BIND_RENDER_TARGET |
1736 PIPE_BIND_DISPLAY_TARGET |
1737 PIPE_BIND_SCANOUT |
1738 PIPE_BIND_SHARED |
1739 PIPE_BIND_BLENDABLE)) &&
1740 si_is_colorbuffer_format_supported(format)) {
1741 retval |= usage &
1742 (PIPE_BIND_RENDER_TARGET |
1743 PIPE_BIND_DISPLAY_TARGET |
1744 PIPE_BIND_SCANOUT |
1745 PIPE_BIND_SHARED);
1746 if (!util_format_is_pure_integer(format) &&
1747 !util_format_is_depth_or_stencil(format))
1748 retval |= usage & PIPE_BIND_BLENDABLE;
1749 }
1750
1751 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1752 si_is_zs_format_supported(format)) {
1753 retval |= PIPE_BIND_DEPTH_STENCIL;
1754 }
1755
1756 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1757 si_is_vertex_format_supported(screen, format)) {
1758 retval |= PIPE_BIND_VERTEX_BUFFER;
1759 }
1760
1761 if (usage & PIPE_BIND_TRANSFER_READ)
1762 retval |= PIPE_BIND_TRANSFER_READ;
1763 if (usage & PIPE_BIND_TRANSFER_WRITE)
1764 retval |= PIPE_BIND_TRANSFER_WRITE;
1765
1766 return retval == usage;
1767 }
1768
1769 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1770 {
1771 unsigned tile_mode_index = 0;
1772
1773 if (stencil) {
1774 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1775 } else {
1776 tile_mode_index = rtex->surface.tiling_index[level];
1777 }
1778 return tile_mode_index;
1779 }
1780
1781 /*
1782 * framebuffer handling
1783 */
1784
1785 static void si_initialize_color_surface(struct si_context *sctx,
1786 struct r600_surface *surf)
1787 {
1788 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1789 unsigned level = surf->base.u.tex.level;
1790 uint64_t offset = rtex->surface.level[level].offset;
1791 unsigned pitch, slice;
1792 unsigned color_info, color_attrib, color_pitch, color_view;
1793 unsigned tile_mode_index;
1794 unsigned format, swap, ntype, endian;
1795 const struct util_format_description *desc;
1796 int i;
1797 unsigned blend_clamp = 0, blend_bypass = 0;
1798 unsigned max_comp_size;
1799
1800 /* Layered rendering doesn't work with LINEAR_GENERAL.
1801 * (LINEAR_ALIGNED and others work) */
1802 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1803 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1804 offset += rtex->surface.level[level].slice_size *
1805 surf->base.u.tex.first_layer;
1806 color_view = 0;
1807 } else {
1808 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1809 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1810 }
1811
1812 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1813 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1814 if (slice) {
1815 slice = slice - 1;
1816 }
1817
1818 tile_mode_index = si_tile_mode_index(rtex, level, false);
1819
1820 desc = util_format_description(surf->base.format);
1821 for (i = 0; i < 4; i++) {
1822 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1823 break;
1824 }
1825 }
1826 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1827 ntype = V_028C70_NUMBER_FLOAT;
1828 } else {
1829 ntype = V_028C70_NUMBER_UNORM;
1830 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1831 ntype = V_028C70_NUMBER_SRGB;
1832 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1833 if (desc->channel[i].pure_integer) {
1834 ntype = V_028C70_NUMBER_SINT;
1835 } else {
1836 assert(desc->channel[i].normalized);
1837 ntype = V_028C70_NUMBER_SNORM;
1838 }
1839 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1840 if (desc->channel[i].pure_integer) {
1841 ntype = V_028C70_NUMBER_UINT;
1842 } else {
1843 assert(desc->channel[i].normalized);
1844 ntype = V_028C70_NUMBER_UNORM;
1845 }
1846 }
1847 }
1848
1849 format = si_translate_colorformat(surf->base.format);
1850 if (format == V_028C70_COLOR_INVALID) {
1851 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1852 }
1853 assert(format != V_028C70_COLOR_INVALID);
1854 swap = r600_translate_colorswap(surf->base.format);
1855 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1856 endian = V_028C70_ENDIAN_NONE;
1857 } else {
1858 endian = si_colorformat_endian_swap(format);
1859 }
1860
1861 /* blend clamp should be set for all NORM/SRGB types */
1862 if (ntype == V_028C70_NUMBER_UNORM ||
1863 ntype == V_028C70_NUMBER_SNORM ||
1864 ntype == V_028C70_NUMBER_SRGB)
1865 blend_clamp = 1;
1866
1867 /* set blend bypass according to docs if SINT/UINT or
1868 8/24 COLOR variants */
1869 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1870 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1871 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1872 blend_clamp = 0;
1873 blend_bypass = 1;
1874 }
1875
1876 color_info = S_028C70_FORMAT(format) |
1877 S_028C70_COMP_SWAP(swap) |
1878 S_028C70_BLEND_CLAMP(blend_clamp) |
1879 S_028C70_BLEND_BYPASS(blend_bypass) |
1880 S_028C70_NUMBER_TYPE(ntype) |
1881 S_028C70_ENDIAN(endian);
1882
1883 color_pitch = S_028C64_TILE_MAX(pitch);
1884
1885 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1886 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1887
1888 if (rtex->resource.b.b.nr_samples > 1) {
1889 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1890
1891 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1892 S_028C74_NUM_FRAGMENTS(log_samples);
1893
1894 if (rtex->fmask.size) {
1895 color_info |= S_028C70_COMPRESSION(1);
1896 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1897
1898 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1899
1900 if (sctx->b.chip_class == SI) {
1901 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1902 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1903 }
1904 if (sctx->b.chip_class >= CIK) {
1905 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1906 }
1907 }
1908 }
1909
1910 offset += rtex->resource.gpu_address;
1911
1912 surf->cb_color_base = offset >> 8;
1913 surf->cb_color_pitch = color_pitch;
1914 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1915 surf->cb_color_view = color_view;
1916 surf->cb_color_info = color_info;
1917 surf->cb_color_attrib = color_attrib;
1918
1919 if (sctx->b.chip_class >= VI)
1920 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1921
1922 if (rtex->fmask.size) {
1923 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1924 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1925 } else {
1926 /* This must be set for fast clear to work without FMASK. */
1927 surf->cb_color_fmask = surf->cb_color_base;
1928 surf->cb_color_fmask_slice = surf->cb_color_slice;
1929 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1930
1931 if (sctx->b.chip_class == SI) {
1932 unsigned bankh = util_logbase2(rtex->surface.bankh);
1933 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1934 }
1935
1936 if (sctx->b.chip_class >= CIK) {
1937 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1938 }
1939 }
1940
1941 /* Determine pixel shader export format */
1942 max_comp_size = si_colorformat_max_comp_size(format);
1943 if (ntype == V_028C70_NUMBER_SRGB ||
1944 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1945 max_comp_size <= 10) ||
1946 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1947 surf->export_16bpc = true;
1948 }
1949
1950 surf->color_initialized = true;
1951 }
1952
1953 static void si_init_depth_surface(struct si_context *sctx,
1954 struct r600_surface *surf)
1955 {
1956 struct si_screen *sscreen = sctx->screen;
1957 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1958 unsigned level = surf->base.u.tex.level;
1959 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1960 unsigned format, tile_mode_index, array_mode;
1961 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1962 uint32_t z_info, s_info, db_depth_info;
1963 uint64_t z_offs, s_offs;
1964 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1965
1966 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1967 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1968 case PIPE_FORMAT_X8Z24_UNORM:
1969 case PIPE_FORMAT_Z24X8_UNORM:
1970 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1971 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1972 break;
1973 case PIPE_FORMAT_Z32_FLOAT:
1974 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1975 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1976 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1977 break;
1978 case PIPE_FORMAT_Z16_UNORM:
1979 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1980 break;
1981 default:
1982 assert(0);
1983 }
1984
1985 format = si_translate_dbformat(rtex->resource.b.b.format);
1986
1987 if (format == V_028040_Z_INVALID) {
1988 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1989 }
1990 assert(format != V_028040_Z_INVALID);
1991
1992 s_offs = z_offs = rtex->resource.gpu_address;
1993 z_offs += rtex->surface.level[level].offset;
1994 s_offs += rtex->surface.stencil_level[level].offset;
1995
1996 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1997
1998 z_info = S_028040_FORMAT(format);
1999 if (rtex->resource.b.b.nr_samples > 1) {
2000 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2001 }
2002
2003 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2004 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2005 else
2006 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2007
2008 if (sctx->b.chip_class >= CIK) {
2009 switch (rtex->surface.level[level].mode) {
2010 case RADEON_SURF_MODE_2D:
2011 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2012 break;
2013 case RADEON_SURF_MODE_1D:
2014 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2015 case RADEON_SURF_MODE_LINEAR:
2016 default:
2017 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2018 break;
2019 }
2020 tile_split = rtex->surface.tile_split;
2021 stile_split = rtex->surface.stencil_tile_split;
2022 macro_aspect = rtex->surface.mtilea;
2023 bankw = rtex->surface.bankw;
2024 bankh = rtex->surface.bankh;
2025 tile_split = cik_tile_split(tile_split);
2026 stile_split = cik_tile_split(stile_split);
2027 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2028 bankw = cik_bank_wh(bankw);
2029 bankh = cik_bank_wh(bankh);
2030 nbanks = si_num_banks(sscreen, rtex);
2031 tile_mode_index = si_tile_mode_index(rtex, level, false);
2032 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2033
2034 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2035 S_02803C_PIPE_CONFIG(pipe_config) |
2036 S_02803C_BANK_WIDTH(bankw) |
2037 S_02803C_BANK_HEIGHT(bankh) |
2038 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2039 S_02803C_NUM_BANKS(nbanks);
2040 z_info |= S_028040_TILE_SPLIT(tile_split);
2041 s_info |= S_028044_TILE_SPLIT(stile_split);
2042 } else {
2043 tile_mode_index = si_tile_mode_index(rtex, level, false);
2044 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2045 tile_mode_index = si_tile_mode_index(rtex, level, true);
2046 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2047 }
2048
2049 /* HiZ aka depth buffer htile */
2050 /* use htile only for first level */
2051 if (rtex->htile_buffer && !level) {
2052 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2053 S_028040_ALLOW_EXPCLEAR(1);
2054
2055 /* Use all of the htile_buffer for depth, because we don't
2056 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2057 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2058
2059 uint64_t va = rtex->htile_buffer->gpu_address;
2060 db_htile_data_base = va >> 8;
2061 db_htile_surface = S_028ABC_FULL_CACHE(1);
2062 } else {
2063 db_htile_data_base = 0;
2064 db_htile_surface = 0;
2065 }
2066
2067 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2068
2069 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2070 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2071 surf->db_htile_data_base = db_htile_data_base;
2072 surf->db_depth_info = db_depth_info;
2073 surf->db_z_info = z_info;
2074 surf->db_stencil_info = s_info;
2075 surf->db_depth_base = z_offs >> 8;
2076 surf->db_stencil_base = s_offs >> 8;
2077 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2078 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2079 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2080 levelinfo->nblk_y) / 64 - 1);
2081 surf->db_htile_surface = db_htile_surface;
2082 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2083
2084 surf->depth_initialized = true;
2085 }
2086
2087 static void si_set_framebuffer_state(struct pipe_context *ctx,
2088 const struct pipe_framebuffer_state *state)
2089 {
2090 struct si_context *sctx = (struct si_context *)ctx;
2091 struct pipe_constant_buffer constbuf = {0};
2092 struct r600_surface *surf = NULL;
2093 struct r600_texture *rtex;
2094 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2095 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2096 int i;
2097
2098 /* Only flush TC when changing the framebuffer state, because
2099 * the only client not using TC that can change textures is
2100 * the framebuffer.
2101 *
2102 * Flush all CB and DB caches here because all buffers can be used
2103 * for write by both TC (with shader image stores) and CB/DB.
2104 */
2105 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2106 SI_CONTEXT_INV_TC_L2 |
2107 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2108
2109 /* Take the maximum of the old and new count. If the new count is lower,
2110 * dirtying is needed to disable the unbound colorbuffers.
2111 */
2112 sctx->framebuffer.dirty_cbufs |=
2113 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2114 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2115
2116 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2117
2118 sctx->framebuffer.export_16bpc = 0;
2119 sctx->framebuffer.compressed_cb_mask = 0;
2120 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2121 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2122 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2123 util_format_is_pure_integer(state->cbufs[0]->format);
2124
2125 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2126 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2127
2128 for (i = 0; i < state->nr_cbufs; i++) {
2129 if (!state->cbufs[i])
2130 continue;
2131
2132 surf = (struct r600_surface*)state->cbufs[i];
2133 rtex = (struct r600_texture*)surf->base.texture;
2134
2135 if (!surf->color_initialized) {
2136 si_initialize_color_surface(sctx, surf);
2137 }
2138
2139 if (surf->export_16bpc) {
2140 sctx->framebuffer.export_16bpc |= 1 << i;
2141 }
2142
2143 if (rtex->fmask.size && rtex->cmask.size) {
2144 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2145 }
2146 r600_context_add_resource_size(ctx, surf->base.texture);
2147 }
2148 /* Set the 16BPC export for possible dual-src blending. */
2149 if (i == 1 && surf && surf->export_16bpc) {
2150 sctx->framebuffer.export_16bpc |= 1 << 1;
2151 }
2152
2153 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2154
2155 if (state->zsbuf) {
2156 surf = (struct r600_surface*)state->zsbuf;
2157
2158 if (!surf->depth_initialized) {
2159 si_init_depth_surface(sctx, surf);
2160 }
2161 r600_context_add_resource_size(ctx, surf->base.texture);
2162 }
2163
2164 si_update_fb_rs_state(sctx);
2165 si_update_fb_blend_state(sctx);
2166
2167 sctx->framebuffer.atom.num_dw = state->nr_cbufs*16 + (8 - state->nr_cbufs)*3;
2168 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2169 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2170 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2171 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2172
2173 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2174 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2175 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2176
2177 /* Set sample locations as fragment shader constants. */
2178 switch (sctx->framebuffer.nr_samples) {
2179 case 1:
2180 constbuf.user_buffer = sctx->b.sample_locations_1x;
2181 break;
2182 case 2:
2183 constbuf.user_buffer = sctx->b.sample_locations_2x;
2184 break;
2185 case 4:
2186 constbuf.user_buffer = sctx->b.sample_locations_4x;
2187 break;
2188 case 8:
2189 constbuf.user_buffer = sctx->b.sample_locations_8x;
2190 break;
2191 case 16:
2192 constbuf.user_buffer = sctx->b.sample_locations_16x;
2193 break;
2194 default:
2195 assert(0);
2196 }
2197 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2198 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2199 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2200
2201 /* Smoothing (only possible with nr_samples == 1) uses the same
2202 * sample locations as the MSAA it simulates.
2203 *
2204 * Therefore, don't update the sample locations when
2205 * transitioning from no AA to smoothing-equivalent AA, and
2206 * vice versa.
2207 */
2208 if ((sctx->framebuffer.nr_samples != 1 ||
2209 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2210 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2211 old_nr_samples != 1))
2212 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2213 }
2214 }
2215
2216 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2217 {
2218 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2219 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2220 unsigned i, nr_cbufs = state->nr_cbufs;
2221 struct r600_texture *tex = NULL;
2222 struct r600_surface *cb = NULL;
2223
2224 /* Colorbuffers. */
2225 for (i = 0; i < nr_cbufs; i++) {
2226 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2227 continue;
2228
2229 cb = (struct r600_surface*)state->cbufs[i];
2230 if (!cb) {
2231 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2232 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2233 continue;
2234 }
2235
2236 tex = (struct r600_texture *)cb->base.texture;
2237 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2238 &tex->resource, RADEON_USAGE_READWRITE,
2239 tex->surface.nsamples > 1 ?
2240 RADEON_PRIO_COLOR_BUFFER_MSAA :
2241 RADEON_PRIO_COLOR_BUFFER);
2242
2243 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2244 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2245 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2246 RADEON_PRIO_COLOR_META);
2247 }
2248
2249 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2250 sctx->b.chip_class >= VI ? 14 : 13);
2251 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2252 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2253 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2254 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2255 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2256 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2257 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2258 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2259 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2260 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2261 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2262 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2263 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2264
2265 if (sctx->b.chip_class >= VI)
2266 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2267 }
2268 /* set CB_COLOR1_INFO for possible dual-src blending */
2269 if (i == 1 && state->cbufs[0] &&
2270 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2271 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2272 cb->cb_color_info | tex->cb_color_info);
2273 i++;
2274 }
2275 for (; i < 8 ; i++)
2276 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2277 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2278
2279 /* ZS buffer. */
2280 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2281 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2282 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2283
2284 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2285 &rtex->resource, RADEON_USAGE_READWRITE,
2286 zb->base.texture->nr_samples > 1 ?
2287 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2288 RADEON_PRIO_DEPTH_BUFFER);
2289
2290 if (zb->db_htile_data_base) {
2291 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2292 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2293 RADEON_PRIO_DEPTH_META);
2294 }
2295
2296 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2297 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2298
2299 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2300 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2301 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2302 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2303 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2304 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2305 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2306 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2307 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2308 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2309 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2310
2311 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2312 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2313 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2314 zb->pa_su_poly_offset_db_fmt_cntl);
2315 } else if (sctx->framebuffer.dirty_zsbuf) {
2316 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2317 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2318 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2319 }
2320
2321 /* Framebuffer dimensions. */
2322 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2323 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2324 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2325
2326 sctx->framebuffer.dirty_cbufs = 0;
2327 sctx->framebuffer.dirty_zsbuf = false;
2328 }
2329
2330 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2331 struct r600_atom *atom)
2332 {
2333 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2334 unsigned nr_samples = sctx->framebuffer.nr_samples;
2335
2336 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2337 SI_NUM_SMOOTH_AA_SAMPLES);
2338 }
2339
2340 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2341 {
2342 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2343
2344 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2345 sctx->ps_iter_samples,
2346 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2347 }
2348
2349
2350 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2351 {
2352 struct si_context *sctx = (struct si_context *)ctx;
2353
2354 if (sctx->ps_iter_samples == min_samples)
2355 return;
2356
2357 sctx->ps_iter_samples = min_samples;
2358
2359 if (sctx->framebuffer.nr_samples > 1)
2360 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2361 }
2362
2363 /*
2364 * Samplers
2365 */
2366
2367 /**
2368 * Create a sampler view.
2369 *
2370 * @param ctx context
2371 * @param texture texture
2372 * @param state sampler view template
2373 * @param width0 width0 override (for compressed textures as int)
2374 * @param height0 height0 override (for compressed textures as int)
2375 * @param force_level set the base address to the level (for compressed textures)
2376 */
2377 struct pipe_sampler_view *
2378 si_create_sampler_view_custom(struct pipe_context *ctx,
2379 struct pipe_resource *texture,
2380 const struct pipe_sampler_view *state,
2381 unsigned width0, unsigned height0,
2382 unsigned force_level)
2383 {
2384 struct si_context *sctx = (struct si_context*)ctx;
2385 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2386 struct r600_texture *tmp = (struct r600_texture*)texture;
2387 const struct util_format_description *desc;
2388 unsigned format, num_format, base_level, first_level, last_level;
2389 uint32_t pitch = 0;
2390 unsigned char state_swizzle[4], swizzle[4];
2391 unsigned height, depth, width;
2392 enum pipe_format pipe_format = state->format;
2393 struct radeon_surf_level *surflevel;
2394 int first_non_void;
2395 uint64_t va;
2396
2397 if (view == NULL)
2398 return NULL;
2399
2400 /* initialize base object */
2401 view->base = *state;
2402 view->base.texture = NULL;
2403 view->base.reference.count = 1;
2404 view->base.context = ctx;
2405
2406 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2407 if (!texture) {
2408 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2409 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2410 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2411 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2412 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2413 return &view->base;
2414 }
2415
2416 pipe_resource_reference(&view->base.texture, texture);
2417 view->resource = &tmp->resource;
2418
2419 /* Buffer resource. */
2420 if (texture->target == PIPE_BUFFER) {
2421 unsigned stride, num_records;
2422
2423 desc = util_format_description(state->format);
2424 first_non_void = util_format_get_first_non_void_channel(state->format);
2425 stride = desc->block.bits / 8;
2426 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2427 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2428 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2429
2430 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2431 num_records = MIN2(num_records, texture->width0 / stride);
2432
2433 if (sctx->b.chip_class >= VI)
2434 num_records *= stride;
2435
2436 view->state[4] = va;
2437 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2438 S_008F04_STRIDE(stride);
2439 view->state[6] = num_records;
2440 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2441 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2442 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2443 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2444 S_008F0C_NUM_FORMAT(num_format) |
2445 S_008F0C_DATA_FORMAT(format);
2446
2447 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2448 return &view->base;
2449 }
2450
2451 state_swizzle[0] = state->swizzle_r;
2452 state_swizzle[1] = state->swizzle_g;
2453 state_swizzle[2] = state->swizzle_b;
2454 state_swizzle[3] = state->swizzle_a;
2455
2456 surflevel = tmp->surface.level;
2457
2458 /* Texturing with separate depth and stencil. */
2459 if (tmp->is_depth && !tmp->is_flushing_texture) {
2460 switch (pipe_format) {
2461 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2462 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2463 break;
2464 case PIPE_FORMAT_X8Z24_UNORM:
2465 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2466 /* Z24 is always stored like this. */
2467 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2468 break;
2469 case PIPE_FORMAT_X24S8_UINT:
2470 case PIPE_FORMAT_S8X24_UINT:
2471 case PIPE_FORMAT_X32_S8X24_UINT:
2472 pipe_format = PIPE_FORMAT_S8_UINT;
2473 surflevel = tmp->surface.stencil_level;
2474 break;
2475 default:;
2476 }
2477 }
2478
2479 desc = util_format_description(pipe_format);
2480
2481 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2482 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2483 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2484
2485 switch (pipe_format) {
2486 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2487 case PIPE_FORMAT_X24S8_UINT:
2488 case PIPE_FORMAT_X32_S8X24_UINT:
2489 case PIPE_FORMAT_X8Z24_UNORM:
2490 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2491 break;
2492 default:
2493 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2494 }
2495 } else {
2496 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2497 }
2498
2499 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2500
2501 switch (pipe_format) {
2502 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2503 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2504 break;
2505 default:
2506 if (first_non_void < 0) {
2507 if (util_format_is_compressed(pipe_format)) {
2508 switch (pipe_format) {
2509 case PIPE_FORMAT_DXT1_SRGB:
2510 case PIPE_FORMAT_DXT1_SRGBA:
2511 case PIPE_FORMAT_DXT3_SRGBA:
2512 case PIPE_FORMAT_DXT5_SRGBA:
2513 case PIPE_FORMAT_BPTC_SRGBA:
2514 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2515 break;
2516 case PIPE_FORMAT_RGTC1_SNORM:
2517 case PIPE_FORMAT_LATC1_SNORM:
2518 case PIPE_FORMAT_RGTC2_SNORM:
2519 case PIPE_FORMAT_LATC2_SNORM:
2520 /* implies float, so use SNORM/UNORM to determine
2521 whether data is signed or not */
2522 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2523 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2524 break;
2525 default:
2526 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2527 break;
2528 }
2529 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2530 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2531 } else {
2532 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2533 }
2534 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2535 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2536 } else {
2537 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2538
2539 switch (desc->channel[first_non_void].type) {
2540 case UTIL_FORMAT_TYPE_FLOAT:
2541 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2542 break;
2543 case UTIL_FORMAT_TYPE_SIGNED:
2544 if (desc->channel[first_non_void].normalized)
2545 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2546 else if (desc->channel[first_non_void].pure_integer)
2547 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2548 else
2549 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2550 break;
2551 case UTIL_FORMAT_TYPE_UNSIGNED:
2552 if (desc->channel[first_non_void].normalized)
2553 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2554 else if (desc->channel[first_non_void].pure_integer)
2555 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2556 else
2557 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2558 }
2559 }
2560 }
2561
2562 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2563 if (format == ~0) {
2564 format = 0;
2565 }
2566
2567 base_level = 0;
2568 first_level = state->u.tex.first_level;
2569 last_level = state->u.tex.last_level;
2570 width = width0;
2571 height = height0;
2572 depth = texture->depth0;
2573
2574 if (force_level) {
2575 assert(force_level == first_level &&
2576 force_level == last_level);
2577 base_level = force_level;
2578 first_level = 0;
2579 last_level = 0;
2580 width = u_minify(width, force_level);
2581 height = u_minify(height, force_level);
2582 depth = u_minify(depth, force_level);
2583 }
2584
2585 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2586
2587 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2588 height = 1;
2589 depth = texture->array_size;
2590 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2591 depth = texture->array_size;
2592 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2593 depth = texture->array_size / 6;
2594
2595 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2596
2597 view->state[0] = va >> 8;
2598 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2599 S_008F14_DATA_FORMAT(format) |
2600 S_008F14_NUM_FORMAT(num_format));
2601 view->state[2] = (S_008F18_WIDTH(width - 1) |
2602 S_008F18_HEIGHT(height - 1));
2603 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2604 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2605 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2606 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2607 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2608 0 : first_level) |
2609 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2610 util_logbase2(texture->nr_samples) :
2611 last_level) |
2612 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2613 S_008F1C_POW2_PAD(texture->last_level > 0) |
2614 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2615 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2616 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2617 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2618 view->state[6] = 0;
2619 view->state[7] = 0;
2620
2621 /* Initialize the sampler view for FMASK. */
2622 if (tmp->fmask.size) {
2623 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2624 uint32_t fmask_format;
2625
2626 switch (texture->nr_samples) {
2627 case 2:
2628 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2629 break;
2630 case 4:
2631 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2632 break;
2633 case 8:
2634 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2635 break;
2636 default:
2637 assert(0);
2638 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2639 }
2640
2641 view->fmask_state[0] = va >> 8;
2642 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2643 S_008F14_DATA_FORMAT(fmask_format) |
2644 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2645 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2646 S_008F18_HEIGHT(height - 1);
2647 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2648 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2649 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2650 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2651 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2652 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2653 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2654 S_008F20_PITCH(tmp->fmask.pitch - 1);
2655 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2656 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2657 view->fmask_state[6] = 0;
2658 view->fmask_state[7] = 0;
2659 }
2660
2661 return &view->base;
2662 }
2663
2664 static struct pipe_sampler_view *
2665 si_create_sampler_view(struct pipe_context *ctx,
2666 struct pipe_resource *texture,
2667 const struct pipe_sampler_view *state)
2668 {
2669 return si_create_sampler_view_custom(ctx, texture, state,
2670 texture ? texture->width0 : 0,
2671 texture ? texture->height0 : 0, 0);
2672 }
2673
2674 static void si_sampler_view_destroy(struct pipe_context *ctx,
2675 struct pipe_sampler_view *state)
2676 {
2677 struct si_sampler_view *view = (struct si_sampler_view *)state;
2678
2679 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2680 LIST_DELINIT(&view->list);
2681
2682 pipe_resource_reference(&state->texture, NULL);
2683 FREE(view);
2684 }
2685
2686 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2687 {
2688 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2689 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2690 (linear_filter &&
2691 (wrap == PIPE_TEX_WRAP_CLAMP ||
2692 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2693 }
2694
2695 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2696 {
2697 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2698 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2699
2700 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2701 state->border_color.ui[2] || state->border_color.ui[3]) &&
2702 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2703 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2704 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2705 }
2706
2707 static void *si_create_sampler_state(struct pipe_context *ctx,
2708 const struct pipe_sampler_state *state)
2709 {
2710 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2711 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2712 unsigned border_color_type;
2713
2714 if (rstate == NULL) {
2715 return NULL;
2716 }
2717
2718 if (sampler_state_needs_border_color(state))
2719 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2720 else
2721 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2722
2723 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2724 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2725 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2726 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2727 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2728 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2729 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2730 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2731 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2732 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2733 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2734 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2735 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2736 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2737
2738 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2739 memcpy(rstate->border_color, state->border_color.ui,
2740 sizeof(rstate->border_color));
2741 }
2742
2743 return rstate;
2744 }
2745
2746 /* Upload border colors and update the pointers in resource descriptors.
2747 * There can only be 4096 border colors per context.
2748 *
2749 * XXX: This is broken if the buffer gets reallocated.
2750 */
2751 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2752 void **states)
2753 {
2754 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2755 uint32_t *border_color_table = NULL;
2756 int i, j;
2757
2758 for (i = 0; i < count; i++) {
2759 if (rstates[i] &&
2760 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2761 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2762 if (!sctx->border_color_table ||
2763 ((sctx->border_color_offset + count - i) &
2764 C_008F3C_BORDER_COLOR_PTR)) {
2765 r600_resource_reference(&sctx->border_color_table, NULL);
2766 sctx->border_color_offset = 0;
2767
2768 sctx->border_color_table =
2769 si_resource_create_custom(&sctx->screen->b.b,
2770 PIPE_USAGE_DYNAMIC,
2771 4096 * 4 * 4);
2772 }
2773
2774 if (!border_color_table) {
2775 border_color_table =
2776 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2777 sctx->b.rings.gfx.cs,
2778 PIPE_TRANSFER_WRITE |
2779 PIPE_TRANSFER_UNSYNCHRONIZED);
2780 }
2781
2782 for (j = 0; j < 4; j++) {
2783 border_color_table[4 * sctx->border_color_offset + j] =
2784 util_le32_to_cpu(rstates[i]->border_color[j]);
2785 }
2786
2787 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2788 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2789 }
2790 }
2791
2792 if (border_color_table) {
2793 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2794
2795 uint64_t va_offset = sctx->border_color_table->gpu_address;
2796
2797 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2798 if (sctx->b.chip_class >= CIK)
2799 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2800 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2801 RADEON_PRIO_SHADER_DATA);
2802 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2803 }
2804 }
2805
2806 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2807 unsigned start, unsigned count,
2808 void **states)
2809 {
2810 struct si_context *sctx = (struct si_context *)ctx;
2811
2812 if (!count || shader >= SI_NUM_SHADERS)
2813 return;
2814
2815 si_set_border_colors(sctx, count, states);
2816 si_set_sampler_descriptors(sctx, shader, start, count, states);
2817 }
2818
2819 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2820 {
2821 struct si_context *sctx = (struct si_context *)ctx;
2822 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2823 struct si_pm4_state *pm4 = &state->pm4;
2824 uint16_t mask = sample_mask;
2825
2826 if (state == NULL)
2827 return;
2828
2829 state->sample_mask = mask;
2830 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2831 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2832
2833 si_pm4_set_state(sctx, sample_mask, state);
2834 }
2835
2836 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2837 {
2838 free(state);
2839 }
2840
2841 /*
2842 * Vertex elements & buffers
2843 */
2844
2845 static void *si_create_vertex_elements(struct pipe_context *ctx,
2846 unsigned count,
2847 const struct pipe_vertex_element *elements)
2848 {
2849 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2850 int i;
2851
2852 assert(count < SI_MAX_ATTRIBS);
2853 if (!v)
2854 return NULL;
2855
2856 v->count = count;
2857 for (i = 0; i < count; ++i) {
2858 const struct util_format_description *desc;
2859 unsigned data_format, num_format;
2860 int first_non_void;
2861
2862 desc = util_format_description(elements[i].src_format);
2863 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2864 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2865 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2866
2867 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2868 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2869 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2870 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2871 S_008F0C_NUM_FORMAT(num_format) |
2872 S_008F0C_DATA_FORMAT(data_format);
2873 v->format_size[i] = desc->block.bits / 8;
2874 }
2875 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2876
2877 return v;
2878 }
2879
2880 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2881 {
2882 struct si_context *sctx = (struct si_context *)ctx;
2883 struct si_vertex_element *v = (struct si_vertex_element*)state;
2884
2885 sctx->vertex_elements = v;
2886 sctx->vertex_buffers_dirty = true;
2887 }
2888
2889 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2890 {
2891 struct si_context *sctx = (struct si_context *)ctx;
2892
2893 if (sctx->vertex_elements == state)
2894 sctx->vertex_elements = NULL;
2895 FREE(state);
2896 }
2897
2898 static void si_set_vertex_buffers(struct pipe_context *ctx,
2899 unsigned start_slot, unsigned count,
2900 const struct pipe_vertex_buffer *buffers)
2901 {
2902 struct si_context *sctx = (struct si_context *)ctx;
2903 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2904 int i;
2905
2906 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2907
2908 if (buffers) {
2909 for (i = 0; i < count; i++) {
2910 const struct pipe_vertex_buffer *src = buffers + i;
2911 struct pipe_vertex_buffer *dsti = dst + i;
2912
2913 pipe_resource_reference(&dsti->buffer, src->buffer);
2914 dsti->buffer_offset = src->buffer_offset;
2915 dsti->stride = src->stride;
2916 r600_context_add_resource_size(ctx, src->buffer);
2917 }
2918 } else {
2919 for (i = 0; i < count; i++) {
2920 pipe_resource_reference(&dst[i].buffer, NULL);
2921 }
2922 }
2923 sctx->vertex_buffers_dirty = true;
2924 }
2925
2926 static void si_set_index_buffer(struct pipe_context *ctx,
2927 const struct pipe_index_buffer *ib)
2928 {
2929 struct si_context *sctx = (struct si_context *)ctx;
2930
2931 if (ib) {
2932 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2933 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2934 r600_context_add_resource_size(ctx, ib->buffer);
2935 } else {
2936 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2937 }
2938 }
2939
2940 /*
2941 * Misc
2942 */
2943 static void si_set_polygon_stipple(struct pipe_context *ctx,
2944 const struct pipe_poly_stipple *state)
2945 {
2946 struct si_context *sctx = (struct si_context *)ctx;
2947 struct pipe_resource *tex;
2948 struct pipe_sampler_view *view;
2949 bool is_zero = true;
2950 bool is_one = true;
2951 int i;
2952
2953 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2954 * the resource is NULL/invalid. Take advantage of this fact and skip
2955 * texture allocation if the stipple pattern is constant.
2956 *
2957 * This is an optimization for the common case when stippling isn't
2958 * used but set_polygon_stipple is still called by st/mesa.
2959 */
2960 for (i = 0; i < Elements(state->stipple); i++) {
2961 is_zero = is_zero && state->stipple[i] == 0;
2962 is_one = is_one && state->stipple[i] == 0xffffffff;
2963 }
2964
2965 if (is_zero || is_one) {
2966 struct pipe_sampler_view templ = {{0}};
2967
2968 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2969 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2970 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2971 /* The pattern should be inverted in the texture. */
2972 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2973
2974 view = ctx->create_sampler_view(ctx, NULL, &templ);
2975 } else {
2976 /* Create a new texture. */
2977 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2978 if (!tex)
2979 return;
2980
2981 view = util_pstipple_create_sampler_view(ctx, tex);
2982 pipe_resource_reference(&tex, NULL);
2983 }
2984
2985 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2986 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2987 pipe_sampler_view_reference(&view, NULL);
2988
2989 /* Bind the sampler state if needed. */
2990 if (!sctx->pstipple_sampler_state) {
2991 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2992 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2993 SI_POLY_STIPPLE_SAMPLER, 1,
2994 &sctx->pstipple_sampler_state);
2995 }
2996 }
2997
2998 static void si_set_tess_state(struct pipe_context *ctx,
2999 const float default_outer_level[4],
3000 const float default_inner_level[2])
3001 {
3002 struct si_context *sctx = (struct si_context *)ctx;
3003 struct pipe_constant_buffer cb;
3004 float array[8];
3005
3006 memcpy(array, default_outer_level, sizeof(float) * 4);
3007 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3008
3009 cb.buffer = NULL;
3010 cb.user_buffer = NULL;
3011 cb.buffer_size = sizeof(array);
3012
3013 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3014 (void*)array, sizeof(array),
3015 &cb.buffer_offset);
3016
3017 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3018 SI_DRIVER_STATE_CONST_BUF, &cb);
3019 pipe_resource_reference(&cb.buffer, NULL);
3020 }
3021
3022 static void si_texture_barrier(struct pipe_context *ctx)
3023 {
3024 struct si_context *sctx = (struct si_context *)ctx;
3025
3026 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3027 SI_CONTEXT_INV_TC_L2 |
3028 SI_CONTEXT_FLUSH_AND_INV_CB;
3029 }
3030
3031 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3032 {
3033 struct pipe_blend_state blend;
3034
3035 memset(&blend, 0, sizeof(blend));
3036 blend.independent_blend_enable = true;
3037 blend.rt[0].colormask = 0xf;
3038 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3039 }
3040
3041 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3042 bool include_draw_vbo)
3043 {
3044 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
3045 }
3046
3047 static void si_init_config(struct si_context *sctx);
3048
3049 void si_init_state_functions(struct si_context *sctx)
3050 {
3051 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3052 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3053
3054 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush, 24);
3055 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
3056 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs, 18);
3057 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
3058 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config, 10);
3059 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
3060 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state, 2+6*4);
3061 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors, 16*4);
3062 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports, 16*8);
3063
3064 sctx->b.b.create_blend_state = si_create_blend_state;
3065 sctx->b.b.bind_blend_state = si_bind_blend_state;
3066 sctx->b.b.delete_blend_state = si_delete_blend_state;
3067 sctx->b.b.set_blend_color = si_set_blend_color;
3068
3069 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3070 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3071 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3072
3073 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3074 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3075 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3076
3077 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3078 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3079 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3080 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3081
3082 sctx->b.b.set_clip_state = si_set_clip_state;
3083 sctx->b.b.set_scissor_states = si_set_scissor_states;
3084 sctx->b.b.set_viewport_states = si_set_viewport_states;
3085 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
3086
3087 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3088 sctx->b.b.get_sample_position = cayman_get_sample_position;
3089
3090 sctx->b.b.create_sampler_state = si_create_sampler_state;
3091 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
3092 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3093
3094 sctx->b.b.create_sampler_view = si_create_sampler_view;
3095 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3096
3097 sctx->b.b.set_sample_mask = si_set_sample_mask;
3098
3099 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3100 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3101 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3102 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3103 sctx->b.b.set_index_buffer = si_set_index_buffer;
3104
3105 sctx->b.b.texture_barrier = si_texture_barrier;
3106 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3107 sctx->b.b.set_min_samples = si_set_min_samples;
3108 sctx->b.b.set_tess_state = si_set_tess_state;
3109
3110 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3111 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3112
3113 sctx->b.b.draw_vbo = si_draw_vbo;
3114
3115 if (sctx->b.chip_class >= CIK) {
3116 sctx->b.dma_copy = cik_sdma_copy;
3117 } else {
3118 sctx->b.dma_copy = si_dma_copy;
3119 }
3120
3121 si_init_config(sctx);
3122 }
3123
3124 static void
3125 si_write_harvested_raster_configs(struct si_context *sctx,
3126 struct si_pm4_state *pm4,
3127 unsigned raster_config,
3128 unsigned raster_config_1)
3129 {
3130 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3131 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3132 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3133 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3134 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3135 unsigned rb_per_se = num_rb / num_se;
3136 unsigned se_mask[4];
3137 unsigned se;
3138
3139 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3140 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3141 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3142 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3143
3144 assert(num_se == 1 || num_se == 2 || num_se == 4);
3145 assert(sh_per_se == 1 || sh_per_se == 2);
3146 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3147
3148 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3149 * fields are for, so I'm leaving them as their default
3150 * values. */
3151
3152 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3153 (!se_mask[2] && !se_mask[3]))) {
3154 raster_config_1 &= C_028354_SE_PAIR_MAP;
3155
3156 if (!se_mask[0] && !se_mask[1]) {
3157 raster_config_1 |=
3158 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3159 } else {
3160 raster_config_1 |=
3161 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3162 }
3163 }
3164
3165 for (se = 0; se < num_se; se++) {
3166 unsigned raster_config_se = raster_config;
3167 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3168 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3169 int idx = (se / 2) * 2;
3170
3171 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3172 raster_config_se &= C_028350_SE_MAP;
3173
3174 if (!se_mask[idx]) {
3175 raster_config_se |=
3176 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3177 } else {
3178 raster_config_se |=
3179 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3180 }
3181 }
3182
3183 pkr0_mask &= rb_mask;
3184 pkr1_mask &= rb_mask;
3185 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3186 raster_config_se &= C_028350_PKR_MAP;
3187
3188 if (!pkr0_mask) {
3189 raster_config_se |=
3190 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3191 } else {
3192 raster_config_se |=
3193 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3194 }
3195 }
3196
3197 if (rb_per_se >= 2) {
3198 unsigned rb0_mask = 1 << (se * rb_per_se);
3199 unsigned rb1_mask = rb0_mask << 1;
3200
3201 rb0_mask &= rb_mask;
3202 rb1_mask &= rb_mask;
3203 if (!rb0_mask || !rb1_mask) {
3204 raster_config_se &= C_028350_RB_MAP_PKR0;
3205
3206 if (!rb0_mask) {
3207 raster_config_se |=
3208 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3209 } else {
3210 raster_config_se |=
3211 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3212 }
3213 }
3214
3215 if (rb_per_se > 2) {
3216 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3217 rb1_mask = rb0_mask << 1;
3218 rb0_mask &= rb_mask;
3219 rb1_mask &= rb_mask;
3220 if (!rb0_mask || !rb1_mask) {
3221 raster_config_se &= C_028350_RB_MAP_PKR1;
3222
3223 if (!rb0_mask) {
3224 raster_config_se |=
3225 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3226 } else {
3227 raster_config_se |=
3228 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3229 }
3230 }
3231 }
3232 }
3233
3234 /* GRBM_GFX_INDEX is privileged on VI */
3235 if (sctx->b.chip_class <= CIK)
3236 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3237 SE_INDEX(se) | SH_BROADCAST_WRITES |
3238 INSTANCE_BROADCAST_WRITES);
3239 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3240 if (sctx->b.chip_class >= CIK)
3241 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3242 }
3243
3244 /* GRBM_GFX_INDEX is privileged on VI */
3245 if (sctx->b.chip_class <= CIK)
3246 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3247 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3248 INSTANCE_BROADCAST_WRITES);
3249 }
3250
3251 static void si_init_config(struct si_context *sctx)
3252 {
3253 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3254 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3255 unsigned raster_config, raster_config_1;
3256 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3257 int i;
3258
3259 if (pm4 == NULL)
3260 return;
3261
3262 si_cmd_context_control(pm4);
3263
3264 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3265 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3266
3267 /* FIXME calculate these values somehow ??? */
3268 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3269 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3270 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3271
3272 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3273 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3274 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3275
3276 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3277 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3278 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3279 if (sctx->b.chip_class < CIK)
3280 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3281 S_008A14_CLIP_VTX_REORDER_ENA(1));
3282
3283 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3284 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3285
3286 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3287
3288 for (i = 0; i < 16; i++) {
3289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3291 }
3292
3293 switch (sctx->screen->b.family) {
3294 case CHIP_TAHITI:
3295 case CHIP_PITCAIRN:
3296 raster_config = 0x2a00126a;
3297 raster_config_1 = 0x00000000;
3298 break;
3299 case CHIP_VERDE:
3300 raster_config = 0x0000124a;
3301 raster_config_1 = 0x00000000;
3302 break;
3303 case CHIP_OLAND:
3304 raster_config = 0x00000082;
3305 raster_config_1 = 0x00000000;
3306 break;
3307 case CHIP_HAINAN:
3308 raster_config = 0x00000000;
3309 raster_config_1 = 0x00000000;
3310 break;
3311 case CHIP_BONAIRE:
3312 raster_config = 0x16000012;
3313 raster_config_1 = 0x00000000;
3314 break;
3315 case CHIP_HAWAII:
3316 raster_config = 0x3a00161a;
3317 raster_config_1 = 0x0000002e;
3318 break;
3319 case CHIP_FIJI:
3320 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3321 raster_config = 0x16000012; /* 0x3a00161a */
3322 raster_config_1 = 0x0000002a; /* 0x0000002e */
3323 break;
3324 case CHIP_TONGA:
3325 raster_config = 0x16000012;
3326 raster_config_1 = 0x0000002a;
3327 break;
3328 case CHIP_ICELAND:
3329 raster_config = 0x00000002;
3330 raster_config_1 = 0x00000000;
3331 break;
3332 case CHIP_CARRIZO:
3333 raster_config = 0x00000002;
3334 raster_config_1 = 0x00000000;
3335 break;
3336 case CHIP_KAVERI:
3337 /* KV should be 0x00000002, but that causes problems with radeon */
3338 raster_config = 0x00000000; /* 0x00000002 */
3339 raster_config_1 = 0x00000000;
3340 break;
3341 case CHIP_KABINI:
3342 case CHIP_MULLINS:
3343 raster_config = 0x00000000;
3344 raster_config_1 = 0x00000000;
3345 break;
3346 default:
3347 fprintf(stderr,
3348 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3349 raster_config = 0x00000000;
3350 raster_config_1 = 0x00000000;
3351 break;
3352 }
3353
3354 /* Always use the default config when all backends are enabled
3355 * (or when we failed to determine the enabled backends).
3356 */
3357 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3358 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3359 raster_config);
3360 if (sctx->b.chip_class >= CIK)
3361 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3362 raster_config_1);
3363 } else {
3364 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3365 }
3366
3367 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3368 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3369 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3370 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3371 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3372 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3373 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3374
3375 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3376 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3377 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3378 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3379 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3380 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3381 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3382 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3383 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3384 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3385 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3386 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3387 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3388
3389 /* There is a hang if stencil is used and fast stencil is enabled
3390 * regardless of whether HTILE is depth-only or not.
3391 */
3392 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3393 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3394 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3395 S_02800C_FAST_STENCIL_DISABLE(1));
3396
3397 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3398 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3399 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3400
3401 if (sctx->b.chip_class >= CIK) {
3402 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3403 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3404 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3405 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3406 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3407 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3408 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3409 }
3410
3411 if (sctx->b.chip_class >= VI) {
3412 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3413 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3414 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3415 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3416 }
3417
3418 sctx->init_config = pm4;
3419 }