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ac/gpu_info: add has_format_bc1_through_bc7
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_winsys_cs *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
91
92 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
93 * I think we don't have to do anything between IBs.
94 */
95 if (sctx->screen->dfsm_allowed &&
96 sctx->last_cb_target_mask != cb_target_mask) {
97 sctx->last_cb_target_mask = cb_target_mask;
98
99 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
100 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
101 }
102
103 if (sctx->chip_class >= VI) {
104 /* DCC MSAA workaround for blending.
105 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
106 * COMBINER_DISABLE, but that would be more complicated.
107 */
108 bool oc_disable = (sctx->chip_class == VI ||
109 sctx->chip_class == GFX9) &&
110 blend &&
111 blend->blend_enable_4bit & cb_target_mask &&
112 sctx->framebuffer.nr_samples >= 2;
113
114 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
115 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
116 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
117 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
118 }
119
120 /* RB+ register settings. */
121 if (sctx->screen->rbplus_allowed) {
122 unsigned spi_shader_col_format =
123 sctx->ps_shader.cso ?
124 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
125 unsigned sx_ps_downconvert = 0;
126 unsigned sx_blend_opt_epsilon = 0;
127 unsigned sx_blend_opt_control = 0;
128
129 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
130 struct r600_surface *surf =
131 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
132 unsigned format, swap, spi_format, colormask;
133 bool has_alpha, has_rgb;
134
135 if (!surf)
136 continue;
137
138 format = G_028C70_FORMAT(surf->cb_color_info);
139 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
140 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
141 colormask = (cb_target_mask >> (i * 4)) & 0xf;
142
143 /* Set if RGB and A are present. */
144 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
145
146 if (format == V_028C70_COLOR_8 ||
147 format == V_028C70_COLOR_16 ||
148 format == V_028C70_COLOR_32)
149 has_rgb = !has_alpha;
150 else
151 has_rgb = true;
152
153 /* Check the colormask and export format. */
154 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
155 has_rgb = false;
156 if (!(colormask & PIPE_MASK_A))
157 has_alpha = false;
158
159 if (spi_format == V_028714_SPI_SHADER_ZERO) {
160 has_rgb = false;
161 has_alpha = false;
162 }
163
164 /* Disable value checking for disabled channels. */
165 if (!has_rgb)
166 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
167 if (!has_alpha)
168 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
169
170 /* Enable down-conversion for 32bpp and smaller formats. */
171 switch (format) {
172 case V_028C70_COLOR_8:
173 case V_028C70_COLOR_8_8:
174 case V_028C70_COLOR_8_8_8_8:
175 /* For 1 and 2-channel formats, use the superset thereof. */
176 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
177 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
178 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
179 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
180 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
181 }
182 break;
183
184 case V_028C70_COLOR_5_6_5:
185 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_1_5_5_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_4_4_4_4:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_32:
206 if (swap == V_028C70_SWAP_STD &&
207 spi_format == V_028714_SPI_SHADER_32_R)
208 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
209 else if (swap == V_028C70_SWAP_ALT_REV &&
210 spi_format == V_028714_SPI_SHADER_32_AR)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
212 break;
213
214 case V_028C70_COLOR_16:
215 case V_028C70_COLOR_16_16:
216 /* For 1-channel formats, use the superset thereof. */
217 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
219 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
220 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
221 if (swap == V_028C70_SWAP_STD ||
222 swap == V_028C70_SWAP_STD_REV)
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
224 else
225 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
226 }
227 break;
228
229 case V_028C70_COLOR_10_11_11:
230 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
232 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_2_10_10_10:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
240 }
241 break;
242 }
243 }
244
245 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
246 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
247 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
248 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
249 }
250 }
251
252 /*
253 * Blender functions
254 */
255
256 static uint32_t si_translate_blend_function(int blend_func)
257 {
258 switch (blend_func) {
259 case PIPE_BLEND_ADD:
260 return V_028780_COMB_DST_PLUS_SRC;
261 case PIPE_BLEND_SUBTRACT:
262 return V_028780_COMB_SRC_MINUS_DST;
263 case PIPE_BLEND_REVERSE_SUBTRACT:
264 return V_028780_COMB_DST_MINUS_SRC;
265 case PIPE_BLEND_MIN:
266 return V_028780_COMB_MIN_DST_SRC;
267 case PIPE_BLEND_MAX:
268 return V_028780_COMB_MAX_DST_SRC;
269 default:
270 PRINT_ERR("Unknown blend function %d\n", blend_func);
271 assert(0);
272 break;
273 }
274 return 0;
275 }
276
277 static uint32_t si_translate_blend_factor(int blend_fact)
278 {
279 switch (blend_fact) {
280 case PIPE_BLENDFACTOR_ONE:
281 return V_028780_BLEND_ONE;
282 case PIPE_BLENDFACTOR_SRC_COLOR:
283 return V_028780_BLEND_SRC_COLOR;
284 case PIPE_BLENDFACTOR_SRC_ALPHA:
285 return V_028780_BLEND_SRC_ALPHA;
286 case PIPE_BLENDFACTOR_DST_ALPHA:
287 return V_028780_BLEND_DST_ALPHA;
288 case PIPE_BLENDFACTOR_DST_COLOR:
289 return V_028780_BLEND_DST_COLOR;
290 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
291 return V_028780_BLEND_SRC_ALPHA_SATURATE;
292 case PIPE_BLENDFACTOR_CONST_COLOR:
293 return V_028780_BLEND_CONSTANT_COLOR;
294 case PIPE_BLENDFACTOR_CONST_ALPHA:
295 return V_028780_BLEND_CONSTANT_ALPHA;
296 case PIPE_BLENDFACTOR_ZERO:
297 return V_028780_BLEND_ZERO;
298 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
299 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
300 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
301 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
303 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
304 case PIPE_BLENDFACTOR_INV_DST_COLOR:
305 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
306 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
307 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
308 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
309 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
310 case PIPE_BLENDFACTOR_SRC1_COLOR:
311 return V_028780_BLEND_SRC1_COLOR;
312 case PIPE_BLENDFACTOR_SRC1_ALPHA:
313 return V_028780_BLEND_SRC1_ALPHA;
314 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
315 return V_028780_BLEND_INV_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
317 return V_028780_BLEND_INV_SRC1_ALPHA;
318 default:
319 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
320 assert(0);
321 break;
322 }
323 return 0;
324 }
325
326 static uint32_t si_translate_blend_opt_function(int blend_func)
327 {
328 switch (blend_func) {
329 case PIPE_BLEND_ADD:
330 return V_028760_OPT_COMB_ADD;
331 case PIPE_BLEND_SUBTRACT:
332 return V_028760_OPT_COMB_SUBTRACT;
333 case PIPE_BLEND_REVERSE_SUBTRACT:
334 return V_028760_OPT_COMB_REVSUBTRACT;
335 case PIPE_BLEND_MIN:
336 return V_028760_OPT_COMB_MIN;
337 case PIPE_BLEND_MAX:
338 return V_028760_OPT_COMB_MAX;
339 default:
340 return V_028760_OPT_COMB_BLEND_DISABLED;
341 }
342 }
343
344 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
345 {
346 switch (blend_fact) {
347 case PIPE_BLENDFACTOR_ZERO:
348 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
349 case PIPE_BLENDFACTOR_ONE:
350 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
351 case PIPE_BLENDFACTOR_SRC_COLOR:
352 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
353 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
354 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
355 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
356 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
357 case PIPE_BLENDFACTOR_SRC_ALPHA:
358 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
359 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
360 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
363 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
364 default:
365 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
366 }
367 }
368
369 static void si_blend_check_commutativity(struct si_screen *sscreen,
370 struct si_state_blend *blend,
371 enum pipe_blend_func func,
372 enum pipe_blendfactor src,
373 enum pipe_blendfactor dst,
374 unsigned chanmask)
375 {
376 /* Src factor is allowed when it does not depend on Dst */
377 static const uint32_t src_allowed =
378 (1u << PIPE_BLENDFACTOR_ONE) |
379 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
380 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
381 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
382 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
383 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
384 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
385 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
386 (1u << PIPE_BLENDFACTOR_ZERO) |
387 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
388 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
389 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
390 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
393
394 if (dst == PIPE_BLENDFACTOR_ONE &&
395 (src_allowed & (1u << src))) {
396 /* Addition is commutative, but floating point addition isn't
397 * associative: subtle changes can be introduced via different
398 * rounding.
399 *
400 * Out-of-order is also non-deterministic, which means that
401 * this breaks OpenGL invariance requirements. So only enable
402 * out-of-order additive blending if explicitly allowed by a
403 * setting.
404 */
405 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
406 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
407 blend->commutative_4bit |= chanmask;
408 }
409 }
410
411 /**
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 */
415 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
416 unsigned *dst_factor, unsigned expected_dst,
417 unsigned replacement_src)
418 {
419 if (*src_factor == expected_dst &&
420 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
421 *src_factor = PIPE_BLENDFACTOR_ZERO;
422 *dst_factor = replacement_src;
423
424 /* Commuting the operands requires reversing subtractions. */
425 if (*func == PIPE_BLEND_SUBTRACT)
426 *func = PIPE_BLEND_REVERSE_SUBTRACT;
427 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
428 *func = PIPE_BLEND_SUBTRACT;
429 }
430 }
431
432 static bool si_blend_factor_uses_dst(unsigned factor)
433 {
434 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
435 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
436 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
437 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
438 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
439 }
440
441 static void *si_create_blend_state_mode(struct pipe_context *ctx,
442 const struct pipe_blend_state *state,
443 unsigned mode)
444 {
445 struct si_context *sctx = (struct si_context*)ctx;
446 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
447 struct si_pm4_state *pm4 = &blend->pm4;
448 uint32_t sx_mrt_blend_opt[8] = {0};
449 uint32_t color_control = 0;
450
451 if (!blend)
452 return NULL;
453
454 blend->alpha_to_coverage = state->alpha_to_coverage;
455 blend->alpha_to_one = state->alpha_to_one;
456 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
457 blend->logicop_enable = state->logicop_enable;
458
459 if (state->logicop_enable) {
460 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
461 } else {
462 color_control |= S_028808_ROP3(0xcc);
463 }
464
465 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
466 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
467 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
468 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
469 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
470 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
471
472 if (state->alpha_to_coverage)
473 blend->need_src_alpha_4bit |= 0xf;
474
475 blend->cb_target_mask = 0;
476 blend->cb_target_enabled_4bit = 0;
477
478 for (int i = 0; i < 8; i++) {
479 /* state->rt entries > 0 only written if independent blending */
480 const int j = state->independent_blend_enable ? i : 0;
481
482 unsigned eqRGB = state->rt[j].rgb_func;
483 unsigned srcRGB = state->rt[j].rgb_src_factor;
484 unsigned dstRGB = state->rt[j].rgb_dst_factor;
485 unsigned eqA = state->rt[j].alpha_func;
486 unsigned srcA = state->rt[j].alpha_src_factor;
487 unsigned dstA = state->rt[j].alpha_dst_factor;
488
489 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
490 unsigned blend_cntl = 0;
491
492 sx_mrt_blend_opt[i] =
493 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
494 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
495
496 /* Only set dual source blending for MRT0 to avoid a hang. */
497 if (i >= 1 && blend->dual_src_blend) {
498 /* Vulkan does this for dual source blending. */
499 if (i == 1)
500 blend_cntl |= S_028780_ENABLE(1);
501
502 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
503 continue;
504 }
505
506 /* Only addition and subtraction equations are supported with
507 * dual source blending.
508 */
509 if (blend->dual_src_blend &&
510 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
511 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
512 assert(!"Unsupported equation for dual source blending");
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* cb_render_state will disable unused ones */
518 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
519 if (state->rt[j].colormask)
520 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
521
522 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
523 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
524 continue;
525 }
526
527 si_blend_check_commutativity(sctx->screen, blend,
528 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
529 si_blend_check_commutativity(sctx->screen, blend,
530 eqA, srcA, dstA, 0x8 << (4 * i));
531
532 /* Blending optimizations for RB+.
533 * These transformations don't change the behavior.
534 *
535 * First, get rid of DST in the blend factors:
536 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
537 */
538 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
539 PIPE_BLENDFACTOR_DST_COLOR,
540 PIPE_BLENDFACTOR_SRC_COLOR);
541 si_blend_remove_dst(&eqA, &srcA, &dstA,
542 PIPE_BLENDFACTOR_DST_COLOR,
543 PIPE_BLENDFACTOR_SRC_COLOR);
544 si_blend_remove_dst(&eqA, &srcA, &dstA,
545 PIPE_BLENDFACTOR_DST_ALPHA,
546 PIPE_BLENDFACTOR_SRC_ALPHA);
547
548 /* Look up the ideal settings from tables. */
549 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
550 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
551 srcA_opt = si_translate_blend_opt_factor(srcA, true);
552 dstA_opt = si_translate_blend_opt_factor(dstA, true);
553
554 /* Handle interdependencies. */
555 if (si_blend_factor_uses_dst(srcRGB))
556 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
557 if (si_blend_factor_uses_dst(srcA))
558 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
559
560 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
561 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
562 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
563 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
564 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
565
566 /* Set the final value. */
567 sx_mrt_blend_opt[i] =
568 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
569 S_028760_COLOR_DST_OPT(dstRGB_opt) |
570 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
571 S_028760_ALPHA_SRC_OPT(srcA_opt) |
572 S_028760_ALPHA_DST_OPT(dstA_opt) |
573 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
574
575 /* Set blend state. */
576 blend_cntl |= S_028780_ENABLE(1);
577 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
578 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
579 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
580
581 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
582 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
583 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
584 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
585 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
586 }
587 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
588
589 blend->blend_enable_4bit |= 0xfu << (i * 4);
590
591 /* This is only important for formats without alpha. */
592 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
593 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
594 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
595 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
596 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
598 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
599 }
600
601 if (blend->cb_target_mask) {
602 color_control |= S_028808_MODE(mode);
603 } else {
604 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
605 }
606
607 if (sctx->screen->rbplus_allowed) {
608 /* Disable RB+ blend optimizations for dual source blending.
609 * Vulkan does this.
610 */
611 if (blend->dual_src_blend) {
612 for (int i = 0; i < 8; i++) {
613 sx_mrt_blend_opt[i] =
614 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
615 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
616 }
617 }
618
619 for (int i = 0; i < 8; i++)
620 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
621 sx_mrt_blend_opt[i]);
622
623 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
624 if (blend->dual_src_blend || state->logicop_enable ||
625 mode == V_028808_CB_RESOLVE)
626 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
627 }
628
629 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
630 return blend;
631 }
632
633 static void *si_create_blend_state(struct pipe_context *ctx,
634 const struct pipe_blend_state *state)
635 {
636 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
637 }
638
639 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
640 {
641 struct si_context *sctx = (struct si_context *)ctx;
642 struct si_state_blend *old_blend = sctx->queued.named.blend;
643 struct si_state_blend *blend = (struct si_state_blend *)state;
644
645 if (!state)
646 return;
647
648 si_pm4_bind_state(sctx, blend, state);
649
650 if (!old_blend ||
651 old_blend->cb_target_mask != blend->cb_target_mask ||
652 old_blend->dual_src_blend != blend->dual_src_blend ||
653 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
654 sctx->framebuffer.nr_samples >= 2 &&
655 sctx->screen->dcc_msaa_allowed))
656 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
657
658 if (!old_blend ||
659 old_blend->cb_target_mask != blend->cb_target_mask ||
660 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
661 old_blend->alpha_to_one != blend->alpha_to_one ||
662 old_blend->dual_src_blend != blend->dual_src_blend ||
663 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
664 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
665 sctx->do_update_shaders = true;
666
667 if (sctx->screen->dpbb_allowed &&
668 (!old_blend ||
669 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
670 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
671 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
672 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
673
674 if (sctx->screen->has_out_of_order_rast &&
675 (!old_blend ||
676 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
677 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
678 old_blend->commutative_4bit != blend->commutative_4bit ||
679 old_blend->logicop_enable != blend->logicop_enable)))
680 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
681 }
682
683 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
684 {
685 struct si_context *sctx = (struct si_context *)ctx;
686 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
687 }
688
689 static void si_set_blend_color(struct pipe_context *ctx,
690 const struct pipe_blend_color *state)
691 {
692 struct si_context *sctx = (struct si_context *)ctx;
693 static const struct pipe_blend_color zeros;
694
695 sctx->blend_color.state = *state;
696 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
697 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
698 }
699
700 static void si_emit_blend_color(struct si_context *sctx)
701 {
702 struct radeon_winsys_cs *cs = sctx->gfx_cs;
703
704 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
705 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
706 }
707
708 /*
709 * Clipping
710 */
711
712 static void si_set_clip_state(struct pipe_context *ctx,
713 const struct pipe_clip_state *state)
714 {
715 struct si_context *sctx = (struct si_context *)ctx;
716 struct pipe_constant_buffer cb;
717 static const struct pipe_clip_state zeros;
718
719 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
720 return;
721
722 sctx->clip_state.state = *state;
723 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
724 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
725
726 cb.buffer = NULL;
727 cb.user_buffer = state->ucp;
728 cb.buffer_offset = 0;
729 cb.buffer_size = 4*4*8;
730 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
731 pipe_resource_reference(&cb.buffer, NULL);
732 }
733
734 static void si_emit_clip_state(struct si_context *sctx)
735 {
736 struct radeon_winsys_cs *cs = sctx->gfx_cs;
737
738 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
739 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
740 }
741
742 static void si_emit_clip_regs(struct si_context *sctx)
743 {
744 struct radeon_winsys_cs *cs = sctx->gfx_cs;
745 struct si_shader *vs = si_get_vs_state(sctx);
746 struct si_shader_selector *vs_sel = vs->selector;
747 struct tgsi_shader_info *info = &vs_sel->info;
748 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
749 unsigned window_space =
750 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
751 unsigned clipdist_mask = vs_sel->clipdist_mask;
752 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
753 unsigned culldist_mask = vs_sel->culldist_mask;
754 unsigned total_mask;
755
756 if (vs->key.opt.clip_disable) {
757 assert(!info->culldist_writemask);
758 clipdist_mask = 0;
759 culldist_mask = 0;
760 }
761 total_mask = clipdist_mask | culldist_mask;
762
763 /* Clip distances on points have no effect, so need to be implemented
764 * as cull distances. This applies for the clipvertex case as well.
765 *
766 * Setting this for primitives other than points should have no adverse
767 * effects.
768 */
769 clipdist_mask &= rs->clip_plane_enable;
770 culldist_mask |= clipdist_mask;
771
772 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
773 vs_sel->pa_cl_vs_out_cntl |
774 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
775 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
776 clipdist_mask | (culldist_mask << 8));
777 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
778 rs->pa_cl_clip_cntl |
779 ucp_mask |
780 S_028810_CLIP_DISABLE(window_space));
781 }
782
783 /*
784 * inferred state between framebuffer and rasterizer
785 */
786 static void si_update_poly_offset_state(struct si_context *sctx)
787 {
788 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
789
790 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
791 si_pm4_bind_state(sctx, poly_offset, NULL);
792 return;
793 }
794
795 /* Use the user format, not db_render_format, so that the polygon
796 * offset behaves as expected by applications.
797 */
798 switch (sctx->framebuffer.state.zsbuf->texture->format) {
799 case PIPE_FORMAT_Z16_UNORM:
800 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
801 break;
802 default: /* 24-bit */
803 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
804 break;
805 case PIPE_FORMAT_Z32_FLOAT:
806 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
807 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
808 break;
809 }
810 }
811
812 /*
813 * Rasterizer
814 */
815
816 static uint32_t si_translate_fill(uint32_t func)
817 {
818 switch(func) {
819 case PIPE_POLYGON_MODE_FILL:
820 return V_028814_X_DRAW_TRIANGLES;
821 case PIPE_POLYGON_MODE_LINE:
822 return V_028814_X_DRAW_LINES;
823 case PIPE_POLYGON_MODE_POINT:
824 return V_028814_X_DRAW_POINTS;
825 default:
826 assert(0);
827 return V_028814_X_DRAW_POINTS;
828 }
829 }
830
831 static void *si_create_rs_state(struct pipe_context *ctx,
832 const struct pipe_rasterizer_state *state)
833 {
834 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
835 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
836 struct si_pm4_state *pm4 = &rs->pm4;
837 unsigned tmp, i;
838 float psize_min, psize_max;
839
840 if (!rs) {
841 return NULL;
842 }
843
844 rs->scissor_enable = state->scissor;
845 rs->clip_halfz = state->clip_halfz;
846 rs->two_side = state->light_twoside;
847 rs->multisample_enable = state->multisample;
848 rs->force_persample_interp = state->force_persample_interp;
849 rs->clip_plane_enable = state->clip_plane_enable;
850 rs->line_stipple_enable = state->line_stipple_enable;
851 rs->poly_stipple_enable = state->poly_stipple_enable;
852 rs->line_smooth = state->line_smooth;
853 rs->line_width = state->line_width;
854 rs->poly_smooth = state->poly_smooth;
855 rs->uses_poly_offset = state->offset_point || state->offset_line ||
856 state->offset_tri;
857 rs->clamp_fragment_color = state->clamp_fragment_color;
858 rs->clamp_vertex_color = state->clamp_vertex_color;
859 rs->flatshade = state->flatshade;
860 rs->sprite_coord_enable = state->sprite_coord_enable;
861 rs->rasterizer_discard = state->rasterizer_discard;
862 rs->pa_sc_line_stipple = state->line_stipple_enable ?
863 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
864 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
865 rs->pa_cl_clip_cntl =
866 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
867 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
868 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
869 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
870 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
871
872 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
873 S_0286D4_FLAT_SHADE_ENA(1) |
874 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
875 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
876 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
877 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
878 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
879 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
880
881 /* point size 12.4 fixed point */
882 tmp = (unsigned)(state->point_size * 8.0);
883 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
884
885 if (state->point_size_per_vertex) {
886 psize_min = util_get_min_point_size(state);
887 psize_max = 8192;
888 } else {
889 /* Force the point size to be as if the vertex output was disabled. */
890 psize_min = state->point_size;
891 psize_max = state->point_size;
892 }
893 rs->max_point_size = psize_max;
894
895 /* Divide by two, because 0.5 = 1 pixel. */
896 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
897 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
898 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
899
900 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
901 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
902 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
903 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
904 S_028A48_MSAA_ENABLE(state->multisample ||
905 state->poly_smooth ||
906 state->line_smooth) |
907 S_028A48_VPORT_SCISSOR_ENABLE(1) |
908 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
909
910 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
911 S_028BE4_PIX_CENTER(state->half_pixel_center) |
912 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
913
914 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
915 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
916 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
917 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
918 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
919 S_028814_FACE(!state->front_ccw) |
920 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
921 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
922 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
923 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
924 state->fill_back != PIPE_POLYGON_MODE_FILL) |
925 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
926 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
927
928 if (!rs->uses_poly_offset)
929 return rs;
930
931 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
932 if (!rs->pm4_poly_offset) {
933 FREE(rs);
934 return NULL;
935 }
936
937 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
938 for (i = 0; i < 3; i++) {
939 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
940 float offset_units = state->offset_units;
941 float offset_scale = state->offset_scale * 16.0f;
942 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
943
944 if (!state->offset_units_unscaled) {
945 switch (i) {
946 case 0: /* 16-bit zbuffer */
947 offset_units *= 4.0f;
948 pa_su_poly_offset_db_fmt_cntl =
949 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
950 break;
951 case 1: /* 24-bit zbuffer */
952 offset_units *= 2.0f;
953 pa_su_poly_offset_db_fmt_cntl =
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
955 break;
956 case 2: /* 32-bit zbuffer */
957 offset_units *= 1.0f;
958 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
959 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
960 break;
961 }
962 }
963
964 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
965 fui(offset_scale));
966 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
967 fui(offset_units));
968 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
969 fui(offset_scale));
970 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
971 fui(offset_units));
972 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
973 pa_su_poly_offset_db_fmt_cntl);
974 }
975
976 return rs;
977 }
978
979 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
980 {
981 struct si_context *sctx = (struct si_context *)ctx;
982 struct si_state_rasterizer *old_rs =
983 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
984 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
985
986 if (!state)
987 return;
988
989 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
990 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
991
992 /* Update the small primitive filter workaround if necessary. */
993 if (sctx->screen->has_msaa_sample_loc_bug &&
994 sctx->framebuffer.nr_samples > 1)
995 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
996 }
997
998 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
999 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1000
1001 si_pm4_bind_state(sctx, rasterizer, rs);
1002 si_update_poly_offset_state(sctx);
1003
1004 if (!old_rs ||
1005 (old_rs->scissor_enable != rs->scissor_enable ||
1006 old_rs->line_width != rs->line_width ||
1007 old_rs->max_point_size != rs->max_point_size)) {
1008 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1009 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1010 }
1011
1012 if (!old_rs ||
1013 old_rs->clip_halfz != rs->clip_halfz) {
1014 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1015 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1016 }
1017
1018 if (!old_rs ||
1019 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1020 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1021 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1022
1023 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1024 rs->line_stipple_enable;
1025
1026 if (!old_rs ||
1027 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1028 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1029 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1030 old_rs->flatshade != rs->flatshade ||
1031 old_rs->two_side != rs->two_side ||
1032 old_rs->multisample_enable != rs->multisample_enable ||
1033 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1034 old_rs->poly_smooth != rs->poly_smooth ||
1035 old_rs->line_smooth != rs->line_smooth ||
1036 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1037 old_rs->force_persample_interp != rs->force_persample_interp)
1038 sctx->do_update_shaders = true;
1039 }
1040
1041 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1042 {
1043 struct si_context *sctx = (struct si_context *)ctx;
1044 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1045
1046 if (sctx->queued.named.rasterizer == state)
1047 si_pm4_bind_state(sctx, poly_offset, NULL);
1048
1049 FREE(rs->pm4_poly_offset);
1050 si_pm4_delete_state(sctx, rasterizer, rs);
1051 }
1052
1053 /*
1054 * infeered state between dsa and stencil ref
1055 */
1056 static void si_emit_stencil_ref(struct si_context *sctx)
1057 {
1058 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1059 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1060 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1061
1062 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1063 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1064 S_028430_STENCILMASK(dsa->valuemask[0]) |
1065 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1066 S_028430_STENCILOPVAL(1));
1067 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1068 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1069 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1070 S_028434_STENCILOPVAL_BF(1));
1071 }
1072
1073 static void si_set_stencil_ref(struct pipe_context *ctx,
1074 const struct pipe_stencil_ref *state)
1075 {
1076 struct si_context *sctx = (struct si_context *)ctx;
1077
1078 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1079 return;
1080
1081 sctx->stencil_ref.state = *state;
1082 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1083 }
1084
1085
1086 /*
1087 * DSA
1088 */
1089
1090 static uint32_t si_translate_stencil_op(int s_op)
1091 {
1092 switch (s_op) {
1093 case PIPE_STENCIL_OP_KEEP:
1094 return V_02842C_STENCIL_KEEP;
1095 case PIPE_STENCIL_OP_ZERO:
1096 return V_02842C_STENCIL_ZERO;
1097 case PIPE_STENCIL_OP_REPLACE:
1098 return V_02842C_STENCIL_REPLACE_TEST;
1099 case PIPE_STENCIL_OP_INCR:
1100 return V_02842C_STENCIL_ADD_CLAMP;
1101 case PIPE_STENCIL_OP_DECR:
1102 return V_02842C_STENCIL_SUB_CLAMP;
1103 case PIPE_STENCIL_OP_INCR_WRAP:
1104 return V_02842C_STENCIL_ADD_WRAP;
1105 case PIPE_STENCIL_OP_DECR_WRAP:
1106 return V_02842C_STENCIL_SUB_WRAP;
1107 case PIPE_STENCIL_OP_INVERT:
1108 return V_02842C_STENCIL_INVERT;
1109 default:
1110 PRINT_ERR("Unknown stencil op %d", s_op);
1111 assert(0);
1112 break;
1113 }
1114 return 0;
1115 }
1116
1117 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1118 {
1119 return s->enabled && s->writemask &&
1120 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1121 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1122 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1123 }
1124
1125 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1126 {
1127 /* REPLACE is normally order invariant, except when the stencil
1128 * reference value is written by the fragment shader. Tracking this
1129 * interaction does not seem worth the effort, so be conservative. */
1130 return op != PIPE_STENCIL_OP_INCR &&
1131 op != PIPE_STENCIL_OP_DECR &&
1132 op != PIPE_STENCIL_OP_REPLACE;
1133 }
1134
1135 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1136 * invariant in the sense that the set of passing fragments as well as the
1137 * final stencil buffer result does not depend on the order of fragments. */
1138 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1139 {
1140 return !state->enabled || !state->writemask ||
1141 /* The following assumes that Z writes are disabled. */
1142 (state->func == PIPE_FUNC_ALWAYS &&
1143 si_order_invariant_stencil_op(state->zpass_op) &&
1144 si_order_invariant_stencil_op(state->zfail_op)) ||
1145 (state->func == PIPE_FUNC_NEVER &&
1146 si_order_invariant_stencil_op(state->fail_op));
1147 }
1148
1149 static void *si_create_dsa_state(struct pipe_context *ctx,
1150 const struct pipe_depth_stencil_alpha_state *state)
1151 {
1152 struct si_context *sctx = (struct si_context *)ctx;
1153 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1154 struct si_pm4_state *pm4 = &dsa->pm4;
1155 unsigned db_depth_control;
1156 uint32_t db_stencil_control = 0;
1157
1158 if (!dsa) {
1159 return NULL;
1160 }
1161
1162 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1163 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1164 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1165 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1166
1167 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1168 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1169 S_028800_ZFUNC(state->depth.func) |
1170 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1171
1172 /* stencil */
1173 if (state->stencil[0].enabled) {
1174 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1175 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1176 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1177 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1178 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1179
1180 if (state->stencil[1].enabled) {
1181 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1182 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1183 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1184 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1185 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1186 }
1187 }
1188
1189 /* alpha */
1190 if (state->alpha.enabled) {
1191 dsa->alpha_func = state->alpha.func;
1192
1193 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1194 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1195 } else {
1196 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1197 }
1198
1199 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1200 if (state->stencil[0].enabled)
1201 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1202 if (state->depth.bounds_test) {
1203 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1204 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1205 }
1206
1207 dsa->depth_enabled = state->depth.enabled;
1208 dsa->depth_write_enabled = state->depth.enabled &&
1209 state->depth.writemask;
1210 dsa->stencil_enabled = state->stencil[0].enabled;
1211 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1212 (si_dsa_writes_stencil(&state->stencil[0]) ||
1213 si_dsa_writes_stencil(&state->stencil[1]));
1214 dsa->db_can_write = dsa->depth_write_enabled ||
1215 dsa->stencil_write_enabled;
1216
1217 bool zfunc_is_ordered =
1218 state->depth.func == PIPE_FUNC_NEVER ||
1219 state->depth.func == PIPE_FUNC_LESS ||
1220 state->depth.func == PIPE_FUNC_LEQUAL ||
1221 state->depth.func == PIPE_FUNC_GREATER ||
1222 state->depth.func == PIPE_FUNC_GEQUAL;
1223
1224 bool nozwrite_and_order_invariant_stencil =
1225 !dsa->db_can_write ||
1226 (!dsa->depth_write_enabled &&
1227 si_order_invariant_stencil_state(&state->stencil[0]) &&
1228 si_order_invariant_stencil_state(&state->stencil[1]));
1229
1230 dsa->order_invariance[1].zs =
1231 nozwrite_and_order_invariant_stencil ||
1232 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1233 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1234
1235 dsa->order_invariance[1].pass_set =
1236 nozwrite_and_order_invariant_stencil ||
1237 (!dsa->stencil_write_enabled &&
1238 (state->depth.func == PIPE_FUNC_ALWAYS ||
1239 state->depth.func == PIPE_FUNC_NEVER));
1240 dsa->order_invariance[0].pass_set =
1241 !dsa->depth_write_enabled ||
1242 (state->depth.func == PIPE_FUNC_ALWAYS ||
1243 state->depth.func == PIPE_FUNC_NEVER);
1244
1245 dsa->order_invariance[1].pass_last =
1246 sctx->screen->assume_no_z_fights &&
1247 !dsa->stencil_write_enabled &&
1248 dsa->depth_write_enabled && zfunc_is_ordered;
1249 dsa->order_invariance[0].pass_last =
1250 sctx->screen->assume_no_z_fights &&
1251 dsa->depth_write_enabled && zfunc_is_ordered;
1252
1253 return dsa;
1254 }
1255
1256 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1257 {
1258 struct si_context *sctx = (struct si_context *)ctx;
1259 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1260 struct si_state_dsa *dsa = state;
1261
1262 if (!state)
1263 return;
1264
1265 si_pm4_bind_state(sctx, dsa, dsa);
1266
1267 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1268 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1269 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1270 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1271 }
1272
1273 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1274 sctx->do_update_shaders = true;
1275
1276 if (sctx->screen->dpbb_allowed &&
1277 (!old_dsa ||
1278 (old_dsa->depth_enabled != dsa->depth_enabled ||
1279 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1280 old_dsa->db_can_write != dsa->db_can_write)))
1281 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1282
1283 if (sctx->screen->has_out_of_order_rast &&
1284 (!old_dsa ||
1285 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1286 sizeof(old_dsa->order_invariance))))
1287 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1288 }
1289
1290 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1291 {
1292 struct si_context *sctx = (struct si_context *)ctx;
1293 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1294 }
1295
1296 static void *si_create_db_flush_dsa(struct si_context *sctx)
1297 {
1298 struct pipe_depth_stencil_alpha_state dsa = {};
1299
1300 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1301 }
1302
1303 /* DB RENDER STATE */
1304
1305 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1306 {
1307 struct si_context *sctx = (struct si_context*)ctx;
1308
1309 /* Pipeline stat & streamout queries. */
1310 if (enable) {
1311 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1312 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1313 } else {
1314 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1315 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1316 }
1317
1318 /* Occlusion queries. */
1319 if (sctx->occlusion_queries_disabled != !enable) {
1320 sctx->occlusion_queries_disabled = !enable;
1321 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1322 }
1323 }
1324
1325 void si_set_occlusion_query_state(struct si_context *sctx,
1326 bool old_perfect_enable)
1327 {
1328 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1329
1330 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1331
1332 if (perfect_enable != old_perfect_enable)
1333 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1334 }
1335
1336 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1337 {
1338 st->saved_compute = sctx->cs_shader_state.program;
1339
1340 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1341 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1342 }
1343
1344 static void si_emit_db_render_state(struct si_context *sctx)
1345 {
1346 struct radeon_winsys_cs *cs = sctx->gfx_cs;
1347 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1348 unsigned db_shader_control;
1349
1350 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1351
1352 /* DB_RENDER_CONTROL */
1353 if (sctx->dbcb_depth_copy_enabled ||
1354 sctx->dbcb_stencil_copy_enabled) {
1355 radeon_emit(cs,
1356 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1357 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1358 S_028000_COPY_CENTROID(1) |
1359 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1360 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1361 radeon_emit(cs,
1362 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1363 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1364 } else {
1365 radeon_emit(cs,
1366 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1367 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1368 }
1369
1370 /* DB_COUNT_CONTROL (occlusion queries) */
1371 if (sctx->num_occlusion_queries > 0 &&
1372 !sctx->occlusion_queries_disabled) {
1373 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1374
1375 if (sctx->chip_class >= CIK) {
1376 radeon_emit(cs,
1377 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1378 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1379 S_028004_ZPASS_ENABLE(1) |
1380 S_028004_SLICE_EVEN_ENABLE(1) |
1381 S_028004_SLICE_ODD_ENABLE(1));
1382 } else {
1383 radeon_emit(cs,
1384 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1385 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1386 }
1387 } else {
1388 /* Disable occlusion queries. */
1389 if (sctx->chip_class >= CIK) {
1390 radeon_emit(cs, 0);
1391 } else {
1392 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1393 }
1394 }
1395
1396 /* DB_RENDER_OVERRIDE2 */
1397 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1398 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1399 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1400 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1401
1402 db_shader_control = sctx->ps_db_shader_control;
1403
1404 /* Bug workaround for smoothing (overrasterization) on SI. */
1405 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1406 db_shader_control &= C_02880C_Z_ORDER;
1407 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1408 }
1409
1410 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1411 if (!rs || !rs->multisample_enable)
1412 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1413
1414 if (sctx->screen->has_rbplus &&
1415 !sctx->screen->rbplus_allowed)
1416 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1417
1418 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1419 db_shader_control);
1420 }
1421
1422 /*
1423 * format translation
1424 */
1425 static uint32_t si_translate_colorformat(enum pipe_format format)
1426 {
1427 const struct util_format_description *desc = util_format_description(format);
1428 if (!desc)
1429 return V_028C70_COLOR_INVALID;
1430
1431 #define HAS_SIZE(x,y,z,w) \
1432 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1433 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1434
1435 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1436 return V_028C70_COLOR_10_11_11;
1437
1438 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1439 return V_028C70_COLOR_INVALID;
1440
1441 /* hw cannot support mixed formats (except depth/stencil, since
1442 * stencil is not written to). */
1443 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1444 return V_028C70_COLOR_INVALID;
1445
1446 switch (desc->nr_channels) {
1447 case 1:
1448 switch (desc->channel[0].size) {
1449 case 8:
1450 return V_028C70_COLOR_8;
1451 case 16:
1452 return V_028C70_COLOR_16;
1453 case 32:
1454 return V_028C70_COLOR_32;
1455 }
1456 break;
1457 case 2:
1458 if (desc->channel[0].size == desc->channel[1].size) {
1459 switch (desc->channel[0].size) {
1460 case 8:
1461 return V_028C70_COLOR_8_8;
1462 case 16:
1463 return V_028C70_COLOR_16_16;
1464 case 32:
1465 return V_028C70_COLOR_32_32;
1466 }
1467 } else if (HAS_SIZE(8,24,0,0)) {
1468 return V_028C70_COLOR_24_8;
1469 } else if (HAS_SIZE(24,8,0,0)) {
1470 return V_028C70_COLOR_8_24;
1471 }
1472 break;
1473 case 3:
1474 if (HAS_SIZE(5,6,5,0)) {
1475 return V_028C70_COLOR_5_6_5;
1476 } else if (HAS_SIZE(32,8,24,0)) {
1477 return V_028C70_COLOR_X24_8_32_FLOAT;
1478 }
1479 break;
1480 case 4:
1481 if (desc->channel[0].size == desc->channel[1].size &&
1482 desc->channel[0].size == desc->channel[2].size &&
1483 desc->channel[0].size == desc->channel[3].size) {
1484 switch (desc->channel[0].size) {
1485 case 4:
1486 return V_028C70_COLOR_4_4_4_4;
1487 case 8:
1488 return V_028C70_COLOR_8_8_8_8;
1489 case 16:
1490 return V_028C70_COLOR_16_16_16_16;
1491 case 32:
1492 return V_028C70_COLOR_32_32_32_32;
1493 }
1494 } else if (HAS_SIZE(5,5,5,1)) {
1495 return V_028C70_COLOR_1_5_5_5;
1496 } else if (HAS_SIZE(1,5,5,5)) {
1497 return V_028C70_COLOR_5_5_5_1;
1498 } else if (HAS_SIZE(10,10,10,2)) {
1499 return V_028C70_COLOR_2_10_10_10;
1500 }
1501 break;
1502 }
1503 return V_028C70_COLOR_INVALID;
1504 }
1505
1506 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1507 {
1508 if (SI_BIG_ENDIAN) {
1509 switch(colorformat) {
1510 /* 8-bit buffers. */
1511 case V_028C70_COLOR_8:
1512 return V_028C70_ENDIAN_NONE;
1513
1514 /* 16-bit buffers. */
1515 case V_028C70_COLOR_5_6_5:
1516 case V_028C70_COLOR_1_5_5_5:
1517 case V_028C70_COLOR_4_4_4_4:
1518 case V_028C70_COLOR_16:
1519 case V_028C70_COLOR_8_8:
1520 return V_028C70_ENDIAN_8IN16;
1521
1522 /* 32-bit buffers. */
1523 case V_028C70_COLOR_8_8_8_8:
1524 case V_028C70_COLOR_2_10_10_10:
1525 case V_028C70_COLOR_8_24:
1526 case V_028C70_COLOR_24_8:
1527 case V_028C70_COLOR_16_16:
1528 return V_028C70_ENDIAN_8IN32;
1529
1530 /* 64-bit buffers. */
1531 case V_028C70_COLOR_16_16_16_16:
1532 return V_028C70_ENDIAN_8IN16;
1533
1534 case V_028C70_COLOR_32_32:
1535 return V_028C70_ENDIAN_8IN32;
1536
1537 /* 128-bit buffers. */
1538 case V_028C70_COLOR_32_32_32_32:
1539 return V_028C70_ENDIAN_8IN32;
1540 default:
1541 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1542 }
1543 } else {
1544 return V_028C70_ENDIAN_NONE;
1545 }
1546 }
1547
1548 static uint32_t si_translate_dbformat(enum pipe_format format)
1549 {
1550 switch (format) {
1551 case PIPE_FORMAT_Z16_UNORM:
1552 return V_028040_Z_16;
1553 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1554 case PIPE_FORMAT_X8Z24_UNORM:
1555 case PIPE_FORMAT_Z24X8_UNORM:
1556 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1557 return V_028040_Z_24; /* deprecated on SI */
1558 case PIPE_FORMAT_Z32_FLOAT:
1559 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1560 return V_028040_Z_32_FLOAT;
1561 default:
1562 return V_028040_Z_INVALID;
1563 }
1564 }
1565
1566 /*
1567 * Texture translation
1568 */
1569
1570 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1571 enum pipe_format format,
1572 const struct util_format_description *desc,
1573 int first_non_void)
1574 {
1575 struct si_screen *sscreen = (struct si_screen*)screen;
1576 bool uniform = true;
1577 int i;
1578
1579 /* Colorspace (return non-RGB formats directly). */
1580 switch (desc->colorspace) {
1581 /* Depth stencil formats */
1582 case UTIL_FORMAT_COLORSPACE_ZS:
1583 switch (format) {
1584 case PIPE_FORMAT_Z16_UNORM:
1585 return V_008F14_IMG_DATA_FORMAT_16;
1586 case PIPE_FORMAT_X24S8_UINT:
1587 case PIPE_FORMAT_S8X24_UINT:
1588 /*
1589 * Implemented as an 8_8_8_8 data format to fix texture
1590 * gathers in stencil sampling. This affects at least
1591 * GL45-CTS.texture_cube_map_array.sampling on VI.
1592 */
1593 if (sscreen->info.chip_class <= VI)
1594 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1595
1596 if (format == PIPE_FORMAT_X24S8_UINT)
1597 return V_008F14_IMG_DATA_FORMAT_8_24;
1598 else
1599 return V_008F14_IMG_DATA_FORMAT_24_8;
1600 case PIPE_FORMAT_Z24X8_UNORM:
1601 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1602 return V_008F14_IMG_DATA_FORMAT_8_24;
1603 case PIPE_FORMAT_X8Z24_UNORM:
1604 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1605 return V_008F14_IMG_DATA_FORMAT_24_8;
1606 case PIPE_FORMAT_S8_UINT:
1607 return V_008F14_IMG_DATA_FORMAT_8;
1608 case PIPE_FORMAT_Z32_FLOAT:
1609 return V_008F14_IMG_DATA_FORMAT_32;
1610 case PIPE_FORMAT_X32_S8X24_UINT:
1611 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1612 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1613 default:
1614 goto out_unknown;
1615 }
1616
1617 case UTIL_FORMAT_COLORSPACE_YUV:
1618 goto out_unknown; /* TODO */
1619
1620 case UTIL_FORMAT_COLORSPACE_SRGB:
1621 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1622 goto out_unknown;
1623 break;
1624
1625 default:
1626 break;
1627 }
1628
1629 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1630 if (!sscreen->info.has_format_bc1_through_bc7)
1631 goto out_unknown;
1632
1633 switch (format) {
1634 case PIPE_FORMAT_RGTC1_SNORM:
1635 case PIPE_FORMAT_LATC1_SNORM:
1636 case PIPE_FORMAT_RGTC1_UNORM:
1637 case PIPE_FORMAT_LATC1_UNORM:
1638 return V_008F14_IMG_DATA_FORMAT_BC4;
1639 case PIPE_FORMAT_RGTC2_SNORM:
1640 case PIPE_FORMAT_LATC2_SNORM:
1641 case PIPE_FORMAT_RGTC2_UNORM:
1642 case PIPE_FORMAT_LATC2_UNORM:
1643 return V_008F14_IMG_DATA_FORMAT_BC5;
1644 default:
1645 goto out_unknown;
1646 }
1647 }
1648
1649 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1650 (sscreen->info.family == CHIP_STONEY ||
1651 sscreen->info.family == CHIP_VEGA10 ||
1652 sscreen->info.family == CHIP_RAVEN)) {
1653 switch (format) {
1654 case PIPE_FORMAT_ETC1_RGB8:
1655 case PIPE_FORMAT_ETC2_RGB8:
1656 case PIPE_FORMAT_ETC2_SRGB8:
1657 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1658 case PIPE_FORMAT_ETC2_RGB8A1:
1659 case PIPE_FORMAT_ETC2_SRGB8A1:
1660 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1661 case PIPE_FORMAT_ETC2_RGBA8:
1662 case PIPE_FORMAT_ETC2_SRGBA8:
1663 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1664 case PIPE_FORMAT_ETC2_R11_UNORM:
1665 case PIPE_FORMAT_ETC2_R11_SNORM:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1667 case PIPE_FORMAT_ETC2_RG11_UNORM:
1668 case PIPE_FORMAT_ETC2_RG11_SNORM:
1669 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1670 default:
1671 goto out_unknown;
1672 }
1673 }
1674
1675 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1676 if (!sscreen->info.has_format_bc1_through_bc7)
1677 goto out_unknown;
1678
1679 switch (format) {
1680 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1681 case PIPE_FORMAT_BPTC_SRGBA:
1682 return V_008F14_IMG_DATA_FORMAT_BC7;
1683 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1684 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1685 return V_008F14_IMG_DATA_FORMAT_BC6;
1686 default:
1687 goto out_unknown;
1688 }
1689 }
1690
1691 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1692 switch (format) {
1693 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1694 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1695 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1696 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1697 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1698 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1699 default:
1700 goto out_unknown;
1701 }
1702 }
1703
1704 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1705 if (!sscreen->info.has_format_bc1_through_bc7)
1706 goto out_unknown;
1707
1708 switch (format) {
1709 case PIPE_FORMAT_DXT1_RGB:
1710 case PIPE_FORMAT_DXT1_RGBA:
1711 case PIPE_FORMAT_DXT1_SRGB:
1712 case PIPE_FORMAT_DXT1_SRGBA:
1713 return V_008F14_IMG_DATA_FORMAT_BC1;
1714 case PIPE_FORMAT_DXT3_RGBA:
1715 case PIPE_FORMAT_DXT3_SRGBA:
1716 return V_008F14_IMG_DATA_FORMAT_BC2;
1717 case PIPE_FORMAT_DXT5_RGBA:
1718 case PIPE_FORMAT_DXT5_SRGBA:
1719 return V_008F14_IMG_DATA_FORMAT_BC3;
1720 default:
1721 goto out_unknown;
1722 }
1723 }
1724
1725 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1726 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1727 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1728 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1729 }
1730
1731 /* R8G8Bx_SNORM - TODO CxV8U8 */
1732
1733 /* hw cannot support mixed formats (except depth/stencil, since only
1734 * depth is read).*/
1735 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1736 goto out_unknown;
1737
1738 /* See whether the components are of the same size. */
1739 for (i = 1; i < desc->nr_channels; i++) {
1740 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1741 }
1742
1743 /* Non-uniform formats. */
1744 if (!uniform) {
1745 switch(desc->nr_channels) {
1746 case 3:
1747 if (desc->channel[0].size == 5 &&
1748 desc->channel[1].size == 6 &&
1749 desc->channel[2].size == 5) {
1750 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1751 }
1752 goto out_unknown;
1753 case 4:
1754 if (desc->channel[0].size == 5 &&
1755 desc->channel[1].size == 5 &&
1756 desc->channel[2].size == 5 &&
1757 desc->channel[3].size == 1) {
1758 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1759 }
1760 if (desc->channel[0].size == 1 &&
1761 desc->channel[1].size == 5 &&
1762 desc->channel[2].size == 5 &&
1763 desc->channel[3].size == 5) {
1764 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1765 }
1766 if (desc->channel[0].size == 10 &&
1767 desc->channel[1].size == 10 &&
1768 desc->channel[2].size == 10 &&
1769 desc->channel[3].size == 2) {
1770 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1771 }
1772 goto out_unknown;
1773 }
1774 goto out_unknown;
1775 }
1776
1777 if (first_non_void < 0 || first_non_void > 3)
1778 goto out_unknown;
1779
1780 /* uniform formats */
1781 switch (desc->channel[first_non_void].size) {
1782 case 4:
1783 switch (desc->nr_channels) {
1784 #if 0 /* Not supported for render targets */
1785 case 2:
1786 return V_008F14_IMG_DATA_FORMAT_4_4;
1787 #endif
1788 case 4:
1789 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1790 }
1791 break;
1792 case 8:
1793 switch (desc->nr_channels) {
1794 case 1:
1795 return V_008F14_IMG_DATA_FORMAT_8;
1796 case 2:
1797 return V_008F14_IMG_DATA_FORMAT_8_8;
1798 case 4:
1799 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1800 }
1801 break;
1802 case 16:
1803 switch (desc->nr_channels) {
1804 case 1:
1805 return V_008F14_IMG_DATA_FORMAT_16;
1806 case 2:
1807 return V_008F14_IMG_DATA_FORMAT_16_16;
1808 case 4:
1809 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1810 }
1811 break;
1812 case 32:
1813 switch (desc->nr_channels) {
1814 case 1:
1815 return V_008F14_IMG_DATA_FORMAT_32;
1816 case 2:
1817 return V_008F14_IMG_DATA_FORMAT_32_32;
1818 #if 0 /* Not supported for render targets */
1819 case 3:
1820 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1821 #endif
1822 case 4:
1823 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1824 }
1825 }
1826
1827 out_unknown:
1828 return ~0;
1829 }
1830
1831 static unsigned si_tex_wrap(unsigned wrap)
1832 {
1833 switch (wrap) {
1834 default:
1835 case PIPE_TEX_WRAP_REPEAT:
1836 return V_008F30_SQ_TEX_WRAP;
1837 case PIPE_TEX_WRAP_CLAMP:
1838 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1839 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1840 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1841 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1842 return V_008F30_SQ_TEX_CLAMP_BORDER;
1843 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1844 return V_008F30_SQ_TEX_MIRROR;
1845 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1846 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1847 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1848 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1849 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1850 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1851 }
1852 }
1853
1854 static unsigned si_tex_mipfilter(unsigned filter)
1855 {
1856 switch (filter) {
1857 case PIPE_TEX_MIPFILTER_NEAREST:
1858 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1859 case PIPE_TEX_MIPFILTER_LINEAR:
1860 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1861 default:
1862 case PIPE_TEX_MIPFILTER_NONE:
1863 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1864 }
1865 }
1866
1867 static unsigned si_tex_compare(unsigned compare)
1868 {
1869 switch (compare) {
1870 default:
1871 case PIPE_FUNC_NEVER:
1872 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1873 case PIPE_FUNC_LESS:
1874 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1875 case PIPE_FUNC_EQUAL:
1876 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1877 case PIPE_FUNC_LEQUAL:
1878 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1879 case PIPE_FUNC_GREATER:
1880 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1881 case PIPE_FUNC_NOTEQUAL:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1883 case PIPE_FUNC_GEQUAL:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1885 case PIPE_FUNC_ALWAYS:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1887 }
1888 }
1889
1890 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1891 unsigned view_target, unsigned nr_samples)
1892 {
1893 unsigned res_target = rtex->buffer.b.b.target;
1894
1895 if (view_target == PIPE_TEXTURE_CUBE ||
1896 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1897 res_target = view_target;
1898 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1899 else if (res_target == PIPE_TEXTURE_CUBE ||
1900 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1901 res_target = PIPE_TEXTURE_2D_ARRAY;
1902
1903 /* GFX9 allocates 1D textures as 2D. */
1904 if ((res_target == PIPE_TEXTURE_1D ||
1905 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1906 sscreen->info.chip_class >= GFX9 &&
1907 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1908 if (res_target == PIPE_TEXTURE_1D)
1909 res_target = PIPE_TEXTURE_2D;
1910 else
1911 res_target = PIPE_TEXTURE_2D_ARRAY;
1912 }
1913
1914 switch (res_target) {
1915 default:
1916 case PIPE_TEXTURE_1D:
1917 return V_008F1C_SQ_RSRC_IMG_1D;
1918 case PIPE_TEXTURE_1D_ARRAY:
1919 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1920 case PIPE_TEXTURE_2D:
1921 case PIPE_TEXTURE_RECT:
1922 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1923 V_008F1C_SQ_RSRC_IMG_2D;
1924 case PIPE_TEXTURE_2D_ARRAY:
1925 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1926 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1927 case PIPE_TEXTURE_3D:
1928 return V_008F1C_SQ_RSRC_IMG_3D;
1929 case PIPE_TEXTURE_CUBE:
1930 case PIPE_TEXTURE_CUBE_ARRAY:
1931 return V_008F1C_SQ_RSRC_IMG_CUBE;
1932 }
1933 }
1934
1935 /*
1936 * Format support testing
1937 */
1938
1939 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1940 {
1941 const struct util_format_description *desc = util_format_description(format);
1942 if (!desc)
1943 return false;
1944
1945 return si_translate_texformat(screen, format, desc,
1946 util_format_get_first_non_void_channel(format)) != ~0U;
1947 }
1948
1949 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1950 const struct util_format_description *desc,
1951 int first_non_void)
1952 {
1953 int i;
1954
1955 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1956 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1957
1958 assert(first_non_void >= 0);
1959
1960 if (desc->nr_channels == 4 &&
1961 desc->channel[0].size == 10 &&
1962 desc->channel[1].size == 10 &&
1963 desc->channel[2].size == 10 &&
1964 desc->channel[3].size == 2)
1965 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1966
1967 /* See whether the components are of the same size. */
1968 for (i = 0; i < desc->nr_channels; i++) {
1969 if (desc->channel[first_non_void].size != desc->channel[i].size)
1970 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1971 }
1972
1973 switch (desc->channel[first_non_void].size) {
1974 case 8:
1975 switch (desc->nr_channels) {
1976 case 1:
1977 case 3: /* 3 loads */
1978 return V_008F0C_BUF_DATA_FORMAT_8;
1979 case 2:
1980 return V_008F0C_BUF_DATA_FORMAT_8_8;
1981 case 4:
1982 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1983 }
1984 break;
1985 case 16:
1986 switch (desc->nr_channels) {
1987 case 1:
1988 case 3: /* 3 loads */
1989 return V_008F0C_BUF_DATA_FORMAT_16;
1990 case 2:
1991 return V_008F0C_BUF_DATA_FORMAT_16_16;
1992 case 4:
1993 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1994 }
1995 break;
1996 case 32:
1997 switch (desc->nr_channels) {
1998 case 1:
1999 return V_008F0C_BUF_DATA_FORMAT_32;
2000 case 2:
2001 return V_008F0C_BUF_DATA_FORMAT_32_32;
2002 case 3:
2003 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2004 case 4:
2005 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2006 }
2007 break;
2008 case 64:
2009 /* Legacy double formats. */
2010 switch (desc->nr_channels) {
2011 case 1: /* 1 load */
2012 return V_008F0C_BUF_DATA_FORMAT_32_32;
2013 case 2: /* 1 load */
2014 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2015 case 3: /* 3 loads */
2016 return V_008F0C_BUF_DATA_FORMAT_32_32;
2017 case 4: /* 2 loads */
2018 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2019 }
2020 break;
2021 }
2022
2023 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2024 }
2025
2026 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2027 const struct util_format_description *desc,
2028 int first_non_void)
2029 {
2030 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2031 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2032
2033 assert(first_non_void >= 0);
2034
2035 switch (desc->channel[first_non_void].type) {
2036 case UTIL_FORMAT_TYPE_SIGNED:
2037 case UTIL_FORMAT_TYPE_FIXED:
2038 if (desc->channel[first_non_void].size >= 32 ||
2039 desc->channel[first_non_void].pure_integer)
2040 return V_008F0C_BUF_NUM_FORMAT_SINT;
2041 else if (desc->channel[first_non_void].normalized)
2042 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2043 else
2044 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2045 break;
2046 case UTIL_FORMAT_TYPE_UNSIGNED:
2047 if (desc->channel[first_non_void].size >= 32 ||
2048 desc->channel[first_non_void].pure_integer)
2049 return V_008F0C_BUF_NUM_FORMAT_UINT;
2050 else if (desc->channel[first_non_void].normalized)
2051 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2052 else
2053 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2054 break;
2055 case UTIL_FORMAT_TYPE_FLOAT:
2056 default:
2057 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2058 }
2059 }
2060
2061 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2062 enum pipe_format format,
2063 unsigned usage)
2064 {
2065 const struct util_format_description *desc;
2066 int first_non_void;
2067 unsigned data_format;
2068
2069 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2070 PIPE_BIND_SAMPLER_VIEW |
2071 PIPE_BIND_VERTEX_BUFFER)) == 0);
2072
2073 desc = util_format_description(format);
2074 if (!desc)
2075 return 0;
2076
2077 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2078 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2079 * for read-only access (with caveats surrounding bounds checks), but
2080 * obviously fails for write access which we have to implement for
2081 * shader images. Luckily, OpenGL doesn't expect this to be supported
2082 * anyway, and so the only impact is on PBO uploads / downloads, which
2083 * shouldn't be expected to be fast for GL_RGB anyway.
2084 */
2085 if (desc->block.bits == 3 * 8 ||
2086 desc->block.bits == 3 * 16) {
2087 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2088 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2089 if (!usage)
2090 return 0;
2091 }
2092 }
2093
2094 first_non_void = util_format_get_first_non_void_channel(format);
2095 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2096 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2097 return 0;
2098
2099 return usage;
2100 }
2101
2102 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2103 {
2104 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2105 si_translate_colorswap(format, false) != ~0U;
2106 }
2107
2108 static bool si_is_zs_format_supported(enum pipe_format format)
2109 {
2110 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2111 }
2112
2113 static boolean si_is_format_supported(struct pipe_screen *screen,
2114 enum pipe_format format,
2115 enum pipe_texture_target target,
2116 unsigned sample_count,
2117 unsigned usage)
2118 {
2119 struct si_screen *sscreen = (struct si_screen *)screen;
2120 unsigned retval = 0;
2121
2122 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2123 PRINT_ERR("r600: unsupported texture type %d\n", target);
2124 return false;
2125 }
2126
2127 if (!util_format_is_supported(format, usage))
2128 return false;
2129
2130 if (sample_count > 1) {
2131 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2132 return false;
2133
2134 if (usage & PIPE_BIND_SHADER_IMAGE)
2135 return false;
2136
2137 switch (sample_count) {
2138 case 2:
2139 case 4:
2140 case 8:
2141 break;
2142 case 16:
2143 /* Allow resource_copy_region with nr_samples == 16. */
2144 if (sscreen->eqaa_force_coverage_samples == 16 &&
2145 !util_format_is_depth_or_stencil(format))
2146 return true;
2147 if (format == PIPE_FORMAT_NONE)
2148 return true;
2149 else
2150 return false;
2151 default:
2152 return false;
2153 }
2154 }
2155
2156 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2157 PIPE_BIND_SHADER_IMAGE)) {
2158 if (target == PIPE_BUFFER) {
2159 retval |= si_is_vertex_format_supported(
2160 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2161 PIPE_BIND_SHADER_IMAGE));
2162 } else {
2163 if (si_is_sampler_format_supported(screen, format))
2164 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2165 PIPE_BIND_SHADER_IMAGE);
2166 }
2167 }
2168
2169 if ((usage & (PIPE_BIND_RENDER_TARGET |
2170 PIPE_BIND_DISPLAY_TARGET |
2171 PIPE_BIND_SCANOUT |
2172 PIPE_BIND_SHARED |
2173 PIPE_BIND_BLENDABLE)) &&
2174 si_is_colorbuffer_format_supported(format)) {
2175 retval |= usage &
2176 (PIPE_BIND_RENDER_TARGET |
2177 PIPE_BIND_DISPLAY_TARGET |
2178 PIPE_BIND_SCANOUT |
2179 PIPE_BIND_SHARED);
2180 if (!util_format_is_pure_integer(format) &&
2181 !util_format_is_depth_or_stencil(format))
2182 retval |= usage & PIPE_BIND_BLENDABLE;
2183 }
2184
2185 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2186 si_is_zs_format_supported(format)) {
2187 retval |= PIPE_BIND_DEPTH_STENCIL;
2188 }
2189
2190 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2191 retval |= si_is_vertex_format_supported(screen, format,
2192 PIPE_BIND_VERTEX_BUFFER);
2193 }
2194
2195 if ((usage & PIPE_BIND_LINEAR) &&
2196 !util_format_is_compressed(format) &&
2197 !(usage & PIPE_BIND_DEPTH_STENCIL))
2198 retval |= PIPE_BIND_LINEAR;
2199
2200 return retval == usage;
2201 }
2202
2203 /*
2204 * framebuffer handling
2205 */
2206
2207 static void si_choose_spi_color_formats(struct r600_surface *surf,
2208 unsigned format, unsigned swap,
2209 unsigned ntype, bool is_depth)
2210 {
2211 /* Alpha is needed for alpha-to-coverage.
2212 * Blending may be with or without alpha.
2213 */
2214 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2215 unsigned alpha = 0; /* exports alpha, but may not support blending */
2216 unsigned blend = 0; /* supports blending, but may not export alpha */
2217 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2218
2219 /* Choose the SPI color formats. These are required values for RB+.
2220 * Other chips have multiple choices, though they are not necessarily better.
2221 */
2222 switch (format) {
2223 case V_028C70_COLOR_5_6_5:
2224 case V_028C70_COLOR_1_5_5_5:
2225 case V_028C70_COLOR_5_5_5_1:
2226 case V_028C70_COLOR_4_4_4_4:
2227 case V_028C70_COLOR_10_11_11:
2228 case V_028C70_COLOR_11_11_10:
2229 case V_028C70_COLOR_8:
2230 case V_028C70_COLOR_8_8:
2231 case V_028C70_COLOR_8_8_8_8:
2232 case V_028C70_COLOR_10_10_10_2:
2233 case V_028C70_COLOR_2_10_10_10:
2234 if (ntype == V_028C70_NUMBER_UINT)
2235 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2236 else if (ntype == V_028C70_NUMBER_SINT)
2237 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2238 else
2239 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2240 break;
2241
2242 case V_028C70_COLOR_16:
2243 case V_028C70_COLOR_16_16:
2244 case V_028C70_COLOR_16_16_16_16:
2245 if (ntype == V_028C70_NUMBER_UNORM ||
2246 ntype == V_028C70_NUMBER_SNORM) {
2247 /* UNORM16 and SNORM16 don't support blending */
2248 if (ntype == V_028C70_NUMBER_UNORM)
2249 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2250 else
2251 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2252
2253 /* Use 32 bits per channel for blending. */
2254 if (format == V_028C70_COLOR_16) {
2255 if (swap == V_028C70_SWAP_STD) { /* R */
2256 blend = V_028714_SPI_SHADER_32_R;
2257 blend_alpha = V_028714_SPI_SHADER_32_AR;
2258 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2259 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2260 else
2261 assert(0);
2262 } else if (format == V_028C70_COLOR_16_16) {
2263 if (swap == V_028C70_SWAP_STD) { /* RG */
2264 blend = V_028714_SPI_SHADER_32_GR;
2265 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2266 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2267 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2268 else
2269 assert(0);
2270 } else /* 16_16_16_16 */
2271 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2272 } else if (ntype == V_028C70_NUMBER_UINT)
2273 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2274 else if (ntype == V_028C70_NUMBER_SINT)
2275 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2276 else if (ntype == V_028C70_NUMBER_FLOAT)
2277 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2278 else
2279 assert(0);
2280 break;
2281
2282 case V_028C70_COLOR_32:
2283 if (swap == V_028C70_SWAP_STD) { /* R */
2284 blend = normal = V_028714_SPI_SHADER_32_R;
2285 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2286 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2287 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2288 else
2289 assert(0);
2290 break;
2291
2292 case V_028C70_COLOR_32_32:
2293 if (swap == V_028C70_SWAP_STD) { /* RG */
2294 blend = normal = V_028714_SPI_SHADER_32_GR;
2295 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2296 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2297 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2298 else
2299 assert(0);
2300 break;
2301
2302 case V_028C70_COLOR_32_32_32_32:
2303 case V_028C70_COLOR_8_24:
2304 case V_028C70_COLOR_24_8:
2305 case V_028C70_COLOR_X24_8_32_FLOAT:
2306 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2307 break;
2308
2309 default:
2310 assert(0);
2311 return;
2312 }
2313
2314 /* The DB->CB copy needs 32_ABGR. */
2315 if (is_depth)
2316 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2317
2318 surf->spi_shader_col_format = normal;
2319 surf->spi_shader_col_format_alpha = alpha;
2320 surf->spi_shader_col_format_blend = blend;
2321 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2322 }
2323
2324 static void si_initialize_color_surface(struct si_context *sctx,
2325 struct r600_surface *surf)
2326 {
2327 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2328 unsigned color_info, color_attrib;
2329 unsigned format, swap, ntype, endian;
2330 const struct util_format_description *desc;
2331 int firstchan;
2332 unsigned blend_clamp = 0, blend_bypass = 0;
2333
2334 desc = util_format_description(surf->base.format);
2335 for (firstchan = 0; firstchan < 4; firstchan++) {
2336 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2337 break;
2338 }
2339 }
2340 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2341 ntype = V_028C70_NUMBER_FLOAT;
2342 } else {
2343 ntype = V_028C70_NUMBER_UNORM;
2344 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2345 ntype = V_028C70_NUMBER_SRGB;
2346 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2347 if (desc->channel[firstchan].pure_integer) {
2348 ntype = V_028C70_NUMBER_SINT;
2349 } else {
2350 assert(desc->channel[firstchan].normalized);
2351 ntype = V_028C70_NUMBER_SNORM;
2352 }
2353 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2354 if (desc->channel[firstchan].pure_integer) {
2355 ntype = V_028C70_NUMBER_UINT;
2356 } else {
2357 assert(desc->channel[firstchan].normalized);
2358 ntype = V_028C70_NUMBER_UNORM;
2359 }
2360 }
2361 }
2362
2363 format = si_translate_colorformat(surf->base.format);
2364 if (format == V_028C70_COLOR_INVALID) {
2365 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2366 }
2367 assert(format != V_028C70_COLOR_INVALID);
2368 swap = si_translate_colorswap(surf->base.format, false);
2369 endian = si_colorformat_endian_swap(format);
2370
2371 /* blend clamp should be set for all NORM/SRGB types */
2372 if (ntype == V_028C70_NUMBER_UNORM ||
2373 ntype == V_028C70_NUMBER_SNORM ||
2374 ntype == V_028C70_NUMBER_SRGB)
2375 blend_clamp = 1;
2376
2377 /* set blend bypass according to docs if SINT/UINT or
2378 8/24 COLOR variants */
2379 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2380 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2381 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2382 blend_clamp = 0;
2383 blend_bypass = 1;
2384 }
2385
2386 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2387 if (format == V_028C70_COLOR_8 ||
2388 format == V_028C70_COLOR_8_8 ||
2389 format == V_028C70_COLOR_8_8_8_8)
2390 surf->color_is_int8 = true;
2391 else if (format == V_028C70_COLOR_10_10_10_2 ||
2392 format == V_028C70_COLOR_2_10_10_10)
2393 surf->color_is_int10 = true;
2394 }
2395
2396 color_info = S_028C70_FORMAT(format) |
2397 S_028C70_COMP_SWAP(swap) |
2398 S_028C70_BLEND_CLAMP(blend_clamp) |
2399 S_028C70_BLEND_BYPASS(blend_bypass) |
2400 S_028C70_SIMPLE_FLOAT(1) |
2401 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2402 ntype != V_028C70_NUMBER_SNORM &&
2403 ntype != V_028C70_NUMBER_SRGB &&
2404 format != V_028C70_COLOR_8_24 &&
2405 format != V_028C70_COLOR_24_8) |
2406 S_028C70_NUMBER_TYPE(ntype) |
2407 S_028C70_ENDIAN(endian);
2408
2409 /* Intensity is implemented as Red, so treat it that way. */
2410 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2411 util_format_is_intensity(surf->base.format));
2412
2413 if (rtex->buffer.b.b.nr_samples > 1) {
2414 unsigned log_samples = util_logbase2(rtex->buffer.b.b.nr_samples);
2415 unsigned log_fragments = util_logbase2(rtex->num_color_samples);
2416
2417 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2418 S_028C74_NUM_FRAGMENTS(log_fragments);
2419
2420 if (rtex->surface.fmask_size) {
2421 color_info |= S_028C70_COMPRESSION(1);
2422 unsigned fmask_bankh = util_logbase2(rtex->surface.u.legacy.fmask.bankh);
2423
2424 if (sctx->chip_class == SI) {
2425 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2426 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2427 }
2428 }
2429 }
2430
2431 if (sctx->chip_class >= VI) {
2432 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2433 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2434
2435 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2436 64 for APU because all of our APUs to date use DIMMs which have
2437 a request granularity size of 64B while all other chips have a
2438 32B request size */
2439 if (!sctx->screen->info.has_dedicated_vram)
2440 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2441
2442 if (rtex->num_color_samples > 1) {
2443 if (rtex->surface.bpe == 1)
2444 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2445 else if (rtex->surface.bpe == 2)
2446 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2447 }
2448
2449 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2450 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2451 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2452 }
2453
2454 /* This must be set for fast clear to work without FMASK. */
2455 if (!rtex->surface.fmask_size && sctx->chip_class == SI) {
2456 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2457 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2458 }
2459
2460 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2461 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2462
2463 if (sctx->chip_class >= GFX9) {
2464 unsigned mip0_depth = util_max_layer(&rtex->buffer.b.b, 0);
2465
2466 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2467 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2468 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2469 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2470 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2471 S_028C68_MAX_MIP(rtex->buffer.b.b.last_level);
2472 }
2473
2474 surf->cb_color_view = color_view;
2475 surf->cb_color_info = color_info;
2476 surf->cb_color_attrib = color_attrib;
2477
2478 /* Determine pixel shader export format */
2479 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2480
2481 surf->color_initialized = true;
2482 }
2483
2484 static void si_init_depth_surface(struct si_context *sctx,
2485 struct r600_surface *surf)
2486 {
2487 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2488 unsigned level = surf->base.u.tex.level;
2489 unsigned format, stencil_format;
2490 uint32_t z_info, s_info;
2491
2492 format = si_translate_dbformat(rtex->db_render_format);
2493 stencil_format = rtex->surface.has_stencil ?
2494 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2495
2496 assert(format != V_028040_Z_INVALID);
2497 if (format == V_028040_Z_INVALID)
2498 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->buffer.b.b.format);
2499
2500 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2501 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2502 surf->db_htile_data_base = 0;
2503 surf->db_htile_surface = 0;
2504
2505 if (sctx->chip_class >= GFX9) {
2506 assert(rtex->surface.u.gfx9.surf_offset == 0);
2507 surf->db_depth_base = rtex->buffer.gpu_address >> 8;
2508 surf->db_stencil_base = (rtex->buffer.gpu_address +
2509 rtex->surface.u.gfx9.stencil_offset) >> 8;
2510 z_info = S_028038_FORMAT(format) |
2511 S_028038_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples)) |
2512 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2513 S_028038_MAXMIP(rtex->buffer.b.b.last_level);
2514 s_info = S_02803C_FORMAT(stencil_format) |
2515 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2516 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2517 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2518 surf->db_depth_view |= S_028008_MIPID(level);
2519 surf->db_depth_size = S_02801C_X_MAX(rtex->buffer.b.b.width0 - 1) |
2520 S_02801C_Y_MAX(rtex->buffer.b.b.height0 - 1);
2521
2522 if (si_htile_enabled(rtex, level)) {
2523 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2524 S_028038_ALLOW_EXPCLEAR(1);
2525
2526 if (rtex->tc_compatible_htile) {
2527 unsigned max_zplanes = 4;
2528
2529 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2530 rtex->buffer.b.b.nr_samples > 1)
2531 max_zplanes = 2;
2532
2533 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2534 S_028038_ITERATE_FLUSH(1);
2535 s_info |= S_02803C_ITERATE_FLUSH(1);
2536 }
2537
2538 if (rtex->surface.has_stencil) {
2539 /* Stencil buffer workaround ported from the SI-CI-VI code.
2540 * See that for explanation.
2541 */
2542 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->buffer.b.b.nr_samples <= 1);
2543 } else {
2544 /* Use all HTILE for depth if there's no stencil. */
2545 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2546 }
2547
2548 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2549 rtex->htile_offset) >> 8;
2550 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2551 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2552 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2553 }
2554 } else {
2555 /* SI-CI-VI */
2556 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2557
2558 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2559
2560 surf->db_depth_base = (rtex->buffer.gpu_address +
2561 rtex->surface.u.legacy.level[level].offset) >> 8;
2562 surf->db_stencil_base = (rtex->buffer.gpu_address +
2563 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2564
2565 z_info = S_028040_FORMAT(format) |
2566 S_028040_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples));
2567 s_info = S_028044_FORMAT(stencil_format);
2568 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2569
2570 if (sctx->chip_class >= CIK) {
2571 struct radeon_info *info = &sctx->screen->info;
2572 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2573 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2574 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2575 unsigned tile_mode = info->si_tile_mode_array[index];
2576 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2577 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2578
2579 surf->db_depth_info |=
2580 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2581 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2582 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2583 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2584 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2585 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2586 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2587 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2588 } else {
2589 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2590 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2591 tile_mode_index = si_tile_mode_index(rtex, level, true);
2592 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2593 }
2594
2595 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2596 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2597 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2598 levelinfo->nblk_y) / 64 - 1);
2599
2600 if (si_htile_enabled(rtex, level)) {
2601 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2602 S_028040_ALLOW_EXPCLEAR(1);
2603
2604 if (rtex->surface.has_stencil) {
2605 /* Workaround: For a not yet understood reason, the
2606 * combination of MSAA, fast stencil clear and stencil
2607 * decompress messes with subsequent stencil buffer
2608 * uses. Problem was reproduced on Verde, Bonaire,
2609 * Tonga, and Carrizo.
2610 *
2611 * Disabling EXPCLEAR works around the problem.
2612 *
2613 * Check piglit's arb_texture_multisample-stencil-clear
2614 * test if you want to try changing this.
2615 */
2616 if (rtex->buffer.b.b.nr_samples <= 1)
2617 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2618 } else if (!rtex->tc_compatible_htile) {
2619 /* Use all of the htile_buffer for depth if there's no stencil.
2620 * This must not be set when TC-compatible HTILE is enabled
2621 * due to a hw bug.
2622 */
2623 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2624 }
2625
2626 surf->db_htile_data_base = (rtex->buffer.gpu_address +
2627 rtex->htile_offset) >> 8;
2628 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2629
2630 if (rtex->tc_compatible_htile) {
2631 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2632
2633 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2634 if (rtex->buffer.b.b.nr_samples <= 1)
2635 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2636 else if (rtex->buffer.b.b.nr_samples <= 4)
2637 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2638 else
2639 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2640 }
2641 }
2642 }
2643
2644 surf->db_z_info = z_info;
2645 surf->db_stencil_info = s_info;
2646
2647 surf->depth_initialized = true;
2648 }
2649
2650 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2651 {
2652 if (sctx->decompression_enabled)
2653 return;
2654
2655 if (sctx->framebuffer.state.zsbuf) {
2656 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2657 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2658
2659 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2660
2661 if (rtex->surface.has_stencil)
2662 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2663 }
2664
2665 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2666 while (compressed_cb_mask) {
2667 unsigned i = u_bit_scan(&compressed_cb_mask);
2668 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2669 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2670
2671 if (rtex->surface.fmask_size)
2672 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2673 if (rtex->dcc_gather_statistics)
2674 rtex->separate_dcc_dirty = true;
2675 }
2676 }
2677
2678 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2679 {
2680 for (int i = 0; i < state->nr_cbufs; ++i) {
2681 struct r600_surface *surf = NULL;
2682 struct r600_texture *rtex;
2683
2684 if (!state->cbufs[i])
2685 continue;
2686 surf = (struct r600_surface*)state->cbufs[i];
2687 rtex = (struct r600_texture*)surf->base.texture;
2688
2689 p_atomic_dec(&rtex->framebuffers_bound);
2690 }
2691 }
2692
2693 static void si_set_framebuffer_state(struct pipe_context *ctx,
2694 const struct pipe_framebuffer_state *state)
2695 {
2696 struct si_context *sctx = (struct si_context *)ctx;
2697 struct pipe_constant_buffer constbuf = {0};
2698 struct r600_surface *surf = NULL;
2699 struct r600_texture *rtex;
2700 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2701 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2702 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2703 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2704 bool old_has_stencil =
2705 old_has_zsbuf &&
2706 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2707 bool unbound = false;
2708 int i;
2709
2710 si_update_fb_dirtiness_after_rendering(sctx);
2711
2712 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2713 if (!sctx->framebuffer.state.cbufs[i])
2714 continue;
2715
2716 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2717 if (rtex->dcc_gather_statistics)
2718 vi_separate_dcc_stop_query(sctx, rtex);
2719 }
2720
2721 /* Disable DCC if the formats are incompatible. */
2722 for (i = 0; i < state->nr_cbufs; i++) {
2723 if (!state->cbufs[i])
2724 continue;
2725
2726 surf = (struct r600_surface*)state->cbufs[i];
2727 rtex = (struct r600_texture*)surf->base.texture;
2728
2729 if (!surf->dcc_incompatible)
2730 continue;
2731
2732 /* Since the DCC decompression calls back into set_framebuffer-
2733 * _state, we need to unbind the framebuffer, so that
2734 * vi_separate_dcc_stop_query isn't called twice with the same
2735 * color buffer.
2736 */
2737 if (!unbound) {
2738 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2739 unbound = true;
2740 }
2741
2742 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2743 if (!si_texture_disable_dcc(sctx, rtex))
2744 si_decompress_dcc(sctx, rtex);
2745
2746 surf->dcc_incompatible = false;
2747 }
2748
2749 /* Only flush TC when changing the framebuffer state, because
2750 * the only client not using TC that can change textures is
2751 * the framebuffer.
2752 *
2753 * Wait for compute shaders because of possible transitions:
2754 * - FB write -> shader read
2755 * - shader write -> FB read
2756 *
2757 * DB caches are flushed on demand (using si_decompress_textures).
2758 *
2759 * When MSAA is enabled, CB and TC caches are flushed on demand
2760 * (after FMASK decompression). Shader write -> FB read transitions
2761 * cannot happen for MSAA textures, because MSAA shader images are
2762 * not supported.
2763 *
2764 * Only flush and wait for CB if there is actually a bound color buffer.
2765 */
2766 if (sctx->framebuffer.uncompressed_cb_mask)
2767 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2768 sctx->framebuffer.CB_has_shader_readable_metadata);
2769
2770 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2771
2772 /* u_blitter doesn't invoke depth decompression when it does multiple
2773 * blits in a row, but the only case when it matters for DB is when
2774 * doing generate_mipmap. So here we flush DB manually between
2775 * individual generate_mipmap blits.
2776 * Note that lower mipmap levels aren't compressed.
2777 */
2778 if (sctx->generate_mipmap_for_depth) {
2779 si_make_DB_shader_coherent(sctx, 1, false,
2780 sctx->framebuffer.DB_has_shader_readable_metadata);
2781 } else if (sctx->chip_class == GFX9) {
2782 /* It appears that DB metadata "leaks" in a sequence of:
2783 * - depth clear
2784 * - DCC decompress for shader image writes (with DB disabled)
2785 * - render with DEPTH_BEFORE_SHADER=1
2786 * Flushing DB metadata works around the problem.
2787 */
2788 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2789 }
2790
2791 /* Take the maximum of the old and new count. If the new count is lower,
2792 * dirtying is needed to disable the unbound colorbuffers.
2793 */
2794 sctx->framebuffer.dirty_cbufs |=
2795 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2796 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2797
2798 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2799 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2800
2801 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2802 sctx->framebuffer.spi_shader_col_format = 0;
2803 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2804 sctx->framebuffer.spi_shader_col_format_blend = 0;
2805 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2806 sctx->framebuffer.color_is_int8 = 0;
2807 sctx->framebuffer.color_is_int10 = 0;
2808
2809 sctx->framebuffer.compressed_cb_mask = 0;
2810 sctx->framebuffer.uncompressed_cb_mask = 0;
2811 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2812 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2813 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2814 sctx->framebuffer.any_dst_linear = false;
2815 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2816 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2817
2818 for (i = 0; i < state->nr_cbufs; i++) {
2819 if (!state->cbufs[i])
2820 continue;
2821
2822 surf = (struct r600_surface*)state->cbufs[i];
2823 rtex = (struct r600_texture*)surf->base.texture;
2824
2825 if (!surf->color_initialized) {
2826 si_initialize_color_surface(sctx, surf);
2827 }
2828
2829 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2830 sctx->framebuffer.spi_shader_col_format |=
2831 surf->spi_shader_col_format << (i * 4);
2832 sctx->framebuffer.spi_shader_col_format_alpha |=
2833 surf->spi_shader_col_format_alpha << (i * 4);
2834 sctx->framebuffer.spi_shader_col_format_blend |=
2835 surf->spi_shader_col_format_blend << (i * 4);
2836 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2837 surf->spi_shader_col_format_blend_alpha << (i * 4);
2838
2839 if (surf->color_is_int8)
2840 sctx->framebuffer.color_is_int8 |= 1 << i;
2841 if (surf->color_is_int10)
2842 sctx->framebuffer.color_is_int10 |= 1 << i;
2843
2844 if (rtex->surface.fmask_size)
2845 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2846 else
2847 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2848
2849 /* Don't update nr_color_samples for non-AA buffers.
2850 * (e.g. destination of MSAA resolve)
2851 */
2852 if (rtex->buffer.b.b.nr_samples >= 2 &&
2853 rtex->num_color_samples < rtex->buffer.b.b.nr_samples) {
2854 sctx->framebuffer.nr_color_samples =
2855 MIN2(sctx->framebuffer.nr_color_samples,
2856 rtex->num_color_samples);
2857 }
2858
2859 if (rtex->surface.is_linear)
2860 sctx->framebuffer.any_dst_linear = true;
2861
2862 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2863 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2864
2865 si_context_add_resource_size(sctx, surf->base.texture);
2866
2867 p_atomic_inc(&rtex->framebuffers_bound);
2868
2869 if (rtex->dcc_gather_statistics) {
2870 /* Dirty tracking must be enabled for DCC usage analysis. */
2871 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2872 vi_separate_dcc_start_query(sctx, rtex);
2873 }
2874 }
2875
2876 struct r600_texture *zstex = NULL;
2877
2878 if (state->zsbuf) {
2879 surf = (struct r600_surface*)state->zsbuf;
2880 zstex = (struct r600_texture*)surf->base.texture;
2881
2882 if (!surf->depth_initialized) {
2883 si_init_depth_surface(sctx, surf);
2884 }
2885
2886 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2887 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2888
2889 si_context_add_resource_size(sctx, surf->base.texture);
2890 }
2891
2892 si_update_ps_colorbuf0_slot(sctx);
2893 si_update_poly_offset_state(sctx);
2894 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2895 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2896
2897 if (sctx->screen->dpbb_allowed)
2898 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2899
2900 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2901 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2902
2903 if (sctx->screen->has_out_of_order_rast &&
2904 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2905 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2906 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2907 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2908
2909 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2910 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2911 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2912
2913 /* Set sample locations as fragment shader constants. */
2914 switch (sctx->framebuffer.nr_samples) {
2915 case 1:
2916 constbuf.user_buffer = sctx->sample_locations_1x;
2917 break;
2918 case 2:
2919 constbuf.user_buffer = sctx->sample_locations_2x;
2920 break;
2921 case 4:
2922 constbuf.user_buffer = sctx->sample_locations_4x;
2923 break;
2924 case 8:
2925 constbuf.user_buffer = sctx->sample_locations_8x;
2926 break;
2927 case 16:
2928 constbuf.user_buffer = sctx->sample_locations_16x;
2929 break;
2930 default:
2931 PRINT_ERR("Requested an invalid number of samples %i.\n",
2932 sctx->framebuffer.nr_samples);
2933 assert(0);
2934 }
2935 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2936 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2937
2938 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2939 }
2940
2941 sctx->do_update_shaders = true;
2942
2943 if (!sctx->decompression_enabled) {
2944 /* Prevent textures decompression when the framebuffer state
2945 * changes come from the decompression passes themselves.
2946 */
2947 sctx->need_check_render_feedback = true;
2948 }
2949 }
2950
2951 static void si_emit_framebuffer_state(struct si_context *sctx)
2952 {
2953 struct radeon_winsys_cs *cs = sctx->gfx_cs;
2954 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2955 unsigned i, nr_cbufs = state->nr_cbufs;
2956 struct r600_texture *tex = NULL;
2957 struct r600_surface *cb = NULL;
2958 unsigned cb_color_info = 0;
2959
2960 /* Colorbuffers. */
2961 for (i = 0; i < nr_cbufs; i++) {
2962 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2963 unsigned cb_color_attrib;
2964
2965 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2966 continue;
2967
2968 cb = (struct r600_surface*)state->cbufs[i];
2969 if (!cb) {
2970 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2971 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2972 continue;
2973 }
2974
2975 tex = (struct r600_texture *)cb->base.texture;
2976 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2977 &tex->buffer, RADEON_USAGE_READWRITE,
2978 tex->buffer.b.b.nr_samples > 1 ?
2979 RADEON_PRIO_COLOR_BUFFER_MSAA :
2980 RADEON_PRIO_COLOR_BUFFER);
2981
2982 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
2983 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2984 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2985 RADEON_PRIO_CMASK);
2986 }
2987
2988 if (tex->dcc_separate_buffer)
2989 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2990 tex->dcc_separate_buffer,
2991 RADEON_USAGE_READWRITE,
2992 RADEON_PRIO_DCC);
2993
2994 /* Compute mutable surface parameters. */
2995 cb_color_base = tex->buffer.gpu_address >> 8;
2996 cb_color_fmask = 0;
2997 cb_color_cmask = tex->cmask.base_address_reg;
2998 cb_dcc_base = 0;
2999 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3000 cb_color_attrib = cb->cb_color_attrib;
3001
3002 if (cb->base.u.tex.level > 0)
3003 cb_color_info &= C_028C70_FAST_CLEAR;
3004
3005 if (tex->surface.fmask_size) {
3006 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3007 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3008 }
3009
3010 /* Set up DCC. */
3011 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3012 bool is_msaa_resolve_dst = state->cbufs[0] &&
3013 state->cbufs[0]->texture->nr_samples > 1 &&
3014 state->cbufs[1] == &cb->base &&
3015 state->cbufs[1]->texture->nr_samples <= 1;
3016
3017 if (!is_msaa_resolve_dst)
3018 cb_color_info |= S_028C70_DCC_ENABLE(1);
3019
3020 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3021 tex->dcc_offset) >> 8;
3022 cb_dcc_base |= tex->surface.tile_swizzle;
3023 }
3024
3025 if (sctx->chip_class >= GFX9) {
3026 struct gfx9_surf_meta_flags meta;
3027
3028 if (tex->dcc_offset)
3029 meta = tex->surface.u.gfx9.dcc;
3030 else
3031 meta = tex->surface.u.gfx9.cmask;
3032
3033 /* Set mutable surface parameters. */
3034 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3035 cb_color_base |= tex->surface.tile_swizzle;
3036 if (!tex->surface.fmask_size)
3037 cb_color_fmask = cb_color_base;
3038 if (cb->base.u.tex.level > 0)
3039 cb_color_cmask = cb_color_base;
3040 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3041 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3042 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3043 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3044
3045 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3046 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3047 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3048 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3049 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3050 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3051 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3052 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3053 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3054 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3055 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3056 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3057 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3058 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3059 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3060 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3061
3062 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3063 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3064 } else {
3065 /* Compute mutable surface parameters (SI-CI-VI). */
3066 const struct legacy_surf_level *level_info =
3067 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3068 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3069 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3070
3071 cb_color_base += level_info->offset >> 8;
3072 /* Only macrotiled modes can set tile swizzle. */
3073 if (level_info->mode == RADEON_SURF_MODE_2D)
3074 cb_color_base |= tex->surface.tile_swizzle;
3075
3076 if (!tex->surface.fmask_size)
3077 cb_color_fmask = cb_color_base;
3078 if (cb->base.u.tex.level > 0)
3079 cb_color_cmask = cb_color_base;
3080 if (cb_dcc_base)
3081 cb_dcc_base += level_info->dcc_offset >> 8;
3082
3083 pitch_tile_max = level_info->nblk_x / 8 - 1;
3084 slice_tile_max = level_info->nblk_x *
3085 level_info->nblk_y / 64 - 1;
3086 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3087
3088 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3089 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3090 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3091
3092 if (tex->surface.fmask_size) {
3093 if (sctx->chip_class >= CIK)
3094 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3095 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3096 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3097 } else {
3098 /* This must be set for fast clear to work without FMASK. */
3099 if (sctx->chip_class >= CIK)
3100 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3101 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3102 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3103 }
3104
3105 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3106 sctx->chip_class >= VI ? 14 : 13);
3107 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3108 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3109 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3110 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3111 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3112 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3113 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3114 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3115 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3116 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3117 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3118 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3119 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3120
3121 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3122 radeon_emit(cs, cb_dcc_base);
3123 }
3124 }
3125 for (; i < 8 ; i++)
3126 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3127 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3128
3129 /* ZS buffer. */
3130 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3131 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3132 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3133
3134 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3135 &rtex->buffer, RADEON_USAGE_READWRITE,
3136 zb->base.texture->nr_samples > 1 ?
3137 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3138 RADEON_PRIO_DEPTH_BUFFER);
3139
3140 if (sctx->chip_class >= GFX9) {
3141 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3142 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3143 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3144 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3145
3146 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3147 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3148 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3149 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3150 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3151 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3152 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3153 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3154 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3155 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3156 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3157 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3158
3159 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3160 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3161 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3162 } else {
3163 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3164
3165 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3166 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3167 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3168 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3169 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3170 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3171 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3172 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3173 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3174 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3175 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3176 }
3177
3178 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3179 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3180 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3181
3182 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3183 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3184 } else if (sctx->framebuffer.dirty_zsbuf) {
3185 if (sctx->chip_class >= GFX9)
3186 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3187 else
3188 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3189
3190 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3191 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3192 }
3193
3194 /* Framebuffer dimensions. */
3195 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3196 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3197 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3198
3199 if (sctx->screen->dfsm_allowed) {
3200 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3201 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3202 }
3203
3204 sctx->framebuffer.dirty_cbufs = 0;
3205 sctx->framebuffer.dirty_zsbuf = false;
3206 }
3207
3208 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3209 {
3210 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3211 unsigned nr_samples = sctx->framebuffer.nr_samples;
3212 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3213
3214 /* Smoothing (only possible with nr_samples == 1) uses the same
3215 * sample locations as the MSAA it simulates.
3216 */
3217 if (nr_samples <= 1 && sctx->smoothing_enabled)
3218 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3219
3220 /* On Polaris, the small primitive filter uses the sample locations
3221 * even when MSAA is off, so we need to make sure they're set to 0.
3222 */
3223 if (has_msaa_sample_loc_bug)
3224 nr_samples = MAX2(nr_samples, 1);
3225
3226 if (nr_samples != sctx->sample_locs_num_samples) {
3227 sctx->sample_locs_num_samples = nr_samples;
3228 si_emit_sample_locations(cs, nr_samples);
3229 }
3230
3231 if (sctx->family >= CHIP_POLARIS10) {
3232 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3233 unsigned small_prim_filter_cntl =
3234 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3235 /* line bug */
3236 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3237
3238 /* The alternative of setting sample locations to 0 would
3239 * require a DB flush to avoid Z errors, see
3240 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3241 */
3242 if (has_msaa_sample_loc_bug &&
3243 sctx->framebuffer.nr_samples > 1 &&
3244 rs && !rs->multisample_enable)
3245 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3246
3247 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3248 small_prim_filter_cntl);
3249 }
3250 }
3251
3252 static bool si_out_of_order_rasterization(struct si_context *sctx)
3253 {
3254 struct si_state_blend *blend = sctx->queued.named.blend;
3255 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3256
3257 if (!sctx->screen->has_out_of_order_rast)
3258 return false;
3259
3260 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3261
3262 if (blend) {
3263 colormask &= blend->cb_target_enabled_4bit;
3264 } else {
3265 colormask = 0;
3266 }
3267
3268 /* Conservative: No logic op. */
3269 if (colormask && blend->logicop_enable)
3270 return false;
3271
3272 struct si_dsa_order_invariance dsa_order_invariant = {
3273 .zs = true, .pass_set = true, .pass_last = false
3274 };
3275
3276 if (sctx->framebuffer.state.zsbuf) {
3277 struct r600_texture *zstex =
3278 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3279 bool has_stencil = zstex->surface.has_stencil;
3280 dsa_order_invariant = dsa->order_invariance[has_stencil];
3281 if (!dsa_order_invariant.zs)
3282 return false;
3283
3284 /* The set of PS invocations is always order invariant,
3285 * except when early Z/S tests are requested. */
3286 if (sctx->ps_shader.cso &&
3287 sctx->ps_shader.cso->info.writes_memory &&
3288 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3289 !dsa_order_invariant.pass_set)
3290 return false;
3291
3292 if (sctx->num_perfect_occlusion_queries != 0 &&
3293 !dsa_order_invariant.pass_set)
3294 return false;
3295 }
3296
3297 if (!colormask)
3298 return true;
3299
3300 unsigned blendmask = colormask & blend->blend_enable_4bit;
3301
3302 if (blendmask) {
3303 /* Only commutative blending. */
3304 if (blendmask & ~blend->commutative_4bit)
3305 return false;
3306
3307 if (!dsa_order_invariant.pass_set)
3308 return false;
3309 }
3310
3311 if (colormask & ~blendmask) {
3312 if (!dsa_order_invariant.pass_last)
3313 return false;
3314 }
3315
3316 return true;
3317 }
3318
3319 static void si_emit_msaa_config(struct si_context *sctx)
3320 {
3321 struct radeon_winsys_cs *cs = sctx->gfx_cs;
3322 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3323 /* 33% faster rendering to linear color buffers */
3324 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3325 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3326 unsigned sc_mode_cntl_1 =
3327 S_028A4C_WALK_SIZE(dst_is_linear) |
3328 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3329 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3330 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3331 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3332 /* always 1: */
3333 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3334 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3335 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3336 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3337 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3338 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3339 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3340 S_028804_INCOHERENT_EQAA_READS(1) |
3341 S_028804_INTERPOLATE_COMP_Z(1) |
3342 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3343 unsigned coverage_samples, color_samples;
3344
3345 /* S: Coverage samples (up to 16x):
3346 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3347 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3348 *
3349 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3350 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3351 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3352 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3353 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3354 * # Z samples).
3355 *
3356 * F: Color samples (up to 8x, must be <= coverage samples):
3357 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3358 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3359 *
3360 * Can be anything between coverage and color samples:
3361 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3362 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3363 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3364 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3365 * # All are currently set the same as coverage samples.
3366 *
3367 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3368 * flag for undefined color samples. A shader-based resolve must handle unknowns
3369 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3370 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3371 * useful. The CB resolve always drops unknowns.
3372 *
3373 * Sensible AA configurations:
3374 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3375 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3376 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3377 * EQAA 8s 8z 8f = 8x MSAA
3378 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3379 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3380 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3381 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3382 * EQAA 4s 4z 4f = 4x MSAA
3383 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3384 * EQAA 2s 2z 2f = 2x MSAA
3385 */
3386 if (sctx->framebuffer.nr_samples > 1) {
3387 coverage_samples = sctx->framebuffer.nr_samples;
3388 color_samples = sctx->framebuffer.nr_color_samples;
3389 } else if (sctx->smoothing_enabled) {
3390 coverage_samples = color_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3391 } else {
3392 coverage_samples = color_samples = 1;
3393 }
3394
3395 /* Required by OpenGL line rasterization.
3396 *
3397 * TODO: We should also enable perpendicular endcaps for AA lines,
3398 * but that requires implementing line stippling in the pixel
3399 * shader. SC can only do line stippling with axis-aligned
3400 * endcaps.
3401 */
3402 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3403
3404 if (coverage_samples > 1) {
3405 /* distance from the pixel center, indexed by log2(nr_samples) */
3406 static unsigned max_dist[] = {
3407 0, /* unused */
3408 4, /* 2x MSAA */
3409 6, /* 4x MSAA */
3410 7, /* 8x MSAA */
3411 8, /* 16x MSAA */
3412 };
3413 unsigned log_samples = util_logbase2(coverage_samples);
3414 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3415 ps_iter_samples = MIN2(ps_iter_samples, color_samples);
3416 unsigned log_ps_iter_samples =
3417 util_logbase2(util_next_power_of_two(ps_iter_samples));
3418
3419 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3420 radeon_emit(cs, sc_line_cntl |
3421 S_028BDC_EXPAND_LINE_WIDTH(1)); /* R_028BDC_PA_SC_LINE_CNTL */
3422 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3423 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3424 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* R_028BE0_PA_SC_AA_CONFIG */
3425
3426 if (sctx->framebuffer.nr_samples > 1) {
3427 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3428 db_eqaa |
3429 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3430 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3431 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3432 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples));
3433 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3434 S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1) |
3435 sc_mode_cntl_1);
3436 } else if (sctx->smoothing_enabled) {
3437 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3438 db_eqaa |
3439 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3440 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3441 sc_mode_cntl_1);
3442 }
3443 } else {
3444 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3445 radeon_emit(cs, sc_line_cntl); /* R_028BDC_PA_SC_LINE_CNTL */
3446 radeon_emit(cs, 0); /* R_028BE0_PA_SC_AA_CONFIG */
3447
3448 radeon_set_context_reg(cs, R_028804_DB_EQAA, db_eqaa);
3449 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3450 sc_mode_cntl_1);
3451 }
3452
3453 /* GFX9: Flush DFSM when the AA mode changes. */
3454 if (sctx->screen->dfsm_allowed) {
3455 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3456 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3457 }
3458 }
3459
3460 void si_update_ps_iter_samples(struct si_context *sctx)
3461 {
3462 if (sctx->framebuffer.nr_samples > 1)
3463 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3464 if (sctx->screen->dpbb_allowed)
3465 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3466 }
3467
3468 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3469 {
3470 struct si_context *sctx = (struct si_context *)ctx;
3471
3472 if (sctx->ps_iter_samples == min_samples)
3473 return;
3474
3475 sctx->ps_iter_samples = min_samples;
3476 sctx->do_update_shaders = true;
3477
3478 si_update_ps_iter_samples(sctx);
3479 }
3480
3481 /*
3482 * Samplers
3483 */
3484
3485 /**
3486 * Build the sampler view descriptor for a buffer texture.
3487 * @param state 256-bit descriptor; only the high 128 bits are filled in
3488 */
3489 void
3490 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3491 enum pipe_format format,
3492 unsigned offset, unsigned size,
3493 uint32_t *state)
3494 {
3495 const struct util_format_description *desc;
3496 int first_non_void;
3497 unsigned stride;
3498 unsigned num_records;
3499 unsigned num_format, data_format;
3500
3501 desc = util_format_description(format);
3502 first_non_void = util_format_get_first_non_void_channel(format);
3503 stride = desc->block.bits / 8;
3504 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3505 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3506
3507 num_records = size / stride;
3508 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3509
3510 /* The NUM_RECORDS field has a different meaning depending on the chip,
3511 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3512 *
3513 * SI-CIK:
3514 * - If STRIDE == 0, it's in byte units.
3515 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3516 *
3517 * VI:
3518 * - For SMEM and STRIDE == 0, it's in byte units.
3519 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3520 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3521 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3522 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3523 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3524 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3525 * That way the same descriptor can be used by both SMEM and VMEM.
3526 *
3527 * GFX9:
3528 * - For SMEM and STRIDE == 0, it's in byte units.
3529 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3530 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3531 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3532 */
3533 if (screen->info.chip_class >= GFX9)
3534 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3535 * from STRIDE to bytes. This works around it by setting
3536 * NUM_RECORDS to at least the size of one element, so that
3537 * the first element is readable when IDXEN == 0.
3538 *
3539 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3540 * IDXEN is enforced?
3541 */
3542 num_records = num_records ? MAX2(num_records, stride) : 0;
3543 else if (screen->info.chip_class == VI)
3544 num_records *= stride;
3545
3546 state[4] = 0;
3547 state[5] = S_008F04_STRIDE(stride);
3548 state[6] = num_records;
3549 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3550 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3551 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3552 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3553 S_008F0C_NUM_FORMAT(num_format) |
3554 S_008F0C_DATA_FORMAT(data_format);
3555 }
3556
3557 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3558 {
3559 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3560
3561 if (swizzle[3] == PIPE_SWIZZLE_X) {
3562 /* For the pre-defined border color values (white, opaque
3563 * black, transparent black), the only thing that matters is
3564 * that the alpha channel winds up in the correct place
3565 * (because the RGB channels are all the same) so either of
3566 * these enumerations will work.
3567 */
3568 if (swizzle[2] == PIPE_SWIZZLE_Y)
3569 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3570 else
3571 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3572 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3573 if (swizzle[1] == PIPE_SWIZZLE_Y)
3574 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3575 else
3576 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3577 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3578 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3579 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3580 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3581 }
3582
3583 return bc_swizzle;
3584 }
3585
3586 /**
3587 * Build the sampler view descriptor for a texture.
3588 */
3589 void
3590 si_make_texture_descriptor(struct si_screen *screen,
3591 struct r600_texture *tex,
3592 bool sampler,
3593 enum pipe_texture_target target,
3594 enum pipe_format pipe_format,
3595 const unsigned char state_swizzle[4],
3596 unsigned first_level, unsigned last_level,
3597 unsigned first_layer, unsigned last_layer,
3598 unsigned width, unsigned height, unsigned depth,
3599 uint32_t *state,
3600 uint32_t *fmask_state)
3601 {
3602 struct pipe_resource *res = &tex->buffer.b.b;
3603 const struct util_format_description *desc;
3604 unsigned char swizzle[4];
3605 int first_non_void;
3606 unsigned num_format, data_format, type, num_samples;
3607 uint64_t va;
3608
3609 desc = util_format_description(pipe_format);
3610
3611 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3612 MAX2(1, res->nr_samples) : tex->num_color_samples;
3613
3614 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3615 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3616 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3617 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3618
3619 switch (pipe_format) {
3620 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3621 case PIPE_FORMAT_X32_S8X24_UINT:
3622 case PIPE_FORMAT_X8Z24_UNORM:
3623 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3624 break;
3625 case PIPE_FORMAT_X24S8_UINT:
3626 /*
3627 * X24S8 is implemented as an 8_8_8_8 data format, to
3628 * fix texture gathers. This affects at least
3629 * GL45-CTS.texture_cube_map_array.sampling on VI.
3630 */
3631 if (screen->info.chip_class <= VI)
3632 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3633 else
3634 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3635 break;
3636 default:
3637 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3638 }
3639 } else {
3640 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3641 }
3642
3643 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3644
3645 switch (pipe_format) {
3646 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3647 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3648 break;
3649 default:
3650 if (first_non_void < 0) {
3651 if (util_format_is_compressed(pipe_format)) {
3652 switch (pipe_format) {
3653 case PIPE_FORMAT_DXT1_SRGB:
3654 case PIPE_FORMAT_DXT1_SRGBA:
3655 case PIPE_FORMAT_DXT3_SRGBA:
3656 case PIPE_FORMAT_DXT5_SRGBA:
3657 case PIPE_FORMAT_BPTC_SRGBA:
3658 case PIPE_FORMAT_ETC2_SRGB8:
3659 case PIPE_FORMAT_ETC2_SRGB8A1:
3660 case PIPE_FORMAT_ETC2_SRGBA8:
3661 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3662 break;
3663 case PIPE_FORMAT_RGTC1_SNORM:
3664 case PIPE_FORMAT_LATC1_SNORM:
3665 case PIPE_FORMAT_RGTC2_SNORM:
3666 case PIPE_FORMAT_LATC2_SNORM:
3667 case PIPE_FORMAT_ETC2_R11_SNORM:
3668 case PIPE_FORMAT_ETC2_RG11_SNORM:
3669 /* implies float, so use SNORM/UNORM to determine
3670 whether data is signed or not */
3671 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3672 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3673 break;
3674 default:
3675 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3676 break;
3677 }
3678 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3679 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3680 } else {
3681 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3682 }
3683 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3684 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3685 } else {
3686 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3687
3688 switch (desc->channel[first_non_void].type) {
3689 case UTIL_FORMAT_TYPE_FLOAT:
3690 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3691 break;
3692 case UTIL_FORMAT_TYPE_SIGNED:
3693 if (desc->channel[first_non_void].normalized)
3694 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3695 else if (desc->channel[first_non_void].pure_integer)
3696 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3697 else
3698 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3699 break;
3700 case UTIL_FORMAT_TYPE_UNSIGNED:
3701 if (desc->channel[first_non_void].normalized)
3702 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3703 else if (desc->channel[first_non_void].pure_integer)
3704 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3705 else
3706 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3707 }
3708 }
3709 }
3710
3711 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3712 if (data_format == ~0) {
3713 data_format = 0;
3714 }
3715
3716 /* S8 with Z32 HTILE needs a special format. */
3717 if (screen->info.chip_class >= GFX9 &&
3718 pipe_format == PIPE_FORMAT_S8_UINT &&
3719 tex->tc_compatible_htile)
3720 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3721
3722 if (!sampler &&
3723 (res->target == PIPE_TEXTURE_CUBE ||
3724 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3725 (screen->info.chip_class <= VI &&
3726 res->target == PIPE_TEXTURE_3D))) {
3727 /* For the purpose of shader images, treat cube maps and 3D
3728 * textures as 2D arrays. For 3D textures, the address
3729 * calculations for mipmaps are different, so we rely on the
3730 * caller to effectively disable mipmaps.
3731 */
3732 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3733
3734 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3735 } else {
3736 type = si_tex_dim(screen, tex, target, num_samples);
3737 }
3738
3739 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3740 height = 1;
3741 depth = res->array_size;
3742 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3743 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3744 if (sampler || res->target != PIPE_TEXTURE_3D)
3745 depth = res->array_size;
3746 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3747 depth = res->array_size / 6;
3748
3749 state[0] = 0;
3750 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3751 S_008F14_NUM_FORMAT_GFX6(num_format));
3752 state[2] = (S_008F18_WIDTH(width - 1) |
3753 S_008F18_HEIGHT(height - 1) |
3754 S_008F18_PERF_MOD(4));
3755 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3756 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3757 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3758 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3759 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3760 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3761 util_logbase2(num_samples) :
3762 last_level) |
3763 S_008F1C_TYPE(type));
3764 state[4] = 0;
3765 state[5] = S_008F24_BASE_ARRAY(first_layer);
3766 state[6] = 0;
3767 state[7] = 0;
3768
3769 if (screen->info.chip_class >= GFX9) {
3770 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3771
3772 /* Depth is the the last accessible layer on Gfx9.
3773 * The hw doesn't need to know the total number of layers.
3774 */
3775 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3776 state[4] |= S_008F20_DEPTH(depth - 1);
3777 else
3778 state[4] |= S_008F20_DEPTH(last_layer);
3779
3780 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3781 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3782 util_logbase2(num_samples) :
3783 tex->buffer.b.b.last_level);
3784 } else {
3785 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3786 state[4] |= S_008F20_DEPTH(depth - 1);
3787 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3788 }
3789
3790 if (tex->dcc_offset) {
3791 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3792 } else {
3793 /* The last dword is unused by hw. The shader uses it to clear
3794 * bits in the first dword of sampler state.
3795 */
3796 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3797 if (first_level == last_level)
3798 state[7] = C_008F30_MAX_ANISO_RATIO;
3799 else
3800 state[7] = 0xffffffff;
3801 }
3802 }
3803
3804 /* Initialize the sampler view for FMASK. */
3805 if (tex->surface.fmask_size) {
3806 uint32_t data_format, num_format;
3807
3808 va = tex->buffer.gpu_address + tex->fmask_offset;
3809
3810 #define FMASK(s,f) (((unsigned)(s) * 16) + (f))
3811 if (screen->info.chip_class >= GFX9) {
3812 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3813 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3814 case FMASK(2,1):
3815 num_format = V_008F14_IMG_FMASK_8_2_1;
3816 break;
3817 case FMASK(2,2):
3818 num_format = V_008F14_IMG_FMASK_8_2_2;
3819 break;
3820 case FMASK(4,1):
3821 num_format = V_008F14_IMG_FMASK_8_4_1;
3822 break;
3823 case FMASK(4,2):
3824 num_format = V_008F14_IMG_FMASK_8_4_2;
3825 break;
3826 case FMASK(4,4):
3827 num_format = V_008F14_IMG_FMASK_8_4_4;
3828 break;
3829 case FMASK(8,1):
3830 num_format = V_008F14_IMG_FMASK_8_8_1;
3831 break;
3832 case FMASK(8,2):
3833 num_format = V_008F14_IMG_FMASK_16_8_2;
3834 break;
3835 case FMASK(8,4):
3836 num_format = V_008F14_IMG_FMASK_32_8_4;
3837 break;
3838 case FMASK(8,8):
3839 num_format = V_008F14_IMG_FMASK_32_8_8;
3840 break;
3841 case FMASK(16,1):
3842 num_format = V_008F14_IMG_FMASK_16_16_1;
3843 break;
3844 case FMASK(16,2):
3845 num_format = V_008F14_IMG_FMASK_32_16_2;
3846 break;
3847 case FMASK(16,4):
3848 num_format = V_008F14_IMG_FMASK_64_16_4;
3849 break;
3850 case FMASK(16,8):
3851 num_format = V_008F14_IMG_FMASK_64_16_8;
3852 break;
3853 default:
3854 unreachable("invalid nr_samples");
3855 }
3856 } else {
3857 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3858 case FMASK(2,1):
3859 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3860 break;
3861 case FMASK(2,2):
3862 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3863 break;
3864 case FMASK(4,1):
3865 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3866 break;
3867 case FMASK(4,2):
3868 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3869 break;
3870 case FMASK(4,4):
3871 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3872 break;
3873 case FMASK(8,1):
3874 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3875 break;
3876 case FMASK(8,2):
3877 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3878 break;
3879 case FMASK(8,4):
3880 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3881 break;
3882 case FMASK(8,8):
3883 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3884 break;
3885 case FMASK(16,1):
3886 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3887 break;
3888 case FMASK(16,2):
3889 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3890 break;
3891 case FMASK(16,4):
3892 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3893 break;
3894 case FMASK(16,8):
3895 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3896 break;
3897 default:
3898 unreachable("invalid nr_samples");
3899 }
3900 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3901 }
3902 #undef FMASK
3903
3904 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3905 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3906 S_008F14_DATA_FORMAT_GFX6(data_format) |
3907 S_008F14_NUM_FORMAT_GFX6(num_format);
3908 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3909 S_008F18_HEIGHT(height - 1);
3910 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3911 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3912 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3913 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3914 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3915 fmask_state[4] = 0;
3916 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3917 fmask_state[6] = 0;
3918 fmask_state[7] = 0;
3919
3920 if (screen->info.chip_class >= GFX9) {
3921 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3922 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3923 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3924 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3925 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3926 } else {
3927 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3928 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3929 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3930 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3931 }
3932 }
3933 }
3934
3935 /**
3936 * Create a sampler view.
3937 *
3938 * @param ctx context
3939 * @param texture texture
3940 * @param state sampler view template
3941 * @param width0 width0 override (for compressed textures as int)
3942 * @param height0 height0 override (for compressed textures as int)
3943 * @param force_level set the base address to the level (for compressed textures)
3944 */
3945 struct pipe_sampler_view *
3946 si_create_sampler_view_custom(struct pipe_context *ctx,
3947 struct pipe_resource *texture,
3948 const struct pipe_sampler_view *state,
3949 unsigned width0, unsigned height0,
3950 unsigned force_level)
3951 {
3952 struct si_context *sctx = (struct si_context*)ctx;
3953 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3954 struct r600_texture *tmp = (struct r600_texture*)texture;
3955 unsigned base_level, first_level, last_level;
3956 unsigned char state_swizzle[4];
3957 unsigned height, depth, width;
3958 unsigned last_layer = state->u.tex.last_layer;
3959 enum pipe_format pipe_format;
3960 const struct legacy_surf_level *surflevel;
3961
3962 if (!view)
3963 return NULL;
3964
3965 /* initialize base object */
3966 view->base = *state;
3967 view->base.texture = NULL;
3968 view->base.reference.count = 1;
3969 view->base.context = ctx;
3970
3971 assert(texture);
3972 pipe_resource_reference(&view->base.texture, texture);
3973
3974 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3975 state->format == PIPE_FORMAT_S8X24_UINT ||
3976 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3977 state->format == PIPE_FORMAT_S8_UINT)
3978 view->is_stencil_sampler = true;
3979
3980 /* Buffer resource. */
3981 if (texture->target == PIPE_BUFFER) {
3982 si_make_buffer_descriptor(sctx->screen,
3983 r600_resource(texture),
3984 state->format,
3985 state->u.buf.offset,
3986 state->u.buf.size,
3987 view->state);
3988 return &view->base;
3989 }
3990
3991 state_swizzle[0] = state->swizzle_r;
3992 state_swizzle[1] = state->swizzle_g;
3993 state_swizzle[2] = state->swizzle_b;
3994 state_swizzle[3] = state->swizzle_a;
3995
3996 base_level = 0;
3997 first_level = state->u.tex.first_level;
3998 last_level = state->u.tex.last_level;
3999 width = width0;
4000 height = height0;
4001 depth = texture->depth0;
4002
4003 if (sctx->chip_class <= VI && force_level) {
4004 assert(force_level == first_level &&
4005 force_level == last_level);
4006 base_level = force_level;
4007 first_level = 0;
4008 last_level = 0;
4009 width = u_minify(width, force_level);
4010 height = u_minify(height, force_level);
4011 depth = u_minify(depth, force_level);
4012 }
4013
4014 /* This is not needed if state trackers set last_layer correctly. */
4015 if (state->target == PIPE_TEXTURE_1D ||
4016 state->target == PIPE_TEXTURE_2D ||
4017 state->target == PIPE_TEXTURE_RECT ||
4018 state->target == PIPE_TEXTURE_CUBE)
4019 last_layer = state->u.tex.first_layer;
4020
4021 /* Texturing with separate depth and stencil. */
4022 pipe_format = state->format;
4023
4024 /* Depth/stencil texturing sometimes needs separate texture. */
4025 if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
4026 if (!tmp->flushed_depth_texture &&
4027 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4028 pipe_resource_reference(&view->base.texture, NULL);
4029 FREE(view);
4030 return NULL;
4031 }
4032
4033 assert(tmp->flushed_depth_texture);
4034
4035 /* Override format for the case where the flushed texture
4036 * contains only Z or only S.
4037 */
4038 if (tmp->flushed_depth_texture->buffer.b.b.format != tmp->buffer.b.b.format)
4039 pipe_format = tmp->flushed_depth_texture->buffer.b.b.format;
4040
4041 tmp = tmp->flushed_depth_texture;
4042 }
4043
4044 surflevel = tmp->surface.u.legacy.level;
4045
4046 if (tmp->db_compatible) {
4047 if (!view->is_stencil_sampler)
4048 pipe_format = tmp->db_render_format;
4049
4050 switch (pipe_format) {
4051 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4052 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4053 break;
4054 case PIPE_FORMAT_X8Z24_UNORM:
4055 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4056 /* Z24 is always stored like this for DB
4057 * compatibility.
4058 */
4059 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4060 break;
4061 case PIPE_FORMAT_X24S8_UINT:
4062 case PIPE_FORMAT_S8X24_UINT:
4063 case PIPE_FORMAT_X32_S8X24_UINT:
4064 pipe_format = PIPE_FORMAT_S8_UINT;
4065 surflevel = tmp->surface.u.legacy.stencil_level;
4066 break;
4067 default:;
4068 }
4069 }
4070
4071 view->dcc_incompatible =
4072 vi_dcc_formats_are_incompatible(texture,
4073 state->u.tex.first_level,
4074 state->format);
4075
4076 si_make_texture_descriptor(sctx->screen, tmp, true,
4077 state->target, pipe_format, state_swizzle,
4078 first_level, last_level,
4079 state->u.tex.first_layer, last_layer,
4080 width, height, depth,
4081 view->state, view->fmask_state);
4082
4083 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4084 view->is_integer =
4085 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4086 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4087 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4088 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4089 view->base_level_info = &surflevel[base_level];
4090 view->base_level = base_level;
4091 view->block_width = util_format_get_blockwidth(pipe_format);
4092 return &view->base;
4093 }
4094
4095 static struct pipe_sampler_view *
4096 si_create_sampler_view(struct pipe_context *ctx,
4097 struct pipe_resource *texture,
4098 const struct pipe_sampler_view *state)
4099 {
4100 return si_create_sampler_view_custom(ctx, texture, state,
4101 texture ? texture->width0 : 0,
4102 texture ? texture->height0 : 0, 0);
4103 }
4104
4105 static void si_sampler_view_destroy(struct pipe_context *ctx,
4106 struct pipe_sampler_view *state)
4107 {
4108 struct si_sampler_view *view = (struct si_sampler_view *)state;
4109
4110 pipe_resource_reference(&state->texture, NULL);
4111 FREE(view);
4112 }
4113
4114 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4115 {
4116 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4117 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4118 (linear_filter &&
4119 (wrap == PIPE_TEX_WRAP_CLAMP ||
4120 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4121 }
4122
4123 static uint32_t si_translate_border_color(struct si_context *sctx,
4124 const struct pipe_sampler_state *state,
4125 const union pipe_color_union *color,
4126 bool is_integer)
4127 {
4128 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4129 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4130
4131 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4132 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4133 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4134 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4135
4136 #define simple_border_types(elt) \
4137 do { \
4138 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4139 color->elt[2] == 0 && color->elt[3] == 0) \
4140 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4141 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4142 color->elt[2] == 0 && color->elt[3] == 1) \
4143 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4144 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4145 color->elt[2] == 1 && color->elt[3] == 1) \
4146 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4147 } while (false)
4148
4149 if (is_integer)
4150 simple_border_types(ui);
4151 else
4152 simple_border_types(f);
4153
4154 #undef simple_border_types
4155
4156 int i;
4157
4158 /* Check if the border has been uploaded already. */
4159 for (i = 0; i < sctx->border_color_count; i++)
4160 if (memcmp(&sctx->border_color_table[i], color,
4161 sizeof(*color)) == 0)
4162 break;
4163
4164 if (i >= SI_MAX_BORDER_COLORS) {
4165 /* Getting 4096 unique border colors is very unlikely. */
4166 fprintf(stderr, "radeonsi: The border color table is full. "
4167 "Any new border colors will be just black. "
4168 "Please file a bug.\n");
4169 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4170 }
4171
4172 if (i == sctx->border_color_count) {
4173 /* Upload a new border color. */
4174 memcpy(&sctx->border_color_table[i], color,
4175 sizeof(*color));
4176 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4177 color, sizeof(*color));
4178 sctx->border_color_count++;
4179 }
4180
4181 return S_008F3C_BORDER_COLOR_PTR(i) |
4182 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4183 }
4184
4185 static inline int S_FIXED(float value, unsigned frac_bits)
4186 {
4187 return value * (1 << frac_bits);
4188 }
4189
4190 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4191 {
4192 if (filter == PIPE_TEX_FILTER_LINEAR)
4193 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4194 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4195 else
4196 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4197 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4198 }
4199
4200 static inline unsigned si_tex_aniso_filter(unsigned filter)
4201 {
4202 if (filter < 2)
4203 return 0;
4204 if (filter < 4)
4205 return 1;
4206 if (filter < 8)
4207 return 2;
4208 if (filter < 16)
4209 return 3;
4210 return 4;
4211 }
4212
4213 static void *si_create_sampler_state(struct pipe_context *ctx,
4214 const struct pipe_sampler_state *state)
4215 {
4216 struct si_context *sctx = (struct si_context *)ctx;
4217 struct si_screen *sscreen = sctx->screen;
4218 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4219 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4220 : state->max_anisotropy;
4221 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4222 union pipe_color_union clamped_border_color;
4223
4224 if (!rstate) {
4225 return NULL;
4226 }
4227
4228 #ifdef DEBUG
4229 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4230 #endif
4231 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4232 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4233 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4234 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4235 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4236 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4237 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4238 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4239 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4240 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4241 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4242 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4243 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4244 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4245 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4246 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4247 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4248 S_008F38_MIP_POINT_PRECLAMP(0) |
4249 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4250 S_008F38_FILTER_PREC_FIX(1) |
4251 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4252 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4253
4254 /* Create sampler resource for integer textures. */
4255 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4256 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4257
4258 /* Create sampler resource for upgraded depth textures. */
4259 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4260
4261 for (unsigned i = 0; i < 4; ++i) {
4262 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4263 * when the border color is 1.0. */
4264 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4265 }
4266
4267 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4268 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4269 else
4270 rstate->upgraded_depth_val[3] =
4271 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4272 S_008F3C_UPGRADED_DEPTH(1);
4273
4274 return rstate;
4275 }
4276
4277 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4278 {
4279 struct si_context *sctx = (struct si_context *)ctx;
4280
4281 if (sctx->sample_mask == (uint16_t)sample_mask)
4282 return;
4283
4284 sctx->sample_mask = sample_mask;
4285 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4286 }
4287
4288 static void si_emit_sample_mask(struct si_context *sctx)
4289 {
4290 struct radeon_winsys_cs *cs = sctx->gfx_cs;
4291 unsigned mask = sctx->sample_mask;
4292
4293 /* Needed for line and polygon smoothing as well as for the Polaris
4294 * small primitive filter. We expect the state tracker to take care of
4295 * this for us.
4296 */
4297 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4298 (mask & 1 && sctx->blitter->running));
4299
4300 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4301 radeon_emit(cs, mask | (mask << 16));
4302 radeon_emit(cs, mask | (mask << 16));
4303 }
4304
4305 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4306 {
4307 #ifdef DEBUG
4308 struct si_sampler_state *s = state;
4309
4310 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4311 s->magic = 0;
4312 #endif
4313 free(state);
4314 }
4315
4316 /*
4317 * Vertex elements & buffers
4318 */
4319
4320 static void *si_create_vertex_elements(struct pipe_context *ctx,
4321 unsigned count,
4322 const struct pipe_vertex_element *elements)
4323 {
4324 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4325 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4326 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4327 int i;
4328
4329 assert(count <= SI_MAX_ATTRIBS);
4330 if (!v)
4331 return NULL;
4332
4333 v->count = count;
4334 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4335
4336 for (i = 0; i < count; ++i) {
4337 const struct util_format_description *desc;
4338 const struct util_format_channel_description *channel;
4339 unsigned data_format, num_format;
4340 int first_non_void;
4341 unsigned vbo_index = elements[i].vertex_buffer_index;
4342 unsigned char swizzle[4];
4343
4344 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4345 FREE(v);
4346 return NULL;
4347 }
4348
4349 if (elements[i].instance_divisor) {
4350 v->uses_instance_divisors = true;
4351 v->instance_divisors[i] = elements[i].instance_divisor;
4352
4353 if (v->instance_divisors[i] == 1)
4354 v->instance_divisor_is_one |= 1u << i;
4355 else
4356 v->instance_divisor_is_fetched |= 1u << i;
4357 }
4358
4359 if (!used[vbo_index]) {
4360 v->first_vb_use_mask |= 1 << i;
4361 used[vbo_index] = true;
4362 }
4363
4364 desc = util_format_description(elements[i].src_format);
4365 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4366 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4367 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4368 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4369 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4370
4371 v->format_size[i] = desc->block.bits / 8;
4372 v->src_offset[i] = elements[i].src_offset;
4373 v->vertex_buffer_index[i] = vbo_index;
4374
4375 /* The hardware always treats the 2-bit alpha channel as
4376 * unsigned, so a shader workaround is needed. The affected
4377 * chips are VI and older except Stoney (GFX8.1).
4378 */
4379 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4380 sscreen->info.chip_class <= VI &&
4381 sscreen->info.family != CHIP_STONEY) {
4382 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4383 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4384 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4385 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4386 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4387 /* This isn't actually used in OpenGL. */
4388 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4389 }
4390 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4391 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4392 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4393 else
4394 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4395 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4396 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4397 if (channel->normalized) {
4398 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4399 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4400 else
4401 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4402 } else {
4403 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4404 }
4405 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4406 if (channel->normalized) {
4407 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4408 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4409 else
4410 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4411 } else {
4412 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4413 }
4414 }
4415 } else if (channel && channel->size == 64 &&
4416 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4417 switch (desc->nr_channels) {
4418 case 1:
4419 case 2:
4420 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4421 swizzle[0] = PIPE_SWIZZLE_X;
4422 swizzle[1] = PIPE_SWIZZLE_Y;
4423 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4424 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4425 break;
4426 case 3:
4427 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4428 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4429 swizzle[1] = PIPE_SWIZZLE_Y;
4430 swizzle[2] = PIPE_SWIZZLE_0;
4431 swizzle[3] = PIPE_SWIZZLE_0;
4432 break;
4433 case 4:
4434 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4435 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4436 swizzle[1] = PIPE_SWIZZLE_Y;
4437 swizzle[2] = PIPE_SWIZZLE_Z;
4438 swizzle[3] = PIPE_SWIZZLE_W;
4439 break;
4440 default:
4441 assert(0);
4442 }
4443 } else if (channel && desc->nr_channels == 3) {
4444 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4445
4446 if (channel->size == 8) {
4447 if (channel->pure_integer)
4448 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4449 else
4450 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4451 } else if (channel->size == 16) {
4452 if (channel->pure_integer)
4453 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4454 else
4455 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4456 }
4457 }
4458
4459 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4460 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4461 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4462 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4463 S_008F0C_NUM_FORMAT(num_format) |
4464 S_008F0C_DATA_FORMAT(data_format);
4465 }
4466 return v;
4467 }
4468
4469 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4470 {
4471 struct si_context *sctx = (struct si_context *)ctx;
4472 struct si_vertex_elements *old = sctx->vertex_elements;
4473 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4474
4475 sctx->vertex_elements = v;
4476 sctx->vertex_buffers_dirty = true;
4477
4478 if (v &&
4479 (!old ||
4480 old->count != v->count ||
4481 old->uses_instance_divisors != v->uses_instance_divisors ||
4482 v->uses_instance_divisors || /* we don't check which divisors changed */
4483 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4484 sctx->do_update_shaders = true;
4485
4486 if (v && v->instance_divisor_is_fetched) {
4487 struct pipe_constant_buffer cb;
4488
4489 cb.buffer = NULL;
4490 cb.user_buffer = v->instance_divisors;
4491 cb.buffer_offset = 0;
4492 cb.buffer_size = sizeof(uint32_t) * v->count;
4493 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4494 }
4495 }
4496
4497 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4498 {
4499 struct si_context *sctx = (struct si_context *)ctx;
4500
4501 if (sctx->vertex_elements == state)
4502 sctx->vertex_elements = NULL;
4503 FREE(state);
4504 }
4505
4506 static void si_set_vertex_buffers(struct pipe_context *ctx,
4507 unsigned start_slot, unsigned count,
4508 const struct pipe_vertex_buffer *buffers)
4509 {
4510 struct si_context *sctx = (struct si_context *)ctx;
4511 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4512 int i;
4513
4514 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4515
4516 if (buffers) {
4517 for (i = 0; i < count; i++) {
4518 const struct pipe_vertex_buffer *src = buffers + i;
4519 struct pipe_vertex_buffer *dsti = dst + i;
4520 struct pipe_resource *buf = src->buffer.resource;
4521
4522 pipe_resource_reference(&dsti->buffer.resource, buf);
4523 dsti->buffer_offset = src->buffer_offset;
4524 dsti->stride = src->stride;
4525 si_context_add_resource_size(sctx, buf);
4526 if (buf)
4527 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4528 }
4529 } else {
4530 for (i = 0; i < count; i++) {
4531 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4532 }
4533 }
4534 sctx->vertex_buffers_dirty = true;
4535 }
4536
4537 /*
4538 * Misc
4539 */
4540
4541 static void si_set_tess_state(struct pipe_context *ctx,
4542 const float default_outer_level[4],
4543 const float default_inner_level[2])
4544 {
4545 struct si_context *sctx = (struct si_context *)ctx;
4546 struct pipe_constant_buffer cb;
4547 float array[8];
4548
4549 memcpy(array, default_outer_level, sizeof(float) * 4);
4550 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4551
4552 cb.buffer = NULL;
4553 cb.user_buffer = NULL;
4554 cb.buffer_size = sizeof(array);
4555
4556 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4557 (void*)array, sizeof(array),
4558 &cb.buffer_offset);
4559
4560 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4561 pipe_resource_reference(&cb.buffer, NULL);
4562 }
4563
4564 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4565 {
4566 struct si_context *sctx = (struct si_context *)ctx;
4567
4568 si_update_fb_dirtiness_after_rendering(sctx);
4569
4570 /* Multisample surfaces are flushed in si_decompress_textures. */
4571 if (sctx->framebuffer.uncompressed_cb_mask)
4572 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4573 sctx->framebuffer.CB_has_shader_readable_metadata);
4574 }
4575
4576 /* This only ensures coherency for shader image/buffer stores. */
4577 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4578 {
4579 struct si_context *sctx = (struct si_context *)ctx;
4580
4581 /* Subsequent commands must wait for all shader invocations to
4582 * complete. */
4583 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4584 SI_CONTEXT_CS_PARTIAL_FLUSH;
4585
4586 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4587 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4588 SI_CONTEXT_INV_VMEM_L1;
4589
4590 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4591 PIPE_BARRIER_SHADER_BUFFER |
4592 PIPE_BARRIER_TEXTURE |
4593 PIPE_BARRIER_IMAGE |
4594 PIPE_BARRIER_STREAMOUT_BUFFER |
4595 PIPE_BARRIER_GLOBAL_BUFFER)) {
4596 /* As far as I can tell, L1 contents are written back to L2
4597 * automatically at end of shader, but the contents of other
4598 * L1 caches might still be stale. */
4599 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4600 }
4601
4602 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4603 /* Indices are read through TC L2 since VI.
4604 * L1 isn't used.
4605 */
4606 if (sctx->screen->info.chip_class <= CIK)
4607 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4608 }
4609
4610 /* MSAA color, any depth and any stencil are flushed in
4611 * si_decompress_textures when needed.
4612 */
4613 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4614 sctx->framebuffer.uncompressed_cb_mask) {
4615 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4616
4617 if (sctx->chip_class <= VI)
4618 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4619 }
4620
4621 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4622 if (sctx->screen->info.chip_class <= VI &&
4623 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4624 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4625 }
4626
4627 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4628 {
4629 struct pipe_blend_state blend;
4630
4631 memset(&blend, 0, sizeof(blend));
4632 blend.independent_blend_enable = true;
4633 blend.rt[0].colormask = 0xf;
4634 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4635 }
4636
4637 static void si_init_config(struct si_context *sctx);
4638
4639 void si_init_state_functions(struct si_context *sctx)
4640 {
4641 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4642 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4643 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4644 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4645 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4646 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4647 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4648 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4649 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4650 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4651 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4652
4653 sctx->b.create_blend_state = si_create_blend_state;
4654 sctx->b.bind_blend_state = si_bind_blend_state;
4655 sctx->b.delete_blend_state = si_delete_blend_state;
4656 sctx->b.set_blend_color = si_set_blend_color;
4657
4658 sctx->b.create_rasterizer_state = si_create_rs_state;
4659 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4660 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4661
4662 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4663 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4664 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4665
4666 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4667 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4668 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4669 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4670 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4671
4672 sctx->b.set_clip_state = si_set_clip_state;
4673 sctx->b.set_stencil_ref = si_set_stencil_ref;
4674
4675 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4676
4677 sctx->b.create_sampler_state = si_create_sampler_state;
4678 sctx->b.delete_sampler_state = si_delete_sampler_state;
4679
4680 sctx->b.create_sampler_view = si_create_sampler_view;
4681 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4682
4683 sctx->b.set_sample_mask = si_set_sample_mask;
4684
4685 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4686 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4687 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4688 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4689
4690 sctx->b.texture_barrier = si_texture_barrier;
4691 sctx->b.memory_barrier = si_memory_barrier;
4692 sctx->b.set_min_samples = si_set_min_samples;
4693 sctx->b.set_tess_state = si_set_tess_state;
4694
4695 sctx->b.set_active_query_state = si_set_active_query_state;
4696
4697 sctx->b.draw_vbo = si_draw_vbo;
4698
4699 si_init_config(sctx);
4700 }
4701
4702 void si_init_screen_state_functions(struct si_screen *sscreen)
4703 {
4704 sscreen->b.is_format_supported = si_is_format_supported;
4705 }
4706
4707 static void si_set_grbm_gfx_index(struct si_context *sctx,
4708 struct si_pm4_state *pm4, unsigned value)
4709 {
4710 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4711 R_00802C_GRBM_GFX_INDEX;
4712 si_pm4_set_reg(pm4, reg, value);
4713 }
4714
4715 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4716 struct si_pm4_state *pm4, unsigned se)
4717 {
4718 assert(se == ~0 || se < sctx->screen->info.max_se);
4719 si_set_grbm_gfx_index(sctx, pm4,
4720 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4721 S_030800_SE_INDEX(se)) |
4722 S_030800_SH_BROADCAST_WRITES(1) |
4723 S_030800_INSTANCE_BROADCAST_WRITES(1));
4724 }
4725
4726 static void
4727 si_write_harvested_raster_configs(struct si_context *sctx,
4728 struct si_pm4_state *pm4,
4729 unsigned raster_config,
4730 unsigned raster_config_1)
4731 {
4732 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4733 unsigned raster_config_se[4];
4734 unsigned se;
4735
4736 ac_get_harvested_configs(&sctx->screen->info,
4737 raster_config,
4738 &raster_config_1,
4739 raster_config_se);
4740
4741 for (se = 0; se < num_se; se++) {
4742 si_set_grbm_gfx_index_se(sctx, pm4, se);
4743 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4744 }
4745 si_set_grbm_gfx_index(sctx, pm4, ~0);
4746
4747 if (sctx->chip_class >= CIK) {
4748 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4749 }
4750 }
4751
4752 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4753 {
4754 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4755 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4756 unsigned raster_config, raster_config_1;
4757
4758 ac_get_raster_config(&sctx->screen->info,
4759 &raster_config,
4760 &raster_config_1);
4761
4762 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4763 /* Always use the default config when all backends are enabled
4764 * (or when we failed to determine the enabled backends).
4765 */
4766 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4767 raster_config);
4768 if (sctx->chip_class >= CIK)
4769 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4770 raster_config_1);
4771 } else {
4772 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4773 }
4774 }
4775
4776 static void si_init_config(struct si_context *sctx)
4777 {
4778 struct si_screen *sscreen = sctx->screen;
4779 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4780 bool has_clear_state = sscreen->has_clear_state;
4781 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4782
4783 /* Only SI can disable CLEAR_STATE for now. */
4784 assert(has_clear_state || sscreen->info.chip_class == SI);
4785
4786 if (!pm4)
4787 return;
4788
4789 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4790 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4791 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4792 si_pm4_cmd_end(pm4, false);
4793
4794 if (has_clear_state) {
4795 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4796 si_pm4_cmd_add(pm4, 0);
4797 si_pm4_cmd_end(pm4, false);
4798 }
4799
4800 if (sctx->chip_class <= VI)
4801 si_set_raster_config(sctx, pm4);
4802
4803 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4804 if (!has_clear_state)
4805 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4806
4807 /* FIXME calculate these values somehow ??? */
4808 if (sctx->chip_class <= VI) {
4809 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4810 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4811 }
4812
4813 if (!has_clear_state) {
4814 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4815 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4816 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4817 }
4818
4819 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4820 if (!has_clear_state)
4821 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4822 if (sctx->chip_class < CIK)
4823 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4824 S_008A14_CLIP_VTX_REORDER_ENA(1));
4825
4826 if (!has_clear_state)
4827 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4828
4829 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4830 * I don't know why. Deduced by trial and error.
4831 */
4832 if (sctx->chip_class <= CIK) {
4833 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4834 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4835 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4836 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4837 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4838 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4839 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4840 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4841 }
4842
4843 if (!has_clear_state) {
4844 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4845 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4846 S_028230_ER_TRI(0xA) |
4847 S_028230_ER_POINT(0xA) |
4848 S_028230_ER_RECT(0xA) |
4849 /* Required by DX10_DIAMOND_TEST_ENA: */
4850 S_028230_ER_LINE_LR(0x1A) |
4851 S_028230_ER_LINE_RL(0x26) |
4852 S_028230_ER_LINE_TB(0xA) |
4853 S_028230_ER_LINE_BT(0xA));
4854 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4855 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4856 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4857 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4858 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4859 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4860 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4861 }
4862
4863 if (sctx->chip_class >= GFX9) {
4864 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4865 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4866 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4867 } else {
4868 /* These registers, when written, also overwrite the CLEAR_STATE
4869 * context, so we can't rely on CLEAR_STATE setting them.
4870 * It would be an issue if there was another UMD changing them.
4871 */
4872 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4873 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4874 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4875 }
4876
4877 if (sctx->chip_class >= CIK) {
4878 if (sctx->chip_class >= GFX9) {
4879 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4880 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4881 } else {
4882 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4883 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4884 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4885 S_00B41C_WAVE_LIMIT(0x3F));
4886 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4887 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4888
4889 /* If this is 0, Bonaire can hang even if GS isn't being used.
4890 * Other chips are unaffected. These are suboptimal values,
4891 * but we don't use on-chip GS.
4892 */
4893 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4894 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4895 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4896 }
4897 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4898 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4899
4900 /* Compute LATE_ALLOC_VS.LIMIT. */
4901 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4902 (sscreen->info.max_se *
4903 sscreen->info.max_sh_per_se);
4904 unsigned late_alloc_limit; /* The limit is per SH. */
4905
4906 if (sctx->family == CHIP_KABINI) {
4907 late_alloc_limit = 0; /* Potential hang on Kabini. */
4908 } else if (num_cu_per_sh <= 4) {
4909 /* Too few available compute units per SH. Disallowing
4910 * VS to run on one CU could hurt us more than late VS
4911 * allocation would help.
4912 *
4913 * 2 is the highest safe number that allows us to keep
4914 * all CUs enabled.
4915 */
4916 late_alloc_limit = 2;
4917 } else {
4918 /* This is a good initial value, allowing 1 late_alloc
4919 * wave per SIMD on num_cu - 2.
4920 */
4921 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4922
4923 /* The limit is 0-based, so 0 means 1. */
4924 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4925 late_alloc_limit -= 1;
4926 }
4927
4928 /* VS can't execute on one CU if the limit is > 2. */
4929 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4930 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4931 S_00B118_WAVE_LIMIT(0x3F));
4932 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4933 S_00B11C_LIMIT(late_alloc_limit));
4934 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4935 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4936 }
4937
4938 if (sctx->chip_class >= VI) {
4939 unsigned vgt_tess_distribution;
4940
4941 vgt_tess_distribution =
4942 S_028B50_ACCUM_ISOLINE(32) |
4943 S_028B50_ACCUM_TRI(11) |
4944 S_028B50_ACCUM_QUAD(11) |
4945 S_028B50_DONUT_SPLIT(16);
4946
4947 /* Testing with Unigine Heaven extreme tesselation yielded best results
4948 * with TRAP_SPLIT = 3.
4949 */
4950 if (sctx->family == CHIP_FIJI ||
4951 sctx->family >= CHIP_POLARIS10)
4952 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4953
4954 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4955 } else if (!has_clear_state) {
4956 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4957 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4958 }
4959
4960 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4961 if (sctx->chip_class >= CIK) {
4962 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4963 S_028084_ADDRESS(border_color_va >> 40));
4964 }
4965 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4966 RADEON_PRIO_BORDER_COLORS);
4967
4968 if (sctx->chip_class >= GFX9) {
4969 unsigned num_se = sscreen->info.max_se;
4970 unsigned pc_lines = 0;
4971
4972 switch (sctx->family) {
4973 case CHIP_VEGA10:
4974 case CHIP_VEGA12:
4975 pc_lines = 4096;
4976 break;
4977 case CHIP_RAVEN:
4978 pc_lines = 1024;
4979 break;
4980 default:
4981 assert(0);
4982 }
4983
4984 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4985 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4986 S_028C48_MAX_PRIM_PER_BATCH(1023));
4987 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4988 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4989 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4990 }
4991
4992 si_pm4_upload_indirect_buffer(sctx, pm4);
4993 sctx->init_config = pm4;
4994 }