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radeonsi: remove 8 bytes from si_shader_key by flattening opt.hw_vs
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 struct si_state_blend *old_blend = sctx->queued.named.blend;
607 struct si_state_blend *blend = (struct si_state_blend *)state;
608
609 if (!state)
610 return;
611
612 if (!old_blend ||
613 old_blend->cb_target_mask != blend->cb_target_mask ||
614 old_blend->dual_src_blend != blend->dual_src_blend)
615 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
616
617 si_pm4_bind_state(sctx, blend, state);
618
619 if (!old_blend ||
620 old_blend->cb_target_mask != blend->cb_target_mask ||
621 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
622 old_blend->alpha_to_one != blend->alpha_to_one ||
623 old_blend->dual_src_blend != blend->dual_src_blend ||
624 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
625 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
626 sctx->do_update_shaders = true;
627 }
628
629 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
630 {
631 struct si_context *sctx = (struct si_context *)ctx;
632 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
633 }
634
635 static void si_set_blend_color(struct pipe_context *ctx,
636 const struct pipe_blend_color *state)
637 {
638 struct si_context *sctx = (struct si_context *)ctx;
639
640 sctx->blend_color.state = *state;
641 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
642 }
643
644 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
645 {
646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
647
648 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
649 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
650 }
651
652 /*
653 * Clipping
654 */
655
656 static void si_set_clip_state(struct pipe_context *ctx,
657 const struct pipe_clip_state *state)
658 {
659 struct si_context *sctx = (struct si_context *)ctx;
660 struct pipe_constant_buffer cb;
661
662 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
663 return;
664
665 sctx->clip_state.state = *state;
666 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
667
668 cb.buffer = NULL;
669 cb.user_buffer = state->ucp;
670 cb.buffer_offset = 0;
671 cb.buffer_size = 4*4*8;
672 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
673 pipe_resource_reference(&cb.buffer, NULL);
674 }
675
676 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
677 {
678 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
679
680 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
681 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
682 }
683
684 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
685 {
686 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
687 struct si_shader *vs = si_get_vs_state(sctx);
688 struct si_shader_selector *vs_sel = vs->selector;
689 struct tgsi_shader_info *info = &vs_sel->info;
690 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
691 unsigned window_space =
692 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
693 unsigned clipdist_mask = vs_sel->clipdist_mask;
694 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
695 unsigned culldist_mask = vs_sel->culldist_mask;
696 unsigned total_mask;
697
698 if (vs->key.opt.clip_disable) {
699 assert(!info->culldist_writemask);
700 clipdist_mask = 0;
701 culldist_mask = 0;
702 }
703 total_mask = clipdist_mask | culldist_mask;
704
705 /* Clip distances on points have no effect, so need to be implemented
706 * as cull distances. This applies for the clipvertex case as well.
707 *
708 * Setting this for primitives other than points should have no adverse
709 * effects.
710 */
711 clipdist_mask &= rs->clip_plane_enable;
712 culldist_mask |= clipdist_mask;
713
714 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
715 vs_sel->pa_cl_vs_out_cntl |
716 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
717 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
718 clipdist_mask | (culldist_mask << 8));
719 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
720 rs->pa_cl_clip_cntl |
721 ucp_mask |
722 S_028810_CLIP_DISABLE(window_space));
723
724 if (sctx->b.chip_class <= VI) {
725 /* reuse needs to be set off if we write oViewport */
726 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
727 S_028AB4_REUSE_OFF(info->writes_viewport_index));
728 }
729 }
730
731 /*
732 * inferred state between framebuffer and rasterizer
733 */
734 static void si_update_poly_offset_state(struct si_context *sctx)
735 {
736 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
737
738 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
739 si_pm4_bind_state(sctx, poly_offset, NULL);
740 return;
741 }
742
743 /* Use the user format, not db_render_format, so that the polygon
744 * offset behaves as expected by applications.
745 */
746 switch (sctx->framebuffer.state.zsbuf->texture->format) {
747 case PIPE_FORMAT_Z16_UNORM:
748 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
749 break;
750 default: /* 24-bit */
751 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
752 break;
753 case PIPE_FORMAT_Z32_FLOAT:
754 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
755 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
756 break;
757 }
758 }
759
760 /*
761 * Rasterizer
762 */
763
764 static uint32_t si_translate_fill(uint32_t func)
765 {
766 switch(func) {
767 case PIPE_POLYGON_MODE_FILL:
768 return V_028814_X_DRAW_TRIANGLES;
769 case PIPE_POLYGON_MODE_LINE:
770 return V_028814_X_DRAW_LINES;
771 case PIPE_POLYGON_MODE_POINT:
772 return V_028814_X_DRAW_POINTS;
773 default:
774 assert(0);
775 return V_028814_X_DRAW_POINTS;
776 }
777 }
778
779 static void *si_create_rs_state(struct pipe_context *ctx,
780 const struct pipe_rasterizer_state *state)
781 {
782 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
783 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
784 struct si_pm4_state *pm4 = &rs->pm4;
785 unsigned tmp, i;
786 float psize_min, psize_max;
787
788 if (!rs) {
789 return NULL;
790 }
791
792 rs->scissor_enable = state->scissor;
793 rs->clip_halfz = state->clip_halfz;
794 rs->two_side = state->light_twoside;
795 rs->multisample_enable = state->multisample;
796 rs->force_persample_interp = state->force_persample_interp;
797 rs->clip_plane_enable = state->clip_plane_enable;
798 rs->line_stipple_enable = state->line_stipple_enable;
799 rs->poly_stipple_enable = state->poly_stipple_enable;
800 rs->line_smooth = state->line_smooth;
801 rs->poly_smooth = state->poly_smooth;
802 rs->uses_poly_offset = state->offset_point || state->offset_line ||
803 state->offset_tri;
804 rs->clamp_fragment_color = state->clamp_fragment_color;
805 rs->clamp_vertex_color = state->clamp_vertex_color;
806 rs->flatshade = state->flatshade;
807 rs->sprite_coord_enable = state->sprite_coord_enable;
808 rs->rasterizer_discard = state->rasterizer_discard;
809 rs->pa_sc_line_stipple = state->line_stipple_enable ?
810 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
811 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
812 rs->pa_cl_clip_cntl =
813 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
814 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
815 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
816 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
817 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
818
819 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
820 S_0286D4_FLAT_SHADE_ENA(1) |
821 S_0286D4_PNT_SPRITE_ENA(1) |
822 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
823 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
824 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
825 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
826 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
827
828 /* point size 12.4 fixed point */
829 tmp = (unsigned)(state->point_size * 8.0);
830 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
831
832 if (state->point_size_per_vertex) {
833 psize_min = util_get_min_point_size(state);
834 psize_max = 8192;
835 } else {
836 /* Force the point size to be as if the vertex output was disabled. */
837 psize_min = state->point_size;
838 psize_max = state->point_size;
839 }
840 /* Divide by two, because 0.5 = 1 pixel. */
841 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
842 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
843 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
844
845 tmp = (unsigned)state->line_width * 8;
846 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
847 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
848 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
849 S_028A48_MSAA_ENABLE(state->multisample ||
850 state->poly_smooth ||
851 state->line_smooth) |
852 S_028A48_VPORT_SCISSOR_ENABLE(1) |
853 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
854
855 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
856 S_028BE4_PIX_CENTER(state->half_pixel_center) |
857 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
858
859 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
860 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
861 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
862 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
863 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
864 S_028814_FACE(!state->front_ccw) |
865 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
866 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
867 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
868 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
869 state->fill_back != PIPE_POLYGON_MODE_FILL) |
870 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
871 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
872
873 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
874 for (i = 0; i < 3; i++) {
875 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
876 float offset_units = state->offset_units;
877 float offset_scale = state->offset_scale * 16.0f;
878 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
879
880 if (!state->offset_units_unscaled) {
881 switch (i) {
882 case 0: /* 16-bit zbuffer */
883 offset_units *= 4.0f;
884 pa_su_poly_offset_db_fmt_cntl =
885 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
886 break;
887 case 1: /* 24-bit zbuffer */
888 offset_units *= 2.0f;
889 pa_su_poly_offset_db_fmt_cntl =
890 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
891 break;
892 case 2: /* 32-bit zbuffer */
893 offset_units *= 1.0f;
894 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
895 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
896 break;
897 }
898 }
899
900 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
901 fui(offset_scale));
902 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
903 fui(offset_units));
904 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
905 fui(offset_scale));
906 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
907 fui(offset_units));
908 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
909 pa_su_poly_offset_db_fmt_cntl);
910 }
911
912 return rs;
913 }
914
915 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
916 {
917 struct si_context *sctx = (struct si_context *)ctx;
918 struct si_state_rasterizer *old_rs =
919 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
920 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
921
922 if (!state)
923 return;
924
925 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
926 si_mark_atom_dirty(sctx, &sctx->db_render_state);
927
928 /* Update the small primitive filter workaround if necessary. */
929 if (sctx->screen->has_msaa_sample_loc_bug &&
930 sctx->framebuffer.nr_samples > 1)
931 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
932 }
933
934 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
935 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
936
937 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
938
939 si_pm4_bind_state(sctx, rasterizer, rs);
940 si_update_poly_offset_state(sctx);
941
942 if (!old_rs ||
943 old_rs->clip_plane_enable != rs->clip_plane_enable ||
944 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
945 si_mark_atom_dirty(sctx, &sctx->clip_regs);
946
947 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
948 rs->line_stipple_enable;
949
950 if (!old_rs ||
951 old_rs->clip_plane_enable != rs->clip_plane_enable ||
952 old_rs->rasterizer_discard != rs->rasterizer_discard ||
953 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
954 old_rs->flatshade != rs->flatshade ||
955 old_rs->two_side != rs->two_side ||
956 old_rs->multisample_enable != rs->multisample_enable ||
957 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
958 old_rs->poly_smooth != rs->poly_smooth ||
959 old_rs->line_smooth != rs->line_smooth ||
960 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
961 old_rs->force_persample_interp != rs->force_persample_interp)
962 sctx->do_update_shaders = true;
963 }
964
965 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
966 {
967 struct si_context *sctx = (struct si_context *)ctx;
968
969 if (sctx->queued.named.rasterizer == state)
970 si_pm4_bind_state(sctx, poly_offset, NULL);
971 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
972 }
973
974 /*
975 * infeered state between dsa and stencil ref
976 */
977 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
978 {
979 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
980 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
981 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
982
983 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
984 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
985 S_028430_STENCILMASK(dsa->valuemask[0]) |
986 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
987 S_028430_STENCILOPVAL(1));
988 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
989 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
990 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
991 S_028434_STENCILOPVAL_BF(1));
992 }
993
994 static void si_set_stencil_ref(struct pipe_context *ctx,
995 const struct pipe_stencil_ref *state)
996 {
997 struct si_context *sctx = (struct si_context *)ctx;
998
999 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1000 return;
1001
1002 sctx->stencil_ref.state = *state;
1003 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1004 }
1005
1006
1007 /*
1008 * DSA
1009 */
1010
1011 static uint32_t si_translate_stencil_op(int s_op)
1012 {
1013 switch (s_op) {
1014 case PIPE_STENCIL_OP_KEEP:
1015 return V_02842C_STENCIL_KEEP;
1016 case PIPE_STENCIL_OP_ZERO:
1017 return V_02842C_STENCIL_ZERO;
1018 case PIPE_STENCIL_OP_REPLACE:
1019 return V_02842C_STENCIL_REPLACE_TEST;
1020 case PIPE_STENCIL_OP_INCR:
1021 return V_02842C_STENCIL_ADD_CLAMP;
1022 case PIPE_STENCIL_OP_DECR:
1023 return V_02842C_STENCIL_SUB_CLAMP;
1024 case PIPE_STENCIL_OP_INCR_WRAP:
1025 return V_02842C_STENCIL_ADD_WRAP;
1026 case PIPE_STENCIL_OP_DECR_WRAP:
1027 return V_02842C_STENCIL_SUB_WRAP;
1028 case PIPE_STENCIL_OP_INVERT:
1029 return V_02842C_STENCIL_INVERT;
1030 default:
1031 R600_ERR("Unknown stencil op %d", s_op);
1032 assert(0);
1033 break;
1034 }
1035 return 0;
1036 }
1037
1038 static void *si_create_dsa_state(struct pipe_context *ctx,
1039 const struct pipe_depth_stencil_alpha_state *state)
1040 {
1041 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1042 struct si_pm4_state *pm4 = &dsa->pm4;
1043 unsigned db_depth_control;
1044 uint32_t db_stencil_control = 0;
1045
1046 if (!dsa) {
1047 return NULL;
1048 }
1049
1050 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1051 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1052 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1053 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1054
1055 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1056 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1057 S_028800_ZFUNC(state->depth.func) |
1058 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1059
1060 /* stencil */
1061 if (state->stencil[0].enabled) {
1062 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1063 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1064 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1065 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1066 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1067
1068 if (state->stencil[1].enabled) {
1069 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1070 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1071 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1072 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1073 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1074 }
1075 }
1076
1077 /* alpha */
1078 if (state->alpha.enabled) {
1079 dsa->alpha_func = state->alpha.func;
1080
1081 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1082 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1083 } else {
1084 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1085 }
1086
1087 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1088 if (state->stencil[0].enabled)
1089 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1090 if (state->depth.bounds_test) {
1091 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1092 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1093 }
1094
1095 return dsa;
1096 }
1097
1098 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1099 {
1100 struct si_context *sctx = (struct si_context *)ctx;
1101 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1102 struct si_state_dsa *dsa = state;
1103
1104 if (!state)
1105 return;
1106
1107 si_pm4_bind_state(sctx, dsa, dsa);
1108
1109 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1110 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1111 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1112 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1113 }
1114
1115 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1116 sctx->do_update_shaders = true;
1117 }
1118
1119 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1120 {
1121 struct si_context *sctx = (struct si_context *)ctx;
1122 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1123 }
1124
1125 static void *si_create_db_flush_dsa(struct si_context *sctx)
1126 {
1127 struct pipe_depth_stencil_alpha_state dsa = {};
1128
1129 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1130 }
1131
1132 /* DB RENDER STATE */
1133
1134 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1135 {
1136 struct si_context *sctx = (struct si_context*)ctx;
1137
1138 /* Pipeline stat & streamout queries. */
1139 if (enable) {
1140 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1141 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1142 } else {
1143 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1144 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1145 }
1146
1147 /* Occlusion queries. */
1148 if (sctx->occlusion_queries_disabled != !enable) {
1149 sctx->occlusion_queries_disabled = !enable;
1150 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1151 }
1152 }
1153
1154 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1155 {
1156 struct si_context *sctx = (struct si_context*)ctx;
1157
1158 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1159 }
1160
1161 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1162 {
1163 struct si_context *sctx = (struct si_context*)ctx;
1164
1165 st->saved_compute = sctx->cs_shader_state.program;
1166
1167 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1168 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1169 }
1170
1171 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1172 {
1173 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1174 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1175 unsigned db_shader_control;
1176
1177 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1178
1179 /* DB_RENDER_CONTROL */
1180 if (sctx->dbcb_depth_copy_enabled ||
1181 sctx->dbcb_stencil_copy_enabled) {
1182 radeon_emit(cs,
1183 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1184 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1185 S_028000_COPY_CENTROID(1) |
1186 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1187 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1188 radeon_emit(cs,
1189 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1190 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1191 } else {
1192 radeon_emit(cs,
1193 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1194 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1195 }
1196
1197 /* DB_COUNT_CONTROL (occlusion queries) */
1198 if (sctx->b.num_occlusion_queries > 0 &&
1199 !sctx->occlusion_queries_disabled) {
1200 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1201
1202 if (sctx->b.chip_class >= CIK) {
1203 radeon_emit(cs,
1204 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1205 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1206 S_028004_ZPASS_ENABLE(1) |
1207 S_028004_SLICE_EVEN_ENABLE(1) |
1208 S_028004_SLICE_ODD_ENABLE(1));
1209 } else {
1210 radeon_emit(cs,
1211 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1212 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1213 }
1214 } else {
1215 /* Disable occlusion queries. */
1216 if (sctx->b.chip_class >= CIK) {
1217 radeon_emit(cs, 0);
1218 } else {
1219 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1220 }
1221 }
1222
1223 /* DB_RENDER_OVERRIDE2 */
1224 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1225 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1226 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1227 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1228
1229 db_shader_control = sctx->ps_db_shader_control;
1230
1231 /* Bug workaround for smoothing (overrasterization) on SI. */
1232 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1233 db_shader_control &= C_02880C_Z_ORDER;
1234 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1235 }
1236
1237 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1238 if (!rs || !rs->multisample_enable)
1239 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1240
1241 if (sctx->screen->b.has_rbplus &&
1242 !sctx->screen->b.rbplus_allowed)
1243 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1244
1245 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1246 db_shader_control);
1247 }
1248
1249 /*
1250 * format translation
1251 */
1252 static uint32_t si_translate_colorformat(enum pipe_format format)
1253 {
1254 const struct util_format_description *desc = util_format_description(format);
1255
1256 #define HAS_SIZE(x,y,z,w) \
1257 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1258 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1259
1260 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1261 return V_028C70_COLOR_10_11_11;
1262
1263 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1264 return V_028C70_COLOR_INVALID;
1265
1266 /* hw cannot support mixed formats (except depth/stencil, since
1267 * stencil is not written to). */
1268 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1269 return V_028C70_COLOR_INVALID;
1270
1271 switch (desc->nr_channels) {
1272 case 1:
1273 switch (desc->channel[0].size) {
1274 case 8:
1275 return V_028C70_COLOR_8;
1276 case 16:
1277 return V_028C70_COLOR_16;
1278 case 32:
1279 return V_028C70_COLOR_32;
1280 }
1281 break;
1282 case 2:
1283 if (desc->channel[0].size == desc->channel[1].size) {
1284 switch (desc->channel[0].size) {
1285 case 8:
1286 return V_028C70_COLOR_8_8;
1287 case 16:
1288 return V_028C70_COLOR_16_16;
1289 case 32:
1290 return V_028C70_COLOR_32_32;
1291 }
1292 } else if (HAS_SIZE(8,24,0,0)) {
1293 return V_028C70_COLOR_24_8;
1294 } else if (HAS_SIZE(24,8,0,0)) {
1295 return V_028C70_COLOR_8_24;
1296 }
1297 break;
1298 case 3:
1299 if (HAS_SIZE(5,6,5,0)) {
1300 return V_028C70_COLOR_5_6_5;
1301 } else if (HAS_SIZE(32,8,24,0)) {
1302 return V_028C70_COLOR_X24_8_32_FLOAT;
1303 }
1304 break;
1305 case 4:
1306 if (desc->channel[0].size == desc->channel[1].size &&
1307 desc->channel[0].size == desc->channel[2].size &&
1308 desc->channel[0].size == desc->channel[3].size) {
1309 switch (desc->channel[0].size) {
1310 case 4:
1311 return V_028C70_COLOR_4_4_4_4;
1312 case 8:
1313 return V_028C70_COLOR_8_8_8_8;
1314 case 16:
1315 return V_028C70_COLOR_16_16_16_16;
1316 case 32:
1317 return V_028C70_COLOR_32_32_32_32;
1318 }
1319 } else if (HAS_SIZE(5,5,5,1)) {
1320 return V_028C70_COLOR_1_5_5_5;
1321 } else if (HAS_SIZE(10,10,10,2)) {
1322 return V_028C70_COLOR_2_10_10_10;
1323 }
1324 break;
1325 }
1326 return V_028C70_COLOR_INVALID;
1327 }
1328
1329 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1330 {
1331 if (SI_BIG_ENDIAN) {
1332 switch(colorformat) {
1333 /* 8-bit buffers. */
1334 case V_028C70_COLOR_8:
1335 return V_028C70_ENDIAN_NONE;
1336
1337 /* 16-bit buffers. */
1338 case V_028C70_COLOR_5_6_5:
1339 case V_028C70_COLOR_1_5_5_5:
1340 case V_028C70_COLOR_4_4_4_4:
1341 case V_028C70_COLOR_16:
1342 case V_028C70_COLOR_8_8:
1343 return V_028C70_ENDIAN_8IN16;
1344
1345 /* 32-bit buffers. */
1346 case V_028C70_COLOR_8_8_8_8:
1347 case V_028C70_COLOR_2_10_10_10:
1348 case V_028C70_COLOR_8_24:
1349 case V_028C70_COLOR_24_8:
1350 case V_028C70_COLOR_16_16:
1351 return V_028C70_ENDIAN_8IN32;
1352
1353 /* 64-bit buffers. */
1354 case V_028C70_COLOR_16_16_16_16:
1355 return V_028C70_ENDIAN_8IN16;
1356
1357 case V_028C70_COLOR_32_32:
1358 return V_028C70_ENDIAN_8IN32;
1359
1360 /* 128-bit buffers. */
1361 case V_028C70_COLOR_32_32_32_32:
1362 return V_028C70_ENDIAN_8IN32;
1363 default:
1364 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1365 }
1366 } else {
1367 return V_028C70_ENDIAN_NONE;
1368 }
1369 }
1370
1371 static uint32_t si_translate_dbformat(enum pipe_format format)
1372 {
1373 switch (format) {
1374 case PIPE_FORMAT_Z16_UNORM:
1375 return V_028040_Z_16;
1376 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1377 case PIPE_FORMAT_X8Z24_UNORM:
1378 case PIPE_FORMAT_Z24X8_UNORM:
1379 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1380 return V_028040_Z_24; /* deprecated on SI */
1381 case PIPE_FORMAT_Z32_FLOAT:
1382 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1383 return V_028040_Z_32_FLOAT;
1384 default:
1385 return V_028040_Z_INVALID;
1386 }
1387 }
1388
1389 /*
1390 * Texture translation
1391 */
1392
1393 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1394 enum pipe_format format,
1395 const struct util_format_description *desc,
1396 int first_non_void)
1397 {
1398 struct si_screen *sscreen = (struct si_screen*)screen;
1399 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1400 sscreen->b.info.drm_minor >= 31) ||
1401 sscreen->b.info.drm_major == 3;
1402 bool uniform = true;
1403 int i;
1404
1405 /* Colorspace (return non-RGB formats directly). */
1406 switch (desc->colorspace) {
1407 /* Depth stencil formats */
1408 case UTIL_FORMAT_COLORSPACE_ZS:
1409 switch (format) {
1410 case PIPE_FORMAT_Z16_UNORM:
1411 return V_008F14_IMG_DATA_FORMAT_16;
1412 case PIPE_FORMAT_X24S8_UINT:
1413 case PIPE_FORMAT_S8X24_UINT:
1414 /*
1415 * Implemented as an 8_8_8_8 data format to fix texture
1416 * gathers in stencil sampling. This affects at least
1417 * GL45-CTS.texture_cube_map_array.sampling on VI.
1418 */
1419 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1420 case PIPE_FORMAT_Z24X8_UNORM:
1421 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1422 return V_008F14_IMG_DATA_FORMAT_8_24;
1423 case PIPE_FORMAT_X8Z24_UNORM:
1424 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1425 return V_008F14_IMG_DATA_FORMAT_24_8;
1426 case PIPE_FORMAT_S8_UINT:
1427 return V_008F14_IMG_DATA_FORMAT_8;
1428 case PIPE_FORMAT_Z32_FLOAT:
1429 return V_008F14_IMG_DATA_FORMAT_32;
1430 case PIPE_FORMAT_X32_S8X24_UINT:
1431 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1432 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1433 default:
1434 goto out_unknown;
1435 }
1436
1437 case UTIL_FORMAT_COLORSPACE_YUV:
1438 goto out_unknown; /* TODO */
1439
1440 case UTIL_FORMAT_COLORSPACE_SRGB:
1441 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1442 goto out_unknown;
1443 break;
1444
1445 default:
1446 break;
1447 }
1448
1449 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1450 if (!enable_compressed_formats)
1451 goto out_unknown;
1452
1453 switch (format) {
1454 case PIPE_FORMAT_RGTC1_SNORM:
1455 case PIPE_FORMAT_LATC1_SNORM:
1456 case PIPE_FORMAT_RGTC1_UNORM:
1457 case PIPE_FORMAT_LATC1_UNORM:
1458 return V_008F14_IMG_DATA_FORMAT_BC4;
1459 case PIPE_FORMAT_RGTC2_SNORM:
1460 case PIPE_FORMAT_LATC2_SNORM:
1461 case PIPE_FORMAT_RGTC2_UNORM:
1462 case PIPE_FORMAT_LATC2_UNORM:
1463 return V_008F14_IMG_DATA_FORMAT_BC5;
1464 default:
1465 goto out_unknown;
1466 }
1467 }
1468
1469 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1470 (sscreen->b.family == CHIP_STONEY ||
1471 sscreen->b.chip_class >= GFX9)) {
1472 switch (format) {
1473 case PIPE_FORMAT_ETC1_RGB8:
1474 case PIPE_FORMAT_ETC2_RGB8:
1475 case PIPE_FORMAT_ETC2_SRGB8:
1476 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1477 case PIPE_FORMAT_ETC2_RGB8A1:
1478 case PIPE_FORMAT_ETC2_SRGB8A1:
1479 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1480 case PIPE_FORMAT_ETC2_RGBA8:
1481 case PIPE_FORMAT_ETC2_SRGBA8:
1482 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1483 case PIPE_FORMAT_ETC2_R11_UNORM:
1484 case PIPE_FORMAT_ETC2_R11_SNORM:
1485 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1486 case PIPE_FORMAT_ETC2_RG11_UNORM:
1487 case PIPE_FORMAT_ETC2_RG11_SNORM:
1488 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1489 default:
1490 goto out_unknown;
1491 }
1492 }
1493
1494 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1495 if (!enable_compressed_formats)
1496 goto out_unknown;
1497
1498 switch (format) {
1499 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1500 case PIPE_FORMAT_BPTC_SRGBA:
1501 return V_008F14_IMG_DATA_FORMAT_BC7;
1502 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1503 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1504 return V_008F14_IMG_DATA_FORMAT_BC6;
1505 default:
1506 goto out_unknown;
1507 }
1508 }
1509
1510 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1511 switch (format) {
1512 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1513 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1514 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1515 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1516 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1517 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1518 default:
1519 goto out_unknown;
1520 }
1521 }
1522
1523 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1524 if (!enable_compressed_formats)
1525 goto out_unknown;
1526
1527 if (!util_format_s3tc_enabled) {
1528 goto out_unknown;
1529 }
1530
1531 switch (format) {
1532 case PIPE_FORMAT_DXT1_RGB:
1533 case PIPE_FORMAT_DXT1_RGBA:
1534 case PIPE_FORMAT_DXT1_SRGB:
1535 case PIPE_FORMAT_DXT1_SRGBA:
1536 return V_008F14_IMG_DATA_FORMAT_BC1;
1537 case PIPE_FORMAT_DXT3_RGBA:
1538 case PIPE_FORMAT_DXT3_SRGBA:
1539 return V_008F14_IMG_DATA_FORMAT_BC2;
1540 case PIPE_FORMAT_DXT5_RGBA:
1541 case PIPE_FORMAT_DXT5_SRGBA:
1542 return V_008F14_IMG_DATA_FORMAT_BC3;
1543 default:
1544 goto out_unknown;
1545 }
1546 }
1547
1548 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1549 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1550 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1551 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1552 }
1553
1554 /* R8G8Bx_SNORM - TODO CxV8U8 */
1555
1556 /* hw cannot support mixed formats (except depth/stencil, since only
1557 * depth is read).*/
1558 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1559 goto out_unknown;
1560
1561 /* See whether the components are of the same size. */
1562 for (i = 1; i < desc->nr_channels; i++) {
1563 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1564 }
1565
1566 /* Non-uniform formats. */
1567 if (!uniform) {
1568 switch(desc->nr_channels) {
1569 case 3:
1570 if (desc->channel[0].size == 5 &&
1571 desc->channel[1].size == 6 &&
1572 desc->channel[2].size == 5) {
1573 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1574 }
1575 goto out_unknown;
1576 case 4:
1577 if (desc->channel[0].size == 5 &&
1578 desc->channel[1].size == 5 &&
1579 desc->channel[2].size == 5 &&
1580 desc->channel[3].size == 1) {
1581 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1582 }
1583 if (desc->channel[0].size == 10 &&
1584 desc->channel[1].size == 10 &&
1585 desc->channel[2].size == 10 &&
1586 desc->channel[3].size == 2) {
1587 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1588 }
1589 goto out_unknown;
1590 }
1591 goto out_unknown;
1592 }
1593
1594 if (first_non_void < 0 || first_non_void > 3)
1595 goto out_unknown;
1596
1597 /* uniform formats */
1598 switch (desc->channel[first_non_void].size) {
1599 case 4:
1600 switch (desc->nr_channels) {
1601 #if 0 /* Not supported for render targets */
1602 case 2:
1603 return V_008F14_IMG_DATA_FORMAT_4_4;
1604 #endif
1605 case 4:
1606 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1607 }
1608 break;
1609 case 8:
1610 switch (desc->nr_channels) {
1611 case 1:
1612 return V_008F14_IMG_DATA_FORMAT_8;
1613 case 2:
1614 return V_008F14_IMG_DATA_FORMAT_8_8;
1615 case 4:
1616 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1617 }
1618 break;
1619 case 16:
1620 switch (desc->nr_channels) {
1621 case 1:
1622 return V_008F14_IMG_DATA_FORMAT_16;
1623 case 2:
1624 return V_008F14_IMG_DATA_FORMAT_16_16;
1625 case 4:
1626 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1627 }
1628 break;
1629 case 32:
1630 switch (desc->nr_channels) {
1631 case 1:
1632 return V_008F14_IMG_DATA_FORMAT_32;
1633 case 2:
1634 return V_008F14_IMG_DATA_FORMAT_32_32;
1635 #if 0 /* Not supported for render targets */
1636 case 3:
1637 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1638 #endif
1639 case 4:
1640 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1641 }
1642 }
1643
1644 out_unknown:
1645 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1646 return ~0;
1647 }
1648
1649 static unsigned si_tex_wrap(unsigned wrap)
1650 {
1651 switch (wrap) {
1652 default:
1653 case PIPE_TEX_WRAP_REPEAT:
1654 return V_008F30_SQ_TEX_WRAP;
1655 case PIPE_TEX_WRAP_CLAMP:
1656 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1657 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1658 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1659 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1660 return V_008F30_SQ_TEX_CLAMP_BORDER;
1661 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1662 return V_008F30_SQ_TEX_MIRROR;
1663 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1664 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1665 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1666 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1667 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1668 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1669 }
1670 }
1671
1672 static unsigned si_tex_mipfilter(unsigned filter)
1673 {
1674 switch (filter) {
1675 case PIPE_TEX_MIPFILTER_NEAREST:
1676 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1677 case PIPE_TEX_MIPFILTER_LINEAR:
1678 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1679 default:
1680 case PIPE_TEX_MIPFILTER_NONE:
1681 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1682 }
1683 }
1684
1685 static unsigned si_tex_compare(unsigned compare)
1686 {
1687 switch (compare) {
1688 default:
1689 case PIPE_FUNC_NEVER:
1690 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1691 case PIPE_FUNC_LESS:
1692 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1693 case PIPE_FUNC_EQUAL:
1694 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1695 case PIPE_FUNC_LEQUAL:
1696 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1697 case PIPE_FUNC_GREATER:
1698 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1699 case PIPE_FUNC_NOTEQUAL:
1700 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1701 case PIPE_FUNC_GEQUAL:
1702 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1703 case PIPE_FUNC_ALWAYS:
1704 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1705 }
1706 }
1707
1708 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1709 unsigned view_target, unsigned nr_samples)
1710 {
1711 unsigned res_target = rtex->resource.b.b.target;
1712
1713 if (view_target == PIPE_TEXTURE_CUBE ||
1714 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1715 res_target = view_target;
1716 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1717 else if (res_target == PIPE_TEXTURE_CUBE ||
1718 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1719 res_target = PIPE_TEXTURE_2D_ARRAY;
1720
1721 /* GFX9 allocates 1D textures as 2D. */
1722 if ((res_target == PIPE_TEXTURE_1D ||
1723 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1724 sscreen->b.chip_class >= GFX9 &&
1725 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1726 if (res_target == PIPE_TEXTURE_1D)
1727 res_target = PIPE_TEXTURE_2D;
1728 else
1729 res_target = PIPE_TEXTURE_2D_ARRAY;
1730 }
1731
1732 switch (res_target) {
1733 default:
1734 case PIPE_TEXTURE_1D:
1735 return V_008F1C_SQ_RSRC_IMG_1D;
1736 case PIPE_TEXTURE_1D_ARRAY:
1737 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1738 case PIPE_TEXTURE_2D:
1739 case PIPE_TEXTURE_RECT:
1740 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1741 V_008F1C_SQ_RSRC_IMG_2D;
1742 case PIPE_TEXTURE_2D_ARRAY:
1743 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1744 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1745 case PIPE_TEXTURE_3D:
1746 return V_008F1C_SQ_RSRC_IMG_3D;
1747 case PIPE_TEXTURE_CUBE:
1748 case PIPE_TEXTURE_CUBE_ARRAY:
1749 return V_008F1C_SQ_RSRC_IMG_CUBE;
1750 }
1751 }
1752
1753 /*
1754 * Format support testing
1755 */
1756
1757 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1758 {
1759 return si_translate_texformat(screen, format, util_format_description(format),
1760 util_format_get_first_non_void_channel(format)) != ~0U;
1761 }
1762
1763 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1764 const struct util_format_description *desc,
1765 int first_non_void)
1766 {
1767 int i;
1768
1769 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1770 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1771
1772 assert(first_non_void >= 0);
1773
1774 if (desc->nr_channels == 4 &&
1775 desc->channel[0].size == 10 &&
1776 desc->channel[1].size == 10 &&
1777 desc->channel[2].size == 10 &&
1778 desc->channel[3].size == 2)
1779 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1780
1781 /* See whether the components are of the same size. */
1782 for (i = 0; i < desc->nr_channels; i++) {
1783 if (desc->channel[first_non_void].size != desc->channel[i].size)
1784 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1785 }
1786
1787 switch (desc->channel[first_non_void].size) {
1788 case 8:
1789 switch (desc->nr_channels) {
1790 case 1:
1791 case 3: /* 3 loads */
1792 return V_008F0C_BUF_DATA_FORMAT_8;
1793 case 2:
1794 return V_008F0C_BUF_DATA_FORMAT_8_8;
1795 case 4:
1796 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1797 }
1798 break;
1799 case 16:
1800 switch (desc->nr_channels) {
1801 case 1:
1802 case 3: /* 3 loads */
1803 return V_008F0C_BUF_DATA_FORMAT_16;
1804 case 2:
1805 return V_008F0C_BUF_DATA_FORMAT_16_16;
1806 case 4:
1807 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1808 }
1809 break;
1810 case 32:
1811 switch (desc->nr_channels) {
1812 case 1:
1813 return V_008F0C_BUF_DATA_FORMAT_32;
1814 case 2:
1815 return V_008F0C_BUF_DATA_FORMAT_32_32;
1816 case 3:
1817 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1818 case 4:
1819 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1820 }
1821 break;
1822 case 64:
1823 /* Legacy double formats. */
1824 switch (desc->nr_channels) {
1825 case 1: /* 1 load */
1826 return V_008F0C_BUF_DATA_FORMAT_32_32;
1827 case 2: /* 1 load */
1828 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1829 case 3: /* 3 loads */
1830 return V_008F0C_BUF_DATA_FORMAT_32_32;
1831 case 4: /* 2 loads */
1832 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1833 }
1834 break;
1835 }
1836
1837 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1838 }
1839
1840 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1841 const struct util_format_description *desc,
1842 int first_non_void)
1843 {
1844 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1845 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1846
1847 assert(first_non_void >= 0);
1848
1849 switch (desc->channel[first_non_void].type) {
1850 case UTIL_FORMAT_TYPE_SIGNED:
1851 case UTIL_FORMAT_TYPE_FIXED:
1852 if (desc->channel[first_non_void].size >= 32 ||
1853 desc->channel[first_non_void].pure_integer)
1854 return V_008F0C_BUF_NUM_FORMAT_SINT;
1855 else if (desc->channel[first_non_void].normalized)
1856 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1857 else
1858 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1859 break;
1860 case UTIL_FORMAT_TYPE_UNSIGNED:
1861 if (desc->channel[first_non_void].size >= 32 ||
1862 desc->channel[first_non_void].pure_integer)
1863 return V_008F0C_BUF_NUM_FORMAT_UINT;
1864 else if (desc->channel[first_non_void].normalized)
1865 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1866 else
1867 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1868 break;
1869 case UTIL_FORMAT_TYPE_FLOAT:
1870 default:
1871 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1872 }
1873 }
1874
1875 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1876 enum pipe_format format,
1877 unsigned usage)
1878 {
1879 const struct util_format_description *desc;
1880 int first_non_void;
1881 unsigned data_format;
1882
1883 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1884 PIPE_BIND_SAMPLER_VIEW |
1885 PIPE_BIND_VERTEX_BUFFER)) == 0);
1886
1887 desc = util_format_description(format);
1888
1889 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1890 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1891 * for read-only access (with caveats surrounding bounds checks), but
1892 * obviously fails for write access which we have to implement for
1893 * shader images. Luckily, OpenGL doesn't expect this to be supported
1894 * anyway, and so the only impact is on PBO uploads / downloads, which
1895 * shouldn't be expected to be fast for GL_RGB anyway.
1896 */
1897 if (desc->block.bits == 3 * 8 ||
1898 desc->block.bits == 3 * 16) {
1899 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1900 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1901 if (!usage)
1902 return 0;
1903 }
1904 }
1905
1906 first_non_void = util_format_get_first_non_void_channel(format);
1907 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1908 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1909 return 0;
1910
1911 return usage;
1912 }
1913
1914 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1915 {
1916 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1917 r600_translate_colorswap(format, false) != ~0U;
1918 }
1919
1920 static bool si_is_zs_format_supported(enum pipe_format format)
1921 {
1922 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1923 }
1924
1925 static boolean si_is_format_supported(struct pipe_screen *screen,
1926 enum pipe_format format,
1927 enum pipe_texture_target target,
1928 unsigned sample_count,
1929 unsigned usage)
1930 {
1931 unsigned retval = 0;
1932
1933 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1934 R600_ERR("r600: unsupported texture type %d\n", target);
1935 return false;
1936 }
1937
1938 if (!util_format_is_supported(format, usage))
1939 return false;
1940
1941 if (sample_count > 1) {
1942 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1943 return false;
1944
1945 if (usage & PIPE_BIND_SHADER_IMAGE)
1946 return false;
1947
1948 switch (sample_count) {
1949 case 2:
1950 case 4:
1951 case 8:
1952 break;
1953 case 16:
1954 if (format == PIPE_FORMAT_NONE)
1955 return true;
1956 else
1957 return false;
1958 default:
1959 return false;
1960 }
1961 }
1962
1963 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1964 PIPE_BIND_SHADER_IMAGE)) {
1965 if (target == PIPE_BUFFER) {
1966 retval |= si_is_vertex_format_supported(
1967 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1968 PIPE_BIND_SHADER_IMAGE));
1969 } else {
1970 if (si_is_sampler_format_supported(screen, format))
1971 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1972 PIPE_BIND_SHADER_IMAGE);
1973 }
1974 }
1975
1976 if ((usage & (PIPE_BIND_RENDER_TARGET |
1977 PIPE_BIND_DISPLAY_TARGET |
1978 PIPE_BIND_SCANOUT |
1979 PIPE_BIND_SHARED |
1980 PIPE_BIND_BLENDABLE)) &&
1981 si_is_colorbuffer_format_supported(format)) {
1982 retval |= usage &
1983 (PIPE_BIND_RENDER_TARGET |
1984 PIPE_BIND_DISPLAY_TARGET |
1985 PIPE_BIND_SCANOUT |
1986 PIPE_BIND_SHARED);
1987 if (!util_format_is_pure_integer(format) &&
1988 !util_format_is_depth_or_stencil(format))
1989 retval |= usage & PIPE_BIND_BLENDABLE;
1990 }
1991
1992 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1993 si_is_zs_format_supported(format)) {
1994 retval |= PIPE_BIND_DEPTH_STENCIL;
1995 }
1996
1997 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1998 retval |= si_is_vertex_format_supported(screen, format,
1999 PIPE_BIND_VERTEX_BUFFER);
2000 }
2001
2002 if ((usage & PIPE_BIND_LINEAR) &&
2003 !util_format_is_compressed(format) &&
2004 !(usage & PIPE_BIND_DEPTH_STENCIL))
2005 retval |= PIPE_BIND_LINEAR;
2006
2007 return retval == usage;
2008 }
2009
2010 /*
2011 * framebuffer handling
2012 */
2013
2014 static void si_choose_spi_color_formats(struct r600_surface *surf,
2015 unsigned format, unsigned swap,
2016 unsigned ntype, bool is_depth)
2017 {
2018 /* Alpha is needed for alpha-to-coverage.
2019 * Blending may be with or without alpha.
2020 */
2021 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2022 unsigned alpha = 0; /* exports alpha, but may not support blending */
2023 unsigned blend = 0; /* supports blending, but may not export alpha */
2024 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2025
2026 /* Choose the SPI color formats. These are required values for RB+.
2027 * Other chips have multiple choices, though they are not necessarily better.
2028 */
2029 switch (format) {
2030 case V_028C70_COLOR_5_6_5:
2031 case V_028C70_COLOR_1_5_5_5:
2032 case V_028C70_COLOR_5_5_5_1:
2033 case V_028C70_COLOR_4_4_4_4:
2034 case V_028C70_COLOR_10_11_11:
2035 case V_028C70_COLOR_11_11_10:
2036 case V_028C70_COLOR_8:
2037 case V_028C70_COLOR_8_8:
2038 case V_028C70_COLOR_8_8_8_8:
2039 case V_028C70_COLOR_10_10_10_2:
2040 case V_028C70_COLOR_2_10_10_10:
2041 if (ntype == V_028C70_NUMBER_UINT)
2042 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2043 else if (ntype == V_028C70_NUMBER_SINT)
2044 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2045 else
2046 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2047 break;
2048
2049 case V_028C70_COLOR_16:
2050 case V_028C70_COLOR_16_16:
2051 case V_028C70_COLOR_16_16_16_16:
2052 if (ntype == V_028C70_NUMBER_UNORM ||
2053 ntype == V_028C70_NUMBER_SNORM) {
2054 /* UNORM16 and SNORM16 don't support blending */
2055 if (ntype == V_028C70_NUMBER_UNORM)
2056 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2057 else
2058 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2059
2060 /* Use 32 bits per channel for blending. */
2061 if (format == V_028C70_COLOR_16) {
2062 if (swap == V_028C70_SWAP_STD) { /* R */
2063 blend = V_028714_SPI_SHADER_32_R;
2064 blend_alpha = V_028714_SPI_SHADER_32_AR;
2065 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2066 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2067 else
2068 assert(0);
2069 } else if (format == V_028C70_COLOR_16_16) {
2070 if (swap == V_028C70_SWAP_STD) { /* RG */
2071 blend = V_028714_SPI_SHADER_32_GR;
2072 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2073 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2074 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2075 else
2076 assert(0);
2077 } else /* 16_16_16_16 */
2078 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2079 } else if (ntype == V_028C70_NUMBER_UINT)
2080 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2081 else if (ntype == V_028C70_NUMBER_SINT)
2082 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2083 else if (ntype == V_028C70_NUMBER_FLOAT)
2084 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2085 else
2086 assert(0);
2087 break;
2088
2089 case V_028C70_COLOR_32:
2090 if (swap == V_028C70_SWAP_STD) { /* R */
2091 blend = normal = V_028714_SPI_SHADER_32_R;
2092 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2093 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2094 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2095 else
2096 assert(0);
2097 break;
2098
2099 case V_028C70_COLOR_32_32:
2100 if (swap == V_028C70_SWAP_STD) { /* RG */
2101 blend = normal = V_028714_SPI_SHADER_32_GR;
2102 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2103 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2104 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2105 else
2106 assert(0);
2107 break;
2108
2109 case V_028C70_COLOR_32_32_32_32:
2110 case V_028C70_COLOR_8_24:
2111 case V_028C70_COLOR_24_8:
2112 case V_028C70_COLOR_X24_8_32_FLOAT:
2113 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2114 break;
2115
2116 default:
2117 assert(0);
2118 return;
2119 }
2120
2121 /* The DB->CB copy needs 32_ABGR. */
2122 if (is_depth)
2123 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2124
2125 surf->spi_shader_col_format = normal;
2126 surf->spi_shader_col_format_alpha = alpha;
2127 surf->spi_shader_col_format_blend = blend;
2128 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2129 }
2130
2131 static void si_initialize_color_surface(struct si_context *sctx,
2132 struct r600_surface *surf)
2133 {
2134 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2135 unsigned color_info, color_attrib, color_view;
2136 unsigned format, swap, ntype, endian;
2137 const struct util_format_description *desc;
2138 int i;
2139 unsigned blend_clamp = 0, blend_bypass = 0;
2140
2141 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2142 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2143
2144 desc = util_format_description(surf->base.format);
2145 for (i = 0; i < 4; i++) {
2146 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2147 break;
2148 }
2149 }
2150 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2151 ntype = V_028C70_NUMBER_FLOAT;
2152 } else {
2153 ntype = V_028C70_NUMBER_UNORM;
2154 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2155 ntype = V_028C70_NUMBER_SRGB;
2156 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2157 if (desc->channel[i].pure_integer) {
2158 ntype = V_028C70_NUMBER_SINT;
2159 } else {
2160 assert(desc->channel[i].normalized);
2161 ntype = V_028C70_NUMBER_SNORM;
2162 }
2163 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2164 if (desc->channel[i].pure_integer) {
2165 ntype = V_028C70_NUMBER_UINT;
2166 } else {
2167 assert(desc->channel[i].normalized);
2168 ntype = V_028C70_NUMBER_UNORM;
2169 }
2170 }
2171 }
2172
2173 format = si_translate_colorformat(surf->base.format);
2174 if (format == V_028C70_COLOR_INVALID) {
2175 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2176 }
2177 assert(format != V_028C70_COLOR_INVALID);
2178 swap = r600_translate_colorswap(surf->base.format, false);
2179 endian = si_colorformat_endian_swap(format);
2180
2181 /* blend clamp should be set for all NORM/SRGB types */
2182 if (ntype == V_028C70_NUMBER_UNORM ||
2183 ntype == V_028C70_NUMBER_SNORM ||
2184 ntype == V_028C70_NUMBER_SRGB)
2185 blend_clamp = 1;
2186
2187 /* set blend bypass according to docs if SINT/UINT or
2188 8/24 COLOR variants */
2189 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2190 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2191 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2192 blend_clamp = 0;
2193 blend_bypass = 1;
2194 }
2195
2196 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2197 if (format == V_028C70_COLOR_8 ||
2198 format == V_028C70_COLOR_8_8 ||
2199 format == V_028C70_COLOR_8_8_8_8)
2200 surf->color_is_int8 = true;
2201 else if (format == V_028C70_COLOR_10_10_10_2 ||
2202 format == V_028C70_COLOR_2_10_10_10)
2203 surf->color_is_int10 = true;
2204 }
2205
2206 color_info = S_028C70_FORMAT(format) |
2207 S_028C70_COMP_SWAP(swap) |
2208 S_028C70_BLEND_CLAMP(blend_clamp) |
2209 S_028C70_BLEND_BYPASS(blend_bypass) |
2210 S_028C70_SIMPLE_FLOAT(1) |
2211 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2212 ntype != V_028C70_NUMBER_SNORM &&
2213 ntype != V_028C70_NUMBER_SRGB &&
2214 format != V_028C70_COLOR_8_24 &&
2215 format != V_028C70_COLOR_24_8) |
2216 S_028C70_NUMBER_TYPE(ntype) |
2217 S_028C70_ENDIAN(endian);
2218
2219 /* Intensity is implemented as Red, so treat it that way. */
2220 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2221 util_format_is_intensity(surf->base.format));
2222
2223 if (rtex->resource.b.b.nr_samples > 1) {
2224 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2225
2226 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2227 S_028C74_NUM_FRAGMENTS(log_samples);
2228
2229 if (rtex->fmask.size) {
2230 color_info |= S_028C70_COMPRESSION(1);
2231 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2232
2233 if (sctx->b.chip_class == SI) {
2234 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2235 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2236 }
2237 }
2238 }
2239
2240 surf->cb_color_view = color_view;
2241 surf->cb_color_info = color_info;
2242 surf->cb_color_attrib = color_attrib;
2243
2244 if (sctx->b.chip_class >= VI) {
2245 unsigned max_uncompressed_block_size = 2;
2246
2247 if (rtex->resource.b.b.nr_samples > 1) {
2248 if (rtex->surface.bpe == 1)
2249 max_uncompressed_block_size = 0;
2250 else if (rtex->surface.bpe == 2)
2251 max_uncompressed_block_size = 1;
2252 }
2253
2254 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2255 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2256 }
2257
2258 /* This must be set for fast clear to work without FMASK. */
2259 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2260 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2261 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2262 }
2263
2264 if (sctx->b.chip_class >= GFX9) {
2265 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2266
2267 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2268 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2269 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2270 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2271 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2272 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2273 }
2274
2275 /* Determine pixel shader export format */
2276 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2277
2278 surf->color_initialized = true;
2279 }
2280
2281 static void si_init_depth_surface(struct si_context *sctx,
2282 struct r600_surface *surf)
2283 {
2284 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2285 unsigned level = surf->base.u.tex.level;
2286 unsigned format, stencil_format;
2287 uint32_t z_info, s_info;
2288
2289 format = si_translate_dbformat(rtex->db_render_format);
2290 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2291 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2292
2293 assert(format != V_028040_Z_INVALID);
2294 if (format == V_028040_Z_INVALID)
2295 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2296
2297 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2298 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2299 surf->db_htile_data_base = 0;
2300 surf->db_htile_surface = 0;
2301
2302 if (sctx->b.chip_class >= GFX9) {
2303 assert(rtex->surface.u.gfx9.surf_offset == 0);
2304 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2305 surf->db_stencil_base = (rtex->resource.gpu_address +
2306 rtex->surface.u.gfx9.stencil_offset) >> 8;
2307 z_info = S_028038_FORMAT(format) |
2308 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2309 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2310 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2311 s_info = S_02803C_FORMAT(stencil_format) |
2312 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2313 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2314 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2315 surf->db_depth_view |= S_028008_MIPID(level);
2316 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2317 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2318
2319 /* Only use HTILE for the first level. */
2320 if (rtex->htile_offset && !level) {
2321 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2322 S_028038_ALLOW_EXPCLEAR(1);
2323
2324 if (rtex->tc_compatible_htile) {
2325 unsigned max_zplanes = 4;
2326
2327 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2328 rtex->resource.b.b.nr_samples > 1)
2329 max_zplanes = 2;
2330
2331 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2332 S_028038_ITERATE_FLUSH(1);
2333 s_info |= S_02803C_ITERATE_FLUSH(1);
2334 }
2335
2336 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2337 /* Stencil buffer workaround ported from the SI-CI-VI code.
2338 * See that for explanation.
2339 */
2340 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2341 } else {
2342 /* Use all HTILE for depth if there's no stencil. */
2343 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2344 }
2345
2346 surf->db_htile_data_base = (rtex->resource.gpu_address +
2347 rtex->htile_offset) >> 8;
2348 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2349 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2350 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2351 }
2352 } else {
2353 /* SI-CI-VI */
2354 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2355
2356 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2357
2358 surf->db_depth_base = (rtex->resource.gpu_address +
2359 rtex->surface.u.legacy.level[level].offset) >> 8;
2360 surf->db_stencil_base = (rtex->resource.gpu_address +
2361 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2362
2363 z_info = S_028040_FORMAT(format) |
2364 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2365 s_info = S_028044_FORMAT(stencil_format);
2366 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2367
2368 if (sctx->b.chip_class >= CIK) {
2369 struct radeon_info *info = &sctx->screen->b.info;
2370 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2371 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2372 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2373 unsigned tile_mode = info->si_tile_mode_array[index];
2374 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2375 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2376
2377 surf->db_depth_info |=
2378 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2379 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2380 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2381 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2382 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2383 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2384 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2385 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2386 } else {
2387 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2388 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2389 tile_mode_index = si_tile_mode_index(rtex, level, true);
2390 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2391 }
2392
2393 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2394 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2395 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2396 levelinfo->nblk_y) / 64 - 1);
2397
2398 /* Only use HTILE for the first level. */
2399 if (rtex->htile_offset && !level) {
2400 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2401 S_028040_ALLOW_EXPCLEAR(1);
2402
2403 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2404 /* Workaround: For a not yet understood reason, the
2405 * combination of MSAA, fast stencil clear and stencil
2406 * decompress messes with subsequent stencil buffer
2407 * uses. Problem was reproduced on Verde, Bonaire,
2408 * Tonga, and Carrizo.
2409 *
2410 * Disabling EXPCLEAR works around the problem.
2411 *
2412 * Check piglit's arb_texture_multisample-stencil-clear
2413 * test if you want to try changing this.
2414 */
2415 if (rtex->resource.b.b.nr_samples <= 1)
2416 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2417 } else if (!rtex->tc_compatible_htile) {
2418 /* Use all of the htile_buffer for depth if there's no stencil.
2419 * This must not be set when TC-compatible HTILE is enabled
2420 * due to a hw bug.
2421 */
2422 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2423 }
2424
2425 surf->db_htile_data_base = (rtex->resource.gpu_address +
2426 rtex->htile_offset) >> 8;
2427 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2428
2429 if (rtex->tc_compatible_htile) {
2430 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2431
2432 if (rtex->resource.b.b.nr_samples <= 1)
2433 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2434 else if (rtex->resource.b.b.nr_samples <= 4)
2435 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2436 else
2437 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2438 }
2439 }
2440 }
2441
2442 surf->db_z_info = z_info;
2443 surf->db_stencil_info = s_info;
2444
2445 surf->depth_initialized = true;
2446 }
2447
2448 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2449 {
2450 for (int i = 0; i < state->nr_cbufs; ++i) {
2451 struct r600_surface *surf = NULL;
2452 struct r600_texture *rtex;
2453
2454 if (!state->cbufs[i])
2455 continue;
2456 surf = (struct r600_surface*)state->cbufs[i];
2457 rtex = (struct r600_texture*)surf->base.texture;
2458
2459 p_atomic_dec(&rtex->framebuffers_bound);
2460 }
2461 }
2462
2463 static void si_set_framebuffer_state(struct pipe_context *ctx,
2464 const struct pipe_framebuffer_state *state)
2465 {
2466 struct si_context *sctx = (struct si_context *)ctx;
2467 struct pipe_constant_buffer constbuf = {0};
2468 struct r600_surface *surf = NULL;
2469 struct r600_texture *rtex;
2470 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2471 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2472 bool unbound = false;
2473 int i;
2474
2475 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2476 if (!sctx->framebuffer.state.cbufs[i])
2477 continue;
2478
2479 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2480 if (rtex->dcc_gather_statistics)
2481 vi_separate_dcc_stop_query(ctx, rtex);
2482 }
2483
2484 /* Disable DCC if the formats are incompatible. */
2485 for (i = 0; i < state->nr_cbufs; i++) {
2486 if (!state->cbufs[i])
2487 continue;
2488
2489 surf = (struct r600_surface*)state->cbufs[i];
2490 rtex = (struct r600_texture*)surf->base.texture;
2491
2492 if (!surf->dcc_incompatible)
2493 continue;
2494
2495 /* Since the DCC decompression calls back into set_framebuffer-
2496 * _state, we need to unbind the framebuffer, so that
2497 * vi_separate_dcc_stop_query isn't called twice with the same
2498 * color buffer.
2499 */
2500 if (!unbound) {
2501 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2502 unbound = true;
2503 }
2504
2505 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2506 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2507 sctx->b.decompress_dcc(ctx, rtex);
2508
2509 surf->dcc_incompatible = false;
2510 }
2511
2512 /* Only flush TC when changing the framebuffer state, because
2513 * the only client not using TC that can change textures is
2514 * the framebuffer.
2515 *
2516 * Flush all CB and DB caches here because all buffers can be used
2517 * for write by both TC (with shader image stores) and CB/DB.
2518 */
2519 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2520 SI_CONTEXT_INV_GLOBAL_L2 |
2521 SI_CONTEXT_FLUSH_AND_INV_CB |
2522 SI_CONTEXT_FLUSH_AND_INV_DB |
2523 SI_CONTEXT_CS_PARTIAL_FLUSH;
2524
2525 /* Take the maximum of the old and new count. If the new count is lower,
2526 * dirtying is needed to disable the unbound colorbuffers.
2527 */
2528 sctx->framebuffer.dirty_cbufs |=
2529 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2530 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2531
2532 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2533 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2534
2535 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2536 sctx->framebuffer.spi_shader_col_format = 0;
2537 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2538 sctx->framebuffer.spi_shader_col_format_blend = 0;
2539 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2540 sctx->framebuffer.color_is_int8 = 0;
2541 sctx->framebuffer.color_is_int10 = 0;
2542
2543 sctx->framebuffer.compressed_cb_mask = 0;
2544 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2545 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2546 sctx->framebuffer.any_dst_linear = false;
2547
2548 for (i = 0; i < state->nr_cbufs; i++) {
2549 if (!state->cbufs[i])
2550 continue;
2551
2552 surf = (struct r600_surface*)state->cbufs[i];
2553 rtex = (struct r600_texture*)surf->base.texture;
2554
2555 if (!surf->color_initialized) {
2556 si_initialize_color_surface(sctx, surf);
2557 }
2558
2559 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2560 sctx->framebuffer.spi_shader_col_format |=
2561 surf->spi_shader_col_format << (i * 4);
2562 sctx->framebuffer.spi_shader_col_format_alpha |=
2563 surf->spi_shader_col_format_alpha << (i * 4);
2564 sctx->framebuffer.spi_shader_col_format_blend |=
2565 surf->spi_shader_col_format_blend << (i * 4);
2566 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2567 surf->spi_shader_col_format_blend_alpha << (i * 4);
2568
2569 if (surf->color_is_int8)
2570 sctx->framebuffer.color_is_int8 |= 1 << i;
2571 if (surf->color_is_int10)
2572 sctx->framebuffer.color_is_int10 |= 1 << i;
2573
2574 if (rtex->fmask.size) {
2575 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2576 }
2577
2578 if (rtex->surface.is_linear)
2579 sctx->framebuffer.any_dst_linear = true;
2580
2581 r600_context_add_resource_size(ctx, surf->base.texture);
2582
2583 p_atomic_inc(&rtex->framebuffers_bound);
2584
2585 if (rtex->dcc_gather_statistics) {
2586 /* Dirty tracking must be enabled for DCC usage analysis. */
2587 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2588 vi_separate_dcc_start_query(ctx, rtex);
2589 }
2590 }
2591
2592 if (state->zsbuf) {
2593 surf = (struct r600_surface*)state->zsbuf;
2594 rtex = (struct r600_texture*)surf->base.texture;
2595
2596 if (!surf->depth_initialized) {
2597 si_init_depth_surface(sctx, surf);
2598 }
2599 r600_context_add_resource_size(ctx, surf->base.texture);
2600 }
2601
2602 si_update_poly_offset_state(sctx);
2603 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2604 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2605
2606 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2607 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2608
2609 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2610 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2611 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2612
2613 /* Set sample locations as fragment shader constants. */
2614 switch (sctx->framebuffer.nr_samples) {
2615 case 1:
2616 constbuf.user_buffer = sctx->b.sample_locations_1x;
2617 break;
2618 case 2:
2619 constbuf.user_buffer = sctx->b.sample_locations_2x;
2620 break;
2621 case 4:
2622 constbuf.user_buffer = sctx->b.sample_locations_4x;
2623 break;
2624 case 8:
2625 constbuf.user_buffer = sctx->b.sample_locations_8x;
2626 break;
2627 case 16:
2628 constbuf.user_buffer = sctx->b.sample_locations_16x;
2629 break;
2630 default:
2631 R600_ERR("Requested an invalid number of samples %i.\n",
2632 sctx->framebuffer.nr_samples);
2633 assert(0);
2634 }
2635 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2636 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2637
2638 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2639 }
2640
2641 sctx->do_update_shaders = true;
2642
2643 if (!sctx->decompression_enabled) {
2644 /* Prevent textures decompression when the framebuffer state
2645 * changes come from the decompression passes themselves.
2646 */
2647 sctx->need_check_render_feedback = true;
2648 sctx->framebuffer.do_update_surf_dirtiness = true;
2649 }
2650 }
2651
2652 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2653 {
2654 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2655 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2656 unsigned i, nr_cbufs = state->nr_cbufs;
2657 struct r600_texture *tex = NULL;
2658 struct r600_surface *cb = NULL;
2659 unsigned cb_color_info = 0;
2660
2661 /* Colorbuffers. */
2662 for (i = 0; i < nr_cbufs; i++) {
2663 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2664 unsigned cb_color_attrib;
2665
2666 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2667 continue;
2668
2669 cb = (struct r600_surface*)state->cbufs[i];
2670 if (!cb) {
2671 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2672 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2673 continue;
2674 }
2675
2676 tex = (struct r600_texture *)cb->base.texture;
2677 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2678 &tex->resource, RADEON_USAGE_READWRITE,
2679 tex->resource.b.b.nr_samples > 1 ?
2680 RADEON_PRIO_COLOR_BUFFER_MSAA :
2681 RADEON_PRIO_COLOR_BUFFER);
2682
2683 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2684 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2685 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2686 RADEON_PRIO_CMASK);
2687 }
2688
2689 if (tex->dcc_separate_buffer)
2690 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2691 tex->dcc_separate_buffer,
2692 RADEON_USAGE_READWRITE,
2693 RADEON_PRIO_DCC);
2694
2695 /* Compute mutable surface parameters. */
2696 cb_color_base = tex->resource.gpu_address >> 8;
2697 cb_color_fmask = cb_color_base;
2698 cb_dcc_base = 0;
2699 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2700 cb_color_attrib = cb->cb_color_attrib;
2701
2702 if (tex->fmask.size)
2703 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2704
2705 /* Set up DCC. */
2706 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2707 bool is_msaa_resolve_dst = state->cbufs[0] &&
2708 state->cbufs[0]->texture->nr_samples > 1 &&
2709 state->cbufs[1] == &cb->base &&
2710 state->cbufs[1]->texture->nr_samples <= 1;
2711
2712 if (!is_msaa_resolve_dst)
2713 cb_color_info |= S_028C70_DCC_ENABLE(1);
2714
2715 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2716 tex->dcc_offset) >> 8;
2717 }
2718
2719 if (sctx->b.chip_class >= GFX9) {
2720 struct gfx9_surf_meta_flags meta;
2721
2722 if (tex->dcc_offset)
2723 meta = tex->surface.u.gfx9.dcc;
2724 else
2725 meta = tex->surface.u.gfx9.cmask;
2726
2727 /* Set mutable surface parameters. */
2728 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2729 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2730 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2731 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2732 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2733
2734 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2735 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2736 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2737 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2738 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2739 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2740 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2741 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2742 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2743 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2744 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2745 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2746 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2747 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2748 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2749 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2750
2751 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2752 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2753 } else {
2754 /* Compute mutable surface parameters (SI-CI-VI). */
2755 const struct legacy_surf_level *level_info =
2756 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2757 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2758 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2759
2760 cb_color_base += level_info->offset >> 8;
2761 if (cb_dcc_base)
2762 cb_dcc_base += level_info->dcc_offset >> 8;
2763
2764 pitch_tile_max = level_info->nblk_x / 8 - 1;
2765 slice_tile_max = level_info->nblk_x *
2766 level_info->nblk_y / 64 - 1;
2767 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2768
2769 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2770 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2771 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2772
2773 if (tex->fmask.size) {
2774 if (sctx->b.chip_class >= CIK)
2775 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2776 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2777 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2778 } else {
2779 /* This must be set for fast clear to work without FMASK. */
2780 if (sctx->b.chip_class >= CIK)
2781 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2782 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2783 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2784 }
2785
2786 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2787 sctx->b.chip_class >= VI ? 14 : 13);
2788 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2789 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2790 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2791 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2792 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2793 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2794 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2795 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2796 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2797 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2798 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2799 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2800 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2801
2802 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2803 radeon_emit(cs, cb_dcc_base);
2804 }
2805 }
2806 for (; i < 8 ; i++)
2807 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2808 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2809
2810 /* ZS buffer. */
2811 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2812 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2813 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2814
2815 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2816 &rtex->resource, RADEON_USAGE_READWRITE,
2817 zb->base.texture->nr_samples > 1 ?
2818 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2819 RADEON_PRIO_DEPTH_BUFFER);
2820
2821 if (sctx->b.chip_class >= GFX9) {
2822 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2823 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2824 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2825 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2826
2827 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2828 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2829 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2830 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2831 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2832 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2833 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2834 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2835 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2836 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2837 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2838 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2839
2840 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2841 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2842 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2843 } else {
2844 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2845
2846 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2847 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2848 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2849 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2850 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2851 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2852 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2853 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2854 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2855 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2856 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2857 }
2858
2859 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2860 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2861 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2862
2863 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2864 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2865 } else if (sctx->framebuffer.dirty_zsbuf) {
2866 if (sctx->b.chip_class >= GFX9)
2867 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2868 else
2869 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2870
2871 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2872 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2873 }
2874
2875 /* Framebuffer dimensions. */
2876 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2877 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2878 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2879
2880 if (sctx->b.chip_class >= GFX9) {
2881 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2882 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2883 }
2884
2885 sctx->framebuffer.dirty_cbufs = 0;
2886 sctx->framebuffer.dirty_zsbuf = false;
2887 }
2888
2889 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2890 struct r600_atom *atom)
2891 {
2892 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2893 unsigned nr_samples = sctx->framebuffer.nr_samples;
2894 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2895
2896 /* Smoothing (only possible with nr_samples == 1) uses the same
2897 * sample locations as the MSAA it simulates.
2898 */
2899 if (nr_samples <= 1 && sctx->smoothing_enabled)
2900 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2901
2902 /* On Polaris, the small primitive filter uses the sample locations
2903 * even when MSAA is off, so we need to make sure they're set to 0.
2904 */
2905 if (has_msaa_sample_loc_bug)
2906 nr_samples = MAX2(nr_samples, 1);
2907
2908 if (nr_samples >= 1 &&
2909 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2910 sctx->msaa_sample_locs.nr_samples = nr_samples;
2911 cayman_emit_msaa_sample_locs(cs, nr_samples);
2912 }
2913
2914 if (sctx->b.family >= CHIP_POLARIS10) {
2915 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2916 unsigned small_prim_filter_cntl =
2917 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2918 /* line bug */
2919 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2920
2921 /* The alternative of setting sample locations to 0 would
2922 * require a DB flush to avoid Z errors, see
2923 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2924 */
2925 if (has_msaa_sample_loc_bug &&
2926 sctx->framebuffer.nr_samples > 1 &&
2927 rs && !rs->multisample_enable)
2928 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2929
2930 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2931 small_prim_filter_cntl);
2932 }
2933 }
2934
2935 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2936 {
2937 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2938 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2939 /* 33% faster rendering to linear color buffers */
2940 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2941 unsigned sc_mode_cntl_1 =
2942 S_028A4C_WALK_SIZE(dst_is_linear) |
2943 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2944 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2945 /* always 1: */
2946 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2947 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2948 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2949 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2950 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2951 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2952
2953 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2954 sctx->ps_iter_samples,
2955 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2956 sc_mode_cntl_1);
2957
2958 /* GFX9: Flush DFSM when the AA mode changes. */
2959 if (sctx->b.chip_class >= GFX9) {
2960 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2961 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2962 }
2963 }
2964
2965 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2966 {
2967 struct si_context *sctx = (struct si_context *)ctx;
2968
2969 if (sctx->ps_iter_samples == min_samples)
2970 return;
2971
2972 sctx->ps_iter_samples = min_samples;
2973 sctx->do_update_shaders = true;
2974
2975 if (sctx->framebuffer.nr_samples > 1)
2976 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2977 }
2978
2979 /*
2980 * Samplers
2981 */
2982
2983 /**
2984 * Build the sampler view descriptor for a buffer texture.
2985 * @param state 256-bit descriptor; only the high 128 bits are filled in
2986 */
2987 void
2988 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2989 enum pipe_format format,
2990 unsigned offset, unsigned size,
2991 uint32_t *state)
2992 {
2993 const struct util_format_description *desc;
2994 int first_non_void;
2995 unsigned stride;
2996 unsigned num_records;
2997 unsigned num_format, data_format;
2998
2999 desc = util_format_description(format);
3000 first_non_void = util_format_get_first_non_void_channel(format);
3001 stride = desc->block.bits / 8;
3002 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3003 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3004
3005 num_records = size / stride;
3006 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3007
3008 /* The NUM_RECORDS field has a different meaning depending on the chip,
3009 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3010 *
3011 * SI-CIK:
3012 * - If STRIDE == 0, it's in byte units.
3013 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3014 *
3015 * VI:
3016 * - For SMEM and STRIDE == 0, it's in byte units.
3017 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3018 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3019 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3020 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3021 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3022 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3023 * That way the same descriptor can be used by both SMEM and VMEM.
3024 *
3025 * GFX9:
3026 * - For SMEM and STRIDE == 0, it's in byte units.
3027 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3028 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3029 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3030 */
3031 if (screen->b.chip_class >= GFX9)
3032 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3033 * from STRIDE to bytes. This works around it by setting
3034 * NUM_RECORDS to at least the size of one element, so that
3035 * the first element is readable when IDXEN == 0.
3036 *
3037 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3038 * IDXEN is enforced?
3039 */
3040 num_records = num_records ? MAX2(num_records, stride) : 0;
3041 else if (screen->b.chip_class == VI)
3042 num_records *= stride;
3043
3044 state[4] = 0;
3045 state[5] = S_008F04_STRIDE(stride);
3046 state[6] = num_records;
3047 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3048 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3049 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3050 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3051 S_008F0C_NUM_FORMAT(num_format) |
3052 S_008F0C_DATA_FORMAT(data_format);
3053 }
3054
3055 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3056 {
3057 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3058
3059 if (swizzle[3] == PIPE_SWIZZLE_X) {
3060 /* For the pre-defined border color values (white, opaque
3061 * black, transparent black), the only thing that matters is
3062 * that the alpha channel winds up in the correct place
3063 * (because the RGB channels are all the same) so either of
3064 * these enumerations will work.
3065 */
3066 if (swizzle[2] == PIPE_SWIZZLE_Y)
3067 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3068 else
3069 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3070 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3071 if (swizzle[1] == PIPE_SWIZZLE_Y)
3072 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3073 else
3074 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3075 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3076 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3077 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3078 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3079 }
3080
3081 return bc_swizzle;
3082 }
3083
3084 /**
3085 * Build the sampler view descriptor for a texture.
3086 */
3087 void
3088 si_make_texture_descriptor(struct si_screen *screen,
3089 struct r600_texture *tex,
3090 bool sampler,
3091 enum pipe_texture_target target,
3092 enum pipe_format pipe_format,
3093 const unsigned char state_swizzle[4],
3094 unsigned first_level, unsigned last_level,
3095 unsigned first_layer, unsigned last_layer,
3096 unsigned width, unsigned height, unsigned depth,
3097 uint32_t *state,
3098 uint32_t *fmask_state)
3099 {
3100 struct pipe_resource *res = &tex->resource.b.b;
3101 const struct util_format_description *base_desc, *desc;
3102 unsigned char swizzle[4];
3103 int first_non_void;
3104 unsigned num_format, data_format, type;
3105 uint64_t va;
3106
3107 desc = util_format_description(pipe_format);
3108 base_desc = util_format_description(res->format);
3109
3110 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3111 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3112 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3113 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3114
3115 switch (pipe_format) {
3116 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3117 case PIPE_FORMAT_X32_S8X24_UINT:
3118 case PIPE_FORMAT_X8Z24_UNORM:
3119 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3120 break;
3121 case PIPE_FORMAT_X24S8_UINT:
3122 /*
3123 * X24S8 is implemented as an 8_8_8_8 data format, to
3124 * fix texture gathers. This affects at least
3125 * GL45-CTS.texture_cube_map_array.sampling on VI.
3126 */
3127 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3128 break;
3129 default:
3130 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3131 }
3132 } else {
3133 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3134 }
3135
3136 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3137
3138 switch (pipe_format) {
3139 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3140 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3141 break;
3142 default:
3143 if (first_non_void < 0) {
3144 if (util_format_is_compressed(pipe_format)) {
3145 switch (pipe_format) {
3146 case PIPE_FORMAT_DXT1_SRGB:
3147 case PIPE_FORMAT_DXT1_SRGBA:
3148 case PIPE_FORMAT_DXT3_SRGBA:
3149 case PIPE_FORMAT_DXT5_SRGBA:
3150 case PIPE_FORMAT_BPTC_SRGBA:
3151 case PIPE_FORMAT_ETC2_SRGB8:
3152 case PIPE_FORMAT_ETC2_SRGB8A1:
3153 case PIPE_FORMAT_ETC2_SRGBA8:
3154 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3155 break;
3156 case PIPE_FORMAT_RGTC1_SNORM:
3157 case PIPE_FORMAT_LATC1_SNORM:
3158 case PIPE_FORMAT_RGTC2_SNORM:
3159 case PIPE_FORMAT_LATC2_SNORM:
3160 case PIPE_FORMAT_ETC2_R11_SNORM:
3161 case PIPE_FORMAT_ETC2_RG11_SNORM:
3162 /* implies float, so use SNORM/UNORM to determine
3163 whether data is signed or not */
3164 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3165 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3166 break;
3167 default:
3168 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3169 break;
3170 }
3171 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3172 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3173 } else {
3174 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3175 }
3176 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3177 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3178 } else {
3179 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3180
3181 switch (desc->channel[first_non_void].type) {
3182 case UTIL_FORMAT_TYPE_FLOAT:
3183 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3184 break;
3185 case UTIL_FORMAT_TYPE_SIGNED:
3186 if (desc->channel[first_non_void].normalized)
3187 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3188 else if (desc->channel[first_non_void].pure_integer)
3189 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3190 else
3191 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3192 break;
3193 case UTIL_FORMAT_TYPE_UNSIGNED:
3194 if (desc->channel[first_non_void].normalized)
3195 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3196 else if (desc->channel[first_non_void].pure_integer)
3197 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3198 else
3199 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3200 }
3201 }
3202 }
3203
3204 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3205 if (data_format == ~0) {
3206 data_format = 0;
3207 }
3208
3209 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3210 if (screen->b.chip_class >= GFX9 &&
3211 util_format_has_depth(desc) &&
3212 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3213 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3214 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3215 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3216 }
3217
3218 if (!sampler &&
3219 (res->target == PIPE_TEXTURE_CUBE ||
3220 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3221 (screen->b.chip_class <= VI &&
3222 res->target == PIPE_TEXTURE_3D))) {
3223 /* For the purpose of shader images, treat cube maps and 3D
3224 * textures as 2D arrays. For 3D textures, the address
3225 * calculations for mipmaps are different, so we rely on the
3226 * caller to effectively disable mipmaps.
3227 */
3228 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3229
3230 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3231 } else {
3232 type = si_tex_dim(screen, tex, target, res->nr_samples);
3233 }
3234
3235 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3236 height = 1;
3237 depth = res->array_size;
3238 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3239 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3240 if (sampler || res->target != PIPE_TEXTURE_3D)
3241 depth = res->array_size;
3242 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3243 depth = res->array_size / 6;
3244
3245 state[0] = 0;
3246 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3247 S_008F14_NUM_FORMAT_GFX6(num_format));
3248 state[2] = (S_008F18_WIDTH(width - 1) |
3249 S_008F18_HEIGHT(height - 1) |
3250 S_008F18_PERF_MOD(4));
3251 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3252 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3253 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3254 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3255 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3256 0 : first_level) |
3257 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3258 util_logbase2(res->nr_samples) :
3259 last_level) |
3260 S_008F1C_TYPE(type));
3261 state[4] = 0;
3262 state[5] = S_008F24_BASE_ARRAY(first_layer);
3263 state[6] = 0;
3264 state[7] = 0;
3265
3266 if (screen->b.chip_class >= GFX9) {
3267 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3268
3269 /* Depth is the the last accessible layer on Gfx9.
3270 * The hw doesn't need to know the total number of layers.
3271 */
3272 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3273 state[4] |= S_008F20_DEPTH(depth - 1);
3274 else
3275 state[4] |= S_008F20_DEPTH(last_layer);
3276
3277 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3278 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3279 util_logbase2(res->nr_samples) :
3280 tex->resource.b.b.last_level);
3281 } else {
3282 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3283 state[4] |= S_008F20_DEPTH(depth - 1);
3284 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3285 }
3286
3287 if (tex->dcc_offset) {
3288 unsigned swap = r600_translate_colorswap(pipe_format, false);
3289
3290 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3291 } else {
3292 /* The last dword is unused by hw. The shader uses it to clear
3293 * bits in the first dword of sampler state.
3294 */
3295 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3296 if (first_level == last_level)
3297 state[7] = C_008F30_MAX_ANISO_RATIO;
3298 else
3299 state[7] = 0xffffffff;
3300 }
3301 }
3302
3303 /* Initialize the sampler view for FMASK. */
3304 if (tex->fmask.size) {
3305 uint32_t data_format, num_format;
3306
3307 va = tex->resource.gpu_address + tex->fmask.offset;
3308
3309 if (screen->b.chip_class >= GFX9) {
3310 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3311 switch (res->nr_samples) {
3312 case 2:
3313 num_format = V_008F14_IMG_FMASK_8_2_2;
3314 break;
3315 case 4:
3316 num_format = V_008F14_IMG_FMASK_8_4_4;
3317 break;
3318 case 8:
3319 num_format = V_008F14_IMG_FMASK_32_8_8;
3320 break;
3321 default:
3322 unreachable("invalid nr_samples");
3323 }
3324 } else {
3325 switch (res->nr_samples) {
3326 case 2:
3327 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3328 break;
3329 case 4:
3330 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3331 break;
3332 case 8:
3333 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3334 break;
3335 default:
3336 unreachable("invalid nr_samples");
3337 }
3338 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3339 }
3340
3341 fmask_state[0] = va >> 8;
3342 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3343 S_008F14_DATA_FORMAT_GFX6(data_format) |
3344 S_008F14_NUM_FORMAT_GFX6(num_format);
3345 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3346 S_008F18_HEIGHT(height - 1);
3347 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3348 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3349 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3350 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3351 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3352 fmask_state[4] = 0;
3353 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3354 fmask_state[6] = 0;
3355 fmask_state[7] = 0;
3356
3357 if (screen->b.chip_class >= GFX9) {
3358 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3359 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3360 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3361 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3362 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3363 } else {
3364 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3365 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3366 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3367 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3368 }
3369 }
3370 }
3371
3372 /**
3373 * Create a sampler view.
3374 *
3375 * @param ctx context
3376 * @param texture texture
3377 * @param state sampler view template
3378 * @param width0 width0 override (for compressed textures as int)
3379 * @param height0 height0 override (for compressed textures as int)
3380 * @param force_level set the base address to the level (for compressed textures)
3381 */
3382 struct pipe_sampler_view *
3383 si_create_sampler_view_custom(struct pipe_context *ctx,
3384 struct pipe_resource *texture,
3385 const struct pipe_sampler_view *state,
3386 unsigned width0, unsigned height0,
3387 unsigned force_level)
3388 {
3389 struct si_context *sctx = (struct si_context*)ctx;
3390 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3391 struct r600_texture *tmp = (struct r600_texture*)texture;
3392 unsigned base_level, first_level, last_level;
3393 unsigned char state_swizzle[4];
3394 unsigned height, depth, width;
3395 unsigned last_layer = state->u.tex.last_layer;
3396 enum pipe_format pipe_format;
3397 const struct legacy_surf_level *surflevel;
3398
3399 if (!view)
3400 return NULL;
3401
3402 /* initialize base object */
3403 view->base = *state;
3404 view->base.texture = NULL;
3405 view->base.reference.count = 1;
3406 view->base.context = ctx;
3407
3408 assert(texture);
3409 pipe_resource_reference(&view->base.texture, texture);
3410
3411 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3412 state->format == PIPE_FORMAT_S8X24_UINT ||
3413 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3414 state->format == PIPE_FORMAT_S8_UINT)
3415 view->is_stencil_sampler = true;
3416
3417 /* Buffer resource. */
3418 if (texture->target == PIPE_BUFFER) {
3419 si_make_buffer_descriptor(sctx->screen,
3420 (struct r600_resource *)texture,
3421 state->format,
3422 state->u.buf.offset,
3423 state->u.buf.size,
3424 view->state);
3425 return &view->base;
3426 }
3427
3428 state_swizzle[0] = state->swizzle_r;
3429 state_swizzle[1] = state->swizzle_g;
3430 state_swizzle[2] = state->swizzle_b;
3431 state_swizzle[3] = state->swizzle_a;
3432
3433 base_level = 0;
3434 first_level = state->u.tex.first_level;
3435 last_level = state->u.tex.last_level;
3436 width = width0;
3437 height = height0;
3438 depth = texture->depth0;
3439
3440 if (sctx->b.chip_class <= VI && force_level) {
3441 assert(force_level == first_level &&
3442 force_level == last_level);
3443 base_level = force_level;
3444 first_level = 0;
3445 last_level = 0;
3446 width = u_minify(width, force_level);
3447 height = u_minify(height, force_level);
3448 depth = u_minify(depth, force_level);
3449 }
3450
3451 /* This is not needed if state trackers set last_layer correctly. */
3452 if (state->target == PIPE_TEXTURE_1D ||
3453 state->target == PIPE_TEXTURE_2D ||
3454 state->target == PIPE_TEXTURE_RECT ||
3455 state->target == PIPE_TEXTURE_CUBE)
3456 last_layer = state->u.tex.first_layer;
3457
3458 /* Texturing with separate depth and stencil. */
3459 pipe_format = state->format;
3460
3461 /* Depth/stencil texturing sometimes needs separate texture. */
3462 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3463 if (!tmp->flushed_depth_texture &&
3464 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3465 pipe_resource_reference(&view->base.texture, NULL);
3466 FREE(view);
3467 return NULL;
3468 }
3469
3470 assert(tmp->flushed_depth_texture);
3471
3472 /* Override format for the case where the flushed texture
3473 * contains only Z or only S.
3474 */
3475 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3476 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3477
3478 tmp = tmp->flushed_depth_texture;
3479 }
3480
3481 surflevel = tmp->surface.u.legacy.level;
3482
3483 if (tmp->db_compatible) {
3484 if (!view->is_stencil_sampler)
3485 pipe_format = tmp->db_render_format;
3486
3487 switch (pipe_format) {
3488 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3489 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3490 break;
3491 case PIPE_FORMAT_X8Z24_UNORM:
3492 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3493 /* Z24 is always stored like this for DB
3494 * compatibility.
3495 */
3496 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3497 break;
3498 case PIPE_FORMAT_X24S8_UINT:
3499 case PIPE_FORMAT_S8X24_UINT:
3500 case PIPE_FORMAT_X32_S8X24_UINT:
3501 pipe_format = PIPE_FORMAT_S8_UINT;
3502 surflevel = tmp->surface.u.legacy.stencil_level;
3503 break;
3504 default:;
3505 }
3506 }
3507
3508 view->dcc_incompatible =
3509 vi_dcc_formats_are_incompatible(texture,
3510 state->u.tex.first_level,
3511 state->format);
3512
3513 si_make_texture_descriptor(sctx->screen, tmp, true,
3514 state->target, pipe_format, state_swizzle,
3515 first_level, last_level,
3516 state->u.tex.first_layer, last_layer,
3517 width, height, depth,
3518 view->state, view->fmask_state);
3519
3520 view->base_level_info = &surflevel[base_level];
3521 view->base_level = base_level;
3522 view->block_width = util_format_get_blockwidth(pipe_format);
3523 return &view->base;
3524 }
3525
3526 static struct pipe_sampler_view *
3527 si_create_sampler_view(struct pipe_context *ctx,
3528 struct pipe_resource *texture,
3529 const struct pipe_sampler_view *state)
3530 {
3531 return si_create_sampler_view_custom(ctx, texture, state,
3532 texture ? texture->width0 : 0,
3533 texture ? texture->height0 : 0, 0);
3534 }
3535
3536 static void si_sampler_view_destroy(struct pipe_context *ctx,
3537 struct pipe_sampler_view *state)
3538 {
3539 struct si_sampler_view *view = (struct si_sampler_view *)state;
3540
3541 pipe_resource_reference(&state->texture, NULL);
3542 FREE(view);
3543 }
3544
3545 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3546 {
3547 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3548 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3549 (linear_filter &&
3550 (wrap == PIPE_TEX_WRAP_CLAMP ||
3551 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3552 }
3553
3554 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3555 {
3556 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3557 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3558
3559 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3560 state->border_color.ui[2] || state->border_color.ui[3]) &&
3561 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3562 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3563 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3564 }
3565
3566 static void *si_create_sampler_state(struct pipe_context *ctx,
3567 const struct pipe_sampler_state *state)
3568 {
3569 struct si_context *sctx = (struct si_context *)ctx;
3570 struct r600_common_screen *rscreen = sctx->b.screen;
3571 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3572 unsigned border_color_type, border_color_index = 0;
3573 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3574 : state->max_anisotropy;
3575 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3576
3577 if (!rstate) {
3578 return NULL;
3579 }
3580
3581 if (!sampler_state_needs_border_color(state))
3582 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3583 else if (state->border_color.f[0] == 0 &&
3584 state->border_color.f[1] == 0 &&
3585 state->border_color.f[2] == 0 &&
3586 state->border_color.f[3] == 0)
3587 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3588 else if (state->border_color.f[0] == 0 &&
3589 state->border_color.f[1] == 0 &&
3590 state->border_color.f[2] == 0 &&
3591 state->border_color.f[3] == 1)
3592 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3593 else if (state->border_color.f[0] == 1 &&
3594 state->border_color.f[1] == 1 &&
3595 state->border_color.f[2] == 1 &&
3596 state->border_color.f[3] == 1)
3597 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3598 else {
3599 int i;
3600
3601 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3602
3603 /* Check if the border has been uploaded already. */
3604 for (i = 0; i < sctx->border_color_count; i++)
3605 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3606 sizeof(state->border_color)) == 0)
3607 break;
3608
3609 if (i >= SI_MAX_BORDER_COLORS) {
3610 /* Getting 4096 unique border colors is very unlikely. */
3611 fprintf(stderr, "radeonsi: The border color table is full. "
3612 "Any new border colors will be just black. "
3613 "Please file a bug.\n");
3614 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3615 } else {
3616 if (i == sctx->border_color_count) {
3617 /* Upload a new border color. */
3618 memcpy(&sctx->border_color_table[i], &state->border_color,
3619 sizeof(state->border_color));
3620 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3621 &state->border_color,
3622 sizeof(state->border_color));
3623 sctx->border_color_count++;
3624 }
3625
3626 border_color_index = i;
3627 }
3628 }
3629
3630 #ifdef DEBUG
3631 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3632 #endif
3633 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3634 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3635 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3636 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3637 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3638 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3639 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3640 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3641 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3642 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3643 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3644 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3645 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3646 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3647 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3648 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3649 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3650 S_008F38_MIP_POINT_PRECLAMP(1) |
3651 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3652 S_008F38_FILTER_PREC_FIX(1) |
3653 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3654 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3655 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3656 return rstate;
3657 }
3658
3659 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3660 {
3661 struct si_context *sctx = (struct si_context *)ctx;
3662
3663 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3664 return;
3665
3666 sctx->sample_mask.sample_mask = sample_mask;
3667 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3668 }
3669
3670 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3671 {
3672 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3673 unsigned mask = sctx->sample_mask.sample_mask;
3674
3675 /* Needed for line and polygon smoothing as well as for the Polaris
3676 * small primitive filter. We expect the state tracker to take care of
3677 * this for us.
3678 */
3679 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3680 (mask & 1 && sctx->blitter->running));
3681
3682 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3683 radeon_emit(cs, mask | (mask << 16));
3684 radeon_emit(cs, mask | (mask << 16));
3685 }
3686
3687 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3688 {
3689 #ifdef DEBUG
3690 struct si_sampler_state *s = state;
3691
3692 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3693 s->magic = 0;
3694 #endif
3695 free(state);
3696 }
3697
3698 /*
3699 * Vertex elements & buffers
3700 */
3701
3702 static void *si_create_vertex_elements(struct pipe_context *ctx,
3703 unsigned count,
3704 const struct pipe_vertex_element *elements)
3705 {
3706 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3707 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3708 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3709 int i;
3710
3711 assert(count <= SI_MAX_ATTRIBS);
3712 if (!v)
3713 return NULL;
3714
3715 v->count = count;
3716 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3717
3718 for (i = 0; i < count; ++i) {
3719 const struct util_format_description *desc;
3720 const struct util_format_channel_description *channel;
3721 unsigned data_format, num_format;
3722 int first_non_void;
3723 unsigned vbo_index = elements[i].vertex_buffer_index;
3724 unsigned char swizzle[4];
3725
3726 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3727 FREE(v);
3728 return NULL;
3729 }
3730
3731 if (elements[i].instance_divisor)
3732 v->uses_instance_divisors = true;
3733
3734 if (!used[vbo_index]) {
3735 v->first_vb_use_mask |= 1 << i;
3736 used[vbo_index] = true;
3737 }
3738
3739 desc = util_format_description(elements[i].src_format);
3740 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3741 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3742 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3743 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3744 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3745
3746 v->format_size[i] = desc->block.bits / 8;
3747
3748 /* The hardware always treats the 2-bit alpha channel as
3749 * unsigned, so a shader workaround is needed. The affected
3750 * chips are VI and older except Stoney (GFX8.1).
3751 */
3752 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3753 sscreen->b.chip_class <= VI &&
3754 sscreen->b.family != CHIP_STONEY) {
3755 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3756 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3757 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3758 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3759 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3760 /* This isn't actually used in OpenGL. */
3761 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3762 }
3763 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3764 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3765 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3766 else
3767 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3768 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3769 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3770 if (channel->normalized) {
3771 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3772 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3773 else
3774 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3775 } else {
3776 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3777 }
3778 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3779 if (channel->normalized) {
3780 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3781 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3782 else
3783 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3784 } else {
3785 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3786 }
3787 }
3788 } else if (channel && channel->size == 64 &&
3789 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3790 switch (desc->nr_channels) {
3791 case 1:
3792 case 2:
3793 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3794 swizzle[0] = PIPE_SWIZZLE_X;
3795 swizzle[1] = PIPE_SWIZZLE_Y;
3796 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3797 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3798 break;
3799 case 3:
3800 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3801 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3802 swizzle[1] = PIPE_SWIZZLE_Y;
3803 swizzle[2] = PIPE_SWIZZLE_0;
3804 swizzle[3] = PIPE_SWIZZLE_0;
3805 break;
3806 case 4:
3807 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3808 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3809 swizzle[1] = PIPE_SWIZZLE_Y;
3810 swizzle[2] = PIPE_SWIZZLE_Z;
3811 swizzle[3] = PIPE_SWIZZLE_W;
3812 break;
3813 default:
3814 assert(0);
3815 }
3816 } else if (channel && desc->nr_channels == 3) {
3817 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3818
3819 if (channel->size == 8) {
3820 if (channel->pure_integer)
3821 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3822 else
3823 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3824 } else if (channel->size == 16) {
3825 if (channel->pure_integer)
3826 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3827 else
3828 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3829 }
3830 }
3831
3832 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3833 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3834 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3835 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3836 S_008F0C_NUM_FORMAT(num_format) |
3837 S_008F0C_DATA_FORMAT(data_format);
3838 }
3839 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3840
3841 return v;
3842 }
3843
3844 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3845 {
3846 struct si_context *sctx = (struct si_context *)ctx;
3847 struct si_vertex_element *old = sctx->vertex_elements;
3848 struct si_vertex_element *v = (struct si_vertex_element*)state;
3849
3850 sctx->vertex_elements = v;
3851 sctx->vertex_buffers_dirty = true;
3852
3853 if (v &&
3854 (!old ||
3855 old->count != v->count ||
3856 old->uses_instance_divisors != v->uses_instance_divisors ||
3857 v->uses_instance_divisors || /* we don't check which divisors changed */
3858 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
3859 sctx->do_update_shaders = true;
3860 }
3861
3862 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3863 {
3864 struct si_context *sctx = (struct si_context *)ctx;
3865
3866 if (sctx->vertex_elements == state)
3867 sctx->vertex_elements = NULL;
3868 FREE(state);
3869 }
3870
3871 static void si_set_vertex_buffers(struct pipe_context *ctx,
3872 unsigned start_slot, unsigned count,
3873 const struct pipe_vertex_buffer *buffers)
3874 {
3875 struct si_context *sctx = (struct si_context *)ctx;
3876 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3877 int i;
3878
3879 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3880
3881 if (buffers) {
3882 for (i = 0; i < count; i++) {
3883 const struct pipe_vertex_buffer *src = buffers + i;
3884 struct pipe_vertex_buffer *dsti = dst + i;
3885 struct pipe_resource *buf = src->buffer.resource;
3886
3887 pipe_resource_reference(&dsti->buffer.resource, buf);
3888 dsti->buffer_offset = src->buffer_offset;
3889 dsti->stride = src->stride;
3890 r600_context_add_resource_size(ctx, buf);
3891 if (buf)
3892 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3893 }
3894 } else {
3895 for (i = 0; i < count; i++) {
3896 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3897 }
3898 }
3899 sctx->vertex_buffers_dirty = true;
3900 }
3901
3902 /*
3903 * Misc
3904 */
3905
3906 static void si_set_tess_state(struct pipe_context *ctx,
3907 const float default_outer_level[4],
3908 const float default_inner_level[2])
3909 {
3910 struct si_context *sctx = (struct si_context *)ctx;
3911 struct pipe_constant_buffer cb;
3912 float array[8];
3913
3914 memcpy(array, default_outer_level, sizeof(float) * 4);
3915 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3916
3917 cb.buffer = NULL;
3918 cb.user_buffer = NULL;
3919 cb.buffer_size = sizeof(array);
3920
3921 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3922 (void*)array, sizeof(array),
3923 &cb.buffer_offset);
3924
3925 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3926 pipe_resource_reference(&cb.buffer, NULL);
3927 }
3928
3929 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3930 {
3931 struct si_context *sctx = (struct si_context *)ctx;
3932
3933 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3934 SI_CONTEXT_INV_GLOBAL_L2 |
3935 SI_CONTEXT_FLUSH_AND_INV_CB;
3936 sctx->framebuffer.do_update_surf_dirtiness = true;
3937 }
3938
3939 /* This only ensures coherency for shader image/buffer stores. */
3940 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3941 {
3942 struct si_context *sctx = (struct si_context *)ctx;
3943
3944 /* Subsequent commands must wait for all shader invocations to
3945 * complete. */
3946 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3947 SI_CONTEXT_CS_PARTIAL_FLUSH;
3948
3949 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3950 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3951 SI_CONTEXT_INV_VMEM_L1;
3952
3953 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3954 PIPE_BARRIER_SHADER_BUFFER |
3955 PIPE_BARRIER_TEXTURE |
3956 PIPE_BARRIER_IMAGE |
3957 PIPE_BARRIER_STREAMOUT_BUFFER |
3958 PIPE_BARRIER_GLOBAL_BUFFER)) {
3959 /* As far as I can tell, L1 contents are written back to L2
3960 * automatically at end of shader, but the contents of other
3961 * L1 caches might still be stale. */
3962 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3963 }
3964
3965 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3966 /* Indices are read through TC L2 since VI.
3967 * L1 isn't used.
3968 */
3969 if (sctx->screen->b.chip_class <= CIK)
3970 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3971 }
3972
3973 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3974 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3975 SI_CONTEXT_FLUSH_AND_INV_DB;
3976
3977 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3978 PIPE_BARRIER_INDIRECT_BUFFER))
3979 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3980 }
3981
3982 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3983 {
3984 struct pipe_blend_state blend;
3985
3986 memset(&blend, 0, sizeof(blend));
3987 blend.independent_blend_enable = true;
3988 blend.rt[0].colormask = 0xf;
3989 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3990 }
3991
3992 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3993 bool include_draw_vbo)
3994 {
3995 si_need_cs_space((struct si_context*)ctx);
3996 }
3997
3998 static void si_init_config(struct si_context *sctx);
3999
4000 void si_init_state_functions(struct si_context *sctx)
4001 {
4002 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4003 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4004 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4005 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4006 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4007
4008 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4009 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4010 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4011 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4012 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4013 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4014 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4015 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4016 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4017 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4018
4019 sctx->b.b.create_blend_state = si_create_blend_state;
4020 sctx->b.b.bind_blend_state = si_bind_blend_state;
4021 sctx->b.b.delete_blend_state = si_delete_blend_state;
4022 sctx->b.b.set_blend_color = si_set_blend_color;
4023
4024 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4025 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4026 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4027
4028 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4029 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4030 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4031
4032 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4033 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4034 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4035 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4036 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4037
4038 sctx->b.b.set_clip_state = si_set_clip_state;
4039 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4040
4041 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4042 sctx->b.b.get_sample_position = cayman_get_sample_position;
4043
4044 sctx->b.b.create_sampler_state = si_create_sampler_state;
4045 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4046
4047 sctx->b.b.create_sampler_view = si_create_sampler_view;
4048 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4049
4050 sctx->b.b.set_sample_mask = si_set_sample_mask;
4051
4052 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4053 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4054 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4055 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4056
4057 sctx->b.b.texture_barrier = si_texture_barrier;
4058 sctx->b.b.memory_barrier = si_memory_barrier;
4059 sctx->b.b.set_min_samples = si_set_min_samples;
4060 sctx->b.b.set_tess_state = si_set_tess_state;
4061
4062 sctx->b.b.set_active_query_state = si_set_active_query_state;
4063 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4064 sctx->b.save_qbo_state = si_save_qbo_state;
4065 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4066
4067 sctx->b.b.draw_vbo = si_draw_vbo;
4068
4069 si_init_config(sctx);
4070 }
4071
4072 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4073 {
4074 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4075 }
4076
4077 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4078 struct r600_texture *rtex,
4079 struct radeon_bo_metadata *md)
4080 {
4081 struct si_screen *sscreen = (struct si_screen*)rscreen;
4082 struct pipe_resource *res = &rtex->resource.b.b;
4083 static const unsigned char swizzle[] = {
4084 PIPE_SWIZZLE_X,
4085 PIPE_SWIZZLE_Y,
4086 PIPE_SWIZZLE_Z,
4087 PIPE_SWIZZLE_W
4088 };
4089 uint32_t desc[8], i;
4090 bool is_array = util_resource_is_array_texture(res);
4091
4092 /* DRM 2.x.x doesn't support this. */
4093 if (rscreen->info.drm_major != 3)
4094 return;
4095
4096 assert(rtex->dcc_separate_buffer == NULL);
4097 assert(rtex->fmask.size == 0);
4098
4099 /* Metadata image format format version 1:
4100 * [0] = 1 (metadata format identifier)
4101 * [1] = (VENDOR_ID << 16) | PCI_ID
4102 * [2:9] = image descriptor for the whole resource
4103 * [2] is always 0, because the base address is cleared
4104 * [9] is the DCC offset bits [39:8] from the beginning of
4105 * the buffer
4106 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4107 */
4108
4109 md->metadata[0] = 1; /* metadata image format version 1 */
4110
4111 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4112 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4113
4114 si_make_texture_descriptor(sscreen, rtex, true,
4115 res->target, res->format,
4116 swizzle, 0, res->last_level, 0,
4117 is_array ? res->array_size - 1 : 0,
4118 res->width0, res->height0, res->depth0,
4119 desc, NULL);
4120
4121 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4122 0, 0, rtex->surface.blk_w, false, desc);
4123
4124 /* Clear the base address and set the relative DCC offset. */
4125 desc[0] = 0;
4126 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4127 desc[7] = rtex->dcc_offset >> 8;
4128
4129 /* Dwords [2:9] contain the image descriptor. */
4130 memcpy(&md->metadata[2], desc, sizeof(desc));
4131 md->size_metadata = 10 * 4;
4132
4133 /* Dwords [10:..] contain the mipmap level offsets. */
4134 if (rscreen->chip_class <= VI) {
4135 for (i = 0; i <= res->last_level; i++)
4136 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4137
4138 md->size_metadata += (1 + res->last_level) * 4;
4139 }
4140 }
4141
4142 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4143 struct r600_texture *rtex,
4144 struct radeon_bo_metadata *md)
4145 {
4146 uint32_t *desc = &md->metadata[2];
4147
4148 if (rscreen->chip_class < VI)
4149 return;
4150
4151 /* Return if DCC is enabled. The texture should be set up with it
4152 * already.
4153 */
4154 if (md->size_metadata >= 11 * 4 &&
4155 md->metadata[0] != 0 &&
4156 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4157 G_008F28_COMPRESSION_EN(desc[6])) {
4158 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4159 return;
4160 }
4161
4162 /* Disable DCC. These are always set by texture_from_handle and must
4163 * be cleared here.
4164 */
4165 rtex->dcc_offset = 0;
4166 }
4167
4168 void si_init_screen_state_functions(struct si_screen *sscreen)
4169 {
4170 sscreen->b.b.is_format_supported = si_is_format_supported;
4171 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4172 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4173 }
4174
4175 static void
4176 si_write_harvested_raster_configs(struct si_context *sctx,
4177 struct si_pm4_state *pm4,
4178 unsigned raster_config,
4179 unsigned raster_config_1)
4180 {
4181 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4182 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4183 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4184 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4185 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4186 unsigned rb_per_se = num_rb / num_se;
4187 unsigned se_mask[4];
4188 unsigned se;
4189
4190 se_mask[0] = ((1 << rb_per_se) - 1);
4191 se_mask[1] = (se_mask[0] << rb_per_se);
4192 se_mask[2] = (se_mask[1] << rb_per_se);
4193 se_mask[3] = (se_mask[2] << rb_per_se);
4194
4195 se_mask[0] &= rb_mask;
4196 se_mask[1] &= rb_mask;
4197 se_mask[2] &= rb_mask;
4198 se_mask[3] &= rb_mask;
4199
4200 assert(num_se == 1 || num_se == 2 || num_se == 4);
4201 assert(sh_per_se == 1 || sh_per_se == 2);
4202 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4203
4204 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4205 * fields are for, so I'm leaving them as their default
4206 * values. */
4207
4208 for (se = 0; se < num_se; se++) {
4209 unsigned raster_config_se = raster_config;
4210 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4211 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4212 int idx = (se / 2) * 2;
4213
4214 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4215 raster_config_se &= C_028350_SE_MAP;
4216
4217 if (!se_mask[idx]) {
4218 raster_config_se |=
4219 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4220 } else {
4221 raster_config_se |=
4222 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4223 }
4224 }
4225
4226 pkr0_mask &= rb_mask;
4227 pkr1_mask &= rb_mask;
4228 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4229 raster_config_se &= C_028350_PKR_MAP;
4230
4231 if (!pkr0_mask) {
4232 raster_config_se |=
4233 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4234 } else {
4235 raster_config_se |=
4236 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4237 }
4238 }
4239
4240 if (rb_per_se >= 2) {
4241 unsigned rb0_mask = 1 << (se * rb_per_se);
4242 unsigned rb1_mask = rb0_mask << 1;
4243
4244 rb0_mask &= rb_mask;
4245 rb1_mask &= rb_mask;
4246 if (!rb0_mask || !rb1_mask) {
4247 raster_config_se &= C_028350_RB_MAP_PKR0;
4248
4249 if (!rb0_mask) {
4250 raster_config_se |=
4251 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4252 } else {
4253 raster_config_se |=
4254 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4255 }
4256 }
4257
4258 if (rb_per_se > 2) {
4259 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4260 rb1_mask = rb0_mask << 1;
4261 rb0_mask &= rb_mask;
4262 rb1_mask &= rb_mask;
4263 if (!rb0_mask || !rb1_mask) {
4264 raster_config_se &= C_028350_RB_MAP_PKR1;
4265
4266 if (!rb0_mask) {
4267 raster_config_se |=
4268 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4269 } else {
4270 raster_config_se |=
4271 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4272 }
4273 }
4274 }
4275 }
4276
4277 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4278 if (sctx->b.chip_class < CIK)
4279 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4280 SE_INDEX(se) | SH_BROADCAST_WRITES |
4281 INSTANCE_BROADCAST_WRITES);
4282 else
4283 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4284 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4285 S_030800_INSTANCE_BROADCAST_WRITES(1));
4286 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4287 }
4288
4289 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4290 if (sctx->b.chip_class < CIK)
4291 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4292 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4293 INSTANCE_BROADCAST_WRITES);
4294 else {
4295 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4296 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4297 S_030800_INSTANCE_BROADCAST_WRITES(1));
4298
4299 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4300 (!se_mask[2] && !se_mask[3]))) {
4301 raster_config_1 &= C_028354_SE_PAIR_MAP;
4302
4303 if (!se_mask[0] && !se_mask[1]) {
4304 raster_config_1 |=
4305 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4306 } else {
4307 raster_config_1 |=
4308 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4309 }
4310 }
4311
4312 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4313 }
4314 }
4315
4316 static void si_init_config(struct si_context *sctx)
4317 {
4318 struct si_screen *sscreen = sctx->screen;
4319 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4320 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4321 unsigned raster_config, raster_config_1;
4322 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4323 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4324
4325 if (!pm4)
4326 return;
4327
4328 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4329 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4330 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4331 si_pm4_cmd_end(pm4, false);
4332
4333 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4334 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4335
4336 /* FIXME calculate these values somehow ??? */
4337 if (sctx->b.chip_class <= VI) {
4338 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4339 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4340 }
4341 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4342
4343 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4344 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4345
4346 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4347 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4348 if (sctx->b.chip_class >= GFX9)
4349 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4350 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4351 if (sctx->b.chip_class < CIK)
4352 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4353 S_008A14_CLIP_VTX_REORDER_ENA(1));
4354
4355 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4356 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4357
4358 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4359
4360 switch (sctx->screen->b.family) {
4361 case CHIP_TAHITI:
4362 case CHIP_PITCAIRN:
4363 raster_config = 0x2a00126a;
4364 raster_config_1 = 0x00000000;
4365 break;
4366 case CHIP_VERDE:
4367 raster_config = 0x0000124a;
4368 raster_config_1 = 0x00000000;
4369 break;
4370 case CHIP_OLAND:
4371 raster_config = 0x00000082;
4372 raster_config_1 = 0x00000000;
4373 break;
4374 case CHIP_HAINAN:
4375 raster_config = 0x00000000;
4376 raster_config_1 = 0x00000000;
4377 break;
4378 case CHIP_BONAIRE:
4379 raster_config = 0x16000012;
4380 raster_config_1 = 0x00000000;
4381 break;
4382 case CHIP_HAWAII:
4383 raster_config = 0x3a00161a;
4384 raster_config_1 = 0x0000002e;
4385 break;
4386 case CHIP_FIJI:
4387 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4388 /* old kernels with old tiling config */
4389 raster_config = 0x16000012;
4390 raster_config_1 = 0x0000002a;
4391 } else {
4392 raster_config = 0x3a00161a;
4393 raster_config_1 = 0x0000002e;
4394 }
4395 break;
4396 case CHIP_POLARIS10:
4397 raster_config = 0x16000012;
4398 raster_config_1 = 0x0000002a;
4399 break;
4400 case CHIP_POLARIS11:
4401 case CHIP_POLARIS12:
4402 raster_config = 0x16000012;
4403 raster_config_1 = 0x00000000;
4404 break;
4405 case CHIP_TONGA:
4406 raster_config = 0x16000012;
4407 raster_config_1 = 0x0000002a;
4408 break;
4409 case CHIP_ICELAND:
4410 if (num_rb == 1)
4411 raster_config = 0x00000000;
4412 else
4413 raster_config = 0x00000002;
4414 raster_config_1 = 0x00000000;
4415 break;
4416 case CHIP_CARRIZO:
4417 raster_config = 0x00000002;
4418 raster_config_1 = 0x00000000;
4419 break;
4420 case CHIP_KAVERI:
4421 /* KV should be 0x00000002, but that causes problems with radeon */
4422 raster_config = 0x00000000; /* 0x00000002 */
4423 raster_config_1 = 0x00000000;
4424 break;
4425 case CHIP_KABINI:
4426 case CHIP_MULLINS:
4427 case CHIP_STONEY:
4428 raster_config = 0x00000000;
4429 raster_config_1 = 0x00000000;
4430 break;
4431 default:
4432 if (sctx->b.chip_class <= VI) {
4433 fprintf(stderr,
4434 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4435 raster_config = 0x00000000;
4436 raster_config_1 = 0x00000000;
4437 }
4438 break;
4439 }
4440
4441 if (sctx->b.chip_class <= VI) {
4442 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4443 /* Always use the default config when all backends are enabled
4444 * (or when we failed to determine the enabled backends).
4445 */
4446 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4447 raster_config);
4448 if (sctx->b.chip_class >= CIK)
4449 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4450 raster_config_1);
4451 } else {
4452 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4453 }
4454 }
4455
4456 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4457 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4458 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4459 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4460 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4461 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4462 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4463
4464 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4465 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4466 S_028230_ER_TRI(0xA) |
4467 S_028230_ER_POINT(0xA) |
4468 S_028230_ER_RECT(0xA) |
4469 /* Required by DX10_DIAMOND_TEST_ENA: */
4470 S_028230_ER_LINE_LR(0x1A) |
4471 S_028230_ER_LINE_RL(0x26) |
4472 S_028230_ER_LINE_TB(0xA) |
4473 S_028230_ER_LINE_BT(0xA));
4474 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4475 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4476 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4477 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4478 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4479 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4480 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4481
4482 if (sctx->b.chip_class >= GFX9) {
4483 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4484 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4485 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4486 } else {
4487 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4488 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4489 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4490 }
4491
4492 if (sctx->b.chip_class >= CIK) {
4493 if (sctx->b.chip_class >= GFX9) {
4494 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4495 } else {
4496 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4497 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4498 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4499
4500 /* If this is 0, Bonaire can hang even if GS isn't being used.
4501 * Other chips are unaffected. These are suboptimal values,
4502 * but we don't use on-chip GS.
4503 */
4504 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4505 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4506 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4507 }
4508 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4509
4510 if (sscreen->b.info.num_good_compute_units /
4511 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4512 /* Too few available compute units per SH. Disallowing
4513 * VS to run on CU0 could hurt us more than late VS
4514 * allocation would help.
4515 *
4516 * LATE_ALLOC_VS = 2 is the highest safe number.
4517 */
4518 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4519 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4520 } else {
4521 /* Set LATE_ALLOC_VS == 31. It should be less than
4522 * the number of scratch waves. Limitations:
4523 * - VS can't execute on CU0.
4524 * - If HS writes outputs to LDS, LS can't execute on CU0.
4525 */
4526 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4527 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4528 }
4529
4530 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4531 }
4532
4533 if (sctx->b.chip_class >= VI) {
4534 unsigned vgt_tess_distribution;
4535
4536 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4537 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4538 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4539 if (sctx->b.family < CHIP_POLARIS10)
4540 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4541 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4542
4543 vgt_tess_distribution =
4544 S_028B50_ACCUM_ISOLINE(32) |
4545 S_028B50_ACCUM_TRI(11) |
4546 S_028B50_ACCUM_QUAD(11) |
4547 S_028B50_DONUT_SPLIT(16);
4548
4549 /* Testing with Unigine Heaven extreme tesselation yielded best results
4550 * with TRAP_SPLIT = 3.
4551 */
4552 if (sctx->b.family == CHIP_FIJI ||
4553 sctx->b.family >= CHIP_POLARIS10)
4554 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4555
4556 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4557 } else {
4558 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4559 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4560 }
4561
4562 if (sctx->screen->b.has_rbplus)
4563 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4564
4565 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4566 if (sctx->b.chip_class >= CIK)
4567 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4568 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4569 RADEON_PRIO_BORDER_COLORS);
4570
4571 if (sctx->b.chip_class >= GFX9) {
4572 unsigned num_se = sscreen->b.info.max_se;
4573 unsigned pc_lines = 0;
4574
4575 switch (sctx->b.family) {
4576 case CHIP_VEGA10:
4577 pc_lines = 4096;
4578 break;
4579 case CHIP_RAVEN:
4580 pc_lines = 1024;
4581 break;
4582 default:
4583 assert(0);
4584 }
4585
4586 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4587 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4588 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4589 /* TODO: We can use this to disable RBs for rendering to GART: */
4590 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4591 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4592 /* TODO: Enable the binner: */
4593 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4594 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4595 S_028C44_DISABLE_START_OF_PRIM(1));
4596 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4597 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4598 S_028C48_MAX_PRIM_PER_BATCH(1023));
4599 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4600 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4601 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4602 }
4603
4604 si_pm4_upload_indirect_buffer(sctx, pm4);
4605 sctx->init_config = pm4;
4606 }