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radeonsi: implement fast stencil clear
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend && blend->dual_src_blend &&
269 sctx->ps_shader.cso &&
270 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
271 mask = 0;
272
273 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
274 }
275
276 /*
277 * Blender functions
278 */
279
280 static uint32_t si_translate_blend_function(int blend_func)
281 {
282 switch (blend_func) {
283 case PIPE_BLEND_ADD:
284 return V_028780_COMB_DST_PLUS_SRC;
285 case PIPE_BLEND_SUBTRACT:
286 return V_028780_COMB_SRC_MINUS_DST;
287 case PIPE_BLEND_REVERSE_SUBTRACT:
288 return V_028780_COMB_DST_MINUS_SRC;
289 case PIPE_BLEND_MIN:
290 return V_028780_COMB_MIN_DST_SRC;
291 case PIPE_BLEND_MAX:
292 return V_028780_COMB_MAX_DST_SRC;
293 default:
294 R600_ERR("Unknown blend function %d\n", blend_func);
295 assert(0);
296 break;
297 }
298 return 0;
299 }
300
301 static uint32_t si_translate_blend_factor(int blend_fact)
302 {
303 switch (blend_fact) {
304 case PIPE_BLENDFACTOR_ONE:
305 return V_028780_BLEND_ONE;
306 case PIPE_BLENDFACTOR_SRC_COLOR:
307 return V_028780_BLEND_SRC_COLOR;
308 case PIPE_BLENDFACTOR_SRC_ALPHA:
309 return V_028780_BLEND_SRC_ALPHA;
310 case PIPE_BLENDFACTOR_DST_ALPHA:
311 return V_028780_BLEND_DST_ALPHA;
312 case PIPE_BLENDFACTOR_DST_COLOR:
313 return V_028780_BLEND_DST_COLOR;
314 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
315 return V_028780_BLEND_SRC_ALPHA_SATURATE;
316 case PIPE_BLENDFACTOR_CONST_COLOR:
317 return V_028780_BLEND_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_CONST_ALPHA:
319 return V_028780_BLEND_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_ZERO:
321 return V_028780_BLEND_ZERO;
322 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
323 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
324 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
326 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
327 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
328 case PIPE_BLENDFACTOR_INV_DST_COLOR:
329 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
330 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
331 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
332 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
333 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
334 case PIPE_BLENDFACTOR_SRC1_COLOR:
335 return V_028780_BLEND_SRC1_COLOR;
336 case PIPE_BLENDFACTOR_SRC1_ALPHA:
337 return V_028780_BLEND_SRC1_ALPHA;
338 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
339 return V_028780_BLEND_INV_SRC1_COLOR;
340 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
341 return V_028780_BLEND_INV_SRC1_ALPHA;
342 default:
343 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
344 assert(0);
345 break;
346 }
347 return 0;
348 }
349
350 static uint32_t si_translate_blend_opt_function(int blend_func)
351 {
352 switch (blend_func) {
353 case PIPE_BLEND_ADD:
354 return V_028760_OPT_COMB_ADD;
355 case PIPE_BLEND_SUBTRACT:
356 return V_028760_OPT_COMB_SUBTRACT;
357 case PIPE_BLEND_REVERSE_SUBTRACT:
358 return V_028760_OPT_COMB_REVSUBTRACT;
359 case PIPE_BLEND_MIN:
360 return V_028760_OPT_COMB_MIN;
361 case PIPE_BLEND_MAX:
362 return V_028760_OPT_COMB_MAX;
363 default:
364 return V_028760_OPT_COMB_BLEND_DISABLED;
365 }
366 }
367
368 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
369 {
370 switch (blend_fact) {
371 case PIPE_BLENDFACTOR_ZERO:
372 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
373 case PIPE_BLENDFACTOR_ONE:
374 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
375 case PIPE_BLENDFACTOR_SRC_COLOR:
376 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
377 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
378 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
379 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
380 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
381 case PIPE_BLENDFACTOR_SRC_ALPHA:
382 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
383 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
384 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
385 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
386 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
387 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
388 default:
389 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
390 }
391 }
392
393 static void *si_create_blend_state_mode(struct pipe_context *ctx,
394 const struct pipe_blend_state *state,
395 unsigned mode)
396 {
397 struct si_context *sctx = (struct si_context*)ctx;
398 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
399 struct si_pm4_state *pm4 = &blend->pm4;
400
401 uint32_t color_control = 0;
402
403 if (!blend)
404 return NULL;
405
406 blend->alpha_to_one = state->alpha_to_one;
407 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
408
409 if (state->logicop_enable) {
410 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
411 } else {
412 color_control |= S_028808_ROP3(0xcc);
413 }
414
415 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
416 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
417 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
418 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
419 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
420 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
421
422 blend->cb_target_mask = 0;
423 for (int i = 0; i < 8; i++) {
424 /* state->rt entries > 0 only written if independent blending */
425 const int j = state->independent_blend_enable ? i : 0;
426
427 unsigned eqRGB = state->rt[j].rgb_func;
428 unsigned srcRGB = state->rt[j].rgb_src_factor;
429 unsigned dstRGB = state->rt[j].rgb_dst_factor;
430 unsigned eqA = state->rt[j].alpha_func;
431 unsigned srcA = state->rt[j].alpha_src_factor;
432 unsigned dstA = state->rt[j].alpha_dst_factor;
433
434 unsigned blend_cntl = 0;
435
436 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
437 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
438
439 if (!state->rt[j].blend_enable) {
440 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
441 continue;
442 }
443
444 blend_cntl |= S_028780_ENABLE(1);
445 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
446 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
447 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
448
449 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
450 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
451 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
452 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
453 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
454 }
455 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
456 }
457
458 if (blend->cb_target_mask) {
459 color_control |= S_028808_MODE(mode);
460 } else {
461 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
462 }
463
464 if (sctx->b.family == CHIP_STONEY) {
465 uint32_t sx_blend_opt_control = 0;
466
467 for (int i = 0; i < 8; i++) {
468 const int j = state->independent_blend_enable ? i : 0;
469
470 /* TODO: We can also set this if the surface doesn't contain RGB. */
471 if (!state->rt[j].blend_enable ||
472 !(state->rt[j].colormask & (PIPE_MASK_R | PIPE_MASK_G | PIPE_MASK_B)))
473 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (4 * i);
474
475 /* TODO: We can also set this if the surface doesn't contain alpha. */
476 if (!state->rt[j].blend_enable ||
477 !(state->rt[j].colormask & PIPE_MASK_A))
478 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (4 * i);
479
480 if (!state->rt[j].blend_enable) {
481 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
482 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
483 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED));
484 continue;
485 }
486
487 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
488 S_028760_COLOR_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_src_factor, false)) |
489 S_028760_COLOR_DST_OPT(si_translate_blend_opt_factor(state->rt[j].rgb_dst_factor, false)) |
490 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(state->rt[j].rgb_func)) |
491 S_028760_ALPHA_SRC_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_src_factor, true)) |
492 S_028760_ALPHA_DST_OPT(si_translate_blend_opt_factor(state->rt[j].alpha_dst_factor, true)) |
493 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(state->rt[j].alpha_func)));
494 }
495
496 si_pm4_set_reg(pm4, R_02875C_SX_BLEND_OPT_CONTROL, sx_blend_opt_control);
497
498 /* RB+ doesn't work with dual source blending */
499 if (blend->dual_src_blend)
500 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
501 }
502
503 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
504 return blend;
505 }
506
507 static void *si_create_blend_state(struct pipe_context *ctx,
508 const struct pipe_blend_state *state)
509 {
510 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
511 }
512
513 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
514 {
515 struct si_context *sctx = (struct si_context *)ctx;
516 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
517 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
518 }
519
520 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
521 {
522 struct si_context *sctx = (struct si_context *)ctx;
523 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
524 }
525
526 static void si_set_blend_color(struct pipe_context *ctx,
527 const struct pipe_blend_color *state)
528 {
529 struct si_context *sctx = (struct si_context *)ctx;
530
531 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
532 return;
533
534 sctx->blend_color.state = *state;
535 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
536 }
537
538 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
539 {
540 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
541
542 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
543 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
544 }
545
546 /*
547 * Clipping, scissors and viewport
548 */
549
550 static void si_set_clip_state(struct pipe_context *ctx,
551 const struct pipe_clip_state *state)
552 {
553 struct si_context *sctx = (struct si_context *)ctx;
554 struct pipe_constant_buffer cb;
555
556 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
557 return;
558
559 sctx->clip_state.state = *state;
560 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
561
562 cb.buffer = NULL;
563 cb.user_buffer = state->ucp;
564 cb.buffer_offset = 0;
565 cb.buffer_size = 4*4*8;
566 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
567 pipe_resource_reference(&cb.buffer, NULL);
568 }
569
570 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
571 {
572 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
573
574 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
575 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
576 }
577
578 #define SIX_BITS 0x3F
579
580 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
581 {
582 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
583 struct tgsi_shader_info *info = si_get_vs_info(sctx);
584 unsigned window_space =
585 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
586 unsigned clipdist_mask =
587 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
588
589 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
590 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
591 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
592 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
593 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
594 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
595 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
596 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
597 info->writes_edgeflag ||
598 info->writes_layer ||
599 info->writes_viewport_index) |
600 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
601 (sctx->queued.named.rasterizer->clip_plane_enable &
602 clipdist_mask));
603 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
604 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
605 (clipdist_mask ? 0 :
606 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
607 S_028810_CLIP_DISABLE(window_space));
608 }
609
610 static void si_set_scissor_states(struct pipe_context *ctx,
611 unsigned start_slot,
612 unsigned num_scissors,
613 const struct pipe_scissor_state *state)
614 {
615 struct si_context *sctx = (struct si_context *)ctx;
616 int i;
617
618 for (i = 0; i < num_scissors; i++)
619 sctx->scissors.states[start_slot + i] = state[i];
620
621 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
622 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
623 }
624
625 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
626 {
627 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
628 struct pipe_scissor_state *states = sctx->scissors.states;
629 unsigned mask = sctx->scissors.dirty_mask;
630
631 /* The simple case: Only 1 viewport is active. */
632 if (mask & 1 &&
633 !si_get_vs_info(sctx)->writes_viewport_index) {
634 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
635 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
636 S_028250_TL_Y(states[0].miny) |
637 S_028250_WINDOW_OFFSET_DISABLE(1));
638 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
639 S_028254_BR_Y(states[0].maxy));
640 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
641 return;
642 }
643
644 while (mask) {
645 int start, count, i;
646
647 u_bit_scan_consecutive_range(&mask, &start, &count);
648
649 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
650 start * 4 * 2, count * 2);
651 for (i = start; i < start+count; i++) {
652 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
653 S_028250_TL_Y(states[i].miny) |
654 S_028250_WINDOW_OFFSET_DISABLE(1));
655 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
656 S_028254_BR_Y(states[i].maxy));
657 }
658 }
659 sctx->scissors.dirty_mask = 0;
660 }
661
662 static void si_set_viewport_states(struct pipe_context *ctx,
663 unsigned start_slot,
664 unsigned num_viewports,
665 const struct pipe_viewport_state *state)
666 {
667 struct si_context *sctx = (struct si_context *)ctx;
668 int i;
669
670 for (i = 0; i < num_viewports; i++)
671 sctx->viewports.states[start_slot + i] = state[i];
672
673 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
674 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
675 }
676
677 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
678 {
679 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
680 struct pipe_viewport_state *states = sctx->viewports.states;
681 unsigned mask = sctx->viewports.dirty_mask;
682
683 /* The simple case: Only 1 viewport is active. */
684 if (mask & 1 &&
685 !si_get_vs_info(sctx)->writes_viewport_index) {
686 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
687 radeon_emit(cs, fui(states[0].scale[0]));
688 radeon_emit(cs, fui(states[0].translate[0]));
689 radeon_emit(cs, fui(states[0].scale[1]));
690 radeon_emit(cs, fui(states[0].translate[1]));
691 radeon_emit(cs, fui(states[0].scale[2]));
692 radeon_emit(cs, fui(states[0].translate[2]));
693 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
694 return;
695 }
696
697 while (mask) {
698 int start, count, i;
699
700 u_bit_scan_consecutive_range(&mask, &start, &count);
701
702 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
703 start * 4 * 6, count * 6);
704 for (i = start; i < start+count; i++) {
705 radeon_emit(cs, fui(states[i].scale[0]));
706 radeon_emit(cs, fui(states[i].translate[0]));
707 radeon_emit(cs, fui(states[i].scale[1]));
708 radeon_emit(cs, fui(states[i].translate[1]));
709 radeon_emit(cs, fui(states[i].scale[2]));
710 radeon_emit(cs, fui(states[i].translate[2]));
711 }
712 }
713 sctx->viewports.dirty_mask = 0;
714 }
715
716 /*
717 * inferred state between framebuffer and rasterizer
718 */
719 static void si_update_poly_offset_state(struct si_context *sctx)
720 {
721 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
722
723 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
724 return;
725
726 switch (sctx->framebuffer.state.zsbuf->texture->format) {
727 case PIPE_FORMAT_Z16_UNORM:
728 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
729 break;
730 default: /* 24-bit */
731 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
732 break;
733 case PIPE_FORMAT_Z32_FLOAT:
734 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
735 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
736 break;
737 }
738 }
739
740 /*
741 * Rasterizer
742 */
743
744 static uint32_t si_translate_fill(uint32_t func)
745 {
746 switch(func) {
747 case PIPE_POLYGON_MODE_FILL:
748 return V_028814_X_DRAW_TRIANGLES;
749 case PIPE_POLYGON_MODE_LINE:
750 return V_028814_X_DRAW_LINES;
751 case PIPE_POLYGON_MODE_POINT:
752 return V_028814_X_DRAW_POINTS;
753 default:
754 assert(0);
755 return V_028814_X_DRAW_POINTS;
756 }
757 }
758
759 static void *si_create_rs_state(struct pipe_context *ctx,
760 const struct pipe_rasterizer_state *state)
761 {
762 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
763 struct si_pm4_state *pm4 = &rs->pm4;
764 unsigned tmp, i;
765 float psize_min, psize_max;
766
767 if (!rs) {
768 return NULL;
769 }
770
771 rs->two_side = state->light_twoside;
772 rs->multisample_enable = state->multisample;
773 rs->force_persample_interp = state->force_persample_interp;
774 rs->clip_plane_enable = state->clip_plane_enable;
775 rs->line_stipple_enable = state->line_stipple_enable;
776 rs->poly_stipple_enable = state->poly_stipple_enable;
777 rs->line_smooth = state->line_smooth;
778 rs->poly_smooth = state->poly_smooth;
779 rs->uses_poly_offset = state->offset_point || state->offset_line ||
780 state->offset_tri;
781 rs->clamp_fragment_color = state->clamp_fragment_color;
782 rs->flatshade = state->flatshade;
783 rs->sprite_coord_enable = state->sprite_coord_enable;
784 rs->rasterizer_discard = state->rasterizer_discard;
785 rs->pa_sc_line_stipple = state->line_stipple_enable ?
786 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
787 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
788 rs->pa_cl_clip_cntl =
789 S_028810_PS_UCP_MODE(3) |
790 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
791 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
792 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
793 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
794 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
795
796 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
797 S_0286D4_FLAT_SHADE_ENA(1) |
798 S_0286D4_PNT_SPRITE_ENA(1) |
799 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
800 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
801 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
802 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
803 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
804
805 /* point size 12.4 fixed point */
806 tmp = (unsigned)(state->point_size * 8.0);
807 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
808
809 if (state->point_size_per_vertex) {
810 psize_min = util_get_min_point_size(state);
811 psize_max = 8192;
812 } else {
813 /* Force the point size to be as if the vertex output was disabled. */
814 psize_min = state->point_size;
815 psize_max = state->point_size;
816 }
817 /* Divide by two, because 0.5 = 1 pixel. */
818 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
819 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
820 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
821
822 tmp = (unsigned)state->line_width * 8;
823 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
824 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
825 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
826 S_028A48_MSAA_ENABLE(state->multisample ||
827 state->poly_smooth ||
828 state->line_smooth) |
829 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
830
831 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
832 S_028BE4_PIX_CENTER(state->half_pixel_center) |
833 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
834
835 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
836 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
837 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
838 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
839 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
840 S_028814_FACE(!state->front_ccw) |
841 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
842 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
843 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
844 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
845 state->fill_back != PIPE_POLYGON_MODE_FILL) |
846 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
847 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
848 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
849 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
850
851 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
852 for (i = 0; i < 3; i++) {
853 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
854 float offset_units = state->offset_units;
855 float offset_scale = state->offset_scale * 16.0f;
856
857 switch (i) {
858 case 0: /* 16-bit zbuffer */
859 offset_units *= 4.0f;
860 break;
861 case 1: /* 24-bit zbuffer */
862 offset_units *= 2.0f;
863 break;
864 case 2: /* 32-bit zbuffer */
865 offset_units *= 1.0f;
866 break;
867 }
868
869 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
870 fui(offset_scale));
871 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
872 fui(offset_units));
873 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
874 fui(offset_scale));
875 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
876 fui(offset_units));
877 }
878
879 return rs;
880 }
881
882 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
883 {
884 struct si_context *sctx = (struct si_context *)ctx;
885 struct si_state_rasterizer *old_rs =
886 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
887 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
888
889 if (!state)
890 return;
891
892 if (sctx->framebuffer.nr_samples > 1 &&
893 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
894 si_mark_atom_dirty(sctx, &sctx->db_render_state);
895
896 si_pm4_bind_state(sctx, rasterizer, rs);
897 si_update_poly_offset_state(sctx);
898
899 si_mark_atom_dirty(sctx, &sctx->clip_regs);
900 }
901
902 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
903 {
904 struct si_context *sctx = (struct si_context *)ctx;
905
906 if (sctx->queued.named.rasterizer == state)
907 si_pm4_bind_state(sctx, poly_offset, NULL);
908 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
909 }
910
911 /*
912 * infeered state between dsa and stencil ref
913 */
914 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
915 {
916 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
917 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
918 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
919
920 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
921 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
922 S_028430_STENCILMASK(dsa->valuemask[0]) |
923 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
924 S_028430_STENCILOPVAL(1));
925 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
926 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
927 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
928 S_028434_STENCILOPVAL_BF(1));
929 }
930
931 static void si_set_stencil_ref(struct pipe_context *ctx,
932 const struct pipe_stencil_ref *state)
933 {
934 struct si_context *sctx = (struct si_context *)ctx;
935
936 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
937 return;
938
939 sctx->stencil_ref.state = *state;
940 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
941 }
942
943
944 /*
945 * DSA
946 */
947
948 static uint32_t si_translate_stencil_op(int s_op)
949 {
950 switch (s_op) {
951 case PIPE_STENCIL_OP_KEEP:
952 return V_02842C_STENCIL_KEEP;
953 case PIPE_STENCIL_OP_ZERO:
954 return V_02842C_STENCIL_ZERO;
955 case PIPE_STENCIL_OP_REPLACE:
956 return V_02842C_STENCIL_REPLACE_TEST;
957 case PIPE_STENCIL_OP_INCR:
958 return V_02842C_STENCIL_ADD_CLAMP;
959 case PIPE_STENCIL_OP_DECR:
960 return V_02842C_STENCIL_SUB_CLAMP;
961 case PIPE_STENCIL_OP_INCR_WRAP:
962 return V_02842C_STENCIL_ADD_WRAP;
963 case PIPE_STENCIL_OP_DECR_WRAP:
964 return V_02842C_STENCIL_SUB_WRAP;
965 case PIPE_STENCIL_OP_INVERT:
966 return V_02842C_STENCIL_INVERT;
967 default:
968 R600_ERR("Unknown stencil op %d", s_op);
969 assert(0);
970 break;
971 }
972 return 0;
973 }
974
975 static void *si_create_dsa_state(struct pipe_context *ctx,
976 const struct pipe_depth_stencil_alpha_state *state)
977 {
978 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
979 struct si_pm4_state *pm4 = &dsa->pm4;
980 unsigned db_depth_control;
981 uint32_t db_stencil_control = 0;
982
983 if (!dsa) {
984 return NULL;
985 }
986
987 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
988 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
989 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
990 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
991
992 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
993 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
994 S_028800_ZFUNC(state->depth.func) |
995 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
996
997 /* stencil */
998 if (state->stencil[0].enabled) {
999 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1000 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1001 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1002 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1003 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1004
1005 if (state->stencil[1].enabled) {
1006 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1007 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1008 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1009 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1010 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1011 }
1012 }
1013
1014 /* alpha */
1015 if (state->alpha.enabled) {
1016 dsa->alpha_func = state->alpha.func;
1017
1018 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1019 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1020 } else {
1021 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1022 }
1023
1024 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1025 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1026 if (state->depth.bounds_test) {
1027 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1028 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1029 }
1030
1031 return dsa;
1032 }
1033
1034 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1035 {
1036 struct si_context *sctx = (struct si_context *)ctx;
1037 struct si_state_dsa *dsa = state;
1038
1039 if (!state)
1040 return;
1041
1042 si_pm4_bind_state(sctx, dsa, dsa);
1043
1044 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1045 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1046 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1047 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1048 }
1049 }
1050
1051 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1052 {
1053 struct si_context *sctx = (struct si_context *)ctx;
1054 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1055 }
1056
1057 static void *si_create_db_flush_dsa(struct si_context *sctx)
1058 {
1059 struct pipe_depth_stencil_alpha_state dsa = {};
1060
1061 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1062 }
1063
1064 /* DB RENDER STATE */
1065
1066 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1067 {
1068 struct si_context *sctx = (struct si_context*)ctx;
1069
1070 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1071 }
1072
1073 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1074 {
1075 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1076 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1077 unsigned db_shader_control;
1078
1079 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1080
1081 /* DB_RENDER_CONTROL */
1082 if (sctx->dbcb_depth_copy_enabled ||
1083 sctx->dbcb_stencil_copy_enabled) {
1084 radeon_emit(cs,
1085 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1086 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1087 S_028000_COPY_CENTROID(1) |
1088 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1089 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1090 radeon_emit(cs,
1091 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1092 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1093 } else {
1094 radeon_emit(cs,
1095 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1096 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1097 }
1098
1099 /* DB_COUNT_CONTROL (occlusion queries) */
1100 if (sctx->b.num_occlusion_queries > 0) {
1101 if (sctx->b.chip_class >= CIK) {
1102 radeon_emit(cs,
1103 S_028004_PERFECT_ZPASS_COUNTS(1) |
1104 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1105 S_028004_ZPASS_ENABLE(1) |
1106 S_028004_SLICE_EVEN_ENABLE(1) |
1107 S_028004_SLICE_ODD_ENABLE(1));
1108 } else {
1109 radeon_emit(cs,
1110 S_028004_PERFECT_ZPASS_COUNTS(1) |
1111 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1112 }
1113 } else {
1114 /* Disable occlusion queries. */
1115 if (sctx->b.chip_class >= CIK) {
1116 radeon_emit(cs, 0);
1117 } else {
1118 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1119 }
1120 }
1121
1122 /* DB_RENDER_OVERRIDE2 */
1123 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1124 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1125 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear));
1126
1127 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1128 sctx->ps_db_shader_control;
1129
1130 /* Bug workaround for smoothing (overrasterization) on SI. */
1131 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1132 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1133 else
1134 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1135
1136 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1137 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1138 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1139
1140 if (sctx->b.family == CHIP_STONEY &&
1141 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1142 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1143
1144 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1145 db_shader_control);
1146 }
1147
1148 /*
1149 * format translation
1150 */
1151 static uint32_t si_translate_colorformat(enum pipe_format format)
1152 {
1153 const struct util_format_description *desc = util_format_description(format);
1154
1155 #define HAS_SIZE(x,y,z,w) \
1156 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1157 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1158
1159 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1160 return V_028C70_COLOR_10_11_11;
1161
1162 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1163 return V_028C70_COLOR_INVALID;
1164
1165 switch (desc->nr_channels) {
1166 case 1:
1167 switch (desc->channel[0].size) {
1168 case 8:
1169 return V_028C70_COLOR_8;
1170 case 16:
1171 return V_028C70_COLOR_16;
1172 case 32:
1173 return V_028C70_COLOR_32;
1174 }
1175 break;
1176 case 2:
1177 if (desc->channel[0].size == desc->channel[1].size) {
1178 switch (desc->channel[0].size) {
1179 case 8:
1180 return V_028C70_COLOR_8_8;
1181 case 16:
1182 return V_028C70_COLOR_16_16;
1183 case 32:
1184 return V_028C70_COLOR_32_32;
1185 }
1186 } else if (HAS_SIZE(8,24,0,0)) {
1187 return V_028C70_COLOR_24_8;
1188 } else if (HAS_SIZE(24,8,0,0)) {
1189 return V_028C70_COLOR_8_24;
1190 }
1191 break;
1192 case 3:
1193 if (HAS_SIZE(5,6,5,0)) {
1194 return V_028C70_COLOR_5_6_5;
1195 } else if (HAS_SIZE(32,8,24,0)) {
1196 return V_028C70_COLOR_X24_8_32_FLOAT;
1197 }
1198 break;
1199 case 4:
1200 if (desc->channel[0].size == desc->channel[1].size &&
1201 desc->channel[0].size == desc->channel[2].size &&
1202 desc->channel[0].size == desc->channel[3].size) {
1203 switch (desc->channel[0].size) {
1204 case 4:
1205 return V_028C70_COLOR_4_4_4_4;
1206 case 8:
1207 return V_028C70_COLOR_8_8_8_8;
1208 case 16:
1209 return V_028C70_COLOR_16_16_16_16;
1210 case 32:
1211 return V_028C70_COLOR_32_32_32_32;
1212 }
1213 } else if (HAS_SIZE(5,5,5,1)) {
1214 return V_028C70_COLOR_1_5_5_5;
1215 } else if (HAS_SIZE(10,10,10,2)) {
1216 return V_028C70_COLOR_2_10_10_10;
1217 }
1218 break;
1219 }
1220 return V_028C70_COLOR_INVALID;
1221 }
1222
1223 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1224 {
1225 if (SI_BIG_ENDIAN) {
1226 switch(colorformat) {
1227 /* 8-bit buffers. */
1228 case V_028C70_COLOR_8:
1229 return V_028C70_ENDIAN_NONE;
1230
1231 /* 16-bit buffers. */
1232 case V_028C70_COLOR_5_6_5:
1233 case V_028C70_COLOR_1_5_5_5:
1234 case V_028C70_COLOR_4_4_4_4:
1235 case V_028C70_COLOR_16:
1236 case V_028C70_COLOR_8_8:
1237 return V_028C70_ENDIAN_8IN16;
1238
1239 /* 32-bit buffers. */
1240 case V_028C70_COLOR_8_8_8_8:
1241 case V_028C70_COLOR_2_10_10_10:
1242 case V_028C70_COLOR_8_24:
1243 case V_028C70_COLOR_24_8:
1244 case V_028C70_COLOR_16_16:
1245 return V_028C70_ENDIAN_8IN32;
1246
1247 /* 64-bit buffers. */
1248 case V_028C70_COLOR_16_16_16_16:
1249 return V_028C70_ENDIAN_8IN16;
1250
1251 case V_028C70_COLOR_32_32:
1252 return V_028C70_ENDIAN_8IN32;
1253
1254 /* 128-bit buffers. */
1255 case V_028C70_COLOR_32_32_32_32:
1256 return V_028C70_ENDIAN_8IN32;
1257 default:
1258 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1259 }
1260 } else {
1261 return V_028C70_ENDIAN_NONE;
1262 }
1263 }
1264
1265 /* Returns the size in bits of the widest component of a CB format */
1266 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1267 {
1268 switch(colorformat) {
1269 case V_028C70_COLOR_4_4_4_4:
1270 return 4;
1271
1272 case V_028C70_COLOR_1_5_5_5:
1273 case V_028C70_COLOR_5_5_5_1:
1274 return 5;
1275
1276 case V_028C70_COLOR_5_6_5:
1277 return 6;
1278
1279 case V_028C70_COLOR_8:
1280 case V_028C70_COLOR_8_8:
1281 case V_028C70_COLOR_8_8_8_8:
1282 return 8;
1283
1284 case V_028C70_COLOR_10_10_10_2:
1285 case V_028C70_COLOR_2_10_10_10:
1286 return 10;
1287
1288 case V_028C70_COLOR_10_11_11:
1289 case V_028C70_COLOR_11_11_10:
1290 return 11;
1291
1292 case V_028C70_COLOR_16:
1293 case V_028C70_COLOR_16_16:
1294 case V_028C70_COLOR_16_16_16_16:
1295 return 16;
1296
1297 case V_028C70_COLOR_8_24:
1298 case V_028C70_COLOR_24_8:
1299 return 24;
1300
1301 case V_028C70_COLOR_32:
1302 case V_028C70_COLOR_32_32:
1303 case V_028C70_COLOR_32_32_32_32:
1304 case V_028C70_COLOR_X24_8_32_FLOAT:
1305 return 32;
1306 }
1307
1308 assert(!"Unknown maximum component size");
1309 return 0;
1310 }
1311
1312 static uint32_t si_translate_dbformat(enum pipe_format format)
1313 {
1314 switch (format) {
1315 case PIPE_FORMAT_Z16_UNORM:
1316 return V_028040_Z_16;
1317 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1318 case PIPE_FORMAT_X8Z24_UNORM:
1319 case PIPE_FORMAT_Z24X8_UNORM:
1320 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1321 return V_028040_Z_24; /* deprecated on SI */
1322 case PIPE_FORMAT_Z32_FLOAT:
1323 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1324 return V_028040_Z_32_FLOAT;
1325 default:
1326 return V_028040_Z_INVALID;
1327 }
1328 }
1329
1330 /*
1331 * Texture translation
1332 */
1333
1334 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1335 enum pipe_format format,
1336 const struct util_format_description *desc,
1337 int first_non_void)
1338 {
1339 struct si_screen *sscreen = (struct si_screen*)screen;
1340 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1341 sscreen->b.info.drm_minor >= 31) ||
1342 sscreen->b.info.drm_major == 3;
1343 boolean uniform = TRUE;
1344 int i;
1345
1346 /* Colorspace (return non-RGB formats directly). */
1347 switch (desc->colorspace) {
1348 /* Depth stencil formats */
1349 case UTIL_FORMAT_COLORSPACE_ZS:
1350 switch (format) {
1351 case PIPE_FORMAT_Z16_UNORM:
1352 return V_008F14_IMG_DATA_FORMAT_16;
1353 case PIPE_FORMAT_X24S8_UINT:
1354 case PIPE_FORMAT_Z24X8_UNORM:
1355 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1356 return V_008F14_IMG_DATA_FORMAT_8_24;
1357 case PIPE_FORMAT_X8Z24_UNORM:
1358 case PIPE_FORMAT_S8X24_UINT:
1359 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1360 return V_008F14_IMG_DATA_FORMAT_24_8;
1361 case PIPE_FORMAT_S8_UINT:
1362 return V_008F14_IMG_DATA_FORMAT_8;
1363 case PIPE_FORMAT_Z32_FLOAT:
1364 return V_008F14_IMG_DATA_FORMAT_32;
1365 case PIPE_FORMAT_X32_S8X24_UINT:
1366 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1367 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1368 default:
1369 goto out_unknown;
1370 }
1371
1372 case UTIL_FORMAT_COLORSPACE_YUV:
1373 goto out_unknown; /* TODO */
1374
1375 case UTIL_FORMAT_COLORSPACE_SRGB:
1376 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1377 goto out_unknown;
1378 break;
1379
1380 default:
1381 break;
1382 }
1383
1384 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1385 if (!enable_compressed_formats)
1386 goto out_unknown;
1387
1388 switch (format) {
1389 case PIPE_FORMAT_RGTC1_SNORM:
1390 case PIPE_FORMAT_LATC1_SNORM:
1391 case PIPE_FORMAT_RGTC1_UNORM:
1392 case PIPE_FORMAT_LATC1_UNORM:
1393 return V_008F14_IMG_DATA_FORMAT_BC4;
1394 case PIPE_FORMAT_RGTC2_SNORM:
1395 case PIPE_FORMAT_LATC2_SNORM:
1396 case PIPE_FORMAT_RGTC2_UNORM:
1397 case PIPE_FORMAT_LATC2_UNORM:
1398 return V_008F14_IMG_DATA_FORMAT_BC5;
1399 default:
1400 goto out_unknown;
1401 }
1402 }
1403
1404 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1405 if (!enable_compressed_formats)
1406 goto out_unknown;
1407
1408 switch (format) {
1409 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1410 case PIPE_FORMAT_BPTC_SRGBA:
1411 return V_008F14_IMG_DATA_FORMAT_BC7;
1412 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1413 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1414 return V_008F14_IMG_DATA_FORMAT_BC6;
1415 default:
1416 goto out_unknown;
1417 }
1418 }
1419
1420 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1421 switch (format) {
1422 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1423 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1424 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1425 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1426 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1427 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1428 default:
1429 goto out_unknown;
1430 }
1431 }
1432
1433 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1434 if (!enable_compressed_formats)
1435 goto out_unknown;
1436
1437 if (!util_format_s3tc_enabled) {
1438 goto out_unknown;
1439 }
1440
1441 switch (format) {
1442 case PIPE_FORMAT_DXT1_RGB:
1443 case PIPE_FORMAT_DXT1_RGBA:
1444 case PIPE_FORMAT_DXT1_SRGB:
1445 case PIPE_FORMAT_DXT1_SRGBA:
1446 return V_008F14_IMG_DATA_FORMAT_BC1;
1447 case PIPE_FORMAT_DXT3_RGBA:
1448 case PIPE_FORMAT_DXT3_SRGBA:
1449 return V_008F14_IMG_DATA_FORMAT_BC2;
1450 case PIPE_FORMAT_DXT5_RGBA:
1451 case PIPE_FORMAT_DXT5_SRGBA:
1452 return V_008F14_IMG_DATA_FORMAT_BC3;
1453 default:
1454 goto out_unknown;
1455 }
1456 }
1457
1458 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1459 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1460 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1461 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1462 }
1463
1464 /* R8G8Bx_SNORM - TODO CxV8U8 */
1465
1466 /* See whether the components are of the same size. */
1467 for (i = 1; i < desc->nr_channels; i++) {
1468 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1469 }
1470
1471 /* Non-uniform formats. */
1472 if (!uniform) {
1473 switch(desc->nr_channels) {
1474 case 3:
1475 if (desc->channel[0].size == 5 &&
1476 desc->channel[1].size == 6 &&
1477 desc->channel[2].size == 5) {
1478 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1479 }
1480 goto out_unknown;
1481 case 4:
1482 if (desc->channel[0].size == 5 &&
1483 desc->channel[1].size == 5 &&
1484 desc->channel[2].size == 5 &&
1485 desc->channel[3].size == 1) {
1486 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1487 }
1488 if (desc->channel[0].size == 10 &&
1489 desc->channel[1].size == 10 &&
1490 desc->channel[2].size == 10 &&
1491 desc->channel[3].size == 2) {
1492 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1493 }
1494 goto out_unknown;
1495 }
1496 goto out_unknown;
1497 }
1498
1499 if (first_non_void < 0 || first_non_void > 3)
1500 goto out_unknown;
1501
1502 /* uniform formats */
1503 switch (desc->channel[first_non_void].size) {
1504 case 4:
1505 switch (desc->nr_channels) {
1506 #if 0 /* Not supported for render targets */
1507 case 2:
1508 return V_008F14_IMG_DATA_FORMAT_4_4;
1509 #endif
1510 case 4:
1511 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1512 }
1513 break;
1514 case 8:
1515 switch (desc->nr_channels) {
1516 case 1:
1517 return V_008F14_IMG_DATA_FORMAT_8;
1518 case 2:
1519 return V_008F14_IMG_DATA_FORMAT_8_8;
1520 case 4:
1521 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1522 }
1523 break;
1524 case 16:
1525 switch (desc->nr_channels) {
1526 case 1:
1527 return V_008F14_IMG_DATA_FORMAT_16;
1528 case 2:
1529 return V_008F14_IMG_DATA_FORMAT_16_16;
1530 case 4:
1531 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1532 }
1533 break;
1534 case 32:
1535 switch (desc->nr_channels) {
1536 case 1:
1537 return V_008F14_IMG_DATA_FORMAT_32;
1538 case 2:
1539 return V_008F14_IMG_DATA_FORMAT_32_32;
1540 #if 0 /* Not supported for render targets */
1541 case 3:
1542 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1543 #endif
1544 case 4:
1545 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1546 }
1547 }
1548
1549 out_unknown:
1550 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1551 return ~0;
1552 }
1553
1554 static unsigned si_tex_wrap(unsigned wrap)
1555 {
1556 switch (wrap) {
1557 default:
1558 case PIPE_TEX_WRAP_REPEAT:
1559 return V_008F30_SQ_TEX_WRAP;
1560 case PIPE_TEX_WRAP_CLAMP:
1561 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1562 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1563 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1564 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1565 return V_008F30_SQ_TEX_CLAMP_BORDER;
1566 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1567 return V_008F30_SQ_TEX_MIRROR;
1568 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1569 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1570 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1571 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1572 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1573 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1574 }
1575 }
1576
1577 static unsigned si_tex_filter(unsigned filter)
1578 {
1579 switch (filter) {
1580 default:
1581 case PIPE_TEX_FILTER_NEAREST:
1582 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1583 case PIPE_TEX_FILTER_LINEAR:
1584 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1585 }
1586 }
1587
1588 static unsigned si_tex_mipfilter(unsigned filter)
1589 {
1590 switch (filter) {
1591 case PIPE_TEX_MIPFILTER_NEAREST:
1592 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1593 case PIPE_TEX_MIPFILTER_LINEAR:
1594 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1595 default:
1596 case PIPE_TEX_MIPFILTER_NONE:
1597 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1598 }
1599 }
1600
1601 static unsigned si_tex_compare(unsigned compare)
1602 {
1603 switch (compare) {
1604 default:
1605 case PIPE_FUNC_NEVER:
1606 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1607 case PIPE_FUNC_LESS:
1608 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1609 case PIPE_FUNC_EQUAL:
1610 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1611 case PIPE_FUNC_LEQUAL:
1612 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1613 case PIPE_FUNC_GREATER:
1614 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1615 case PIPE_FUNC_NOTEQUAL:
1616 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1617 case PIPE_FUNC_GEQUAL:
1618 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1619 case PIPE_FUNC_ALWAYS:
1620 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1621 }
1622 }
1623
1624 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1625 unsigned nr_samples)
1626 {
1627 if (view_target == PIPE_TEXTURE_CUBE ||
1628 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1629 res_target = view_target;
1630
1631 switch (res_target) {
1632 default:
1633 case PIPE_TEXTURE_1D:
1634 return V_008F1C_SQ_RSRC_IMG_1D;
1635 case PIPE_TEXTURE_1D_ARRAY:
1636 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1637 case PIPE_TEXTURE_2D:
1638 case PIPE_TEXTURE_RECT:
1639 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1640 V_008F1C_SQ_RSRC_IMG_2D;
1641 case PIPE_TEXTURE_2D_ARRAY:
1642 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1643 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1644 case PIPE_TEXTURE_3D:
1645 return V_008F1C_SQ_RSRC_IMG_3D;
1646 case PIPE_TEXTURE_CUBE:
1647 case PIPE_TEXTURE_CUBE_ARRAY:
1648 return V_008F1C_SQ_RSRC_IMG_CUBE;
1649 }
1650 }
1651
1652 /*
1653 * Format support testing
1654 */
1655
1656 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1657 {
1658 return si_translate_texformat(screen, format, util_format_description(format),
1659 util_format_get_first_non_void_channel(format)) != ~0U;
1660 }
1661
1662 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1663 const struct util_format_description *desc,
1664 int first_non_void)
1665 {
1666 unsigned type = desc->channel[first_non_void].type;
1667 int i;
1668
1669 if (type == UTIL_FORMAT_TYPE_FIXED)
1670 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1671
1672 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1673 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1674
1675 if (desc->nr_channels == 4 &&
1676 desc->channel[0].size == 10 &&
1677 desc->channel[1].size == 10 &&
1678 desc->channel[2].size == 10 &&
1679 desc->channel[3].size == 2)
1680 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1681
1682 /* See whether the components are of the same size. */
1683 for (i = 0; i < desc->nr_channels; i++) {
1684 if (desc->channel[first_non_void].size != desc->channel[i].size)
1685 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1686 }
1687
1688 switch (desc->channel[first_non_void].size) {
1689 case 8:
1690 switch (desc->nr_channels) {
1691 case 1:
1692 return V_008F0C_BUF_DATA_FORMAT_8;
1693 case 2:
1694 return V_008F0C_BUF_DATA_FORMAT_8_8;
1695 case 3:
1696 case 4:
1697 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1698 }
1699 break;
1700 case 16:
1701 switch (desc->nr_channels) {
1702 case 1:
1703 return V_008F0C_BUF_DATA_FORMAT_16;
1704 case 2:
1705 return V_008F0C_BUF_DATA_FORMAT_16_16;
1706 case 3:
1707 case 4:
1708 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1709 }
1710 break;
1711 case 32:
1712 /* From the Southern Islands ISA documentation about MTBUF:
1713 * 'Memory reads of data in memory that is 32 or 64 bits do not
1714 * undergo any format conversion.'
1715 */
1716 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1717 !desc->channel[first_non_void].pure_integer)
1718 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1719
1720 switch (desc->nr_channels) {
1721 case 1:
1722 return V_008F0C_BUF_DATA_FORMAT_32;
1723 case 2:
1724 return V_008F0C_BUF_DATA_FORMAT_32_32;
1725 case 3:
1726 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1727 case 4:
1728 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1729 }
1730 break;
1731 }
1732
1733 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1734 }
1735
1736 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1737 const struct util_format_description *desc,
1738 int first_non_void)
1739 {
1740 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1741 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1742
1743 switch (desc->channel[first_non_void].type) {
1744 case UTIL_FORMAT_TYPE_SIGNED:
1745 if (desc->channel[first_non_void].normalized)
1746 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1747 else if (desc->channel[first_non_void].pure_integer)
1748 return V_008F0C_BUF_NUM_FORMAT_SINT;
1749 else
1750 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1751 break;
1752 case UTIL_FORMAT_TYPE_UNSIGNED:
1753 if (desc->channel[first_non_void].normalized)
1754 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1755 else if (desc->channel[first_non_void].pure_integer)
1756 return V_008F0C_BUF_NUM_FORMAT_UINT;
1757 else
1758 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1759 break;
1760 case UTIL_FORMAT_TYPE_FLOAT:
1761 default:
1762 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1763 }
1764 }
1765
1766 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1767 {
1768 const struct util_format_description *desc;
1769 int first_non_void;
1770 unsigned data_format;
1771
1772 desc = util_format_description(format);
1773 first_non_void = util_format_get_first_non_void_channel(format);
1774 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1775 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1776 }
1777
1778 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1779 {
1780 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1781 r600_translate_colorswap(format) != ~0U;
1782 }
1783
1784 static bool si_is_zs_format_supported(enum pipe_format format)
1785 {
1786 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1787 }
1788
1789 boolean si_is_format_supported(struct pipe_screen *screen,
1790 enum pipe_format format,
1791 enum pipe_texture_target target,
1792 unsigned sample_count,
1793 unsigned usage)
1794 {
1795 unsigned retval = 0;
1796
1797 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1798 R600_ERR("r600: unsupported texture type %d\n", target);
1799 return FALSE;
1800 }
1801
1802 if (!util_format_is_supported(format, usage))
1803 return FALSE;
1804
1805 if (sample_count > 1) {
1806 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1807 return FALSE;
1808
1809 switch (sample_count) {
1810 case 2:
1811 case 4:
1812 case 8:
1813 break;
1814 default:
1815 return FALSE;
1816 }
1817 }
1818
1819 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1820 if (target == PIPE_BUFFER) {
1821 if (si_is_vertex_format_supported(screen, format))
1822 retval |= PIPE_BIND_SAMPLER_VIEW;
1823 } else {
1824 if (si_is_sampler_format_supported(screen, format))
1825 retval |= PIPE_BIND_SAMPLER_VIEW;
1826 }
1827 }
1828
1829 if ((usage & (PIPE_BIND_RENDER_TARGET |
1830 PIPE_BIND_DISPLAY_TARGET |
1831 PIPE_BIND_SCANOUT |
1832 PIPE_BIND_SHARED |
1833 PIPE_BIND_BLENDABLE)) &&
1834 si_is_colorbuffer_format_supported(format)) {
1835 retval |= usage &
1836 (PIPE_BIND_RENDER_TARGET |
1837 PIPE_BIND_DISPLAY_TARGET |
1838 PIPE_BIND_SCANOUT |
1839 PIPE_BIND_SHARED);
1840 if (!util_format_is_pure_integer(format) &&
1841 !util_format_is_depth_or_stencil(format))
1842 retval |= usage & PIPE_BIND_BLENDABLE;
1843 }
1844
1845 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1846 si_is_zs_format_supported(format)) {
1847 retval |= PIPE_BIND_DEPTH_STENCIL;
1848 }
1849
1850 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1851 si_is_vertex_format_supported(screen, format)) {
1852 retval |= PIPE_BIND_VERTEX_BUFFER;
1853 }
1854
1855 if (usage & PIPE_BIND_TRANSFER_READ)
1856 retval |= PIPE_BIND_TRANSFER_READ;
1857 if (usage & PIPE_BIND_TRANSFER_WRITE)
1858 retval |= PIPE_BIND_TRANSFER_WRITE;
1859
1860 return retval == usage;
1861 }
1862
1863 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1864 {
1865 unsigned tile_mode_index = 0;
1866
1867 if (stencil) {
1868 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1869 } else {
1870 tile_mode_index = rtex->surface.tiling_index[level];
1871 }
1872 return tile_mode_index;
1873 }
1874
1875 /*
1876 * framebuffer handling
1877 */
1878
1879 static void si_initialize_color_surface(struct si_context *sctx,
1880 struct r600_surface *surf)
1881 {
1882 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1883 unsigned level = surf->base.u.tex.level;
1884 uint64_t offset = rtex->surface.level[level].offset;
1885 unsigned pitch, slice;
1886 unsigned color_info, color_attrib, color_pitch, color_view;
1887 unsigned tile_mode_index;
1888 unsigned format, swap, ntype, endian;
1889 const struct util_format_description *desc;
1890 int i;
1891 unsigned blend_clamp = 0, blend_bypass = 0;
1892 unsigned max_comp_size;
1893
1894 /* Layered rendering doesn't work with LINEAR_GENERAL.
1895 * (LINEAR_ALIGNED and others work) */
1896 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1897 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1898 offset += rtex->surface.level[level].slice_size *
1899 surf->base.u.tex.first_layer;
1900 color_view = 0;
1901 } else {
1902 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1903 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1904 }
1905
1906 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1907 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1908 if (slice) {
1909 slice = slice - 1;
1910 }
1911
1912 tile_mode_index = si_tile_mode_index(rtex, level, false);
1913
1914 desc = util_format_description(surf->base.format);
1915 for (i = 0; i < 4; i++) {
1916 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1917 break;
1918 }
1919 }
1920 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1921 ntype = V_028C70_NUMBER_FLOAT;
1922 } else {
1923 ntype = V_028C70_NUMBER_UNORM;
1924 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1925 ntype = V_028C70_NUMBER_SRGB;
1926 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1927 if (desc->channel[i].pure_integer) {
1928 ntype = V_028C70_NUMBER_SINT;
1929 } else {
1930 assert(desc->channel[i].normalized);
1931 ntype = V_028C70_NUMBER_SNORM;
1932 }
1933 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1934 if (desc->channel[i].pure_integer) {
1935 ntype = V_028C70_NUMBER_UINT;
1936 } else {
1937 assert(desc->channel[i].normalized);
1938 ntype = V_028C70_NUMBER_UNORM;
1939 }
1940 }
1941 }
1942
1943 format = si_translate_colorformat(surf->base.format);
1944 if (format == V_028C70_COLOR_INVALID) {
1945 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1946 }
1947 assert(format != V_028C70_COLOR_INVALID);
1948 swap = r600_translate_colorswap(surf->base.format);
1949 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1950 endian = V_028C70_ENDIAN_NONE;
1951 } else {
1952 endian = si_colorformat_endian_swap(format);
1953 }
1954
1955 /* blend clamp should be set for all NORM/SRGB types */
1956 if (ntype == V_028C70_NUMBER_UNORM ||
1957 ntype == V_028C70_NUMBER_SNORM ||
1958 ntype == V_028C70_NUMBER_SRGB)
1959 blend_clamp = 1;
1960
1961 /* set blend bypass according to docs if SINT/UINT or
1962 8/24 COLOR variants */
1963 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1964 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1965 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1966 blend_clamp = 0;
1967 blend_bypass = 1;
1968 }
1969
1970 color_info = S_028C70_FORMAT(format) |
1971 S_028C70_COMP_SWAP(swap) |
1972 S_028C70_BLEND_CLAMP(blend_clamp) |
1973 S_028C70_BLEND_BYPASS(blend_bypass) |
1974 S_028C70_NUMBER_TYPE(ntype) |
1975 S_028C70_ENDIAN(endian);
1976
1977 color_pitch = S_028C64_TILE_MAX(pitch);
1978
1979 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1980 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1981
1982 if (rtex->resource.b.b.nr_samples > 1) {
1983 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1984
1985 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1986 S_028C74_NUM_FRAGMENTS(log_samples);
1987
1988 if (rtex->fmask.size) {
1989 color_info |= S_028C70_COMPRESSION(1);
1990 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1991
1992 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1993
1994 if (sctx->b.chip_class == SI) {
1995 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1996 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1997 }
1998 if (sctx->b.chip_class >= CIK) {
1999 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2000 }
2001 }
2002 }
2003
2004 offset += rtex->resource.gpu_address;
2005
2006 surf->cb_color_base = offset >> 8;
2007 surf->cb_color_pitch = color_pitch;
2008 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2009 surf->cb_color_view = color_view;
2010 surf->cb_color_info = color_info;
2011 surf->cb_color_attrib = color_attrib;
2012
2013 if (sctx->b.chip_class >= VI && rtex->dcc_buffer) {
2014 unsigned max_uncompressed_block_size = 2;
2015 uint64_t dcc_offset = rtex->surface.level[level].dcc_offset;
2016
2017 if (rtex->surface.nsamples > 1) {
2018 if (rtex->surface.bpe == 1)
2019 max_uncompressed_block_size = 0;
2020 else if (rtex->surface.bpe == 2)
2021 max_uncompressed_block_size = 1;
2022 }
2023
2024 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2025 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2026 surf->cb_dcc_base = (rtex->dcc_buffer->gpu_address + dcc_offset) >> 8;
2027 }
2028
2029 if (rtex->fmask.size) {
2030 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2031 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2032 } else {
2033 /* This must be set for fast clear to work without FMASK. */
2034 surf->cb_color_fmask = surf->cb_color_base;
2035 surf->cb_color_fmask_slice = surf->cb_color_slice;
2036 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2037
2038 if (sctx->b.chip_class == SI) {
2039 unsigned bankh = util_logbase2(rtex->surface.bankh);
2040 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2041 }
2042
2043 if (sctx->b.chip_class >= CIK) {
2044 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2045 }
2046 }
2047
2048 /* Determine pixel shader export format */
2049 max_comp_size = si_colorformat_max_comp_size(format);
2050 if (ntype == V_028C70_NUMBER_SRGB ||
2051 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
2052 max_comp_size <= 10) ||
2053 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
2054 surf->export_16bpc = true;
2055 }
2056
2057 if (sctx->b.family == CHIP_STONEY &&
2058 !(sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)) {
2059 switch (desc->channel[0].size) {
2060 case 32:
2061 if (desc->nr_channels == 1) {
2062 if (swap == V_0280A0_SWAP_STD)
2063 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_R;
2064 else if (swap == V_0280A0_SWAP_ALT_REV)
2065 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_32_A;
2066 }
2067 break;
2068 case 16:
2069 /* For 1-channel formats, use the superset thereof. */
2070 if (desc->nr_channels <= 2) {
2071 if (swap == V_0280A0_SWAP_STD ||
2072 swap == V_0280A0_SWAP_STD_REV)
2073 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_GR;
2074 else
2075 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_16_16_AR;
2076 }
2077 break;
2078 case 11:
2079 if (desc->nr_channels == 3) {
2080 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_10_11_11;
2081 surf->sx_blend_opt_epsilon = V_028758_11BIT_FORMAT;
2082 }
2083 break;
2084 case 10:
2085 if (desc->nr_channels == 4) {
2086 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_2_10_10_10;
2087 surf->sx_blend_opt_epsilon = V_028758_10BIT_FORMAT;
2088 }
2089 break;
2090 case 8:
2091 /* For 1 and 2-channel formats, use the superset thereof. */
2092 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_8_8_8_8;
2093 surf->sx_blend_opt_epsilon = V_028758_8BIT_FORMAT;
2094 break;
2095 case 5:
2096 if (desc->nr_channels == 3) {
2097 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_5_6_5;
2098 surf->sx_blend_opt_epsilon = V_028758_6BIT_FORMAT;
2099 } else if (desc->nr_channels == 4) {
2100 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_1_5_5_5;
2101 surf->sx_blend_opt_epsilon = V_028758_5BIT_FORMAT;
2102 }
2103 break;
2104 case 4:
2105 /* For 1 nad 2-channel formats, use the superset thereof. */
2106 surf->sx_ps_downconvert = V_028754_SX_RT_EXPORT_4_4_4_4;
2107 surf->sx_blend_opt_epsilon = V_028758_4BIT_FORMAT;
2108 break;
2109 }
2110 }
2111
2112 surf->color_initialized = true;
2113 }
2114
2115 static void si_init_depth_surface(struct si_context *sctx,
2116 struct r600_surface *surf)
2117 {
2118 struct si_screen *sscreen = sctx->screen;
2119 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2120 unsigned level = surf->base.u.tex.level;
2121 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2122 unsigned format, tile_mode_index, array_mode;
2123 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
2124 uint32_t z_info, s_info, db_depth_info;
2125 uint64_t z_offs, s_offs;
2126 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2127
2128 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2129 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2130 case PIPE_FORMAT_X8Z24_UNORM:
2131 case PIPE_FORMAT_Z24X8_UNORM:
2132 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2133 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2134 break;
2135 case PIPE_FORMAT_Z32_FLOAT:
2136 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2137 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2138 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2139 break;
2140 case PIPE_FORMAT_Z16_UNORM:
2141 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2142 break;
2143 default:
2144 assert(0);
2145 }
2146
2147 format = si_translate_dbformat(rtex->resource.b.b.format);
2148
2149 if (format == V_028040_Z_INVALID) {
2150 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2151 }
2152 assert(format != V_028040_Z_INVALID);
2153
2154 s_offs = z_offs = rtex->resource.gpu_address;
2155 z_offs += rtex->surface.level[level].offset;
2156 s_offs += rtex->surface.stencil_level[level].offset;
2157
2158 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2159
2160 z_info = S_028040_FORMAT(format);
2161 if (rtex->resource.b.b.nr_samples > 1) {
2162 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2163 }
2164
2165 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2166 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2167 else
2168 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2169
2170 if (sctx->b.chip_class >= CIK) {
2171 switch (rtex->surface.level[level].mode) {
2172 case RADEON_SURF_MODE_2D:
2173 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2174 break;
2175 case RADEON_SURF_MODE_1D:
2176 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2177 case RADEON_SURF_MODE_LINEAR:
2178 default:
2179 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2180 break;
2181 }
2182 tile_split = rtex->surface.tile_split;
2183 stile_split = rtex->surface.stencil_tile_split;
2184 macro_aspect = rtex->surface.mtilea;
2185 bankw = rtex->surface.bankw;
2186 bankh = rtex->surface.bankh;
2187 tile_split = cik_tile_split(tile_split);
2188 stile_split = cik_tile_split(stile_split);
2189 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2190 bankw = cik_bank_wh(bankw);
2191 bankh = cik_bank_wh(bankh);
2192 nbanks = si_num_banks(sscreen, rtex);
2193 tile_mode_index = si_tile_mode_index(rtex, level, false);
2194 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2195
2196 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2197 S_02803C_PIPE_CONFIG(pipe_config) |
2198 S_02803C_BANK_WIDTH(bankw) |
2199 S_02803C_BANK_HEIGHT(bankh) |
2200 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2201 S_02803C_NUM_BANKS(nbanks);
2202 z_info |= S_028040_TILE_SPLIT(tile_split);
2203 s_info |= S_028044_TILE_SPLIT(stile_split);
2204 } else {
2205 tile_mode_index = si_tile_mode_index(rtex, level, false);
2206 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2207 tile_mode_index = si_tile_mode_index(rtex, level, true);
2208 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2209 }
2210
2211 /* HiZ aka depth buffer htile */
2212 /* use htile only for first level */
2213 if (rtex->htile_buffer && !level) {
2214 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2215 S_028040_ALLOW_EXPCLEAR(1);
2216
2217 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2218 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2219 else
2220 /* Use all of the htile_buffer for depth if there's no stencil. */
2221 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2222
2223 uint64_t va = rtex->htile_buffer->gpu_address;
2224 db_htile_data_base = va >> 8;
2225 db_htile_surface = S_028ABC_FULL_CACHE(1);
2226 } else {
2227 db_htile_data_base = 0;
2228 db_htile_surface = 0;
2229 }
2230
2231 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2232
2233 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2234 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2235 surf->db_htile_data_base = db_htile_data_base;
2236 surf->db_depth_info = db_depth_info;
2237 surf->db_z_info = z_info;
2238 surf->db_stencil_info = s_info;
2239 surf->db_depth_base = z_offs >> 8;
2240 surf->db_stencil_base = s_offs >> 8;
2241 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2242 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2243 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2244 levelinfo->nblk_y) / 64 - 1);
2245 surf->db_htile_surface = db_htile_surface;
2246 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2247
2248 surf->depth_initialized = true;
2249 }
2250
2251 static void si_set_framebuffer_state(struct pipe_context *ctx,
2252 const struct pipe_framebuffer_state *state)
2253 {
2254 struct si_context *sctx = (struct si_context *)ctx;
2255 struct pipe_constant_buffer constbuf = {0};
2256 struct r600_surface *surf = NULL;
2257 struct r600_texture *rtex;
2258 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2259 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2260 int i;
2261
2262 /* Only flush TC when changing the framebuffer state, because
2263 * the only client not using TC that can change textures is
2264 * the framebuffer.
2265 *
2266 * Flush all CB and DB caches here because all buffers can be used
2267 * for write by both TC (with shader image stores) and CB/DB.
2268 */
2269 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2270 SI_CONTEXT_INV_GLOBAL_L2 |
2271 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2272
2273 /* Take the maximum of the old and new count. If the new count is lower,
2274 * dirtying is needed to disable the unbound colorbuffers.
2275 */
2276 sctx->framebuffer.dirty_cbufs |=
2277 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2278 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2279
2280 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2281
2282 sctx->framebuffer.export_16bpc = 0;
2283 sctx->framebuffer.compressed_cb_mask = 0;
2284 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2285 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2286 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2287 util_format_is_pure_integer(state->cbufs[0]->format);
2288
2289 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2290 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2291
2292 for (i = 0; i < state->nr_cbufs; i++) {
2293 if (!state->cbufs[i])
2294 continue;
2295
2296 surf = (struct r600_surface*)state->cbufs[i];
2297 rtex = (struct r600_texture*)surf->base.texture;
2298
2299 if (!surf->color_initialized) {
2300 si_initialize_color_surface(sctx, surf);
2301 }
2302
2303 if (surf->export_16bpc) {
2304 sctx->framebuffer.export_16bpc |= 1 << i;
2305 }
2306
2307 if (rtex->fmask.size && rtex->cmask.size) {
2308 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2309 }
2310 r600_context_add_resource_size(ctx, surf->base.texture);
2311 }
2312 /* Set the 16BPC export for possible dual-src blending. */
2313 if (i == 1 && surf && surf->export_16bpc) {
2314 sctx->framebuffer.export_16bpc |= 1 << 1;
2315 }
2316
2317 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2318
2319 if (state->zsbuf) {
2320 surf = (struct r600_surface*)state->zsbuf;
2321
2322 if (!surf->depth_initialized) {
2323 si_init_depth_surface(sctx, surf);
2324 }
2325 r600_context_add_resource_size(ctx, surf->base.texture);
2326 }
2327
2328 si_update_poly_offset_state(sctx);
2329 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2330 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2331
2332 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2333 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2334 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2335
2336 /* Set sample locations as fragment shader constants. */
2337 switch (sctx->framebuffer.nr_samples) {
2338 case 1:
2339 constbuf.user_buffer = sctx->b.sample_locations_1x;
2340 break;
2341 case 2:
2342 constbuf.user_buffer = sctx->b.sample_locations_2x;
2343 break;
2344 case 4:
2345 constbuf.user_buffer = sctx->b.sample_locations_4x;
2346 break;
2347 case 8:
2348 constbuf.user_buffer = sctx->b.sample_locations_8x;
2349 break;
2350 case 16:
2351 constbuf.user_buffer = sctx->b.sample_locations_16x;
2352 break;
2353 default:
2354 assert(0);
2355 }
2356 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2357 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2358 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2359
2360 /* Smoothing (only possible with nr_samples == 1) uses the same
2361 * sample locations as the MSAA it simulates.
2362 *
2363 * Therefore, don't update the sample locations when
2364 * transitioning from no AA to smoothing-equivalent AA, and
2365 * vice versa.
2366 */
2367 if ((sctx->framebuffer.nr_samples != 1 ||
2368 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2369 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2370 old_nr_samples != 1))
2371 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2372 }
2373 }
2374
2375 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2376 {
2377 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2378 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2379 unsigned i, nr_cbufs = state->nr_cbufs;
2380 struct r600_texture *tex = NULL;
2381 struct r600_surface *cb = NULL;
2382 uint32_t sx_ps_downconvert = 0;
2383 uint32_t sx_blend_opt_epsilon = 0;
2384
2385 /* Colorbuffers. */
2386 for (i = 0; i < nr_cbufs; i++) {
2387 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2388 continue;
2389
2390 cb = (struct r600_surface*)state->cbufs[i];
2391 if (!cb) {
2392 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2393 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2394 continue;
2395 }
2396
2397 tex = (struct r600_texture *)cb->base.texture;
2398 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2399 &tex->resource, RADEON_USAGE_READWRITE,
2400 tex->surface.nsamples > 1 ?
2401 RADEON_PRIO_COLOR_BUFFER_MSAA :
2402 RADEON_PRIO_COLOR_BUFFER);
2403
2404 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2405 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2406 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2407 RADEON_PRIO_CMASK);
2408 }
2409
2410 if (tex->dcc_buffer && tex->dcc_buffer != &tex->resource) {
2411 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2412 tex->dcc_buffer, RADEON_USAGE_READWRITE,
2413 RADEON_PRIO_DCC);
2414 }
2415
2416 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2417 sctx->b.chip_class >= VI ? 14 : 13);
2418 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2419 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2420 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2421 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2422 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2423 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2424 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2425 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2426 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2427 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2428 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2429 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2430 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2431
2432 if (sctx->b.chip_class >= VI)
2433 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2434
2435 sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i);
2436 sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i);
2437 }
2438 /* set CB_COLOR1_INFO for possible dual-src blending */
2439 if (i == 1 && state->cbufs[0] &&
2440 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2441 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2442 cb->cb_color_info | tex->cb_color_info);
2443 sx_ps_downconvert |= cb->sx_ps_downconvert << (4 * i);
2444 sx_blend_opt_epsilon |= cb->sx_blend_opt_epsilon << (4 * i);
2445 i++;
2446 }
2447 for (; i < 8 ; i++)
2448 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2449 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2450
2451 if (sctx->b.family == CHIP_STONEY) {
2452 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 2);
2453 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
2454 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
2455 }
2456
2457 /* ZS buffer. */
2458 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2459 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2460 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2461
2462 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2463 &rtex->resource, RADEON_USAGE_READWRITE,
2464 zb->base.texture->nr_samples > 1 ?
2465 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2466 RADEON_PRIO_DEPTH_BUFFER);
2467
2468 if (zb->db_htile_data_base) {
2469 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2470 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2471 RADEON_PRIO_HTILE);
2472 }
2473
2474 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2475 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2476
2477 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2478 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2479 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2480 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2481 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2482 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2483 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2484 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2485 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2486 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2487 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2488
2489 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2490 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2491 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2492
2493 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2494 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2495 zb->pa_su_poly_offset_db_fmt_cntl);
2496 } else if (sctx->framebuffer.dirty_zsbuf) {
2497 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2498 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2499 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2500 }
2501
2502 /* Framebuffer dimensions. */
2503 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2504 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2505 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2506
2507 sctx->framebuffer.dirty_cbufs = 0;
2508 sctx->framebuffer.dirty_zsbuf = false;
2509 }
2510
2511 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2512 struct r600_atom *atom)
2513 {
2514 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2515 unsigned nr_samples = sctx->framebuffer.nr_samples;
2516
2517 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2518 SI_NUM_SMOOTH_AA_SAMPLES);
2519 }
2520
2521 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2522 {
2523 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2524
2525 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2526 sctx->ps_iter_samples,
2527 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2528 }
2529
2530
2531 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2532 {
2533 struct si_context *sctx = (struct si_context *)ctx;
2534
2535 if (sctx->ps_iter_samples == min_samples)
2536 return;
2537
2538 sctx->ps_iter_samples = min_samples;
2539
2540 if (sctx->framebuffer.nr_samples > 1)
2541 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2542 }
2543
2544 /*
2545 * Samplers
2546 */
2547
2548 /**
2549 * Create a sampler view.
2550 *
2551 * @param ctx context
2552 * @param texture texture
2553 * @param state sampler view template
2554 * @param width0 width0 override (for compressed textures as int)
2555 * @param height0 height0 override (for compressed textures as int)
2556 * @param force_level set the base address to the level (for compressed textures)
2557 */
2558 struct pipe_sampler_view *
2559 si_create_sampler_view_custom(struct pipe_context *ctx,
2560 struct pipe_resource *texture,
2561 const struct pipe_sampler_view *state,
2562 unsigned width0, unsigned height0,
2563 unsigned force_level)
2564 {
2565 struct si_context *sctx = (struct si_context*)ctx;
2566 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2567 struct r600_texture *tmp = (struct r600_texture*)texture;
2568 const struct util_format_description *desc;
2569 unsigned format, num_format, base_level, first_level, last_level;
2570 uint32_t pitch = 0;
2571 unsigned char state_swizzle[4], swizzle[4];
2572 unsigned height, depth, width;
2573 enum pipe_format pipe_format = state->format;
2574 struct radeon_surf_level *surflevel;
2575 int first_non_void;
2576 uint64_t va;
2577 unsigned last_layer = state->u.tex.last_layer;
2578
2579 if (!view)
2580 return NULL;
2581
2582 /* initialize base object */
2583 view->base = *state;
2584 view->base.texture = NULL;
2585 view->base.reference.count = 1;
2586 view->base.context = ctx;
2587
2588 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2589 if (!texture) {
2590 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2591 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2592 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2593 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2594 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2595 return &view->base;
2596 }
2597
2598 pipe_resource_reference(&view->base.texture, texture);
2599 view->resource = &tmp->resource;
2600
2601 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2602 state->format == PIPE_FORMAT_S8X24_UINT ||
2603 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2604 state->format == PIPE_FORMAT_S8_UINT)
2605 view->is_stencil_sampler = true;
2606
2607 /* Buffer resource. */
2608 if (texture->target == PIPE_BUFFER) {
2609 unsigned stride, num_records;
2610
2611 desc = util_format_description(state->format);
2612 first_non_void = util_format_get_first_non_void_channel(state->format);
2613 stride = desc->block.bits / 8;
2614 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2615 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2616 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2617
2618 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2619 num_records = MIN2(num_records, texture->width0 / stride);
2620
2621 if (sctx->b.chip_class >= VI)
2622 num_records *= stride;
2623
2624 view->state[4] = va;
2625 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2626 S_008F04_STRIDE(stride);
2627 view->state[6] = num_records;
2628 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2629 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2630 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2631 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2632 S_008F0C_NUM_FORMAT(num_format) |
2633 S_008F0C_DATA_FORMAT(format);
2634
2635 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2636 return &view->base;
2637 }
2638
2639 state_swizzle[0] = state->swizzle_r;
2640 state_swizzle[1] = state->swizzle_g;
2641 state_swizzle[2] = state->swizzle_b;
2642 state_swizzle[3] = state->swizzle_a;
2643
2644 surflevel = tmp->surface.level;
2645
2646 /* Texturing with separate depth and stencil. */
2647 if (tmp->is_depth && !tmp->is_flushing_texture) {
2648 switch (pipe_format) {
2649 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2650 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2651 break;
2652 case PIPE_FORMAT_X8Z24_UNORM:
2653 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2654 /* Z24 is always stored like this. */
2655 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2656 break;
2657 case PIPE_FORMAT_X24S8_UINT:
2658 case PIPE_FORMAT_S8X24_UINT:
2659 case PIPE_FORMAT_X32_S8X24_UINT:
2660 pipe_format = PIPE_FORMAT_S8_UINT;
2661 surflevel = tmp->surface.stencil_level;
2662 break;
2663 default:;
2664 }
2665 }
2666
2667 desc = util_format_description(pipe_format);
2668
2669 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2670 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2671 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2672
2673 switch (pipe_format) {
2674 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2675 case PIPE_FORMAT_X24S8_UINT:
2676 case PIPE_FORMAT_X32_S8X24_UINT:
2677 case PIPE_FORMAT_X8Z24_UNORM:
2678 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2679 break;
2680 default:
2681 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2682 }
2683 } else {
2684 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2685 }
2686
2687 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2688
2689 switch (pipe_format) {
2690 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2691 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2692 break;
2693 default:
2694 if (first_non_void < 0) {
2695 if (util_format_is_compressed(pipe_format)) {
2696 switch (pipe_format) {
2697 case PIPE_FORMAT_DXT1_SRGB:
2698 case PIPE_FORMAT_DXT1_SRGBA:
2699 case PIPE_FORMAT_DXT3_SRGBA:
2700 case PIPE_FORMAT_DXT5_SRGBA:
2701 case PIPE_FORMAT_BPTC_SRGBA:
2702 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2703 break;
2704 case PIPE_FORMAT_RGTC1_SNORM:
2705 case PIPE_FORMAT_LATC1_SNORM:
2706 case PIPE_FORMAT_RGTC2_SNORM:
2707 case PIPE_FORMAT_LATC2_SNORM:
2708 /* implies float, so use SNORM/UNORM to determine
2709 whether data is signed or not */
2710 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2711 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2712 break;
2713 default:
2714 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2715 break;
2716 }
2717 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2718 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2719 } else {
2720 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2721 }
2722 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2723 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2724 } else {
2725 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2726
2727 switch (desc->channel[first_non_void].type) {
2728 case UTIL_FORMAT_TYPE_FLOAT:
2729 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2730 break;
2731 case UTIL_FORMAT_TYPE_SIGNED:
2732 if (desc->channel[first_non_void].normalized)
2733 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2734 else if (desc->channel[first_non_void].pure_integer)
2735 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2736 else
2737 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2738 break;
2739 case UTIL_FORMAT_TYPE_UNSIGNED:
2740 if (desc->channel[first_non_void].normalized)
2741 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2742 else if (desc->channel[first_non_void].pure_integer)
2743 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2744 else
2745 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2746 }
2747 }
2748 }
2749
2750 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2751 if (format == ~0) {
2752 format = 0;
2753 }
2754
2755 base_level = 0;
2756 first_level = state->u.tex.first_level;
2757 last_level = state->u.tex.last_level;
2758 width = width0;
2759 height = height0;
2760 depth = texture->depth0;
2761
2762 if (force_level) {
2763 assert(force_level == first_level &&
2764 force_level == last_level);
2765 base_level = force_level;
2766 first_level = 0;
2767 last_level = 0;
2768 width = u_minify(width, force_level);
2769 height = u_minify(height, force_level);
2770 depth = u_minify(depth, force_level);
2771 }
2772
2773 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2774
2775 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2776 height = 1;
2777 depth = texture->array_size;
2778 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2779 depth = texture->array_size;
2780 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2781 depth = texture->array_size / 6;
2782
2783 /* This is not needed if state trackers set last_layer correctly. */
2784 if (state->target == PIPE_TEXTURE_1D ||
2785 state->target == PIPE_TEXTURE_2D ||
2786 state->target == PIPE_TEXTURE_RECT ||
2787 state->target == PIPE_TEXTURE_CUBE)
2788 last_layer = state->u.tex.first_layer;
2789
2790 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2791
2792 view->state[0] = va >> 8;
2793 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2794 S_008F14_DATA_FORMAT(format) |
2795 S_008F14_NUM_FORMAT(num_format));
2796 view->state[2] = (S_008F18_WIDTH(width - 1) |
2797 S_008F18_HEIGHT(height - 1));
2798 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2799 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2800 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2801 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2802 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2803 0 : first_level) |
2804 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2805 util_logbase2(texture->nr_samples) :
2806 last_level) |
2807 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2808 S_008F1C_POW2_PAD(texture->last_level > 0) |
2809 S_008F1C_TYPE(si_tex_dim(texture->target, state->target,
2810 texture->nr_samples)));
2811 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2812 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2813 S_008F24_LAST_ARRAY(last_layer));
2814
2815 if (tmp->dcc_buffer) {
2816 uint64_t dcc_offset = surflevel[base_level].dcc_offset;
2817 unsigned swap = r600_translate_colorswap(pipe_format);
2818
2819 view->state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2820 view->state[7] = (tmp->dcc_buffer->gpu_address + dcc_offset) >> 8;
2821 view->dcc_buffer = tmp->dcc_buffer;
2822 } else {
2823 view->state[6] = 0;
2824 view->state[7] = 0;
2825 }
2826
2827 /* Initialize the sampler view for FMASK. */
2828 if (tmp->fmask.size) {
2829 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2830 uint32_t fmask_format;
2831
2832 switch (texture->nr_samples) {
2833 case 2:
2834 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2835 break;
2836 case 4:
2837 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2838 break;
2839 case 8:
2840 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2841 break;
2842 default:
2843 assert(0);
2844 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2845 }
2846
2847 view->fmask_state[0] = va >> 8;
2848 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2849 S_008F14_DATA_FORMAT(fmask_format) |
2850 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2851 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2852 S_008F18_HEIGHT(height - 1);
2853 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2854 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2855 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2856 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2857 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2858 S_008F1C_TYPE(si_tex_dim(texture->target,
2859 state->target, 0));
2860 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2861 S_008F20_PITCH(tmp->fmask.pitch_in_pixels - 1);
2862 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2863 S_008F24_LAST_ARRAY(last_layer);
2864 view->fmask_state[6] = 0;
2865 view->fmask_state[7] = 0;
2866 }
2867
2868 return &view->base;
2869 }
2870
2871 static struct pipe_sampler_view *
2872 si_create_sampler_view(struct pipe_context *ctx,
2873 struct pipe_resource *texture,
2874 const struct pipe_sampler_view *state)
2875 {
2876 return si_create_sampler_view_custom(ctx, texture, state,
2877 texture ? texture->width0 : 0,
2878 texture ? texture->height0 : 0, 0);
2879 }
2880
2881 static void si_sampler_view_destroy(struct pipe_context *ctx,
2882 struct pipe_sampler_view *state)
2883 {
2884 struct si_sampler_view *view = (struct si_sampler_view *)state;
2885
2886 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2887 LIST_DELINIT(&view->list);
2888
2889 pipe_resource_reference(&state->texture, NULL);
2890 FREE(view);
2891 }
2892
2893 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2894 {
2895 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2896 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2897 (linear_filter &&
2898 (wrap == PIPE_TEX_WRAP_CLAMP ||
2899 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2900 }
2901
2902 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2903 {
2904 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2905 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2906
2907 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2908 state->border_color.ui[2] || state->border_color.ui[3]) &&
2909 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2910 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2911 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2912 }
2913
2914 static void *si_create_sampler_state(struct pipe_context *ctx,
2915 const struct pipe_sampler_state *state)
2916 {
2917 struct si_context *sctx = (struct si_context *)ctx;
2918 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2919 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2920 unsigned border_color_type, border_color_index = 0;
2921
2922 if (!rstate) {
2923 return NULL;
2924 }
2925
2926 if (!sampler_state_needs_border_color(state))
2927 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2928 else if (state->border_color.f[0] == 0 &&
2929 state->border_color.f[1] == 0 &&
2930 state->border_color.f[2] == 0 &&
2931 state->border_color.f[3] == 0)
2932 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2933 else if (state->border_color.f[0] == 0 &&
2934 state->border_color.f[1] == 0 &&
2935 state->border_color.f[2] == 0 &&
2936 state->border_color.f[3] == 1)
2937 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2938 else if (state->border_color.f[0] == 1 &&
2939 state->border_color.f[1] == 1 &&
2940 state->border_color.f[2] == 1 &&
2941 state->border_color.f[3] == 1)
2942 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2943 else {
2944 int i;
2945
2946 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2947
2948 /* Check if the border has been uploaded already. */
2949 for (i = 0; i < sctx->border_color_count; i++)
2950 if (memcmp(&sctx->border_color_table[i], &state->border_color,
2951 sizeof(state->border_color)) == 0)
2952 break;
2953
2954 if (i >= SI_MAX_BORDER_COLORS) {
2955 /* Getting 4096 unique border colors is very unlikely. */
2956 fprintf(stderr, "radeonsi: The border color table is full. "
2957 "Any new border colors will be just black. "
2958 "Please file a bug.\n");
2959 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2960 } else {
2961 if (i == sctx->border_color_count) {
2962 /* Upload a new border color. */
2963 memcpy(&sctx->border_color_table[i], &state->border_color,
2964 sizeof(state->border_color));
2965 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
2966 &state->border_color,
2967 sizeof(state->border_color));
2968 sctx->border_color_count++;
2969 }
2970
2971 border_color_index = i;
2972 }
2973 }
2974
2975 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2976 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2977 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2978 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2979 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2980 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2981 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2982 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2983 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2984 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2985 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2986 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2987 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2988 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
2989 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2990 return rstate;
2991 }
2992
2993 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2994 {
2995 struct si_context *sctx = (struct si_context *)ctx;
2996
2997 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2998 return;
2999
3000 sctx->sample_mask.sample_mask = sample_mask;
3001 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3002 }
3003
3004 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3005 {
3006 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3007 unsigned mask = sctx->sample_mask.sample_mask;
3008
3009 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3010 radeon_emit(cs, mask | (mask << 16));
3011 radeon_emit(cs, mask | (mask << 16));
3012 }
3013
3014 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3015 {
3016 free(state);
3017 }
3018
3019 /*
3020 * Vertex elements & buffers
3021 */
3022
3023 static void *si_create_vertex_elements(struct pipe_context *ctx,
3024 unsigned count,
3025 const struct pipe_vertex_element *elements)
3026 {
3027 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3028 int i;
3029
3030 assert(count < SI_MAX_ATTRIBS);
3031 if (!v)
3032 return NULL;
3033
3034 v->count = count;
3035 for (i = 0; i < count; ++i) {
3036 const struct util_format_description *desc;
3037 unsigned data_format, num_format;
3038 int first_non_void;
3039
3040 desc = util_format_description(elements[i].src_format);
3041 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3042 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3043 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3044
3045 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3046 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3047 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3048 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3049 S_008F0C_NUM_FORMAT(num_format) |
3050 S_008F0C_DATA_FORMAT(data_format);
3051 v->format_size[i] = desc->block.bits / 8;
3052 }
3053 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3054
3055 return v;
3056 }
3057
3058 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3059 {
3060 struct si_context *sctx = (struct si_context *)ctx;
3061 struct si_vertex_element *v = (struct si_vertex_element*)state;
3062
3063 sctx->vertex_elements = v;
3064 sctx->vertex_buffers_dirty = true;
3065 }
3066
3067 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3068 {
3069 struct si_context *sctx = (struct si_context *)ctx;
3070
3071 if (sctx->vertex_elements == state)
3072 sctx->vertex_elements = NULL;
3073 FREE(state);
3074 }
3075
3076 static void si_set_vertex_buffers(struct pipe_context *ctx,
3077 unsigned start_slot, unsigned count,
3078 const struct pipe_vertex_buffer *buffers)
3079 {
3080 struct si_context *sctx = (struct si_context *)ctx;
3081 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3082 int i;
3083
3084 assert(start_slot + count <= Elements(sctx->vertex_buffer));
3085
3086 if (buffers) {
3087 for (i = 0; i < count; i++) {
3088 const struct pipe_vertex_buffer *src = buffers + i;
3089 struct pipe_vertex_buffer *dsti = dst + i;
3090
3091 pipe_resource_reference(&dsti->buffer, src->buffer);
3092 dsti->buffer_offset = src->buffer_offset;
3093 dsti->stride = src->stride;
3094 r600_context_add_resource_size(ctx, src->buffer);
3095 }
3096 } else {
3097 for (i = 0; i < count; i++) {
3098 pipe_resource_reference(&dst[i].buffer, NULL);
3099 }
3100 }
3101 sctx->vertex_buffers_dirty = true;
3102 }
3103
3104 static void si_set_index_buffer(struct pipe_context *ctx,
3105 const struct pipe_index_buffer *ib)
3106 {
3107 struct si_context *sctx = (struct si_context *)ctx;
3108
3109 if (ib) {
3110 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3111 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3112 r600_context_add_resource_size(ctx, ib->buffer);
3113 } else {
3114 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3115 }
3116 }
3117
3118 /*
3119 * Misc
3120 */
3121 static void si_set_polygon_stipple(struct pipe_context *ctx,
3122 const struct pipe_poly_stipple *state)
3123 {
3124 struct si_context *sctx = (struct si_context *)ctx;
3125 struct pipe_resource *tex;
3126 struct pipe_sampler_view *view;
3127 bool is_zero = true;
3128 bool is_one = true;
3129 int i;
3130
3131 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3132 * the resource is NULL/invalid. Take advantage of this fact and skip
3133 * texture allocation if the stipple pattern is constant.
3134 *
3135 * This is an optimization for the common case when stippling isn't
3136 * used but set_polygon_stipple is still called by st/mesa.
3137 */
3138 for (i = 0; i < Elements(state->stipple); i++) {
3139 is_zero = is_zero && state->stipple[i] == 0;
3140 is_one = is_one && state->stipple[i] == 0xffffffff;
3141 }
3142
3143 if (is_zero || is_one) {
3144 struct pipe_sampler_view templ = {{0}};
3145
3146 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
3147 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
3148 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
3149 /* The pattern should be inverted in the texture. */
3150 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
3151
3152 view = ctx->create_sampler_view(ctx, NULL, &templ);
3153 } else {
3154 /* Create a new texture. */
3155 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
3156 if (!tex)
3157 return;
3158
3159 view = util_pstipple_create_sampler_view(ctx, tex);
3160 pipe_resource_reference(&tex, NULL);
3161 }
3162
3163 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
3164 SI_POLY_STIPPLE_SAMPLER, 1, &view);
3165 pipe_sampler_view_reference(&view, NULL);
3166
3167 /* Bind the sampler state if needed. */
3168 if (!sctx->pstipple_sampler_state) {
3169 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
3170 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
3171 SI_POLY_STIPPLE_SAMPLER, 1,
3172 &sctx->pstipple_sampler_state);
3173 }
3174 }
3175
3176 static void si_set_tess_state(struct pipe_context *ctx,
3177 const float default_outer_level[4],
3178 const float default_inner_level[2])
3179 {
3180 struct si_context *sctx = (struct si_context *)ctx;
3181 struct pipe_constant_buffer cb;
3182 float array[8];
3183
3184 memcpy(array, default_outer_level, sizeof(float) * 4);
3185 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3186
3187 cb.buffer = NULL;
3188 cb.user_buffer = NULL;
3189 cb.buffer_size = sizeof(array);
3190
3191 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3192 (void*)array, sizeof(array),
3193 &cb.buffer_offset);
3194
3195 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
3196 SI_DRIVER_STATE_CONST_BUF, &cb);
3197 pipe_resource_reference(&cb.buffer, NULL);
3198 }
3199
3200 static void si_texture_barrier(struct pipe_context *ctx)
3201 {
3202 struct si_context *sctx = (struct si_context *)ctx;
3203
3204 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3205 SI_CONTEXT_INV_GLOBAL_L2 |
3206 SI_CONTEXT_FLUSH_AND_INV_CB;
3207 }
3208
3209 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3210 {
3211 struct pipe_blend_state blend;
3212
3213 memset(&blend, 0, sizeof(blend));
3214 blend.independent_blend_enable = true;
3215 blend.rt[0].colormask = 0xf;
3216 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3217 }
3218
3219 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3220 bool include_draw_vbo)
3221 {
3222 si_need_cs_space((struct si_context*)ctx);
3223 }
3224
3225 static void si_init_config(struct si_context *sctx);
3226
3227 void si_init_state_functions(struct si_context *sctx)
3228 {
3229 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3230 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3231 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3232
3233 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3234 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3235 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3236 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3237 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3238 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3239 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3240 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3241 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3242 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3243 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3244 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3245 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3246
3247 sctx->b.b.create_blend_state = si_create_blend_state;
3248 sctx->b.b.bind_blend_state = si_bind_blend_state;
3249 sctx->b.b.delete_blend_state = si_delete_blend_state;
3250 sctx->b.b.set_blend_color = si_set_blend_color;
3251
3252 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3253 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3254 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3255
3256 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3257 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3258 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3259
3260 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3261 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3262 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3263 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3264
3265 sctx->b.b.set_clip_state = si_set_clip_state;
3266 sctx->b.b.set_scissor_states = si_set_scissor_states;
3267 sctx->b.b.set_viewport_states = si_set_viewport_states;
3268 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3269
3270 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3271 sctx->b.b.get_sample_position = cayman_get_sample_position;
3272
3273 sctx->b.b.create_sampler_state = si_create_sampler_state;
3274 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3275
3276 sctx->b.b.create_sampler_view = si_create_sampler_view;
3277 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3278
3279 sctx->b.b.set_sample_mask = si_set_sample_mask;
3280
3281 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3282 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3283 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3284 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3285 sctx->b.b.set_index_buffer = si_set_index_buffer;
3286
3287 sctx->b.b.texture_barrier = si_texture_barrier;
3288 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3289 sctx->b.b.set_min_samples = si_set_min_samples;
3290 sctx->b.b.set_tess_state = si_set_tess_state;
3291
3292 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3293 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3294
3295 sctx->b.b.draw_vbo = si_draw_vbo;
3296
3297 if (sctx->b.chip_class >= CIK) {
3298 sctx->b.dma_copy = cik_sdma_copy;
3299 } else {
3300 sctx->b.dma_copy = si_dma_copy;
3301 }
3302
3303 si_init_config(sctx);
3304 }
3305
3306 static void
3307 si_write_harvested_raster_configs(struct si_context *sctx,
3308 struct si_pm4_state *pm4,
3309 unsigned raster_config,
3310 unsigned raster_config_1)
3311 {
3312 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3313 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3314 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3315 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3316 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3317 unsigned rb_per_se = num_rb / num_se;
3318 unsigned se_mask[4];
3319 unsigned se;
3320
3321 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3322 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3323 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3324 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3325
3326 assert(num_se == 1 || num_se == 2 || num_se == 4);
3327 assert(sh_per_se == 1 || sh_per_se == 2);
3328 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3329
3330 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3331 * fields are for, so I'm leaving them as their default
3332 * values. */
3333
3334 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3335 (!se_mask[2] && !se_mask[3]))) {
3336 raster_config_1 &= C_028354_SE_PAIR_MAP;
3337
3338 if (!se_mask[0] && !se_mask[1]) {
3339 raster_config_1 |=
3340 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3341 } else {
3342 raster_config_1 |=
3343 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3344 }
3345 }
3346
3347 for (se = 0; se < num_se; se++) {
3348 unsigned raster_config_se = raster_config;
3349 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3350 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3351 int idx = (se / 2) * 2;
3352
3353 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3354 raster_config_se &= C_028350_SE_MAP;
3355
3356 if (!se_mask[idx]) {
3357 raster_config_se |=
3358 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3359 } else {
3360 raster_config_se |=
3361 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3362 }
3363 }
3364
3365 pkr0_mask &= rb_mask;
3366 pkr1_mask &= rb_mask;
3367 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3368 raster_config_se &= C_028350_PKR_MAP;
3369
3370 if (!pkr0_mask) {
3371 raster_config_se |=
3372 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3373 } else {
3374 raster_config_se |=
3375 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3376 }
3377 }
3378
3379 if (rb_per_se >= 2) {
3380 unsigned rb0_mask = 1 << (se * rb_per_se);
3381 unsigned rb1_mask = rb0_mask << 1;
3382
3383 rb0_mask &= rb_mask;
3384 rb1_mask &= rb_mask;
3385 if (!rb0_mask || !rb1_mask) {
3386 raster_config_se &= C_028350_RB_MAP_PKR0;
3387
3388 if (!rb0_mask) {
3389 raster_config_se |=
3390 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3391 } else {
3392 raster_config_se |=
3393 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3394 }
3395 }
3396
3397 if (rb_per_se > 2) {
3398 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3399 rb1_mask = rb0_mask << 1;
3400 rb0_mask &= rb_mask;
3401 rb1_mask &= rb_mask;
3402 if (!rb0_mask || !rb1_mask) {
3403 raster_config_se &= C_028350_RB_MAP_PKR1;
3404
3405 if (!rb0_mask) {
3406 raster_config_se |=
3407 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3408 } else {
3409 raster_config_se |=
3410 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3411 }
3412 }
3413 }
3414 }
3415
3416 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3417 if (sctx->b.chip_class < CIK)
3418 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3419 SE_INDEX(se) | SH_BROADCAST_WRITES |
3420 INSTANCE_BROADCAST_WRITES);
3421 else
3422 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3423 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3424 S_030800_INSTANCE_BROADCAST_WRITES(1));
3425 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3426 if (sctx->b.chip_class >= CIK)
3427 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3428 }
3429
3430 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3431 if (sctx->b.chip_class < CIK)
3432 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3433 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3434 INSTANCE_BROADCAST_WRITES);
3435 else
3436 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3437 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3438 S_030800_INSTANCE_BROADCAST_WRITES(1));
3439 }
3440
3441 static void si_init_config(struct si_context *sctx)
3442 {
3443 struct si_screen *sscreen = sctx->screen;
3444 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3445 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3446 unsigned raster_config, raster_config_1;
3447 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3448 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3449 int i;
3450
3451 if (!pm4)
3452 return;
3453
3454 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3455 si_pm4_cmd_add(pm4, 0x80000000);
3456 si_pm4_cmd_add(pm4, 0x80000000);
3457 si_pm4_cmd_end(pm4, false);
3458
3459 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3460 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3461
3462 /* FIXME calculate these values somehow ??? */
3463 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3464 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3465 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3466
3467 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3468 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3469
3470 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3471 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3472 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3473 if (sctx->b.chip_class < CIK)
3474 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3475 S_008A14_CLIP_VTX_REORDER_ENA(1));
3476
3477 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3478 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3479
3480 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3481
3482 for (i = 0; i < 16; i++) {
3483 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3484 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3485 }
3486
3487 switch (sctx->screen->b.family) {
3488 case CHIP_TAHITI:
3489 case CHIP_PITCAIRN:
3490 raster_config = 0x2a00126a;
3491 raster_config_1 = 0x00000000;
3492 break;
3493 case CHIP_VERDE:
3494 raster_config = 0x0000124a;
3495 raster_config_1 = 0x00000000;
3496 break;
3497 case CHIP_OLAND:
3498 raster_config = 0x00000082;
3499 raster_config_1 = 0x00000000;
3500 break;
3501 case CHIP_HAINAN:
3502 raster_config = 0x00000000;
3503 raster_config_1 = 0x00000000;
3504 break;
3505 case CHIP_BONAIRE:
3506 raster_config = 0x16000012;
3507 raster_config_1 = 0x00000000;
3508 break;
3509 case CHIP_HAWAII:
3510 raster_config = 0x3a00161a;
3511 raster_config_1 = 0x0000002e;
3512 break;
3513 case CHIP_FIJI:
3514 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3515 /* old kernels with old tiling config */
3516 raster_config = 0x16000012;
3517 raster_config_1 = 0x0000002a;
3518 } else {
3519 raster_config = 0x3a00161a;
3520 raster_config_1 = 0x0000002e;
3521 }
3522 break;
3523 case CHIP_TONGA:
3524 raster_config = 0x16000012;
3525 raster_config_1 = 0x0000002a;
3526 break;
3527 case CHIP_ICELAND:
3528 raster_config = 0x00000002;
3529 raster_config_1 = 0x00000000;
3530 break;
3531 case CHIP_CARRIZO:
3532 raster_config = 0x00000002;
3533 raster_config_1 = 0x00000000;
3534 break;
3535 case CHIP_KAVERI:
3536 /* KV should be 0x00000002, but that causes problems with radeon */
3537 raster_config = 0x00000000; /* 0x00000002 */
3538 raster_config_1 = 0x00000000;
3539 break;
3540 case CHIP_KABINI:
3541 case CHIP_MULLINS:
3542 case CHIP_STONEY:
3543 raster_config = 0x00000000;
3544 raster_config_1 = 0x00000000;
3545 break;
3546 default:
3547 fprintf(stderr,
3548 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3549 raster_config = 0x00000000;
3550 raster_config_1 = 0x00000000;
3551 break;
3552 }
3553
3554 /* Always use the default config when all backends are enabled
3555 * (or when we failed to determine the enabled backends).
3556 */
3557 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3558 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3559 raster_config);
3560 if (sctx->b.chip_class >= CIK)
3561 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3562 raster_config_1);
3563 } else {
3564 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3565 }
3566
3567 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3568 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3569 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3570 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3571 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3572 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3573 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3574
3575 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3576 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3577 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3578 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3579 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3580 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3581 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3582 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3583 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3584 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3585 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3586 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3587 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3588 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3589 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3590
3591 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3592 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3593 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3594
3595 if (sctx->b.chip_class >= CIK) {
3596 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3597 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3598 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3599 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3600 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3601 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3602 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3603 }
3604
3605 if (sctx->b.chip_class >= VI) {
3606 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3607 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3608 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3609 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3610 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3611 }
3612
3613 if (sctx->b.family == CHIP_STONEY)
3614 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3615
3616 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3617 if (sctx->b.chip_class >= CIK)
3618 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3619 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3620 RADEON_PRIO_BORDER_COLORS);
3621
3622 si_pm4_upload_indirect_buffer(sctx, pm4);
3623 sctx->init_config = pm4;
3624 }