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radeonsi: enable dithered alpha-to-coverage for better quality
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
92 * I think we don't have to do anything between IBs.
93 */
94 if (sctx->screen->dfsm_allowed &&
95 sctx->last_cb_target_mask != cb_target_mask) {
96 sctx->last_cb_target_mask = cb_target_mask;
97
98 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
99 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
100 }
101
102 unsigned initial_cdw = cs->current.cdw;
103 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
104 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
105
106 if (sctx->chip_class >= VI) {
107 /* DCC MSAA workaround for blending.
108 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
109 * COMBINER_DISABLE, but that would be more complicated.
110 */
111 bool oc_disable = (sctx->chip_class == VI ||
112 sctx->chip_class == GFX9) &&
113 blend &&
114 blend->blend_enable_4bit & cb_target_mask &&
115 sctx->framebuffer.nr_samples >= 2;
116 unsigned watermark = sctx->framebuffer.dcc_overwrite_combiner_watermark;
117
118 radeon_opt_set_context_reg(
119 sctx, R_028424_CB_DCC_CONTROL,
120 SI_TRACKED_CB_DCC_CONTROL,
121 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
122 S_028424_OVERWRITE_COMBINER_WATERMARK(watermark) |
123 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable) |
124 S_028424_DISABLE_CONSTANT_ENCODE_REG(sctx->screen->has_dcc_constant_encode));
125 }
126
127 /* RB+ register settings. */
128 if (sctx->screen->rbplus_allowed) {
129 unsigned spi_shader_col_format =
130 sctx->ps_shader.cso ?
131 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
132 unsigned sx_ps_downconvert = 0;
133 unsigned sx_blend_opt_epsilon = 0;
134 unsigned sx_blend_opt_control = 0;
135
136 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
137 struct si_surface *surf =
138 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
139 unsigned format, swap, spi_format, colormask;
140 bool has_alpha, has_rgb;
141
142 if (!surf)
143 continue;
144
145 format = G_028C70_FORMAT(surf->cb_color_info);
146 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
147 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
148 colormask = (cb_target_mask >> (i * 4)) & 0xf;
149
150 /* Set if RGB and A are present. */
151 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
152
153 if (format == V_028C70_COLOR_8 ||
154 format == V_028C70_COLOR_16 ||
155 format == V_028C70_COLOR_32)
156 has_rgb = !has_alpha;
157 else
158 has_rgb = true;
159
160 /* Check the colormask and export format. */
161 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
162 has_rgb = false;
163 if (!(colormask & PIPE_MASK_A))
164 has_alpha = false;
165
166 if (spi_format == V_028714_SPI_SHADER_ZERO) {
167 has_rgb = false;
168 has_alpha = false;
169 }
170
171 /* Disable value checking for disabled channels. */
172 if (!has_rgb)
173 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
174 if (!has_alpha)
175 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
176
177 /* Enable down-conversion for 32bpp and smaller formats. */
178 switch (format) {
179 case V_028C70_COLOR_8:
180 case V_028C70_COLOR_8_8:
181 case V_028C70_COLOR_8_8_8_8:
182 /* For 1 and 2-channel formats, use the superset thereof. */
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
185 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
186 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
187 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
188 }
189 break;
190
191 case V_028C70_COLOR_5_6_5:
192 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
193 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
194 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
195 }
196 break;
197
198 case V_028C70_COLOR_1_5_5_5:
199 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
200 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
201 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
202 }
203 break;
204
205 case V_028C70_COLOR_4_4_4_4:
206 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
207 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
208 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
209 }
210 break;
211
212 case V_028C70_COLOR_32:
213 if (swap == V_028C70_SWAP_STD &&
214 spi_format == V_028714_SPI_SHADER_32_R)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
216 else if (swap == V_028C70_SWAP_ALT_REV &&
217 spi_format == V_028714_SPI_SHADER_32_AR)
218 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
219 break;
220
221 case V_028C70_COLOR_16:
222 case V_028C70_COLOR_16_16:
223 /* For 1-channel formats, use the superset thereof. */
224 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
227 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
228 if (swap == V_028C70_SWAP_STD ||
229 swap == V_028C70_SWAP_STD_REV)
230 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
231 else
232 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
233 }
234 break;
235
236 case V_028C70_COLOR_10_11_11:
237 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
238 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
239 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
240 }
241 break;
242
243 case V_028C70_COLOR_2_10_10_10:
244 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
246 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
247 }
248 break;
249 }
250 }
251
252 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
253 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
254 SI_TRACKED_SX_PS_DOWNCONVERT,
255 sx_ps_downconvert, sx_blend_opt_epsilon,
256 sx_blend_opt_control);
257 }
258 if (initial_cdw != cs->current.cdw)
259 sctx->context_roll_counter++;
260 }
261
262 /*
263 * Blender functions
264 */
265
266 static uint32_t si_translate_blend_function(int blend_func)
267 {
268 switch (blend_func) {
269 case PIPE_BLEND_ADD:
270 return V_028780_COMB_DST_PLUS_SRC;
271 case PIPE_BLEND_SUBTRACT:
272 return V_028780_COMB_SRC_MINUS_DST;
273 case PIPE_BLEND_REVERSE_SUBTRACT:
274 return V_028780_COMB_DST_MINUS_SRC;
275 case PIPE_BLEND_MIN:
276 return V_028780_COMB_MIN_DST_SRC;
277 case PIPE_BLEND_MAX:
278 return V_028780_COMB_MAX_DST_SRC;
279 default:
280 PRINT_ERR("Unknown blend function %d\n", blend_func);
281 assert(0);
282 break;
283 }
284 return 0;
285 }
286
287 static uint32_t si_translate_blend_factor(int blend_fact)
288 {
289 switch (blend_fact) {
290 case PIPE_BLENDFACTOR_ONE:
291 return V_028780_BLEND_ONE;
292 case PIPE_BLENDFACTOR_SRC_COLOR:
293 return V_028780_BLEND_SRC_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA:
295 return V_028780_BLEND_SRC_ALPHA;
296 case PIPE_BLENDFACTOR_DST_ALPHA:
297 return V_028780_BLEND_DST_ALPHA;
298 case PIPE_BLENDFACTOR_DST_COLOR:
299 return V_028780_BLEND_DST_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
301 return V_028780_BLEND_SRC_ALPHA_SATURATE;
302 case PIPE_BLENDFACTOR_CONST_COLOR:
303 return V_028780_BLEND_CONSTANT_COLOR;
304 case PIPE_BLENDFACTOR_CONST_ALPHA:
305 return V_028780_BLEND_CONSTANT_ALPHA;
306 case PIPE_BLENDFACTOR_ZERO:
307 return V_028780_BLEND_ZERO;
308 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
309 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
310 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
311 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
312 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_COLOR:
315 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
316 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
320 case PIPE_BLENDFACTOR_SRC1_COLOR:
321 return V_028780_BLEND_SRC1_COLOR;
322 case PIPE_BLENDFACTOR_SRC1_ALPHA:
323 return V_028780_BLEND_SRC1_ALPHA;
324 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
325 return V_028780_BLEND_INV_SRC1_COLOR;
326 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
327 return V_028780_BLEND_INV_SRC1_ALPHA;
328 default:
329 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
330 assert(0);
331 break;
332 }
333 return 0;
334 }
335
336 static uint32_t si_translate_blend_opt_function(int blend_func)
337 {
338 switch (blend_func) {
339 case PIPE_BLEND_ADD:
340 return V_028760_OPT_COMB_ADD;
341 case PIPE_BLEND_SUBTRACT:
342 return V_028760_OPT_COMB_SUBTRACT;
343 case PIPE_BLEND_REVERSE_SUBTRACT:
344 return V_028760_OPT_COMB_REVSUBTRACT;
345 case PIPE_BLEND_MIN:
346 return V_028760_OPT_COMB_MIN;
347 case PIPE_BLEND_MAX:
348 return V_028760_OPT_COMB_MAX;
349 default:
350 return V_028760_OPT_COMB_BLEND_DISABLED;
351 }
352 }
353
354 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
355 {
356 switch (blend_fact) {
357 case PIPE_BLENDFACTOR_ZERO:
358 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
359 case PIPE_BLENDFACTOR_ONE:
360 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
361 case PIPE_BLENDFACTOR_SRC_COLOR:
362 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
363 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
364 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
365 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
366 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
367 case PIPE_BLENDFACTOR_SRC_ALPHA:
368 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
369 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
371 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
372 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
373 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
374 default:
375 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
376 }
377 }
378
379 static void si_blend_check_commutativity(struct si_screen *sscreen,
380 struct si_state_blend *blend,
381 enum pipe_blend_func func,
382 enum pipe_blendfactor src,
383 enum pipe_blendfactor dst,
384 unsigned chanmask)
385 {
386 /* Src factor is allowed when it does not depend on Dst */
387 static const uint32_t src_allowed =
388 (1u << PIPE_BLENDFACTOR_ONE) |
389 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
392 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
393 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
395 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_ZERO) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
398 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
399 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
400 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
401 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
402 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
403
404 if (dst == PIPE_BLENDFACTOR_ONE &&
405 (src_allowed & (1u << src))) {
406 /* Addition is commutative, but floating point addition isn't
407 * associative: subtle changes can be introduced via different
408 * rounding.
409 *
410 * Out-of-order is also non-deterministic, which means that
411 * this breaks OpenGL invariance requirements. So only enable
412 * out-of-order additive blending if explicitly allowed by a
413 * setting.
414 */
415 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
416 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
417 blend->commutative_4bit |= chanmask;
418 }
419 }
420
421 /**
422 * Get rid of DST in the blend factors by commuting the operands:
423 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
424 */
425 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
426 unsigned *dst_factor, unsigned expected_dst,
427 unsigned replacement_src)
428 {
429 if (*src_factor == expected_dst &&
430 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
431 *src_factor = PIPE_BLENDFACTOR_ZERO;
432 *dst_factor = replacement_src;
433
434 /* Commuting the operands requires reversing subtractions. */
435 if (*func == PIPE_BLEND_SUBTRACT)
436 *func = PIPE_BLEND_REVERSE_SUBTRACT;
437 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
438 *func = PIPE_BLEND_SUBTRACT;
439 }
440 }
441
442 static bool si_blend_factor_uses_dst(unsigned factor)
443 {
444 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
445 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
446 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
447 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
448 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
449 }
450
451 static void *si_create_blend_state_mode(struct pipe_context *ctx,
452 const struct pipe_blend_state *state,
453 unsigned mode)
454 {
455 struct si_context *sctx = (struct si_context*)ctx;
456 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
457 struct si_pm4_state *pm4 = &blend->pm4;
458 uint32_t sx_mrt_blend_opt[8] = {0};
459 uint32_t color_control = 0;
460
461 if (!blend)
462 return NULL;
463
464 blend->alpha_to_coverage = state->alpha_to_coverage;
465 blend->alpha_to_one = state->alpha_to_one;
466 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
467 blend->logicop_enable = state->logicop_enable;
468
469 if (state->logicop_enable) {
470 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
471 } else {
472 color_control |= S_028808_ROP3(0xcc);
473 }
474
475 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
476 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
477 S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
478 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
479 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
480 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
481 S_028B70_OFFSET_ROUND(1));
482
483 if (state->alpha_to_coverage)
484 blend->need_src_alpha_4bit |= 0xf;
485
486 blend->cb_target_mask = 0;
487 blend->cb_target_enabled_4bit = 0;
488
489 for (int i = 0; i < 8; i++) {
490 /* state->rt entries > 0 only written if independent blending */
491 const int j = state->independent_blend_enable ? i : 0;
492
493 unsigned eqRGB = state->rt[j].rgb_func;
494 unsigned srcRGB = state->rt[j].rgb_src_factor;
495 unsigned dstRGB = state->rt[j].rgb_dst_factor;
496 unsigned eqA = state->rt[j].alpha_func;
497 unsigned srcA = state->rt[j].alpha_src_factor;
498 unsigned dstA = state->rt[j].alpha_dst_factor;
499
500 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
501 unsigned blend_cntl = 0;
502
503 sx_mrt_blend_opt[i] =
504 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
505 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
506
507 /* Only set dual source blending for MRT0 to avoid a hang. */
508 if (i >= 1 && blend->dual_src_blend) {
509 /* Vulkan does this for dual source blending. */
510 if (i == 1)
511 blend_cntl |= S_028780_ENABLE(1);
512
513 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
514 continue;
515 }
516
517 /* Only addition and subtraction equations are supported with
518 * dual source blending.
519 */
520 if (blend->dual_src_blend &&
521 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
522 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
523 assert(!"Unsupported equation for dual source blending");
524 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
525 continue;
526 }
527
528 /* cb_render_state will disable unused ones */
529 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
530 if (state->rt[j].colormask)
531 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
532
533 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
534 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
535 continue;
536 }
537
538 si_blend_check_commutativity(sctx->screen, blend,
539 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
540 si_blend_check_commutativity(sctx->screen, blend,
541 eqA, srcA, dstA, 0x8 << (4 * i));
542
543 /* Blending optimizations for RB+.
544 * These transformations don't change the behavior.
545 *
546 * First, get rid of DST in the blend factors:
547 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
548 */
549 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
550 PIPE_BLENDFACTOR_DST_COLOR,
551 PIPE_BLENDFACTOR_SRC_COLOR);
552 si_blend_remove_dst(&eqA, &srcA, &dstA,
553 PIPE_BLENDFACTOR_DST_COLOR,
554 PIPE_BLENDFACTOR_SRC_COLOR);
555 si_blend_remove_dst(&eqA, &srcA, &dstA,
556 PIPE_BLENDFACTOR_DST_ALPHA,
557 PIPE_BLENDFACTOR_SRC_ALPHA);
558
559 /* Look up the ideal settings from tables. */
560 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
561 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
562 srcA_opt = si_translate_blend_opt_factor(srcA, true);
563 dstA_opt = si_translate_blend_opt_factor(dstA, true);
564
565 /* Handle interdependencies. */
566 if (si_blend_factor_uses_dst(srcRGB))
567 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
568 if (si_blend_factor_uses_dst(srcA))
569 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
570
571 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
572 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
573 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
574 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
575 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
576
577 /* Set the final value. */
578 sx_mrt_blend_opt[i] =
579 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
580 S_028760_COLOR_DST_OPT(dstRGB_opt) |
581 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
582 S_028760_ALPHA_SRC_OPT(srcA_opt) |
583 S_028760_ALPHA_DST_OPT(dstA_opt) |
584 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
585
586 /* Set blend state. */
587 blend_cntl |= S_028780_ENABLE(1);
588 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
589 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
590 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
591
592 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
593 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
594 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
595 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
596 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
597 }
598 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
599
600 blend->blend_enable_4bit |= 0xfu << (i * 4);
601
602 /* This is only important for formats without alpha. */
603 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
604 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
605 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
606 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
607 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
608 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
609 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
610 }
611
612 if (blend->cb_target_mask) {
613 color_control |= S_028808_MODE(mode);
614 } else {
615 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
616 }
617
618 if (sctx->screen->rbplus_allowed) {
619 /* Disable RB+ blend optimizations for dual source blending.
620 * Vulkan does this.
621 */
622 if (blend->dual_src_blend) {
623 for (int i = 0; i < 8; i++) {
624 sx_mrt_blend_opt[i] =
625 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
626 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
627 }
628 }
629
630 for (int i = 0; i < 8; i++)
631 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
632 sx_mrt_blend_opt[i]);
633
634 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
635 if (blend->dual_src_blend || state->logicop_enable ||
636 mode == V_028808_CB_RESOLVE)
637 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
638 }
639
640 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
641 return blend;
642 }
643
644 static void *si_create_blend_state(struct pipe_context *ctx,
645 const struct pipe_blend_state *state)
646 {
647 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
648 }
649
650 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
651 {
652 struct si_context *sctx = (struct si_context *)ctx;
653 struct si_state_blend *old_blend = sctx->queued.named.blend;
654 struct si_state_blend *blend = (struct si_state_blend *)state;
655
656 if (!state)
657 return;
658
659 si_pm4_bind_state(sctx, blend, state);
660
661 if (!old_blend ||
662 old_blend->cb_target_mask != blend->cb_target_mask ||
663 old_blend->dual_src_blend != blend->dual_src_blend ||
664 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
665 sctx->framebuffer.nr_samples >= 2 &&
666 sctx->screen->dcc_msaa_allowed))
667 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
668
669 if (!old_blend ||
670 old_blend->cb_target_mask != blend->cb_target_mask ||
671 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
672 old_blend->alpha_to_one != blend->alpha_to_one ||
673 old_blend->dual_src_blend != blend->dual_src_blend ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
676 sctx->do_update_shaders = true;
677
678 if (sctx->screen->dpbb_allowed &&
679 (!old_blend ||
680 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
681 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
682 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
683 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
684
685 if (sctx->screen->has_out_of_order_rast &&
686 (!old_blend ||
687 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
688 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
689 old_blend->commutative_4bit != blend->commutative_4bit ||
690 old_blend->logicop_enable != blend->logicop_enable)))
691 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
692 }
693
694 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
698 }
699
700 static void si_set_blend_color(struct pipe_context *ctx,
701 const struct pipe_blend_color *state)
702 {
703 struct si_context *sctx = (struct si_context *)ctx;
704 static const struct pipe_blend_color zeros;
705
706 sctx->blend_color.state = *state;
707 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
708 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
709 }
710
711 static void si_emit_blend_color(struct si_context *sctx)
712 {
713 struct radeon_cmdbuf *cs = sctx->gfx_cs;
714
715 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
716 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
717 }
718
719 /*
720 * Clipping
721 */
722
723 static void si_set_clip_state(struct pipe_context *ctx,
724 const struct pipe_clip_state *state)
725 {
726 struct si_context *sctx = (struct si_context *)ctx;
727 struct pipe_constant_buffer cb;
728 static const struct pipe_clip_state zeros;
729
730 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
731 return;
732
733 sctx->clip_state.state = *state;
734 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
735 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
736
737 cb.buffer = NULL;
738 cb.user_buffer = state->ucp;
739 cb.buffer_offset = 0;
740 cb.buffer_size = 4*4*8;
741 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
742 pipe_resource_reference(&cb.buffer, NULL);
743 }
744
745 static void si_emit_clip_state(struct si_context *sctx)
746 {
747 struct radeon_cmdbuf *cs = sctx->gfx_cs;
748
749 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
750 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
751 }
752
753 static void si_emit_clip_regs(struct si_context *sctx)
754 {
755 struct si_shader *vs = si_get_vs_state(sctx);
756 struct si_shader_selector *vs_sel = vs->selector;
757 struct tgsi_shader_info *info = &vs_sel->info;
758 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
759 unsigned window_space =
760 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
761 unsigned clipdist_mask = vs_sel->clipdist_mask;
762 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
763 unsigned culldist_mask = vs_sel->culldist_mask;
764 unsigned total_mask;
765
766 if (vs->key.opt.clip_disable) {
767 assert(!info->culldist_writemask);
768 clipdist_mask = 0;
769 culldist_mask = 0;
770 }
771 total_mask = clipdist_mask | culldist_mask;
772
773 /* Clip distances on points have no effect, so need to be implemented
774 * as cull distances. This applies for the clipvertex case as well.
775 *
776 * Setting this for primitives other than points should have no adverse
777 * effects.
778 */
779 clipdist_mask &= rs->clip_plane_enable;
780 culldist_mask |= clipdist_mask;
781
782 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
783 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
784 SI_TRACKED_PA_CL_VS_OUT_CNTL,
785 vs_sel->pa_cl_vs_out_cntl |
786 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
787 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
788 clipdist_mask | (culldist_mask << 8));
789 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
790 SI_TRACKED_PA_CL_CLIP_CNTL,
791 rs->pa_cl_clip_cntl |
792 ucp_mask |
793 S_028810_CLIP_DISABLE(window_space));
794
795 if (initial_cdw != sctx->gfx_cs->current.cdw)
796 sctx->context_roll_counter++;
797 }
798
799 /*
800 * inferred state between framebuffer and rasterizer
801 */
802 static void si_update_poly_offset_state(struct si_context *sctx)
803 {
804 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
805
806 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
807 si_pm4_bind_state(sctx, poly_offset, NULL);
808 return;
809 }
810
811 /* Use the user format, not db_render_format, so that the polygon
812 * offset behaves as expected by applications.
813 */
814 switch (sctx->framebuffer.state.zsbuf->texture->format) {
815 case PIPE_FORMAT_Z16_UNORM:
816 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
817 break;
818 default: /* 24-bit */
819 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
820 break;
821 case PIPE_FORMAT_Z32_FLOAT:
822 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
823 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
824 break;
825 }
826 }
827
828 /*
829 * Rasterizer
830 */
831
832 static uint32_t si_translate_fill(uint32_t func)
833 {
834 switch(func) {
835 case PIPE_POLYGON_MODE_FILL:
836 return V_028814_X_DRAW_TRIANGLES;
837 case PIPE_POLYGON_MODE_LINE:
838 return V_028814_X_DRAW_LINES;
839 case PIPE_POLYGON_MODE_POINT:
840 return V_028814_X_DRAW_POINTS;
841 default:
842 assert(0);
843 return V_028814_X_DRAW_POINTS;
844 }
845 }
846
847 static void *si_create_rs_state(struct pipe_context *ctx,
848 const struct pipe_rasterizer_state *state)
849 {
850 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
851 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
852 struct si_pm4_state *pm4 = &rs->pm4;
853 unsigned tmp, i;
854 float psize_min, psize_max;
855
856 if (!rs) {
857 return NULL;
858 }
859
860 rs->scissor_enable = state->scissor;
861 rs->clip_halfz = state->clip_halfz;
862 rs->two_side = state->light_twoside;
863 rs->multisample_enable = state->multisample;
864 rs->force_persample_interp = state->force_persample_interp;
865 rs->clip_plane_enable = state->clip_plane_enable;
866 rs->half_pixel_center = state->half_pixel_center;
867 rs->line_stipple_enable = state->line_stipple_enable;
868 rs->poly_stipple_enable = state->poly_stipple_enable;
869 rs->line_smooth = state->line_smooth;
870 rs->line_width = state->line_width;
871 rs->poly_smooth = state->poly_smooth;
872 rs->uses_poly_offset = state->offset_point || state->offset_line ||
873 state->offset_tri;
874 rs->clamp_fragment_color = state->clamp_fragment_color;
875 rs->clamp_vertex_color = state->clamp_vertex_color;
876 rs->flatshade = state->flatshade;
877 rs->sprite_coord_enable = state->sprite_coord_enable;
878 rs->rasterizer_discard = state->rasterizer_discard;
879 rs->pa_sc_line_stipple = state->line_stipple_enable ?
880 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
881 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
882 rs->pa_cl_clip_cntl =
883 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
884 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
885 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
886 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
887 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
888
889 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
890 S_0286D4_FLAT_SHADE_ENA(1) |
891 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
892 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
893 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
894 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
895 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
896 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
897
898 /* point size 12.4 fixed point */
899 tmp = (unsigned)(state->point_size * 8.0);
900 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
901
902 if (state->point_size_per_vertex) {
903 psize_min = util_get_min_point_size(state);
904 psize_max = SI_MAX_POINT_SIZE;
905 } else {
906 /* Force the point size to be as if the vertex output was disabled. */
907 psize_min = state->point_size;
908 psize_max = state->point_size;
909 }
910 rs->max_point_size = psize_max;
911
912 /* Divide by two, because 0.5 = 1 pixel. */
913 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
914 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
915 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
916
917 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
918 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
919 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
920 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
921 S_028A48_MSAA_ENABLE(state->multisample ||
922 state->poly_smooth ||
923 state->line_smooth) |
924 S_028A48_VPORT_SCISSOR_ENABLE(1) |
925 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
926
927 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
928 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
929 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
930 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
931 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
932 S_028814_FACE(!state->front_ccw) |
933 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
934 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
935 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
936 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
937 state->fill_back != PIPE_POLYGON_MODE_FILL) |
938 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
939 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
940
941 if (!rs->uses_poly_offset)
942 return rs;
943
944 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
945 if (!rs->pm4_poly_offset) {
946 FREE(rs);
947 return NULL;
948 }
949
950 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
951 for (i = 0; i < 3; i++) {
952 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
953 float offset_units = state->offset_units;
954 float offset_scale = state->offset_scale * 16.0f;
955 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
956
957 if (!state->offset_units_unscaled) {
958 switch (i) {
959 case 0: /* 16-bit zbuffer */
960 offset_units *= 4.0f;
961 pa_su_poly_offset_db_fmt_cntl =
962 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
963 break;
964 case 1: /* 24-bit zbuffer */
965 offset_units *= 2.0f;
966 pa_su_poly_offset_db_fmt_cntl =
967 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
968 break;
969 case 2: /* 32-bit zbuffer */
970 offset_units *= 1.0f;
971 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
972 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
973 break;
974 }
975 }
976
977 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
978 fui(offset_scale));
979 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
980 fui(offset_units));
981 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
982 fui(offset_scale));
983 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
984 fui(offset_units));
985 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
986 pa_su_poly_offset_db_fmt_cntl);
987 }
988
989 return rs;
990 }
991
992 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
993 {
994 struct si_context *sctx = (struct si_context *)ctx;
995 struct si_state_rasterizer *old_rs =
996 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
997 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
998
999 if (!state)
1000 return;
1001
1002 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1003 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1004
1005 /* Update the small primitive filter workaround if necessary. */
1006 if (sctx->screen->has_msaa_sample_loc_bug &&
1007 sctx->framebuffer.nr_samples > 1)
1008 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1009 }
1010
1011 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1012 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1013
1014 si_pm4_bind_state(sctx, rasterizer, rs);
1015 si_update_poly_offset_state(sctx);
1016
1017 if (!old_rs ||
1018 old_rs->scissor_enable != rs->scissor_enable) {
1019 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1020 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1021 }
1022
1023 if (!old_rs ||
1024 old_rs->line_width != rs->line_width ||
1025 old_rs->max_point_size != rs->max_point_size ||
1026 old_rs->half_pixel_center != rs->half_pixel_center)
1027 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1028
1029 if (!old_rs ||
1030 old_rs->clip_halfz != rs->clip_halfz) {
1031 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1032 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1033 }
1034
1035 if (!old_rs ||
1036 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1037 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1038 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1039
1040 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1041 rs->line_stipple_enable;
1042
1043 if (!old_rs ||
1044 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1045 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1046 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1047 old_rs->flatshade != rs->flatshade ||
1048 old_rs->two_side != rs->two_side ||
1049 old_rs->multisample_enable != rs->multisample_enable ||
1050 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1051 old_rs->poly_smooth != rs->poly_smooth ||
1052 old_rs->line_smooth != rs->line_smooth ||
1053 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1054 old_rs->force_persample_interp != rs->force_persample_interp)
1055 sctx->do_update_shaders = true;
1056 }
1057
1058 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1059 {
1060 struct si_context *sctx = (struct si_context *)ctx;
1061 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1062
1063 if (sctx->queued.named.rasterizer == state)
1064 si_pm4_bind_state(sctx, poly_offset, NULL);
1065
1066 FREE(rs->pm4_poly_offset);
1067 si_pm4_delete_state(sctx, rasterizer, rs);
1068 }
1069
1070 /*
1071 * infeered state between dsa and stencil ref
1072 */
1073 static void si_emit_stencil_ref(struct si_context *sctx)
1074 {
1075 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1076 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1077 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1078
1079 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1080 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1081 S_028430_STENCILMASK(dsa->valuemask[0]) |
1082 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1083 S_028430_STENCILOPVAL(1));
1084 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1085 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1086 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1087 S_028434_STENCILOPVAL_BF(1));
1088 }
1089
1090 static void si_set_stencil_ref(struct pipe_context *ctx,
1091 const struct pipe_stencil_ref *state)
1092 {
1093 struct si_context *sctx = (struct si_context *)ctx;
1094
1095 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1096 return;
1097
1098 sctx->stencil_ref.state = *state;
1099 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1100 }
1101
1102
1103 /*
1104 * DSA
1105 */
1106
1107 static uint32_t si_translate_stencil_op(int s_op)
1108 {
1109 switch (s_op) {
1110 case PIPE_STENCIL_OP_KEEP:
1111 return V_02842C_STENCIL_KEEP;
1112 case PIPE_STENCIL_OP_ZERO:
1113 return V_02842C_STENCIL_ZERO;
1114 case PIPE_STENCIL_OP_REPLACE:
1115 return V_02842C_STENCIL_REPLACE_TEST;
1116 case PIPE_STENCIL_OP_INCR:
1117 return V_02842C_STENCIL_ADD_CLAMP;
1118 case PIPE_STENCIL_OP_DECR:
1119 return V_02842C_STENCIL_SUB_CLAMP;
1120 case PIPE_STENCIL_OP_INCR_WRAP:
1121 return V_02842C_STENCIL_ADD_WRAP;
1122 case PIPE_STENCIL_OP_DECR_WRAP:
1123 return V_02842C_STENCIL_SUB_WRAP;
1124 case PIPE_STENCIL_OP_INVERT:
1125 return V_02842C_STENCIL_INVERT;
1126 default:
1127 PRINT_ERR("Unknown stencil op %d", s_op);
1128 assert(0);
1129 break;
1130 }
1131 return 0;
1132 }
1133
1134 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1135 {
1136 return s->enabled && s->writemask &&
1137 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1138 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1139 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1140 }
1141
1142 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1143 {
1144 /* REPLACE is normally order invariant, except when the stencil
1145 * reference value is written by the fragment shader. Tracking this
1146 * interaction does not seem worth the effort, so be conservative. */
1147 return op != PIPE_STENCIL_OP_INCR &&
1148 op != PIPE_STENCIL_OP_DECR &&
1149 op != PIPE_STENCIL_OP_REPLACE;
1150 }
1151
1152 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1153 * invariant in the sense that the set of passing fragments as well as the
1154 * final stencil buffer result does not depend on the order of fragments. */
1155 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1156 {
1157 return !state->enabled || !state->writemask ||
1158 /* The following assumes that Z writes are disabled. */
1159 (state->func == PIPE_FUNC_ALWAYS &&
1160 si_order_invariant_stencil_op(state->zpass_op) &&
1161 si_order_invariant_stencil_op(state->zfail_op)) ||
1162 (state->func == PIPE_FUNC_NEVER &&
1163 si_order_invariant_stencil_op(state->fail_op));
1164 }
1165
1166 static void *si_create_dsa_state(struct pipe_context *ctx,
1167 const struct pipe_depth_stencil_alpha_state *state)
1168 {
1169 struct si_context *sctx = (struct si_context *)ctx;
1170 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1171 struct si_pm4_state *pm4 = &dsa->pm4;
1172 unsigned db_depth_control;
1173 uint32_t db_stencil_control = 0;
1174
1175 if (!dsa) {
1176 return NULL;
1177 }
1178
1179 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1180 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1181 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1182 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1183
1184 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1185 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1186 S_028800_ZFUNC(state->depth.func) |
1187 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1188
1189 /* stencil */
1190 if (state->stencil[0].enabled) {
1191 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1192 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1193 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1194 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1195 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1196
1197 if (state->stencil[1].enabled) {
1198 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1199 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1200 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1201 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1202 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1203 }
1204 }
1205
1206 /* alpha */
1207 if (state->alpha.enabled) {
1208 dsa->alpha_func = state->alpha.func;
1209
1210 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1211 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1212 } else {
1213 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1214 }
1215
1216 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1217 if (state->stencil[0].enabled)
1218 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1219 if (state->depth.bounds_test) {
1220 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1221 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1222 }
1223
1224 dsa->depth_enabled = state->depth.enabled;
1225 dsa->depth_write_enabled = state->depth.enabled &&
1226 state->depth.writemask;
1227 dsa->stencil_enabled = state->stencil[0].enabled;
1228 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1229 (si_dsa_writes_stencil(&state->stencil[0]) ||
1230 si_dsa_writes_stencil(&state->stencil[1]));
1231 dsa->db_can_write = dsa->depth_write_enabled ||
1232 dsa->stencil_write_enabled;
1233
1234 bool zfunc_is_ordered =
1235 state->depth.func == PIPE_FUNC_NEVER ||
1236 state->depth.func == PIPE_FUNC_LESS ||
1237 state->depth.func == PIPE_FUNC_LEQUAL ||
1238 state->depth.func == PIPE_FUNC_GREATER ||
1239 state->depth.func == PIPE_FUNC_GEQUAL;
1240
1241 bool nozwrite_and_order_invariant_stencil =
1242 !dsa->db_can_write ||
1243 (!dsa->depth_write_enabled &&
1244 si_order_invariant_stencil_state(&state->stencil[0]) &&
1245 si_order_invariant_stencil_state(&state->stencil[1]));
1246
1247 dsa->order_invariance[1].zs =
1248 nozwrite_and_order_invariant_stencil ||
1249 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1250 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1251
1252 dsa->order_invariance[1].pass_set =
1253 nozwrite_and_order_invariant_stencil ||
1254 (!dsa->stencil_write_enabled &&
1255 (state->depth.func == PIPE_FUNC_ALWAYS ||
1256 state->depth.func == PIPE_FUNC_NEVER));
1257 dsa->order_invariance[0].pass_set =
1258 !dsa->depth_write_enabled ||
1259 (state->depth.func == PIPE_FUNC_ALWAYS ||
1260 state->depth.func == PIPE_FUNC_NEVER);
1261
1262 dsa->order_invariance[1].pass_last =
1263 sctx->screen->assume_no_z_fights &&
1264 !dsa->stencil_write_enabled &&
1265 dsa->depth_write_enabled && zfunc_is_ordered;
1266 dsa->order_invariance[0].pass_last =
1267 sctx->screen->assume_no_z_fights &&
1268 dsa->depth_write_enabled && zfunc_is_ordered;
1269
1270 return dsa;
1271 }
1272
1273 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1274 {
1275 struct si_context *sctx = (struct si_context *)ctx;
1276 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1277 struct si_state_dsa *dsa = state;
1278
1279 if (!state)
1280 return;
1281
1282 si_pm4_bind_state(sctx, dsa, dsa);
1283
1284 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1285 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1286 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1287 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1288 }
1289
1290 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1291 sctx->do_update_shaders = true;
1292
1293 if (sctx->screen->dpbb_allowed &&
1294 (!old_dsa ||
1295 (old_dsa->depth_enabled != dsa->depth_enabled ||
1296 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1297 old_dsa->db_can_write != dsa->db_can_write)))
1298 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1299
1300 if (sctx->screen->has_out_of_order_rast &&
1301 (!old_dsa ||
1302 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1303 sizeof(old_dsa->order_invariance))))
1304 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1305 }
1306
1307 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1308 {
1309 struct si_context *sctx = (struct si_context *)ctx;
1310 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1311 }
1312
1313 static void *si_create_db_flush_dsa(struct si_context *sctx)
1314 {
1315 struct pipe_depth_stencil_alpha_state dsa = {};
1316
1317 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1318 }
1319
1320 /* DB RENDER STATE */
1321
1322 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1323 {
1324 struct si_context *sctx = (struct si_context*)ctx;
1325
1326 /* Pipeline stat & streamout queries. */
1327 if (enable) {
1328 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1329 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1330 } else {
1331 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1332 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1333 }
1334
1335 /* Occlusion queries. */
1336 if (sctx->occlusion_queries_disabled != !enable) {
1337 sctx->occlusion_queries_disabled = !enable;
1338 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1339 }
1340 }
1341
1342 void si_set_occlusion_query_state(struct si_context *sctx,
1343 bool old_perfect_enable)
1344 {
1345 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1346
1347 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1348
1349 if (perfect_enable != old_perfect_enable)
1350 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1351 }
1352
1353 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1354 {
1355 st->saved_compute = sctx->cs_shader_state.program;
1356
1357 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1358 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1359 }
1360
1361 static void si_emit_db_render_state(struct si_context *sctx)
1362 {
1363 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1364 unsigned db_shader_control, db_render_control, db_count_control;
1365 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1366
1367 /* DB_RENDER_CONTROL */
1368 if (sctx->dbcb_depth_copy_enabled ||
1369 sctx->dbcb_stencil_copy_enabled) {
1370 db_render_control =
1371 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1372 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1373 S_028000_COPY_CENTROID(1) |
1374 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1375 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1376 db_render_control =
1377 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1378 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1379 } else {
1380 db_render_control =
1381 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1382 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1383 }
1384
1385 /* DB_COUNT_CONTROL (occlusion queries) */
1386 if (sctx->num_occlusion_queries > 0 &&
1387 !sctx->occlusion_queries_disabled) {
1388 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1389
1390 if (sctx->chip_class >= CIK) {
1391 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1392
1393 /* Stoney doesn't increment occlusion query counters
1394 * if the sample rate is 16x. Use 8x sample rate instead.
1395 */
1396 if (sctx->family == CHIP_STONEY)
1397 log_sample_rate = MIN2(log_sample_rate, 3);
1398
1399 db_count_control =
1400 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1401 S_028004_SAMPLE_RATE(log_sample_rate) |
1402 S_028004_ZPASS_ENABLE(1) |
1403 S_028004_SLICE_EVEN_ENABLE(1) |
1404 S_028004_SLICE_ODD_ENABLE(1);
1405 } else {
1406 db_count_control =
1407 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1408 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1409 }
1410 } else {
1411 /* Disable occlusion queries. */
1412 if (sctx->chip_class >= CIK) {
1413 db_count_control = 0;
1414 } else {
1415 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1416 }
1417 }
1418
1419 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1420 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1421 db_count_control);
1422
1423 /* DB_RENDER_OVERRIDE2 */
1424 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1425 SI_TRACKED_DB_RENDER_OVERRIDE2,
1426 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1427 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1428 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1429
1430 db_shader_control = sctx->ps_db_shader_control;
1431
1432 /* Bug workaround for smoothing (overrasterization) on SI. */
1433 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1434 db_shader_control &= C_02880C_Z_ORDER;
1435 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1436 }
1437
1438 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1439 if (!rs->multisample_enable)
1440 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1441
1442 if (sctx->screen->has_rbplus &&
1443 !sctx->screen->rbplus_allowed)
1444 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1445
1446 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1447 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1448
1449 if (initial_cdw != sctx->gfx_cs->current.cdw)
1450 sctx->context_roll_counter++;
1451 }
1452
1453 /*
1454 * format translation
1455 */
1456 static uint32_t si_translate_colorformat(enum pipe_format format)
1457 {
1458 const struct util_format_description *desc = util_format_description(format);
1459 if (!desc)
1460 return V_028C70_COLOR_INVALID;
1461
1462 #define HAS_SIZE(x,y,z,w) \
1463 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1464 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1465
1466 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1467 return V_028C70_COLOR_10_11_11;
1468
1469 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1470 return V_028C70_COLOR_INVALID;
1471
1472 /* hw cannot support mixed formats (except depth/stencil, since
1473 * stencil is not written to). */
1474 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1475 return V_028C70_COLOR_INVALID;
1476
1477 switch (desc->nr_channels) {
1478 case 1:
1479 switch (desc->channel[0].size) {
1480 case 8:
1481 return V_028C70_COLOR_8;
1482 case 16:
1483 return V_028C70_COLOR_16;
1484 case 32:
1485 return V_028C70_COLOR_32;
1486 }
1487 break;
1488 case 2:
1489 if (desc->channel[0].size == desc->channel[1].size) {
1490 switch (desc->channel[0].size) {
1491 case 8:
1492 return V_028C70_COLOR_8_8;
1493 case 16:
1494 return V_028C70_COLOR_16_16;
1495 case 32:
1496 return V_028C70_COLOR_32_32;
1497 }
1498 } else if (HAS_SIZE(8,24,0,0)) {
1499 return V_028C70_COLOR_24_8;
1500 } else if (HAS_SIZE(24,8,0,0)) {
1501 return V_028C70_COLOR_8_24;
1502 }
1503 break;
1504 case 3:
1505 if (HAS_SIZE(5,6,5,0)) {
1506 return V_028C70_COLOR_5_6_5;
1507 } else if (HAS_SIZE(32,8,24,0)) {
1508 return V_028C70_COLOR_X24_8_32_FLOAT;
1509 }
1510 break;
1511 case 4:
1512 if (desc->channel[0].size == desc->channel[1].size &&
1513 desc->channel[0].size == desc->channel[2].size &&
1514 desc->channel[0].size == desc->channel[3].size) {
1515 switch (desc->channel[0].size) {
1516 case 4:
1517 return V_028C70_COLOR_4_4_4_4;
1518 case 8:
1519 return V_028C70_COLOR_8_8_8_8;
1520 case 16:
1521 return V_028C70_COLOR_16_16_16_16;
1522 case 32:
1523 return V_028C70_COLOR_32_32_32_32;
1524 }
1525 } else if (HAS_SIZE(5,5,5,1)) {
1526 return V_028C70_COLOR_1_5_5_5;
1527 } else if (HAS_SIZE(1,5,5,5)) {
1528 return V_028C70_COLOR_5_5_5_1;
1529 } else if (HAS_SIZE(10,10,10,2)) {
1530 return V_028C70_COLOR_2_10_10_10;
1531 }
1532 break;
1533 }
1534 return V_028C70_COLOR_INVALID;
1535 }
1536
1537 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1538 {
1539 if (SI_BIG_ENDIAN) {
1540 switch(colorformat) {
1541 /* 8-bit buffers. */
1542 case V_028C70_COLOR_8:
1543 return V_028C70_ENDIAN_NONE;
1544
1545 /* 16-bit buffers. */
1546 case V_028C70_COLOR_5_6_5:
1547 case V_028C70_COLOR_1_5_5_5:
1548 case V_028C70_COLOR_4_4_4_4:
1549 case V_028C70_COLOR_16:
1550 case V_028C70_COLOR_8_8:
1551 return V_028C70_ENDIAN_8IN16;
1552
1553 /* 32-bit buffers. */
1554 case V_028C70_COLOR_8_8_8_8:
1555 case V_028C70_COLOR_2_10_10_10:
1556 case V_028C70_COLOR_8_24:
1557 case V_028C70_COLOR_24_8:
1558 case V_028C70_COLOR_16_16:
1559 return V_028C70_ENDIAN_8IN32;
1560
1561 /* 64-bit buffers. */
1562 case V_028C70_COLOR_16_16_16_16:
1563 return V_028C70_ENDIAN_8IN16;
1564
1565 case V_028C70_COLOR_32_32:
1566 return V_028C70_ENDIAN_8IN32;
1567
1568 /* 128-bit buffers. */
1569 case V_028C70_COLOR_32_32_32_32:
1570 return V_028C70_ENDIAN_8IN32;
1571 default:
1572 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1573 }
1574 } else {
1575 return V_028C70_ENDIAN_NONE;
1576 }
1577 }
1578
1579 static uint32_t si_translate_dbformat(enum pipe_format format)
1580 {
1581 switch (format) {
1582 case PIPE_FORMAT_Z16_UNORM:
1583 return V_028040_Z_16;
1584 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1585 case PIPE_FORMAT_X8Z24_UNORM:
1586 case PIPE_FORMAT_Z24X8_UNORM:
1587 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1588 return V_028040_Z_24; /* deprecated on SI */
1589 case PIPE_FORMAT_Z32_FLOAT:
1590 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1591 return V_028040_Z_32_FLOAT;
1592 default:
1593 return V_028040_Z_INVALID;
1594 }
1595 }
1596
1597 /*
1598 * Texture translation
1599 */
1600
1601 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1602 enum pipe_format format,
1603 const struct util_format_description *desc,
1604 int first_non_void)
1605 {
1606 struct si_screen *sscreen = (struct si_screen*)screen;
1607 bool uniform = true;
1608 int i;
1609
1610 /* Colorspace (return non-RGB formats directly). */
1611 switch (desc->colorspace) {
1612 /* Depth stencil formats */
1613 case UTIL_FORMAT_COLORSPACE_ZS:
1614 switch (format) {
1615 case PIPE_FORMAT_Z16_UNORM:
1616 return V_008F14_IMG_DATA_FORMAT_16;
1617 case PIPE_FORMAT_X24S8_UINT:
1618 case PIPE_FORMAT_S8X24_UINT:
1619 /*
1620 * Implemented as an 8_8_8_8 data format to fix texture
1621 * gathers in stencil sampling. This affects at least
1622 * GL45-CTS.texture_cube_map_array.sampling on VI.
1623 */
1624 if (sscreen->info.chip_class <= VI)
1625 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1626
1627 if (format == PIPE_FORMAT_X24S8_UINT)
1628 return V_008F14_IMG_DATA_FORMAT_8_24;
1629 else
1630 return V_008F14_IMG_DATA_FORMAT_24_8;
1631 case PIPE_FORMAT_Z24X8_UNORM:
1632 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1633 return V_008F14_IMG_DATA_FORMAT_8_24;
1634 case PIPE_FORMAT_X8Z24_UNORM:
1635 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1636 return V_008F14_IMG_DATA_FORMAT_24_8;
1637 case PIPE_FORMAT_S8_UINT:
1638 return V_008F14_IMG_DATA_FORMAT_8;
1639 case PIPE_FORMAT_Z32_FLOAT:
1640 return V_008F14_IMG_DATA_FORMAT_32;
1641 case PIPE_FORMAT_X32_S8X24_UINT:
1642 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1643 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1644 default:
1645 goto out_unknown;
1646 }
1647
1648 case UTIL_FORMAT_COLORSPACE_YUV:
1649 goto out_unknown; /* TODO */
1650
1651 case UTIL_FORMAT_COLORSPACE_SRGB:
1652 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1653 goto out_unknown;
1654 break;
1655
1656 default:
1657 break;
1658 }
1659
1660 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1661 if (!sscreen->info.has_format_bc1_through_bc7)
1662 goto out_unknown;
1663
1664 switch (format) {
1665 case PIPE_FORMAT_RGTC1_SNORM:
1666 case PIPE_FORMAT_LATC1_SNORM:
1667 case PIPE_FORMAT_RGTC1_UNORM:
1668 case PIPE_FORMAT_LATC1_UNORM:
1669 return V_008F14_IMG_DATA_FORMAT_BC4;
1670 case PIPE_FORMAT_RGTC2_SNORM:
1671 case PIPE_FORMAT_LATC2_SNORM:
1672 case PIPE_FORMAT_RGTC2_UNORM:
1673 case PIPE_FORMAT_LATC2_UNORM:
1674 return V_008F14_IMG_DATA_FORMAT_BC5;
1675 default:
1676 goto out_unknown;
1677 }
1678 }
1679
1680 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1681 (sscreen->info.family == CHIP_STONEY ||
1682 sscreen->info.family == CHIP_VEGA10 ||
1683 sscreen->info.family == CHIP_RAVEN)) {
1684 switch (format) {
1685 case PIPE_FORMAT_ETC1_RGB8:
1686 case PIPE_FORMAT_ETC2_RGB8:
1687 case PIPE_FORMAT_ETC2_SRGB8:
1688 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1689 case PIPE_FORMAT_ETC2_RGB8A1:
1690 case PIPE_FORMAT_ETC2_SRGB8A1:
1691 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1692 case PIPE_FORMAT_ETC2_RGBA8:
1693 case PIPE_FORMAT_ETC2_SRGBA8:
1694 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1695 case PIPE_FORMAT_ETC2_R11_UNORM:
1696 case PIPE_FORMAT_ETC2_R11_SNORM:
1697 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1698 case PIPE_FORMAT_ETC2_RG11_UNORM:
1699 case PIPE_FORMAT_ETC2_RG11_SNORM:
1700 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1701 default:
1702 goto out_unknown;
1703 }
1704 }
1705
1706 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1707 if (!sscreen->info.has_format_bc1_through_bc7)
1708 goto out_unknown;
1709
1710 switch (format) {
1711 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1712 case PIPE_FORMAT_BPTC_SRGBA:
1713 return V_008F14_IMG_DATA_FORMAT_BC7;
1714 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1715 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1716 return V_008F14_IMG_DATA_FORMAT_BC6;
1717 default:
1718 goto out_unknown;
1719 }
1720 }
1721
1722 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1723 switch (format) {
1724 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1725 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1726 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1727 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1728 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1729 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1730 default:
1731 goto out_unknown;
1732 }
1733 }
1734
1735 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1736 if (!sscreen->info.has_format_bc1_through_bc7)
1737 goto out_unknown;
1738
1739 switch (format) {
1740 case PIPE_FORMAT_DXT1_RGB:
1741 case PIPE_FORMAT_DXT1_RGBA:
1742 case PIPE_FORMAT_DXT1_SRGB:
1743 case PIPE_FORMAT_DXT1_SRGBA:
1744 return V_008F14_IMG_DATA_FORMAT_BC1;
1745 case PIPE_FORMAT_DXT3_RGBA:
1746 case PIPE_FORMAT_DXT3_SRGBA:
1747 return V_008F14_IMG_DATA_FORMAT_BC2;
1748 case PIPE_FORMAT_DXT5_RGBA:
1749 case PIPE_FORMAT_DXT5_SRGBA:
1750 return V_008F14_IMG_DATA_FORMAT_BC3;
1751 default:
1752 goto out_unknown;
1753 }
1754 }
1755
1756 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1757 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1758 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1759 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1760 }
1761
1762 /* R8G8Bx_SNORM - TODO CxV8U8 */
1763
1764 /* hw cannot support mixed formats (except depth/stencil, since only
1765 * depth is read).*/
1766 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1767 goto out_unknown;
1768
1769 /* See whether the components are of the same size. */
1770 for (i = 1; i < desc->nr_channels; i++) {
1771 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1772 }
1773
1774 /* Non-uniform formats. */
1775 if (!uniform) {
1776 switch(desc->nr_channels) {
1777 case 3:
1778 if (desc->channel[0].size == 5 &&
1779 desc->channel[1].size == 6 &&
1780 desc->channel[2].size == 5) {
1781 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1782 }
1783 goto out_unknown;
1784 case 4:
1785 if (desc->channel[0].size == 5 &&
1786 desc->channel[1].size == 5 &&
1787 desc->channel[2].size == 5 &&
1788 desc->channel[3].size == 1) {
1789 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1790 }
1791 if (desc->channel[0].size == 1 &&
1792 desc->channel[1].size == 5 &&
1793 desc->channel[2].size == 5 &&
1794 desc->channel[3].size == 5) {
1795 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1796 }
1797 if (desc->channel[0].size == 10 &&
1798 desc->channel[1].size == 10 &&
1799 desc->channel[2].size == 10 &&
1800 desc->channel[3].size == 2) {
1801 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1802 }
1803 goto out_unknown;
1804 }
1805 goto out_unknown;
1806 }
1807
1808 if (first_non_void < 0 || first_non_void > 3)
1809 goto out_unknown;
1810
1811 /* uniform formats */
1812 switch (desc->channel[first_non_void].size) {
1813 case 4:
1814 switch (desc->nr_channels) {
1815 #if 0 /* Not supported for render targets */
1816 case 2:
1817 return V_008F14_IMG_DATA_FORMAT_4_4;
1818 #endif
1819 case 4:
1820 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1821 }
1822 break;
1823 case 8:
1824 switch (desc->nr_channels) {
1825 case 1:
1826 return V_008F14_IMG_DATA_FORMAT_8;
1827 case 2:
1828 return V_008F14_IMG_DATA_FORMAT_8_8;
1829 case 4:
1830 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1831 }
1832 break;
1833 case 16:
1834 switch (desc->nr_channels) {
1835 case 1:
1836 return V_008F14_IMG_DATA_FORMAT_16;
1837 case 2:
1838 return V_008F14_IMG_DATA_FORMAT_16_16;
1839 case 4:
1840 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1841 }
1842 break;
1843 case 32:
1844 switch (desc->nr_channels) {
1845 case 1:
1846 return V_008F14_IMG_DATA_FORMAT_32;
1847 case 2:
1848 return V_008F14_IMG_DATA_FORMAT_32_32;
1849 #if 0 /* Not supported for render targets */
1850 case 3:
1851 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1852 #endif
1853 case 4:
1854 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1855 }
1856 }
1857
1858 out_unknown:
1859 return ~0;
1860 }
1861
1862 static unsigned si_tex_wrap(unsigned wrap)
1863 {
1864 switch (wrap) {
1865 default:
1866 case PIPE_TEX_WRAP_REPEAT:
1867 return V_008F30_SQ_TEX_WRAP;
1868 case PIPE_TEX_WRAP_CLAMP:
1869 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1870 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1871 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1872 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1873 return V_008F30_SQ_TEX_CLAMP_BORDER;
1874 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1875 return V_008F30_SQ_TEX_MIRROR;
1876 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1877 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1878 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1879 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1880 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1881 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1882 }
1883 }
1884
1885 static unsigned si_tex_mipfilter(unsigned filter)
1886 {
1887 switch (filter) {
1888 case PIPE_TEX_MIPFILTER_NEAREST:
1889 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1890 case PIPE_TEX_MIPFILTER_LINEAR:
1891 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1892 default:
1893 case PIPE_TEX_MIPFILTER_NONE:
1894 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1895 }
1896 }
1897
1898 static unsigned si_tex_compare(unsigned compare)
1899 {
1900 switch (compare) {
1901 default:
1902 case PIPE_FUNC_NEVER:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1904 case PIPE_FUNC_LESS:
1905 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1906 case PIPE_FUNC_EQUAL:
1907 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1908 case PIPE_FUNC_LEQUAL:
1909 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1910 case PIPE_FUNC_GREATER:
1911 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1912 case PIPE_FUNC_NOTEQUAL:
1913 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1914 case PIPE_FUNC_GEQUAL:
1915 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1916 case PIPE_FUNC_ALWAYS:
1917 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1918 }
1919 }
1920
1921 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1922 unsigned view_target, unsigned nr_samples)
1923 {
1924 unsigned res_target = tex->buffer.b.b.target;
1925
1926 if (view_target == PIPE_TEXTURE_CUBE ||
1927 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1928 res_target = view_target;
1929 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1930 else if (res_target == PIPE_TEXTURE_CUBE ||
1931 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1932 res_target = PIPE_TEXTURE_2D_ARRAY;
1933
1934 /* GFX9 allocates 1D textures as 2D. */
1935 if ((res_target == PIPE_TEXTURE_1D ||
1936 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1937 sscreen->info.chip_class >= GFX9 &&
1938 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1939 if (res_target == PIPE_TEXTURE_1D)
1940 res_target = PIPE_TEXTURE_2D;
1941 else
1942 res_target = PIPE_TEXTURE_2D_ARRAY;
1943 }
1944
1945 switch (res_target) {
1946 default:
1947 case PIPE_TEXTURE_1D:
1948 return V_008F1C_SQ_RSRC_IMG_1D;
1949 case PIPE_TEXTURE_1D_ARRAY:
1950 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1951 case PIPE_TEXTURE_2D:
1952 case PIPE_TEXTURE_RECT:
1953 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1954 V_008F1C_SQ_RSRC_IMG_2D;
1955 case PIPE_TEXTURE_2D_ARRAY:
1956 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1957 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1958 case PIPE_TEXTURE_3D:
1959 return V_008F1C_SQ_RSRC_IMG_3D;
1960 case PIPE_TEXTURE_CUBE:
1961 case PIPE_TEXTURE_CUBE_ARRAY:
1962 return V_008F1C_SQ_RSRC_IMG_CUBE;
1963 }
1964 }
1965
1966 /*
1967 * Format support testing
1968 */
1969
1970 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1971 {
1972 const struct util_format_description *desc = util_format_description(format);
1973 if (!desc)
1974 return false;
1975
1976 return si_translate_texformat(screen, format, desc,
1977 util_format_get_first_non_void_channel(format)) != ~0U;
1978 }
1979
1980 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1981 const struct util_format_description *desc,
1982 int first_non_void)
1983 {
1984 int i;
1985
1986 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1987 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1988
1989 assert(first_non_void >= 0);
1990
1991 if (desc->nr_channels == 4 &&
1992 desc->channel[0].size == 10 &&
1993 desc->channel[1].size == 10 &&
1994 desc->channel[2].size == 10 &&
1995 desc->channel[3].size == 2)
1996 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1997
1998 /* See whether the components are of the same size. */
1999 for (i = 0; i < desc->nr_channels; i++) {
2000 if (desc->channel[first_non_void].size != desc->channel[i].size)
2001 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2002 }
2003
2004 switch (desc->channel[first_non_void].size) {
2005 case 8:
2006 switch (desc->nr_channels) {
2007 case 1:
2008 case 3: /* 3 loads */
2009 return V_008F0C_BUF_DATA_FORMAT_8;
2010 case 2:
2011 return V_008F0C_BUF_DATA_FORMAT_8_8;
2012 case 4:
2013 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2014 }
2015 break;
2016 case 16:
2017 switch (desc->nr_channels) {
2018 case 1:
2019 case 3: /* 3 loads */
2020 return V_008F0C_BUF_DATA_FORMAT_16;
2021 case 2:
2022 return V_008F0C_BUF_DATA_FORMAT_16_16;
2023 case 4:
2024 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2025 }
2026 break;
2027 case 32:
2028 switch (desc->nr_channels) {
2029 case 1:
2030 return V_008F0C_BUF_DATA_FORMAT_32;
2031 case 2:
2032 return V_008F0C_BUF_DATA_FORMAT_32_32;
2033 case 3:
2034 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2035 case 4:
2036 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2037 }
2038 break;
2039 case 64:
2040 /* Legacy double formats. */
2041 switch (desc->nr_channels) {
2042 case 1: /* 1 load */
2043 return V_008F0C_BUF_DATA_FORMAT_32_32;
2044 case 2: /* 1 load */
2045 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2046 case 3: /* 3 loads */
2047 return V_008F0C_BUF_DATA_FORMAT_32_32;
2048 case 4: /* 2 loads */
2049 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2050 }
2051 break;
2052 }
2053
2054 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2055 }
2056
2057 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2058 const struct util_format_description *desc,
2059 int first_non_void)
2060 {
2061 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2062 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2063
2064 assert(first_non_void >= 0);
2065
2066 switch (desc->channel[first_non_void].type) {
2067 case UTIL_FORMAT_TYPE_SIGNED:
2068 case UTIL_FORMAT_TYPE_FIXED:
2069 if (desc->channel[first_non_void].size >= 32 ||
2070 desc->channel[first_non_void].pure_integer)
2071 return V_008F0C_BUF_NUM_FORMAT_SINT;
2072 else if (desc->channel[first_non_void].normalized)
2073 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2074 else
2075 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2076 break;
2077 case UTIL_FORMAT_TYPE_UNSIGNED:
2078 if (desc->channel[first_non_void].size >= 32 ||
2079 desc->channel[first_non_void].pure_integer)
2080 return V_008F0C_BUF_NUM_FORMAT_UINT;
2081 else if (desc->channel[first_non_void].normalized)
2082 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2083 else
2084 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2085 break;
2086 case UTIL_FORMAT_TYPE_FLOAT:
2087 default:
2088 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2089 }
2090 }
2091
2092 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2093 enum pipe_format format,
2094 unsigned usage)
2095 {
2096 const struct util_format_description *desc;
2097 int first_non_void;
2098 unsigned data_format;
2099
2100 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2101 PIPE_BIND_SAMPLER_VIEW |
2102 PIPE_BIND_VERTEX_BUFFER)) == 0);
2103
2104 desc = util_format_description(format);
2105 if (!desc)
2106 return 0;
2107
2108 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2109 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2110 * for read-only access (with caveats surrounding bounds checks), but
2111 * obviously fails for write access which we have to implement for
2112 * shader images. Luckily, OpenGL doesn't expect this to be supported
2113 * anyway, and so the only impact is on PBO uploads / downloads, which
2114 * shouldn't be expected to be fast for GL_RGB anyway.
2115 */
2116 if (desc->block.bits == 3 * 8 ||
2117 desc->block.bits == 3 * 16) {
2118 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2119 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2120 if (!usage)
2121 return 0;
2122 }
2123 }
2124
2125 first_non_void = util_format_get_first_non_void_channel(format);
2126 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2127 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2128 return 0;
2129
2130 return usage;
2131 }
2132
2133 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2134 {
2135 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2136 si_translate_colorswap(format, false) != ~0U;
2137 }
2138
2139 static bool si_is_zs_format_supported(enum pipe_format format)
2140 {
2141 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2142 }
2143
2144 static boolean si_is_format_supported(struct pipe_screen *screen,
2145 enum pipe_format format,
2146 enum pipe_texture_target target,
2147 unsigned sample_count,
2148 unsigned storage_sample_count,
2149 unsigned usage)
2150 {
2151 struct si_screen *sscreen = (struct si_screen *)screen;
2152 unsigned retval = 0;
2153
2154 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2155 PRINT_ERR("radeonsi: unsupported texture type %d\n", target);
2156 return false;
2157 }
2158
2159 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2160 return false;
2161
2162 if (sample_count > 1) {
2163 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2164 return false;
2165
2166 if (usage & PIPE_BIND_SHADER_IMAGE)
2167 return false;
2168
2169 /* Only power-of-two sample counts are supported. */
2170 if (!util_is_power_of_two_or_zero(sample_count) ||
2171 !util_is_power_of_two_or_zero(storage_sample_count))
2172 return false;
2173
2174 /* MSAA support without framebuffer attachments. */
2175 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2176 return true;
2177
2178 if (!sscreen->info.has_eqaa_surface_allocator ||
2179 util_format_is_depth_or_stencil(format)) {
2180 /* Color without EQAA or depth/stencil. */
2181 if (sample_count > 8 ||
2182 sample_count != storage_sample_count)
2183 return false;
2184 } else {
2185 /* Color with EQAA. */
2186 if (sample_count > 16 ||
2187 storage_sample_count > 8)
2188 return false;
2189 }
2190 }
2191
2192 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2193 PIPE_BIND_SHADER_IMAGE)) {
2194 if (target == PIPE_BUFFER) {
2195 retval |= si_is_vertex_format_supported(
2196 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2197 PIPE_BIND_SHADER_IMAGE));
2198 } else {
2199 if (si_is_sampler_format_supported(screen, format))
2200 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2201 PIPE_BIND_SHADER_IMAGE);
2202 }
2203 }
2204
2205 if ((usage & (PIPE_BIND_RENDER_TARGET |
2206 PIPE_BIND_DISPLAY_TARGET |
2207 PIPE_BIND_SCANOUT |
2208 PIPE_BIND_SHARED |
2209 PIPE_BIND_BLENDABLE)) &&
2210 si_is_colorbuffer_format_supported(format)) {
2211 retval |= usage &
2212 (PIPE_BIND_RENDER_TARGET |
2213 PIPE_BIND_DISPLAY_TARGET |
2214 PIPE_BIND_SCANOUT |
2215 PIPE_BIND_SHARED);
2216 if (!util_format_is_pure_integer(format) &&
2217 !util_format_is_depth_or_stencil(format))
2218 retval |= usage & PIPE_BIND_BLENDABLE;
2219 }
2220
2221 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2222 si_is_zs_format_supported(format)) {
2223 retval |= PIPE_BIND_DEPTH_STENCIL;
2224 }
2225
2226 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2227 retval |= si_is_vertex_format_supported(screen, format,
2228 PIPE_BIND_VERTEX_BUFFER);
2229 }
2230
2231 if ((usage & PIPE_BIND_LINEAR) &&
2232 !util_format_is_compressed(format) &&
2233 !(usage & PIPE_BIND_DEPTH_STENCIL))
2234 retval |= PIPE_BIND_LINEAR;
2235
2236 return retval == usage;
2237 }
2238
2239 /*
2240 * framebuffer handling
2241 */
2242
2243 static void si_choose_spi_color_formats(struct si_surface *surf,
2244 unsigned format, unsigned swap,
2245 unsigned ntype, bool is_depth)
2246 {
2247 /* Alpha is needed for alpha-to-coverage.
2248 * Blending may be with or without alpha.
2249 */
2250 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2251 unsigned alpha = 0; /* exports alpha, but may not support blending */
2252 unsigned blend = 0; /* supports blending, but may not export alpha */
2253 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2254
2255 /* Choose the SPI color formats. These are required values for RB+.
2256 * Other chips have multiple choices, though they are not necessarily better.
2257 */
2258 switch (format) {
2259 case V_028C70_COLOR_5_6_5:
2260 case V_028C70_COLOR_1_5_5_5:
2261 case V_028C70_COLOR_5_5_5_1:
2262 case V_028C70_COLOR_4_4_4_4:
2263 case V_028C70_COLOR_10_11_11:
2264 case V_028C70_COLOR_11_11_10:
2265 case V_028C70_COLOR_8:
2266 case V_028C70_COLOR_8_8:
2267 case V_028C70_COLOR_8_8_8_8:
2268 case V_028C70_COLOR_10_10_10_2:
2269 case V_028C70_COLOR_2_10_10_10:
2270 if (ntype == V_028C70_NUMBER_UINT)
2271 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2272 else if (ntype == V_028C70_NUMBER_SINT)
2273 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2274 else
2275 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2276 break;
2277
2278 case V_028C70_COLOR_16:
2279 case V_028C70_COLOR_16_16:
2280 case V_028C70_COLOR_16_16_16_16:
2281 if (ntype == V_028C70_NUMBER_UNORM ||
2282 ntype == V_028C70_NUMBER_SNORM) {
2283 /* UNORM16 and SNORM16 don't support blending */
2284 if (ntype == V_028C70_NUMBER_UNORM)
2285 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2286 else
2287 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2288
2289 /* Use 32 bits per channel for blending. */
2290 if (format == V_028C70_COLOR_16) {
2291 if (swap == V_028C70_SWAP_STD) { /* R */
2292 blend = V_028714_SPI_SHADER_32_R;
2293 blend_alpha = V_028714_SPI_SHADER_32_AR;
2294 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2295 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2296 else
2297 assert(0);
2298 } else if (format == V_028C70_COLOR_16_16) {
2299 if (swap == V_028C70_SWAP_STD) { /* RG */
2300 blend = V_028714_SPI_SHADER_32_GR;
2301 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2302 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2303 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2304 else
2305 assert(0);
2306 } else /* 16_16_16_16 */
2307 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2308 } else if (ntype == V_028C70_NUMBER_UINT)
2309 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2310 else if (ntype == V_028C70_NUMBER_SINT)
2311 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2312 else if (ntype == V_028C70_NUMBER_FLOAT)
2313 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2314 else
2315 assert(0);
2316 break;
2317
2318 case V_028C70_COLOR_32:
2319 if (swap == V_028C70_SWAP_STD) { /* R */
2320 blend = normal = V_028714_SPI_SHADER_32_R;
2321 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2322 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2323 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2324 else
2325 assert(0);
2326 break;
2327
2328 case V_028C70_COLOR_32_32:
2329 if (swap == V_028C70_SWAP_STD) { /* RG */
2330 blend = normal = V_028714_SPI_SHADER_32_GR;
2331 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2332 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2333 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2334 else
2335 assert(0);
2336 break;
2337
2338 case V_028C70_COLOR_32_32_32_32:
2339 case V_028C70_COLOR_8_24:
2340 case V_028C70_COLOR_24_8:
2341 case V_028C70_COLOR_X24_8_32_FLOAT:
2342 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2343 break;
2344
2345 default:
2346 assert(0);
2347 return;
2348 }
2349
2350 /* The DB->CB copy needs 32_ABGR. */
2351 if (is_depth)
2352 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2353
2354 surf->spi_shader_col_format = normal;
2355 surf->spi_shader_col_format_alpha = alpha;
2356 surf->spi_shader_col_format_blend = blend;
2357 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2358 }
2359
2360 static void si_initialize_color_surface(struct si_context *sctx,
2361 struct si_surface *surf)
2362 {
2363 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2364 unsigned color_info, color_attrib;
2365 unsigned format, swap, ntype, endian;
2366 const struct util_format_description *desc;
2367 int firstchan;
2368 unsigned blend_clamp = 0, blend_bypass = 0;
2369
2370 desc = util_format_description(surf->base.format);
2371 for (firstchan = 0; firstchan < 4; firstchan++) {
2372 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2373 break;
2374 }
2375 }
2376 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2377 ntype = V_028C70_NUMBER_FLOAT;
2378 } else {
2379 ntype = V_028C70_NUMBER_UNORM;
2380 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2381 ntype = V_028C70_NUMBER_SRGB;
2382 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2383 if (desc->channel[firstchan].pure_integer) {
2384 ntype = V_028C70_NUMBER_SINT;
2385 } else {
2386 assert(desc->channel[firstchan].normalized);
2387 ntype = V_028C70_NUMBER_SNORM;
2388 }
2389 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2390 if (desc->channel[firstchan].pure_integer) {
2391 ntype = V_028C70_NUMBER_UINT;
2392 } else {
2393 assert(desc->channel[firstchan].normalized);
2394 ntype = V_028C70_NUMBER_UNORM;
2395 }
2396 }
2397 }
2398
2399 format = si_translate_colorformat(surf->base.format);
2400 if (format == V_028C70_COLOR_INVALID) {
2401 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2402 }
2403 assert(format != V_028C70_COLOR_INVALID);
2404 swap = si_translate_colorswap(surf->base.format, false);
2405 endian = si_colorformat_endian_swap(format);
2406
2407 /* blend clamp should be set for all NORM/SRGB types */
2408 if (ntype == V_028C70_NUMBER_UNORM ||
2409 ntype == V_028C70_NUMBER_SNORM ||
2410 ntype == V_028C70_NUMBER_SRGB)
2411 blend_clamp = 1;
2412
2413 /* set blend bypass according to docs if SINT/UINT or
2414 8/24 COLOR variants */
2415 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2416 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2417 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2418 blend_clamp = 0;
2419 blend_bypass = 1;
2420 }
2421
2422 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2423 if (format == V_028C70_COLOR_8 ||
2424 format == V_028C70_COLOR_8_8 ||
2425 format == V_028C70_COLOR_8_8_8_8)
2426 surf->color_is_int8 = true;
2427 else if (format == V_028C70_COLOR_10_10_10_2 ||
2428 format == V_028C70_COLOR_2_10_10_10)
2429 surf->color_is_int10 = true;
2430 }
2431
2432 color_info = S_028C70_FORMAT(format) |
2433 S_028C70_COMP_SWAP(swap) |
2434 S_028C70_BLEND_CLAMP(blend_clamp) |
2435 S_028C70_BLEND_BYPASS(blend_bypass) |
2436 S_028C70_SIMPLE_FLOAT(1) |
2437 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2438 ntype != V_028C70_NUMBER_SNORM &&
2439 ntype != V_028C70_NUMBER_SRGB &&
2440 format != V_028C70_COLOR_8_24 &&
2441 format != V_028C70_COLOR_24_8) |
2442 S_028C70_NUMBER_TYPE(ntype) |
2443 S_028C70_ENDIAN(endian);
2444
2445 /* Intensity is implemented as Red, so treat it that way. */
2446 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2447 util_format_is_intensity(surf->base.format));
2448
2449 if (tex->buffer.b.b.nr_samples > 1) {
2450 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2451 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2452
2453 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2454 S_028C74_NUM_FRAGMENTS(log_fragments);
2455
2456 if (tex->surface.fmask_size) {
2457 color_info |= S_028C70_COMPRESSION(1);
2458 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2459
2460 if (sctx->chip_class == SI) {
2461 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2462 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2463 }
2464 }
2465 }
2466
2467 if (sctx->chip_class >= VI) {
2468 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2469 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2470
2471 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2472 64 for APU because all of our APUs to date use DIMMs which have
2473 a request granularity size of 64B while all other chips have a
2474 32B request size */
2475 if (!sctx->screen->info.has_dedicated_vram)
2476 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2477
2478 if (tex->buffer.b.b.nr_storage_samples > 1) {
2479 if (tex->surface.bpe == 1)
2480 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2481 else if (tex->surface.bpe == 2)
2482 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2483 }
2484
2485 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2486 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2487 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2488 }
2489
2490 /* This must be set for fast clear to work without FMASK. */
2491 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2492 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2493 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2494 }
2495
2496 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2497 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2498
2499 if (sctx->chip_class >= GFX9) {
2500 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2501
2502 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2503 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2504 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2505 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2506 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2507 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2508 }
2509
2510 surf->cb_color_view = color_view;
2511 surf->cb_color_info = color_info;
2512 surf->cb_color_attrib = color_attrib;
2513
2514 /* Determine pixel shader export format */
2515 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2516
2517 surf->color_initialized = true;
2518 }
2519
2520 static void si_init_depth_surface(struct si_context *sctx,
2521 struct si_surface *surf)
2522 {
2523 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2524 unsigned level = surf->base.u.tex.level;
2525 unsigned format, stencil_format;
2526 uint32_t z_info, s_info;
2527
2528 format = si_translate_dbformat(tex->db_render_format);
2529 stencil_format = tex->surface.has_stencil ?
2530 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2531
2532 assert(format != V_028040_Z_INVALID);
2533 if (format == V_028040_Z_INVALID)
2534 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2535
2536 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2537 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2538 surf->db_htile_data_base = 0;
2539 surf->db_htile_surface = 0;
2540
2541 if (sctx->chip_class >= GFX9) {
2542 assert(tex->surface.u.gfx9.surf_offset == 0);
2543 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2544 surf->db_stencil_base = (tex->buffer.gpu_address +
2545 tex->surface.u.gfx9.stencil_offset) >> 8;
2546 z_info = S_028038_FORMAT(format) |
2547 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2548 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2549 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2550 s_info = S_02803C_FORMAT(stencil_format) |
2551 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2552 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2553 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2554 surf->db_depth_view |= S_028008_MIPID(level);
2555 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2556 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2557
2558 if (si_htile_enabled(tex, level)) {
2559 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2560 S_028038_ALLOW_EXPCLEAR(1);
2561
2562 if (tex->tc_compatible_htile) {
2563 unsigned max_zplanes = 4;
2564
2565 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2566 tex->buffer.b.b.nr_samples > 1)
2567 max_zplanes = 2;
2568
2569 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2570 S_028038_ITERATE_FLUSH(1);
2571 s_info |= S_02803C_ITERATE_FLUSH(1);
2572 }
2573
2574 if (tex->surface.has_stencil) {
2575 /* Stencil buffer workaround ported from the SI-CI-VI code.
2576 * See that for explanation.
2577 */
2578 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2579 } else {
2580 /* Use all HTILE for depth if there's no stencil. */
2581 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2582 }
2583
2584 surf->db_htile_data_base = (tex->buffer.gpu_address +
2585 tex->htile_offset) >> 8;
2586 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2587 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2588 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2589 }
2590 } else {
2591 /* SI-CI-VI */
2592 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2593
2594 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2595
2596 surf->db_depth_base = (tex->buffer.gpu_address +
2597 tex->surface.u.legacy.level[level].offset) >> 8;
2598 surf->db_stencil_base = (tex->buffer.gpu_address +
2599 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2600
2601 z_info = S_028040_FORMAT(format) |
2602 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2603 s_info = S_028044_FORMAT(stencil_format);
2604 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2605
2606 if (sctx->chip_class >= CIK) {
2607 struct radeon_info *info = &sctx->screen->info;
2608 unsigned index = tex->surface.u.legacy.tiling_index[level];
2609 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2610 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2611 unsigned tile_mode = info->si_tile_mode_array[index];
2612 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2613 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2614
2615 surf->db_depth_info |=
2616 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2617 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2618 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2619 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2620 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2621 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2622 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2623 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2624 } else {
2625 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2626 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2627 tile_mode_index = si_tile_mode_index(tex, level, true);
2628 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2629 }
2630
2631 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2632 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2633 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2634 levelinfo->nblk_y) / 64 - 1);
2635
2636 if (si_htile_enabled(tex, level)) {
2637 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2638 S_028040_ALLOW_EXPCLEAR(1);
2639
2640 if (tex->surface.has_stencil) {
2641 /* Workaround: For a not yet understood reason, the
2642 * combination of MSAA, fast stencil clear and stencil
2643 * decompress messes with subsequent stencil buffer
2644 * uses. Problem was reproduced on Verde, Bonaire,
2645 * Tonga, and Carrizo.
2646 *
2647 * Disabling EXPCLEAR works around the problem.
2648 *
2649 * Check piglit's arb_texture_multisample-stencil-clear
2650 * test if you want to try changing this.
2651 */
2652 if (tex->buffer.b.b.nr_samples <= 1)
2653 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2654 } else if (!tex->tc_compatible_htile) {
2655 /* Use all of the htile_buffer for depth if there's no stencil.
2656 * This must not be set when TC-compatible HTILE is enabled
2657 * due to a hw bug.
2658 */
2659 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2660 }
2661
2662 surf->db_htile_data_base = (tex->buffer.gpu_address +
2663 tex->htile_offset) >> 8;
2664 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2665
2666 if (tex->tc_compatible_htile) {
2667 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2668
2669 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2670 if (tex->buffer.b.b.nr_samples <= 1)
2671 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2672 else if (tex->buffer.b.b.nr_samples <= 4)
2673 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2674 else
2675 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2676 }
2677 }
2678 }
2679
2680 surf->db_z_info = z_info;
2681 surf->db_stencil_info = s_info;
2682
2683 surf->depth_initialized = true;
2684 }
2685
2686 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2687 {
2688 if (sctx->decompression_enabled)
2689 return;
2690
2691 if (sctx->framebuffer.state.zsbuf) {
2692 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2693 struct si_texture *tex = (struct si_texture *)surf->texture;
2694
2695 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2696
2697 if (tex->surface.has_stencil)
2698 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2699 }
2700
2701 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2702 while (compressed_cb_mask) {
2703 unsigned i = u_bit_scan(&compressed_cb_mask);
2704 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2705 struct si_texture *tex = (struct si_texture*)surf->texture;
2706
2707 if (tex->surface.fmask_size)
2708 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2709 if (tex->dcc_gather_statistics)
2710 tex->separate_dcc_dirty = true;
2711 }
2712 }
2713
2714 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2715 {
2716 for (int i = 0; i < state->nr_cbufs; ++i) {
2717 struct si_surface *surf = NULL;
2718 struct si_texture *tex;
2719
2720 if (!state->cbufs[i])
2721 continue;
2722 surf = (struct si_surface*)state->cbufs[i];
2723 tex = (struct si_texture*)surf->base.texture;
2724
2725 p_atomic_dec(&tex->framebuffers_bound);
2726 }
2727 }
2728
2729 static void si_set_framebuffer_state(struct pipe_context *ctx,
2730 const struct pipe_framebuffer_state *state)
2731 {
2732 struct si_context *sctx = (struct si_context *)ctx;
2733 struct si_surface *surf = NULL;
2734 struct si_texture *tex;
2735 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2736 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2737 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2738 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2739 bool old_has_stencil =
2740 old_has_zsbuf &&
2741 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2742 bool unbound = false;
2743 int i;
2744
2745 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2746 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2747 * We could implement the full workaround here, but it's a useless case.
2748 */
2749 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2750 unreachable("the framebuffer shouldn't have zero area");
2751 return;
2752 }
2753
2754 si_update_fb_dirtiness_after_rendering(sctx);
2755
2756 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2757 if (!sctx->framebuffer.state.cbufs[i])
2758 continue;
2759
2760 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2761 if (tex->dcc_gather_statistics)
2762 vi_separate_dcc_stop_query(sctx, tex);
2763 }
2764
2765 /* Disable DCC if the formats are incompatible. */
2766 for (i = 0; i < state->nr_cbufs; i++) {
2767 if (!state->cbufs[i])
2768 continue;
2769
2770 surf = (struct si_surface*)state->cbufs[i];
2771 tex = (struct si_texture*)surf->base.texture;
2772
2773 if (!surf->dcc_incompatible)
2774 continue;
2775
2776 /* Since the DCC decompression calls back into set_framebuffer-
2777 * _state, we need to unbind the framebuffer, so that
2778 * vi_separate_dcc_stop_query isn't called twice with the same
2779 * color buffer.
2780 */
2781 if (!unbound) {
2782 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2783 unbound = true;
2784 }
2785
2786 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2787 if (!si_texture_disable_dcc(sctx, tex))
2788 si_decompress_dcc(sctx, tex);
2789
2790 surf->dcc_incompatible = false;
2791 }
2792
2793 /* Only flush TC when changing the framebuffer state, because
2794 * the only client not using TC that can change textures is
2795 * the framebuffer.
2796 *
2797 * Wait for compute shaders because of possible transitions:
2798 * - FB write -> shader read
2799 * - shader write -> FB read
2800 *
2801 * DB caches are flushed on demand (using si_decompress_textures).
2802 *
2803 * When MSAA is enabled, CB and TC caches are flushed on demand
2804 * (after FMASK decompression). Shader write -> FB read transitions
2805 * cannot happen for MSAA textures, because MSAA shader images are
2806 * not supported.
2807 *
2808 * Only flush and wait for CB if there is actually a bound color buffer.
2809 */
2810 if (sctx->framebuffer.uncompressed_cb_mask)
2811 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2812 sctx->framebuffer.CB_has_shader_readable_metadata);
2813
2814 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2815
2816 /* u_blitter doesn't invoke depth decompression when it does multiple
2817 * blits in a row, but the only case when it matters for DB is when
2818 * doing generate_mipmap. So here we flush DB manually between
2819 * individual generate_mipmap blits.
2820 * Note that lower mipmap levels aren't compressed.
2821 */
2822 if (sctx->generate_mipmap_for_depth) {
2823 si_make_DB_shader_coherent(sctx, 1, false,
2824 sctx->framebuffer.DB_has_shader_readable_metadata);
2825 } else if (sctx->chip_class == GFX9) {
2826 /* It appears that DB metadata "leaks" in a sequence of:
2827 * - depth clear
2828 * - DCC decompress for shader image writes (with DB disabled)
2829 * - render with DEPTH_BEFORE_SHADER=1
2830 * Flushing DB metadata works around the problem.
2831 */
2832 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2833 }
2834
2835 /* Take the maximum of the old and new count. If the new count is lower,
2836 * dirtying is needed to disable the unbound colorbuffers.
2837 */
2838 sctx->framebuffer.dirty_cbufs |=
2839 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2840 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2841
2842 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2843 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2844
2845 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2846 sctx->framebuffer.spi_shader_col_format = 0;
2847 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2848 sctx->framebuffer.spi_shader_col_format_blend = 0;
2849 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2850 sctx->framebuffer.color_is_int8 = 0;
2851 sctx->framebuffer.color_is_int10 = 0;
2852
2853 sctx->framebuffer.compressed_cb_mask = 0;
2854 sctx->framebuffer.uncompressed_cb_mask = 0;
2855 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2856 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2857 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2858 sctx->framebuffer.any_dst_linear = false;
2859 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2860 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2861 unsigned num_bpp64_colorbufs = 0;
2862
2863 for (i = 0; i < state->nr_cbufs; i++) {
2864 if (!state->cbufs[i])
2865 continue;
2866
2867 surf = (struct si_surface*)state->cbufs[i];
2868 tex = (struct si_texture*)surf->base.texture;
2869
2870 if (!surf->color_initialized) {
2871 si_initialize_color_surface(sctx, surf);
2872 }
2873
2874 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2875 sctx->framebuffer.spi_shader_col_format |=
2876 surf->spi_shader_col_format << (i * 4);
2877 sctx->framebuffer.spi_shader_col_format_alpha |=
2878 surf->spi_shader_col_format_alpha << (i * 4);
2879 sctx->framebuffer.spi_shader_col_format_blend |=
2880 surf->spi_shader_col_format_blend << (i * 4);
2881 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2882 surf->spi_shader_col_format_blend_alpha << (i * 4);
2883
2884 if (surf->color_is_int8)
2885 sctx->framebuffer.color_is_int8 |= 1 << i;
2886 if (surf->color_is_int10)
2887 sctx->framebuffer.color_is_int10 |= 1 << i;
2888
2889 if (tex->surface.fmask_size)
2890 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2891 else
2892 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2893
2894 /* Don't update nr_color_samples for non-AA buffers.
2895 * (e.g. destination of MSAA resolve)
2896 */
2897 if (tex->buffer.b.b.nr_samples >= 2 &&
2898 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2899 sctx->framebuffer.nr_color_samples =
2900 MIN2(sctx->framebuffer.nr_color_samples,
2901 tex->buffer.b.b.nr_storage_samples);
2902 sctx->framebuffer.nr_color_samples =
2903 MAX2(1, sctx->framebuffer.nr_color_samples);
2904 }
2905
2906 if (tex->surface.is_linear)
2907 sctx->framebuffer.any_dst_linear = true;
2908 if (tex->surface.bpe >= 8)
2909 num_bpp64_colorbufs++;
2910
2911 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2912 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2913
2914 si_context_add_resource_size(sctx, surf->base.texture);
2915
2916 p_atomic_inc(&tex->framebuffers_bound);
2917
2918 if (tex->dcc_gather_statistics) {
2919 /* Dirty tracking must be enabled for DCC usage analysis. */
2920 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2921 vi_separate_dcc_start_query(sctx, tex);
2922 }
2923 }
2924
2925 /* For optimal DCC performance. */
2926 if (sctx->chip_class == VI)
2927 sctx->framebuffer.dcc_overwrite_combiner_watermark = 4;
2928 else if (num_bpp64_colorbufs >= 5)
2929 sctx->framebuffer.dcc_overwrite_combiner_watermark = 8;
2930 else
2931 sctx->framebuffer.dcc_overwrite_combiner_watermark = 6;
2932
2933 struct si_texture *zstex = NULL;
2934
2935 if (state->zsbuf) {
2936 surf = (struct si_surface*)state->zsbuf;
2937 zstex = (struct si_texture*)surf->base.texture;
2938
2939 if (!surf->depth_initialized) {
2940 si_init_depth_surface(sctx, surf);
2941 }
2942
2943 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2944 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2945
2946 si_context_add_resource_size(sctx, surf->base.texture);
2947 }
2948
2949 si_update_ps_colorbuf0_slot(sctx);
2950 si_update_poly_offset_state(sctx);
2951 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2952 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2953
2954 if (sctx->screen->dpbb_allowed)
2955 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2956
2957 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2958 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2959
2960 if (sctx->screen->has_out_of_order_rast &&
2961 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2962 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2963 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2964 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2965
2966 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2967 struct pipe_constant_buffer constbuf = {0};
2968
2969 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2970 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2971
2972 constbuf.buffer = sctx->sample_pos_buffer;
2973
2974 /* Set sample locations as fragment shader constants. */
2975 switch (sctx->framebuffer.nr_samples) {
2976 case 1:
2977 constbuf.buffer_offset = 0;
2978 break;
2979 case 2:
2980 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
2981 (ubyte*)sctx->sample_positions.x1;
2982 break;
2983 case 4:
2984 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
2985 (ubyte*)sctx->sample_positions.x1;
2986 break;
2987 case 8:
2988 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
2989 (ubyte*)sctx->sample_positions.x1;
2990 break;
2991 case 16:
2992 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
2993 (ubyte*)sctx->sample_positions.x1;
2994 break;
2995 default:
2996 PRINT_ERR("Requested an invalid number of samples %i.\n",
2997 sctx->framebuffer.nr_samples);
2998 assert(0);
2999 }
3000 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
3001 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
3002
3003 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3004 }
3005
3006 sctx->do_update_shaders = true;
3007
3008 if (!sctx->decompression_enabled) {
3009 /* Prevent textures decompression when the framebuffer state
3010 * changes come from the decompression passes themselves.
3011 */
3012 sctx->need_check_render_feedback = true;
3013 }
3014 }
3015
3016 static void si_emit_framebuffer_state(struct si_context *sctx)
3017 {
3018 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3019 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
3020 unsigned i, nr_cbufs = state->nr_cbufs;
3021 struct si_texture *tex = NULL;
3022 struct si_surface *cb = NULL;
3023 unsigned cb_color_info = 0;
3024
3025 /* Colorbuffers. */
3026 for (i = 0; i < nr_cbufs; i++) {
3027 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3028 unsigned cb_color_attrib;
3029
3030 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3031 continue;
3032
3033 cb = (struct si_surface*)state->cbufs[i];
3034 if (!cb) {
3035 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3036 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3037 continue;
3038 }
3039
3040 tex = (struct si_texture *)cb->base.texture;
3041 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3042 &tex->buffer, RADEON_USAGE_READWRITE,
3043 tex->buffer.b.b.nr_samples > 1 ?
3044 RADEON_PRIO_COLOR_BUFFER_MSAA :
3045 RADEON_PRIO_COLOR_BUFFER);
3046
3047 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3048 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3049 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3050 RADEON_PRIO_SEPARATE_META);
3051 }
3052
3053 if (tex->dcc_separate_buffer)
3054 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3055 tex->dcc_separate_buffer,
3056 RADEON_USAGE_READWRITE,
3057 RADEON_PRIO_SEPARATE_META);
3058
3059 /* Compute mutable surface parameters. */
3060 cb_color_base = tex->buffer.gpu_address >> 8;
3061 cb_color_fmask = 0;
3062 cb_color_cmask = tex->cmask_base_address_reg;
3063 cb_dcc_base = 0;
3064 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3065 cb_color_attrib = cb->cb_color_attrib;
3066
3067 if (cb->base.u.tex.level > 0)
3068 cb_color_info &= C_028C70_FAST_CLEAR;
3069
3070 if (tex->surface.fmask_size) {
3071 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3072 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3073 }
3074
3075 /* Set up DCC. */
3076 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3077 bool is_msaa_resolve_dst = state->cbufs[0] &&
3078 state->cbufs[0]->texture->nr_samples > 1 &&
3079 state->cbufs[1] == &cb->base &&
3080 state->cbufs[1]->texture->nr_samples <= 1;
3081
3082 if (!is_msaa_resolve_dst)
3083 cb_color_info |= S_028C70_DCC_ENABLE(1);
3084
3085 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3086 tex->dcc_offset) >> 8;
3087 cb_dcc_base |= tex->surface.tile_swizzle;
3088 }
3089
3090 if (sctx->chip_class >= GFX9) {
3091 struct gfx9_surf_meta_flags meta;
3092
3093 if (tex->dcc_offset)
3094 meta = tex->surface.u.gfx9.dcc;
3095 else
3096 meta = tex->surface.u.gfx9.cmask;
3097
3098 /* Set mutable surface parameters. */
3099 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3100 cb_color_base |= tex->surface.tile_swizzle;
3101 if (!tex->surface.fmask_size)
3102 cb_color_fmask = cb_color_base;
3103 if (cb->base.u.tex.level > 0)
3104 cb_color_cmask = cb_color_base;
3105 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3106 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3107 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3108 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3109
3110 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3111 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3112 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3113 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3114 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3115 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3116 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3117 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3118 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3119 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3120 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3121 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3122 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3123 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3124 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3125 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3126
3127 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3128 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3129 } else {
3130 /* Compute mutable surface parameters (SI-CI-VI). */
3131 const struct legacy_surf_level *level_info =
3132 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3133 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3134 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3135
3136 cb_color_base += level_info->offset >> 8;
3137 /* Only macrotiled modes can set tile swizzle. */
3138 if (level_info->mode == RADEON_SURF_MODE_2D)
3139 cb_color_base |= tex->surface.tile_swizzle;
3140
3141 if (!tex->surface.fmask_size)
3142 cb_color_fmask = cb_color_base;
3143 if (cb->base.u.tex.level > 0)
3144 cb_color_cmask = cb_color_base;
3145 if (cb_dcc_base)
3146 cb_dcc_base += level_info->dcc_offset >> 8;
3147
3148 pitch_tile_max = level_info->nblk_x / 8 - 1;
3149 slice_tile_max = level_info->nblk_x *
3150 level_info->nblk_y / 64 - 1;
3151 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3152
3153 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3154 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3155 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3156
3157 if (tex->surface.fmask_size) {
3158 if (sctx->chip_class >= CIK)
3159 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3160 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3161 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3162 } else {
3163 /* This must be set for fast clear to work without FMASK. */
3164 if (sctx->chip_class >= CIK)
3165 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3166 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3167 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3168 }
3169
3170 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3171 sctx->chip_class >= VI ? 14 : 13);
3172 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3173 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3174 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3175 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3176 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3177 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3178 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3179 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3180 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3181 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3182 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3183 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3184 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3185
3186 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3187 radeon_emit(cs, cb_dcc_base);
3188 }
3189 }
3190 for (; i < 8 ; i++)
3191 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3192 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3193
3194 /* ZS buffer. */
3195 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3196 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3197 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3198
3199 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3200 &tex->buffer, RADEON_USAGE_READWRITE,
3201 zb->base.texture->nr_samples > 1 ?
3202 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3203 RADEON_PRIO_DEPTH_BUFFER);
3204
3205 if (sctx->chip_class >= GFX9) {
3206 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3207 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3208 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3209 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3210
3211 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3212 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3213 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3214 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3215 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3216 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3217 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3218 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3219 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3220 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3221 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3222 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3223
3224 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3225 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3226 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3227 } else {
3228 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3229
3230 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3231 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3232 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3233 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3234 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3235 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3236 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3237 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3238 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3239 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3240 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3241 }
3242
3243 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3244 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3245 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3246
3247 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3248 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3249 } else if (sctx->framebuffer.dirty_zsbuf) {
3250 if (sctx->chip_class >= GFX9)
3251 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3252 else
3253 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3254
3255 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3256 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3257 }
3258
3259 /* Framebuffer dimensions. */
3260 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3261 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3262 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3263
3264 if (sctx->screen->dfsm_allowed) {
3265 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3266 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3267 }
3268
3269 sctx->framebuffer.dirty_cbufs = 0;
3270 sctx->framebuffer.dirty_zsbuf = false;
3271 }
3272
3273 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3274 {
3275 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3276 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3277 unsigned nr_samples = sctx->framebuffer.nr_samples;
3278 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3279
3280 /* Smoothing (only possible with nr_samples == 1) uses the same
3281 * sample locations as the MSAA it simulates.
3282 */
3283 if (nr_samples <= 1 && sctx->smoothing_enabled)
3284 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3285
3286 /* On Polaris, the small primitive filter uses the sample locations
3287 * even when MSAA is off, so we need to make sure they're set to 0.
3288 */
3289 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3290 nr_samples != sctx->sample_locs_num_samples) {
3291 sctx->sample_locs_num_samples = nr_samples;
3292 si_emit_sample_locations(cs, nr_samples);
3293 }
3294
3295 if (sctx->family >= CHIP_POLARIS10) {
3296 unsigned small_prim_filter_cntl =
3297 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3298 /* line bug */
3299 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3300
3301 /* The alternative of setting sample locations to 0 would
3302 * require a DB flush to avoid Z errors, see
3303 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3304 */
3305 if (has_msaa_sample_loc_bug &&
3306 sctx->framebuffer.nr_samples > 1 &&
3307 !rs->multisample_enable)
3308 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3309
3310 radeon_opt_set_context_reg(sctx,
3311 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3312 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3313 small_prim_filter_cntl);
3314 }
3315
3316 /* The exclusion bits can be set to improve rasterization efficiency
3317 * if no sample lies on the pixel boundary (-8 sample offset).
3318 */
3319 bool exclusion = sctx->chip_class >= CIK &&
3320 (!rs->multisample_enable || nr_samples != 16);
3321 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3322 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3323 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3324 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3325 }
3326
3327 static bool si_out_of_order_rasterization(struct si_context *sctx)
3328 {
3329 struct si_state_blend *blend = sctx->queued.named.blend;
3330 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3331
3332 if (!sctx->screen->has_out_of_order_rast)
3333 return false;
3334
3335 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3336
3337 if (blend) {
3338 colormask &= blend->cb_target_enabled_4bit;
3339 } else {
3340 colormask = 0;
3341 }
3342
3343 /* Conservative: No logic op. */
3344 if (colormask && blend->logicop_enable)
3345 return false;
3346
3347 struct si_dsa_order_invariance dsa_order_invariant = {
3348 .zs = true, .pass_set = true, .pass_last = false
3349 };
3350
3351 if (sctx->framebuffer.state.zsbuf) {
3352 struct si_texture *zstex =
3353 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3354 bool has_stencil = zstex->surface.has_stencil;
3355 dsa_order_invariant = dsa->order_invariance[has_stencil];
3356 if (!dsa_order_invariant.zs)
3357 return false;
3358
3359 /* The set of PS invocations is always order invariant,
3360 * except when early Z/S tests are requested. */
3361 if (sctx->ps_shader.cso &&
3362 sctx->ps_shader.cso->info.writes_memory &&
3363 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3364 !dsa_order_invariant.pass_set)
3365 return false;
3366
3367 if (sctx->num_perfect_occlusion_queries != 0 &&
3368 !dsa_order_invariant.pass_set)
3369 return false;
3370 }
3371
3372 if (!colormask)
3373 return true;
3374
3375 unsigned blendmask = colormask & blend->blend_enable_4bit;
3376
3377 if (blendmask) {
3378 /* Only commutative blending. */
3379 if (blendmask & ~blend->commutative_4bit)
3380 return false;
3381
3382 if (!dsa_order_invariant.pass_set)
3383 return false;
3384 }
3385
3386 if (colormask & ~blendmask) {
3387 if (!dsa_order_invariant.pass_last)
3388 return false;
3389 }
3390
3391 return true;
3392 }
3393
3394 static void si_emit_msaa_config(struct si_context *sctx)
3395 {
3396 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3397 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3398 /* 33% faster rendering to linear color buffers */
3399 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3400 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3401 unsigned sc_mode_cntl_1 =
3402 S_028A4C_WALK_SIZE(dst_is_linear) |
3403 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3404 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3405 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3406 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3407 /* always 1: */
3408 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3409 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3410 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3411 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3412 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3413 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3414 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3415 S_028804_INCOHERENT_EQAA_READS(1) |
3416 S_028804_INTERPOLATE_COMP_Z(1) |
3417 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3418 unsigned coverage_samples, color_samples, z_samples;
3419
3420 /* S: Coverage samples (up to 16x):
3421 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3422 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3423 *
3424 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3425 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3426 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3427 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3428 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3429 * # Z samples).
3430 *
3431 * F: Color samples (up to 8x, must be <= coverage samples):
3432 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3433 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3434 *
3435 * Can be anything between coverage and color samples:
3436 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3437 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3438 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3439 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3440 * # All are currently set the same as coverage samples.
3441 *
3442 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3443 * flag for undefined color samples. A shader-based resolve must handle unknowns
3444 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3445 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3446 * useful. The CB resolve always drops unknowns.
3447 *
3448 * Sensible AA configurations:
3449 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3450 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3451 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3452 * EQAA 8s 8z 8f = 8x MSAA
3453 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3454 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3455 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3456 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3457 * EQAA 4s 4z 4f = 4x MSAA
3458 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3459 * EQAA 2s 2z 2f = 2x MSAA
3460 */
3461 if (sctx->framebuffer.nr_samples > 1) {
3462 coverage_samples = sctx->framebuffer.nr_samples;
3463 color_samples = sctx->framebuffer.nr_color_samples;
3464
3465 if (sctx->framebuffer.state.zsbuf) {
3466 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3467 z_samples = MAX2(1, z_samples);
3468 } else {
3469 z_samples = coverage_samples;
3470 }
3471 } else if (sctx->smoothing_enabled) {
3472 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3473 } else {
3474 coverage_samples = color_samples = z_samples = 1;
3475 }
3476
3477 /* Required by OpenGL line rasterization.
3478 *
3479 * TODO: We should also enable perpendicular endcaps for AA lines,
3480 * but that requires implementing line stippling in the pixel
3481 * shader. SC can only do line stippling with axis-aligned
3482 * endcaps.
3483 */
3484 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3485 unsigned sc_aa_config = 0;
3486
3487 if (coverage_samples > 1) {
3488 /* distance from the pixel center, indexed by log2(nr_samples) */
3489 static unsigned max_dist[] = {
3490 0, /* unused */
3491 4, /* 2x MSAA */
3492 6, /* 4x MSAA */
3493 7, /* 8x MSAA */
3494 8, /* 16x MSAA */
3495 };
3496 unsigned log_samples = util_logbase2(coverage_samples);
3497 unsigned log_z_samples = util_logbase2(z_samples);
3498 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3499 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3500
3501 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3502 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3503 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3504 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3505
3506 if (sctx->framebuffer.nr_samples > 1) {
3507 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3508 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3509 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3510 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3511 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3512 } else if (sctx->smoothing_enabled) {
3513 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3514 }
3515 }
3516
3517 unsigned initial_cdw = cs->current.cdw;
3518
3519 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3520 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3521 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3522 sc_aa_config);
3523 /* R_028804_DB_EQAA */
3524 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3525 db_eqaa);
3526 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3527 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3528 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3529
3530 if (initial_cdw != cs->current.cdw) {
3531 sctx->context_roll_counter++;
3532
3533 /* GFX9: Flush DFSM when the AA mode changes. */
3534 if (sctx->screen->dfsm_allowed) {
3535 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3536 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3537 }
3538 }
3539 }
3540
3541 void si_update_ps_iter_samples(struct si_context *sctx)
3542 {
3543 if (sctx->framebuffer.nr_samples > 1)
3544 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3545 if (sctx->screen->dpbb_allowed)
3546 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3547 }
3548
3549 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3550 {
3551 struct si_context *sctx = (struct si_context *)ctx;
3552
3553 /* The hardware can only do sample shading with 2^n samples. */
3554 min_samples = util_next_power_of_two(min_samples);
3555
3556 if (sctx->ps_iter_samples == min_samples)
3557 return;
3558
3559 sctx->ps_iter_samples = min_samples;
3560 sctx->do_update_shaders = true;
3561
3562 si_update_ps_iter_samples(sctx);
3563 }
3564
3565 /*
3566 * Samplers
3567 */
3568
3569 /**
3570 * Build the sampler view descriptor for a buffer texture.
3571 * @param state 256-bit descriptor; only the high 128 bits are filled in
3572 */
3573 void
3574 si_make_buffer_descriptor(struct si_screen *screen, struct si_resource *buf,
3575 enum pipe_format format,
3576 unsigned offset, unsigned size,
3577 uint32_t *state)
3578 {
3579 const struct util_format_description *desc;
3580 int first_non_void;
3581 unsigned stride;
3582 unsigned num_records;
3583 unsigned num_format, data_format;
3584
3585 desc = util_format_description(format);
3586 first_non_void = util_format_get_first_non_void_channel(format);
3587 stride = desc->block.bits / 8;
3588 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3589 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3590
3591 num_records = size / stride;
3592 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3593
3594 /* The NUM_RECORDS field has a different meaning depending on the chip,
3595 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3596 *
3597 * SI-CIK:
3598 * - If STRIDE == 0, it's in byte units.
3599 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3600 *
3601 * VI:
3602 * - For SMEM and STRIDE == 0, it's in byte units.
3603 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3604 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3605 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3606 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3607 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3608 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3609 * That way the same descriptor can be used by both SMEM and VMEM.
3610 *
3611 * GFX9:
3612 * - For SMEM and STRIDE == 0, it's in byte units.
3613 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3614 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3615 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3616 */
3617 if (screen->info.chip_class >= GFX9 && HAVE_LLVM < 0x0800)
3618 /* When vindex == 0, LLVM < 8.0 sets IDXEN = 0, thus changing units
3619 * from STRIDE to bytes. This works around it by setting
3620 * NUM_RECORDS to at least the size of one element, so that
3621 * the first element is readable when IDXEN == 0.
3622 */
3623 num_records = num_records ? MAX2(num_records, stride) : 0;
3624 else if (screen->info.chip_class == VI)
3625 num_records *= stride;
3626
3627 state[4] = 0;
3628 state[5] = S_008F04_STRIDE(stride);
3629 state[6] = num_records;
3630 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3631 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3632 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3633 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3634 S_008F0C_NUM_FORMAT(num_format) |
3635 S_008F0C_DATA_FORMAT(data_format);
3636 }
3637
3638 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3639 {
3640 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3641
3642 if (swizzle[3] == PIPE_SWIZZLE_X) {
3643 /* For the pre-defined border color values (white, opaque
3644 * black, transparent black), the only thing that matters is
3645 * that the alpha channel winds up in the correct place
3646 * (because the RGB channels are all the same) so either of
3647 * these enumerations will work.
3648 */
3649 if (swizzle[2] == PIPE_SWIZZLE_Y)
3650 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3651 else
3652 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3653 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3654 if (swizzle[1] == PIPE_SWIZZLE_Y)
3655 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3656 else
3657 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3658 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3659 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3660 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3661 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3662 }
3663
3664 return bc_swizzle;
3665 }
3666
3667 /**
3668 * Build the sampler view descriptor for a texture.
3669 */
3670 void
3671 si_make_texture_descriptor(struct si_screen *screen,
3672 struct si_texture *tex,
3673 bool sampler,
3674 enum pipe_texture_target target,
3675 enum pipe_format pipe_format,
3676 const unsigned char state_swizzle[4],
3677 unsigned first_level, unsigned last_level,
3678 unsigned first_layer, unsigned last_layer,
3679 unsigned width, unsigned height, unsigned depth,
3680 uint32_t *state,
3681 uint32_t *fmask_state)
3682 {
3683 struct pipe_resource *res = &tex->buffer.b.b;
3684 const struct util_format_description *desc;
3685 unsigned char swizzle[4];
3686 int first_non_void;
3687 unsigned num_format, data_format, type, num_samples;
3688 uint64_t va;
3689
3690 desc = util_format_description(pipe_format);
3691
3692 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3693 MAX2(1, res->nr_samples) :
3694 MAX2(1, res->nr_storage_samples);
3695
3696 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3697 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3698 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3699 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3700
3701 switch (pipe_format) {
3702 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3703 case PIPE_FORMAT_X32_S8X24_UINT:
3704 case PIPE_FORMAT_X8Z24_UNORM:
3705 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3706 break;
3707 case PIPE_FORMAT_X24S8_UINT:
3708 /*
3709 * X24S8 is implemented as an 8_8_8_8 data format, to
3710 * fix texture gathers. This affects at least
3711 * GL45-CTS.texture_cube_map_array.sampling on VI.
3712 */
3713 if (screen->info.chip_class <= VI)
3714 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3715 else
3716 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3717 break;
3718 default:
3719 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3720 }
3721 } else {
3722 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3723 }
3724
3725 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3726
3727 switch (pipe_format) {
3728 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3729 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3730 break;
3731 default:
3732 if (first_non_void < 0) {
3733 if (util_format_is_compressed(pipe_format)) {
3734 switch (pipe_format) {
3735 case PIPE_FORMAT_DXT1_SRGB:
3736 case PIPE_FORMAT_DXT1_SRGBA:
3737 case PIPE_FORMAT_DXT3_SRGBA:
3738 case PIPE_FORMAT_DXT5_SRGBA:
3739 case PIPE_FORMAT_BPTC_SRGBA:
3740 case PIPE_FORMAT_ETC2_SRGB8:
3741 case PIPE_FORMAT_ETC2_SRGB8A1:
3742 case PIPE_FORMAT_ETC2_SRGBA8:
3743 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3744 break;
3745 case PIPE_FORMAT_RGTC1_SNORM:
3746 case PIPE_FORMAT_LATC1_SNORM:
3747 case PIPE_FORMAT_RGTC2_SNORM:
3748 case PIPE_FORMAT_LATC2_SNORM:
3749 case PIPE_FORMAT_ETC2_R11_SNORM:
3750 case PIPE_FORMAT_ETC2_RG11_SNORM:
3751 /* implies float, so use SNORM/UNORM to determine
3752 whether data is signed or not */
3753 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3754 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3755 break;
3756 default:
3757 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3758 break;
3759 }
3760 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3761 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3762 } else {
3763 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3764 }
3765 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3766 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3767 } else {
3768 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3769
3770 switch (desc->channel[first_non_void].type) {
3771 case UTIL_FORMAT_TYPE_FLOAT:
3772 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3773 break;
3774 case UTIL_FORMAT_TYPE_SIGNED:
3775 if (desc->channel[first_non_void].normalized)
3776 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3777 else if (desc->channel[first_non_void].pure_integer)
3778 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3779 else
3780 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3781 break;
3782 case UTIL_FORMAT_TYPE_UNSIGNED:
3783 if (desc->channel[first_non_void].normalized)
3784 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3785 else if (desc->channel[first_non_void].pure_integer)
3786 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3787 else
3788 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3789 }
3790 }
3791 }
3792
3793 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3794 if (data_format == ~0) {
3795 data_format = 0;
3796 }
3797
3798 /* S8 with Z32 HTILE needs a special format. */
3799 if (screen->info.chip_class >= GFX9 &&
3800 pipe_format == PIPE_FORMAT_S8_UINT &&
3801 tex->tc_compatible_htile)
3802 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3803
3804 if (!sampler &&
3805 (res->target == PIPE_TEXTURE_CUBE ||
3806 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3807 (screen->info.chip_class <= VI &&
3808 res->target == PIPE_TEXTURE_3D))) {
3809 /* For the purpose of shader images, treat cube maps and 3D
3810 * textures as 2D arrays. For 3D textures, the address
3811 * calculations for mipmaps are different, so we rely on the
3812 * caller to effectively disable mipmaps.
3813 */
3814 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3815
3816 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3817 } else {
3818 type = si_tex_dim(screen, tex, target, num_samples);
3819 }
3820
3821 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3822 height = 1;
3823 depth = res->array_size;
3824 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3825 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3826 if (sampler || res->target != PIPE_TEXTURE_3D)
3827 depth = res->array_size;
3828 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3829 depth = res->array_size / 6;
3830
3831 state[0] = 0;
3832 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3833 S_008F14_NUM_FORMAT_GFX6(num_format));
3834 state[2] = (S_008F18_WIDTH(width - 1) |
3835 S_008F18_HEIGHT(height - 1) |
3836 S_008F18_PERF_MOD(4));
3837 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3838 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3839 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3840 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3841 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3842 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3843 util_logbase2(num_samples) :
3844 last_level) |
3845 S_008F1C_TYPE(type));
3846 state[4] = 0;
3847 state[5] = S_008F24_BASE_ARRAY(first_layer);
3848 state[6] = 0;
3849 state[7] = 0;
3850
3851 if (screen->info.chip_class >= GFX9) {
3852 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3853
3854 /* Depth is the the last accessible layer on Gfx9.
3855 * The hw doesn't need to know the total number of layers.
3856 */
3857 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3858 state[4] |= S_008F20_DEPTH(depth - 1);
3859 else
3860 state[4] |= S_008F20_DEPTH(last_layer);
3861
3862 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3863 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3864 util_logbase2(num_samples) :
3865 tex->buffer.b.b.last_level);
3866 } else {
3867 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3868 state[4] |= S_008F20_DEPTH(depth - 1);
3869 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3870 }
3871
3872 if (tex->dcc_offset) {
3873 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3874 } else {
3875 /* The last dword is unused by hw. The shader uses it to clear
3876 * bits in the first dword of sampler state.
3877 */
3878 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3879 if (first_level == last_level)
3880 state[7] = C_008F30_MAX_ANISO_RATIO;
3881 else
3882 state[7] = 0xffffffff;
3883 }
3884 }
3885
3886 /* Initialize the sampler view for FMASK. */
3887 if (tex->surface.fmask_size) {
3888 uint32_t data_format, num_format;
3889
3890 va = tex->buffer.gpu_address + tex->fmask_offset;
3891
3892 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3893 if (screen->info.chip_class >= GFX9) {
3894 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3895 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3896 case FMASK(2,1):
3897 num_format = V_008F14_IMG_FMASK_8_2_1;
3898 break;
3899 case FMASK(2,2):
3900 num_format = V_008F14_IMG_FMASK_8_2_2;
3901 break;
3902 case FMASK(4,1):
3903 num_format = V_008F14_IMG_FMASK_8_4_1;
3904 break;
3905 case FMASK(4,2):
3906 num_format = V_008F14_IMG_FMASK_8_4_2;
3907 break;
3908 case FMASK(4,4):
3909 num_format = V_008F14_IMG_FMASK_8_4_4;
3910 break;
3911 case FMASK(8,1):
3912 num_format = V_008F14_IMG_FMASK_8_8_1;
3913 break;
3914 case FMASK(8,2):
3915 num_format = V_008F14_IMG_FMASK_16_8_2;
3916 break;
3917 case FMASK(8,4):
3918 num_format = V_008F14_IMG_FMASK_32_8_4;
3919 break;
3920 case FMASK(8,8):
3921 num_format = V_008F14_IMG_FMASK_32_8_8;
3922 break;
3923 case FMASK(16,1):
3924 num_format = V_008F14_IMG_FMASK_16_16_1;
3925 break;
3926 case FMASK(16,2):
3927 num_format = V_008F14_IMG_FMASK_32_16_2;
3928 break;
3929 case FMASK(16,4):
3930 num_format = V_008F14_IMG_FMASK_64_16_4;
3931 break;
3932 case FMASK(16,8):
3933 num_format = V_008F14_IMG_FMASK_64_16_8;
3934 break;
3935 default:
3936 unreachable("invalid nr_samples");
3937 }
3938 } else {
3939 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3940 case FMASK(2,1):
3941 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3942 break;
3943 case FMASK(2,2):
3944 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3945 break;
3946 case FMASK(4,1):
3947 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3948 break;
3949 case FMASK(4,2):
3950 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3951 break;
3952 case FMASK(4,4):
3953 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3954 break;
3955 case FMASK(8,1):
3956 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3957 break;
3958 case FMASK(8,2):
3959 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3960 break;
3961 case FMASK(8,4):
3962 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3963 break;
3964 case FMASK(8,8):
3965 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3966 break;
3967 case FMASK(16,1):
3968 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3969 break;
3970 case FMASK(16,2):
3971 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3972 break;
3973 case FMASK(16,4):
3974 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3975 break;
3976 case FMASK(16,8):
3977 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3978 break;
3979 default:
3980 unreachable("invalid nr_samples");
3981 }
3982 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3983 }
3984 #undef FMASK
3985
3986 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3987 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3988 S_008F14_DATA_FORMAT_GFX6(data_format) |
3989 S_008F14_NUM_FORMAT_GFX6(num_format);
3990 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3991 S_008F18_HEIGHT(height - 1);
3992 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3993 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3994 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3995 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3996 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3997 fmask_state[4] = 0;
3998 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3999 fmask_state[6] = 0;
4000 fmask_state[7] = 0;
4001
4002 if (screen->info.chip_class >= GFX9) {
4003 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
4004 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
4005 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
4006 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
4007 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
4008 } else {
4009 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
4010 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
4011 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
4012 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
4013 }
4014 }
4015 }
4016
4017 /**
4018 * Create a sampler view.
4019 *
4020 * @param ctx context
4021 * @param texture texture
4022 * @param state sampler view template
4023 * @param width0 width0 override (for compressed textures as int)
4024 * @param height0 height0 override (for compressed textures as int)
4025 * @param force_level set the base address to the level (for compressed textures)
4026 */
4027 struct pipe_sampler_view *
4028 si_create_sampler_view_custom(struct pipe_context *ctx,
4029 struct pipe_resource *texture,
4030 const struct pipe_sampler_view *state,
4031 unsigned width0, unsigned height0,
4032 unsigned force_level)
4033 {
4034 struct si_context *sctx = (struct si_context*)ctx;
4035 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4036 struct si_texture *tex = (struct si_texture*)texture;
4037 unsigned base_level, first_level, last_level;
4038 unsigned char state_swizzle[4];
4039 unsigned height, depth, width;
4040 unsigned last_layer = state->u.tex.last_layer;
4041 enum pipe_format pipe_format;
4042 const struct legacy_surf_level *surflevel;
4043
4044 if (!view)
4045 return NULL;
4046
4047 /* initialize base object */
4048 view->base = *state;
4049 view->base.texture = NULL;
4050 view->base.reference.count = 1;
4051 view->base.context = ctx;
4052
4053 assert(texture);
4054 pipe_resource_reference(&view->base.texture, texture);
4055
4056 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4057 state->format == PIPE_FORMAT_S8X24_UINT ||
4058 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4059 state->format == PIPE_FORMAT_S8_UINT)
4060 view->is_stencil_sampler = true;
4061
4062 /* Buffer resource. */
4063 if (texture->target == PIPE_BUFFER) {
4064 si_make_buffer_descriptor(sctx->screen,
4065 si_resource(texture),
4066 state->format,
4067 state->u.buf.offset,
4068 state->u.buf.size,
4069 view->state);
4070 return &view->base;
4071 }
4072
4073 state_swizzle[0] = state->swizzle_r;
4074 state_swizzle[1] = state->swizzle_g;
4075 state_swizzle[2] = state->swizzle_b;
4076 state_swizzle[3] = state->swizzle_a;
4077
4078 base_level = 0;
4079 first_level = state->u.tex.first_level;
4080 last_level = state->u.tex.last_level;
4081 width = width0;
4082 height = height0;
4083 depth = texture->depth0;
4084
4085 if (sctx->chip_class <= VI && force_level) {
4086 assert(force_level == first_level &&
4087 force_level == last_level);
4088 base_level = force_level;
4089 first_level = 0;
4090 last_level = 0;
4091 width = u_minify(width, force_level);
4092 height = u_minify(height, force_level);
4093 depth = u_minify(depth, force_level);
4094 }
4095
4096 /* This is not needed if state trackers set last_layer correctly. */
4097 if (state->target == PIPE_TEXTURE_1D ||
4098 state->target == PIPE_TEXTURE_2D ||
4099 state->target == PIPE_TEXTURE_RECT ||
4100 state->target == PIPE_TEXTURE_CUBE)
4101 last_layer = state->u.tex.first_layer;
4102
4103 /* Texturing with separate depth and stencil. */
4104 pipe_format = state->format;
4105
4106 /* Depth/stencil texturing sometimes needs separate texture. */
4107 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4108 if (!tex->flushed_depth_texture &&
4109 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4110 pipe_resource_reference(&view->base.texture, NULL);
4111 FREE(view);
4112 return NULL;
4113 }
4114
4115 assert(tex->flushed_depth_texture);
4116
4117 /* Override format for the case where the flushed texture
4118 * contains only Z or only S.
4119 */
4120 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4121 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4122
4123 tex = tex->flushed_depth_texture;
4124 }
4125
4126 surflevel = tex->surface.u.legacy.level;
4127
4128 if (tex->db_compatible) {
4129 if (!view->is_stencil_sampler)
4130 pipe_format = tex->db_render_format;
4131
4132 switch (pipe_format) {
4133 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4134 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4135 break;
4136 case PIPE_FORMAT_X8Z24_UNORM:
4137 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4138 /* Z24 is always stored like this for DB
4139 * compatibility.
4140 */
4141 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4142 break;
4143 case PIPE_FORMAT_X24S8_UINT:
4144 case PIPE_FORMAT_S8X24_UINT:
4145 case PIPE_FORMAT_X32_S8X24_UINT:
4146 pipe_format = PIPE_FORMAT_S8_UINT;
4147 surflevel = tex->surface.u.legacy.stencil_level;
4148 break;
4149 default:;
4150 }
4151 }
4152
4153 view->dcc_incompatible =
4154 vi_dcc_formats_are_incompatible(texture,
4155 state->u.tex.first_level,
4156 state->format);
4157
4158 si_make_texture_descriptor(sctx->screen, tex, true,
4159 state->target, pipe_format, state_swizzle,
4160 first_level, last_level,
4161 state->u.tex.first_layer, last_layer,
4162 width, height, depth,
4163 view->state, view->fmask_state);
4164
4165 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4166 view->is_integer =
4167 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4168 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4169 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4170 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4171 view->base_level_info = &surflevel[base_level];
4172 view->base_level = base_level;
4173 view->block_width = util_format_get_blockwidth(pipe_format);
4174 return &view->base;
4175 }
4176
4177 static struct pipe_sampler_view *
4178 si_create_sampler_view(struct pipe_context *ctx,
4179 struct pipe_resource *texture,
4180 const struct pipe_sampler_view *state)
4181 {
4182 return si_create_sampler_view_custom(ctx, texture, state,
4183 texture ? texture->width0 : 0,
4184 texture ? texture->height0 : 0, 0);
4185 }
4186
4187 static void si_sampler_view_destroy(struct pipe_context *ctx,
4188 struct pipe_sampler_view *state)
4189 {
4190 struct si_sampler_view *view = (struct si_sampler_view *)state;
4191
4192 pipe_resource_reference(&state->texture, NULL);
4193 FREE(view);
4194 }
4195
4196 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4197 {
4198 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4199 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4200 (linear_filter &&
4201 (wrap == PIPE_TEX_WRAP_CLAMP ||
4202 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4203 }
4204
4205 static uint32_t si_translate_border_color(struct si_context *sctx,
4206 const struct pipe_sampler_state *state,
4207 const union pipe_color_union *color,
4208 bool is_integer)
4209 {
4210 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4211 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4212
4213 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4214 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4215 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4216 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4217
4218 #define simple_border_types(elt) \
4219 do { \
4220 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4221 color->elt[2] == 0 && color->elt[3] == 0) \
4222 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4223 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4224 color->elt[2] == 0 && color->elt[3] == 1) \
4225 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4226 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4227 color->elt[2] == 1 && color->elt[3] == 1) \
4228 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4229 } while (false)
4230
4231 if (is_integer)
4232 simple_border_types(ui);
4233 else
4234 simple_border_types(f);
4235
4236 #undef simple_border_types
4237
4238 int i;
4239
4240 /* Check if the border has been uploaded already. */
4241 for (i = 0; i < sctx->border_color_count; i++)
4242 if (memcmp(&sctx->border_color_table[i], color,
4243 sizeof(*color)) == 0)
4244 break;
4245
4246 if (i >= SI_MAX_BORDER_COLORS) {
4247 /* Getting 4096 unique border colors is very unlikely. */
4248 fprintf(stderr, "radeonsi: The border color table is full. "
4249 "Any new border colors will be just black. "
4250 "Please file a bug.\n");
4251 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4252 }
4253
4254 if (i == sctx->border_color_count) {
4255 /* Upload a new border color. */
4256 memcpy(&sctx->border_color_table[i], color,
4257 sizeof(*color));
4258 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4259 color, sizeof(*color));
4260 sctx->border_color_count++;
4261 }
4262
4263 return S_008F3C_BORDER_COLOR_PTR(i) |
4264 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4265 }
4266
4267 static inline int S_FIXED(float value, unsigned frac_bits)
4268 {
4269 return value * (1 << frac_bits);
4270 }
4271
4272 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4273 {
4274 if (filter == PIPE_TEX_FILTER_LINEAR)
4275 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4276 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4277 else
4278 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4279 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4280 }
4281
4282 static inline unsigned si_tex_aniso_filter(unsigned filter)
4283 {
4284 if (filter < 2)
4285 return 0;
4286 if (filter < 4)
4287 return 1;
4288 if (filter < 8)
4289 return 2;
4290 if (filter < 16)
4291 return 3;
4292 return 4;
4293 }
4294
4295 static void *si_create_sampler_state(struct pipe_context *ctx,
4296 const struct pipe_sampler_state *state)
4297 {
4298 struct si_context *sctx = (struct si_context *)ctx;
4299 struct si_screen *sscreen = sctx->screen;
4300 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4301 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4302 : state->max_anisotropy;
4303 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4304 union pipe_color_union clamped_border_color;
4305
4306 if (!rstate) {
4307 return NULL;
4308 }
4309
4310 #ifdef DEBUG
4311 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4312 #endif
4313 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4314 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4315 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4316 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4317 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4318 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4319 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4320 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4321 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4322 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4323 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4324 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4325 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4326 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4327 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4328 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4329 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4330 S_008F38_MIP_POINT_PRECLAMP(0) |
4331 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4332 S_008F38_FILTER_PREC_FIX(1) |
4333 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4334 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4335
4336 /* Create sampler resource for integer textures. */
4337 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4338 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4339
4340 /* Create sampler resource for upgraded depth textures. */
4341 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4342
4343 for (unsigned i = 0; i < 4; ++i) {
4344 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4345 * when the border color is 1.0. */
4346 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4347 }
4348
4349 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4350 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4351 else
4352 rstate->upgraded_depth_val[3] =
4353 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4354 S_008F3C_UPGRADED_DEPTH(1);
4355
4356 return rstate;
4357 }
4358
4359 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4360 {
4361 struct si_context *sctx = (struct si_context *)ctx;
4362
4363 if (sctx->sample_mask == (uint16_t)sample_mask)
4364 return;
4365
4366 sctx->sample_mask = sample_mask;
4367 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4368 }
4369
4370 static void si_emit_sample_mask(struct si_context *sctx)
4371 {
4372 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4373 unsigned mask = sctx->sample_mask;
4374
4375 /* Needed for line and polygon smoothing as well as for the Polaris
4376 * small primitive filter. We expect the state tracker to take care of
4377 * this for us.
4378 */
4379 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4380 (mask & 1 && sctx->blitter->running));
4381
4382 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4383 radeon_emit(cs, mask | (mask << 16));
4384 radeon_emit(cs, mask | (mask << 16));
4385 }
4386
4387 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4388 {
4389 #ifdef DEBUG
4390 struct si_sampler_state *s = state;
4391
4392 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4393 s->magic = 0;
4394 #endif
4395 free(state);
4396 }
4397
4398 /*
4399 * Vertex elements & buffers
4400 */
4401
4402 struct util_fast_udiv_info32 {
4403 unsigned multiplier; /* the "magic number" multiplier */
4404 unsigned pre_shift; /* shift for the dividend before multiplying */
4405 unsigned post_shift; /* shift for the dividend after multiplying */
4406 int increment; /* 0 or 1; if set then increment the numerator, using one of
4407 the two strategies */
4408 };
4409
4410 static struct util_fast_udiv_info32
4411 util_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4412 {
4413 struct util_fast_udiv_info info =
4414 util_compute_fast_udiv_info(D, num_bits, 32);
4415
4416 struct util_fast_udiv_info32 result = {
4417 info.multiplier,
4418 info.pre_shift,
4419 info.post_shift,
4420 info.increment,
4421 };
4422 return result;
4423 }
4424
4425 static void *si_create_vertex_elements(struct pipe_context *ctx,
4426 unsigned count,
4427 const struct pipe_vertex_element *elements)
4428 {
4429 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4430 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4431 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4432 struct util_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4433 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32) == 16);
4434 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4435 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4436 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4437 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4438 int i;
4439
4440 assert(count <= SI_MAX_ATTRIBS);
4441 if (!v)
4442 return NULL;
4443
4444 v->count = count;
4445 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4446
4447 for (i = 0; i < count; ++i) {
4448 const struct util_format_description *desc;
4449 const struct util_format_channel_description *channel;
4450 unsigned data_format, num_format;
4451 int first_non_void;
4452 unsigned vbo_index = elements[i].vertex_buffer_index;
4453 unsigned char swizzle[4];
4454
4455 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4456 FREE(v);
4457 return NULL;
4458 }
4459
4460 unsigned instance_divisor = elements[i].instance_divisor;
4461 if (instance_divisor) {
4462 v->uses_instance_divisors = true;
4463
4464 if (instance_divisor == 1) {
4465 v->instance_divisor_is_one |= 1u << i;
4466 } else {
4467 v->instance_divisor_is_fetched |= 1u << i;
4468 divisor_factors[i] =
4469 util_compute_fast_udiv_info32(instance_divisor, 32);
4470 }
4471 }
4472
4473 if (!used[vbo_index]) {
4474 v->first_vb_use_mask |= 1 << i;
4475 used[vbo_index] = true;
4476 }
4477
4478 desc = util_format_description(elements[i].src_format);
4479 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4480 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4481 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4482 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4483 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4484
4485 v->format_size[i] = desc->block.bits / 8;
4486 v->src_offset[i] = elements[i].src_offset;
4487 v->vertex_buffer_index[i] = vbo_index;
4488
4489 /* The hardware always treats the 2-bit alpha channel as
4490 * unsigned, so a shader workaround is needed. The affected
4491 * chips are VI and older except Stoney (GFX8.1).
4492 */
4493 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4494 sscreen->info.chip_class <= VI &&
4495 sscreen->info.family != CHIP_STONEY) {
4496 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4497 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4498 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4499 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4500 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4501 /* This isn't actually used in OpenGL. */
4502 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4503 }
4504 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4505 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4506 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4507 else
4508 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4509 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4510 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4511 if (channel->normalized) {
4512 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4513 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4514 else
4515 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4516 } else {
4517 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4518 }
4519 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4520 if (channel->normalized) {
4521 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4522 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4523 else
4524 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4525 } else {
4526 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4527 }
4528 }
4529 } else if (channel && channel->size == 64 &&
4530 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4531 switch (desc->nr_channels) {
4532 case 1:
4533 case 2:
4534 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4535 swizzle[0] = PIPE_SWIZZLE_X;
4536 swizzle[1] = PIPE_SWIZZLE_Y;
4537 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4538 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4539 break;
4540 case 3:
4541 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4542 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4543 swizzle[1] = PIPE_SWIZZLE_Y;
4544 swizzle[2] = PIPE_SWIZZLE_0;
4545 swizzle[3] = PIPE_SWIZZLE_0;
4546 break;
4547 case 4:
4548 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4549 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4550 swizzle[1] = PIPE_SWIZZLE_Y;
4551 swizzle[2] = PIPE_SWIZZLE_Z;
4552 swizzle[3] = PIPE_SWIZZLE_W;
4553 break;
4554 default:
4555 assert(0);
4556 }
4557 } else if (channel && desc->nr_channels == 3) {
4558 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4559
4560 if (channel->size == 8) {
4561 if (channel->pure_integer)
4562 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4563 else
4564 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4565 } else if (channel->size == 16) {
4566 if (channel->pure_integer)
4567 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4568 else
4569 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4570 }
4571 }
4572
4573 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4574 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4575 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4576 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4577 S_008F0C_NUM_FORMAT(num_format) |
4578 S_008F0C_DATA_FORMAT(data_format);
4579 }
4580
4581 if (v->instance_divisor_is_fetched) {
4582 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4583
4584 v->instance_divisor_factor_buffer =
4585 (struct si_resource*)
4586 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4587 num_divisors * sizeof(divisor_factors[0]));
4588 if (!v->instance_divisor_factor_buffer) {
4589 FREE(v);
4590 return NULL;
4591 }
4592 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4593 NULL, PIPE_TRANSFER_WRITE);
4594 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4595 }
4596 return v;
4597 }
4598
4599 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4600 {
4601 struct si_context *sctx = (struct si_context *)ctx;
4602 struct si_vertex_elements *old = sctx->vertex_elements;
4603 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4604
4605 sctx->vertex_elements = v;
4606 sctx->vertex_buffers_dirty = true;
4607
4608 if (v &&
4609 (!old ||
4610 old->count != v->count ||
4611 old->uses_instance_divisors != v->uses_instance_divisors ||
4612 v->uses_instance_divisors || /* we don't check which divisors changed */
4613 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4614 sctx->do_update_shaders = true;
4615
4616 if (v && v->instance_divisor_is_fetched) {
4617 struct pipe_constant_buffer cb;
4618
4619 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4620 cb.user_buffer = NULL;
4621 cb.buffer_offset = 0;
4622 cb.buffer_size = 0xffffffff;
4623 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4624 }
4625 }
4626
4627 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4628 {
4629 struct si_context *sctx = (struct si_context *)ctx;
4630 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4631
4632 if (sctx->vertex_elements == state)
4633 sctx->vertex_elements = NULL;
4634 si_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4635 FREE(state);
4636 }
4637
4638 static void si_set_vertex_buffers(struct pipe_context *ctx,
4639 unsigned start_slot, unsigned count,
4640 const struct pipe_vertex_buffer *buffers)
4641 {
4642 struct si_context *sctx = (struct si_context *)ctx;
4643 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4644 int i;
4645
4646 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4647
4648 if (buffers) {
4649 for (i = 0; i < count; i++) {
4650 const struct pipe_vertex_buffer *src = buffers + i;
4651 struct pipe_vertex_buffer *dsti = dst + i;
4652 struct pipe_resource *buf = src->buffer.resource;
4653
4654 pipe_resource_reference(&dsti->buffer.resource, buf);
4655 dsti->buffer_offset = src->buffer_offset;
4656 dsti->stride = src->stride;
4657 si_context_add_resource_size(sctx, buf);
4658 if (buf)
4659 si_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4660 }
4661 } else {
4662 for (i = 0; i < count; i++) {
4663 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4664 }
4665 }
4666 sctx->vertex_buffers_dirty = true;
4667 }
4668
4669 /*
4670 * Misc
4671 */
4672
4673 static void si_set_tess_state(struct pipe_context *ctx,
4674 const float default_outer_level[4],
4675 const float default_inner_level[2])
4676 {
4677 struct si_context *sctx = (struct si_context *)ctx;
4678 struct pipe_constant_buffer cb;
4679 float array[8];
4680
4681 memcpy(array, default_outer_level, sizeof(float) * 4);
4682 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4683
4684 cb.buffer = NULL;
4685 cb.user_buffer = NULL;
4686 cb.buffer_size = sizeof(array);
4687
4688 si_upload_const_buffer(sctx, (struct si_resource**)&cb.buffer,
4689 (void*)array, sizeof(array),
4690 &cb.buffer_offset);
4691
4692 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4693 pipe_resource_reference(&cb.buffer, NULL);
4694 }
4695
4696 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4697 {
4698 struct si_context *sctx = (struct si_context *)ctx;
4699
4700 si_update_fb_dirtiness_after_rendering(sctx);
4701
4702 /* Multisample surfaces are flushed in si_decompress_textures. */
4703 if (sctx->framebuffer.uncompressed_cb_mask)
4704 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4705 sctx->framebuffer.CB_has_shader_readable_metadata);
4706 }
4707
4708 /* This only ensures coherency for shader image/buffer stores. */
4709 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4710 {
4711 struct si_context *sctx = (struct si_context *)ctx;
4712
4713 /* Subsequent commands must wait for all shader invocations to
4714 * complete. */
4715 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4716 SI_CONTEXT_CS_PARTIAL_FLUSH;
4717
4718 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4719 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4720 SI_CONTEXT_INV_VMEM_L1;
4721
4722 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4723 PIPE_BARRIER_SHADER_BUFFER |
4724 PIPE_BARRIER_TEXTURE |
4725 PIPE_BARRIER_IMAGE |
4726 PIPE_BARRIER_STREAMOUT_BUFFER |
4727 PIPE_BARRIER_GLOBAL_BUFFER)) {
4728 /* As far as I can tell, L1 contents are written back to L2
4729 * automatically at end of shader, but the contents of other
4730 * L1 caches might still be stale. */
4731 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4732 }
4733
4734 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4735 /* Indices are read through TC L2 since VI.
4736 * L1 isn't used.
4737 */
4738 if (sctx->screen->info.chip_class <= CIK)
4739 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4740 }
4741
4742 /* MSAA color, any depth and any stencil are flushed in
4743 * si_decompress_textures when needed.
4744 */
4745 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4746 sctx->framebuffer.uncompressed_cb_mask) {
4747 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4748
4749 if (sctx->chip_class <= VI)
4750 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4751 }
4752
4753 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4754 if (sctx->screen->info.chip_class <= VI &&
4755 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4756 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4757 }
4758
4759 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4760 {
4761 struct pipe_blend_state blend;
4762
4763 memset(&blend, 0, sizeof(blend));
4764 blend.independent_blend_enable = true;
4765 blend.rt[0].colormask = 0xf;
4766 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4767 }
4768
4769 static void si_init_config(struct si_context *sctx);
4770
4771 void si_init_state_functions(struct si_context *sctx)
4772 {
4773 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4774 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4775 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4776 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4777 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4778 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4779 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4780 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4781 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4782 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4783 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4784
4785 sctx->b.create_blend_state = si_create_blend_state;
4786 sctx->b.bind_blend_state = si_bind_blend_state;
4787 sctx->b.delete_blend_state = si_delete_blend_state;
4788 sctx->b.set_blend_color = si_set_blend_color;
4789
4790 sctx->b.create_rasterizer_state = si_create_rs_state;
4791 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4792 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4793
4794 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4795 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4796 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4797
4798 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4799 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4800 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4801 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4802 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4803
4804 sctx->b.set_clip_state = si_set_clip_state;
4805 sctx->b.set_stencil_ref = si_set_stencil_ref;
4806
4807 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4808
4809 sctx->b.create_sampler_state = si_create_sampler_state;
4810 sctx->b.delete_sampler_state = si_delete_sampler_state;
4811
4812 sctx->b.create_sampler_view = si_create_sampler_view;
4813 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4814
4815 sctx->b.set_sample_mask = si_set_sample_mask;
4816
4817 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4818 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4819 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4820 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4821
4822 sctx->b.texture_barrier = si_texture_barrier;
4823 sctx->b.memory_barrier = si_memory_barrier;
4824 sctx->b.set_min_samples = si_set_min_samples;
4825 sctx->b.set_tess_state = si_set_tess_state;
4826
4827 sctx->b.set_active_query_state = si_set_active_query_state;
4828
4829 si_init_config(sctx);
4830 }
4831
4832 void si_init_screen_state_functions(struct si_screen *sscreen)
4833 {
4834 sscreen->b.is_format_supported = si_is_format_supported;
4835 }
4836
4837 static void si_set_grbm_gfx_index(struct si_context *sctx,
4838 struct si_pm4_state *pm4, unsigned value)
4839 {
4840 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4841 R_00802C_GRBM_GFX_INDEX;
4842 si_pm4_set_reg(pm4, reg, value);
4843 }
4844
4845 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4846 struct si_pm4_state *pm4, unsigned se)
4847 {
4848 assert(se == ~0 || se < sctx->screen->info.max_se);
4849 si_set_grbm_gfx_index(sctx, pm4,
4850 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4851 S_030800_SE_INDEX(se)) |
4852 S_030800_SH_BROADCAST_WRITES(1) |
4853 S_030800_INSTANCE_BROADCAST_WRITES(1));
4854 }
4855
4856 static void
4857 si_write_harvested_raster_configs(struct si_context *sctx,
4858 struct si_pm4_state *pm4,
4859 unsigned raster_config,
4860 unsigned raster_config_1)
4861 {
4862 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4863 unsigned raster_config_se[4];
4864 unsigned se;
4865
4866 ac_get_harvested_configs(&sctx->screen->info,
4867 raster_config,
4868 &raster_config_1,
4869 raster_config_se);
4870
4871 for (se = 0; se < num_se; se++) {
4872 si_set_grbm_gfx_index_se(sctx, pm4, se);
4873 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4874 }
4875 si_set_grbm_gfx_index(sctx, pm4, ~0);
4876
4877 if (sctx->chip_class >= CIK) {
4878 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4879 }
4880 }
4881
4882 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4883 {
4884 struct si_screen *sscreen = sctx->screen;
4885 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4886 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4887 unsigned raster_config = sscreen->pa_sc_raster_config;
4888 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4889
4890 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4891 /* Always use the default config when all backends are enabled
4892 * (or when we failed to determine the enabled backends).
4893 */
4894 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4895 raster_config);
4896 if (sctx->chip_class >= CIK)
4897 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4898 raster_config_1);
4899 } else {
4900 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4901 }
4902 }
4903
4904 static void si_init_config(struct si_context *sctx)
4905 {
4906 struct si_screen *sscreen = sctx->screen;
4907 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4908 bool has_clear_state = sscreen->has_clear_state;
4909 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4910
4911 /* SI, radeon kernel disabled CLEAR_STATE. */
4912 assert(has_clear_state || sscreen->info.chip_class == SI ||
4913 sscreen->info.drm_major != 3);
4914
4915 if (!pm4)
4916 return;
4917
4918 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4919 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4920 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4921 si_pm4_cmd_end(pm4, false);
4922
4923 if (has_clear_state) {
4924 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4925 si_pm4_cmd_add(pm4, 0);
4926 si_pm4_cmd_end(pm4, false);
4927 }
4928
4929 if (sctx->chip_class <= VI)
4930 si_set_raster_config(sctx, pm4);
4931
4932 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4933 if (!has_clear_state)
4934 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4935
4936 /* FIXME calculate these values somehow ??? */
4937 if (sctx->chip_class <= VI) {
4938 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4939 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4940 }
4941
4942 if (!has_clear_state) {
4943 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4944 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4945 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4946 }
4947
4948 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4949 if (!has_clear_state)
4950 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4951 if (sctx->chip_class < CIK)
4952 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4953 S_008A14_CLIP_VTX_REORDER_ENA(1));
4954
4955 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4956 * I don't know why. Deduced by trial and error.
4957 */
4958 if (sctx->chip_class <= CIK) {
4959 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4960 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4961 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4962 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4963 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4964 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4965 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4966 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4967 }
4968
4969 if (!has_clear_state) {
4970 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4971 S_028230_ER_TRI(0xA) |
4972 S_028230_ER_POINT(0xA) |
4973 S_028230_ER_RECT(0xA) |
4974 /* Required by DX10_DIAMOND_TEST_ENA: */
4975 S_028230_ER_LINE_LR(0x1A) |
4976 S_028230_ER_LINE_RL(0x26) |
4977 S_028230_ER_LINE_TB(0xA) |
4978 S_028230_ER_LINE_BT(0xA));
4979 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4980 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4981 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4982 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4983 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4984 }
4985
4986 if (sctx->chip_class >= GFX9) {
4987 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4988 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4989 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4990 } else {
4991 /* These registers, when written, also overwrite the CLEAR_STATE
4992 * context, so we can't rely on CLEAR_STATE setting them.
4993 * It would be an issue if there was another UMD changing them.
4994 */
4995 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4996 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4997 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4998 }
4999
5000 if (sctx->chip_class >= CIK) {
5001 if (sctx->chip_class >= GFX9) {
5002 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5003 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5004 } else {
5005 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5006 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5007 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5008 S_00B41C_WAVE_LIMIT(0x3F));
5009 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5010 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5011
5012 /* If this is 0, Bonaire can hang even if GS isn't being used.
5013 * Other chips are unaffected. These are suboptimal values,
5014 * but we don't use on-chip GS.
5015 */
5016 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5017 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5018 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5019 }
5020 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5021 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5022
5023 /* Compute LATE_ALLOC_VS.LIMIT. */
5024 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
5025 unsigned late_alloc_limit; /* The limit is per SH. */
5026
5027 if (sctx->family == CHIP_KABINI) {
5028 late_alloc_limit = 0; /* Potential hang on Kabini. */
5029 } else if (num_cu_per_sh <= 4) {
5030 /* Too few available compute units per SH. Disallowing
5031 * VS to run on one CU could hurt us more than late VS
5032 * allocation would help.
5033 *
5034 * 2 is the highest safe number that allows us to keep
5035 * all CUs enabled.
5036 */
5037 late_alloc_limit = 2;
5038 } else {
5039 /* This is a good initial value, allowing 1 late_alloc
5040 * wave per SIMD on num_cu - 2.
5041 */
5042 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5043
5044 /* The limit is 0-based, so 0 means 1. */
5045 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5046 late_alloc_limit -= 1;
5047 }
5048
5049 /* VS can't execute on one CU if the limit is > 2. */
5050 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5051 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5052 S_00B118_WAVE_LIMIT(0x3F));
5053 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5054 S_00B11C_LIMIT(late_alloc_limit));
5055 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5056 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5057 }
5058
5059 if (sctx->chip_class >= VI) {
5060 unsigned vgt_tess_distribution;
5061
5062 vgt_tess_distribution =
5063 S_028B50_ACCUM_ISOLINE(32) |
5064 S_028B50_ACCUM_TRI(11) |
5065 S_028B50_ACCUM_QUAD(11) |
5066 S_028B50_DONUT_SPLIT(16);
5067
5068 /* Testing with Unigine Heaven extreme tesselation yielded best results
5069 * with TRAP_SPLIT = 3.
5070 */
5071 if (sctx->family == CHIP_FIJI ||
5072 sctx->family >= CHIP_POLARIS10)
5073 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5074
5075 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5076 } else if (!has_clear_state) {
5077 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5078 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5079 }
5080
5081 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5082 if (sctx->chip_class >= CIK) {
5083 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5084 S_028084_ADDRESS(border_color_va >> 40));
5085 }
5086 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5087 RADEON_PRIO_BORDER_COLORS);
5088
5089 if (sctx->chip_class >= GFX9) {
5090 unsigned num_se = sscreen->info.max_se;
5091 unsigned pc_lines = 0;
5092
5093 switch (sctx->family) {
5094 case CHIP_VEGA10:
5095 case CHIP_VEGA12:
5096 case CHIP_VEGA20:
5097 pc_lines = 4096;
5098 break;
5099 case CHIP_RAVEN:
5100 case CHIP_RAVEN2:
5101 pc_lines = 1024;
5102 break;
5103 default:
5104 assert(0);
5105 }
5106
5107 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5108 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5109 S_028C48_MAX_PRIM_PER_BATCH(1023));
5110 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5111 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5112 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5113 }
5114
5115 si_pm4_upload_indirect_buffer(sctx, pm4);
5116 sctx->init_config = pm4;
5117 }