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radeonsi: implement fragment color clamping
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array + 1;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
54 *list_elem = atom;
55 }
56
57 unsigned si_array_mode(unsigned mode)
58 {
59 switch (mode) {
60 case RADEON_SURF_MODE_LINEAR_ALIGNED:
61 return V_009910_ARRAY_LINEAR_ALIGNED;
62 case RADEON_SURF_MODE_1D:
63 return V_009910_ARRAY_1D_TILED_THIN1;
64 case RADEON_SURF_MODE_2D:
65 return V_009910_ARRAY_2D_TILED_THIN1;
66 default:
67 case RADEON_SURF_MODE_LINEAR:
68 return V_009910_ARRAY_LINEAR_GENERAL;
69 }
70 }
71
72 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
73 {
74 if (sscreen->b.chip_class >= CIK &&
75 sscreen->b.info.cik_macrotile_mode_array_valid) {
76 unsigned index, tileb;
77
78 tileb = 8 * 8 * tex->surface.bpe;
79 tileb = MIN2(tex->surface.tile_split, tileb);
80
81 for (index = 0; tileb > 64; index++) {
82 tileb >>= 1;
83 }
84 assert(index < 16);
85
86 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
87 }
88
89 if (sscreen->b.chip_class == SI &&
90 sscreen->b.info.si_tile_mode_array_valid) {
91 /* Don't use stencil_tiling_index, because num_banks is always
92 * read from the depth mode. */
93 unsigned tile_mode_index = tex->surface.tiling_index[0];
94 assert(tile_mode_index < 32);
95
96 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
97 }
98
99 /* The old way. */
100 switch (sscreen->b.tiling_info.num_banks) {
101 case 2:
102 return V_02803C_ADDR_SURF_2_BANK;
103 case 4:
104 return V_02803C_ADDR_SURF_4_BANK;
105 case 8:
106 default:
107 return V_02803C_ADDR_SURF_8_BANK;
108 case 16:
109 return V_02803C_ADDR_SURF_16_BANK;
110 }
111 }
112
113 unsigned cik_tile_split(unsigned tile_split)
114 {
115 switch (tile_split) {
116 case 64:
117 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
118 break;
119 case 128:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
121 break;
122 case 256:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
124 break;
125 case 512:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
127 break;
128 default:
129 case 1024:
130 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
131 break;
132 case 2048:
133 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
134 break;
135 case 4096:
136 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
137 break;
138 }
139 return tile_split;
140 }
141
142 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
143 {
144 switch (macro_tile_aspect) {
145 default:
146 case 1:
147 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
148 break;
149 case 2:
150 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
151 break;
152 case 4:
153 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
154 break;
155 case 8:
156 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
157 break;
158 }
159 return macro_tile_aspect;
160 }
161
162 unsigned cik_bank_wh(unsigned bankwh)
163 {
164 switch (bankwh) {
165 default:
166 case 1:
167 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
168 break;
169 case 2:
170 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
171 break;
172 case 4:
173 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
174 break;
175 case 8:
176 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
177 break;
178 }
179 return bankwh;
180 }
181
182 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
183 {
184 if (sscreen->b.info.si_tile_mode_array_valid) {
185 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
186
187 return G_009910_PIPE_CONFIG(gb_tile_mode);
188 }
189
190 /* This is probably broken for a lot of chips, but it's only used
191 * if the kernel cannot return the tile mode array for CIK. */
192 switch (sscreen->b.info.r600_num_tile_pipes) {
193 case 16:
194 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
195 case 8:
196 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
197 case 4:
198 default:
199 if (sscreen->b.info.r600_num_backends == 4)
200 return V_02803C_X_ADDR_SURF_P4_16X16;
201 else
202 return V_02803C_X_ADDR_SURF_P4_8X16;
203 case 2:
204 return V_02803C_ADDR_SURF_P2;
205 }
206 }
207
208 static unsigned si_map_swizzle(unsigned swizzle)
209 {
210 switch (swizzle) {
211 case UTIL_FORMAT_SWIZZLE_Y:
212 return V_008F0C_SQ_SEL_Y;
213 case UTIL_FORMAT_SWIZZLE_Z:
214 return V_008F0C_SQ_SEL_Z;
215 case UTIL_FORMAT_SWIZZLE_W:
216 return V_008F0C_SQ_SEL_W;
217 case UTIL_FORMAT_SWIZZLE_0:
218 return V_008F0C_SQ_SEL_0;
219 case UTIL_FORMAT_SWIZZLE_1:
220 return V_008F0C_SQ_SEL_1;
221 default: /* UTIL_FORMAT_SWIZZLE_X */
222 return V_008F0C_SQ_SEL_X;
223 }
224 }
225
226 static uint32_t S_FIXED(float value, uint32_t frac_bits)
227 {
228 return value * (1 << frac_bits);
229 }
230
231 /* 12.4 fixed-point */
232 static unsigned si_pack_float_12p4(float x)
233 {
234 return x <= 0 ? 0 :
235 x >= 4096 ? 0xffff : x * 16;
236 }
237
238 /*
239 * Inferred framebuffer and blender state.
240 *
241 * One of the reasons this must be derived from the framebuffer state is that:
242 * - The blend state mask is 0xf most of the time.
243 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
244 * so COLOR1 is enabled pretty much all the time.
245 * So CB_TARGET_MASK is the only register that can disable COLOR1.
246 *
247 * Another reason is to avoid a hang with dual source blending.
248 */
249 static void si_emit_cb_target_mask(struct si_context *sctx, struct r600_atom *atom)
250 {
251 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
252 struct si_state_blend *blend = sctx->queued.named.blend;
253 uint32_t mask = 0, i;
254
255 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
256 if (sctx->framebuffer.state.cbufs[i])
257 mask |= 0xf << (4*i);
258
259 if (blend)
260 mask &= blend->cb_target_mask;
261
262 /* Avoid a hang that happens when dual source blending is enabled
263 * but there is not enough color outputs. This is undefined behavior,
264 * so disable color writes completely.
265 *
266 * Reproducible with Unigine Heaven 4.0 and drirc missing.
267 */
268 if (blend->dual_src_blend &&
269 (sctx->ps_shader->ps_colors_written & 0x3) != 0x3)
270 mask = 0;
271
272 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, mask);
273 }
274
275 /*
276 * Blender functions
277 */
278
279 static uint32_t si_translate_blend_function(int blend_func)
280 {
281 switch (blend_func) {
282 case PIPE_BLEND_ADD:
283 return V_028780_COMB_DST_PLUS_SRC;
284 case PIPE_BLEND_SUBTRACT:
285 return V_028780_COMB_SRC_MINUS_DST;
286 case PIPE_BLEND_REVERSE_SUBTRACT:
287 return V_028780_COMB_DST_MINUS_SRC;
288 case PIPE_BLEND_MIN:
289 return V_028780_COMB_MIN_DST_SRC;
290 case PIPE_BLEND_MAX:
291 return V_028780_COMB_MAX_DST_SRC;
292 default:
293 R600_ERR("Unknown blend function %d\n", blend_func);
294 assert(0);
295 break;
296 }
297 return 0;
298 }
299
300 static uint32_t si_translate_blend_factor(int blend_fact)
301 {
302 switch (blend_fact) {
303 case PIPE_BLENDFACTOR_ONE:
304 return V_028780_BLEND_ONE;
305 case PIPE_BLENDFACTOR_SRC_COLOR:
306 return V_028780_BLEND_SRC_COLOR;
307 case PIPE_BLENDFACTOR_SRC_ALPHA:
308 return V_028780_BLEND_SRC_ALPHA;
309 case PIPE_BLENDFACTOR_DST_ALPHA:
310 return V_028780_BLEND_DST_ALPHA;
311 case PIPE_BLENDFACTOR_DST_COLOR:
312 return V_028780_BLEND_DST_COLOR;
313 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
314 return V_028780_BLEND_SRC_ALPHA_SATURATE;
315 case PIPE_BLENDFACTOR_CONST_COLOR:
316 return V_028780_BLEND_CONSTANT_COLOR;
317 case PIPE_BLENDFACTOR_CONST_ALPHA:
318 return V_028780_BLEND_CONSTANT_ALPHA;
319 case PIPE_BLENDFACTOR_ZERO:
320 return V_028780_BLEND_ZERO;
321 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
322 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
323 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
324 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
325 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
326 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
327 case PIPE_BLENDFACTOR_INV_DST_COLOR:
328 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
329 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
330 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
331 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
333 case PIPE_BLENDFACTOR_SRC1_COLOR:
334 return V_028780_BLEND_SRC1_COLOR;
335 case PIPE_BLENDFACTOR_SRC1_ALPHA:
336 return V_028780_BLEND_SRC1_ALPHA;
337 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
338 return V_028780_BLEND_INV_SRC1_COLOR;
339 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
340 return V_028780_BLEND_INV_SRC1_ALPHA;
341 default:
342 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
343 assert(0);
344 break;
345 }
346 return 0;
347 }
348
349 static void *si_create_blend_state_mode(struct pipe_context *ctx,
350 const struct pipe_blend_state *state,
351 unsigned mode)
352 {
353 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
354 struct si_pm4_state *pm4 = &blend->pm4;
355
356 uint32_t color_control = 0;
357
358 if (blend == NULL)
359 return NULL;
360
361 blend->alpha_to_one = state->alpha_to_one;
362 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
363
364 if (state->logicop_enable) {
365 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
366 } else {
367 color_control |= S_028808_ROP3(0xcc);
368 }
369
370 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
371 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
372 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
373 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
374 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
375 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
376
377 blend->cb_target_mask = 0;
378 for (int i = 0; i < 8; i++) {
379 /* state->rt entries > 0 only written if independent blending */
380 const int j = state->independent_blend_enable ? i : 0;
381
382 unsigned eqRGB = state->rt[j].rgb_func;
383 unsigned srcRGB = state->rt[j].rgb_src_factor;
384 unsigned dstRGB = state->rt[j].rgb_dst_factor;
385 unsigned eqA = state->rt[j].alpha_func;
386 unsigned srcA = state->rt[j].alpha_src_factor;
387 unsigned dstA = state->rt[j].alpha_dst_factor;
388
389 unsigned blend_cntl = 0;
390
391 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
392 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
393
394 if (!state->rt[j].blend_enable) {
395 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
396 continue;
397 }
398
399 blend_cntl |= S_028780_ENABLE(1);
400 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
401 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
402 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
403
404 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
405 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
406 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
407 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
408 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
409 }
410 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
411 }
412
413 if (blend->cb_target_mask) {
414 color_control |= S_028808_MODE(mode);
415 } else {
416 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
417 }
418 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
419
420 return blend;
421 }
422
423 static void *si_create_blend_state(struct pipe_context *ctx,
424 const struct pipe_blend_state *state)
425 {
426 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
427 }
428
429 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
430 {
431 struct si_context *sctx = (struct si_context *)ctx;
432 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
433 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
434 }
435
436 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
437 {
438 struct si_context *sctx = (struct si_context *)ctx;
439 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
440 }
441
442 static void si_set_blend_color(struct pipe_context *ctx,
443 const struct pipe_blend_color *state)
444 {
445 struct si_context *sctx = (struct si_context *)ctx;
446
447 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
448 return;
449
450 sctx->blend_color.state = *state;
451 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
452 }
453
454 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
455 {
456 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
457
458 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
459 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
460 }
461
462 /*
463 * Clipping, scissors and viewport
464 */
465
466 static void si_set_clip_state(struct pipe_context *ctx,
467 const struct pipe_clip_state *state)
468 {
469 struct si_context *sctx = (struct si_context *)ctx;
470 struct pipe_constant_buffer cb;
471
472 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
473 return;
474
475 sctx->clip_state.state = *state;
476 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
477
478 cb.buffer = NULL;
479 cb.user_buffer = state->ucp;
480 cb.buffer_offset = 0;
481 cb.buffer_size = 4*4*8;
482 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
483 pipe_resource_reference(&cb.buffer, NULL);
484 }
485
486 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
487 {
488 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
489
490 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
491 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
492 }
493
494 #define SIX_BITS 0x3F
495
496 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
497 {
498 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
499 struct tgsi_shader_info *info = si_get_vs_info(sctx);
500 unsigned window_space =
501 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
502 unsigned clipdist_mask =
503 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
504
505 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
506 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
507 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
508 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
509 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
510 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
511 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
512 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
513 info->writes_edgeflag ||
514 info->writes_layer ||
515 info->writes_viewport_index) |
516 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
517 (sctx->queued.named.rasterizer->clip_plane_enable &
518 clipdist_mask));
519 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
520 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
521 (clipdist_mask ? 0 :
522 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
523 S_028810_CLIP_DISABLE(window_space));
524 }
525
526 static void si_set_scissor_states(struct pipe_context *ctx,
527 unsigned start_slot,
528 unsigned num_scissors,
529 const struct pipe_scissor_state *state)
530 {
531 struct si_context *sctx = (struct si_context *)ctx;
532 int i;
533
534 for (i = 0; i < num_scissors; i++)
535 sctx->scissors.states[start_slot + i] = state[i];
536
537 sctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
538 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
539 }
540
541 static void si_emit_scissors(struct si_context *sctx, struct r600_atom *atom)
542 {
543 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
544 struct pipe_scissor_state *states = sctx->scissors.states;
545 unsigned mask = sctx->scissors.dirty_mask;
546
547 /* The simple case: Only 1 viewport is active. */
548 if (mask & 1 &&
549 !si_get_vs_info(sctx)->writes_viewport_index) {
550 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
551 radeon_emit(cs, S_028250_TL_X(states[0].minx) |
552 S_028250_TL_Y(states[0].miny) |
553 S_028250_WINDOW_OFFSET_DISABLE(1));
554 radeon_emit(cs, S_028254_BR_X(states[0].maxx) |
555 S_028254_BR_Y(states[0].maxy));
556 sctx->scissors.dirty_mask &= ~1; /* clear one bit */
557 return;
558 }
559
560 while (mask) {
561 int start, count, i;
562
563 u_bit_scan_consecutive_range(&mask, &start, &count);
564
565 radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
566 start * 4 * 2, count * 2);
567 for (i = start; i < start+count; i++) {
568 radeon_emit(cs, S_028250_TL_X(states[i].minx) |
569 S_028250_TL_Y(states[i].miny) |
570 S_028250_WINDOW_OFFSET_DISABLE(1));
571 radeon_emit(cs, S_028254_BR_X(states[i].maxx) |
572 S_028254_BR_Y(states[i].maxy));
573 }
574 }
575 sctx->scissors.dirty_mask = 0;
576 }
577
578 static void si_set_viewport_states(struct pipe_context *ctx,
579 unsigned start_slot,
580 unsigned num_viewports,
581 const struct pipe_viewport_state *state)
582 {
583 struct si_context *sctx = (struct si_context *)ctx;
584 int i;
585
586 for (i = 0; i < num_viewports; i++)
587 sctx->viewports.states[start_slot + i] = state[i];
588
589 sctx->viewports.dirty_mask |= ((1 << num_viewports) - 1) << start_slot;
590 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
591 }
592
593 static void si_emit_viewports(struct si_context *sctx, struct r600_atom *atom)
594 {
595 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
596 struct pipe_viewport_state *states = sctx->viewports.states;
597 unsigned mask = sctx->viewports.dirty_mask;
598
599 /* The simple case: Only 1 viewport is active. */
600 if (mask & 1 &&
601 !si_get_vs_info(sctx)->writes_viewport_index) {
602 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
603 radeon_emit(cs, fui(states[0].scale[0]));
604 radeon_emit(cs, fui(states[0].translate[0]));
605 radeon_emit(cs, fui(states[0].scale[1]));
606 radeon_emit(cs, fui(states[0].translate[1]));
607 radeon_emit(cs, fui(states[0].scale[2]));
608 radeon_emit(cs, fui(states[0].translate[2]));
609 sctx->viewports.dirty_mask &= ~1; /* clear one bit */
610 return;
611 }
612
613 while (mask) {
614 int start, count, i;
615
616 u_bit_scan_consecutive_range(&mask, &start, &count);
617
618 radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
619 start * 4 * 6, count * 6);
620 for (i = start; i < start+count; i++) {
621 radeon_emit(cs, fui(states[i].scale[0]));
622 radeon_emit(cs, fui(states[i].translate[0]));
623 radeon_emit(cs, fui(states[i].scale[1]));
624 radeon_emit(cs, fui(states[i].translate[1]));
625 radeon_emit(cs, fui(states[i].scale[2]));
626 radeon_emit(cs, fui(states[i].translate[2]));
627 }
628 }
629 sctx->viewports.dirty_mask = 0;
630 }
631
632 /*
633 * inferred state between framebuffer and rasterizer
634 */
635 static void si_update_poly_offset_state(struct si_context *sctx)
636 {
637 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
638
639 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
640 return;
641
642 switch (sctx->framebuffer.state.zsbuf->texture->format) {
643 case PIPE_FORMAT_Z16_UNORM:
644 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
645 break;
646 default: /* 24-bit */
647 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
648 break;
649 case PIPE_FORMAT_Z32_FLOAT:
650 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
651 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
652 break;
653 }
654 }
655
656 /*
657 * Rasterizer
658 */
659
660 static uint32_t si_translate_fill(uint32_t func)
661 {
662 switch(func) {
663 case PIPE_POLYGON_MODE_FILL:
664 return V_028814_X_DRAW_TRIANGLES;
665 case PIPE_POLYGON_MODE_LINE:
666 return V_028814_X_DRAW_LINES;
667 case PIPE_POLYGON_MODE_POINT:
668 return V_028814_X_DRAW_POINTS;
669 default:
670 assert(0);
671 return V_028814_X_DRAW_POINTS;
672 }
673 }
674
675 static void *si_create_rs_state(struct pipe_context *ctx,
676 const struct pipe_rasterizer_state *state)
677 {
678 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
679 struct si_pm4_state *pm4 = &rs->pm4;
680 unsigned tmp, i;
681 float psize_min, psize_max;
682
683 if (rs == NULL) {
684 return NULL;
685 }
686
687 rs->two_side = state->light_twoside;
688 rs->multisample_enable = state->multisample;
689 rs->force_persample_interp = state->force_persample_interp;
690 rs->clip_plane_enable = state->clip_plane_enable;
691 rs->line_stipple_enable = state->line_stipple_enable;
692 rs->poly_stipple_enable = state->poly_stipple_enable;
693 rs->line_smooth = state->line_smooth;
694 rs->poly_smooth = state->poly_smooth;
695 rs->uses_poly_offset = state->offset_point || state->offset_line ||
696 state->offset_tri;
697 rs->clamp_fragment_color = state->clamp_fragment_color;
698 rs->flatshade = state->flatshade;
699 rs->sprite_coord_enable = state->sprite_coord_enable;
700 rs->pa_sc_line_stipple = state->line_stipple_enable ?
701 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
702 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
703 rs->pa_cl_clip_cntl =
704 S_028810_PS_UCP_MODE(3) |
705 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
706 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
707 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
708 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
709 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
710
711 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
712 S_0286D4_FLAT_SHADE_ENA(1) |
713 S_0286D4_PNT_SPRITE_ENA(1) |
714 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
715 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
716 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
717 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
718 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
719
720 /* point size 12.4 fixed point */
721 tmp = (unsigned)(state->point_size * 8.0);
722 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
723
724 if (state->point_size_per_vertex) {
725 psize_min = util_get_min_point_size(state);
726 psize_max = 8192;
727 } else {
728 /* Force the point size to be as if the vertex output was disabled. */
729 psize_min = state->point_size;
730 psize_max = state->point_size;
731 }
732 /* Divide by two, because 0.5 = 1 pixel. */
733 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
734 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
735 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
736
737 tmp = (unsigned)state->line_width * 8;
738 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
739 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
740 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
741 S_028A48_MSAA_ENABLE(state->multisample ||
742 state->poly_smooth ||
743 state->line_smooth) |
744 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
745
746 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
747 S_028BE4_PIX_CENTER(state->half_pixel_center) |
748 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
749
750 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
751 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
752 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
753 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
754 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
755 S_028814_FACE(!state->front_ccw) |
756 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
757 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
758 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
759 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
760 state->fill_back != PIPE_POLYGON_MODE_FILL) |
761 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
762 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
763
764 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
765 for (i = 0; i < 3; i++) {
766 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
767 float offset_units = state->offset_units;
768 float offset_scale = state->offset_scale * 16.0f;
769
770 switch (i) {
771 case 0: /* 16-bit zbuffer */
772 offset_units *= 4.0f;
773 break;
774 case 1: /* 24-bit zbuffer */
775 offset_units *= 2.0f;
776 break;
777 case 2: /* 32-bit zbuffer */
778 offset_units *= 1.0f;
779 break;
780 }
781
782 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
783 fui(offset_scale));
784 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
785 fui(offset_units));
786 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
787 fui(offset_scale));
788 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
789 fui(offset_units));
790 }
791
792 return rs;
793 }
794
795 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
796 {
797 struct si_context *sctx = (struct si_context *)ctx;
798 struct si_state_rasterizer *old_rs =
799 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
800 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
801
802 if (state == NULL)
803 return;
804
805 if (sctx->framebuffer.nr_samples > 1 &&
806 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
807 si_mark_atom_dirty(sctx, &sctx->db_render_state);
808
809 si_pm4_bind_state(sctx, rasterizer, rs);
810 si_update_poly_offset_state(sctx);
811
812 si_mark_atom_dirty(sctx, &sctx->clip_regs);
813 }
814
815 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
816 {
817 struct si_context *sctx = (struct si_context *)ctx;
818
819 if (sctx->queued.named.rasterizer == state)
820 si_pm4_bind_state(sctx, poly_offset, NULL);
821 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
822 }
823
824 /*
825 * infeered state between dsa and stencil ref
826 */
827 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
828 {
829 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
830 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
831 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
832
833 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
834 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
835 S_028430_STENCILMASK(dsa->valuemask[0]) |
836 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
837 S_028430_STENCILOPVAL(1));
838 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
839 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
840 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
841 S_028434_STENCILOPVAL_BF(1));
842 }
843
844 static void si_set_stencil_ref(struct pipe_context *ctx,
845 const struct pipe_stencil_ref *state)
846 {
847 struct si_context *sctx = (struct si_context *)ctx;
848
849 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
850 return;
851
852 sctx->stencil_ref.state = *state;
853 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
854 }
855
856
857 /*
858 * DSA
859 */
860
861 static uint32_t si_translate_stencil_op(int s_op)
862 {
863 switch (s_op) {
864 case PIPE_STENCIL_OP_KEEP:
865 return V_02842C_STENCIL_KEEP;
866 case PIPE_STENCIL_OP_ZERO:
867 return V_02842C_STENCIL_ZERO;
868 case PIPE_STENCIL_OP_REPLACE:
869 return V_02842C_STENCIL_REPLACE_TEST;
870 case PIPE_STENCIL_OP_INCR:
871 return V_02842C_STENCIL_ADD_CLAMP;
872 case PIPE_STENCIL_OP_DECR:
873 return V_02842C_STENCIL_SUB_CLAMP;
874 case PIPE_STENCIL_OP_INCR_WRAP:
875 return V_02842C_STENCIL_ADD_WRAP;
876 case PIPE_STENCIL_OP_DECR_WRAP:
877 return V_02842C_STENCIL_SUB_WRAP;
878 case PIPE_STENCIL_OP_INVERT:
879 return V_02842C_STENCIL_INVERT;
880 default:
881 R600_ERR("Unknown stencil op %d", s_op);
882 assert(0);
883 break;
884 }
885 return 0;
886 }
887
888 static void *si_create_dsa_state(struct pipe_context *ctx,
889 const struct pipe_depth_stencil_alpha_state *state)
890 {
891 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
892 struct si_pm4_state *pm4 = &dsa->pm4;
893 unsigned db_depth_control;
894 uint32_t db_stencil_control = 0;
895
896 if (dsa == NULL) {
897 return NULL;
898 }
899
900 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
901 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
902 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
903 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
904
905 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
906 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
907 S_028800_ZFUNC(state->depth.func) |
908 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
909
910 /* stencil */
911 if (state->stencil[0].enabled) {
912 db_depth_control |= S_028800_STENCIL_ENABLE(1);
913 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
914 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
915 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
916 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
917
918 if (state->stencil[1].enabled) {
919 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
920 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
921 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
922 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
923 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
924 }
925 }
926
927 /* alpha */
928 if (state->alpha.enabled) {
929 dsa->alpha_func = state->alpha.func;
930
931 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
932 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
933 } else {
934 dsa->alpha_func = PIPE_FUNC_ALWAYS;
935 }
936
937 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
938 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
939 if (state->depth.bounds_test) {
940 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
941 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
942 }
943
944 return dsa;
945 }
946
947 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
948 {
949 struct si_context *sctx = (struct si_context *)ctx;
950 struct si_state_dsa *dsa = state;
951
952 if (state == NULL)
953 return;
954
955 si_pm4_bind_state(sctx, dsa, dsa);
956
957 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
958 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
959 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
960 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
961 }
962 }
963
964 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
965 {
966 struct si_context *sctx = (struct si_context *)ctx;
967 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
968 }
969
970 static void *si_create_db_flush_dsa(struct si_context *sctx)
971 {
972 struct pipe_depth_stencil_alpha_state dsa = {};
973
974 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
975 }
976
977 /* DB RENDER STATE */
978
979 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
980 {
981 struct si_context *sctx = (struct si_context*)ctx;
982
983 si_mark_atom_dirty(sctx, &sctx->db_render_state);
984 }
985
986 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
987 {
988 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
989 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
990 unsigned db_shader_control;
991
992 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
993
994 /* DB_RENDER_CONTROL */
995 if (sctx->dbcb_depth_copy_enabled ||
996 sctx->dbcb_stencil_copy_enabled) {
997 radeon_emit(cs,
998 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
999 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1000 S_028000_COPY_CENTROID(1) |
1001 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1002 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1003 radeon_emit(cs,
1004 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1005 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1006 } else if (sctx->db_depth_clear) {
1007 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
1008 } else {
1009 radeon_emit(cs, 0);
1010 }
1011
1012 /* DB_COUNT_CONTROL (occlusion queries) */
1013 if (sctx->b.num_occlusion_queries > 0) {
1014 if (sctx->b.chip_class >= CIK) {
1015 radeon_emit(cs,
1016 S_028004_PERFECT_ZPASS_COUNTS(1) |
1017 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1018 S_028004_ZPASS_ENABLE(1) |
1019 S_028004_SLICE_EVEN_ENABLE(1) |
1020 S_028004_SLICE_ODD_ENABLE(1));
1021 } else {
1022 radeon_emit(cs,
1023 S_028004_PERFECT_ZPASS_COUNTS(1) |
1024 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1025 }
1026 } else {
1027 /* Disable occlusion queries. */
1028 if (sctx->b.chip_class >= CIK) {
1029 radeon_emit(cs, 0);
1030 } else {
1031 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1032 }
1033 }
1034
1035 /* DB_RENDER_OVERRIDE2 */
1036 if (sctx->db_depth_disable_expclear) {
1037 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1038 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
1039 } else {
1040 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
1041 }
1042
1043 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1044 sctx->ps_db_shader_control;
1045
1046 /* Bug workaround for smoothing (overrasterization) on SI. */
1047 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
1048 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1049 else
1050 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
1051
1052 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1053 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1054 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1055
1056 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1057 db_shader_control);
1058 }
1059
1060 /*
1061 * format translation
1062 */
1063 static uint32_t si_translate_colorformat(enum pipe_format format)
1064 {
1065 const struct util_format_description *desc = util_format_description(format);
1066
1067 #define HAS_SIZE(x,y,z,w) \
1068 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1069 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1070
1071 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1072 return V_028C70_COLOR_10_11_11;
1073
1074 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1075 return V_028C70_COLOR_INVALID;
1076
1077 switch (desc->nr_channels) {
1078 case 1:
1079 switch (desc->channel[0].size) {
1080 case 8:
1081 return V_028C70_COLOR_8;
1082 case 16:
1083 return V_028C70_COLOR_16;
1084 case 32:
1085 return V_028C70_COLOR_32;
1086 }
1087 break;
1088 case 2:
1089 if (desc->channel[0].size == desc->channel[1].size) {
1090 switch (desc->channel[0].size) {
1091 case 8:
1092 return V_028C70_COLOR_8_8;
1093 case 16:
1094 return V_028C70_COLOR_16_16;
1095 case 32:
1096 return V_028C70_COLOR_32_32;
1097 }
1098 } else if (HAS_SIZE(8,24,0,0)) {
1099 return V_028C70_COLOR_24_8;
1100 } else if (HAS_SIZE(24,8,0,0)) {
1101 return V_028C70_COLOR_8_24;
1102 }
1103 break;
1104 case 3:
1105 if (HAS_SIZE(5,6,5,0)) {
1106 return V_028C70_COLOR_5_6_5;
1107 } else if (HAS_SIZE(32,8,24,0)) {
1108 return V_028C70_COLOR_X24_8_32_FLOAT;
1109 }
1110 break;
1111 case 4:
1112 if (desc->channel[0].size == desc->channel[1].size &&
1113 desc->channel[0].size == desc->channel[2].size &&
1114 desc->channel[0].size == desc->channel[3].size) {
1115 switch (desc->channel[0].size) {
1116 case 4:
1117 return V_028C70_COLOR_4_4_4_4;
1118 case 8:
1119 return V_028C70_COLOR_8_8_8_8;
1120 case 16:
1121 return V_028C70_COLOR_16_16_16_16;
1122 case 32:
1123 return V_028C70_COLOR_32_32_32_32;
1124 }
1125 } else if (HAS_SIZE(5,5,5,1)) {
1126 return V_028C70_COLOR_1_5_5_5;
1127 } else if (HAS_SIZE(10,10,10,2)) {
1128 return V_028C70_COLOR_2_10_10_10;
1129 }
1130 break;
1131 }
1132 return V_028C70_COLOR_INVALID;
1133 }
1134
1135 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1136 {
1137 if (SI_BIG_ENDIAN) {
1138 switch(colorformat) {
1139 /* 8-bit buffers. */
1140 case V_028C70_COLOR_8:
1141 return V_028C70_ENDIAN_NONE;
1142
1143 /* 16-bit buffers. */
1144 case V_028C70_COLOR_5_6_5:
1145 case V_028C70_COLOR_1_5_5_5:
1146 case V_028C70_COLOR_4_4_4_4:
1147 case V_028C70_COLOR_16:
1148 case V_028C70_COLOR_8_8:
1149 return V_028C70_ENDIAN_8IN16;
1150
1151 /* 32-bit buffers. */
1152 case V_028C70_COLOR_8_8_8_8:
1153 case V_028C70_COLOR_2_10_10_10:
1154 case V_028C70_COLOR_8_24:
1155 case V_028C70_COLOR_24_8:
1156 case V_028C70_COLOR_16_16:
1157 return V_028C70_ENDIAN_8IN32;
1158
1159 /* 64-bit buffers. */
1160 case V_028C70_COLOR_16_16_16_16:
1161 return V_028C70_ENDIAN_8IN16;
1162
1163 case V_028C70_COLOR_32_32:
1164 return V_028C70_ENDIAN_8IN32;
1165
1166 /* 128-bit buffers. */
1167 case V_028C70_COLOR_32_32_32_32:
1168 return V_028C70_ENDIAN_8IN32;
1169 default:
1170 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1171 }
1172 } else {
1173 return V_028C70_ENDIAN_NONE;
1174 }
1175 }
1176
1177 /* Returns the size in bits of the widest component of a CB format */
1178 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1179 {
1180 switch(colorformat) {
1181 case V_028C70_COLOR_4_4_4_4:
1182 return 4;
1183
1184 case V_028C70_COLOR_1_5_5_5:
1185 case V_028C70_COLOR_5_5_5_1:
1186 return 5;
1187
1188 case V_028C70_COLOR_5_6_5:
1189 return 6;
1190
1191 case V_028C70_COLOR_8:
1192 case V_028C70_COLOR_8_8:
1193 case V_028C70_COLOR_8_8_8_8:
1194 return 8;
1195
1196 case V_028C70_COLOR_10_10_10_2:
1197 case V_028C70_COLOR_2_10_10_10:
1198 return 10;
1199
1200 case V_028C70_COLOR_10_11_11:
1201 case V_028C70_COLOR_11_11_10:
1202 return 11;
1203
1204 case V_028C70_COLOR_16:
1205 case V_028C70_COLOR_16_16:
1206 case V_028C70_COLOR_16_16_16_16:
1207 return 16;
1208
1209 case V_028C70_COLOR_8_24:
1210 case V_028C70_COLOR_24_8:
1211 return 24;
1212
1213 case V_028C70_COLOR_32:
1214 case V_028C70_COLOR_32_32:
1215 case V_028C70_COLOR_32_32_32_32:
1216 case V_028C70_COLOR_X24_8_32_FLOAT:
1217 return 32;
1218 }
1219
1220 assert(!"Unknown maximum component size");
1221 return 0;
1222 }
1223
1224 static uint32_t si_translate_dbformat(enum pipe_format format)
1225 {
1226 switch (format) {
1227 case PIPE_FORMAT_Z16_UNORM:
1228 return V_028040_Z_16;
1229 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1230 case PIPE_FORMAT_X8Z24_UNORM:
1231 case PIPE_FORMAT_Z24X8_UNORM:
1232 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1233 return V_028040_Z_24; /* deprecated on SI */
1234 case PIPE_FORMAT_Z32_FLOAT:
1235 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1236 return V_028040_Z_32_FLOAT;
1237 default:
1238 return V_028040_Z_INVALID;
1239 }
1240 }
1241
1242 /*
1243 * Texture translation
1244 */
1245
1246 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1247 enum pipe_format format,
1248 const struct util_format_description *desc,
1249 int first_non_void)
1250 {
1251 struct si_screen *sscreen = (struct si_screen*)screen;
1252 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1253 sscreen->b.info.drm_minor >= 31) ||
1254 sscreen->b.info.drm_major == 3;
1255 boolean uniform = TRUE;
1256 int i;
1257
1258 /* Colorspace (return non-RGB formats directly). */
1259 switch (desc->colorspace) {
1260 /* Depth stencil formats */
1261 case UTIL_FORMAT_COLORSPACE_ZS:
1262 switch (format) {
1263 case PIPE_FORMAT_Z16_UNORM:
1264 return V_008F14_IMG_DATA_FORMAT_16;
1265 case PIPE_FORMAT_X24S8_UINT:
1266 case PIPE_FORMAT_Z24X8_UNORM:
1267 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1268 return V_008F14_IMG_DATA_FORMAT_8_24;
1269 case PIPE_FORMAT_X8Z24_UNORM:
1270 case PIPE_FORMAT_S8X24_UINT:
1271 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1272 return V_008F14_IMG_DATA_FORMAT_24_8;
1273 case PIPE_FORMAT_S8_UINT:
1274 return V_008F14_IMG_DATA_FORMAT_8;
1275 case PIPE_FORMAT_Z32_FLOAT:
1276 return V_008F14_IMG_DATA_FORMAT_32;
1277 case PIPE_FORMAT_X32_S8X24_UINT:
1278 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1279 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1280 default:
1281 goto out_unknown;
1282 }
1283
1284 case UTIL_FORMAT_COLORSPACE_YUV:
1285 goto out_unknown; /* TODO */
1286
1287 case UTIL_FORMAT_COLORSPACE_SRGB:
1288 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1289 goto out_unknown;
1290 break;
1291
1292 default:
1293 break;
1294 }
1295
1296 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1297 if (!enable_compressed_formats)
1298 goto out_unknown;
1299
1300 switch (format) {
1301 case PIPE_FORMAT_RGTC1_SNORM:
1302 case PIPE_FORMAT_LATC1_SNORM:
1303 case PIPE_FORMAT_RGTC1_UNORM:
1304 case PIPE_FORMAT_LATC1_UNORM:
1305 return V_008F14_IMG_DATA_FORMAT_BC4;
1306 case PIPE_FORMAT_RGTC2_SNORM:
1307 case PIPE_FORMAT_LATC2_SNORM:
1308 case PIPE_FORMAT_RGTC2_UNORM:
1309 case PIPE_FORMAT_LATC2_UNORM:
1310 return V_008F14_IMG_DATA_FORMAT_BC5;
1311 default:
1312 goto out_unknown;
1313 }
1314 }
1315
1316 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1317 if (!enable_compressed_formats)
1318 goto out_unknown;
1319
1320 switch (format) {
1321 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1322 case PIPE_FORMAT_BPTC_SRGBA:
1323 return V_008F14_IMG_DATA_FORMAT_BC7;
1324 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1325 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1326 return V_008F14_IMG_DATA_FORMAT_BC6;
1327 default:
1328 goto out_unknown;
1329 }
1330 }
1331
1332 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1333 switch (format) {
1334 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1335 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1336 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1337 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1338 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1339 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1340 default:
1341 goto out_unknown;
1342 }
1343 }
1344
1345 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1346 if (!enable_compressed_formats)
1347 goto out_unknown;
1348
1349 if (!util_format_s3tc_enabled) {
1350 goto out_unknown;
1351 }
1352
1353 switch (format) {
1354 case PIPE_FORMAT_DXT1_RGB:
1355 case PIPE_FORMAT_DXT1_RGBA:
1356 case PIPE_FORMAT_DXT1_SRGB:
1357 case PIPE_FORMAT_DXT1_SRGBA:
1358 return V_008F14_IMG_DATA_FORMAT_BC1;
1359 case PIPE_FORMAT_DXT3_RGBA:
1360 case PIPE_FORMAT_DXT3_SRGBA:
1361 return V_008F14_IMG_DATA_FORMAT_BC2;
1362 case PIPE_FORMAT_DXT5_RGBA:
1363 case PIPE_FORMAT_DXT5_SRGBA:
1364 return V_008F14_IMG_DATA_FORMAT_BC3;
1365 default:
1366 goto out_unknown;
1367 }
1368 }
1369
1370 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1371 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1372 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1373 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1374 }
1375
1376 /* R8G8Bx_SNORM - TODO CxV8U8 */
1377
1378 /* See whether the components are of the same size. */
1379 for (i = 1; i < desc->nr_channels; i++) {
1380 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1381 }
1382
1383 /* Non-uniform formats. */
1384 if (!uniform) {
1385 switch(desc->nr_channels) {
1386 case 3:
1387 if (desc->channel[0].size == 5 &&
1388 desc->channel[1].size == 6 &&
1389 desc->channel[2].size == 5) {
1390 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1391 }
1392 goto out_unknown;
1393 case 4:
1394 if (desc->channel[0].size == 5 &&
1395 desc->channel[1].size == 5 &&
1396 desc->channel[2].size == 5 &&
1397 desc->channel[3].size == 1) {
1398 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1399 }
1400 if (desc->channel[0].size == 10 &&
1401 desc->channel[1].size == 10 &&
1402 desc->channel[2].size == 10 &&
1403 desc->channel[3].size == 2) {
1404 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1405 }
1406 goto out_unknown;
1407 }
1408 goto out_unknown;
1409 }
1410
1411 if (first_non_void < 0 || first_non_void > 3)
1412 goto out_unknown;
1413
1414 /* uniform formats */
1415 switch (desc->channel[first_non_void].size) {
1416 case 4:
1417 switch (desc->nr_channels) {
1418 #if 0 /* Not supported for render targets */
1419 case 2:
1420 return V_008F14_IMG_DATA_FORMAT_4_4;
1421 #endif
1422 case 4:
1423 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1424 }
1425 break;
1426 case 8:
1427 switch (desc->nr_channels) {
1428 case 1:
1429 return V_008F14_IMG_DATA_FORMAT_8;
1430 case 2:
1431 return V_008F14_IMG_DATA_FORMAT_8_8;
1432 case 4:
1433 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1434 }
1435 break;
1436 case 16:
1437 switch (desc->nr_channels) {
1438 case 1:
1439 return V_008F14_IMG_DATA_FORMAT_16;
1440 case 2:
1441 return V_008F14_IMG_DATA_FORMAT_16_16;
1442 case 4:
1443 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1444 }
1445 break;
1446 case 32:
1447 switch (desc->nr_channels) {
1448 case 1:
1449 return V_008F14_IMG_DATA_FORMAT_32;
1450 case 2:
1451 return V_008F14_IMG_DATA_FORMAT_32_32;
1452 #if 0 /* Not supported for render targets */
1453 case 3:
1454 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1455 #endif
1456 case 4:
1457 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1458 }
1459 }
1460
1461 out_unknown:
1462 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1463 return ~0;
1464 }
1465
1466 static unsigned si_tex_wrap(unsigned wrap)
1467 {
1468 switch (wrap) {
1469 default:
1470 case PIPE_TEX_WRAP_REPEAT:
1471 return V_008F30_SQ_TEX_WRAP;
1472 case PIPE_TEX_WRAP_CLAMP:
1473 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1474 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1475 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1476 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1477 return V_008F30_SQ_TEX_CLAMP_BORDER;
1478 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1479 return V_008F30_SQ_TEX_MIRROR;
1480 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1481 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1482 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1483 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1484 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1485 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1486 }
1487 }
1488
1489 static unsigned si_tex_filter(unsigned filter)
1490 {
1491 switch (filter) {
1492 default:
1493 case PIPE_TEX_FILTER_NEAREST:
1494 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1495 case PIPE_TEX_FILTER_LINEAR:
1496 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1497 }
1498 }
1499
1500 static unsigned si_tex_mipfilter(unsigned filter)
1501 {
1502 switch (filter) {
1503 case PIPE_TEX_MIPFILTER_NEAREST:
1504 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1505 case PIPE_TEX_MIPFILTER_LINEAR:
1506 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1507 default:
1508 case PIPE_TEX_MIPFILTER_NONE:
1509 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1510 }
1511 }
1512
1513 static unsigned si_tex_compare(unsigned compare)
1514 {
1515 switch (compare) {
1516 default:
1517 case PIPE_FUNC_NEVER:
1518 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1519 case PIPE_FUNC_LESS:
1520 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1521 case PIPE_FUNC_EQUAL:
1522 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1523 case PIPE_FUNC_LEQUAL:
1524 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1525 case PIPE_FUNC_GREATER:
1526 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1527 case PIPE_FUNC_NOTEQUAL:
1528 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1529 case PIPE_FUNC_GEQUAL:
1530 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1531 case PIPE_FUNC_ALWAYS:
1532 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1533 }
1534 }
1535
1536 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1537 {
1538 switch (dim) {
1539 default:
1540 case PIPE_TEXTURE_1D:
1541 return V_008F1C_SQ_RSRC_IMG_1D;
1542 case PIPE_TEXTURE_1D_ARRAY:
1543 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1544 case PIPE_TEXTURE_2D:
1545 case PIPE_TEXTURE_RECT:
1546 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1547 V_008F1C_SQ_RSRC_IMG_2D;
1548 case PIPE_TEXTURE_2D_ARRAY:
1549 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1550 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1551 case PIPE_TEXTURE_3D:
1552 return V_008F1C_SQ_RSRC_IMG_3D;
1553 case PIPE_TEXTURE_CUBE:
1554 case PIPE_TEXTURE_CUBE_ARRAY:
1555 return V_008F1C_SQ_RSRC_IMG_CUBE;
1556 }
1557 }
1558
1559 /*
1560 * Format support testing
1561 */
1562
1563 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1564 {
1565 return si_translate_texformat(screen, format, util_format_description(format),
1566 util_format_get_first_non_void_channel(format)) != ~0U;
1567 }
1568
1569 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1570 const struct util_format_description *desc,
1571 int first_non_void)
1572 {
1573 unsigned type = desc->channel[first_non_void].type;
1574 int i;
1575
1576 if (type == UTIL_FORMAT_TYPE_FIXED)
1577 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1578
1579 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1580 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1581
1582 if (desc->nr_channels == 4 &&
1583 desc->channel[0].size == 10 &&
1584 desc->channel[1].size == 10 &&
1585 desc->channel[2].size == 10 &&
1586 desc->channel[3].size == 2)
1587 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1588
1589 /* See whether the components are of the same size. */
1590 for (i = 0; i < desc->nr_channels; i++) {
1591 if (desc->channel[first_non_void].size != desc->channel[i].size)
1592 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1593 }
1594
1595 switch (desc->channel[first_non_void].size) {
1596 case 8:
1597 switch (desc->nr_channels) {
1598 case 1:
1599 return V_008F0C_BUF_DATA_FORMAT_8;
1600 case 2:
1601 return V_008F0C_BUF_DATA_FORMAT_8_8;
1602 case 3:
1603 case 4:
1604 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1605 }
1606 break;
1607 case 16:
1608 switch (desc->nr_channels) {
1609 case 1:
1610 return V_008F0C_BUF_DATA_FORMAT_16;
1611 case 2:
1612 return V_008F0C_BUF_DATA_FORMAT_16_16;
1613 case 3:
1614 case 4:
1615 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1616 }
1617 break;
1618 case 32:
1619 /* From the Southern Islands ISA documentation about MTBUF:
1620 * 'Memory reads of data in memory that is 32 or 64 bits do not
1621 * undergo any format conversion.'
1622 */
1623 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1624 !desc->channel[first_non_void].pure_integer)
1625 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1626
1627 switch (desc->nr_channels) {
1628 case 1:
1629 return V_008F0C_BUF_DATA_FORMAT_32;
1630 case 2:
1631 return V_008F0C_BUF_DATA_FORMAT_32_32;
1632 case 3:
1633 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1634 case 4:
1635 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1636 }
1637 break;
1638 }
1639
1640 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1641 }
1642
1643 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1644 const struct util_format_description *desc,
1645 int first_non_void)
1646 {
1647 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1648 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1649
1650 switch (desc->channel[first_non_void].type) {
1651 case UTIL_FORMAT_TYPE_SIGNED:
1652 if (desc->channel[first_non_void].normalized)
1653 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1654 else if (desc->channel[first_non_void].pure_integer)
1655 return V_008F0C_BUF_NUM_FORMAT_SINT;
1656 else
1657 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1658 break;
1659 case UTIL_FORMAT_TYPE_UNSIGNED:
1660 if (desc->channel[first_non_void].normalized)
1661 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1662 else if (desc->channel[first_non_void].pure_integer)
1663 return V_008F0C_BUF_NUM_FORMAT_UINT;
1664 else
1665 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1666 break;
1667 case UTIL_FORMAT_TYPE_FLOAT:
1668 default:
1669 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1670 }
1671 }
1672
1673 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1674 {
1675 const struct util_format_description *desc;
1676 int first_non_void;
1677 unsigned data_format;
1678
1679 desc = util_format_description(format);
1680 first_non_void = util_format_get_first_non_void_channel(format);
1681 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1682 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1683 }
1684
1685 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1686 {
1687 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1688 r600_translate_colorswap(format) != ~0U;
1689 }
1690
1691 static bool si_is_zs_format_supported(enum pipe_format format)
1692 {
1693 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1694 }
1695
1696 boolean si_is_format_supported(struct pipe_screen *screen,
1697 enum pipe_format format,
1698 enum pipe_texture_target target,
1699 unsigned sample_count,
1700 unsigned usage)
1701 {
1702 unsigned retval = 0;
1703
1704 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1705 R600_ERR("r600: unsupported texture type %d\n", target);
1706 return FALSE;
1707 }
1708
1709 if (!util_format_is_supported(format, usage))
1710 return FALSE;
1711
1712 if (sample_count > 1) {
1713 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1714 return FALSE;
1715
1716 switch (sample_count) {
1717 case 2:
1718 case 4:
1719 case 8:
1720 break;
1721 default:
1722 return FALSE;
1723 }
1724 }
1725
1726 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1727 if (target == PIPE_BUFFER) {
1728 if (si_is_vertex_format_supported(screen, format))
1729 retval |= PIPE_BIND_SAMPLER_VIEW;
1730 } else {
1731 if (si_is_sampler_format_supported(screen, format))
1732 retval |= PIPE_BIND_SAMPLER_VIEW;
1733 }
1734 }
1735
1736 if ((usage & (PIPE_BIND_RENDER_TARGET |
1737 PIPE_BIND_DISPLAY_TARGET |
1738 PIPE_BIND_SCANOUT |
1739 PIPE_BIND_SHARED |
1740 PIPE_BIND_BLENDABLE)) &&
1741 si_is_colorbuffer_format_supported(format)) {
1742 retval |= usage &
1743 (PIPE_BIND_RENDER_TARGET |
1744 PIPE_BIND_DISPLAY_TARGET |
1745 PIPE_BIND_SCANOUT |
1746 PIPE_BIND_SHARED);
1747 if (!util_format_is_pure_integer(format) &&
1748 !util_format_is_depth_or_stencil(format))
1749 retval |= usage & PIPE_BIND_BLENDABLE;
1750 }
1751
1752 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1753 si_is_zs_format_supported(format)) {
1754 retval |= PIPE_BIND_DEPTH_STENCIL;
1755 }
1756
1757 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1758 si_is_vertex_format_supported(screen, format)) {
1759 retval |= PIPE_BIND_VERTEX_BUFFER;
1760 }
1761
1762 if (usage & PIPE_BIND_TRANSFER_READ)
1763 retval |= PIPE_BIND_TRANSFER_READ;
1764 if (usage & PIPE_BIND_TRANSFER_WRITE)
1765 retval |= PIPE_BIND_TRANSFER_WRITE;
1766
1767 return retval == usage;
1768 }
1769
1770 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1771 {
1772 unsigned tile_mode_index = 0;
1773
1774 if (stencil) {
1775 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1776 } else {
1777 tile_mode_index = rtex->surface.tiling_index[level];
1778 }
1779 return tile_mode_index;
1780 }
1781
1782 /*
1783 * framebuffer handling
1784 */
1785
1786 static void si_initialize_color_surface(struct si_context *sctx,
1787 struct r600_surface *surf)
1788 {
1789 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1790 unsigned level = surf->base.u.tex.level;
1791 uint64_t offset = rtex->surface.level[level].offset;
1792 unsigned pitch, slice;
1793 unsigned color_info, color_attrib, color_pitch, color_view;
1794 unsigned tile_mode_index;
1795 unsigned format, swap, ntype, endian;
1796 const struct util_format_description *desc;
1797 int i;
1798 unsigned blend_clamp = 0, blend_bypass = 0;
1799 unsigned max_comp_size;
1800
1801 /* Layered rendering doesn't work with LINEAR_GENERAL.
1802 * (LINEAR_ALIGNED and others work) */
1803 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1804 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1805 offset += rtex->surface.level[level].slice_size *
1806 surf->base.u.tex.first_layer;
1807 color_view = 0;
1808 } else {
1809 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1810 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1811 }
1812
1813 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1814 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1815 if (slice) {
1816 slice = slice - 1;
1817 }
1818
1819 tile_mode_index = si_tile_mode_index(rtex, level, false);
1820
1821 desc = util_format_description(surf->base.format);
1822 for (i = 0; i < 4; i++) {
1823 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1824 break;
1825 }
1826 }
1827 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1828 ntype = V_028C70_NUMBER_FLOAT;
1829 } else {
1830 ntype = V_028C70_NUMBER_UNORM;
1831 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1832 ntype = V_028C70_NUMBER_SRGB;
1833 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1834 if (desc->channel[i].pure_integer) {
1835 ntype = V_028C70_NUMBER_SINT;
1836 } else {
1837 assert(desc->channel[i].normalized);
1838 ntype = V_028C70_NUMBER_SNORM;
1839 }
1840 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1841 if (desc->channel[i].pure_integer) {
1842 ntype = V_028C70_NUMBER_UINT;
1843 } else {
1844 assert(desc->channel[i].normalized);
1845 ntype = V_028C70_NUMBER_UNORM;
1846 }
1847 }
1848 }
1849
1850 format = si_translate_colorformat(surf->base.format);
1851 if (format == V_028C70_COLOR_INVALID) {
1852 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1853 }
1854 assert(format != V_028C70_COLOR_INVALID);
1855 swap = r600_translate_colorswap(surf->base.format);
1856 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1857 endian = V_028C70_ENDIAN_NONE;
1858 } else {
1859 endian = si_colorformat_endian_swap(format);
1860 }
1861
1862 /* blend clamp should be set for all NORM/SRGB types */
1863 if (ntype == V_028C70_NUMBER_UNORM ||
1864 ntype == V_028C70_NUMBER_SNORM ||
1865 ntype == V_028C70_NUMBER_SRGB)
1866 blend_clamp = 1;
1867
1868 /* set blend bypass according to docs if SINT/UINT or
1869 8/24 COLOR variants */
1870 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1871 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1872 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1873 blend_clamp = 0;
1874 blend_bypass = 1;
1875 }
1876
1877 color_info = S_028C70_FORMAT(format) |
1878 S_028C70_COMP_SWAP(swap) |
1879 S_028C70_BLEND_CLAMP(blend_clamp) |
1880 S_028C70_BLEND_BYPASS(blend_bypass) |
1881 S_028C70_NUMBER_TYPE(ntype) |
1882 S_028C70_ENDIAN(endian);
1883
1884 color_pitch = S_028C64_TILE_MAX(pitch);
1885
1886 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1887 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1888
1889 if (rtex->resource.b.b.nr_samples > 1) {
1890 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1891
1892 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1893 S_028C74_NUM_FRAGMENTS(log_samples);
1894
1895 if (rtex->fmask.size) {
1896 color_info |= S_028C70_COMPRESSION(1);
1897 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1898
1899 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1900
1901 if (sctx->b.chip_class == SI) {
1902 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1903 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1904 }
1905 if (sctx->b.chip_class >= CIK) {
1906 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1907 }
1908 }
1909 }
1910
1911 offset += rtex->resource.gpu_address;
1912
1913 surf->cb_color_base = offset >> 8;
1914 surf->cb_color_pitch = color_pitch;
1915 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1916 surf->cb_color_view = color_view;
1917 surf->cb_color_info = color_info;
1918 surf->cb_color_attrib = color_attrib;
1919
1920 if (sctx->b.chip_class >= VI)
1921 surf->cb_dcc_control = S_028C78_OVERWRITE_COMBINER_DISABLE(1);
1922
1923 if (rtex->fmask.size) {
1924 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1925 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1926 } else {
1927 /* This must be set for fast clear to work without FMASK. */
1928 surf->cb_color_fmask = surf->cb_color_base;
1929 surf->cb_color_fmask_slice = surf->cb_color_slice;
1930 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1931
1932 if (sctx->b.chip_class == SI) {
1933 unsigned bankh = util_logbase2(rtex->surface.bankh);
1934 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1935 }
1936
1937 if (sctx->b.chip_class >= CIK) {
1938 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1939 }
1940 }
1941
1942 /* Determine pixel shader export format */
1943 max_comp_size = si_colorformat_max_comp_size(format);
1944 if (ntype == V_028C70_NUMBER_SRGB ||
1945 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1946 max_comp_size <= 10) ||
1947 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1948 surf->export_16bpc = true;
1949 }
1950
1951 surf->color_initialized = true;
1952 }
1953
1954 static void si_init_depth_surface(struct si_context *sctx,
1955 struct r600_surface *surf)
1956 {
1957 struct si_screen *sscreen = sctx->screen;
1958 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1959 unsigned level = surf->base.u.tex.level;
1960 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1961 unsigned format, tile_mode_index, array_mode;
1962 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1963 uint32_t z_info, s_info, db_depth_info;
1964 uint64_t z_offs, s_offs;
1965 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1966
1967 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1968 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1969 case PIPE_FORMAT_X8Z24_UNORM:
1970 case PIPE_FORMAT_Z24X8_UNORM:
1971 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1972 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1973 break;
1974 case PIPE_FORMAT_Z32_FLOAT:
1975 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1976 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1977 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1978 break;
1979 case PIPE_FORMAT_Z16_UNORM:
1980 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1981 break;
1982 default:
1983 assert(0);
1984 }
1985
1986 format = si_translate_dbformat(rtex->resource.b.b.format);
1987
1988 if (format == V_028040_Z_INVALID) {
1989 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1990 }
1991 assert(format != V_028040_Z_INVALID);
1992
1993 s_offs = z_offs = rtex->resource.gpu_address;
1994 z_offs += rtex->surface.level[level].offset;
1995 s_offs += rtex->surface.stencil_level[level].offset;
1996
1997 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1998
1999 z_info = S_028040_FORMAT(format);
2000 if (rtex->resource.b.b.nr_samples > 1) {
2001 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2002 }
2003
2004 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2005 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2006 else
2007 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2008
2009 if (sctx->b.chip_class >= CIK) {
2010 switch (rtex->surface.level[level].mode) {
2011 case RADEON_SURF_MODE_2D:
2012 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
2013 break;
2014 case RADEON_SURF_MODE_1D:
2015 case RADEON_SURF_MODE_LINEAR_ALIGNED:
2016 case RADEON_SURF_MODE_LINEAR:
2017 default:
2018 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
2019 break;
2020 }
2021 tile_split = rtex->surface.tile_split;
2022 stile_split = rtex->surface.stencil_tile_split;
2023 macro_aspect = rtex->surface.mtilea;
2024 bankw = rtex->surface.bankw;
2025 bankh = rtex->surface.bankh;
2026 tile_split = cik_tile_split(tile_split);
2027 stile_split = cik_tile_split(stile_split);
2028 macro_aspect = cik_macro_tile_aspect(macro_aspect);
2029 bankw = cik_bank_wh(bankw);
2030 bankh = cik_bank_wh(bankh);
2031 nbanks = si_num_banks(sscreen, rtex);
2032 tile_mode_index = si_tile_mode_index(rtex, level, false);
2033 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
2034
2035 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
2036 S_02803C_PIPE_CONFIG(pipe_config) |
2037 S_02803C_BANK_WIDTH(bankw) |
2038 S_02803C_BANK_HEIGHT(bankh) |
2039 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
2040 S_02803C_NUM_BANKS(nbanks);
2041 z_info |= S_028040_TILE_SPLIT(tile_split);
2042 s_info |= S_028044_TILE_SPLIT(stile_split);
2043 } else {
2044 tile_mode_index = si_tile_mode_index(rtex, level, false);
2045 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2046 tile_mode_index = si_tile_mode_index(rtex, level, true);
2047 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2048 }
2049
2050 /* HiZ aka depth buffer htile */
2051 /* use htile only for first level */
2052 if (rtex->htile_buffer && !level) {
2053 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2054 S_028040_ALLOW_EXPCLEAR(1);
2055
2056 /* Use all of the htile_buffer for depth, because we don't
2057 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
2058 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2059
2060 uint64_t va = rtex->htile_buffer->gpu_address;
2061 db_htile_data_base = va >> 8;
2062 db_htile_surface = S_028ABC_FULL_CACHE(1);
2063 } else {
2064 db_htile_data_base = 0;
2065 db_htile_surface = 0;
2066 }
2067
2068 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2069
2070 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2071 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2072 surf->db_htile_data_base = db_htile_data_base;
2073 surf->db_depth_info = db_depth_info;
2074 surf->db_z_info = z_info;
2075 surf->db_stencil_info = s_info;
2076 surf->db_depth_base = z_offs >> 8;
2077 surf->db_stencil_base = s_offs >> 8;
2078 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2079 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2080 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2081 levelinfo->nblk_y) / 64 - 1);
2082 surf->db_htile_surface = db_htile_surface;
2083 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2084
2085 surf->depth_initialized = true;
2086 }
2087
2088 static void si_set_framebuffer_state(struct pipe_context *ctx,
2089 const struct pipe_framebuffer_state *state)
2090 {
2091 struct si_context *sctx = (struct si_context *)ctx;
2092 struct pipe_constant_buffer constbuf = {0};
2093 struct r600_surface *surf = NULL;
2094 struct r600_texture *rtex;
2095 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2096 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2097 int i;
2098
2099 /* Only flush TC when changing the framebuffer state, because
2100 * the only client not using TC that can change textures is
2101 * the framebuffer.
2102 *
2103 * Flush all CB and DB caches here because all buffers can be used
2104 * for write by both TC (with shader image stores) and CB/DB.
2105 */
2106 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2107 SI_CONTEXT_INV_TC_L2 |
2108 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2109
2110 /* Take the maximum of the old and new count. If the new count is lower,
2111 * dirtying is needed to disable the unbound colorbuffers.
2112 */
2113 sctx->framebuffer.dirty_cbufs |=
2114 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2115 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2116
2117 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2118
2119 sctx->framebuffer.export_16bpc = 0;
2120 sctx->framebuffer.compressed_cb_mask = 0;
2121 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2122 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2123 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2124 util_format_is_pure_integer(state->cbufs[0]->format);
2125
2126 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2127 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2128
2129 for (i = 0; i < state->nr_cbufs; i++) {
2130 if (!state->cbufs[i])
2131 continue;
2132
2133 surf = (struct r600_surface*)state->cbufs[i];
2134 rtex = (struct r600_texture*)surf->base.texture;
2135
2136 if (!surf->color_initialized) {
2137 si_initialize_color_surface(sctx, surf);
2138 }
2139
2140 if (surf->export_16bpc) {
2141 sctx->framebuffer.export_16bpc |= 1 << i;
2142 }
2143
2144 if (rtex->fmask.size && rtex->cmask.size) {
2145 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2146 }
2147 r600_context_add_resource_size(ctx, surf->base.texture);
2148 }
2149 /* Set the 16BPC export for possible dual-src blending. */
2150 if (i == 1 && surf && surf->export_16bpc) {
2151 sctx->framebuffer.export_16bpc |= 1 << 1;
2152 }
2153
2154 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2155
2156 if (state->zsbuf) {
2157 surf = (struct r600_surface*)state->zsbuf;
2158
2159 if (!surf->depth_initialized) {
2160 si_init_depth_surface(sctx, surf);
2161 }
2162 r600_context_add_resource_size(ctx, surf->base.texture);
2163 }
2164
2165 si_update_poly_offset_state(sctx);
2166 si_mark_atom_dirty(sctx, &sctx->cb_target_mask);
2167 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2168
2169 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2170 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2171 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2172
2173 /* Set sample locations as fragment shader constants. */
2174 switch (sctx->framebuffer.nr_samples) {
2175 case 1:
2176 constbuf.user_buffer = sctx->b.sample_locations_1x;
2177 break;
2178 case 2:
2179 constbuf.user_buffer = sctx->b.sample_locations_2x;
2180 break;
2181 case 4:
2182 constbuf.user_buffer = sctx->b.sample_locations_4x;
2183 break;
2184 case 8:
2185 constbuf.user_buffer = sctx->b.sample_locations_8x;
2186 break;
2187 case 16:
2188 constbuf.user_buffer = sctx->b.sample_locations_16x;
2189 break;
2190 default:
2191 assert(0);
2192 }
2193 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2194 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2195 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2196
2197 /* Smoothing (only possible with nr_samples == 1) uses the same
2198 * sample locations as the MSAA it simulates.
2199 *
2200 * Therefore, don't update the sample locations when
2201 * transitioning from no AA to smoothing-equivalent AA, and
2202 * vice versa.
2203 */
2204 if ((sctx->framebuffer.nr_samples != 1 ||
2205 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2206 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2207 old_nr_samples != 1))
2208 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2209 }
2210 }
2211
2212 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2213 {
2214 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2215 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2216 unsigned i, nr_cbufs = state->nr_cbufs;
2217 struct r600_texture *tex = NULL;
2218 struct r600_surface *cb = NULL;
2219
2220 /* Colorbuffers. */
2221 for (i = 0; i < nr_cbufs; i++) {
2222 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2223 continue;
2224
2225 cb = (struct r600_surface*)state->cbufs[i];
2226 if (!cb) {
2227 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2228 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2229 continue;
2230 }
2231
2232 tex = (struct r600_texture *)cb->base.texture;
2233 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2234 &tex->resource, RADEON_USAGE_READWRITE,
2235 tex->surface.nsamples > 1 ?
2236 RADEON_PRIO_COLOR_BUFFER_MSAA :
2237 RADEON_PRIO_COLOR_BUFFER);
2238
2239 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2240 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2241 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2242 RADEON_PRIO_CMASK);
2243 }
2244
2245 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2246 sctx->b.chip_class >= VI ? 14 : 13);
2247 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2248 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2249 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2250 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2251 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2252 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2253 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2254 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2255 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2256 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2257 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2258 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2259 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2260
2261 if (sctx->b.chip_class >= VI)
2262 radeon_emit(cs, 0); /* R_028C94_CB_COLOR0_DCC_BASE */
2263 }
2264 /* set CB_COLOR1_INFO for possible dual-src blending */
2265 if (i == 1 && state->cbufs[0] &&
2266 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2267 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2268 cb->cb_color_info | tex->cb_color_info);
2269 i++;
2270 }
2271 for (; i < 8 ; i++)
2272 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2273 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2274
2275 /* ZS buffer. */
2276 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2277 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2278 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2279
2280 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2281 &rtex->resource, RADEON_USAGE_READWRITE,
2282 zb->base.texture->nr_samples > 1 ?
2283 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2284 RADEON_PRIO_DEPTH_BUFFER);
2285
2286 if (zb->db_htile_data_base) {
2287 radeon_add_to_buffer_list(&sctx->b, &sctx->b.rings.gfx,
2288 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2289 RADEON_PRIO_HTILE);
2290 }
2291
2292 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2293 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2294
2295 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2296 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2297 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2298 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2299 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2300 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2301 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2302 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2303 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2304 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2305 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2306
2307 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2308 radeon_set_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2309 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2310 zb->pa_su_poly_offset_db_fmt_cntl);
2311 } else if (sctx->framebuffer.dirty_zsbuf) {
2312 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2313 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2314 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2315 }
2316
2317 /* Framebuffer dimensions. */
2318 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2319 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2320 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2321
2322 sctx->framebuffer.dirty_cbufs = 0;
2323 sctx->framebuffer.dirty_zsbuf = false;
2324 }
2325
2326 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2327 struct r600_atom *atom)
2328 {
2329 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2330 unsigned nr_samples = sctx->framebuffer.nr_samples;
2331
2332 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2333 SI_NUM_SMOOTH_AA_SAMPLES);
2334 }
2335
2336 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2337 {
2338 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2339
2340 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2341 sctx->ps_iter_samples,
2342 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2343 }
2344
2345
2346 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2347 {
2348 struct si_context *sctx = (struct si_context *)ctx;
2349
2350 if (sctx->ps_iter_samples == min_samples)
2351 return;
2352
2353 sctx->ps_iter_samples = min_samples;
2354
2355 if (sctx->framebuffer.nr_samples > 1)
2356 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2357 }
2358
2359 /*
2360 * Samplers
2361 */
2362
2363 /**
2364 * Create a sampler view.
2365 *
2366 * @param ctx context
2367 * @param texture texture
2368 * @param state sampler view template
2369 * @param width0 width0 override (for compressed textures as int)
2370 * @param height0 height0 override (for compressed textures as int)
2371 * @param force_level set the base address to the level (for compressed textures)
2372 */
2373 struct pipe_sampler_view *
2374 si_create_sampler_view_custom(struct pipe_context *ctx,
2375 struct pipe_resource *texture,
2376 const struct pipe_sampler_view *state,
2377 unsigned width0, unsigned height0,
2378 unsigned force_level)
2379 {
2380 struct si_context *sctx = (struct si_context*)ctx;
2381 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2382 struct r600_texture *tmp = (struct r600_texture*)texture;
2383 const struct util_format_description *desc;
2384 unsigned format, num_format, base_level, first_level, last_level;
2385 uint32_t pitch = 0;
2386 unsigned char state_swizzle[4], swizzle[4];
2387 unsigned height, depth, width;
2388 enum pipe_format pipe_format = state->format;
2389 struct radeon_surf_level *surflevel;
2390 int first_non_void;
2391 uint64_t va;
2392
2393 if (view == NULL)
2394 return NULL;
2395
2396 /* initialize base object */
2397 view->base = *state;
2398 view->base.texture = NULL;
2399 view->base.reference.count = 1;
2400 view->base.context = ctx;
2401
2402 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2403 if (!texture) {
2404 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2405 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2406 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2407 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2408 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2409 return &view->base;
2410 }
2411
2412 pipe_resource_reference(&view->base.texture, texture);
2413 view->resource = &tmp->resource;
2414
2415 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2416 state->format == PIPE_FORMAT_S8X24_UINT ||
2417 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2418 state->format == PIPE_FORMAT_S8_UINT)
2419 view->is_stencil_sampler = true;
2420
2421 /* Buffer resource. */
2422 if (texture->target == PIPE_BUFFER) {
2423 unsigned stride, num_records;
2424
2425 desc = util_format_description(state->format);
2426 first_non_void = util_format_get_first_non_void_channel(state->format);
2427 stride = desc->block.bits / 8;
2428 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2429 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2430 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2431
2432 num_records = state->u.buf.last_element + 1 - state->u.buf.first_element;
2433 num_records = MIN2(num_records, texture->width0 / stride);
2434
2435 if (sctx->b.chip_class >= VI)
2436 num_records *= stride;
2437
2438 view->state[4] = va;
2439 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2440 S_008F04_STRIDE(stride);
2441 view->state[6] = num_records;
2442 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2443 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2444 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2445 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2446 S_008F0C_NUM_FORMAT(num_format) |
2447 S_008F0C_DATA_FORMAT(format);
2448
2449 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2450 return &view->base;
2451 }
2452
2453 state_swizzle[0] = state->swizzle_r;
2454 state_swizzle[1] = state->swizzle_g;
2455 state_swizzle[2] = state->swizzle_b;
2456 state_swizzle[3] = state->swizzle_a;
2457
2458 surflevel = tmp->surface.level;
2459
2460 /* Texturing with separate depth and stencil. */
2461 if (tmp->is_depth && !tmp->is_flushing_texture) {
2462 switch (pipe_format) {
2463 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2464 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2465 break;
2466 case PIPE_FORMAT_X8Z24_UNORM:
2467 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2468 /* Z24 is always stored like this. */
2469 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2470 break;
2471 case PIPE_FORMAT_X24S8_UINT:
2472 case PIPE_FORMAT_S8X24_UINT:
2473 case PIPE_FORMAT_X32_S8X24_UINT:
2474 pipe_format = PIPE_FORMAT_S8_UINT;
2475 surflevel = tmp->surface.stencil_level;
2476 break;
2477 default:;
2478 }
2479 }
2480
2481 desc = util_format_description(pipe_format);
2482
2483 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2484 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2485 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2486
2487 switch (pipe_format) {
2488 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2489 case PIPE_FORMAT_X24S8_UINT:
2490 case PIPE_FORMAT_X32_S8X24_UINT:
2491 case PIPE_FORMAT_X8Z24_UNORM:
2492 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2493 break;
2494 default:
2495 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2496 }
2497 } else {
2498 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2499 }
2500
2501 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2502
2503 switch (pipe_format) {
2504 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2505 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2506 break;
2507 default:
2508 if (first_non_void < 0) {
2509 if (util_format_is_compressed(pipe_format)) {
2510 switch (pipe_format) {
2511 case PIPE_FORMAT_DXT1_SRGB:
2512 case PIPE_FORMAT_DXT1_SRGBA:
2513 case PIPE_FORMAT_DXT3_SRGBA:
2514 case PIPE_FORMAT_DXT5_SRGBA:
2515 case PIPE_FORMAT_BPTC_SRGBA:
2516 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2517 break;
2518 case PIPE_FORMAT_RGTC1_SNORM:
2519 case PIPE_FORMAT_LATC1_SNORM:
2520 case PIPE_FORMAT_RGTC2_SNORM:
2521 case PIPE_FORMAT_LATC2_SNORM:
2522 /* implies float, so use SNORM/UNORM to determine
2523 whether data is signed or not */
2524 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2525 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2526 break;
2527 default:
2528 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2529 break;
2530 }
2531 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2532 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2533 } else {
2534 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2535 }
2536 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2537 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2538 } else {
2539 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2540
2541 switch (desc->channel[first_non_void].type) {
2542 case UTIL_FORMAT_TYPE_FLOAT:
2543 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2544 break;
2545 case UTIL_FORMAT_TYPE_SIGNED:
2546 if (desc->channel[first_non_void].normalized)
2547 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2548 else if (desc->channel[first_non_void].pure_integer)
2549 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2550 else
2551 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2552 break;
2553 case UTIL_FORMAT_TYPE_UNSIGNED:
2554 if (desc->channel[first_non_void].normalized)
2555 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2556 else if (desc->channel[first_non_void].pure_integer)
2557 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2558 else
2559 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2560 }
2561 }
2562 }
2563
2564 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2565 if (format == ~0) {
2566 format = 0;
2567 }
2568
2569 base_level = 0;
2570 first_level = state->u.tex.first_level;
2571 last_level = state->u.tex.last_level;
2572 width = width0;
2573 height = height0;
2574 depth = texture->depth0;
2575
2576 if (force_level) {
2577 assert(force_level == first_level &&
2578 force_level == last_level);
2579 base_level = force_level;
2580 first_level = 0;
2581 last_level = 0;
2582 width = u_minify(width, force_level);
2583 height = u_minify(height, force_level);
2584 depth = u_minify(depth, force_level);
2585 }
2586
2587 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2588
2589 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2590 height = 1;
2591 depth = texture->array_size;
2592 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2593 depth = texture->array_size;
2594 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2595 depth = texture->array_size / 6;
2596
2597 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2598
2599 view->state[0] = va >> 8;
2600 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2601 S_008F14_DATA_FORMAT(format) |
2602 S_008F14_NUM_FORMAT(num_format));
2603 view->state[2] = (S_008F18_WIDTH(width - 1) |
2604 S_008F18_HEIGHT(height - 1));
2605 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2606 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2607 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2608 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2609 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2610 0 : first_level) |
2611 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2612 util_logbase2(texture->nr_samples) :
2613 last_level) |
2614 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, base_level, false)) |
2615 S_008F1C_POW2_PAD(texture->last_level > 0) |
2616 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2617 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2618 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2619 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2620 view->state[6] = 0;
2621 view->state[7] = 0;
2622
2623 /* Initialize the sampler view for FMASK. */
2624 if (tmp->fmask.size) {
2625 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2626 uint32_t fmask_format;
2627
2628 switch (texture->nr_samples) {
2629 case 2:
2630 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2631 break;
2632 case 4:
2633 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2634 break;
2635 case 8:
2636 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2637 break;
2638 default:
2639 assert(0);
2640 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2641 }
2642
2643 view->fmask_state[0] = va >> 8;
2644 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2645 S_008F14_DATA_FORMAT(fmask_format) |
2646 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2647 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2648 S_008F18_HEIGHT(height - 1);
2649 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2650 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2651 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2652 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2653 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2654 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2655 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2656 S_008F20_PITCH(tmp->fmask.pitch - 1);
2657 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2658 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2659 view->fmask_state[6] = 0;
2660 view->fmask_state[7] = 0;
2661 }
2662
2663 return &view->base;
2664 }
2665
2666 static struct pipe_sampler_view *
2667 si_create_sampler_view(struct pipe_context *ctx,
2668 struct pipe_resource *texture,
2669 const struct pipe_sampler_view *state)
2670 {
2671 return si_create_sampler_view_custom(ctx, texture, state,
2672 texture ? texture->width0 : 0,
2673 texture ? texture->height0 : 0, 0);
2674 }
2675
2676 static void si_sampler_view_destroy(struct pipe_context *ctx,
2677 struct pipe_sampler_view *state)
2678 {
2679 struct si_sampler_view *view = (struct si_sampler_view *)state;
2680
2681 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2682 LIST_DELINIT(&view->list);
2683
2684 pipe_resource_reference(&state->texture, NULL);
2685 FREE(view);
2686 }
2687
2688 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2689 {
2690 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2691 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2692 (linear_filter &&
2693 (wrap == PIPE_TEX_WRAP_CLAMP ||
2694 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2695 }
2696
2697 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2698 {
2699 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2700 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2701
2702 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2703 state->border_color.ui[2] || state->border_color.ui[3]) &&
2704 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2705 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2706 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2707 }
2708
2709 static void *si_create_sampler_state(struct pipe_context *ctx,
2710 const struct pipe_sampler_state *state)
2711 {
2712 struct si_context *sctx = (struct si_context *)ctx;
2713 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2714 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2715 unsigned border_color_type, border_color_index = 0;
2716
2717 if (rstate == NULL) {
2718 return NULL;
2719 }
2720
2721 if (!sampler_state_needs_border_color(state))
2722 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2723 else if (state->border_color.f[0] == 0 &&
2724 state->border_color.f[1] == 0 &&
2725 state->border_color.f[2] == 0 &&
2726 state->border_color.f[3] == 0)
2727 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2728 else if (state->border_color.f[0] == 0 &&
2729 state->border_color.f[1] == 0 &&
2730 state->border_color.f[2] == 0 &&
2731 state->border_color.f[3] == 1)
2732 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2733 else if (state->border_color.f[0] == 1 &&
2734 state->border_color.f[1] == 1 &&
2735 state->border_color.f[2] == 1 &&
2736 state->border_color.f[3] == 1)
2737 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2738 else {
2739 int i;
2740
2741 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2742
2743 /* Check if the border has been uploaded already. */
2744 for (i = 0; i < sctx->border_color_count; i++)
2745 if (memcmp(&sctx->border_color_table[i], &state->border_color,
2746 sizeof(state->border_color)) == 0)
2747 break;
2748
2749 if (i >= SI_MAX_BORDER_COLORS) {
2750 /* Getting 4096 unique border colors is very unlikely. */
2751 fprintf(stderr, "radeonsi: The border color table is full. "
2752 "Any new border colors will be just black. "
2753 "Please file a bug.\n");
2754 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2755 } else {
2756 if (i == sctx->border_color_count) {
2757 /* Upload a new border color. */
2758 memcpy(&sctx->border_color_table[i], &state->border_color,
2759 sizeof(state->border_color));
2760 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
2761 &state->border_color,
2762 sizeof(state->border_color));
2763 sctx->border_color_count++;
2764 }
2765
2766 border_color_index = i;
2767 }
2768 }
2769
2770 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2771 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2772 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2773 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2774 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2775 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2776 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2777 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2778 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2779 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2780 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2781 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2782 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2783 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
2784 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2785 return rstate;
2786 }
2787
2788 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2789 {
2790 struct si_context *sctx = (struct si_context *)ctx;
2791
2792 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
2793 return;
2794
2795 sctx->sample_mask.sample_mask = sample_mask;
2796 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
2797 }
2798
2799 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
2800 {
2801 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2802 unsigned mask = sctx->sample_mask.sample_mask;
2803
2804 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
2805 radeon_emit(cs, mask | (mask << 16));
2806 radeon_emit(cs, mask | (mask << 16));
2807 }
2808
2809 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2810 {
2811 free(state);
2812 }
2813
2814 /*
2815 * Vertex elements & buffers
2816 */
2817
2818 static void *si_create_vertex_elements(struct pipe_context *ctx,
2819 unsigned count,
2820 const struct pipe_vertex_element *elements)
2821 {
2822 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2823 int i;
2824
2825 assert(count < SI_MAX_ATTRIBS);
2826 if (!v)
2827 return NULL;
2828
2829 v->count = count;
2830 for (i = 0; i < count; ++i) {
2831 const struct util_format_description *desc;
2832 unsigned data_format, num_format;
2833 int first_non_void;
2834
2835 desc = util_format_description(elements[i].src_format);
2836 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2837 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2838 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2839
2840 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2841 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2842 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2843 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2844 S_008F0C_NUM_FORMAT(num_format) |
2845 S_008F0C_DATA_FORMAT(data_format);
2846 v->format_size[i] = desc->block.bits / 8;
2847 }
2848 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2849
2850 return v;
2851 }
2852
2853 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2854 {
2855 struct si_context *sctx = (struct si_context *)ctx;
2856 struct si_vertex_element *v = (struct si_vertex_element*)state;
2857
2858 sctx->vertex_elements = v;
2859 sctx->vertex_buffers_dirty = true;
2860 }
2861
2862 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2863 {
2864 struct si_context *sctx = (struct si_context *)ctx;
2865
2866 if (sctx->vertex_elements == state)
2867 sctx->vertex_elements = NULL;
2868 FREE(state);
2869 }
2870
2871 static void si_set_vertex_buffers(struct pipe_context *ctx,
2872 unsigned start_slot, unsigned count,
2873 const struct pipe_vertex_buffer *buffers)
2874 {
2875 struct si_context *sctx = (struct si_context *)ctx;
2876 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2877 int i;
2878
2879 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2880
2881 if (buffers) {
2882 for (i = 0; i < count; i++) {
2883 const struct pipe_vertex_buffer *src = buffers + i;
2884 struct pipe_vertex_buffer *dsti = dst + i;
2885
2886 pipe_resource_reference(&dsti->buffer, src->buffer);
2887 dsti->buffer_offset = src->buffer_offset;
2888 dsti->stride = src->stride;
2889 r600_context_add_resource_size(ctx, src->buffer);
2890 }
2891 } else {
2892 for (i = 0; i < count; i++) {
2893 pipe_resource_reference(&dst[i].buffer, NULL);
2894 }
2895 }
2896 sctx->vertex_buffers_dirty = true;
2897 }
2898
2899 static void si_set_index_buffer(struct pipe_context *ctx,
2900 const struct pipe_index_buffer *ib)
2901 {
2902 struct si_context *sctx = (struct si_context *)ctx;
2903
2904 if (ib) {
2905 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2906 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2907 r600_context_add_resource_size(ctx, ib->buffer);
2908 } else {
2909 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2910 }
2911 }
2912
2913 /*
2914 * Misc
2915 */
2916 static void si_set_polygon_stipple(struct pipe_context *ctx,
2917 const struct pipe_poly_stipple *state)
2918 {
2919 struct si_context *sctx = (struct si_context *)ctx;
2920 struct pipe_resource *tex;
2921 struct pipe_sampler_view *view;
2922 bool is_zero = true;
2923 bool is_one = true;
2924 int i;
2925
2926 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2927 * the resource is NULL/invalid. Take advantage of this fact and skip
2928 * texture allocation if the stipple pattern is constant.
2929 *
2930 * This is an optimization for the common case when stippling isn't
2931 * used but set_polygon_stipple is still called by st/mesa.
2932 */
2933 for (i = 0; i < Elements(state->stipple); i++) {
2934 is_zero = is_zero && state->stipple[i] == 0;
2935 is_one = is_one && state->stipple[i] == 0xffffffff;
2936 }
2937
2938 if (is_zero || is_one) {
2939 struct pipe_sampler_view templ = {{0}};
2940
2941 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2942 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2943 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2944 /* The pattern should be inverted in the texture. */
2945 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2946
2947 view = ctx->create_sampler_view(ctx, NULL, &templ);
2948 } else {
2949 /* Create a new texture. */
2950 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2951 if (!tex)
2952 return;
2953
2954 view = util_pstipple_create_sampler_view(ctx, tex);
2955 pipe_resource_reference(&tex, NULL);
2956 }
2957
2958 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2959 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2960 pipe_sampler_view_reference(&view, NULL);
2961
2962 /* Bind the sampler state if needed. */
2963 if (!sctx->pstipple_sampler_state) {
2964 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2965 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2966 SI_POLY_STIPPLE_SAMPLER, 1,
2967 &sctx->pstipple_sampler_state);
2968 }
2969 }
2970
2971 static void si_set_tess_state(struct pipe_context *ctx,
2972 const float default_outer_level[4],
2973 const float default_inner_level[2])
2974 {
2975 struct si_context *sctx = (struct si_context *)ctx;
2976 struct pipe_constant_buffer cb;
2977 float array[8];
2978
2979 memcpy(array, default_outer_level, sizeof(float) * 4);
2980 memcpy(array+4, default_inner_level, sizeof(float) * 2);
2981
2982 cb.buffer = NULL;
2983 cb.user_buffer = NULL;
2984 cb.buffer_size = sizeof(array);
2985
2986 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
2987 (void*)array, sizeof(array),
2988 &cb.buffer_offset);
2989
2990 ctx->set_constant_buffer(ctx, PIPE_SHADER_TESS_CTRL,
2991 SI_DRIVER_STATE_CONST_BUF, &cb);
2992 pipe_resource_reference(&cb.buffer, NULL);
2993 }
2994
2995 static void si_texture_barrier(struct pipe_context *ctx)
2996 {
2997 struct si_context *sctx = (struct si_context *)ctx;
2998
2999 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
3000 SI_CONTEXT_INV_TC_L2 |
3001 SI_CONTEXT_FLUSH_AND_INV_CB;
3002 }
3003
3004 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3005 {
3006 struct pipe_blend_state blend;
3007
3008 memset(&blend, 0, sizeof(blend));
3009 blend.independent_blend_enable = true;
3010 blend.rt[0].colormask = 0xf;
3011 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3012 }
3013
3014 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3015 bool include_draw_vbo)
3016 {
3017 si_need_cs_space((struct si_context*)ctx);
3018 }
3019
3020 static void si_init_config(struct si_context *sctx);
3021
3022 void si_init_state_functions(struct si_context *sctx)
3023 {
3024 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3025 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3026
3027 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3028 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3029 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3030 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3031 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3032 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3033 si_init_atom(sctx, &sctx->cb_target_mask, &sctx->atoms.s.cb_target_mask, si_emit_cb_target_mask);
3034 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3035 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3036 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3037 si_init_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors, si_emit_scissors);
3038 si_init_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports, si_emit_viewports);
3039 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3040
3041 sctx->b.b.create_blend_state = si_create_blend_state;
3042 sctx->b.b.bind_blend_state = si_bind_blend_state;
3043 sctx->b.b.delete_blend_state = si_delete_blend_state;
3044 sctx->b.b.set_blend_color = si_set_blend_color;
3045
3046 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3047 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3048 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3049
3050 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3051 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3052 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3053
3054 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3055 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3056 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3057 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3058
3059 sctx->b.b.set_clip_state = si_set_clip_state;
3060 sctx->b.b.set_scissor_states = si_set_scissor_states;
3061 sctx->b.b.set_viewport_states = si_set_viewport_states;
3062 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3063
3064 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3065 sctx->b.b.get_sample_position = cayman_get_sample_position;
3066
3067 sctx->b.b.create_sampler_state = si_create_sampler_state;
3068 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3069
3070 sctx->b.b.create_sampler_view = si_create_sampler_view;
3071 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3072
3073 sctx->b.b.set_sample_mask = si_set_sample_mask;
3074
3075 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3076 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3077 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3078 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3079 sctx->b.b.set_index_buffer = si_set_index_buffer;
3080
3081 sctx->b.b.texture_barrier = si_texture_barrier;
3082 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
3083 sctx->b.b.set_min_samples = si_set_min_samples;
3084 sctx->b.b.set_tess_state = si_set_tess_state;
3085
3086 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3087 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3088
3089 sctx->b.b.draw_vbo = si_draw_vbo;
3090
3091 if (sctx->b.chip_class >= CIK) {
3092 sctx->b.dma_copy = cik_sdma_copy;
3093 } else {
3094 sctx->b.dma_copy = si_dma_copy;
3095 }
3096
3097 si_init_config(sctx);
3098 }
3099
3100 static void
3101 si_write_harvested_raster_configs(struct si_context *sctx,
3102 struct si_pm4_state *pm4,
3103 unsigned raster_config,
3104 unsigned raster_config_1)
3105 {
3106 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3107 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3108 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3109 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3110 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3111 unsigned rb_per_se = num_rb / num_se;
3112 unsigned se_mask[4];
3113 unsigned se;
3114
3115 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3116 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3117 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3118 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3119
3120 assert(num_se == 1 || num_se == 2 || num_se == 4);
3121 assert(sh_per_se == 1 || sh_per_se == 2);
3122 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3123
3124 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3125 * fields are for, so I'm leaving them as their default
3126 * values. */
3127
3128 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3129 (!se_mask[2] && !se_mask[3]))) {
3130 raster_config_1 &= C_028354_SE_PAIR_MAP;
3131
3132 if (!se_mask[0] && !se_mask[1]) {
3133 raster_config_1 |=
3134 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3135 } else {
3136 raster_config_1 |=
3137 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3138 }
3139 }
3140
3141 for (se = 0; se < num_se; se++) {
3142 unsigned raster_config_se = raster_config;
3143 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3144 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3145 int idx = (se / 2) * 2;
3146
3147 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3148 raster_config_se &= C_028350_SE_MAP;
3149
3150 if (!se_mask[idx]) {
3151 raster_config_se |=
3152 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3153 } else {
3154 raster_config_se |=
3155 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3156 }
3157 }
3158
3159 pkr0_mask &= rb_mask;
3160 pkr1_mask &= rb_mask;
3161 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3162 raster_config_se &= C_028350_PKR_MAP;
3163
3164 if (!pkr0_mask) {
3165 raster_config_se |=
3166 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3167 } else {
3168 raster_config_se |=
3169 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3170 }
3171 }
3172
3173 if (rb_per_se >= 2) {
3174 unsigned rb0_mask = 1 << (se * rb_per_se);
3175 unsigned rb1_mask = rb0_mask << 1;
3176
3177 rb0_mask &= rb_mask;
3178 rb1_mask &= rb_mask;
3179 if (!rb0_mask || !rb1_mask) {
3180 raster_config_se &= C_028350_RB_MAP_PKR0;
3181
3182 if (!rb0_mask) {
3183 raster_config_se |=
3184 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3185 } else {
3186 raster_config_se |=
3187 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3188 }
3189 }
3190
3191 if (rb_per_se > 2) {
3192 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3193 rb1_mask = rb0_mask << 1;
3194 rb0_mask &= rb_mask;
3195 rb1_mask &= rb_mask;
3196 if (!rb0_mask || !rb1_mask) {
3197 raster_config_se &= C_028350_RB_MAP_PKR1;
3198
3199 if (!rb0_mask) {
3200 raster_config_se |=
3201 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3202 } else {
3203 raster_config_se |=
3204 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3205 }
3206 }
3207 }
3208 }
3209
3210 /* GRBM_GFX_INDEX is privileged on VI */
3211 if (sctx->b.chip_class <= CIK)
3212 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3213 SE_INDEX(se) | SH_BROADCAST_WRITES |
3214 INSTANCE_BROADCAST_WRITES);
3215 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3216 if (sctx->b.chip_class >= CIK)
3217 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3218 }
3219
3220 /* GRBM_GFX_INDEX is privileged on VI */
3221 if (sctx->b.chip_class <= CIK)
3222 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3223 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3224 INSTANCE_BROADCAST_WRITES);
3225 }
3226
3227 static void si_init_config(struct si_context *sctx)
3228 {
3229 unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
3230 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3231 unsigned raster_config, raster_config_1;
3232 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3233 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3234 int i;
3235
3236 if (pm4 == NULL)
3237 return;
3238
3239 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3240 si_pm4_cmd_add(pm4, 0x80000000);
3241 si_pm4_cmd_add(pm4, 0x80000000);
3242 si_pm4_cmd_end(pm4, false);
3243
3244 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3245 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3246
3247 /* FIXME calculate these values somehow ??? */
3248 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3249 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3250 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3251
3252 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3253 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3254
3255 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3256 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3257 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3258 if (sctx->b.chip_class < CIK)
3259 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3260 S_008A14_CLIP_VTX_REORDER_ENA(1));
3261
3262 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3263 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3264
3265 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3266
3267 for (i = 0; i < 16; i++) {
3268 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3269 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3270 }
3271
3272 switch (sctx->screen->b.family) {
3273 case CHIP_TAHITI:
3274 case CHIP_PITCAIRN:
3275 raster_config = 0x2a00126a;
3276 raster_config_1 = 0x00000000;
3277 break;
3278 case CHIP_VERDE:
3279 raster_config = 0x0000124a;
3280 raster_config_1 = 0x00000000;
3281 break;
3282 case CHIP_OLAND:
3283 raster_config = 0x00000082;
3284 raster_config_1 = 0x00000000;
3285 break;
3286 case CHIP_HAINAN:
3287 raster_config = 0x00000000;
3288 raster_config_1 = 0x00000000;
3289 break;
3290 case CHIP_BONAIRE:
3291 raster_config = 0x16000012;
3292 raster_config_1 = 0x00000000;
3293 break;
3294 case CHIP_HAWAII:
3295 raster_config = 0x3a00161a;
3296 raster_config_1 = 0x0000002e;
3297 break;
3298 case CHIP_FIJI:
3299 /* Fiji should be same as Hawaii, but that causes corruption in some cases */
3300 raster_config = 0x16000012; /* 0x3a00161a */
3301 raster_config_1 = 0x0000002a; /* 0x0000002e */
3302 break;
3303 case CHIP_TONGA:
3304 raster_config = 0x16000012;
3305 raster_config_1 = 0x0000002a;
3306 break;
3307 case CHIP_ICELAND:
3308 raster_config = 0x00000002;
3309 raster_config_1 = 0x00000000;
3310 break;
3311 case CHIP_CARRIZO:
3312 raster_config = 0x00000002;
3313 raster_config_1 = 0x00000000;
3314 break;
3315 case CHIP_KAVERI:
3316 /* KV should be 0x00000002, but that causes problems with radeon */
3317 raster_config = 0x00000000; /* 0x00000002 */
3318 raster_config_1 = 0x00000000;
3319 break;
3320 case CHIP_KABINI:
3321 case CHIP_MULLINS:
3322 raster_config = 0x00000000;
3323 raster_config_1 = 0x00000000;
3324 break;
3325 default:
3326 fprintf(stderr,
3327 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3328 raster_config = 0x00000000;
3329 raster_config_1 = 0x00000000;
3330 break;
3331 }
3332
3333 /* Always use the default config when all backends are enabled
3334 * (or when we failed to determine the enabled backends).
3335 */
3336 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3337 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3338 raster_config);
3339 if (sctx->b.chip_class >= CIK)
3340 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3341 raster_config_1);
3342 } else {
3343 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3344 }
3345
3346 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3347 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3348 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3349 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3350 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3351 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3352 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3353
3354 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3355 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3356 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3357 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3358 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3359 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3360 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3361 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3362 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3363 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3364 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3365 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3366 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3367
3368 /* There is a hang if stencil is used and fast stencil is enabled
3369 * regardless of whether HTILE is depth-only or not.
3370 */
3371 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3372 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3373 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3374 S_02800C_FAST_STENCIL_DISABLE(1));
3375
3376 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3377 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3378 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3379
3380 if (sctx->b.chip_class >= CIK) {
3381 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffc));
3382 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3383 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xfffe));
3384 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3385 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3386 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3387 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3388 }
3389
3390 if (sctx->b.chip_class >= VI) {
3391 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3392 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1));
3393 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3394 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3395 }
3396
3397 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3398 if (sctx->b.chip_class >= CIK)
3399 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3400 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3401 RADEON_PRIO_BORDER_COLORS);
3402
3403 si_pm4_upload_indirect_buffer(sctx, pm4);
3404 sctx->init_config = pm4;
3405 }