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radeonsi: move all shader-related functions to a new file si_state_shaders.c
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35
36 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
37 void (*emit)(struct si_context *ctx, struct r600_atom *state),
38 unsigned num_dw)
39 {
40 atom->emit = (void*)emit;
41 atom->num_dw = num_dw;
42 atom->dirty = false;
43 *list_elem = atom;
44 }
45
46 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
47 {
48 if (sscreen->b.chip_class == CIK &&
49 sscreen->b.info.cik_macrotile_mode_array_valid) {
50 unsigned index, tileb;
51
52 tileb = 8 * 8 * tex->surface.bpe;
53 tileb = MIN2(tex->surface.tile_split, tileb);
54
55 for (index = 0; tileb > 64; index++) {
56 tileb >>= 1;
57 }
58 assert(index < 16);
59
60 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
61 }
62
63 if (sscreen->b.chip_class == SI &&
64 sscreen->b.info.si_tile_mode_array_valid) {
65 /* Don't use stencil_tiling_index, because num_banks is always
66 * read from the depth mode. */
67 unsigned tile_mode_index = tex->surface.tiling_index[0];
68 assert(tile_mode_index < 32);
69
70 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
71 }
72
73 /* The old way. */
74 switch (sscreen->b.tiling_info.num_banks) {
75 case 2:
76 return V_02803C_ADDR_SURF_2_BANK;
77 case 4:
78 return V_02803C_ADDR_SURF_4_BANK;
79 case 8:
80 default:
81 return V_02803C_ADDR_SURF_8_BANK;
82 case 16:
83 return V_02803C_ADDR_SURF_16_BANK;
84 }
85 }
86
87 unsigned cik_tile_split(unsigned tile_split)
88 {
89 switch (tile_split) {
90 case 64:
91 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
92 break;
93 case 128:
94 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
95 break;
96 case 256:
97 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
98 break;
99 case 512:
100 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
101 break;
102 default:
103 case 1024:
104 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
105 break;
106 case 2048:
107 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
108 break;
109 case 4096:
110 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
111 break;
112 }
113 return tile_split;
114 }
115
116 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
117 {
118 switch (macro_tile_aspect) {
119 default:
120 case 1:
121 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
122 break;
123 case 2:
124 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
125 break;
126 case 4:
127 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
128 break;
129 case 8:
130 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
131 break;
132 }
133 return macro_tile_aspect;
134 }
135
136 unsigned cik_bank_wh(unsigned bankwh)
137 {
138 switch (bankwh) {
139 default:
140 case 1:
141 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
142 break;
143 case 2:
144 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
145 break;
146 case 4:
147 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
148 break;
149 case 8:
150 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
151 break;
152 }
153 return bankwh;
154 }
155
156 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
157 {
158 if (sscreen->b.info.si_tile_mode_array_valid) {
159 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
160
161 return G_009910_PIPE_CONFIG(gb_tile_mode);
162 }
163
164 /* This is probably broken for a lot of chips, but it's only used
165 * if the kernel cannot return the tile mode array for CIK. */
166 switch (sscreen->b.info.r600_num_tile_pipes) {
167 case 16:
168 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
169 case 8:
170 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
171 case 4:
172 default:
173 if (sscreen->b.info.r600_num_backends == 4)
174 return V_02803C_X_ADDR_SURF_P4_16X16;
175 else
176 return V_02803C_X_ADDR_SURF_P4_8X16;
177 case 2:
178 return V_02803C_ADDR_SURF_P2;
179 }
180 }
181
182 static unsigned si_map_swizzle(unsigned swizzle)
183 {
184 switch (swizzle) {
185 case UTIL_FORMAT_SWIZZLE_Y:
186 return V_008F0C_SQ_SEL_Y;
187 case UTIL_FORMAT_SWIZZLE_Z:
188 return V_008F0C_SQ_SEL_Z;
189 case UTIL_FORMAT_SWIZZLE_W:
190 return V_008F0C_SQ_SEL_W;
191 case UTIL_FORMAT_SWIZZLE_0:
192 return V_008F0C_SQ_SEL_0;
193 case UTIL_FORMAT_SWIZZLE_1:
194 return V_008F0C_SQ_SEL_1;
195 default: /* UTIL_FORMAT_SWIZZLE_X */
196 return V_008F0C_SQ_SEL_X;
197 }
198 }
199
200 static uint32_t S_FIXED(float value, uint32_t frac_bits)
201 {
202 return value * (1 << frac_bits);
203 }
204
205 /* 12.4 fixed-point */
206 static unsigned si_pack_float_12p4(float x)
207 {
208 return x <= 0 ? 0 :
209 x >= 4096 ? 0xffff : x * 16;
210 }
211
212 /*
213 * inferred framebuffer and blender state
214 */
215 static void si_update_fb_blend_state(struct si_context *sctx)
216 {
217 struct si_pm4_state *pm4;
218 struct si_state_blend *blend = sctx->queued.named.blend;
219 uint32_t mask;
220
221 if (blend == NULL)
222 return;
223
224 pm4 = CALLOC_STRUCT(si_pm4_state);
225 if (pm4 == NULL)
226 return;
227
228 mask = (1ULL << ((unsigned)sctx->framebuffer.state.nr_cbufs * 4)) - 1;
229 mask &= blend->cb_target_mask;
230 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
231
232 si_pm4_set_state(sctx, fb_blend, pm4);
233 }
234
235 /*
236 * Blender functions
237 */
238
239 static uint32_t si_translate_blend_function(int blend_func)
240 {
241 switch (blend_func) {
242 case PIPE_BLEND_ADD:
243 return V_028780_COMB_DST_PLUS_SRC;
244 case PIPE_BLEND_SUBTRACT:
245 return V_028780_COMB_SRC_MINUS_DST;
246 case PIPE_BLEND_REVERSE_SUBTRACT:
247 return V_028780_COMB_DST_MINUS_SRC;
248 case PIPE_BLEND_MIN:
249 return V_028780_COMB_MIN_DST_SRC;
250 case PIPE_BLEND_MAX:
251 return V_028780_COMB_MAX_DST_SRC;
252 default:
253 R600_ERR("Unknown blend function %d\n", blend_func);
254 assert(0);
255 break;
256 }
257 return 0;
258 }
259
260 static uint32_t si_translate_blend_factor(int blend_fact)
261 {
262 switch (blend_fact) {
263 case PIPE_BLENDFACTOR_ONE:
264 return V_028780_BLEND_ONE;
265 case PIPE_BLENDFACTOR_SRC_COLOR:
266 return V_028780_BLEND_SRC_COLOR;
267 case PIPE_BLENDFACTOR_SRC_ALPHA:
268 return V_028780_BLEND_SRC_ALPHA;
269 case PIPE_BLENDFACTOR_DST_ALPHA:
270 return V_028780_BLEND_DST_ALPHA;
271 case PIPE_BLENDFACTOR_DST_COLOR:
272 return V_028780_BLEND_DST_COLOR;
273 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
274 return V_028780_BLEND_SRC_ALPHA_SATURATE;
275 case PIPE_BLENDFACTOR_CONST_COLOR:
276 return V_028780_BLEND_CONSTANT_COLOR;
277 case PIPE_BLENDFACTOR_CONST_ALPHA:
278 return V_028780_BLEND_CONSTANT_ALPHA;
279 case PIPE_BLENDFACTOR_ZERO:
280 return V_028780_BLEND_ZERO;
281 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
282 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
283 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
284 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
285 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
286 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
287 case PIPE_BLENDFACTOR_INV_DST_COLOR:
288 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
289 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
290 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
291 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
292 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
293 case PIPE_BLENDFACTOR_SRC1_COLOR:
294 return V_028780_BLEND_SRC1_COLOR;
295 case PIPE_BLENDFACTOR_SRC1_ALPHA:
296 return V_028780_BLEND_SRC1_ALPHA;
297 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
298 return V_028780_BLEND_INV_SRC1_COLOR;
299 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
300 return V_028780_BLEND_INV_SRC1_ALPHA;
301 default:
302 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
303 assert(0);
304 break;
305 }
306 return 0;
307 }
308
309 static void *si_create_blend_state_mode(struct pipe_context *ctx,
310 const struct pipe_blend_state *state,
311 unsigned mode)
312 {
313 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
314 struct si_pm4_state *pm4 = &blend->pm4;
315
316 uint32_t color_control = 0;
317
318 if (blend == NULL)
319 return NULL;
320
321 blend->alpha_to_one = state->alpha_to_one;
322
323 if (state->logicop_enable) {
324 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
325 } else {
326 color_control |= S_028808_ROP3(0xcc);
327 }
328
329 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
330 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
331 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
332 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
333 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
334 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
335
336 blend->cb_target_mask = 0;
337 for (int i = 0; i < 8; i++) {
338 /* state->rt entries > 0 only written if independent blending */
339 const int j = state->independent_blend_enable ? i : 0;
340
341 unsigned eqRGB = state->rt[j].rgb_func;
342 unsigned srcRGB = state->rt[j].rgb_src_factor;
343 unsigned dstRGB = state->rt[j].rgb_dst_factor;
344 unsigned eqA = state->rt[j].alpha_func;
345 unsigned srcA = state->rt[j].alpha_src_factor;
346 unsigned dstA = state->rt[j].alpha_dst_factor;
347
348 unsigned blend_cntl = 0;
349
350 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
351 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
352
353 if (!state->rt[j].blend_enable) {
354 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
355 continue;
356 }
357
358 blend_cntl |= S_028780_ENABLE(1);
359 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
360 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
361 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
362
363 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
364 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
365 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
366 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
367 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
368 }
369 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
370 }
371
372 if (blend->cb_target_mask) {
373 color_control |= S_028808_MODE(mode);
374 } else {
375 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
376 }
377 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
378
379 return blend;
380 }
381
382 static void *si_create_blend_state(struct pipe_context *ctx,
383 const struct pipe_blend_state *state)
384 {
385 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
386 }
387
388 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
389 {
390 struct si_context *sctx = (struct si_context *)ctx;
391 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
392 si_update_fb_blend_state(sctx);
393 }
394
395 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
396 {
397 struct si_context *sctx = (struct si_context *)ctx;
398 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
399 }
400
401 static void si_set_blend_color(struct pipe_context *ctx,
402 const struct pipe_blend_color *state)
403 {
404 struct si_context *sctx = (struct si_context *)ctx;
405 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
406
407 if (pm4 == NULL)
408 return;
409
410 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
411 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
412 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
413 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
414
415 si_pm4_set_state(sctx, blend_color, pm4);
416 }
417
418 /*
419 * Clipping, scissors and viewport
420 */
421
422 static void si_set_clip_state(struct pipe_context *ctx,
423 const struct pipe_clip_state *state)
424 {
425 struct si_context *sctx = (struct si_context *)ctx;
426 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
427 struct pipe_constant_buffer cb;
428
429 if (pm4 == NULL)
430 return;
431
432 for (int i = 0; i < 6; i++) {
433 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
434 fui(state->ucp[i][0]));
435 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
436 fui(state->ucp[i][1]));
437 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
438 fui(state->ucp[i][2]));
439 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
440 fui(state->ucp[i][3]));
441 }
442
443 cb.buffer = NULL;
444 cb.user_buffer = state->ucp;
445 cb.buffer_offset = 0;
446 cb.buffer_size = 4*4*8;
447 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
448 pipe_resource_reference(&cb.buffer, NULL);
449
450 si_pm4_set_state(sctx, clip, pm4);
451 }
452
453 static void si_set_scissor_states(struct pipe_context *ctx,
454 unsigned start_slot,
455 unsigned num_scissors,
456 const struct pipe_scissor_state *state)
457 {
458 struct si_context *sctx = (struct si_context *)ctx;
459 struct si_state_scissor *scissor = CALLOC_STRUCT(si_state_scissor);
460 struct si_pm4_state *pm4 = &scissor->pm4;
461
462 if (scissor == NULL)
463 return;
464
465 scissor->scissor = *state;
466 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL,
467 S_028250_TL_X(state->minx) | S_028250_TL_Y(state->miny) |
468 S_028250_WINDOW_OFFSET_DISABLE(1));
469 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR,
470 S_028254_BR_X(state->maxx) | S_028254_BR_Y(state->maxy));
471
472 si_pm4_set_state(sctx, scissor, scissor);
473 }
474
475 static void si_set_viewport_states(struct pipe_context *ctx,
476 unsigned start_slot,
477 unsigned num_viewports,
478 const struct pipe_viewport_state *state)
479 {
480 struct si_context *sctx = (struct si_context *)ctx;
481 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
482 struct si_pm4_state *pm4 = &viewport->pm4;
483
484 if (viewport == NULL)
485 return;
486
487 viewport->viewport = *state;
488 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
489 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
490 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
491 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
492 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
493 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
494
495 si_pm4_set_state(sctx, viewport, viewport);
496 }
497
498 /*
499 * inferred state between framebuffer and rasterizer
500 */
501 static void si_update_fb_rs_state(struct si_context *sctx)
502 {
503 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
504 struct si_pm4_state *pm4;
505 float offset_units;
506
507 if (!rs || !sctx->framebuffer.state.zsbuf)
508 return;
509
510 offset_units = sctx->queued.named.rasterizer->offset_units;
511 switch (sctx->framebuffer.state.zsbuf->texture->format) {
512 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
513 case PIPE_FORMAT_X8Z24_UNORM:
514 case PIPE_FORMAT_Z24X8_UNORM:
515 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
516 offset_units *= 2.0f;
517 break;
518 case PIPE_FORMAT_Z32_FLOAT:
519 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
520 offset_units *= 1.0f;
521 break;
522 case PIPE_FORMAT_Z16_UNORM:
523 offset_units *= 4.0f;
524 break;
525 default:
526 return;
527 }
528
529 pm4 = CALLOC_STRUCT(si_pm4_state);
530
531 if (pm4 == NULL)
532 return;
533
534 /* FIXME some of those reg can be computed with cso */
535 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
536 fui(sctx->queued.named.rasterizer->offset_scale));
537 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
538 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
539 fui(sctx->queued.named.rasterizer->offset_scale));
540 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
541
542 si_pm4_set_state(sctx, fb_rs, pm4);
543 }
544
545 /*
546 * Rasterizer
547 */
548
549 static uint32_t si_translate_fill(uint32_t func)
550 {
551 switch(func) {
552 case PIPE_POLYGON_MODE_FILL:
553 return V_028814_X_DRAW_TRIANGLES;
554 case PIPE_POLYGON_MODE_LINE:
555 return V_028814_X_DRAW_LINES;
556 case PIPE_POLYGON_MODE_POINT:
557 return V_028814_X_DRAW_POINTS;
558 default:
559 assert(0);
560 return V_028814_X_DRAW_POINTS;
561 }
562 }
563
564 static void *si_create_rs_state(struct pipe_context *ctx,
565 const struct pipe_rasterizer_state *state)
566 {
567 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
568 struct si_pm4_state *pm4 = &rs->pm4;
569 unsigned tmp;
570 unsigned prov_vtx = 1, polygon_dual_mode;
571 float psize_min, psize_max;
572
573 if (rs == NULL) {
574 return NULL;
575 }
576
577 rs->two_side = state->light_twoside;
578 rs->multisample_enable = state->multisample;
579 rs->clip_plane_enable = state->clip_plane_enable;
580 rs->line_stipple_enable = state->line_stipple_enable;
581
582 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
583 state->fill_back != PIPE_POLYGON_MODE_FILL);
584
585 if (state->flatshade_first)
586 prov_vtx = 0;
587
588 rs->flatshade = state->flatshade;
589 rs->sprite_coord_enable = state->sprite_coord_enable;
590 rs->pa_sc_line_stipple = state->line_stipple_enable ?
591 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
592 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
593 rs->pa_su_sc_mode_cntl =
594 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
595 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
596 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
597 S_028814_FACE(!state->front_ccw) |
598 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
599 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
600 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
601 S_028814_POLY_MODE(polygon_dual_mode) |
602 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
603 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
604 rs->pa_cl_clip_cntl =
605 S_028810_PS_UCP_MODE(3) |
606 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
607 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
608 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
609 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
610 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
611
612 /* offset */
613 rs->offset_units = state->offset_units;
614 rs->offset_scale = state->offset_scale * 12.0f;
615
616 tmp = S_0286D4_FLAT_SHADE_ENA(1);
617 if (state->sprite_coord_enable) {
618 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
619 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
620 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
621 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
622 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
623 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
624 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
625 }
626 }
627 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
628
629 /* point size 12.4 fixed point */
630 tmp = (unsigned)(state->point_size * 8.0);
631 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
632
633 if (state->point_size_per_vertex) {
634 psize_min = util_get_min_point_size(state);
635 psize_max = 8192;
636 } else {
637 /* Force the point size to be as if the vertex output was disabled. */
638 psize_min = state->point_size;
639 psize_max = state->point_size;
640 }
641 /* Divide by two, because 0.5 = 1 pixel. */
642 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
643 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
644 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
645
646 tmp = (unsigned)state->line_width * 8;
647 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
648 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
649 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
650 S_028A48_MSAA_ENABLE(state->multisample) |
651 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
652
653 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
654 S_028BE4_PIX_CENTER(state->half_pixel_center) |
655 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
656
657 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
658
659 return rs;
660 }
661
662 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
663 {
664 struct si_context *sctx = (struct si_context *)ctx;
665 struct si_state_rasterizer *old_rs =
666 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
667 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
668
669 if (state == NULL)
670 return;
671
672 // TODO
673 sctx->sprite_coord_enable = rs->sprite_coord_enable;
674 sctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
675 sctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
676
677 if (sctx->framebuffer.nr_samples > 1 &&
678 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
679 sctx->db_render_state.dirty = true;
680
681 si_pm4_bind_state(sctx, rasterizer, rs);
682 si_update_fb_rs_state(sctx);
683 }
684
685 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
686 {
687 struct si_context *sctx = (struct si_context *)ctx;
688 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
689 }
690
691 /*
692 * infeered state between dsa and stencil ref
693 */
694 static void si_update_dsa_stencil_ref(struct si_context *sctx)
695 {
696 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
697 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
698 struct si_state_dsa *dsa = sctx->queued.named.dsa;
699
700 if (pm4 == NULL)
701 return;
702
703 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
704 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
705 S_028430_STENCILMASK(dsa->valuemask[0]) |
706 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
707 S_028430_STENCILOPVAL(1));
708 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
709 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
710 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
711 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
712 S_028434_STENCILOPVAL_BF(1));
713
714 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
715 }
716
717 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
718 const struct pipe_stencil_ref *state)
719 {
720 struct si_context *sctx = (struct si_context *)ctx;
721 sctx->stencil_ref = *state;
722 si_update_dsa_stencil_ref(sctx);
723 }
724
725
726 /*
727 * DSA
728 */
729
730 static uint32_t si_translate_stencil_op(int s_op)
731 {
732 switch (s_op) {
733 case PIPE_STENCIL_OP_KEEP:
734 return V_02842C_STENCIL_KEEP;
735 case PIPE_STENCIL_OP_ZERO:
736 return V_02842C_STENCIL_ZERO;
737 case PIPE_STENCIL_OP_REPLACE:
738 return V_02842C_STENCIL_REPLACE_TEST;
739 case PIPE_STENCIL_OP_INCR:
740 return V_02842C_STENCIL_ADD_CLAMP;
741 case PIPE_STENCIL_OP_DECR:
742 return V_02842C_STENCIL_SUB_CLAMP;
743 case PIPE_STENCIL_OP_INCR_WRAP:
744 return V_02842C_STENCIL_ADD_WRAP;
745 case PIPE_STENCIL_OP_DECR_WRAP:
746 return V_02842C_STENCIL_SUB_WRAP;
747 case PIPE_STENCIL_OP_INVERT:
748 return V_02842C_STENCIL_INVERT;
749 default:
750 R600_ERR("Unknown stencil op %d", s_op);
751 assert(0);
752 break;
753 }
754 return 0;
755 }
756
757 static void *si_create_dsa_state(struct pipe_context *ctx,
758 const struct pipe_depth_stencil_alpha_state *state)
759 {
760 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
761 struct si_pm4_state *pm4 = &dsa->pm4;
762 unsigned db_depth_control;
763 uint32_t db_stencil_control = 0;
764
765 if (dsa == NULL) {
766 return NULL;
767 }
768
769 dsa->valuemask[0] = state->stencil[0].valuemask;
770 dsa->valuemask[1] = state->stencil[1].valuemask;
771 dsa->writemask[0] = state->stencil[0].writemask;
772 dsa->writemask[1] = state->stencil[1].writemask;
773
774 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
775 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
776 S_028800_ZFUNC(state->depth.func);
777
778 /* stencil */
779 if (state->stencil[0].enabled) {
780 db_depth_control |= S_028800_STENCIL_ENABLE(1);
781 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
782 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
783 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
784 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
785
786 if (state->stencil[1].enabled) {
787 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
788 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
789 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
790 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
791 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
792 }
793 }
794
795 /* alpha */
796 if (state->alpha.enabled) {
797 dsa->alpha_func = state->alpha.func;
798 dsa->alpha_ref = state->alpha.ref_value;
799
800 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
801 SI_SGPR_ALPHA_REF * 4, fui(dsa->alpha_ref));
802 } else {
803 dsa->alpha_func = PIPE_FUNC_ALWAYS;
804 }
805
806 /* misc */
807 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
808 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
809
810 return dsa;
811 }
812
813 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
814 {
815 struct si_context *sctx = (struct si_context *)ctx;
816 struct si_state_dsa *dsa = state;
817
818 if (state == NULL)
819 return;
820
821 si_pm4_bind_state(sctx, dsa, dsa);
822 si_update_dsa_stencil_ref(sctx);
823 }
824
825 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
826 {
827 struct si_context *sctx = (struct si_context *)ctx;
828 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
829 }
830
831 static void *si_create_db_flush_dsa(struct si_context *sctx)
832 {
833 struct pipe_depth_stencil_alpha_state dsa = {};
834
835 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
836 }
837
838 /* DB RENDER STATE */
839
840 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
841 {
842 struct si_context *sctx = (struct si_context*)ctx;
843
844 sctx->db_render_state.dirty = true;
845 }
846
847 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
848 {
849 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
850 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
851 unsigned db_shader_control;
852
853 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
854
855 /* DB_RENDER_CONTROL */
856 if (sctx->dbcb_depth_copy_enabled ||
857 sctx->dbcb_stencil_copy_enabled) {
858 radeon_emit(cs,
859 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
860 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
861 S_028000_COPY_CENTROID(1) |
862 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
863 } else if (sctx->db_inplace_flush_enabled) {
864 radeon_emit(cs,
865 S_028000_DEPTH_COMPRESS_DISABLE(1) |
866 S_028000_STENCIL_COMPRESS_DISABLE(1));
867 } else if (sctx->db_depth_clear) {
868 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
869 } else {
870 radeon_emit(cs, 0);
871 }
872
873 /* DB_COUNT_CONTROL (occlusion queries) */
874 if (sctx->b.num_occlusion_queries > 0) {
875 if (sctx->b.chip_class >= CIK) {
876 radeon_emit(cs,
877 S_028004_PERFECT_ZPASS_COUNTS(1) |
878 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
879 S_028004_ZPASS_ENABLE(1) |
880 S_028004_SLICE_EVEN_ENABLE(1) |
881 S_028004_SLICE_ODD_ENABLE(1));
882 } else {
883 radeon_emit(cs,
884 S_028004_PERFECT_ZPASS_COUNTS(1) |
885 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
886 }
887 } else {
888 /* Disable occlusion queries. */
889 if (sctx->b.chip_class >= CIK) {
890 radeon_emit(cs, 0);
891 } else {
892 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
893 }
894 }
895
896 /* DB_RENDER_OVERRIDE2 */
897 if (sctx->db_depth_disable_expclear) {
898 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
899 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
900 } else {
901 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
902 }
903
904 db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
905 S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
906 sctx->ps_db_shader_control;
907
908 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
909 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
910 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
911
912 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
913 db_shader_control);
914 }
915
916 /*
917 * format translation
918 */
919 static uint32_t si_translate_colorformat(enum pipe_format format)
920 {
921 const struct util_format_description *desc = util_format_description(format);
922
923 #define HAS_SIZE(x,y,z,w) \
924 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
925 desc->channel[2].size == (z) && desc->channel[3].size == (w))
926
927 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
928 return V_028C70_COLOR_10_11_11;
929
930 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
931 return V_028C70_COLOR_INVALID;
932
933 switch (desc->nr_channels) {
934 case 1:
935 switch (desc->channel[0].size) {
936 case 8:
937 return V_028C70_COLOR_8;
938 case 16:
939 return V_028C70_COLOR_16;
940 case 32:
941 return V_028C70_COLOR_32;
942 }
943 break;
944 case 2:
945 if (desc->channel[0].size == desc->channel[1].size) {
946 switch (desc->channel[0].size) {
947 case 8:
948 return V_028C70_COLOR_8_8;
949 case 16:
950 return V_028C70_COLOR_16_16;
951 case 32:
952 return V_028C70_COLOR_32_32;
953 }
954 } else if (HAS_SIZE(8,24,0,0)) {
955 return V_028C70_COLOR_24_8;
956 } else if (HAS_SIZE(24,8,0,0)) {
957 return V_028C70_COLOR_8_24;
958 }
959 break;
960 case 3:
961 if (HAS_SIZE(5,6,5,0)) {
962 return V_028C70_COLOR_5_6_5;
963 } else if (HAS_SIZE(32,8,24,0)) {
964 return V_028C70_COLOR_X24_8_32_FLOAT;
965 }
966 break;
967 case 4:
968 if (desc->channel[0].size == desc->channel[1].size &&
969 desc->channel[0].size == desc->channel[2].size &&
970 desc->channel[0].size == desc->channel[3].size) {
971 switch (desc->channel[0].size) {
972 case 4:
973 return V_028C70_COLOR_4_4_4_4;
974 case 8:
975 return V_028C70_COLOR_8_8_8_8;
976 case 16:
977 return V_028C70_COLOR_16_16_16_16;
978 case 32:
979 return V_028C70_COLOR_32_32_32_32;
980 }
981 } else if (HAS_SIZE(5,5,5,1)) {
982 return V_028C70_COLOR_1_5_5_5;
983 } else if (HAS_SIZE(10,10,10,2)) {
984 return V_028C70_COLOR_2_10_10_10;
985 }
986 break;
987 }
988 return V_028C70_COLOR_INVALID;
989 }
990
991 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
992 {
993 if (SI_BIG_ENDIAN) {
994 switch(colorformat) {
995 /* 8-bit buffers. */
996 case V_028C70_COLOR_8:
997 return V_028C70_ENDIAN_NONE;
998
999 /* 16-bit buffers. */
1000 case V_028C70_COLOR_5_6_5:
1001 case V_028C70_COLOR_1_5_5_5:
1002 case V_028C70_COLOR_4_4_4_4:
1003 case V_028C70_COLOR_16:
1004 case V_028C70_COLOR_8_8:
1005 return V_028C70_ENDIAN_8IN16;
1006
1007 /* 32-bit buffers. */
1008 case V_028C70_COLOR_8_8_8_8:
1009 case V_028C70_COLOR_2_10_10_10:
1010 case V_028C70_COLOR_8_24:
1011 case V_028C70_COLOR_24_8:
1012 case V_028C70_COLOR_16_16:
1013 return V_028C70_ENDIAN_8IN32;
1014
1015 /* 64-bit buffers. */
1016 case V_028C70_COLOR_16_16_16_16:
1017 return V_028C70_ENDIAN_8IN16;
1018
1019 case V_028C70_COLOR_32_32:
1020 return V_028C70_ENDIAN_8IN32;
1021
1022 /* 128-bit buffers. */
1023 case V_028C70_COLOR_32_32_32_32:
1024 return V_028C70_ENDIAN_8IN32;
1025 default:
1026 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1027 }
1028 } else {
1029 return V_028C70_ENDIAN_NONE;
1030 }
1031 }
1032
1033 /* Returns the size in bits of the widest component of a CB format */
1034 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1035 {
1036 switch(colorformat) {
1037 case V_028C70_COLOR_4_4_4_4:
1038 return 4;
1039
1040 case V_028C70_COLOR_1_5_5_5:
1041 case V_028C70_COLOR_5_5_5_1:
1042 return 5;
1043
1044 case V_028C70_COLOR_5_6_5:
1045 return 6;
1046
1047 case V_028C70_COLOR_8:
1048 case V_028C70_COLOR_8_8:
1049 case V_028C70_COLOR_8_8_8_8:
1050 return 8;
1051
1052 case V_028C70_COLOR_10_10_10_2:
1053 case V_028C70_COLOR_2_10_10_10:
1054 return 10;
1055
1056 case V_028C70_COLOR_10_11_11:
1057 case V_028C70_COLOR_11_11_10:
1058 return 11;
1059
1060 case V_028C70_COLOR_16:
1061 case V_028C70_COLOR_16_16:
1062 case V_028C70_COLOR_16_16_16_16:
1063 return 16;
1064
1065 case V_028C70_COLOR_8_24:
1066 case V_028C70_COLOR_24_8:
1067 return 24;
1068
1069 case V_028C70_COLOR_32:
1070 case V_028C70_COLOR_32_32:
1071 case V_028C70_COLOR_32_32_32_32:
1072 case V_028C70_COLOR_X24_8_32_FLOAT:
1073 return 32;
1074 }
1075
1076 assert(!"Unknown maximum component size");
1077 return 0;
1078 }
1079
1080 static uint32_t si_translate_dbformat(enum pipe_format format)
1081 {
1082 switch (format) {
1083 case PIPE_FORMAT_Z16_UNORM:
1084 return V_028040_Z_16;
1085 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1086 case PIPE_FORMAT_X8Z24_UNORM:
1087 case PIPE_FORMAT_Z24X8_UNORM:
1088 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1089 return V_028040_Z_24; /* deprecated on SI */
1090 case PIPE_FORMAT_Z32_FLOAT:
1091 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1092 return V_028040_Z_32_FLOAT;
1093 default:
1094 return V_028040_Z_INVALID;
1095 }
1096 }
1097
1098 /*
1099 * Texture translation
1100 */
1101
1102 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1103 enum pipe_format format,
1104 const struct util_format_description *desc,
1105 int first_non_void)
1106 {
1107 struct si_screen *sscreen = (struct si_screen*)screen;
1108 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1109 boolean uniform = TRUE;
1110 int i;
1111
1112 /* Colorspace (return non-RGB formats directly). */
1113 switch (desc->colorspace) {
1114 /* Depth stencil formats */
1115 case UTIL_FORMAT_COLORSPACE_ZS:
1116 switch (format) {
1117 case PIPE_FORMAT_Z16_UNORM:
1118 return V_008F14_IMG_DATA_FORMAT_16;
1119 case PIPE_FORMAT_X24S8_UINT:
1120 case PIPE_FORMAT_Z24X8_UNORM:
1121 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1122 return V_008F14_IMG_DATA_FORMAT_8_24;
1123 case PIPE_FORMAT_X8Z24_UNORM:
1124 case PIPE_FORMAT_S8X24_UINT:
1125 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1126 return V_008F14_IMG_DATA_FORMAT_24_8;
1127 case PIPE_FORMAT_S8_UINT:
1128 return V_008F14_IMG_DATA_FORMAT_8;
1129 case PIPE_FORMAT_Z32_FLOAT:
1130 return V_008F14_IMG_DATA_FORMAT_32;
1131 case PIPE_FORMAT_X32_S8X24_UINT:
1132 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1133 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1134 default:
1135 goto out_unknown;
1136 }
1137
1138 case UTIL_FORMAT_COLORSPACE_YUV:
1139 goto out_unknown; /* TODO */
1140
1141 case UTIL_FORMAT_COLORSPACE_SRGB:
1142 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1143 goto out_unknown;
1144 break;
1145
1146 default:
1147 break;
1148 }
1149
1150 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1151 if (!enable_s3tc)
1152 goto out_unknown;
1153
1154 switch (format) {
1155 case PIPE_FORMAT_RGTC1_SNORM:
1156 case PIPE_FORMAT_LATC1_SNORM:
1157 case PIPE_FORMAT_RGTC1_UNORM:
1158 case PIPE_FORMAT_LATC1_UNORM:
1159 return V_008F14_IMG_DATA_FORMAT_BC4;
1160 case PIPE_FORMAT_RGTC2_SNORM:
1161 case PIPE_FORMAT_LATC2_SNORM:
1162 case PIPE_FORMAT_RGTC2_UNORM:
1163 case PIPE_FORMAT_LATC2_UNORM:
1164 return V_008F14_IMG_DATA_FORMAT_BC5;
1165 default:
1166 goto out_unknown;
1167 }
1168 }
1169
1170 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1171 if (!enable_s3tc)
1172 goto out_unknown;
1173
1174 switch (format) {
1175 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1176 case PIPE_FORMAT_BPTC_SRGBA:
1177 return V_008F14_IMG_DATA_FORMAT_BC7;
1178 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1179 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1180 return V_008F14_IMG_DATA_FORMAT_BC6;
1181 default:
1182 goto out_unknown;
1183 }
1184 }
1185
1186 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1187 switch (format) {
1188 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1189 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1190 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1191 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1192 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1193 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1194 default:
1195 goto out_unknown;
1196 }
1197 }
1198
1199 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1200
1201 if (!enable_s3tc)
1202 goto out_unknown;
1203
1204 if (!util_format_s3tc_enabled) {
1205 goto out_unknown;
1206 }
1207
1208 switch (format) {
1209 case PIPE_FORMAT_DXT1_RGB:
1210 case PIPE_FORMAT_DXT1_RGBA:
1211 case PIPE_FORMAT_DXT1_SRGB:
1212 case PIPE_FORMAT_DXT1_SRGBA:
1213 return V_008F14_IMG_DATA_FORMAT_BC1;
1214 case PIPE_FORMAT_DXT3_RGBA:
1215 case PIPE_FORMAT_DXT3_SRGBA:
1216 return V_008F14_IMG_DATA_FORMAT_BC2;
1217 case PIPE_FORMAT_DXT5_RGBA:
1218 case PIPE_FORMAT_DXT5_SRGBA:
1219 return V_008F14_IMG_DATA_FORMAT_BC3;
1220 default:
1221 goto out_unknown;
1222 }
1223 }
1224
1225 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1226 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1227 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1228 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1229 }
1230
1231 /* R8G8Bx_SNORM - TODO CxV8U8 */
1232
1233 /* See whether the components are of the same size. */
1234 for (i = 1; i < desc->nr_channels; i++) {
1235 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1236 }
1237
1238 /* Non-uniform formats. */
1239 if (!uniform) {
1240 switch(desc->nr_channels) {
1241 case 3:
1242 if (desc->channel[0].size == 5 &&
1243 desc->channel[1].size == 6 &&
1244 desc->channel[2].size == 5) {
1245 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1246 }
1247 goto out_unknown;
1248 case 4:
1249 if (desc->channel[0].size == 5 &&
1250 desc->channel[1].size == 5 &&
1251 desc->channel[2].size == 5 &&
1252 desc->channel[3].size == 1) {
1253 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1254 }
1255 if (desc->channel[0].size == 10 &&
1256 desc->channel[1].size == 10 &&
1257 desc->channel[2].size == 10 &&
1258 desc->channel[3].size == 2) {
1259 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1260 }
1261 goto out_unknown;
1262 }
1263 goto out_unknown;
1264 }
1265
1266 if (first_non_void < 0 || first_non_void > 3)
1267 goto out_unknown;
1268
1269 /* uniform formats */
1270 switch (desc->channel[first_non_void].size) {
1271 case 4:
1272 switch (desc->nr_channels) {
1273 #if 0 /* Not supported for render targets */
1274 case 2:
1275 return V_008F14_IMG_DATA_FORMAT_4_4;
1276 #endif
1277 case 4:
1278 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1279 }
1280 break;
1281 case 8:
1282 switch (desc->nr_channels) {
1283 case 1:
1284 return V_008F14_IMG_DATA_FORMAT_8;
1285 case 2:
1286 return V_008F14_IMG_DATA_FORMAT_8_8;
1287 case 4:
1288 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1289 }
1290 break;
1291 case 16:
1292 switch (desc->nr_channels) {
1293 case 1:
1294 return V_008F14_IMG_DATA_FORMAT_16;
1295 case 2:
1296 return V_008F14_IMG_DATA_FORMAT_16_16;
1297 case 4:
1298 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1299 }
1300 break;
1301 case 32:
1302 switch (desc->nr_channels) {
1303 case 1:
1304 return V_008F14_IMG_DATA_FORMAT_32;
1305 case 2:
1306 return V_008F14_IMG_DATA_FORMAT_32_32;
1307 #if 0 /* Not supported for render targets */
1308 case 3:
1309 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1310 #endif
1311 case 4:
1312 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1313 }
1314 }
1315
1316 out_unknown:
1317 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1318 return ~0;
1319 }
1320
1321 static unsigned si_tex_wrap(unsigned wrap)
1322 {
1323 switch (wrap) {
1324 default:
1325 case PIPE_TEX_WRAP_REPEAT:
1326 return V_008F30_SQ_TEX_WRAP;
1327 case PIPE_TEX_WRAP_CLAMP:
1328 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1329 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1330 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1331 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1332 return V_008F30_SQ_TEX_CLAMP_BORDER;
1333 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1334 return V_008F30_SQ_TEX_MIRROR;
1335 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1336 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1337 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1338 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1339 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1340 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1341 }
1342 }
1343
1344 static unsigned si_tex_filter(unsigned filter)
1345 {
1346 switch (filter) {
1347 default:
1348 case PIPE_TEX_FILTER_NEAREST:
1349 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1350 case PIPE_TEX_FILTER_LINEAR:
1351 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1352 }
1353 }
1354
1355 static unsigned si_tex_mipfilter(unsigned filter)
1356 {
1357 switch (filter) {
1358 case PIPE_TEX_MIPFILTER_NEAREST:
1359 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1360 case PIPE_TEX_MIPFILTER_LINEAR:
1361 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1362 default:
1363 case PIPE_TEX_MIPFILTER_NONE:
1364 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1365 }
1366 }
1367
1368 static unsigned si_tex_compare(unsigned compare)
1369 {
1370 switch (compare) {
1371 default:
1372 case PIPE_FUNC_NEVER:
1373 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1374 case PIPE_FUNC_LESS:
1375 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1376 case PIPE_FUNC_EQUAL:
1377 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1378 case PIPE_FUNC_LEQUAL:
1379 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1380 case PIPE_FUNC_GREATER:
1381 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1382 case PIPE_FUNC_NOTEQUAL:
1383 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1384 case PIPE_FUNC_GEQUAL:
1385 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1386 case PIPE_FUNC_ALWAYS:
1387 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1388 }
1389 }
1390
1391 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1392 {
1393 switch (dim) {
1394 default:
1395 case PIPE_TEXTURE_1D:
1396 return V_008F1C_SQ_RSRC_IMG_1D;
1397 case PIPE_TEXTURE_1D_ARRAY:
1398 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1399 case PIPE_TEXTURE_2D:
1400 case PIPE_TEXTURE_RECT:
1401 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1402 V_008F1C_SQ_RSRC_IMG_2D;
1403 case PIPE_TEXTURE_2D_ARRAY:
1404 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1405 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1406 case PIPE_TEXTURE_3D:
1407 return V_008F1C_SQ_RSRC_IMG_3D;
1408 case PIPE_TEXTURE_CUBE:
1409 case PIPE_TEXTURE_CUBE_ARRAY:
1410 return V_008F1C_SQ_RSRC_IMG_CUBE;
1411 }
1412 }
1413
1414 /*
1415 * Format support testing
1416 */
1417
1418 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1419 {
1420 return si_translate_texformat(screen, format, util_format_description(format),
1421 util_format_get_first_non_void_channel(format)) != ~0U;
1422 }
1423
1424 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1425 const struct util_format_description *desc,
1426 int first_non_void)
1427 {
1428 unsigned type = desc->channel[first_non_void].type;
1429 int i;
1430
1431 if (type == UTIL_FORMAT_TYPE_FIXED)
1432 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1433
1434 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1435 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1436
1437 if (desc->nr_channels == 4 &&
1438 desc->channel[0].size == 10 &&
1439 desc->channel[1].size == 10 &&
1440 desc->channel[2].size == 10 &&
1441 desc->channel[3].size == 2)
1442 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1443
1444 /* See whether the components are of the same size. */
1445 for (i = 0; i < desc->nr_channels; i++) {
1446 if (desc->channel[first_non_void].size != desc->channel[i].size)
1447 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1448 }
1449
1450 switch (desc->channel[first_non_void].size) {
1451 case 8:
1452 switch (desc->nr_channels) {
1453 case 1:
1454 return V_008F0C_BUF_DATA_FORMAT_8;
1455 case 2:
1456 return V_008F0C_BUF_DATA_FORMAT_8_8;
1457 case 3:
1458 case 4:
1459 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1460 }
1461 break;
1462 case 16:
1463 switch (desc->nr_channels) {
1464 case 1:
1465 return V_008F0C_BUF_DATA_FORMAT_16;
1466 case 2:
1467 return V_008F0C_BUF_DATA_FORMAT_16_16;
1468 case 3:
1469 case 4:
1470 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1471 }
1472 break;
1473 case 32:
1474 /* From the Southern Islands ISA documentation about MTBUF:
1475 * 'Memory reads of data in memory that is 32 or 64 bits do not
1476 * undergo any format conversion.'
1477 */
1478 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1479 !desc->channel[first_non_void].pure_integer)
1480 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1481
1482 switch (desc->nr_channels) {
1483 case 1:
1484 return V_008F0C_BUF_DATA_FORMAT_32;
1485 case 2:
1486 return V_008F0C_BUF_DATA_FORMAT_32_32;
1487 case 3:
1488 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1489 case 4:
1490 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1491 }
1492 break;
1493 }
1494
1495 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1496 }
1497
1498 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1499 const struct util_format_description *desc,
1500 int first_non_void)
1501 {
1502 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1503 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1504
1505 switch (desc->channel[first_non_void].type) {
1506 case UTIL_FORMAT_TYPE_SIGNED:
1507 if (desc->channel[first_non_void].normalized)
1508 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1509 else if (desc->channel[first_non_void].pure_integer)
1510 return V_008F0C_BUF_NUM_FORMAT_SINT;
1511 else
1512 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1513 break;
1514 case UTIL_FORMAT_TYPE_UNSIGNED:
1515 if (desc->channel[first_non_void].normalized)
1516 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1517 else if (desc->channel[first_non_void].pure_integer)
1518 return V_008F0C_BUF_NUM_FORMAT_UINT;
1519 else
1520 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1521 break;
1522 case UTIL_FORMAT_TYPE_FLOAT:
1523 default:
1524 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1525 }
1526 }
1527
1528 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1529 {
1530 const struct util_format_description *desc;
1531 int first_non_void;
1532 unsigned data_format;
1533
1534 desc = util_format_description(format);
1535 first_non_void = util_format_get_first_non_void_channel(format);
1536 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1537 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1538 }
1539
1540 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1541 {
1542 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1543 r600_translate_colorswap(format) != ~0U;
1544 }
1545
1546 static bool si_is_zs_format_supported(enum pipe_format format)
1547 {
1548 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1549 }
1550
1551 boolean si_is_format_supported(struct pipe_screen *screen,
1552 enum pipe_format format,
1553 enum pipe_texture_target target,
1554 unsigned sample_count,
1555 unsigned usage)
1556 {
1557 struct si_screen *sscreen = (struct si_screen *)screen;
1558 unsigned retval = 0;
1559
1560 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1561 R600_ERR("r600: unsupported texture type %d\n", target);
1562 return FALSE;
1563 }
1564
1565 if (!util_format_is_supported(format, usage))
1566 return FALSE;
1567
1568 if (sample_count > 1) {
1569 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1570 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1571 return FALSE;
1572
1573 switch (sample_count) {
1574 case 2:
1575 case 4:
1576 case 8:
1577 break;
1578 default:
1579 return FALSE;
1580 }
1581 }
1582
1583 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1584 if (target == PIPE_BUFFER) {
1585 if (si_is_vertex_format_supported(screen, format))
1586 retval |= PIPE_BIND_SAMPLER_VIEW;
1587 } else {
1588 if (si_is_sampler_format_supported(screen, format))
1589 retval |= PIPE_BIND_SAMPLER_VIEW;
1590 }
1591 }
1592
1593 if ((usage & (PIPE_BIND_RENDER_TARGET |
1594 PIPE_BIND_DISPLAY_TARGET |
1595 PIPE_BIND_SCANOUT |
1596 PIPE_BIND_SHARED |
1597 PIPE_BIND_BLENDABLE)) &&
1598 si_is_colorbuffer_format_supported(format)) {
1599 retval |= usage &
1600 (PIPE_BIND_RENDER_TARGET |
1601 PIPE_BIND_DISPLAY_TARGET |
1602 PIPE_BIND_SCANOUT |
1603 PIPE_BIND_SHARED);
1604 if (!util_format_is_pure_integer(format) &&
1605 !util_format_is_depth_or_stencil(format))
1606 retval |= usage & PIPE_BIND_BLENDABLE;
1607 }
1608
1609 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1610 si_is_zs_format_supported(format)) {
1611 retval |= PIPE_BIND_DEPTH_STENCIL;
1612 }
1613
1614 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1615 si_is_vertex_format_supported(screen, format)) {
1616 retval |= PIPE_BIND_VERTEX_BUFFER;
1617 }
1618
1619 if (usage & PIPE_BIND_TRANSFER_READ)
1620 retval |= PIPE_BIND_TRANSFER_READ;
1621 if (usage & PIPE_BIND_TRANSFER_WRITE)
1622 retval |= PIPE_BIND_TRANSFER_WRITE;
1623
1624 return retval == usage;
1625 }
1626
1627 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1628 {
1629 unsigned tile_mode_index = 0;
1630
1631 if (stencil) {
1632 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1633 } else {
1634 tile_mode_index = rtex->surface.tiling_index[level];
1635 }
1636 return tile_mode_index;
1637 }
1638
1639 /*
1640 * framebuffer handling
1641 */
1642
1643 static void si_initialize_color_surface(struct si_context *sctx,
1644 struct r600_surface *surf)
1645 {
1646 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1647 unsigned level = surf->base.u.tex.level;
1648 uint64_t offset = rtex->surface.level[level].offset;
1649 unsigned pitch, slice;
1650 unsigned color_info, color_attrib, color_pitch, color_view;
1651 unsigned tile_mode_index;
1652 unsigned format, swap, ntype, endian;
1653 const struct util_format_description *desc;
1654 int i;
1655 unsigned blend_clamp = 0, blend_bypass = 0;
1656 unsigned max_comp_size;
1657
1658 /* Layered rendering doesn't work with LINEAR_GENERAL.
1659 * (LINEAR_ALIGNED and others work) */
1660 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1661 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1662 offset += rtex->surface.level[level].slice_size *
1663 surf->base.u.tex.first_layer;
1664 color_view = 0;
1665 } else {
1666 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1667 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1668 }
1669
1670 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1671 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1672 if (slice) {
1673 slice = slice - 1;
1674 }
1675
1676 tile_mode_index = si_tile_mode_index(rtex, level, false);
1677
1678 desc = util_format_description(surf->base.format);
1679 for (i = 0; i < 4; i++) {
1680 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1681 break;
1682 }
1683 }
1684 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1685 ntype = V_028C70_NUMBER_FLOAT;
1686 } else {
1687 ntype = V_028C70_NUMBER_UNORM;
1688 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1689 ntype = V_028C70_NUMBER_SRGB;
1690 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1691 if (desc->channel[i].pure_integer) {
1692 ntype = V_028C70_NUMBER_SINT;
1693 } else {
1694 assert(desc->channel[i].normalized);
1695 ntype = V_028C70_NUMBER_SNORM;
1696 }
1697 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1698 if (desc->channel[i].pure_integer) {
1699 ntype = V_028C70_NUMBER_UINT;
1700 } else {
1701 assert(desc->channel[i].normalized);
1702 ntype = V_028C70_NUMBER_UNORM;
1703 }
1704 }
1705 }
1706
1707 format = si_translate_colorformat(surf->base.format);
1708 if (format == V_028C70_COLOR_INVALID) {
1709 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1710 }
1711 assert(format != V_028C70_COLOR_INVALID);
1712 swap = r600_translate_colorswap(surf->base.format);
1713 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1714 endian = V_028C70_ENDIAN_NONE;
1715 } else {
1716 endian = si_colorformat_endian_swap(format);
1717 }
1718
1719 /* blend clamp should be set for all NORM/SRGB types */
1720 if (ntype == V_028C70_NUMBER_UNORM ||
1721 ntype == V_028C70_NUMBER_SNORM ||
1722 ntype == V_028C70_NUMBER_SRGB)
1723 blend_clamp = 1;
1724
1725 /* set blend bypass according to docs if SINT/UINT or
1726 8/24 COLOR variants */
1727 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1728 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1729 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1730 blend_clamp = 0;
1731 blend_bypass = 1;
1732 }
1733
1734 color_info = S_028C70_FORMAT(format) |
1735 S_028C70_COMP_SWAP(swap) |
1736 S_028C70_BLEND_CLAMP(blend_clamp) |
1737 S_028C70_BLEND_BYPASS(blend_bypass) |
1738 S_028C70_NUMBER_TYPE(ntype) |
1739 S_028C70_ENDIAN(endian);
1740
1741 color_pitch = S_028C64_TILE_MAX(pitch);
1742
1743 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1744 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1745
1746 if (rtex->resource.b.b.nr_samples > 1) {
1747 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1748
1749 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1750 S_028C74_NUM_FRAGMENTS(log_samples);
1751
1752 if (rtex->fmask.size) {
1753 color_info |= S_028C70_COMPRESSION(1);
1754 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1755
1756 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1757
1758 if (sctx->b.chip_class == SI) {
1759 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1760 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1761 }
1762 if (sctx->b.chip_class >= CIK) {
1763 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1764 }
1765 }
1766 }
1767
1768 offset += rtex->resource.gpu_address;
1769
1770 surf->cb_color_base = offset >> 8;
1771 surf->cb_color_pitch = color_pitch;
1772 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1773 surf->cb_color_view = color_view;
1774 surf->cb_color_info = color_info;
1775 surf->cb_color_attrib = color_attrib;
1776
1777 if (rtex->fmask.size) {
1778 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1779 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1780 } else {
1781 /* This must be set for fast clear to work without FMASK. */
1782 surf->cb_color_fmask = surf->cb_color_base;
1783 surf->cb_color_fmask_slice = surf->cb_color_slice;
1784 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1785
1786 if (sctx->b.chip_class == SI) {
1787 unsigned bankh = util_logbase2(rtex->surface.bankh);
1788 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1789 }
1790
1791 if (sctx->b.chip_class >= CIK) {
1792 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1793 }
1794 }
1795
1796 /* Determine pixel shader export format */
1797 max_comp_size = si_colorformat_max_comp_size(format);
1798 if (ntype == V_028C70_NUMBER_SRGB ||
1799 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1800 max_comp_size <= 10) ||
1801 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1802 surf->export_16bpc = true;
1803 }
1804
1805 surf->color_initialized = true;
1806 }
1807
1808 static void si_init_depth_surface(struct si_context *sctx,
1809 struct r600_surface *surf)
1810 {
1811 struct si_screen *sscreen = sctx->screen;
1812 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1813 unsigned level = surf->base.u.tex.level;
1814 struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
1815 unsigned format, tile_mode_index, array_mode;
1816 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1817 uint32_t z_info, s_info, db_depth_info;
1818 uint64_t z_offs, s_offs;
1819 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1820
1821 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1822 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1823 case PIPE_FORMAT_X8Z24_UNORM:
1824 case PIPE_FORMAT_Z24X8_UNORM:
1825 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1826 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1827 break;
1828 case PIPE_FORMAT_Z32_FLOAT:
1829 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1830 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1831 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1832 break;
1833 case PIPE_FORMAT_Z16_UNORM:
1834 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1835 break;
1836 default:
1837 assert(0);
1838 }
1839
1840 format = si_translate_dbformat(rtex->resource.b.b.format);
1841
1842 if (format == V_028040_Z_INVALID) {
1843 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1844 }
1845 assert(format != V_028040_Z_INVALID);
1846
1847 s_offs = z_offs = rtex->resource.gpu_address;
1848 z_offs += rtex->surface.level[level].offset;
1849 s_offs += rtex->surface.stencil_level[level].offset;
1850
1851 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1852
1853 z_info = S_028040_FORMAT(format);
1854 if (rtex->resource.b.b.nr_samples > 1) {
1855 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1856 }
1857
1858 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1859 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1860 else
1861 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1862
1863 if (sctx->b.chip_class >= CIK) {
1864 switch (rtex->surface.level[level].mode) {
1865 case RADEON_SURF_MODE_2D:
1866 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1867 break;
1868 case RADEON_SURF_MODE_1D:
1869 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1870 case RADEON_SURF_MODE_LINEAR:
1871 default:
1872 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1873 break;
1874 }
1875 tile_split = rtex->surface.tile_split;
1876 stile_split = rtex->surface.stencil_tile_split;
1877 macro_aspect = rtex->surface.mtilea;
1878 bankw = rtex->surface.bankw;
1879 bankh = rtex->surface.bankh;
1880 tile_split = cik_tile_split(tile_split);
1881 stile_split = cik_tile_split(stile_split);
1882 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1883 bankw = cik_bank_wh(bankw);
1884 bankh = cik_bank_wh(bankh);
1885 nbanks = si_num_banks(sscreen, rtex);
1886 tile_mode_index = si_tile_mode_index(rtex, level, false);
1887 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1888
1889 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1890 S_02803C_PIPE_CONFIG(pipe_config) |
1891 S_02803C_BANK_WIDTH(bankw) |
1892 S_02803C_BANK_HEIGHT(bankh) |
1893 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1894 S_02803C_NUM_BANKS(nbanks);
1895 z_info |= S_028040_TILE_SPLIT(tile_split);
1896 s_info |= S_028044_TILE_SPLIT(stile_split);
1897 } else {
1898 tile_mode_index = si_tile_mode_index(rtex, level, false);
1899 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1900 tile_mode_index = si_tile_mode_index(rtex, level, true);
1901 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1902 }
1903
1904 /* HiZ aka depth buffer htile */
1905 /* use htile only for first level */
1906 if (rtex->htile_buffer && !level) {
1907 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1908 S_028040_ALLOW_EXPCLEAR(1);
1909
1910 /* This is optimal for the clear value of 1.0 and using
1911 * the LESS and LEQUAL test functions. Set this to 0
1912 * for the opposite case. This can only be changed when
1913 * clearing. */
1914 z_info |= S_028040_ZRANGE_PRECISION(1);
1915
1916 /* Use all of the htile_buffer for depth, because we don't
1917 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1918 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1919
1920 uint64_t va = rtex->htile_buffer->gpu_address;
1921 db_htile_data_base = va >> 8;
1922 db_htile_surface = S_028ABC_FULL_CACHE(1);
1923 } else {
1924 db_htile_data_base = 0;
1925 db_htile_surface = 0;
1926 }
1927
1928 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1929
1930 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1931 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1932 surf->db_htile_data_base = db_htile_data_base;
1933 surf->db_depth_info = db_depth_info;
1934 surf->db_z_info = z_info;
1935 surf->db_stencil_info = s_info;
1936 surf->db_depth_base = z_offs >> 8;
1937 surf->db_stencil_base = s_offs >> 8;
1938 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
1939 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
1940 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
1941 levelinfo->nblk_y) / 64 - 1);
1942 surf->db_htile_surface = db_htile_surface;
1943 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
1944
1945 surf->depth_initialized = true;
1946 }
1947
1948 static void si_set_framebuffer_state(struct pipe_context *ctx,
1949 const struct pipe_framebuffer_state *state)
1950 {
1951 struct si_context *sctx = (struct si_context *)ctx;
1952 struct pipe_constant_buffer constbuf = {0};
1953 struct r600_surface *surf = NULL;
1954 struct r600_texture *rtex;
1955 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
1956 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
1957 int i;
1958
1959 if (sctx->framebuffer.state.nr_cbufs) {
1960 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_CB |
1961 R600_CONTEXT_FLUSH_AND_INV_CB_META;
1962 }
1963 if (sctx->framebuffer.state.zsbuf) {
1964 sctx->b.flags |= R600_CONTEXT_FLUSH_AND_INV_DB |
1965 R600_CONTEXT_FLUSH_AND_INV_DB_META;
1966 }
1967
1968 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
1969
1970 sctx->framebuffer.export_16bpc = 0;
1971 sctx->framebuffer.compressed_cb_mask = 0;
1972 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
1973 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
1974 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
1975 util_format_is_pure_integer(state->cbufs[0]->format);
1976
1977 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
1978 sctx->db_render_state.dirty = true;
1979
1980 for (i = 0; i < state->nr_cbufs; i++) {
1981 if (!state->cbufs[i])
1982 continue;
1983
1984 surf = (struct r600_surface*)state->cbufs[i];
1985 rtex = (struct r600_texture*)surf->base.texture;
1986
1987 if (!surf->color_initialized) {
1988 si_initialize_color_surface(sctx, surf);
1989 }
1990
1991 if (surf->export_16bpc) {
1992 sctx->framebuffer.export_16bpc |= 1 << i;
1993 }
1994
1995 if (rtex->fmask.size && rtex->cmask.size) {
1996 sctx->framebuffer.compressed_cb_mask |= 1 << i;
1997 }
1998 }
1999 /* Set the 16BPC export for possible dual-src blending. */
2000 if (i == 1 && surf && surf->export_16bpc) {
2001 sctx->framebuffer.export_16bpc |= 1 << 1;
2002 }
2003
2004 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2005
2006 if (state->zsbuf) {
2007 surf = (struct r600_surface*)state->zsbuf;
2008
2009 if (!surf->depth_initialized) {
2010 si_init_depth_surface(sctx, surf);
2011 }
2012 }
2013
2014 si_update_fb_rs_state(sctx);
2015 si_update_fb_blend_state(sctx);
2016
2017 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2018 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2019 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2020 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2021 sctx->framebuffer.atom.dirty = true;
2022
2023 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2024 sctx->msaa_config.dirty = true;
2025 sctx->db_render_state.dirty = true;
2026
2027 /* Set sample locations as fragment shader constants. */
2028 switch (sctx->framebuffer.nr_samples) {
2029 case 1:
2030 constbuf.user_buffer = sctx->b.sample_locations_1x;
2031 break;
2032 case 2:
2033 constbuf.user_buffer = sctx->b.sample_locations_2x;
2034 break;
2035 case 4:
2036 constbuf.user_buffer = sctx->b.sample_locations_4x;
2037 break;
2038 case 8:
2039 constbuf.user_buffer = sctx->b.sample_locations_8x;
2040 break;
2041 case 16:
2042 constbuf.user_buffer = sctx->b.sample_locations_16x;
2043 break;
2044 default:
2045 assert(0);
2046 }
2047 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2048 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2049 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2050 }
2051 }
2052
2053 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2054 {
2055 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2056 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2057 unsigned i, nr_cbufs = state->nr_cbufs;
2058 struct r600_texture *tex = NULL;
2059 struct r600_surface *cb = NULL;
2060
2061 /* Colorbuffers. */
2062 for (i = 0; i < nr_cbufs; i++) {
2063 cb = (struct r600_surface*)state->cbufs[i];
2064 if (!cb) {
2065 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2066 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2067 continue;
2068 }
2069
2070 tex = (struct r600_texture *)cb->base.texture;
2071 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2072 &tex->resource, RADEON_USAGE_READWRITE,
2073 tex->surface.nsamples > 1 ?
2074 RADEON_PRIO_COLOR_BUFFER_MSAA :
2075 RADEON_PRIO_COLOR_BUFFER);
2076
2077 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2078 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2079 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2080 RADEON_PRIO_COLOR_META);
2081 }
2082
2083 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2084 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2085 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2086 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2087 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2088 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2089 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2090 radeon_emit(cs, 0); /* R_028C78 unused */
2091 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2092 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2093 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2094 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2095 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2096 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2097 }
2098 /* set CB_COLOR1_INFO for possible dual-src blending */
2099 if (i == 1 && state->cbufs[0]) {
2100 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2101 cb->cb_color_info | tex->cb_color_info);
2102 i++;
2103 }
2104 for (; i < 8 ; i++) {
2105 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2106 }
2107
2108 /* ZS buffer. */
2109 if (state->zsbuf) {
2110 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2111 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2112
2113 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2114 &rtex->resource, RADEON_USAGE_READWRITE,
2115 zb->base.texture->nr_samples > 1 ?
2116 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2117 RADEON_PRIO_DEPTH_BUFFER);
2118
2119 if (zb->db_htile_data_base) {
2120 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2121 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2122 RADEON_PRIO_DEPTH_META);
2123 }
2124
2125 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2126 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2127
2128 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2129 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2130 radeon_emit(cs, zb->db_z_info); /* R_028040_DB_Z_INFO */
2131 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2132 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2133 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2134 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2135 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2136 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2137 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2138
2139 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2140 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2141 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2142 zb->pa_su_poly_offset_db_fmt_cntl);
2143 } else {
2144 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2145 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2146 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2147 }
2148
2149 /* Framebuffer dimensions. */
2150 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2151 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2152 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2153
2154 cayman_emit_msaa_sample_locs(cs, sctx->framebuffer.nr_samples);
2155 }
2156
2157 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2158 {
2159 struct si_context *sctx = (struct si_context *)rctx;
2160 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2161
2162 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2163 sctx->ps_iter_samples);
2164 }
2165
2166 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2167
2168 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2169 {
2170 struct si_context *sctx = (struct si_context *)ctx;
2171
2172 if (sctx->ps_iter_samples == min_samples)
2173 return;
2174
2175 sctx->ps_iter_samples = min_samples;
2176
2177 if (sctx->framebuffer.nr_samples > 1)
2178 sctx->msaa_config.dirty = true;
2179 }
2180
2181 /*
2182 * Samplers
2183 */
2184
2185 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2186 struct pipe_resource *texture,
2187 const struct pipe_sampler_view *state)
2188 {
2189 struct si_context *sctx = (struct si_context*)ctx;
2190 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2191 struct r600_texture *tmp = (struct r600_texture*)texture;
2192 const struct util_format_description *desc;
2193 unsigned format, num_format;
2194 uint32_t pitch = 0;
2195 unsigned char state_swizzle[4], swizzle[4];
2196 unsigned height, depth, width;
2197 enum pipe_format pipe_format = state->format;
2198 struct radeon_surface_level *surflevel;
2199 int first_non_void;
2200 uint64_t va;
2201
2202 if (view == NULL)
2203 return NULL;
2204
2205 /* initialize base object */
2206 view->base = *state;
2207 view->base.texture = NULL;
2208 pipe_resource_reference(&view->base.texture, texture);
2209 view->base.reference.count = 1;
2210 view->base.context = ctx;
2211 view->resource = &tmp->resource;
2212
2213 /* Buffer resource. */
2214 if (texture->target == PIPE_BUFFER) {
2215 unsigned stride;
2216
2217 desc = util_format_description(state->format);
2218 first_non_void = util_format_get_first_non_void_channel(state->format);
2219 stride = desc->block.bits / 8;
2220 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2221 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2222 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2223
2224 view->state[0] = va;
2225 view->state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2226 S_008F04_STRIDE(stride);
2227 view->state[2] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2228 view->state[3] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2229 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2230 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2231 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2232 S_008F0C_NUM_FORMAT(num_format) |
2233 S_008F0C_DATA_FORMAT(format);
2234
2235 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2236 return &view->base;
2237 }
2238
2239 state_swizzle[0] = state->swizzle_r;
2240 state_swizzle[1] = state->swizzle_g;
2241 state_swizzle[2] = state->swizzle_b;
2242 state_swizzle[3] = state->swizzle_a;
2243
2244 surflevel = tmp->surface.level;
2245
2246 /* Texturing with separate depth and stencil. */
2247 if (tmp->is_depth && !tmp->is_flushing_texture) {
2248 switch (pipe_format) {
2249 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2250 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2251 break;
2252 case PIPE_FORMAT_X8Z24_UNORM:
2253 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2254 /* Z24 is always stored like this. */
2255 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2256 break;
2257 case PIPE_FORMAT_X24S8_UINT:
2258 case PIPE_FORMAT_S8X24_UINT:
2259 case PIPE_FORMAT_X32_S8X24_UINT:
2260 pipe_format = PIPE_FORMAT_S8_UINT;
2261 surflevel = tmp->surface.stencil_level;
2262 break;
2263 default:;
2264 }
2265 }
2266
2267 desc = util_format_description(pipe_format);
2268
2269 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2270 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2271 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2272
2273 switch (pipe_format) {
2274 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2275 case PIPE_FORMAT_X24S8_UINT:
2276 case PIPE_FORMAT_X32_S8X24_UINT:
2277 case PIPE_FORMAT_X8Z24_UNORM:
2278 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2279 break;
2280 default:
2281 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2282 }
2283 } else {
2284 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2285 }
2286
2287 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2288
2289 switch (pipe_format) {
2290 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2291 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2292 break;
2293 default:
2294 if (first_non_void < 0) {
2295 if (util_format_is_compressed(pipe_format)) {
2296 switch (pipe_format) {
2297 case PIPE_FORMAT_DXT1_SRGB:
2298 case PIPE_FORMAT_DXT1_SRGBA:
2299 case PIPE_FORMAT_DXT3_SRGBA:
2300 case PIPE_FORMAT_DXT5_SRGBA:
2301 case PIPE_FORMAT_BPTC_SRGBA:
2302 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2303 break;
2304 case PIPE_FORMAT_RGTC1_SNORM:
2305 case PIPE_FORMAT_LATC1_SNORM:
2306 case PIPE_FORMAT_RGTC2_SNORM:
2307 case PIPE_FORMAT_LATC2_SNORM:
2308 /* implies float, so use SNORM/UNORM to determine
2309 whether data is signed or not */
2310 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2311 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2312 break;
2313 default:
2314 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2315 break;
2316 }
2317 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2318 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2319 } else {
2320 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2321 }
2322 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2323 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2324 } else {
2325 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2326
2327 switch (desc->channel[first_non_void].type) {
2328 case UTIL_FORMAT_TYPE_FLOAT:
2329 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2330 break;
2331 case UTIL_FORMAT_TYPE_SIGNED:
2332 if (desc->channel[first_non_void].normalized)
2333 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2334 else if (desc->channel[first_non_void].pure_integer)
2335 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2336 else
2337 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2338 break;
2339 case UTIL_FORMAT_TYPE_UNSIGNED:
2340 if (desc->channel[first_non_void].normalized)
2341 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2342 else if (desc->channel[first_non_void].pure_integer)
2343 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2344 else
2345 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2346 }
2347 }
2348 }
2349
2350 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2351 if (format == ~0) {
2352 format = 0;
2353 }
2354
2355 /* not supported any more */
2356 //endian = si_colorformat_endian_swap(format);
2357
2358 width = surflevel[0].npix_x;
2359 height = surflevel[0].npix_y;
2360 depth = surflevel[0].npix_z;
2361 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2362
2363 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2364 height = 1;
2365 depth = texture->array_size;
2366 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2367 depth = texture->array_size;
2368 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2369 depth = texture->array_size / 6;
2370
2371 va = tmp->resource.gpu_address + surflevel[0].offset;
2372 va += tmp->mipmap_shift * surflevel[texture->last_level].slice_size * tmp->surface.array_size;
2373
2374 view->state[0] = va >> 8;
2375 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2376 S_008F14_DATA_FORMAT(format) |
2377 S_008F14_NUM_FORMAT(num_format));
2378 view->state[2] = (S_008F18_WIDTH(width - 1) |
2379 S_008F18_HEIGHT(height - 1));
2380 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2381 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2382 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2383 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2384 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2385 0 : state->u.tex.first_level - tmp->mipmap_shift) |
2386 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2387 util_logbase2(texture->nr_samples) :
2388 state->u.tex.last_level - tmp->mipmap_shift) |
2389 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2390 S_008F1C_POW2_PAD(texture->last_level > 0) |
2391 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2392 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2393 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2394 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2395 view->state[6] = 0;
2396 view->state[7] = 0;
2397
2398 /* Initialize the sampler view for FMASK. */
2399 if (tmp->fmask.size) {
2400 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2401 uint32_t fmask_format;
2402
2403 switch (texture->nr_samples) {
2404 case 2:
2405 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2406 break;
2407 case 4:
2408 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2409 break;
2410 case 8:
2411 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2412 break;
2413 default:
2414 assert(0);
2415 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2416 }
2417
2418 view->fmask_state[0] = va >> 8;
2419 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2420 S_008F14_DATA_FORMAT(fmask_format) |
2421 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2422 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2423 S_008F18_HEIGHT(height - 1);
2424 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2425 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2426 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2427 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2428 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2429 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2430 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2431 S_008F20_PITCH(tmp->fmask.pitch - 1);
2432 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2433 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2434 view->fmask_state[6] = 0;
2435 view->fmask_state[7] = 0;
2436 }
2437
2438 return &view->base;
2439 }
2440
2441 static void si_sampler_view_destroy(struct pipe_context *ctx,
2442 struct pipe_sampler_view *state)
2443 {
2444 struct si_sampler_view *view = (struct si_sampler_view *)state;
2445
2446 if (view->resource->b.b.target == PIPE_BUFFER)
2447 LIST_DELINIT(&view->list);
2448
2449 pipe_resource_reference(&state->texture, NULL);
2450 FREE(view);
2451 }
2452
2453 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2454 {
2455 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2456 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2457 (linear_filter &&
2458 (wrap == PIPE_TEX_WRAP_CLAMP ||
2459 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2460 }
2461
2462 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2463 {
2464 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2465 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2466
2467 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2468 state->border_color.ui[2] || state->border_color.ui[3]) &&
2469 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2470 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2471 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2472 }
2473
2474 static void *si_create_sampler_state(struct pipe_context *ctx,
2475 const struct pipe_sampler_state *state)
2476 {
2477 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2478 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2479 unsigned border_color_type;
2480
2481 if (rstate == NULL) {
2482 return NULL;
2483 }
2484
2485 if (sampler_state_needs_border_color(state))
2486 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2487 else
2488 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2489
2490 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2491 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2492 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2493 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2494 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2495 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2496 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2497 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2498 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2499 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2500 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2501 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2502 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2503 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2504
2505 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2506 memcpy(rstate->border_color, state->border_color.ui,
2507 sizeof(rstate->border_color));
2508 }
2509
2510 return rstate;
2511 }
2512
2513 /* Upload border colors and update the pointers in resource descriptors.
2514 * There can only be 4096 border colors per context.
2515 *
2516 * XXX: This is broken if the buffer gets reallocated.
2517 */
2518 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2519 void **states)
2520 {
2521 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2522 uint32_t *border_color_table = NULL;
2523 int i, j;
2524
2525 for (i = 0; i < count; i++) {
2526 if (rstates[i] &&
2527 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2528 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2529 if (!sctx->border_color_table ||
2530 ((sctx->border_color_offset + count - i) &
2531 C_008F3C_BORDER_COLOR_PTR)) {
2532 r600_resource_reference(&sctx->border_color_table, NULL);
2533 sctx->border_color_offset = 0;
2534
2535 sctx->border_color_table =
2536 si_resource_create_custom(&sctx->screen->b.b,
2537 PIPE_USAGE_DYNAMIC,
2538 4096 * 4 * 4);
2539 }
2540
2541 if (!border_color_table) {
2542 border_color_table =
2543 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2544 sctx->b.rings.gfx.cs,
2545 PIPE_TRANSFER_WRITE |
2546 PIPE_TRANSFER_UNSYNCHRONIZED);
2547 }
2548
2549 for (j = 0; j < 4; j++) {
2550 border_color_table[4 * sctx->border_color_offset + j] =
2551 util_le32_to_cpu(rstates[i]->border_color[j]);
2552 }
2553
2554 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2555 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2556 }
2557 }
2558
2559 if (border_color_table) {
2560 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2561
2562 uint64_t va_offset = sctx->border_color_table->gpu_address;
2563
2564 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2565 if (sctx->b.chip_class >= CIK)
2566 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2567 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2568 RADEON_PRIO_SHADER_DATA);
2569 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2570 }
2571 }
2572
2573 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2574 unsigned start, unsigned count,
2575 void **states)
2576 {
2577 struct si_context *sctx = (struct si_context *)ctx;
2578
2579 if (!count || shader >= SI_NUM_SHADERS)
2580 return;
2581
2582 si_set_border_colors(sctx, count, states);
2583 si_set_sampler_descriptors(sctx, shader, start, count, states);
2584 }
2585
2586 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2587 {
2588 struct si_context *sctx = (struct si_context *)ctx;
2589 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2590 struct si_pm4_state *pm4 = &state->pm4;
2591 uint16_t mask = sample_mask;
2592
2593 if (state == NULL)
2594 return;
2595
2596 state->sample_mask = mask;
2597 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2598 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2599
2600 si_pm4_set_state(sctx, sample_mask, state);
2601 }
2602
2603 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2604 {
2605 free(state);
2606 }
2607
2608 /*
2609 * Vertex elements & buffers
2610 */
2611
2612 static void *si_create_vertex_elements(struct pipe_context *ctx,
2613 unsigned count,
2614 const struct pipe_vertex_element *elements)
2615 {
2616 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2617 int i;
2618
2619 assert(count < PIPE_MAX_ATTRIBS);
2620 if (!v)
2621 return NULL;
2622
2623 v->count = count;
2624 for (i = 0; i < count; ++i) {
2625 const struct util_format_description *desc;
2626 unsigned data_format, num_format;
2627 int first_non_void;
2628
2629 desc = util_format_description(elements[i].src_format);
2630 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2631 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2632 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2633
2634 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2635 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2636 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2637 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2638 S_008F0C_NUM_FORMAT(num_format) |
2639 S_008F0C_DATA_FORMAT(data_format);
2640 v->format_size[i] = desc->block.bits / 8;
2641 }
2642 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2643
2644 return v;
2645 }
2646
2647 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2648 {
2649 struct si_context *sctx = (struct si_context *)ctx;
2650 struct si_vertex_element *v = (struct si_vertex_element*)state;
2651
2652 sctx->vertex_elements = v;
2653 sctx->vertex_buffers_dirty = true;
2654 }
2655
2656 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2657 {
2658 struct si_context *sctx = (struct si_context *)ctx;
2659
2660 if (sctx->vertex_elements == state)
2661 sctx->vertex_elements = NULL;
2662 FREE(state);
2663 }
2664
2665 static void si_set_vertex_buffers(struct pipe_context *ctx,
2666 unsigned start_slot, unsigned count,
2667 const struct pipe_vertex_buffer *buffers)
2668 {
2669 struct si_context *sctx = (struct si_context *)ctx;
2670 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2671 int i;
2672
2673 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2674
2675 if (buffers) {
2676 for (i = 0; i < count; i++) {
2677 const struct pipe_vertex_buffer *src = buffers + i;
2678 struct pipe_vertex_buffer *dsti = dst + i;
2679
2680 pipe_resource_reference(&dsti->buffer, src->buffer);
2681 dsti->buffer_offset = src->buffer_offset;
2682 dsti->stride = src->stride;
2683 }
2684 } else {
2685 for (i = 0; i < count; i++) {
2686 pipe_resource_reference(&dst[i].buffer, NULL);
2687 }
2688 }
2689 sctx->vertex_buffers_dirty = true;
2690 }
2691
2692 static void si_set_index_buffer(struct pipe_context *ctx,
2693 const struct pipe_index_buffer *ib)
2694 {
2695 struct si_context *sctx = (struct si_context *)ctx;
2696
2697 if (ib) {
2698 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2699 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2700 } else {
2701 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2702 }
2703 }
2704
2705 /*
2706 * Misc
2707 */
2708 static void si_set_polygon_stipple(struct pipe_context *ctx,
2709 const struct pipe_poly_stipple *state)
2710 {
2711 }
2712
2713 static void si_texture_barrier(struct pipe_context *ctx)
2714 {
2715 struct si_context *sctx = (struct si_context *)ctx;
2716
2717 sctx->b.flags |= R600_CONTEXT_INV_TEX_CACHE |
2718 R600_CONTEXT_FLUSH_AND_INV_CB;
2719 }
2720
2721 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2722 {
2723 struct pipe_blend_state blend;
2724
2725 memset(&blend, 0, sizeof(blend));
2726 blend.independent_blend_enable = true;
2727 blend.rt[0].colormask = 0xf;
2728 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2729 }
2730
2731 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2732 bool include_draw_vbo)
2733 {
2734 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2735 }
2736
2737 void si_init_state_functions(struct si_context *sctx)
2738 {
2739 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2740 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2741
2742 sctx->b.b.create_blend_state = si_create_blend_state;
2743 sctx->b.b.bind_blend_state = si_bind_blend_state;
2744 sctx->b.b.delete_blend_state = si_delete_blend_state;
2745 sctx->b.b.set_blend_color = si_set_blend_color;
2746
2747 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2748 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2749 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2750
2751 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2752 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2753 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2754
2755 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2756 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2757 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2758 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2759
2760 sctx->b.b.set_clip_state = si_set_clip_state;
2761 sctx->b.b.set_scissor_states = si_set_scissor_states;
2762 sctx->b.b.set_viewport_states = si_set_viewport_states;
2763 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2764
2765 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2766 sctx->b.b.get_sample_position = cayman_get_sample_position;
2767
2768 sctx->b.b.create_sampler_state = si_create_sampler_state;
2769 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2770 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2771
2772 sctx->b.b.create_sampler_view = si_create_sampler_view;
2773 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2774
2775 sctx->b.b.set_sample_mask = si_set_sample_mask;
2776
2777 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2778 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2779 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2780 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2781 sctx->b.b.set_index_buffer = si_set_index_buffer;
2782
2783 sctx->b.b.texture_barrier = si_texture_barrier;
2784 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2785 sctx->b.b.set_min_samples = si_set_min_samples;
2786
2787 sctx->b.dma_copy = si_dma_copy;
2788 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2789 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2790
2791 sctx->b.b.draw_vbo = si_draw_vbo;
2792 }
2793
2794 static void
2795 si_write_harvested_raster_configs(struct si_context *sctx,
2796 struct si_pm4_state *pm4,
2797 unsigned raster_config)
2798 {
2799 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
2800 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
2801 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2802 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2803 unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
2804 unsigned rb_per_se = num_rb / num_se;
2805 unsigned se0_mask = (1 << rb_per_se) - 1;
2806 unsigned se1_mask = se0_mask << rb_per_se;
2807 unsigned se;
2808
2809 assert(num_se == 1 || num_se == 2);
2810 assert(sh_per_se == 1 || sh_per_se == 2);
2811 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
2812
2813 /* XXX: I can't figure out what the *_XSEL and *_YSEL
2814 * fields are for, so I'm leaving them as their default
2815 * values. */
2816
2817 se0_mask &= rb_mask;
2818 se1_mask &= rb_mask;
2819 if (num_se == 2 && (!se0_mask || !se1_mask)) {
2820 raster_config &= C_028350_SE_MAP;
2821
2822 if (!se0_mask) {
2823 raster_config |=
2824 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
2825 } else {
2826 raster_config |=
2827 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
2828 }
2829 }
2830
2831 for (se = 0; se < num_se; se++) {
2832 unsigned raster_config_se = raster_config;
2833 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
2834 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
2835
2836 pkr0_mask &= rb_mask;
2837 pkr1_mask &= rb_mask;
2838 if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
2839 raster_config_se &= C_028350_PKR_MAP;
2840
2841 if (!pkr0_mask) {
2842 raster_config_se |=
2843 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
2844 } else {
2845 raster_config_se |=
2846 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
2847 }
2848 }
2849
2850 if (rb_per_pkr == 2) {
2851 unsigned rb0_mask = 1 << (se * rb_per_se);
2852 unsigned rb1_mask = rb0_mask << 1;
2853
2854 rb0_mask &= rb_mask;
2855 rb1_mask &= rb_mask;
2856 if (!rb0_mask || !rb1_mask) {
2857 raster_config_se &= C_028350_RB_MAP_PKR0;
2858
2859 if (!rb0_mask) {
2860 raster_config_se |=
2861 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
2862 } else {
2863 raster_config_se |=
2864 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
2865 }
2866 }
2867
2868 if (sh_per_se == 2) {
2869 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
2870 rb1_mask = rb0_mask << 1;
2871 rb0_mask &= rb_mask;
2872 rb1_mask &= rb_mask;
2873 if (!rb0_mask || !rb1_mask) {
2874 raster_config_se &= C_028350_RB_MAP_PKR1;
2875
2876 if (!rb0_mask) {
2877 raster_config_se |=
2878 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
2879 } else {
2880 raster_config_se |=
2881 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
2882 }
2883 }
2884 }
2885 }
2886
2887 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
2888 SE_INDEX(se) | SH_BROADCAST_WRITES |
2889 INSTANCE_BROADCAST_WRITES);
2890 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
2891 }
2892
2893 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
2894 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
2895 INSTANCE_BROADCAST_WRITES);
2896 }
2897
2898 void si_init_config(struct si_context *sctx)
2899 {
2900 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2901
2902 if (pm4 == NULL)
2903 return;
2904
2905 si_cmd_context_control(pm4);
2906
2907 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2908 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2909 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2910 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2911 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2912 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2913 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2914 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2915 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2916 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2917 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2918 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2919
2920 /* FIXME calculate these values somehow ??? */
2921 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
2922 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
2923 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
2924
2925 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2926 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2927 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
2928 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2929
2930 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
2931 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
2932 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
2933 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT, 0);
2934
2935 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2936 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2937 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2938 if (sctx->b.chip_class < CIK)
2939 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2940 S_008A14_CLIP_VTX_REORDER_ENA(1));
2941
2942 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2943 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2944
2945 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2946
2947 if (sctx->b.chip_class >= CIK) {
2948 switch (sctx->screen->b.family) {
2949 case CHIP_BONAIRE:
2950 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
2951 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
2952 break;
2953 case CHIP_HAWAII:
2954 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
2955 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
2956 break;
2957 case CHIP_KAVERI:
2958 /* XXX todo */
2959 case CHIP_KABINI:
2960 /* XXX todo */
2961 case CHIP_MULLINS:
2962 /* XXX todo */
2963 default:
2964 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
2965 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x00000000);
2966 break;
2967 }
2968 } else {
2969 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2970 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2971 unsigned raster_config;
2972
2973 switch (sctx->screen->b.family) {
2974 case CHIP_TAHITI:
2975 case CHIP_PITCAIRN:
2976 raster_config = 0x2a00126a;
2977 break;
2978 case CHIP_VERDE:
2979 raster_config = 0x0000124a;
2980 break;
2981 case CHIP_OLAND:
2982 raster_config = 0x00000082;
2983 break;
2984 case CHIP_HAINAN:
2985 raster_config = 0x00000000;
2986 break;
2987 default:
2988 fprintf(stderr,
2989 "radeonsi: Unknown GPU, using 0 for raster_config\n");
2990 raster_config = 0x00000000;
2991 break;
2992 }
2993
2994 /* Always use the default config when all backends are enabled. */
2995 if (rb_mask && util_bitcount(rb_mask) >= num_rb) {
2996 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
2997 raster_config);
2998 } else {
2999 si_write_harvested_raster_configs(sctx, pm4, raster_config);
3000 }
3001 }
3002
3003 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3004 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3005 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3006 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3007 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3008 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3009 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3010
3011 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3012 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3013 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
3014 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
3015 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
3016 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
3017 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
3018 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
3019 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
3020 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
3021 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
3022 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
3023 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3024 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3025 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3026
3027 /* There is a hang if stencil is used and fast stencil is enabled
3028 * regardless of whether HTILE is depth-only or not.
3029 */
3030 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3031 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3032 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3033 S_02800C_FAST_STENCIL_DISABLE(1));
3034
3035 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3036 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3037 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3038
3039 if (sctx->b.chip_class >= CIK) {
3040 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3041 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3042 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3043 }
3044
3045 si_pm4_set_state(sctx, init, pm4);
3046 }