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radeonsi: emit sample locations for 1xAA only when the hw bug is present
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35 #include "util/fast_idiv_by_const.h"
36
37 static unsigned si_map_swizzle(unsigned swizzle)
38 {
39 switch (swizzle) {
40 case PIPE_SWIZZLE_Y:
41 return V_008F0C_SQ_SEL_Y;
42 case PIPE_SWIZZLE_Z:
43 return V_008F0C_SQ_SEL_Z;
44 case PIPE_SWIZZLE_W:
45 return V_008F0C_SQ_SEL_W;
46 case PIPE_SWIZZLE_0:
47 return V_008F0C_SQ_SEL_0;
48 case PIPE_SWIZZLE_1:
49 return V_008F0C_SQ_SEL_1;
50 default: /* PIPE_SWIZZLE_X */
51 return V_008F0C_SQ_SEL_X;
52 }
53 }
54
55 /* 12.4 fixed-point */
56 static unsigned si_pack_float_12p4(float x)
57 {
58 return x <= 0 ? 0 :
59 x >= 4096 ? 0xffff : x * 16;
60 }
61
62 /*
63 * Inferred framebuffer and blender state.
64 *
65 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
66 * if there is not enough PS outputs.
67 */
68 static void si_emit_cb_render_state(struct si_context *sctx)
69 {
70 struct radeon_cmdbuf *cs = sctx->gfx_cs;
71 struct si_state_blend *blend = sctx->queued.named.blend;
72 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
73 * but you never know. */
74 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
75 unsigned i;
76
77 if (blend)
78 cb_target_mask &= blend->cb_target_mask;
79
80 /* Avoid a hang that happens when dual source blending is enabled
81 * but there is not enough color outputs. This is undefined behavior,
82 * so disable color writes completely.
83 *
84 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 */
86 if (blend && blend->dual_src_blend &&
87 sctx->ps_shader.cso &&
88 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
89 cb_target_mask = 0;
90
91 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
92 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
93
94 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
95 * I think we don't have to do anything between IBs.
96 */
97 if (sctx->screen->dfsm_allowed &&
98 sctx->last_cb_target_mask != cb_target_mask) {
99 sctx->last_cb_target_mask = cb_target_mask;
100
101 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
102 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
103 }
104
105 if (sctx->chip_class >= VI) {
106 /* DCC MSAA workaround for blending.
107 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
108 * COMBINER_DISABLE, but that would be more complicated.
109 */
110 bool oc_disable = (sctx->chip_class == VI ||
111 sctx->chip_class == GFX9) &&
112 blend &&
113 blend->blend_enable_4bit & cb_target_mask &&
114 sctx->framebuffer.nr_samples >= 2;
115
116 radeon_opt_set_context_reg(
117 sctx, R_028424_CB_DCC_CONTROL,
118 SI_TRACKED_CB_DCC_CONTROL,
119 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
120 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
121 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
122 }
123
124 /* RB+ register settings. */
125 if (sctx->screen->rbplus_allowed) {
126 unsigned spi_shader_col_format =
127 sctx->ps_shader.cso ?
128 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
129 unsigned sx_ps_downconvert = 0;
130 unsigned sx_blend_opt_epsilon = 0;
131 unsigned sx_blend_opt_control = 0;
132
133 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
134 struct si_surface *surf =
135 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
136 unsigned format, swap, spi_format, colormask;
137 bool has_alpha, has_rgb;
138
139 if (!surf)
140 continue;
141
142 format = G_028C70_FORMAT(surf->cb_color_info);
143 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
144 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
145 colormask = (cb_target_mask >> (i * 4)) & 0xf;
146
147 /* Set if RGB and A are present. */
148 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
149
150 if (format == V_028C70_COLOR_8 ||
151 format == V_028C70_COLOR_16 ||
152 format == V_028C70_COLOR_32)
153 has_rgb = !has_alpha;
154 else
155 has_rgb = true;
156
157 /* Check the colormask and export format. */
158 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
159 has_rgb = false;
160 if (!(colormask & PIPE_MASK_A))
161 has_alpha = false;
162
163 if (spi_format == V_028714_SPI_SHADER_ZERO) {
164 has_rgb = false;
165 has_alpha = false;
166 }
167
168 /* Disable value checking for disabled channels. */
169 if (!has_rgb)
170 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
171 if (!has_alpha)
172 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
173
174 /* Enable down-conversion for 32bpp and smaller formats. */
175 switch (format) {
176 case V_028C70_COLOR_8:
177 case V_028C70_COLOR_8_8:
178 case V_028C70_COLOR_8_8_8_8:
179 /* For 1 and 2-channel formats, use the superset thereof. */
180 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
182 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
183 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
184 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
185 }
186 break;
187
188 case V_028C70_COLOR_5_6_5:
189 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_1_5_5_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_4_4_4_4:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_32:
210 if (swap == V_028C70_SWAP_STD &&
211 spi_format == V_028714_SPI_SHADER_32_R)
212 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
213 else if (swap == V_028C70_SWAP_ALT_REV &&
214 spi_format == V_028714_SPI_SHADER_32_AR)
215 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
216 break;
217
218 case V_028C70_COLOR_16:
219 case V_028C70_COLOR_16_16:
220 /* For 1-channel formats, use the superset thereof. */
221 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
225 if (swap == V_028C70_SWAP_STD ||
226 swap == V_028C70_SWAP_STD_REV)
227 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
228 else
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
230 }
231 break;
232
233 case V_028C70_COLOR_10_11_11:
234 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
235 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
236 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_2_10_10_10:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
244 }
245 break;
246 }
247 }
248
249 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
250 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
251 SI_TRACKED_SX_PS_DOWNCONVERT,
252 sx_ps_downconvert, sx_blend_opt_epsilon,
253 sx_blend_opt_control);
254 }
255 }
256
257 /*
258 * Blender functions
259 */
260
261 static uint32_t si_translate_blend_function(int blend_func)
262 {
263 switch (blend_func) {
264 case PIPE_BLEND_ADD:
265 return V_028780_COMB_DST_PLUS_SRC;
266 case PIPE_BLEND_SUBTRACT:
267 return V_028780_COMB_SRC_MINUS_DST;
268 case PIPE_BLEND_REVERSE_SUBTRACT:
269 return V_028780_COMB_DST_MINUS_SRC;
270 case PIPE_BLEND_MIN:
271 return V_028780_COMB_MIN_DST_SRC;
272 case PIPE_BLEND_MAX:
273 return V_028780_COMB_MAX_DST_SRC;
274 default:
275 PRINT_ERR("Unknown blend function %d\n", blend_func);
276 assert(0);
277 break;
278 }
279 return 0;
280 }
281
282 static uint32_t si_translate_blend_factor(int blend_fact)
283 {
284 switch (blend_fact) {
285 case PIPE_BLENDFACTOR_ONE:
286 return V_028780_BLEND_ONE;
287 case PIPE_BLENDFACTOR_SRC_COLOR:
288 return V_028780_BLEND_SRC_COLOR;
289 case PIPE_BLENDFACTOR_SRC_ALPHA:
290 return V_028780_BLEND_SRC_ALPHA;
291 case PIPE_BLENDFACTOR_DST_ALPHA:
292 return V_028780_BLEND_DST_ALPHA;
293 case PIPE_BLENDFACTOR_DST_COLOR:
294 return V_028780_BLEND_DST_COLOR;
295 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
296 return V_028780_BLEND_SRC_ALPHA_SATURATE;
297 case PIPE_BLENDFACTOR_CONST_COLOR:
298 return V_028780_BLEND_CONSTANT_COLOR;
299 case PIPE_BLENDFACTOR_CONST_ALPHA:
300 return V_028780_BLEND_CONSTANT_ALPHA;
301 case PIPE_BLENDFACTOR_ZERO:
302 return V_028780_BLEND_ZERO;
303 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
304 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
305 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
306 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
307 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_COLOR:
310 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
311 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
315 case PIPE_BLENDFACTOR_SRC1_COLOR:
316 return V_028780_BLEND_SRC1_COLOR;
317 case PIPE_BLENDFACTOR_SRC1_ALPHA:
318 return V_028780_BLEND_SRC1_ALPHA;
319 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
320 return V_028780_BLEND_INV_SRC1_COLOR;
321 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
322 return V_028780_BLEND_INV_SRC1_ALPHA;
323 default:
324 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
325 assert(0);
326 break;
327 }
328 return 0;
329 }
330
331 static uint32_t si_translate_blend_opt_function(int blend_func)
332 {
333 switch (blend_func) {
334 case PIPE_BLEND_ADD:
335 return V_028760_OPT_COMB_ADD;
336 case PIPE_BLEND_SUBTRACT:
337 return V_028760_OPT_COMB_SUBTRACT;
338 case PIPE_BLEND_REVERSE_SUBTRACT:
339 return V_028760_OPT_COMB_REVSUBTRACT;
340 case PIPE_BLEND_MIN:
341 return V_028760_OPT_COMB_MIN;
342 case PIPE_BLEND_MAX:
343 return V_028760_OPT_COMB_MAX;
344 default:
345 return V_028760_OPT_COMB_BLEND_DISABLED;
346 }
347 }
348
349 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
350 {
351 switch (blend_fact) {
352 case PIPE_BLENDFACTOR_ZERO:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
354 case PIPE_BLENDFACTOR_ONE:
355 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
356 case PIPE_BLENDFACTOR_SRC_COLOR:
357 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
358 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
359 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
360 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
361 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
362 case PIPE_BLENDFACTOR_SRC_ALPHA:
363 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
364 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
365 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
366 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
368 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
369 default:
370 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
371 }
372 }
373
374 static void si_blend_check_commutativity(struct si_screen *sscreen,
375 struct si_state_blend *blend,
376 enum pipe_blend_func func,
377 enum pipe_blendfactor src,
378 enum pipe_blendfactor dst,
379 unsigned chanmask)
380 {
381 /* Src factor is allowed when it does not depend on Dst */
382 static const uint32_t src_allowed =
383 (1u << PIPE_BLENDFACTOR_ONE) |
384 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
386 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
387 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
388 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
389 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
390 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
391 (1u << PIPE_BLENDFACTOR_ZERO) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
393 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
395 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
397 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
398
399 if (dst == PIPE_BLENDFACTOR_ONE &&
400 (src_allowed & (1u << src))) {
401 /* Addition is commutative, but floating point addition isn't
402 * associative: subtle changes can be introduced via different
403 * rounding.
404 *
405 * Out-of-order is also non-deterministic, which means that
406 * this breaks OpenGL invariance requirements. So only enable
407 * out-of-order additive blending if explicitly allowed by a
408 * setting.
409 */
410 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
411 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
412 blend->commutative_4bit |= chanmask;
413 }
414 }
415
416 /**
417 * Get rid of DST in the blend factors by commuting the operands:
418 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 */
420 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
421 unsigned *dst_factor, unsigned expected_dst,
422 unsigned replacement_src)
423 {
424 if (*src_factor == expected_dst &&
425 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
426 *src_factor = PIPE_BLENDFACTOR_ZERO;
427 *dst_factor = replacement_src;
428
429 /* Commuting the operands requires reversing subtractions. */
430 if (*func == PIPE_BLEND_SUBTRACT)
431 *func = PIPE_BLEND_REVERSE_SUBTRACT;
432 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
433 *func = PIPE_BLEND_SUBTRACT;
434 }
435 }
436
437 static bool si_blend_factor_uses_dst(unsigned factor)
438 {
439 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
440 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
441 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
442 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
443 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
444 }
445
446 static void *si_create_blend_state_mode(struct pipe_context *ctx,
447 const struct pipe_blend_state *state,
448 unsigned mode)
449 {
450 struct si_context *sctx = (struct si_context*)ctx;
451 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
452 struct si_pm4_state *pm4 = &blend->pm4;
453 uint32_t sx_mrt_blend_opt[8] = {0};
454 uint32_t color_control = 0;
455
456 if (!blend)
457 return NULL;
458
459 blend->alpha_to_coverage = state->alpha_to_coverage;
460 blend->alpha_to_one = state->alpha_to_one;
461 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
462 blend->logicop_enable = state->logicop_enable;
463
464 if (state->logicop_enable) {
465 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
466 } else {
467 color_control |= S_028808_ROP3(0xcc);
468 }
469
470 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
471 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
472 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
475 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
476
477 if (state->alpha_to_coverage)
478 blend->need_src_alpha_4bit |= 0xf;
479
480 blend->cb_target_mask = 0;
481 blend->cb_target_enabled_4bit = 0;
482
483 for (int i = 0; i < 8; i++) {
484 /* state->rt entries > 0 only written if independent blending */
485 const int j = state->independent_blend_enable ? i : 0;
486
487 unsigned eqRGB = state->rt[j].rgb_func;
488 unsigned srcRGB = state->rt[j].rgb_src_factor;
489 unsigned dstRGB = state->rt[j].rgb_dst_factor;
490 unsigned eqA = state->rt[j].alpha_func;
491 unsigned srcA = state->rt[j].alpha_src_factor;
492 unsigned dstA = state->rt[j].alpha_dst_factor;
493
494 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
495 unsigned blend_cntl = 0;
496
497 sx_mrt_blend_opt[i] =
498 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
499 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
500
501 /* Only set dual source blending for MRT0 to avoid a hang. */
502 if (i >= 1 && blend->dual_src_blend) {
503 /* Vulkan does this for dual source blending. */
504 if (i == 1)
505 blend_cntl |= S_028780_ENABLE(1);
506
507 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
508 continue;
509 }
510
511 /* Only addition and subtraction equations are supported with
512 * dual source blending.
513 */
514 if (blend->dual_src_blend &&
515 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
516 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
517 assert(!"Unsupported equation for dual source blending");
518 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
519 continue;
520 }
521
522 /* cb_render_state will disable unused ones */
523 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
524 if (state->rt[j].colormask)
525 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
526
527 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
528 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
529 continue;
530 }
531
532 si_blend_check_commutativity(sctx->screen, blend,
533 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
534 si_blend_check_commutativity(sctx->screen, blend,
535 eqA, srcA, dstA, 0x8 << (4 * i));
536
537 /* Blending optimizations for RB+.
538 * These transformations don't change the behavior.
539 *
540 * First, get rid of DST in the blend factors:
541 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
542 */
543 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
544 PIPE_BLENDFACTOR_DST_COLOR,
545 PIPE_BLENDFACTOR_SRC_COLOR);
546 si_blend_remove_dst(&eqA, &srcA, &dstA,
547 PIPE_BLENDFACTOR_DST_COLOR,
548 PIPE_BLENDFACTOR_SRC_COLOR);
549 si_blend_remove_dst(&eqA, &srcA, &dstA,
550 PIPE_BLENDFACTOR_DST_ALPHA,
551 PIPE_BLENDFACTOR_SRC_ALPHA);
552
553 /* Look up the ideal settings from tables. */
554 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
555 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
556 srcA_opt = si_translate_blend_opt_factor(srcA, true);
557 dstA_opt = si_translate_blend_opt_factor(dstA, true);
558
559 /* Handle interdependencies. */
560 if (si_blend_factor_uses_dst(srcRGB))
561 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
562 if (si_blend_factor_uses_dst(srcA))
563 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
564
565 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
566 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
567 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
568 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
569 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
570
571 /* Set the final value. */
572 sx_mrt_blend_opt[i] =
573 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
574 S_028760_COLOR_DST_OPT(dstRGB_opt) |
575 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
576 S_028760_ALPHA_SRC_OPT(srcA_opt) |
577 S_028760_ALPHA_DST_OPT(dstA_opt) |
578 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
579
580 /* Set blend state. */
581 blend_cntl |= S_028780_ENABLE(1);
582 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
583 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
584 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
585
586 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
587 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
588 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
589 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
590 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
591 }
592 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
593
594 blend->blend_enable_4bit |= 0xfu << (i * 4);
595
596 /* This is only important for formats without alpha. */
597 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
598 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
599 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
600 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
601 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
602 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
603 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
604 }
605
606 if (blend->cb_target_mask) {
607 color_control |= S_028808_MODE(mode);
608 } else {
609 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
610 }
611
612 if (sctx->screen->rbplus_allowed) {
613 /* Disable RB+ blend optimizations for dual source blending.
614 * Vulkan does this.
615 */
616 if (blend->dual_src_blend) {
617 for (int i = 0; i < 8; i++) {
618 sx_mrt_blend_opt[i] =
619 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
620 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
621 }
622 }
623
624 for (int i = 0; i < 8; i++)
625 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
626 sx_mrt_blend_opt[i]);
627
628 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
629 if (blend->dual_src_blend || state->logicop_enable ||
630 mode == V_028808_CB_RESOLVE)
631 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
632 }
633
634 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
635 return blend;
636 }
637
638 static void *si_create_blend_state(struct pipe_context *ctx,
639 const struct pipe_blend_state *state)
640 {
641 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
642 }
643
644 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
645 {
646 struct si_context *sctx = (struct si_context *)ctx;
647 struct si_state_blend *old_blend = sctx->queued.named.blend;
648 struct si_state_blend *blend = (struct si_state_blend *)state;
649
650 if (!state)
651 return;
652
653 si_pm4_bind_state(sctx, blend, state);
654
655 if (!old_blend ||
656 old_blend->cb_target_mask != blend->cb_target_mask ||
657 old_blend->dual_src_blend != blend->dual_src_blend ||
658 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
659 sctx->framebuffer.nr_samples >= 2 &&
660 sctx->screen->dcc_msaa_allowed))
661 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
662
663 if (!old_blend ||
664 old_blend->cb_target_mask != blend->cb_target_mask ||
665 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
666 old_blend->alpha_to_one != blend->alpha_to_one ||
667 old_blend->dual_src_blend != blend->dual_src_blend ||
668 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
669 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
670 sctx->do_update_shaders = true;
671
672 if (sctx->screen->dpbb_allowed &&
673 (!old_blend ||
674 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
675 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
676 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
677 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
678
679 if (sctx->screen->has_out_of_order_rast &&
680 (!old_blend ||
681 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
682 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
683 old_blend->commutative_4bit != blend->commutative_4bit ||
684 old_blend->logicop_enable != blend->logicop_enable)))
685 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
686 }
687
688 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
689 {
690 struct si_context *sctx = (struct si_context *)ctx;
691 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
692 }
693
694 static void si_set_blend_color(struct pipe_context *ctx,
695 const struct pipe_blend_color *state)
696 {
697 struct si_context *sctx = (struct si_context *)ctx;
698 static const struct pipe_blend_color zeros;
699
700 sctx->blend_color.state = *state;
701 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
702 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
703 }
704
705 static void si_emit_blend_color(struct si_context *sctx)
706 {
707 struct radeon_cmdbuf *cs = sctx->gfx_cs;
708
709 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
710 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
711 }
712
713 /*
714 * Clipping
715 */
716
717 static void si_set_clip_state(struct pipe_context *ctx,
718 const struct pipe_clip_state *state)
719 {
720 struct si_context *sctx = (struct si_context *)ctx;
721 struct pipe_constant_buffer cb;
722 static const struct pipe_clip_state zeros;
723
724 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
725 return;
726
727 sctx->clip_state.state = *state;
728 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
729 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
730
731 cb.buffer = NULL;
732 cb.user_buffer = state->ucp;
733 cb.buffer_offset = 0;
734 cb.buffer_size = 4*4*8;
735 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
736 pipe_resource_reference(&cb.buffer, NULL);
737 }
738
739 static void si_emit_clip_state(struct si_context *sctx)
740 {
741 struct radeon_cmdbuf *cs = sctx->gfx_cs;
742
743 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
744 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
745 }
746
747 static void si_emit_clip_regs(struct si_context *sctx)
748 {
749 struct si_shader *vs = si_get_vs_state(sctx);
750 struct si_shader_selector *vs_sel = vs->selector;
751 struct tgsi_shader_info *info = &vs_sel->info;
752 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
753 unsigned window_space =
754 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
755 unsigned clipdist_mask = vs_sel->clipdist_mask;
756 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
757 unsigned culldist_mask = vs_sel->culldist_mask;
758 unsigned total_mask;
759
760 if (vs->key.opt.clip_disable) {
761 assert(!info->culldist_writemask);
762 clipdist_mask = 0;
763 culldist_mask = 0;
764 }
765 total_mask = clipdist_mask | culldist_mask;
766
767 /* Clip distances on points have no effect, so need to be implemented
768 * as cull distances. This applies for the clipvertex case as well.
769 *
770 * Setting this for primitives other than points should have no adverse
771 * effects.
772 */
773 clipdist_mask &= rs->clip_plane_enable;
774 culldist_mask |= clipdist_mask;
775
776 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
777 SI_TRACKED_PA_CL_VS_OUT_CNTL,
778 vs_sel->pa_cl_vs_out_cntl |
779 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
780 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
781 clipdist_mask | (culldist_mask << 8));
782 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
783 SI_TRACKED_PA_CL_CLIP_CNTL,
784 rs->pa_cl_clip_cntl |
785 ucp_mask |
786 S_028810_CLIP_DISABLE(window_space));
787 }
788
789 /*
790 * inferred state between framebuffer and rasterizer
791 */
792 static void si_update_poly_offset_state(struct si_context *sctx)
793 {
794 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
795
796 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
797 si_pm4_bind_state(sctx, poly_offset, NULL);
798 return;
799 }
800
801 /* Use the user format, not db_render_format, so that the polygon
802 * offset behaves as expected by applications.
803 */
804 switch (sctx->framebuffer.state.zsbuf->texture->format) {
805 case PIPE_FORMAT_Z16_UNORM:
806 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
807 break;
808 default: /* 24-bit */
809 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
810 break;
811 case PIPE_FORMAT_Z32_FLOAT:
812 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
813 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
814 break;
815 }
816 }
817
818 /*
819 * Rasterizer
820 */
821
822 static uint32_t si_translate_fill(uint32_t func)
823 {
824 switch(func) {
825 case PIPE_POLYGON_MODE_FILL:
826 return V_028814_X_DRAW_TRIANGLES;
827 case PIPE_POLYGON_MODE_LINE:
828 return V_028814_X_DRAW_LINES;
829 case PIPE_POLYGON_MODE_POINT:
830 return V_028814_X_DRAW_POINTS;
831 default:
832 assert(0);
833 return V_028814_X_DRAW_POINTS;
834 }
835 }
836
837 static void *si_create_rs_state(struct pipe_context *ctx,
838 const struct pipe_rasterizer_state *state)
839 {
840 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
841 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
842 struct si_pm4_state *pm4 = &rs->pm4;
843 unsigned tmp, i;
844 float psize_min, psize_max;
845
846 if (!rs) {
847 return NULL;
848 }
849
850 rs->scissor_enable = state->scissor;
851 rs->clip_halfz = state->clip_halfz;
852 rs->two_side = state->light_twoside;
853 rs->multisample_enable = state->multisample;
854 rs->force_persample_interp = state->force_persample_interp;
855 rs->clip_plane_enable = state->clip_plane_enable;
856 rs->half_pixel_center = state->half_pixel_center;
857 rs->line_stipple_enable = state->line_stipple_enable;
858 rs->poly_stipple_enable = state->poly_stipple_enable;
859 rs->line_smooth = state->line_smooth;
860 rs->line_width = state->line_width;
861 rs->poly_smooth = state->poly_smooth;
862 rs->uses_poly_offset = state->offset_point || state->offset_line ||
863 state->offset_tri;
864 rs->clamp_fragment_color = state->clamp_fragment_color;
865 rs->clamp_vertex_color = state->clamp_vertex_color;
866 rs->flatshade = state->flatshade;
867 rs->sprite_coord_enable = state->sprite_coord_enable;
868 rs->rasterizer_discard = state->rasterizer_discard;
869 rs->pa_sc_line_stipple = state->line_stipple_enable ?
870 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
871 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
872 rs->pa_cl_clip_cntl =
873 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
874 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
875 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
876 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
877 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
878
879 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
880 S_0286D4_FLAT_SHADE_ENA(1) |
881 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
882 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
883 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
884 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
885 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
886 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
887
888 /* point size 12.4 fixed point */
889 tmp = (unsigned)(state->point_size * 8.0);
890 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
891
892 if (state->point_size_per_vertex) {
893 psize_min = util_get_min_point_size(state);
894 psize_max = 8192;
895 } else {
896 /* Force the point size to be as if the vertex output was disabled. */
897 psize_min = state->point_size;
898 psize_max = state->point_size;
899 }
900 rs->max_point_size = psize_max;
901
902 /* Divide by two, because 0.5 = 1 pixel. */
903 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
904 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
905 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
906
907 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
908 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
909 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
910 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
911 S_028A48_MSAA_ENABLE(state->multisample ||
912 state->poly_smooth ||
913 state->line_smooth) |
914 S_028A48_VPORT_SCISSOR_ENABLE(1) |
915 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
916
917 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
918 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
919 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
920 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
921 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
922 S_028814_FACE(!state->front_ccw) |
923 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
924 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
925 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
926 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
927 state->fill_back != PIPE_POLYGON_MODE_FILL) |
928 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
929 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
930
931 if (!rs->uses_poly_offset)
932 return rs;
933
934 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
935 if (!rs->pm4_poly_offset) {
936 FREE(rs);
937 return NULL;
938 }
939
940 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
941 for (i = 0; i < 3; i++) {
942 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
943 float offset_units = state->offset_units;
944 float offset_scale = state->offset_scale * 16.0f;
945 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
946
947 if (!state->offset_units_unscaled) {
948 switch (i) {
949 case 0: /* 16-bit zbuffer */
950 offset_units *= 4.0f;
951 pa_su_poly_offset_db_fmt_cntl =
952 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
953 break;
954 case 1: /* 24-bit zbuffer */
955 offset_units *= 2.0f;
956 pa_su_poly_offset_db_fmt_cntl =
957 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
958 break;
959 case 2: /* 32-bit zbuffer */
960 offset_units *= 1.0f;
961 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
962 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
963 break;
964 }
965 }
966
967 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
968 fui(offset_scale));
969 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
970 fui(offset_units));
971 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
972 fui(offset_scale));
973 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
974 fui(offset_units));
975 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
976 pa_su_poly_offset_db_fmt_cntl);
977 }
978
979 return rs;
980 }
981
982 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
983 {
984 struct si_context *sctx = (struct si_context *)ctx;
985 struct si_state_rasterizer *old_rs =
986 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
987 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
988
989 if (!state)
990 return;
991
992 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
993 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
994
995 /* Update the small primitive filter workaround if necessary. */
996 if (sctx->screen->has_msaa_sample_loc_bug &&
997 sctx->framebuffer.nr_samples > 1)
998 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
999 }
1000
1001 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1002 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1003
1004 si_pm4_bind_state(sctx, rasterizer, rs);
1005 si_update_poly_offset_state(sctx);
1006
1007 if (!old_rs ||
1008 old_rs->scissor_enable != rs->scissor_enable) {
1009 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1010 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1011 }
1012
1013 if (!old_rs ||
1014 old_rs->line_width != rs->line_width ||
1015 old_rs->max_point_size != rs->max_point_size ||
1016 old_rs->half_pixel_center != rs->half_pixel_center)
1017 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1018
1019 if (!old_rs ||
1020 old_rs->clip_halfz != rs->clip_halfz) {
1021 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1022 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1023 }
1024
1025 if (!old_rs ||
1026 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1027 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1028 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1029
1030 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1031 rs->line_stipple_enable;
1032
1033 if (!old_rs ||
1034 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1035 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1036 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1037 old_rs->flatshade != rs->flatshade ||
1038 old_rs->two_side != rs->two_side ||
1039 old_rs->multisample_enable != rs->multisample_enable ||
1040 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1041 old_rs->poly_smooth != rs->poly_smooth ||
1042 old_rs->line_smooth != rs->line_smooth ||
1043 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1044 old_rs->force_persample_interp != rs->force_persample_interp)
1045 sctx->do_update_shaders = true;
1046 }
1047
1048 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1049 {
1050 struct si_context *sctx = (struct si_context *)ctx;
1051 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1052
1053 if (sctx->queued.named.rasterizer == state)
1054 si_pm4_bind_state(sctx, poly_offset, NULL);
1055
1056 FREE(rs->pm4_poly_offset);
1057 si_pm4_delete_state(sctx, rasterizer, rs);
1058 }
1059
1060 /*
1061 * infeered state between dsa and stencil ref
1062 */
1063 static void si_emit_stencil_ref(struct si_context *sctx)
1064 {
1065 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1066 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1067 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1068
1069 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1070 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1071 S_028430_STENCILMASK(dsa->valuemask[0]) |
1072 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1073 S_028430_STENCILOPVAL(1));
1074 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1075 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1076 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1077 S_028434_STENCILOPVAL_BF(1));
1078 }
1079
1080 static void si_set_stencil_ref(struct pipe_context *ctx,
1081 const struct pipe_stencil_ref *state)
1082 {
1083 struct si_context *sctx = (struct si_context *)ctx;
1084
1085 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1086 return;
1087
1088 sctx->stencil_ref.state = *state;
1089 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1090 }
1091
1092
1093 /*
1094 * DSA
1095 */
1096
1097 static uint32_t si_translate_stencil_op(int s_op)
1098 {
1099 switch (s_op) {
1100 case PIPE_STENCIL_OP_KEEP:
1101 return V_02842C_STENCIL_KEEP;
1102 case PIPE_STENCIL_OP_ZERO:
1103 return V_02842C_STENCIL_ZERO;
1104 case PIPE_STENCIL_OP_REPLACE:
1105 return V_02842C_STENCIL_REPLACE_TEST;
1106 case PIPE_STENCIL_OP_INCR:
1107 return V_02842C_STENCIL_ADD_CLAMP;
1108 case PIPE_STENCIL_OP_DECR:
1109 return V_02842C_STENCIL_SUB_CLAMP;
1110 case PIPE_STENCIL_OP_INCR_WRAP:
1111 return V_02842C_STENCIL_ADD_WRAP;
1112 case PIPE_STENCIL_OP_DECR_WRAP:
1113 return V_02842C_STENCIL_SUB_WRAP;
1114 case PIPE_STENCIL_OP_INVERT:
1115 return V_02842C_STENCIL_INVERT;
1116 default:
1117 PRINT_ERR("Unknown stencil op %d", s_op);
1118 assert(0);
1119 break;
1120 }
1121 return 0;
1122 }
1123
1124 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1125 {
1126 return s->enabled && s->writemask &&
1127 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1128 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1129 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1130 }
1131
1132 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1133 {
1134 /* REPLACE is normally order invariant, except when the stencil
1135 * reference value is written by the fragment shader. Tracking this
1136 * interaction does not seem worth the effort, so be conservative. */
1137 return op != PIPE_STENCIL_OP_INCR &&
1138 op != PIPE_STENCIL_OP_DECR &&
1139 op != PIPE_STENCIL_OP_REPLACE;
1140 }
1141
1142 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1143 * invariant in the sense that the set of passing fragments as well as the
1144 * final stencil buffer result does not depend on the order of fragments. */
1145 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1146 {
1147 return !state->enabled || !state->writemask ||
1148 /* The following assumes that Z writes are disabled. */
1149 (state->func == PIPE_FUNC_ALWAYS &&
1150 si_order_invariant_stencil_op(state->zpass_op) &&
1151 si_order_invariant_stencil_op(state->zfail_op)) ||
1152 (state->func == PIPE_FUNC_NEVER &&
1153 si_order_invariant_stencil_op(state->fail_op));
1154 }
1155
1156 static void *si_create_dsa_state(struct pipe_context *ctx,
1157 const struct pipe_depth_stencil_alpha_state *state)
1158 {
1159 struct si_context *sctx = (struct si_context *)ctx;
1160 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1161 struct si_pm4_state *pm4 = &dsa->pm4;
1162 unsigned db_depth_control;
1163 uint32_t db_stencil_control = 0;
1164
1165 if (!dsa) {
1166 return NULL;
1167 }
1168
1169 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1170 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1171 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1172 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1173
1174 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1175 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1176 S_028800_ZFUNC(state->depth.func) |
1177 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1178
1179 /* stencil */
1180 if (state->stencil[0].enabled) {
1181 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1182 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1183 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1184 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1185 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1186
1187 if (state->stencil[1].enabled) {
1188 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1189 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1190 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1191 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1192 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1193 }
1194 }
1195
1196 /* alpha */
1197 if (state->alpha.enabled) {
1198 dsa->alpha_func = state->alpha.func;
1199
1200 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1201 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1202 } else {
1203 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1204 }
1205
1206 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1207 if (state->stencil[0].enabled)
1208 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1209 if (state->depth.bounds_test) {
1210 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1211 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1212 }
1213
1214 dsa->depth_enabled = state->depth.enabled;
1215 dsa->depth_write_enabled = state->depth.enabled &&
1216 state->depth.writemask;
1217 dsa->stencil_enabled = state->stencil[0].enabled;
1218 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1219 (si_dsa_writes_stencil(&state->stencil[0]) ||
1220 si_dsa_writes_stencil(&state->stencil[1]));
1221 dsa->db_can_write = dsa->depth_write_enabled ||
1222 dsa->stencil_write_enabled;
1223
1224 bool zfunc_is_ordered =
1225 state->depth.func == PIPE_FUNC_NEVER ||
1226 state->depth.func == PIPE_FUNC_LESS ||
1227 state->depth.func == PIPE_FUNC_LEQUAL ||
1228 state->depth.func == PIPE_FUNC_GREATER ||
1229 state->depth.func == PIPE_FUNC_GEQUAL;
1230
1231 bool nozwrite_and_order_invariant_stencil =
1232 !dsa->db_can_write ||
1233 (!dsa->depth_write_enabled &&
1234 si_order_invariant_stencil_state(&state->stencil[0]) &&
1235 si_order_invariant_stencil_state(&state->stencil[1]));
1236
1237 dsa->order_invariance[1].zs =
1238 nozwrite_and_order_invariant_stencil ||
1239 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1240 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1241
1242 dsa->order_invariance[1].pass_set =
1243 nozwrite_and_order_invariant_stencil ||
1244 (!dsa->stencil_write_enabled &&
1245 (state->depth.func == PIPE_FUNC_ALWAYS ||
1246 state->depth.func == PIPE_FUNC_NEVER));
1247 dsa->order_invariance[0].pass_set =
1248 !dsa->depth_write_enabled ||
1249 (state->depth.func == PIPE_FUNC_ALWAYS ||
1250 state->depth.func == PIPE_FUNC_NEVER);
1251
1252 dsa->order_invariance[1].pass_last =
1253 sctx->screen->assume_no_z_fights &&
1254 !dsa->stencil_write_enabled &&
1255 dsa->depth_write_enabled && zfunc_is_ordered;
1256 dsa->order_invariance[0].pass_last =
1257 sctx->screen->assume_no_z_fights &&
1258 dsa->depth_write_enabled && zfunc_is_ordered;
1259
1260 return dsa;
1261 }
1262
1263 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1264 {
1265 struct si_context *sctx = (struct si_context *)ctx;
1266 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1267 struct si_state_dsa *dsa = state;
1268
1269 if (!state)
1270 return;
1271
1272 si_pm4_bind_state(sctx, dsa, dsa);
1273
1274 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1275 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1276 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1277 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1278 }
1279
1280 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1281 sctx->do_update_shaders = true;
1282
1283 if (sctx->screen->dpbb_allowed &&
1284 (!old_dsa ||
1285 (old_dsa->depth_enabled != dsa->depth_enabled ||
1286 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1287 old_dsa->db_can_write != dsa->db_can_write)))
1288 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1289
1290 if (sctx->screen->has_out_of_order_rast &&
1291 (!old_dsa ||
1292 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1293 sizeof(old_dsa->order_invariance))))
1294 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1295 }
1296
1297 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1298 {
1299 struct si_context *sctx = (struct si_context *)ctx;
1300 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1301 }
1302
1303 static void *si_create_db_flush_dsa(struct si_context *sctx)
1304 {
1305 struct pipe_depth_stencil_alpha_state dsa = {};
1306
1307 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1308 }
1309
1310 /* DB RENDER STATE */
1311
1312 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1313 {
1314 struct si_context *sctx = (struct si_context*)ctx;
1315
1316 /* Pipeline stat & streamout queries. */
1317 if (enable) {
1318 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1319 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1320 } else {
1321 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1322 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1323 }
1324
1325 /* Occlusion queries. */
1326 if (sctx->occlusion_queries_disabled != !enable) {
1327 sctx->occlusion_queries_disabled = !enable;
1328 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1329 }
1330 }
1331
1332 void si_set_occlusion_query_state(struct si_context *sctx,
1333 bool old_perfect_enable)
1334 {
1335 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1336
1337 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1338
1339 if (perfect_enable != old_perfect_enable)
1340 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1341 }
1342
1343 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1344 {
1345 st->saved_compute = sctx->cs_shader_state.program;
1346
1347 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1348 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1349 }
1350
1351 static void si_emit_db_render_state(struct si_context *sctx)
1352 {
1353 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1354 unsigned db_shader_control, db_render_control, db_count_control;
1355
1356 /* DB_RENDER_CONTROL */
1357 if (sctx->dbcb_depth_copy_enabled ||
1358 sctx->dbcb_stencil_copy_enabled) {
1359 db_render_control =
1360 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1361 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1362 S_028000_COPY_CENTROID(1) |
1363 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1364 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1365 db_render_control =
1366 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1367 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1368 } else {
1369 db_render_control =
1370 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1371 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1372 }
1373
1374 /* DB_COUNT_CONTROL (occlusion queries) */
1375 if (sctx->num_occlusion_queries > 0 &&
1376 !sctx->occlusion_queries_disabled) {
1377 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1378
1379 if (sctx->chip_class >= CIK) {
1380 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1381
1382 /* Stoney doesn't increment occlusion query counters
1383 * if the sample rate is 16x. Use 8x sample rate instead.
1384 */
1385 if (sctx->family == CHIP_STONEY)
1386 log_sample_rate = MIN2(log_sample_rate, 3);
1387
1388 db_count_control =
1389 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1390 S_028004_SAMPLE_RATE(log_sample_rate) |
1391 S_028004_ZPASS_ENABLE(1) |
1392 S_028004_SLICE_EVEN_ENABLE(1) |
1393 S_028004_SLICE_ODD_ENABLE(1);
1394 } else {
1395 db_count_control =
1396 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1397 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1398 }
1399 } else {
1400 /* Disable occlusion queries. */
1401 if (sctx->chip_class >= CIK) {
1402 db_count_control = 0;
1403 } else {
1404 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1405 }
1406 }
1407
1408 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1409 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1410 db_count_control);
1411
1412 /* DB_RENDER_OVERRIDE2 */
1413 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1414 SI_TRACKED_DB_RENDER_OVERRIDE2,
1415 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1416 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1417 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1418
1419 db_shader_control = sctx->ps_db_shader_control;
1420
1421 /* Bug workaround for smoothing (overrasterization) on SI. */
1422 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1423 db_shader_control &= C_02880C_Z_ORDER;
1424 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1425 }
1426
1427 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1428 if (!rs->multisample_enable)
1429 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1430
1431 if (sctx->screen->has_rbplus &&
1432 !sctx->screen->rbplus_allowed)
1433 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1434
1435 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1436 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1437 }
1438
1439 /*
1440 * format translation
1441 */
1442 static uint32_t si_translate_colorformat(enum pipe_format format)
1443 {
1444 const struct util_format_description *desc = util_format_description(format);
1445 if (!desc)
1446 return V_028C70_COLOR_INVALID;
1447
1448 #define HAS_SIZE(x,y,z,w) \
1449 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1450 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1451
1452 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1453 return V_028C70_COLOR_10_11_11;
1454
1455 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1456 return V_028C70_COLOR_INVALID;
1457
1458 /* hw cannot support mixed formats (except depth/stencil, since
1459 * stencil is not written to). */
1460 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1461 return V_028C70_COLOR_INVALID;
1462
1463 switch (desc->nr_channels) {
1464 case 1:
1465 switch (desc->channel[0].size) {
1466 case 8:
1467 return V_028C70_COLOR_8;
1468 case 16:
1469 return V_028C70_COLOR_16;
1470 case 32:
1471 return V_028C70_COLOR_32;
1472 }
1473 break;
1474 case 2:
1475 if (desc->channel[0].size == desc->channel[1].size) {
1476 switch (desc->channel[0].size) {
1477 case 8:
1478 return V_028C70_COLOR_8_8;
1479 case 16:
1480 return V_028C70_COLOR_16_16;
1481 case 32:
1482 return V_028C70_COLOR_32_32;
1483 }
1484 } else if (HAS_SIZE(8,24,0,0)) {
1485 return V_028C70_COLOR_24_8;
1486 } else if (HAS_SIZE(24,8,0,0)) {
1487 return V_028C70_COLOR_8_24;
1488 }
1489 break;
1490 case 3:
1491 if (HAS_SIZE(5,6,5,0)) {
1492 return V_028C70_COLOR_5_6_5;
1493 } else if (HAS_SIZE(32,8,24,0)) {
1494 return V_028C70_COLOR_X24_8_32_FLOAT;
1495 }
1496 break;
1497 case 4:
1498 if (desc->channel[0].size == desc->channel[1].size &&
1499 desc->channel[0].size == desc->channel[2].size &&
1500 desc->channel[0].size == desc->channel[3].size) {
1501 switch (desc->channel[0].size) {
1502 case 4:
1503 return V_028C70_COLOR_4_4_4_4;
1504 case 8:
1505 return V_028C70_COLOR_8_8_8_8;
1506 case 16:
1507 return V_028C70_COLOR_16_16_16_16;
1508 case 32:
1509 return V_028C70_COLOR_32_32_32_32;
1510 }
1511 } else if (HAS_SIZE(5,5,5,1)) {
1512 return V_028C70_COLOR_1_5_5_5;
1513 } else if (HAS_SIZE(1,5,5,5)) {
1514 return V_028C70_COLOR_5_5_5_1;
1515 } else if (HAS_SIZE(10,10,10,2)) {
1516 return V_028C70_COLOR_2_10_10_10;
1517 }
1518 break;
1519 }
1520 return V_028C70_COLOR_INVALID;
1521 }
1522
1523 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1524 {
1525 if (SI_BIG_ENDIAN) {
1526 switch(colorformat) {
1527 /* 8-bit buffers. */
1528 case V_028C70_COLOR_8:
1529 return V_028C70_ENDIAN_NONE;
1530
1531 /* 16-bit buffers. */
1532 case V_028C70_COLOR_5_6_5:
1533 case V_028C70_COLOR_1_5_5_5:
1534 case V_028C70_COLOR_4_4_4_4:
1535 case V_028C70_COLOR_16:
1536 case V_028C70_COLOR_8_8:
1537 return V_028C70_ENDIAN_8IN16;
1538
1539 /* 32-bit buffers. */
1540 case V_028C70_COLOR_8_8_8_8:
1541 case V_028C70_COLOR_2_10_10_10:
1542 case V_028C70_COLOR_8_24:
1543 case V_028C70_COLOR_24_8:
1544 case V_028C70_COLOR_16_16:
1545 return V_028C70_ENDIAN_8IN32;
1546
1547 /* 64-bit buffers. */
1548 case V_028C70_COLOR_16_16_16_16:
1549 return V_028C70_ENDIAN_8IN16;
1550
1551 case V_028C70_COLOR_32_32:
1552 return V_028C70_ENDIAN_8IN32;
1553
1554 /* 128-bit buffers. */
1555 case V_028C70_COLOR_32_32_32_32:
1556 return V_028C70_ENDIAN_8IN32;
1557 default:
1558 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1559 }
1560 } else {
1561 return V_028C70_ENDIAN_NONE;
1562 }
1563 }
1564
1565 static uint32_t si_translate_dbformat(enum pipe_format format)
1566 {
1567 switch (format) {
1568 case PIPE_FORMAT_Z16_UNORM:
1569 return V_028040_Z_16;
1570 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1571 case PIPE_FORMAT_X8Z24_UNORM:
1572 case PIPE_FORMAT_Z24X8_UNORM:
1573 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1574 return V_028040_Z_24; /* deprecated on SI */
1575 case PIPE_FORMAT_Z32_FLOAT:
1576 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1577 return V_028040_Z_32_FLOAT;
1578 default:
1579 return V_028040_Z_INVALID;
1580 }
1581 }
1582
1583 /*
1584 * Texture translation
1585 */
1586
1587 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1588 enum pipe_format format,
1589 const struct util_format_description *desc,
1590 int first_non_void)
1591 {
1592 struct si_screen *sscreen = (struct si_screen*)screen;
1593 bool uniform = true;
1594 int i;
1595
1596 /* Colorspace (return non-RGB formats directly). */
1597 switch (desc->colorspace) {
1598 /* Depth stencil formats */
1599 case UTIL_FORMAT_COLORSPACE_ZS:
1600 switch (format) {
1601 case PIPE_FORMAT_Z16_UNORM:
1602 return V_008F14_IMG_DATA_FORMAT_16;
1603 case PIPE_FORMAT_X24S8_UINT:
1604 case PIPE_FORMAT_S8X24_UINT:
1605 /*
1606 * Implemented as an 8_8_8_8 data format to fix texture
1607 * gathers in stencil sampling. This affects at least
1608 * GL45-CTS.texture_cube_map_array.sampling on VI.
1609 */
1610 if (sscreen->info.chip_class <= VI)
1611 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1612
1613 if (format == PIPE_FORMAT_X24S8_UINT)
1614 return V_008F14_IMG_DATA_FORMAT_8_24;
1615 else
1616 return V_008F14_IMG_DATA_FORMAT_24_8;
1617 case PIPE_FORMAT_Z24X8_UNORM:
1618 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1619 return V_008F14_IMG_DATA_FORMAT_8_24;
1620 case PIPE_FORMAT_X8Z24_UNORM:
1621 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1622 return V_008F14_IMG_DATA_FORMAT_24_8;
1623 case PIPE_FORMAT_S8_UINT:
1624 return V_008F14_IMG_DATA_FORMAT_8;
1625 case PIPE_FORMAT_Z32_FLOAT:
1626 return V_008F14_IMG_DATA_FORMAT_32;
1627 case PIPE_FORMAT_X32_S8X24_UINT:
1628 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1629 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1630 default:
1631 goto out_unknown;
1632 }
1633
1634 case UTIL_FORMAT_COLORSPACE_YUV:
1635 goto out_unknown; /* TODO */
1636
1637 case UTIL_FORMAT_COLORSPACE_SRGB:
1638 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1639 goto out_unknown;
1640 break;
1641
1642 default:
1643 break;
1644 }
1645
1646 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1647 if (!sscreen->info.has_format_bc1_through_bc7)
1648 goto out_unknown;
1649
1650 switch (format) {
1651 case PIPE_FORMAT_RGTC1_SNORM:
1652 case PIPE_FORMAT_LATC1_SNORM:
1653 case PIPE_FORMAT_RGTC1_UNORM:
1654 case PIPE_FORMAT_LATC1_UNORM:
1655 return V_008F14_IMG_DATA_FORMAT_BC4;
1656 case PIPE_FORMAT_RGTC2_SNORM:
1657 case PIPE_FORMAT_LATC2_SNORM:
1658 case PIPE_FORMAT_RGTC2_UNORM:
1659 case PIPE_FORMAT_LATC2_UNORM:
1660 return V_008F14_IMG_DATA_FORMAT_BC5;
1661 default:
1662 goto out_unknown;
1663 }
1664 }
1665
1666 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1667 (sscreen->info.family == CHIP_STONEY ||
1668 sscreen->info.family == CHIP_VEGA10 ||
1669 sscreen->info.family == CHIP_RAVEN)) {
1670 switch (format) {
1671 case PIPE_FORMAT_ETC1_RGB8:
1672 case PIPE_FORMAT_ETC2_RGB8:
1673 case PIPE_FORMAT_ETC2_SRGB8:
1674 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1675 case PIPE_FORMAT_ETC2_RGB8A1:
1676 case PIPE_FORMAT_ETC2_SRGB8A1:
1677 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1678 case PIPE_FORMAT_ETC2_RGBA8:
1679 case PIPE_FORMAT_ETC2_SRGBA8:
1680 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1681 case PIPE_FORMAT_ETC2_R11_UNORM:
1682 case PIPE_FORMAT_ETC2_R11_SNORM:
1683 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1684 case PIPE_FORMAT_ETC2_RG11_UNORM:
1685 case PIPE_FORMAT_ETC2_RG11_SNORM:
1686 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1687 default:
1688 goto out_unknown;
1689 }
1690 }
1691
1692 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1693 if (!sscreen->info.has_format_bc1_through_bc7)
1694 goto out_unknown;
1695
1696 switch (format) {
1697 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1698 case PIPE_FORMAT_BPTC_SRGBA:
1699 return V_008F14_IMG_DATA_FORMAT_BC7;
1700 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1701 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1702 return V_008F14_IMG_DATA_FORMAT_BC6;
1703 default:
1704 goto out_unknown;
1705 }
1706 }
1707
1708 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1709 switch (format) {
1710 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1711 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1712 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1713 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1714 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1715 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1716 default:
1717 goto out_unknown;
1718 }
1719 }
1720
1721 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1722 if (!sscreen->info.has_format_bc1_through_bc7)
1723 goto out_unknown;
1724
1725 switch (format) {
1726 case PIPE_FORMAT_DXT1_RGB:
1727 case PIPE_FORMAT_DXT1_RGBA:
1728 case PIPE_FORMAT_DXT1_SRGB:
1729 case PIPE_FORMAT_DXT1_SRGBA:
1730 return V_008F14_IMG_DATA_FORMAT_BC1;
1731 case PIPE_FORMAT_DXT3_RGBA:
1732 case PIPE_FORMAT_DXT3_SRGBA:
1733 return V_008F14_IMG_DATA_FORMAT_BC2;
1734 case PIPE_FORMAT_DXT5_RGBA:
1735 case PIPE_FORMAT_DXT5_SRGBA:
1736 return V_008F14_IMG_DATA_FORMAT_BC3;
1737 default:
1738 goto out_unknown;
1739 }
1740 }
1741
1742 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1743 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1744 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1745 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1746 }
1747
1748 /* R8G8Bx_SNORM - TODO CxV8U8 */
1749
1750 /* hw cannot support mixed formats (except depth/stencil, since only
1751 * depth is read).*/
1752 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1753 goto out_unknown;
1754
1755 /* See whether the components are of the same size. */
1756 for (i = 1; i < desc->nr_channels; i++) {
1757 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1758 }
1759
1760 /* Non-uniform formats. */
1761 if (!uniform) {
1762 switch(desc->nr_channels) {
1763 case 3:
1764 if (desc->channel[0].size == 5 &&
1765 desc->channel[1].size == 6 &&
1766 desc->channel[2].size == 5) {
1767 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1768 }
1769 goto out_unknown;
1770 case 4:
1771 if (desc->channel[0].size == 5 &&
1772 desc->channel[1].size == 5 &&
1773 desc->channel[2].size == 5 &&
1774 desc->channel[3].size == 1) {
1775 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1776 }
1777 if (desc->channel[0].size == 1 &&
1778 desc->channel[1].size == 5 &&
1779 desc->channel[2].size == 5 &&
1780 desc->channel[3].size == 5) {
1781 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1782 }
1783 if (desc->channel[0].size == 10 &&
1784 desc->channel[1].size == 10 &&
1785 desc->channel[2].size == 10 &&
1786 desc->channel[3].size == 2) {
1787 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1788 }
1789 goto out_unknown;
1790 }
1791 goto out_unknown;
1792 }
1793
1794 if (first_non_void < 0 || first_non_void > 3)
1795 goto out_unknown;
1796
1797 /* uniform formats */
1798 switch (desc->channel[first_non_void].size) {
1799 case 4:
1800 switch (desc->nr_channels) {
1801 #if 0 /* Not supported for render targets */
1802 case 2:
1803 return V_008F14_IMG_DATA_FORMAT_4_4;
1804 #endif
1805 case 4:
1806 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1807 }
1808 break;
1809 case 8:
1810 switch (desc->nr_channels) {
1811 case 1:
1812 return V_008F14_IMG_DATA_FORMAT_8;
1813 case 2:
1814 return V_008F14_IMG_DATA_FORMAT_8_8;
1815 case 4:
1816 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1817 }
1818 break;
1819 case 16:
1820 switch (desc->nr_channels) {
1821 case 1:
1822 return V_008F14_IMG_DATA_FORMAT_16;
1823 case 2:
1824 return V_008F14_IMG_DATA_FORMAT_16_16;
1825 case 4:
1826 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1827 }
1828 break;
1829 case 32:
1830 switch (desc->nr_channels) {
1831 case 1:
1832 return V_008F14_IMG_DATA_FORMAT_32;
1833 case 2:
1834 return V_008F14_IMG_DATA_FORMAT_32_32;
1835 #if 0 /* Not supported for render targets */
1836 case 3:
1837 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1838 #endif
1839 case 4:
1840 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1841 }
1842 }
1843
1844 out_unknown:
1845 return ~0;
1846 }
1847
1848 static unsigned si_tex_wrap(unsigned wrap)
1849 {
1850 switch (wrap) {
1851 default:
1852 case PIPE_TEX_WRAP_REPEAT:
1853 return V_008F30_SQ_TEX_WRAP;
1854 case PIPE_TEX_WRAP_CLAMP:
1855 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1856 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1857 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1858 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1859 return V_008F30_SQ_TEX_CLAMP_BORDER;
1860 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1861 return V_008F30_SQ_TEX_MIRROR;
1862 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1863 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1864 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1865 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1866 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1867 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1868 }
1869 }
1870
1871 static unsigned si_tex_mipfilter(unsigned filter)
1872 {
1873 switch (filter) {
1874 case PIPE_TEX_MIPFILTER_NEAREST:
1875 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1876 case PIPE_TEX_MIPFILTER_LINEAR:
1877 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1878 default:
1879 case PIPE_TEX_MIPFILTER_NONE:
1880 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1881 }
1882 }
1883
1884 static unsigned si_tex_compare(unsigned compare)
1885 {
1886 switch (compare) {
1887 default:
1888 case PIPE_FUNC_NEVER:
1889 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1890 case PIPE_FUNC_LESS:
1891 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1892 case PIPE_FUNC_EQUAL:
1893 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1894 case PIPE_FUNC_LEQUAL:
1895 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1896 case PIPE_FUNC_GREATER:
1897 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1898 case PIPE_FUNC_NOTEQUAL:
1899 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1900 case PIPE_FUNC_GEQUAL:
1901 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1902 case PIPE_FUNC_ALWAYS:
1903 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1904 }
1905 }
1906
1907 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1908 unsigned view_target, unsigned nr_samples)
1909 {
1910 unsigned res_target = tex->buffer.b.b.target;
1911
1912 if (view_target == PIPE_TEXTURE_CUBE ||
1913 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1914 res_target = view_target;
1915 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1916 else if (res_target == PIPE_TEXTURE_CUBE ||
1917 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1918 res_target = PIPE_TEXTURE_2D_ARRAY;
1919
1920 /* GFX9 allocates 1D textures as 2D. */
1921 if ((res_target == PIPE_TEXTURE_1D ||
1922 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1923 sscreen->info.chip_class >= GFX9 &&
1924 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1925 if (res_target == PIPE_TEXTURE_1D)
1926 res_target = PIPE_TEXTURE_2D;
1927 else
1928 res_target = PIPE_TEXTURE_2D_ARRAY;
1929 }
1930
1931 switch (res_target) {
1932 default:
1933 case PIPE_TEXTURE_1D:
1934 return V_008F1C_SQ_RSRC_IMG_1D;
1935 case PIPE_TEXTURE_1D_ARRAY:
1936 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1937 case PIPE_TEXTURE_2D:
1938 case PIPE_TEXTURE_RECT:
1939 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1940 V_008F1C_SQ_RSRC_IMG_2D;
1941 case PIPE_TEXTURE_2D_ARRAY:
1942 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1943 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1944 case PIPE_TEXTURE_3D:
1945 return V_008F1C_SQ_RSRC_IMG_3D;
1946 case PIPE_TEXTURE_CUBE:
1947 case PIPE_TEXTURE_CUBE_ARRAY:
1948 return V_008F1C_SQ_RSRC_IMG_CUBE;
1949 }
1950 }
1951
1952 /*
1953 * Format support testing
1954 */
1955
1956 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1957 {
1958 const struct util_format_description *desc = util_format_description(format);
1959 if (!desc)
1960 return false;
1961
1962 return si_translate_texformat(screen, format, desc,
1963 util_format_get_first_non_void_channel(format)) != ~0U;
1964 }
1965
1966 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1967 const struct util_format_description *desc,
1968 int first_non_void)
1969 {
1970 int i;
1971
1972 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1973 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1974
1975 assert(first_non_void >= 0);
1976
1977 if (desc->nr_channels == 4 &&
1978 desc->channel[0].size == 10 &&
1979 desc->channel[1].size == 10 &&
1980 desc->channel[2].size == 10 &&
1981 desc->channel[3].size == 2)
1982 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1983
1984 /* See whether the components are of the same size. */
1985 for (i = 0; i < desc->nr_channels; i++) {
1986 if (desc->channel[first_non_void].size != desc->channel[i].size)
1987 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1988 }
1989
1990 switch (desc->channel[first_non_void].size) {
1991 case 8:
1992 switch (desc->nr_channels) {
1993 case 1:
1994 case 3: /* 3 loads */
1995 return V_008F0C_BUF_DATA_FORMAT_8;
1996 case 2:
1997 return V_008F0C_BUF_DATA_FORMAT_8_8;
1998 case 4:
1999 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2000 }
2001 break;
2002 case 16:
2003 switch (desc->nr_channels) {
2004 case 1:
2005 case 3: /* 3 loads */
2006 return V_008F0C_BUF_DATA_FORMAT_16;
2007 case 2:
2008 return V_008F0C_BUF_DATA_FORMAT_16_16;
2009 case 4:
2010 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2011 }
2012 break;
2013 case 32:
2014 switch (desc->nr_channels) {
2015 case 1:
2016 return V_008F0C_BUF_DATA_FORMAT_32;
2017 case 2:
2018 return V_008F0C_BUF_DATA_FORMAT_32_32;
2019 case 3:
2020 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2021 case 4:
2022 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2023 }
2024 break;
2025 case 64:
2026 /* Legacy double formats. */
2027 switch (desc->nr_channels) {
2028 case 1: /* 1 load */
2029 return V_008F0C_BUF_DATA_FORMAT_32_32;
2030 case 2: /* 1 load */
2031 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2032 case 3: /* 3 loads */
2033 return V_008F0C_BUF_DATA_FORMAT_32_32;
2034 case 4: /* 2 loads */
2035 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2036 }
2037 break;
2038 }
2039
2040 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2041 }
2042
2043 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2044 const struct util_format_description *desc,
2045 int first_non_void)
2046 {
2047 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2048 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2049
2050 assert(first_non_void >= 0);
2051
2052 switch (desc->channel[first_non_void].type) {
2053 case UTIL_FORMAT_TYPE_SIGNED:
2054 case UTIL_FORMAT_TYPE_FIXED:
2055 if (desc->channel[first_non_void].size >= 32 ||
2056 desc->channel[first_non_void].pure_integer)
2057 return V_008F0C_BUF_NUM_FORMAT_SINT;
2058 else if (desc->channel[first_non_void].normalized)
2059 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2060 else
2061 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2062 break;
2063 case UTIL_FORMAT_TYPE_UNSIGNED:
2064 if (desc->channel[first_non_void].size >= 32 ||
2065 desc->channel[first_non_void].pure_integer)
2066 return V_008F0C_BUF_NUM_FORMAT_UINT;
2067 else if (desc->channel[first_non_void].normalized)
2068 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2069 else
2070 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2071 break;
2072 case UTIL_FORMAT_TYPE_FLOAT:
2073 default:
2074 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2075 }
2076 }
2077
2078 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2079 enum pipe_format format,
2080 unsigned usage)
2081 {
2082 const struct util_format_description *desc;
2083 int first_non_void;
2084 unsigned data_format;
2085
2086 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2087 PIPE_BIND_SAMPLER_VIEW |
2088 PIPE_BIND_VERTEX_BUFFER)) == 0);
2089
2090 desc = util_format_description(format);
2091 if (!desc)
2092 return 0;
2093
2094 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2095 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2096 * for read-only access (with caveats surrounding bounds checks), but
2097 * obviously fails for write access which we have to implement for
2098 * shader images. Luckily, OpenGL doesn't expect this to be supported
2099 * anyway, and so the only impact is on PBO uploads / downloads, which
2100 * shouldn't be expected to be fast for GL_RGB anyway.
2101 */
2102 if (desc->block.bits == 3 * 8 ||
2103 desc->block.bits == 3 * 16) {
2104 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2105 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2106 if (!usage)
2107 return 0;
2108 }
2109 }
2110
2111 first_non_void = util_format_get_first_non_void_channel(format);
2112 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2113 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2114 return 0;
2115
2116 return usage;
2117 }
2118
2119 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2120 {
2121 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2122 si_translate_colorswap(format, false) != ~0U;
2123 }
2124
2125 static bool si_is_zs_format_supported(enum pipe_format format)
2126 {
2127 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2128 }
2129
2130 static boolean si_is_format_supported(struct pipe_screen *screen,
2131 enum pipe_format format,
2132 enum pipe_texture_target target,
2133 unsigned sample_count,
2134 unsigned storage_sample_count,
2135 unsigned usage)
2136 {
2137 struct si_screen *sscreen = (struct si_screen *)screen;
2138 unsigned retval = 0;
2139
2140 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2141 PRINT_ERR("r600: unsupported texture type %d\n", target);
2142 return false;
2143 }
2144
2145 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2146 return false;
2147
2148 if (sample_count > 1) {
2149 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2150 return false;
2151
2152 if (usage & PIPE_BIND_SHADER_IMAGE)
2153 return false;
2154
2155 /* Only power-of-two sample counts are supported. */
2156 if (!util_is_power_of_two_or_zero(sample_count) ||
2157 !util_is_power_of_two_or_zero(storage_sample_count))
2158 return false;
2159
2160 /* MSAA support without framebuffer attachments. */
2161 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2162 return true;
2163
2164 if (!sscreen->info.has_eqaa_surface_allocator ||
2165 util_format_is_depth_or_stencil(format)) {
2166 /* Color without EQAA or depth/stencil. */
2167 if (sample_count > 8 ||
2168 sample_count != storage_sample_count)
2169 return false;
2170 } else {
2171 /* Color with EQAA. */
2172 if (sample_count > 16 ||
2173 storage_sample_count > 8)
2174 return false;
2175 }
2176 }
2177
2178 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2179 PIPE_BIND_SHADER_IMAGE)) {
2180 if (target == PIPE_BUFFER) {
2181 retval |= si_is_vertex_format_supported(
2182 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2183 PIPE_BIND_SHADER_IMAGE));
2184 } else {
2185 if (si_is_sampler_format_supported(screen, format))
2186 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2187 PIPE_BIND_SHADER_IMAGE);
2188 }
2189 }
2190
2191 if ((usage & (PIPE_BIND_RENDER_TARGET |
2192 PIPE_BIND_DISPLAY_TARGET |
2193 PIPE_BIND_SCANOUT |
2194 PIPE_BIND_SHARED |
2195 PIPE_BIND_BLENDABLE)) &&
2196 si_is_colorbuffer_format_supported(format)) {
2197 retval |= usage &
2198 (PIPE_BIND_RENDER_TARGET |
2199 PIPE_BIND_DISPLAY_TARGET |
2200 PIPE_BIND_SCANOUT |
2201 PIPE_BIND_SHARED);
2202 if (!util_format_is_pure_integer(format) &&
2203 !util_format_is_depth_or_stencil(format))
2204 retval |= usage & PIPE_BIND_BLENDABLE;
2205 }
2206
2207 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2208 si_is_zs_format_supported(format)) {
2209 retval |= PIPE_BIND_DEPTH_STENCIL;
2210 }
2211
2212 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2213 retval |= si_is_vertex_format_supported(screen, format,
2214 PIPE_BIND_VERTEX_BUFFER);
2215 }
2216
2217 if ((usage & PIPE_BIND_LINEAR) &&
2218 !util_format_is_compressed(format) &&
2219 !(usage & PIPE_BIND_DEPTH_STENCIL))
2220 retval |= PIPE_BIND_LINEAR;
2221
2222 return retval == usage;
2223 }
2224
2225 /*
2226 * framebuffer handling
2227 */
2228
2229 static void si_choose_spi_color_formats(struct si_surface *surf,
2230 unsigned format, unsigned swap,
2231 unsigned ntype, bool is_depth)
2232 {
2233 /* Alpha is needed for alpha-to-coverage.
2234 * Blending may be with or without alpha.
2235 */
2236 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2237 unsigned alpha = 0; /* exports alpha, but may not support blending */
2238 unsigned blend = 0; /* supports blending, but may not export alpha */
2239 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2240
2241 /* Choose the SPI color formats. These are required values for RB+.
2242 * Other chips have multiple choices, though they are not necessarily better.
2243 */
2244 switch (format) {
2245 case V_028C70_COLOR_5_6_5:
2246 case V_028C70_COLOR_1_5_5_5:
2247 case V_028C70_COLOR_5_5_5_1:
2248 case V_028C70_COLOR_4_4_4_4:
2249 case V_028C70_COLOR_10_11_11:
2250 case V_028C70_COLOR_11_11_10:
2251 case V_028C70_COLOR_8:
2252 case V_028C70_COLOR_8_8:
2253 case V_028C70_COLOR_8_8_8_8:
2254 case V_028C70_COLOR_10_10_10_2:
2255 case V_028C70_COLOR_2_10_10_10:
2256 if (ntype == V_028C70_NUMBER_UINT)
2257 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2258 else if (ntype == V_028C70_NUMBER_SINT)
2259 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2260 else
2261 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2262 break;
2263
2264 case V_028C70_COLOR_16:
2265 case V_028C70_COLOR_16_16:
2266 case V_028C70_COLOR_16_16_16_16:
2267 if (ntype == V_028C70_NUMBER_UNORM ||
2268 ntype == V_028C70_NUMBER_SNORM) {
2269 /* UNORM16 and SNORM16 don't support blending */
2270 if (ntype == V_028C70_NUMBER_UNORM)
2271 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2272 else
2273 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2274
2275 /* Use 32 bits per channel for blending. */
2276 if (format == V_028C70_COLOR_16) {
2277 if (swap == V_028C70_SWAP_STD) { /* R */
2278 blend = V_028714_SPI_SHADER_32_R;
2279 blend_alpha = V_028714_SPI_SHADER_32_AR;
2280 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2281 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2282 else
2283 assert(0);
2284 } else if (format == V_028C70_COLOR_16_16) {
2285 if (swap == V_028C70_SWAP_STD) { /* RG */
2286 blend = V_028714_SPI_SHADER_32_GR;
2287 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2288 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2289 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2290 else
2291 assert(0);
2292 } else /* 16_16_16_16 */
2293 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2294 } else if (ntype == V_028C70_NUMBER_UINT)
2295 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2296 else if (ntype == V_028C70_NUMBER_SINT)
2297 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2298 else if (ntype == V_028C70_NUMBER_FLOAT)
2299 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2300 else
2301 assert(0);
2302 break;
2303
2304 case V_028C70_COLOR_32:
2305 if (swap == V_028C70_SWAP_STD) { /* R */
2306 blend = normal = V_028714_SPI_SHADER_32_R;
2307 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2308 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2309 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2310 else
2311 assert(0);
2312 break;
2313
2314 case V_028C70_COLOR_32_32:
2315 if (swap == V_028C70_SWAP_STD) { /* RG */
2316 blend = normal = V_028714_SPI_SHADER_32_GR;
2317 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2318 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2319 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2320 else
2321 assert(0);
2322 break;
2323
2324 case V_028C70_COLOR_32_32_32_32:
2325 case V_028C70_COLOR_8_24:
2326 case V_028C70_COLOR_24_8:
2327 case V_028C70_COLOR_X24_8_32_FLOAT:
2328 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2329 break;
2330
2331 default:
2332 assert(0);
2333 return;
2334 }
2335
2336 /* The DB->CB copy needs 32_ABGR. */
2337 if (is_depth)
2338 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2339
2340 surf->spi_shader_col_format = normal;
2341 surf->spi_shader_col_format_alpha = alpha;
2342 surf->spi_shader_col_format_blend = blend;
2343 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2344 }
2345
2346 static void si_initialize_color_surface(struct si_context *sctx,
2347 struct si_surface *surf)
2348 {
2349 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2350 unsigned color_info, color_attrib;
2351 unsigned format, swap, ntype, endian;
2352 const struct util_format_description *desc;
2353 int firstchan;
2354 unsigned blend_clamp = 0, blend_bypass = 0;
2355
2356 desc = util_format_description(surf->base.format);
2357 for (firstchan = 0; firstchan < 4; firstchan++) {
2358 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2359 break;
2360 }
2361 }
2362 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2363 ntype = V_028C70_NUMBER_FLOAT;
2364 } else {
2365 ntype = V_028C70_NUMBER_UNORM;
2366 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2367 ntype = V_028C70_NUMBER_SRGB;
2368 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2369 if (desc->channel[firstchan].pure_integer) {
2370 ntype = V_028C70_NUMBER_SINT;
2371 } else {
2372 assert(desc->channel[firstchan].normalized);
2373 ntype = V_028C70_NUMBER_SNORM;
2374 }
2375 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2376 if (desc->channel[firstchan].pure_integer) {
2377 ntype = V_028C70_NUMBER_UINT;
2378 } else {
2379 assert(desc->channel[firstchan].normalized);
2380 ntype = V_028C70_NUMBER_UNORM;
2381 }
2382 }
2383 }
2384
2385 format = si_translate_colorformat(surf->base.format);
2386 if (format == V_028C70_COLOR_INVALID) {
2387 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2388 }
2389 assert(format != V_028C70_COLOR_INVALID);
2390 swap = si_translate_colorswap(surf->base.format, false);
2391 endian = si_colorformat_endian_swap(format);
2392
2393 /* blend clamp should be set for all NORM/SRGB types */
2394 if (ntype == V_028C70_NUMBER_UNORM ||
2395 ntype == V_028C70_NUMBER_SNORM ||
2396 ntype == V_028C70_NUMBER_SRGB)
2397 blend_clamp = 1;
2398
2399 /* set blend bypass according to docs if SINT/UINT or
2400 8/24 COLOR variants */
2401 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2402 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2403 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2404 blend_clamp = 0;
2405 blend_bypass = 1;
2406 }
2407
2408 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2409 if (format == V_028C70_COLOR_8 ||
2410 format == V_028C70_COLOR_8_8 ||
2411 format == V_028C70_COLOR_8_8_8_8)
2412 surf->color_is_int8 = true;
2413 else if (format == V_028C70_COLOR_10_10_10_2 ||
2414 format == V_028C70_COLOR_2_10_10_10)
2415 surf->color_is_int10 = true;
2416 }
2417
2418 color_info = S_028C70_FORMAT(format) |
2419 S_028C70_COMP_SWAP(swap) |
2420 S_028C70_BLEND_CLAMP(blend_clamp) |
2421 S_028C70_BLEND_BYPASS(blend_bypass) |
2422 S_028C70_SIMPLE_FLOAT(1) |
2423 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2424 ntype != V_028C70_NUMBER_SNORM &&
2425 ntype != V_028C70_NUMBER_SRGB &&
2426 format != V_028C70_COLOR_8_24 &&
2427 format != V_028C70_COLOR_24_8) |
2428 S_028C70_NUMBER_TYPE(ntype) |
2429 S_028C70_ENDIAN(endian);
2430
2431 /* Intensity is implemented as Red, so treat it that way. */
2432 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2433 util_format_is_intensity(surf->base.format));
2434
2435 if (tex->buffer.b.b.nr_samples > 1) {
2436 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2437 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2438
2439 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2440 S_028C74_NUM_FRAGMENTS(log_fragments);
2441
2442 if (tex->surface.fmask_size) {
2443 color_info |= S_028C70_COMPRESSION(1);
2444 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2445
2446 if (sctx->chip_class == SI) {
2447 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2448 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2449 }
2450 }
2451 }
2452
2453 if (sctx->chip_class >= VI) {
2454 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2455 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2456
2457 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2458 64 for APU because all of our APUs to date use DIMMs which have
2459 a request granularity size of 64B while all other chips have a
2460 32B request size */
2461 if (!sctx->screen->info.has_dedicated_vram)
2462 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2463
2464 if (tex->buffer.b.b.nr_storage_samples > 1) {
2465 if (tex->surface.bpe == 1)
2466 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2467 else if (tex->surface.bpe == 2)
2468 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2469 }
2470
2471 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2472 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2473 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2474 }
2475
2476 /* This must be set for fast clear to work without FMASK. */
2477 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2478 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2479 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2480 }
2481
2482 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2483 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2484
2485 if (sctx->chip_class >= GFX9) {
2486 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2487
2488 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2489 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2490 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2491 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2492 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2493 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2494 }
2495
2496 surf->cb_color_view = color_view;
2497 surf->cb_color_info = color_info;
2498 surf->cb_color_attrib = color_attrib;
2499
2500 /* Determine pixel shader export format */
2501 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2502
2503 surf->color_initialized = true;
2504 }
2505
2506 static void si_init_depth_surface(struct si_context *sctx,
2507 struct si_surface *surf)
2508 {
2509 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2510 unsigned level = surf->base.u.tex.level;
2511 unsigned format, stencil_format;
2512 uint32_t z_info, s_info;
2513
2514 format = si_translate_dbformat(tex->db_render_format);
2515 stencil_format = tex->surface.has_stencil ?
2516 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2517
2518 assert(format != V_028040_Z_INVALID);
2519 if (format == V_028040_Z_INVALID)
2520 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2521
2522 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2523 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2524 surf->db_htile_data_base = 0;
2525 surf->db_htile_surface = 0;
2526
2527 if (sctx->chip_class >= GFX9) {
2528 assert(tex->surface.u.gfx9.surf_offset == 0);
2529 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2530 surf->db_stencil_base = (tex->buffer.gpu_address +
2531 tex->surface.u.gfx9.stencil_offset) >> 8;
2532 z_info = S_028038_FORMAT(format) |
2533 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2534 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2535 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2536 s_info = S_02803C_FORMAT(stencil_format) |
2537 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2538 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2539 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2540 surf->db_depth_view |= S_028008_MIPID(level);
2541 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2542 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2543
2544 if (si_htile_enabled(tex, level)) {
2545 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2546 S_028038_ALLOW_EXPCLEAR(1);
2547
2548 if (tex->tc_compatible_htile) {
2549 unsigned max_zplanes = 4;
2550
2551 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2552 tex->buffer.b.b.nr_samples > 1)
2553 max_zplanes = 2;
2554
2555 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2556 S_028038_ITERATE_FLUSH(1);
2557 s_info |= S_02803C_ITERATE_FLUSH(1);
2558 }
2559
2560 if (tex->surface.has_stencil) {
2561 /* Stencil buffer workaround ported from the SI-CI-VI code.
2562 * See that for explanation.
2563 */
2564 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2565 } else {
2566 /* Use all HTILE for depth if there's no stencil. */
2567 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2568 }
2569
2570 surf->db_htile_data_base = (tex->buffer.gpu_address +
2571 tex->htile_offset) >> 8;
2572 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2573 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2574 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2575 }
2576 } else {
2577 /* SI-CI-VI */
2578 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2579
2580 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2581
2582 surf->db_depth_base = (tex->buffer.gpu_address +
2583 tex->surface.u.legacy.level[level].offset) >> 8;
2584 surf->db_stencil_base = (tex->buffer.gpu_address +
2585 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2586
2587 z_info = S_028040_FORMAT(format) |
2588 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2589 s_info = S_028044_FORMAT(stencil_format);
2590 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2591
2592 if (sctx->chip_class >= CIK) {
2593 struct radeon_info *info = &sctx->screen->info;
2594 unsigned index = tex->surface.u.legacy.tiling_index[level];
2595 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2596 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2597 unsigned tile_mode = info->si_tile_mode_array[index];
2598 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2599 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2600
2601 surf->db_depth_info |=
2602 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2603 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2604 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2605 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2606 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2607 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2608 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2609 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2610 } else {
2611 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2612 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2613 tile_mode_index = si_tile_mode_index(tex, level, true);
2614 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2615 }
2616
2617 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2618 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2619 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2620 levelinfo->nblk_y) / 64 - 1);
2621
2622 if (si_htile_enabled(tex, level)) {
2623 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2624 S_028040_ALLOW_EXPCLEAR(1);
2625
2626 if (tex->surface.has_stencil) {
2627 /* Workaround: For a not yet understood reason, the
2628 * combination of MSAA, fast stencil clear and stencil
2629 * decompress messes with subsequent stencil buffer
2630 * uses. Problem was reproduced on Verde, Bonaire,
2631 * Tonga, and Carrizo.
2632 *
2633 * Disabling EXPCLEAR works around the problem.
2634 *
2635 * Check piglit's arb_texture_multisample-stencil-clear
2636 * test if you want to try changing this.
2637 */
2638 if (tex->buffer.b.b.nr_samples <= 1)
2639 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2640 } else if (!tex->tc_compatible_htile) {
2641 /* Use all of the htile_buffer for depth if there's no stencil.
2642 * This must not be set when TC-compatible HTILE is enabled
2643 * due to a hw bug.
2644 */
2645 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2646 }
2647
2648 surf->db_htile_data_base = (tex->buffer.gpu_address +
2649 tex->htile_offset) >> 8;
2650 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2651
2652 if (tex->tc_compatible_htile) {
2653 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2654
2655 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2656 if (tex->buffer.b.b.nr_samples <= 1)
2657 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2658 else if (tex->buffer.b.b.nr_samples <= 4)
2659 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2660 else
2661 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2662 }
2663 }
2664 }
2665
2666 surf->db_z_info = z_info;
2667 surf->db_stencil_info = s_info;
2668
2669 surf->depth_initialized = true;
2670 }
2671
2672 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2673 {
2674 if (sctx->decompression_enabled)
2675 return;
2676
2677 if (sctx->framebuffer.state.zsbuf) {
2678 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2679 struct si_texture *tex = (struct si_texture *)surf->texture;
2680
2681 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2682
2683 if (tex->surface.has_stencil)
2684 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2685 }
2686
2687 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2688 while (compressed_cb_mask) {
2689 unsigned i = u_bit_scan(&compressed_cb_mask);
2690 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2691 struct si_texture *tex = (struct si_texture*)surf->texture;
2692
2693 if (tex->surface.fmask_size)
2694 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2695 if (tex->dcc_gather_statistics)
2696 tex->separate_dcc_dirty = true;
2697 }
2698 }
2699
2700 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2701 {
2702 for (int i = 0; i < state->nr_cbufs; ++i) {
2703 struct si_surface *surf = NULL;
2704 struct si_texture *tex;
2705
2706 if (!state->cbufs[i])
2707 continue;
2708 surf = (struct si_surface*)state->cbufs[i];
2709 tex = (struct si_texture*)surf->base.texture;
2710
2711 p_atomic_dec(&tex->framebuffers_bound);
2712 }
2713 }
2714
2715 static void si_set_framebuffer_state(struct pipe_context *ctx,
2716 const struct pipe_framebuffer_state *state)
2717 {
2718 struct si_context *sctx = (struct si_context *)ctx;
2719 struct si_surface *surf = NULL;
2720 struct si_texture *tex;
2721 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2722 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2723 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2724 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2725 bool old_has_stencil =
2726 old_has_zsbuf &&
2727 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2728 bool unbound = false;
2729 int i;
2730
2731 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2732 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2733 * We could implement the full workaround here, but it's a useless case.
2734 */
2735 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2736 unreachable("the framebuffer shouldn't have zero area");
2737 return;
2738 }
2739
2740 si_update_fb_dirtiness_after_rendering(sctx);
2741
2742 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2743 if (!sctx->framebuffer.state.cbufs[i])
2744 continue;
2745
2746 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2747 if (tex->dcc_gather_statistics)
2748 vi_separate_dcc_stop_query(sctx, tex);
2749 }
2750
2751 /* Disable DCC if the formats are incompatible. */
2752 for (i = 0; i < state->nr_cbufs; i++) {
2753 if (!state->cbufs[i])
2754 continue;
2755
2756 surf = (struct si_surface*)state->cbufs[i];
2757 tex = (struct si_texture*)surf->base.texture;
2758
2759 if (!surf->dcc_incompatible)
2760 continue;
2761
2762 /* Since the DCC decompression calls back into set_framebuffer-
2763 * _state, we need to unbind the framebuffer, so that
2764 * vi_separate_dcc_stop_query isn't called twice with the same
2765 * color buffer.
2766 */
2767 if (!unbound) {
2768 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2769 unbound = true;
2770 }
2771
2772 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2773 if (!si_texture_disable_dcc(sctx, tex))
2774 si_decompress_dcc(sctx, tex);
2775
2776 surf->dcc_incompatible = false;
2777 }
2778
2779 /* Only flush TC when changing the framebuffer state, because
2780 * the only client not using TC that can change textures is
2781 * the framebuffer.
2782 *
2783 * Wait for compute shaders because of possible transitions:
2784 * - FB write -> shader read
2785 * - shader write -> FB read
2786 *
2787 * DB caches are flushed on demand (using si_decompress_textures).
2788 *
2789 * When MSAA is enabled, CB and TC caches are flushed on demand
2790 * (after FMASK decompression). Shader write -> FB read transitions
2791 * cannot happen for MSAA textures, because MSAA shader images are
2792 * not supported.
2793 *
2794 * Only flush and wait for CB if there is actually a bound color buffer.
2795 */
2796 if (sctx->framebuffer.uncompressed_cb_mask)
2797 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2798 sctx->framebuffer.CB_has_shader_readable_metadata);
2799
2800 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2801
2802 /* u_blitter doesn't invoke depth decompression when it does multiple
2803 * blits in a row, but the only case when it matters for DB is when
2804 * doing generate_mipmap. So here we flush DB manually between
2805 * individual generate_mipmap blits.
2806 * Note that lower mipmap levels aren't compressed.
2807 */
2808 if (sctx->generate_mipmap_for_depth) {
2809 si_make_DB_shader_coherent(sctx, 1, false,
2810 sctx->framebuffer.DB_has_shader_readable_metadata);
2811 } else if (sctx->chip_class == GFX9) {
2812 /* It appears that DB metadata "leaks" in a sequence of:
2813 * - depth clear
2814 * - DCC decompress for shader image writes (with DB disabled)
2815 * - render with DEPTH_BEFORE_SHADER=1
2816 * Flushing DB metadata works around the problem.
2817 */
2818 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2819 }
2820
2821 /* Take the maximum of the old and new count. If the new count is lower,
2822 * dirtying is needed to disable the unbound colorbuffers.
2823 */
2824 sctx->framebuffer.dirty_cbufs |=
2825 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2826 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2827
2828 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2829 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2830
2831 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2832 sctx->framebuffer.spi_shader_col_format = 0;
2833 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2834 sctx->framebuffer.spi_shader_col_format_blend = 0;
2835 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2836 sctx->framebuffer.color_is_int8 = 0;
2837 sctx->framebuffer.color_is_int10 = 0;
2838
2839 sctx->framebuffer.compressed_cb_mask = 0;
2840 sctx->framebuffer.uncompressed_cb_mask = 0;
2841 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2842 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2843 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2844 sctx->framebuffer.any_dst_linear = false;
2845 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2846 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2847
2848 for (i = 0; i < state->nr_cbufs; i++) {
2849 if (!state->cbufs[i])
2850 continue;
2851
2852 surf = (struct si_surface*)state->cbufs[i];
2853 tex = (struct si_texture*)surf->base.texture;
2854
2855 if (!surf->color_initialized) {
2856 si_initialize_color_surface(sctx, surf);
2857 }
2858
2859 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2860 sctx->framebuffer.spi_shader_col_format |=
2861 surf->spi_shader_col_format << (i * 4);
2862 sctx->framebuffer.spi_shader_col_format_alpha |=
2863 surf->spi_shader_col_format_alpha << (i * 4);
2864 sctx->framebuffer.spi_shader_col_format_blend |=
2865 surf->spi_shader_col_format_blend << (i * 4);
2866 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2867 surf->spi_shader_col_format_blend_alpha << (i * 4);
2868
2869 if (surf->color_is_int8)
2870 sctx->framebuffer.color_is_int8 |= 1 << i;
2871 if (surf->color_is_int10)
2872 sctx->framebuffer.color_is_int10 |= 1 << i;
2873
2874 if (tex->surface.fmask_size)
2875 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2876 else
2877 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2878
2879 /* Don't update nr_color_samples for non-AA buffers.
2880 * (e.g. destination of MSAA resolve)
2881 */
2882 if (tex->buffer.b.b.nr_samples >= 2 &&
2883 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2884 sctx->framebuffer.nr_color_samples =
2885 MIN2(sctx->framebuffer.nr_color_samples,
2886 tex->buffer.b.b.nr_storage_samples);
2887 sctx->framebuffer.nr_color_samples =
2888 MAX2(1, sctx->framebuffer.nr_color_samples);
2889 }
2890
2891 if (tex->surface.is_linear)
2892 sctx->framebuffer.any_dst_linear = true;
2893
2894 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2895 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2896
2897 si_context_add_resource_size(sctx, surf->base.texture);
2898
2899 p_atomic_inc(&tex->framebuffers_bound);
2900
2901 if (tex->dcc_gather_statistics) {
2902 /* Dirty tracking must be enabled for DCC usage analysis. */
2903 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2904 vi_separate_dcc_start_query(sctx, tex);
2905 }
2906 }
2907
2908 struct si_texture *zstex = NULL;
2909
2910 if (state->zsbuf) {
2911 surf = (struct si_surface*)state->zsbuf;
2912 zstex = (struct si_texture*)surf->base.texture;
2913
2914 if (!surf->depth_initialized) {
2915 si_init_depth_surface(sctx, surf);
2916 }
2917
2918 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2919 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2920
2921 si_context_add_resource_size(sctx, surf->base.texture);
2922 }
2923
2924 si_update_ps_colorbuf0_slot(sctx);
2925 si_update_poly_offset_state(sctx);
2926 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2927 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2928
2929 if (sctx->screen->dpbb_allowed)
2930 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2931
2932 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2933 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2934
2935 if (sctx->screen->has_out_of_order_rast &&
2936 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2937 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2938 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2939 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2940
2941 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2942 struct pipe_constant_buffer constbuf = {0};
2943
2944 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2945 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2946
2947 constbuf.buffer = sctx->sample_pos_buffer;
2948
2949 /* Set sample locations as fragment shader constants. */
2950 switch (sctx->framebuffer.nr_samples) {
2951 case 1:
2952 constbuf.buffer_offset = 0;
2953 break;
2954 case 2:
2955 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
2956 (ubyte*)sctx->sample_positions.x1;
2957 break;
2958 case 4:
2959 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
2960 (ubyte*)sctx->sample_positions.x1;
2961 break;
2962 case 8:
2963 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
2964 (ubyte*)sctx->sample_positions.x1;
2965 break;
2966 case 16:
2967 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
2968 (ubyte*)sctx->sample_positions.x1;
2969 break;
2970 default:
2971 PRINT_ERR("Requested an invalid number of samples %i.\n",
2972 sctx->framebuffer.nr_samples);
2973 assert(0);
2974 }
2975 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2976 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2977
2978 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2979 }
2980
2981 sctx->do_update_shaders = true;
2982
2983 if (!sctx->decompression_enabled) {
2984 /* Prevent textures decompression when the framebuffer state
2985 * changes come from the decompression passes themselves.
2986 */
2987 sctx->need_check_render_feedback = true;
2988 }
2989 }
2990
2991 static void si_emit_framebuffer_state(struct si_context *sctx)
2992 {
2993 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2994 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2995 unsigned i, nr_cbufs = state->nr_cbufs;
2996 struct si_texture *tex = NULL;
2997 struct si_surface *cb = NULL;
2998 unsigned cb_color_info = 0;
2999
3000 /* Colorbuffers. */
3001 for (i = 0; i < nr_cbufs; i++) {
3002 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3003 unsigned cb_color_attrib;
3004
3005 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3006 continue;
3007
3008 cb = (struct si_surface*)state->cbufs[i];
3009 if (!cb) {
3010 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3011 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3012 continue;
3013 }
3014
3015 tex = (struct si_texture *)cb->base.texture;
3016 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3017 &tex->buffer, RADEON_USAGE_READWRITE,
3018 tex->buffer.b.b.nr_samples > 1 ?
3019 RADEON_PRIO_COLOR_BUFFER_MSAA :
3020 RADEON_PRIO_COLOR_BUFFER);
3021
3022 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3023 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3024 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3025 RADEON_PRIO_SEPARATE_META);
3026 }
3027
3028 if (tex->dcc_separate_buffer)
3029 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3030 tex->dcc_separate_buffer,
3031 RADEON_USAGE_READWRITE,
3032 RADEON_PRIO_SEPARATE_META);
3033
3034 /* Compute mutable surface parameters. */
3035 cb_color_base = tex->buffer.gpu_address >> 8;
3036 cb_color_fmask = 0;
3037 cb_color_cmask = tex->cmask_base_address_reg;
3038 cb_dcc_base = 0;
3039 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3040 cb_color_attrib = cb->cb_color_attrib;
3041
3042 if (cb->base.u.tex.level > 0)
3043 cb_color_info &= C_028C70_FAST_CLEAR;
3044
3045 if (tex->surface.fmask_size) {
3046 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3047 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3048 }
3049
3050 /* Set up DCC. */
3051 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3052 bool is_msaa_resolve_dst = state->cbufs[0] &&
3053 state->cbufs[0]->texture->nr_samples > 1 &&
3054 state->cbufs[1] == &cb->base &&
3055 state->cbufs[1]->texture->nr_samples <= 1;
3056
3057 if (!is_msaa_resolve_dst)
3058 cb_color_info |= S_028C70_DCC_ENABLE(1);
3059
3060 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3061 tex->dcc_offset) >> 8;
3062 cb_dcc_base |= tex->surface.tile_swizzle;
3063 }
3064
3065 if (sctx->chip_class >= GFX9) {
3066 struct gfx9_surf_meta_flags meta;
3067
3068 if (tex->dcc_offset)
3069 meta = tex->surface.u.gfx9.dcc;
3070 else
3071 meta = tex->surface.u.gfx9.cmask;
3072
3073 /* Set mutable surface parameters. */
3074 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3075 cb_color_base |= tex->surface.tile_swizzle;
3076 if (!tex->surface.fmask_size)
3077 cb_color_fmask = cb_color_base;
3078 if (cb->base.u.tex.level > 0)
3079 cb_color_cmask = cb_color_base;
3080 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3081 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3082 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3083 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3084
3085 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3086 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3087 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3088 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3089 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3090 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3091 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3092 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3093 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3094 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3095 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3096 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3097 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3098 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3099 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3100 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3101
3102 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3103 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3104 } else {
3105 /* Compute mutable surface parameters (SI-CI-VI). */
3106 const struct legacy_surf_level *level_info =
3107 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3108 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3109 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3110
3111 cb_color_base += level_info->offset >> 8;
3112 /* Only macrotiled modes can set tile swizzle. */
3113 if (level_info->mode == RADEON_SURF_MODE_2D)
3114 cb_color_base |= tex->surface.tile_swizzle;
3115
3116 if (!tex->surface.fmask_size)
3117 cb_color_fmask = cb_color_base;
3118 if (cb->base.u.tex.level > 0)
3119 cb_color_cmask = cb_color_base;
3120 if (cb_dcc_base)
3121 cb_dcc_base += level_info->dcc_offset >> 8;
3122
3123 pitch_tile_max = level_info->nblk_x / 8 - 1;
3124 slice_tile_max = level_info->nblk_x *
3125 level_info->nblk_y / 64 - 1;
3126 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3127
3128 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3129 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3130 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3131
3132 if (tex->surface.fmask_size) {
3133 if (sctx->chip_class >= CIK)
3134 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3135 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3136 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3137 } else {
3138 /* This must be set for fast clear to work without FMASK. */
3139 if (sctx->chip_class >= CIK)
3140 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3141 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3142 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3143 }
3144
3145 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3146 sctx->chip_class >= VI ? 14 : 13);
3147 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3148 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3149 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3150 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3151 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3152 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3153 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3154 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3155 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3156 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3157 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3158 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3159 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3160
3161 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3162 radeon_emit(cs, cb_dcc_base);
3163 }
3164 }
3165 for (; i < 8 ; i++)
3166 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3167 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3168
3169 /* ZS buffer. */
3170 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3171 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3172 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3173
3174 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3175 &tex->buffer, RADEON_USAGE_READWRITE,
3176 zb->base.texture->nr_samples > 1 ?
3177 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3178 RADEON_PRIO_DEPTH_BUFFER);
3179
3180 if (sctx->chip_class >= GFX9) {
3181 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3182 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3183 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3184 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3185
3186 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3187 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3188 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3189 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3190 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3191 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3192 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3193 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3194 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3195 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3196 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3197 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3198
3199 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3200 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3201 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3202 } else {
3203 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3204
3205 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3206 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3207 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3208 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3209 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3210 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3211 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3212 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3213 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3214 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3215 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3216 }
3217
3218 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3219 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3220 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3221
3222 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3223 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3224 } else if (sctx->framebuffer.dirty_zsbuf) {
3225 if (sctx->chip_class >= GFX9)
3226 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3227 else
3228 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3229
3230 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3231 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3232 }
3233
3234 /* Framebuffer dimensions. */
3235 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3236 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3237 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3238
3239 if (sctx->screen->dfsm_allowed) {
3240 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3241 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3242 }
3243
3244 sctx->framebuffer.dirty_cbufs = 0;
3245 sctx->framebuffer.dirty_zsbuf = false;
3246 }
3247
3248 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3249 {
3250 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3251 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3252 unsigned nr_samples = sctx->framebuffer.nr_samples;
3253 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3254
3255 /* Smoothing (only possible with nr_samples == 1) uses the same
3256 * sample locations as the MSAA it simulates.
3257 */
3258 if (nr_samples <= 1 && sctx->smoothing_enabled)
3259 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3260
3261 /* On Polaris, the small primitive filter uses the sample locations
3262 * even when MSAA is off, so we need to make sure they're set to 0.
3263 */
3264 if ((nr_samples >= 2 || has_msaa_sample_loc_bug) &&
3265 nr_samples != sctx->sample_locs_num_samples) {
3266 sctx->sample_locs_num_samples = nr_samples;
3267 si_emit_sample_locations(cs, nr_samples);
3268 }
3269
3270 if (sctx->family >= CHIP_POLARIS10) {
3271 unsigned small_prim_filter_cntl =
3272 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3273 /* line bug */
3274 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3275
3276 /* The alternative of setting sample locations to 0 would
3277 * require a DB flush to avoid Z errors, see
3278 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3279 */
3280 if (has_msaa_sample_loc_bug &&
3281 sctx->framebuffer.nr_samples > 1 &&
3282 !rs->multisample_enable)
3283 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3284
3285 radeon_opt_set_context_reg(sctx,
3286 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3287 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3288 small_prim_filter_cntl);
3289 }
3290
3291 /* The exclusion bits can be set to improve rasterization efficiency
3292 * if no sample lies on the pixel boundary (-8 sample offset).
3293 */
3294 bool exclusion = sctx->chip_class >= CIK &&
3295 (!rs->multisample_enable || nr_samples != 16);
3296 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3297 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3298 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3299 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3300 }
3301
3302 static bool si_out_of_order_rasterization(struct si_context *sctx)
3303 {
3304 struct si_state_blend *blend = sctx->queued.named.blend;
3305 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3306
3307 if (!sctx->screen->has_out_of_order_rast)
3308 return false;
3309
3310 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3311
3312 if (blend) {
3313 colormask &= blend->cb_target_enabled_4bit;
3314 } else {
3315 colormask = 0;
3316 }
3317
3318 /* Conservative: No logic op. */
3319 if (colormask && blend->logicop_enable)
3320 return false;
3321
3322 struct si_dsa_order_invariance dsa_order_invariant = {
3323 .zs = true, .pass_set = true, .pass_last = false
3324 };
3325
3326 if (sctx->framebuffer.state.zsbuf) {
3327 struct si_texture *zstex =
3328 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3329 bool has_stencil = zstex->surface.has_stencil;
3330 dsa_order_invariant = dsa->order_invariance[has_stencil];
3331 if (!dsa_order_invariant.zs)
3332 return false;
3333
3334 /* The set of PS invocations is always order invariant,
3335 * except when early Z/S tests are requested. */
3336 if (sctx->ps_shader.cso &&
3337 sctx->ps_shader.cso->info.writes_memory &&
3338 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3339 !dsa_order_invariant.pass_set)
3340 return false;
3341
3342 if (sctx->num_perfect_occlusion_queries != 0 &&
3343 !dsa_order_invariant.pass_set)
3344 return false;
3345 }
3346
3347 if (!colormask)
3348 return true;
3349
3350 unsigned blendmask = colormask & blend->blend_enable_4bit;
3351
3352 if (blendmask) {
3353 /* Only commutative blending. */
3354 if (blendmask & ~blend->commutative_4bit)
3355 return false;
3356
3357 if (!dsa_order_invariant.pass_set)
3358 return false;
3359 }
3360
3361 if (colormask & ~blendmask) {
3362 if (!dsa_order_invariant.pass_last)
3363 return false;
3364 }
3365
3366 return true;
3367 }
3368
3369 static void si_emit_msaa_config(struct si_context *sctx)
3370 {
3371 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3372 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3373 /* 33% faster rendering to linear color buffers */
3374 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3375 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3376 unsigned sc_mode_cntl_1 =
3377 S_028A4C_WALK_SIZE(dst_is_linear) |
3378 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3379 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3380 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3381 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3382 /* always 1: */
3383 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3384 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3385 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3386 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3387 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3388 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3389 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3390 S_028804_INCOHERENT_EQAA_READS(1) |
3391 S_028804_INTERPOLATE_COMP_Z(1) |
3392 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3393 unsigned coverage_samples, color_samples, z_samples;
3394
3395 /* S: Coverage samples (up to 16x):
3396 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3397 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3398 *
3399 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3400 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3401 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3402 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3403 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3404 * # Z samples).
3405 *
3406 * F: Color samples (up to 8x, must be <= coverage samples):
3407 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3408 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3409 *
3410 * Can be anything between coverage and color samples:
3411 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3412 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3413 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3414 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3415 * # All are currently set the same as coverage samples.
3416 *
3417 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3418 * flag for undefined color samples. A shader-based resolve must handle unknowns
3419 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3420 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3421 * useful. The CB resolve always drops unknowns.
3422 *
3423 * Sensible AA configurations:
3424 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3425 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3426 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3427 * EQAA 8s 8z 8f = 8x MSAA
3428 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3429 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3430 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3431 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3432 * EQAA 4s 4z 4f = 4x MSAA
3433 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3434 * EQAA 2s 2z 2f = 2x MSAA
3435 */
3436 if (sctx->framebuffer.nr_samples > 1) {
3437 coverage_samples = sctx->framebuffer.nr_samples;
3438 color_samples = sctx->framebuffer.nr_color_samples;
3439
3440 if (sctx->framebuffer.state.zsbuf) {
3441 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3442 z_samples = MAX2(1, z_samples);
3443 } else {
3444 z_samples = coverage_samples;
3445 }
3446 } else if (sctx->smoothing_enabled) {
3447 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3448 } else {
3449 coverage_samples = color_samples = z_samples = 1;
3450 }
3451
3452 /* Required by OpenGL line rasterization.
3453 *
3454 * TODO: We should also enable perpendicular endcaps for AA lines,
3455 * but that requires implementing line stippling in the pixel
3456 * shader. SC can only do line stippling with axis-aligned
3457 * endcaps.
3458 */
3459 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3460 unsigned sc_aa_config = 0;
3461
3462 if (coverage_samples > 1) {
3463 /* distance from the pixel center, indexed by log2(nr_samples) */
3464 static unsigned max_dist[] = {
3465 0, /* unused */
3466 4, /* 2x MSAA */
3467 6, /* 4x MSAA */
3468 7, /* 8x MSAA */
3469 8, /* 16x MSAA */
3470 };
3471 unsigned log_samples = util_logbase2(coverage_samples);
3472 unsigned log_z_samples = util_logbase2(z_samples);
3473 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3474 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3475
3476 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3477 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3478 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3479 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3480
3481 if (sctx->framebuffer.nr_samples > 1) {
3482 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3483 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3484 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3485 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3486 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3487 } else if (sctx->smoothing_enabled) {
3488 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3489 }
3490 }
3491
3492 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3493 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3494 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3495 sc_aa_config);
3496 /* R_028804_DB_EQAA */
3497 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3498 db_eqaa);
3499 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3500 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3501 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3502
3503 /* GFX9: Flush DFSM when the AA mode changes. */
3504 if (sctx->screen->dfsm_allowed) {
3505 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3506 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3507 }
3508 }
3509
3510 void si_update_ps_iter_samples(struct si_context *sctx)
3511 {
3512 if (sctx->framebuffer.nr_samples > 1)
3513 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3514 if (sctx->screen->dpbb_allowed)
3515 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3516 }
3517
3518 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3519 {
3520 struct si_context *sctx = (struct si_context *)ctx;
3521
3522 /* The hardware can only do sample shading with 2^n samples. */
3523 min_samples = util_next_power_of_two(min_samples);
3524
3525 if (sctx->ps_iter_samples == min_samples)
3526 return;
3527
3528 sctx->ps_iter_samples = min_samples;
3529 sctx->do_update_shaders = true;
3530
3531 si_update_ps_iter_samples(sctx);
3532 }
3533
3534 /*
3535 * Samplers
3536 */
3537
3538 /**
3539 * Build the sampler view descriptor for a buffer texture.
3540 * @param state 256-bit descriptor; only the high 128 bits are filled in
3541 */
3542 void
3543 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3544 enum pipe_format format,
3545 unsigned offset, unsigned size,
3546 uint32_t *state)
3547 {
3548 const struct util_format_description *desc;
3549 int first_non_void;
3550 unsigned stride;
3551 unsigned num_records;
3552 unsigned num_format, data_format;
3553
3554 desc = util_format_description(format);
3555 first_non_void = util_format_get_first_non_void_channel(format);
3556 stride = desc->block.bits / 8;
3557 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3558 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3559
3560 num_records = size / stride;
3561 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3562
3563 /* The NUM_RECORDS field has a different meaning depending on the chip,
3564 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3565 *
3566 * SI-CIK:
3567 * - If STRIDE == 0, it's in byte units.
3568 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3569 *
3570 * VI:
3571 * - For SMEM and STRIDE == 0, it's in byte units.
3572 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3573 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3574 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3575 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3576 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3577 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3578 * That way the same descriptor can be used by both SMEM and VMEM.
3579 *
3580 * GFX9:
3581 * - For SMEM and STRIDE == 0, it's in byte units.
3582 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3583 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3584 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3585 */
3586 if (screen->info.chip_class >= GFX9)
3587 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3588 * from STRIDE to bytes. This works around it by setting
3589 * NUM_RECORDS to at least the size of one element, so that
3590 * the first element is readable when IDXEN == 0.
3591 *
3592 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3593 * IDXEN is enforced?
3594 */
3595 num_records = num_records ? MAX2(num_records, stride) : 0;
3596 else if (screen->info.chip_class == VI)
3597 num_records *= stride;
3598
3599 state[4] = 0;
3600 state[5] = S_008F04_STRIDE(stride);
3601 state[6] = num_records;
3602 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3603 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3604 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3605 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3606 S_008F0C_NUM_FORMAT(num_format) |
3607 S_008F0C_DATA_FORMAT(data_format);
3608 }
3609
3610 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3611 {
3612 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3613
3614 if (swizzle[3] == PIPE_SWIZZLE_X) {
3615 /* For the pre-defined border color values (white, opaque
3616 * black, transparent black), the only thing that matters is
3617 * that the alpha channel winds up in the correct place
3618 * (because the RGB channels are all the same) so either of
3619 * these enumerations will work.
3620 */
3621 if (swizzle[2] == PIPE_SWIZZLE_Y)
3622 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3623 else
3624 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3625 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3626 if (swizzle[1] == PIPE_SWIZZLE_Y)
3627 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3628 else
3629 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3630 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3631 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3632 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3633 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3634 }
3635
3636 return bc_swizzle;
3637 }
3638
3639 /**
3640 * Build the sampler view descriptor for a texture.
3641 */
3642 void
3643 si_make_texture_descriptor(struct si_screen *screen,
3644 struct si_texture *tex,
3645 bool sampler,
3646 enum pipe_texture_target target,
3647 enum pipe_format pipe_format,
3648 const unsigned char state_swizzle[4],
3649 unsigned first_level, unsigned last_level,
3650 unsigned first_layer, unsigned last_layer,
3651 unsigned width, unsigned height, unsigned depth,
3652 uint32_t *state,
3653 uint32_t *fmask_state)
3654 {
3655 struct pipe_resource *res = &tex->buffer.b.b;
3656 const struct util_format_description *desc;
3657 unsigned char swizzle[4];
3658 int first_non_void;
3659 unsigned num_format, data_format, type, num_samples;
3660 uint64_t va;
3661
3662 desc = util_format_description(pipe_format);
3663
3664 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3665 MAX2(1, res->nr_samples) :
3666 MAX2(1, res->nr_storage_samples);
3667
3668 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3669 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3670 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3671 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3672
3673 switch (pipe_format) {
3674 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3675 case PIPE_FORMAT_X32_S8X24_UINT:
3676 case PIPE_FORMAT_X8Z24_UNORM:
3677 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3678 break;
3679 case PIPE_FORMAT_X24S8_UINT:
3680 /*
3681 * X24S8 is implemented as an 8_8_8_8 data format, to
3682 * fix texture gathers. This affects at least
3683 * GL45-CTS.texture_cube_map_array.sampling on VI.
3684 */
3685 if (screen->info.chip_class <= VI)
3686 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3687 else
3688 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3689 break;
3690 default:
3691 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3692 }
3693 } else {
3694 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3695 }
3696
3697 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3698
3699 switch (pipe_format) {
3700 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3701 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3702 break;
3703 default:
3704 if (first_non_void < 0) {
3705 if (util_format_is_compressed(pipe_format)) {
3706 switch (pipe_format) {
3707 case PIPE_FORMAT_DXT1_SRGB:
3708 case PIPE_FORMAT_DXT1_SRGBA:
3709 case PIPE_FORMAT_DXT3_SRGBA:
3710 case PIPE_FORMAT_DXT5_SRGBA:
3711 case PIPE_FORMAT_BPTC_SRGBA:
3712 case PIPE_FORMAT_ETC2_SRGB8:
3713 case PIPE_FORMAT_ETC2_SRGB8A1:
3714 case PIPE_FORMAT_ETC2_SRGBA8:
3715 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3716 break;
3717 case PIPE_FORMAT_RGTC1_SNORM:
3718 case PIPE_FORMAT_LATC1_SNORM:
3719 case PIPE_FORMAT_RGTC2_SNORM:
3720 case PIPE_FORMAT_LATC2_SNORM:
3721 case PIPE_FORMAT_ETC2_R11_SNORM:
3722 case PIPE_FORMAT_ETC2_RG11_SNORM:
3723 /* implies float, so use SNORM/UNORM to determine
3724 whether data is signed or not */
3725 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3726 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3727 break;
3728 default:
3729 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3730 break;
3731 }
3732 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3733 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3734 } else {
3735 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3736 }
3737 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3738 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3739 } else {
3740 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3741
3742 switch (desc->channel[first_non_void].type) {
3743 case UTIL_FORMAT_TYPE_FLOAT:
3744 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3745 break;
3746 case UTIL_FORMAT_TYPE_SIGNED:
3747 if (desc->channel[first_non_void].normalized)
3748 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3749 else if (desc->channel[first_non_void].pure_integer)
3750 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3751 else
3752 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3753 break;
3754 case UTIL_FORMAT_TYPE_UNSIGNED:
3755 if (desc->channel[first_non_void].normalized)
3756 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3757 else if (desc->channel[first_non_void].pure_integer)
3758 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3759 else
3760 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3761 }
3762 }
3763 }
3764
3765 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3766 if (data_format == ~0) {
3767 data_format = 0;
3768 }
3769
3770 /* S8 with Z32 HTILE needs a special format. */
3771 if (screen->info.chip_class >= GFX9 &&
3772 pipe_format == PIPE_FORMAT_S8_UINT &&
3773 tex->tc_compatible_htile)
3774 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3775
3776 if (!sampler &&
3777 (res->target == PIPE_TEXTURE_CUBE ||
3778 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3779 (screen->info.chip_class <= VI &&
3780 res->target == PIPE_TEXTURE_3D))) {
3781 /* For the purpose of shader images, treat cube maps and 3D
3782 * textures as 2D arrays. For 3D textures, the address
3783 * calculations for mipmaps are different, so we rely on the
3784 * caller to effectively disable mipmaps.
3785 */
3786 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3787
3788 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3789 } else {
3790 type = si_tex_dim(screen, tex, target, num_samples);
3791 }
3792
3793 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3794 height = 1;
3795 depth = res->array_size;
3796 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3797 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3798 if (sampler || res->target != PIPE_TEXTURE_3D)
3799 depth = res->array_size;
3800 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3801 depth = res->array_size / 6;
3802
3803 state[0] = 0;
3804 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3805 S_008F14_NUM_FORMAT_GFX6(num_format));
3806 state[2] = (S_008F18_WIDTH(width - 1) |
3807 S_008F18_HEIGHT(height - 1) |
3808 S_008F18_PERF_MOD(4));
3809 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3810 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3811 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3812 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3813 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3814 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3815 util_logbase2(num_samples) :
3816 last_level) |
3817 S_008F1C_TYPE(type));
3818 state[4] = 0;
3819 state[5] = S_008F24_BASE_ARRAY(first_layer);
3820 state[6] = 0;
3821 state[7] = 0;
3822
3823 if (screen->info.chip_class >= GFX9) {
3824 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3825
3826 /* Depth is the the last accessible layer on Gfx9.
3827 * The hw doesn't need to know the total number of layers.
3828 */
3829 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3830 state[4] |= S_008F20_DEPTH(depth - 1);
3831 else
3832 state[4] |= S_008F20_DEPTH(last_layer);
3833
3834 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3835 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3836 util_logbase2(num_samples) :
3837 tex->buffer.b.b.last_level);
3838 } else {
3839 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3840 state[4] |= S_008F20_DEPTH(depth - 1);
3841 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3842 }
3843
3844 if (tex->dcc_offset) {
3845 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3846 } else {
3847 /* The last dword is unused by hw. The shader uses it to clear
3848 * bits in the first dword of sampler state.
3849 */
3850 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3851 if (first_level == last_level)
3852 state[7] = C_008F30_MAX_ANISO_RATIO;
3853 else
3854 state[7] = 0xffffffff;
3855 }
3856 }
3857
3858 /* Initialize the sampler view for FMASK. */
3859 if (tex->surface.fmask_size) {
3860 uint32_t data_format, num_format;
3861
3862 va = tex->buffer.gpu_address + tex->fmask_offset;
3863
3864 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3865 if (screen->info.chip_class >= GFX9) {
3866 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3867 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3868 case FMASK(2,1):
3869 num_format = V_008F14_IMG_FMASK_8_2_1;
3870 break;
3871 case FMASK(2,2):
3872 num_format = V_008F14_IMG_FMASK_8_2_2;
3873 break;
3874 case FMASK(4,1):
3875 num_format = V_008F14_IMG_FMASK_8_4_1;
3876 break;
3877 case FMASK(4,2):
3878 num_format = V_008F14_IMG_FMASK_8_4_2;
3879 break;
3880 case FMASK(4,4):
3881 num_format = V_008F14_IMG_FMASK_8_4_4;
3882 break;
3883 case FMASK(8,1):
3884 num_format = V_008F14_IMG_FMASK_8_8_1;
3885 break;
3886 case FMASK(8,2):
3887 num_format = V_008F14_IMG_FMASK_16_8_2;
3888 break;
3889 case FMASK(8,4):
3890 num_format = V_008F14_IMG_FMASK_32_8_4;
3891 break;
3892 case FMASK(8,8):
3893 num_format = V_008F14_IMG_FMASK_32_8_8;
3894 break;
3895 case FMASK(16,1):
3896 num_format = V_008F14_IMG_FMASK_16_16_1;
3897 break;
3898 case FMASK(16,2):
3899 num_format = V_008F14_IMG_FMASK_32_16_2;
3900 break;
3901 case FMASK(16,4):
3902 num_format = V_008F14_IMG_FMASK_64_16_4;
3903 break;
3904 case FMASK(16,8):
3905 num_format = V_008F14_IMG_FMASK_64_16_8;
3906 break;
3907 default:
3908 unreachable("invalid nr_samples");
3909 }
3910 } else {
3911 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3912 case FMASK(2,1):
3913 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3914 break;
3915 case FMASK(2,2):
3916 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3917 break;
3918 case FMASK(4,1):
3919 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3920 break;
3921 case FMASK(4,2):
3922 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3923 break;
3924 case FMASK(4,4):
3925 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3926 break;
3927 case FMASK(8,1):
3928 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3929 break;
3930 case FMASK(8,2):
3931 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3932 break;
3933 case FMASK(8,4):
3934 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3935 break;
3936 case FMASK(8,8):
3937 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3938 break;
3939 case FMASK(16,1):
3940 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3941 break;
3942 case FMASK(16,2):
3943 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3944 break;
3945 case FMASK(16,4):
3946 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3947 break;
3948 case FMASK(16,8):
3949 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3950 break;
3951 default:
3952 unreachable("invalid nr_samples");
3953 }
3954 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3955 }
3956 #undef FMASK
3957
3958 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3959 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3960 S_008F14_DATA_FORMAT_GFX6(data_format) |
3961 S_008F14_NUM_FORMAT_GFX6(num_format);
3962 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3963 S_008F18_HEIGHT(height - 1);
3964 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3965 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3966 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3967 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3968 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3969 fmask_state[4] = 0;
3970 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3971 fmask_state[6] = 0;
3972 fmask_state[7] = 0;
3973
3974 if (screen->info.chip_class >= GFX9) {
3975 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3976 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3977 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3978 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3979 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3980 } else {
3981 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3982 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3983 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3984 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3985 }
3986 }
3987 }
3988
3989 /**
3990 * Create a sampler view.
3991 *
3992 * @param ctx context
3993 * @param texture texture
3994 * @param state sampler view template
3995 * @param width0 width0 override (for compressed textures as int)
3996 * @param height0 height0 override (for compressed textures as int)
3997 * @param force_level set the base address to the level (for compressed textures)
3998 */
3999 struct pipe_sampler_view *
4000 si_create_sampler_view_custom(struct pipe_context *ctx,
4001 struct pipe_resource *texture,
4002 const struct pipe_sampler_view *state,
4003 unsigned width0, unsigned height0,
4004 unsigned force_level)
4005 {
4006 struct si_context *sctx = (struct si_context*)ctx;
4007 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4008 struct si_texture *tex = (struct si_texture*)texture;
4009 unsigned base_level, first_level, last_level;
4010 unsigned char state_swizzle[4];
4011 unsigned height, depth, width;
4012 unsigned last_layer = state->u.tex.last_layer;
4013 enum pipe_format pipe_format;
4014 const struct legacy_surf_level *surflevel;
4015
4016 if (!view)
4017 return NULL;
4018
4019 /* initialize base object */
4020 view->base = *state;
4021 view->base.texture = NULL;
4022 view->base.reference.count = 1;
4023 view->base.context = ctx;
4024
4025 assert(texture);
4026 pipe_resource_reference(&view->base.texture, texture);
4027
4028 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4029 state->format == PIPE_FORMAT_S8X24_UINT ||
4030 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4031 state->format == PIPE_FORMAT_S8_UINT)
4032 view->is_stencil_sampler = true;
4033
4034 /* Buffer resource. */
4035 if (texture->target == PIPE_BUFFER) {
4036 si_make_buffer_descriptor(sctx->screen,
4037 r600_resource(texture),
4038 state->format,
4039 state->u.buf.offset,
4040 state->u.buf.size,
4041 view->state);
4042 return &view->base;
4043 }
4044
4045 state_swizzle[0] = state->swizzle_r;
4046 state_swizzle[1] = state->swizzle_g;
4047 state_swizzle[2] = state->swizzle_b;
4048 state_swizzle[3] = state->swizzle_a;
4049
4050 base_level = 0;
4051 first_level = state->u.tex.first_level;
4052 last_level = state->u.tex.last_level;
4053 width = width0;
4054 height = height0;
4055 depth = texture->depth0;
4056
4057 if (sctx->chip_class <= VI && force_level) {
4058 assert(force_level == first_level &&
4059 force_level == last_level);
4060 base_level = force_level;
4061 first_level = 0;
4062 last_level = 0;
4063 width = u_minify(width, force_level);
4064 height = u_minify(height, force_level);
4065 depth = u_minify(depth, force_level);
4066 }
4067
4068 /* This is not needed if state trackers set last_layer correctly. */
4069 if (state->target == PIPE_TEXTURE_1D ||
4070 state->target == PIPE_TEXTURE_2D ||
4071 state->target == PIPE_TEXTURE_RECT ||
4072 state->target == PIPE_TEXTURE_CUBE)
4073 last_layer = state->u.tex.first_layer;
4074
4075 /* Texturing with separate depth and stencil. */
4076 pipe_format = state->format;
4077
4078 /* Depth/stencil texturing sometimes needs separate texture. */
4079 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4080 if (!tex->flushed_depth_texture &&
4081 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4082 pipe_resource_reference(&view->base.texture, NULL);
4083 FREE(view);
4084 return NULL;
4085 }
4086
4087 assert(tex->flushed_depth_texture);
4088
4089 /* Override format for the case where the flushed texture
4090 * contains only Z or only S.
4091 */
4092 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4093 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4094
4095 tex = tex->flushed_depth_texture;
4096 }
4097
4098 surflevel = tex->surface.u.legacy.level;
4099
4100 if (tex->db_compatible) {
4101 if (!view->is_stencil_sampler)
4102 pipe_format = tex->db_render_format;
4103
4104 switch (pipe_format) {
4105 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4106 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4107 break;
4108 case PIPE_FORMAT_X8Z24_UNORM:
4109 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4110 /* Z24 is always stored like this for DB
4111 * compatibility.
4112 */
4113 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4114 break;
4115 case PIPE_FORMAT_X24S8_UINT:
4116 case PIPE_FORMAT_S8X24_UINT:
4117 case PIPE_FORMAT_X32_S8X24_UINT:
4118 pipe_format = PIPE_FORMAT_S8_UINT;
4119 surflevel = tex->surface.u.legacy.stencil_level;
4120 break;
4121 default:;
4122 }
4123 }
4124
4125 view->dcc_incompatible =
4126 vi_dcc_formats_are_incompatible(texture,
4127 state->u.tex.first_level,
4128 state->format);
4129
4130 si_make_texture_descriptor(sctx->screen, tex, true,
4131 state->target, pipe_format, state_swizzle,
4132 first_level, last_level,
4133 state->u.tex.first_layer, last_layer,
4134 width, height, depth,
4135 view->state, view->fmask_state);
4136
4137 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4138 view->is_integer =
4139 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4140 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4141 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4142 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4143 view->base_level_info = &surflevel[base_level];
4144 view->base_level = base_level;
4145 view->block_width = util_format_get_blockwidth(pipe_format);
4146 return &view->base;
4147 }
4148
4149 static struct pipe_sampler_view *
4150 si_create_sampler_view(struct pipe_context *ctx,
4151 struct pipe_resource *texture,
4152 const struct pipe_sampler_view *state)
4153 {
4154 return si_create_sampler_view_custom(ctx, texture, state,
4155 texture ? texture->width0 : 0,
4156 texture ? texture->height0 : 0, 0);
4157 }
4158
4159 static void si_sampler_view_destroy(struct pipe_context *ctx,
4160 struct pipe_sampler_view *state)
4161 {
4162 struct si_sampler_view *view = (struct si_sampler_view *)state;
4163
4164 pipe_resource_reference(&state->texture, NULL);
4165 FREE(view);
4166 }
4167
4168 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4169 {
4170 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4171 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4172 (linear_filter &&
4173 (wrap == PIPE_TEX_WRAP_CLAMP ||
4174 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4175 }
4176
4177 static uint32_t si_translate_border_color(struct si_context *sctx,
4178 const struct pipe_sampler_state *state,
4179 const union pipe_color_union *color,
4180 bool is_integer)
4181 {
4182 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4183 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4184
4185 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4186 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4187 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4188 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4189
4190 #define simple_border_types(elt) \
4191 do { \
4192 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4193 color->elt[2] == 0 && color->elt[3] == 0) \
4194 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4195 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4196 color->elt[2] == 0 && color->elt[3] == 1) \
4197 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4198 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4199 color->elt[2] == 1 && color->elt[3] == 1) \
4200 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4201 } while (false)
4202
4203 if (is_integer)
4204 simple_border_types(ui);
4205 else
4206 simple_border_types(f);
4207
4208 #undef simple_border_types
4209
4210 int i;
4211
4212 /* Check if the border has been uploaded already. */
4213 for (i = 0; i < sctx->border_color_count; i++)
4214 if (memcmp(&sctx->border_color_table[i], color,
4215 sizeof(*color)) == 0)
4216 break;
4217
4218 if (i >= SI_MAX_BORDER_COLORS) {
4219 /* Getting 4096 unique border colors is very unlikely. */
4220 fprintf(stderr, "radeonsi: The border color table is full. "
4221 "Any new border colors will be just black. "
4222 "Please file a bug.\n");
4223 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4224 }
4225
4226 if (i == sctx->border_color_count) {
4227 /* Upload a new border color. */
4228 memcpy(&sctx->border_color_table[i], color,
4229 sizeof(*color));
4230 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4231 color, sizeof(*color));
4232 sctx->border_color_count++;
4233 }
4234
4235 return S_008F3C_BORDER_COLOR_PTR(i) |
4236 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4237 }
4238
4239 static inline int S_FIXED(float value, unsigned frac_bits)
4240 {
4241 return value * (1 << frac_bits);
4242 }
4243
4244 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4245 {
4246 if (filter == PIPE_TEX_FILTER_LINEAR)
4247 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4248 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4249 else
4250 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4251 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4252 }
4253
4254 static inline unsigned si_tex_aniso_filter(unsigned filter)
4255 {
4256 if (filter < 2)
4257 return 0;
4258 if (filter < 4)
4259 return 1;
4260 if (filter < 8)
4261 return 2;
4262 if (filter < 16)
4263 return 3;
4264 return 4;
4265 }
4266
4267 static void *si_create_sampler_state(struct pipe_context *ctx,
4268 const struct pipe_sampler_state *state)
4269 {
4270 struct si_context *sctx = (struct si_context *)ctx;
4271 struct si_screen *sscreen = sctx->screen;
4272 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4273 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4274 : state->max_anisotropy;
4275 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4276 union pipe_color_union clamped_border_color;
4277
4278 if (!rstate) {
4279 return NULL;
4280 }
4281
4282 #ifdef DEBUG
4283 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4284 #endif
4285 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4286 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4287 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4288 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4289 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4290 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4291 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4292 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4293 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4294 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4295 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4296 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4297 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4298 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4299 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4300 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4301 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4302 S_008F38_MIP_POINT_PRECLAMP(0) |
4303 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4304 S_008F38_FILTER_PREC_FIX(1) |
4305 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4306 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4307
4308 /* Create sampler resource for integer textures. */
4309 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4310 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4311
4312 /* Create sampler resource for upgraded depth textures. */
4313 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4314
4315 for (unsigned i = 0; i < 4; ++i) {
4316 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4317 * when the border color is 1.0. */
4318 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4319 }
4320
4321 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4322 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4323 else
4324 rstate->upgraded_depth_val[3] =
4325 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4326 S_008F3C_UPGRADED_DEPTH(1);
4327
4328 return rstate;
4329 }
4330
4331 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4332 {
4333 struct si_context *sctx = (struct si_context *)ctx;
4334
4335 if (sctx->sample_mask == (uint16_t)sample_mask)
4336 return;
4337
4338 sctx->sample_mask = sample_mask;
4339 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4340 }
4341
4342 static void si_emit_sample_mask(struct si_context *sctx)
4343 {
4344 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4345 unsigned mask = sctx->sample_mask;
4346
4347 /* Needed for line and polygon smoothing as well as for the Polaris
4348 * small primitive filter. We expect the state tracker to take care of
4349 * this for us.
4350 */
4351 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4352 (mask & 1 && sctx->blitter->running));
4353
4354 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4355 radeon_emit(cs, mask | (mask << 16));
4356 radeon_emit(cs, mask | (mask << 16));
4357 }
4358
4359 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4360 {
4361 #ifdef DEBUG
4362 struct si_sampler_state *s = state;
4363
4364 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4365 s->magic = 0;
4366 #endif
4367 free(state);
4368 }
4369
4370 /*
4371 * Vertex elements & buffers
4372 */
4373
4374 struct util_fast_udiv_info32 {
4375 unsigned multiplier; /* the "magic number" multiplier */
4376 unsigned pre_shift; /* shift for the dividend before multiplying */
4377 unsigned post_shift; /* shift for the dividend after multiplying */
4378 int increment; /* 0 or 1; if set then increment the numerator, using one of
4379 the two strategies */
4380 };
4381
4382 static struct util_fast_udiv_info32
4383 util_compute_fast_udiv_info32(uint32_t D, unsigned num_bits)
4384 {
4385 struct util_fast_udiv_info info =
4386 util_compute_fast_udiv_info(D, num_bits, 32);
4387
4388 struct util_fast_udiv_info32 result = {
4389 info.multiplier,
4390 info.pre_shift,
4391 info.post_shift,
4392 info.increment,
4393 };
4394 return result;
4395 }
4396
4397 static void *si_create_vertex_elements(struct pipe_context *ctx,
4398 unsigned count,
4399 const struct pipe_vertex_element *elements)
4400 {
4401 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4402 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4403 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4404 struct util_fast_udiv_info32 divisor_factors[SI_MAX_ATTRIBS] = {};
4405 STATIC_ASSERT(sizeof(struct util_fast_udiv_info32) == 16);
4406 STATIC_ASSERT(sizeof(divisor_factors[0].multiplier) == 4);
4407 STATIC_ASSERT(sizeof(divisor_factors[0].pre_shift) == 4);
4408 STATIC_ASSERT(sizeof(divisor_factors[0].post_shift) == 4);
4409 STATIC_ASSERT(sizeof(divisor_factors[0].increment) == 4);
4410 int i;
4411
4412 assert(count <= SI_MAX_ATTRIBS);
4413 if (!v)
4414 return NULL;
4415
4416 v->count = count;
4417 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4418
4419 for (i = 0; i < count; ++i) {
4420 const struct util_format_description *desc;
4421 const struct util_format_channel_description *channel;
4422 unsigned data_format, num_format;
4423 int first_non_void;
4424 unsigned vbo_index = elements[i].vertex_buffer_index;
4425 unsigned char swizzle[4];
4426
4427 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4428 FREE(v);
4429 return NULL;
4430 }
4431
4432 unsigned instance_divisor = elements[i].instance_divisor;
4433 if (instance_divisor) {
4434 v->uses_instance_divisors = true;
4435
4436 if (instance_divisor == 1) {
4437 v->instance_divisor_is_one |= 1u << i;
4438 } else {
4439 v->instance_divisor_is_fetched |= 1u << i;
4440 divisor_factors[i] =
4441 util_compute_fast_udiv_info32(instance_divisor, 32);
4442 }
4443 }
4444
4445 if (!used[vbo_index]) {
4446 v->first_vb_use_mask |= 1 << i;
4447 used[vbo_index] = true;
4448 }
4449
4450 desc = util_format_description(elements[i].src_format);
4451 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4452 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4453 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4454 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4455 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4456
4457 v->format_size[i] = desc->block.bits / 8;
4458 v->src_offset[i] = elements[i].src_offset;
4459 v->vertex_buffer_index[i] = vbo_index;
4460
4461 /* The hardware always treats the 2-bit alpha channel as
4462 * unsigned, so a shader workaround is needed. The affected
4463 * chips are VI and older except Stoney (GFX8.1).
4464 */
4465 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4466 sscreen->info.chip_class <= VI &&
4467 sscreen->info.family != CHIP_STONEY) {
4468 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4469 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4470 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4471 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4472 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4473 /* This isn't actually used in OpenGL. */
4474 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4475 }
4476 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4477 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4478 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4479 else
4480 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4481 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4482 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4483 if (channel->normalized) {
4484 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4485 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4486 else
4487 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4488 } else {
4489 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4490 }
4491 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4492 if (channel->normalized) {
4493 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4494 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4495 else
4496 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4497 } else {
4498 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4499 }
4500 }
4501 } else if (channel && channel->size == 64 &&
4502 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4503 switch (desc->nr_channels) {
4504 case 1:
4505 case 2:
4506 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4507 swizzle[0] = PIPE_SWIZZLE_X;
4508 swizzle[1] = PIPE_SWIZZLE_Y;
4509 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4510 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4511 break;
4512 case 3:
4513 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4514 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4515 swizzle[1] = PIPE_SWIZZLE_Y;
4516 swizzle[2] = PIPE_SWIZZLE_0;
4517 swizzle[3] = PIPE_SWIZZLE_0;
4518 break;
4519 case 4:
4520 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4521 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4522 swizzle[1] = PIPE_SWIZZLE_Y;
4523 swizzle[2] = PIPE_SWIZZLE_Z;
4524 swizzle[3] = PIPE_SWIZZLE_W;
4525 break;
4526 default:
4527 assert(0);
4528 }
4529 } else if (channel && desc->nr_channels == 3) {
4530 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4531
4532 if (channel->size == 8) {
4533 if (channel->pure_integer)
4534 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4535 else
4536 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4537 } else if (channel->size == 16) {
4538 if (channel->pure_integer)
4539 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4540 else
4541 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4542 }
4543 }
4544
4545 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4546 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4547 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4548 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4549 S_008F0C_NUM_FORMAT(num_format) |
4550 S_008F0C_DATA_FORMAT(data_format);
4551 }
4552
4553 if (v->instance_divisor_is_fetched) {
4554 unsigned num_divisors = util_last_bit(v->instance_divisor_is_fetched);
4555
4556 v->instance_divisor_factor_buffer =
4557 (struct r600_resource*)
4558 pipe_buffer_create(&sscreen->b, 0, PIPE_USAGE_DEFAULT,
4559 num_divisors * sizeof(divisor_factors[0]));
4560 if (!v->instance_divisor_factor_buffer) {
4561 FREE(v);
4562 return NULL;
4563 }
4564 void *map = sscreen->ws->buffer_map(v->instance_divisor_factor_buffer->buf,
4565 NULL, PIPE_TRANSFER_WRITE);
4566 memcpy(map , divisor_factors, num_divisors * sizeof(divisor_factors[0]));
4567 }
4568 return v;
4569 }
4570
4571 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4572 {
4573 struct si_context *sctx = (struct si_context *)ctx;
4574 struct si_vertex_elements *old = sctx->vertex_elements;
4575 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4576
4577 sctx->vertex_elements = v;
4578 sctx->vertex_buffers_dirty = true;
4579
4580 if (v &&
4581 (!old ||
4582 old->count != v->count ||
4583 old->uses_instance_divisors != v->uses_instance_divisors ||
4584 v->uses_instance_divisors || /* we don't check which divisors changed */
4585 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4586 sctx->do_update_shaders = true;
4587
4588 if (v && v->instance_divisor_is_fetched) {
4589 struct pipe_constant_buffer cb;
4590
4591 cb.buffer = &v->instance_divisor_factor_buffer->b.b;
4592 cb.user_buffer = NULL;
4593 cb.buffer_offset = 0;
4594 cb.buffer_size = 0xffffffff;
4595 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4596 }
4597 }
4598
4599 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4600 {
4601 struct si_context *sctx = (struct si_context *)ctx;
4602 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4603
4604 if (sctx->vertex_elements == state)
4605 sctx->vertex_elements = NULL;
4606 r600_resource_reference(&v->instance_divisor_factor_buffer, NULL);
4607 FREE(state);
4608 }
4609
4610 static void si_set_vertex_buffers(struct pipe_context *ctx,
4611 unsigned start_slot, unsigned count,
4612 const struct pipe_vertex_buffer *buffers)
4613 {
4614 struct si_context *sctx = (struct si_context *)ctx;
4615 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4616 int i;
4617
4618 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4619
4620 if (buffers) {
4621 for (i = 0; i < count; i++) {
4622 const struct pipe_vertex_buffer *src = buffers + i;
4623 struct pipe_vertex_buffer *dsti = dst + i;
4624 struct pipe_resource *buf = src->buffer.resource;
4625
4626 pipe_resource_reference(&dsti->buffer.resource, buf);
4627 dsti->buffer_offset = src->buffer_offset;
4628 dsti->stride = src->stride;
4629 si_context_add_resource_size(sctx, buf);
4630 if (buf)
4631 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4632 }
4633 } else {
4634 for (i = 0; i < count; i++) {
4635 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4636 }
4637 }
4638 sctx->vertex_buffers_dirty = true;
4639 }
4640
4641 /*
4642 * Misc
4643 */
4644
4645 static void si_set_tess_state(struct pipe_context *ctx,
4646 const float default_outer_level[4],
4647 const float default_inner_level[2])
4648 {
4649 struct si_context *sctx = (struct si_context *)ctx;
4650 struct pipe_constant_buffer cb;
4651 float array[8];
4652
4653 memcpy(array, default_outer_level, sizeof(float) * 4);
4654 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4655
4656 cb.buffer = NULL;
4657 cb.user_buffer = NULL;
4658 cb.buffer_size = sizeof(array);
4659
4660 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4661 (void*)array, sizeof(array),
4662 &cb.buffer_offset);
4663
4664 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4665 pipe_resource_reference(&cb.buffer, NULL);
4666 }
4667
4668 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4669 {
4670 struct si_context *sctx = (struct si_context *)ctx;
4671
4672 si_update_fb_dirtiness_after_rendering(sctx);
4673
4674 /* Multisample surfaces are flushed in si_decompress_textures. */
4675 if (sctx->framebuffer.uncompressed_cb_mask)
4676 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4677 sctx->framebuffer.CB_has_shader_readable_metadata);
4678 }
4679
4680 /* This only ensures coherency for shader image/buffer stores. */
4681 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4682 {
4683 struct si_context *sctx = (struct si_context *)ctx;
4684
4685 /* Subsequent commands must wait for all shader invocations to
4686 * complete. */
4687 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4688 SI_CONTEXT_CS_PARTIAL_FLUSH;
4689
4690 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4691 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4692 SI_CONTEXT_INV_VMEM_L1;
4693
4694 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4695 PIPE_BARRIER_SHADER_BUFFER |
4696 PIPE_BARRIER_TEXTURE |
4697 PIPE_BARRIER_IMAGE |
4698 PIPE_BARRIER_STREAMOUT_BUFFER |
4699 PIPE_BARRIER_GLOBAL_BUFFER)) {
4700 /* As far as I can tell, L1 contents are written back to L2
4701 * automatically at end of shader, but the contents of other
4702 * L1 caches might still be stale. */
4703 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4704 }
4705
4706 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4707 /* Indices are read through TC L2 since VI.
4708 * L1 isn't used.
4709 */
4710 if (sctx->screen->info.chip_class <= CIK)
4711 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4712 }
4713
4714 /* MSAA color, any depth and any stencil are flushed in
4715 * si_decompress_textures when needed.
4716 */
4717 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4718 sctx->framebuffer.uncompressed_cb_mask) {
4719 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4720
4721 if (sctx->chip_class <= VI)
4722 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4723 }
4724
4725 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4726 if (sctx->screen->info.chip_class <= VI &&
4727 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4728 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4729 }
4730
4731 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4732 {
4733 struct pipe_blend_state blend;
4734
4735 memset(&blend, 0, sizeof(blend));
4736 blend.independent_blend_enable = true;
4737 blend.rt[0].colormask = 0xf;
4738 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4739 }
4740
4741 static void si_init_config(struct si_context *sctx);
4742
4743 void si_init_state_functions(struct si_context *sctx)
4744 {
4745 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4746 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4747 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4748 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4749 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4750 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4751 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4752 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4753 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4754 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4755 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4756
4757 sctx->b.create_blend_state = si_create_blend_state;
4758 sctx->b.bind_blend_state = si_bind_blend_state;
4759 sctx->b.delete_blend_state = si_delete_blend_state;
4760 sctx->b.set_blend_color = si_set_blend_color;
4761
4762 sctx->b.create_rasterizer_state = si_create_rs_state;
4763 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4764 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4765
4766 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4767 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4768 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4769
4770 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4771 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4772 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4773 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4774 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4775
4776 sctx->b.set_clip_state = si_set_clip_state;
4777 sctx->b.set_stencil_ref = si_set_stencil_ref;
4778
4779 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4780
4781 sctx->b.create_sampler_state = si_create_sampler_state;
4782 sctx->b.delete_sampler_state = si_delete_sampler_state;
4783
4784 sctx->b.create_sampler_view = si_create_sampler_view;
4785 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4786
4787 sctx->b.set_sample_mask = si_set_sample_mask;
4788
4789 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4790 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4791 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4792 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4793
4794 sctx->b.texture_barrier = si_texture_barrier;
4795 sctx->b.memory_barrier = si_memory_barrier;
4796 sctx->b.set_min_samples = si_set_min_samples;
4797 sctx->b.set_tess_state = si_set_tess_state;
4798
4799 sctx->b.set_active_query_state = si_set_active_query_state;
4800
4801 sctx->b.draw_vbo = si_draw_vbo;
4802
4803 si_init_config(sctx);
4804 }
4805
4806 void si_init_screen_state_functions(struct si_screen *sscreen)
4807 {
4808 sscreen->b.is_format_supported = si_is_format_supported;
4809 }
4810
4811 static void si_set_grbm_gfx_index(struct si_context *sctx,
4812 struct si_pm4_state *pm4, unsigned value)
4813 {
4814 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4815 R_00802C_GRBM_GFX_INDEX;
4816 si_pm4_set_reg(pm4, reg, value);
4817 }
4818
4819 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4820 struct si_pm4_state *pm4, unsigned se)
4821 {
4822 assert(se == ~0 || se < sctx->screen->info.max_se);
4823 si_set_grbm_gfx_index(sctx, pm4,
4824 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4825 S_030800_SE_INDEX(se)) |
4826 S_030800_SH_BROADCAST_WRITES(1) |
4827 S_030800_INSTANCE_BROADCAST_WRITES(1));
4828 }
4829
4830 static void
4831 si_write_harvested_raster_configs(struct si_context *sctx,
4832 struct si_pm4_state *pm4,
4833 unsigned raster_config,
4834 unsigned raster_config_1)
4835 {
4836 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4837 unsigned raster_config_se[4];
4838 unsigned se;
4839
4840 ac_get_harvested_configs(&sctx->screen->info,
4841 raster_config,
4842 &raster_config_1,
4843 raster_config_se);
4844
4845 for (se = 0; se < num_se; se++) {
4846 si_set_grbm_gfx_index_se(sctx, pm4, se);
4847 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4848 }
4849 si_set_grbm_gfx_index(sctx, pm4, ~0);
4850
4851 if (sctx->chip_class >= CIK) {
4852 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4853 }
4854 }
4855
4856 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4857 {
4858 struct si_screen *sscreen = sctx->screen;
4859 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4860 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4861 unsigned raster_config = sscreen->pa_sc_raster_config;
4862 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4863
4864 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4865 /* Always use the default config when all backends are enabled
4866 * (or when we failed to determine the enabled backends).
4867 */
4868 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4869 raster_config);
4870 if (sctx->chip_class >= CIK)
4871 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4872 raster_config_1);
4873 } else {
4874 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4875 }
4876 }
4877
4878 static void si_init_config(struct si_context *sctx)
4879 {
4880 struct si_screen *sscreen = sctx->screen;
4881 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4882 bool has_clear_state = sscreen->has_clear_state;
4883 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4884
4885 /* Only SI can disable CLEAR_STATE for now. */
4886 assert(has_clear_state || sscreen->info.chip_class == SI);
4887
4888 if (!pm4)
4889 return;
4890
4891 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4892 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4893 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4894 si_pm4_cmd_end(pm4, false);
4895
4896 if (has_clear_state) {
4897 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4898 si_pm4_cmd_add(pm4, 0);
4899 si_pm4_cmd_end(pm4, false);
4900 }
4901
4902 if (sctx->chip_class <= VI)
4903 si_set_raster_config(sctx, pm4);
4904
4905 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4906 if (!has_clear_state)
4907 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4908
4909 /* FIXME calculate these values somehow ??? */
4910 if (sctx->chip_class <= VI) {
4911 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4912 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4913 }
4914
4915 if (!has_clear_state) {
4916 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4917 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4918 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4919 }
4920
4921 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4922 if (!has_clear_state)
4923 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4924 if (sctx->chip_class < CIK)
4925 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4926 S_008A14_CLIP_VTX_REORDER_ENA(1));
4927
4928 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4929 * I don't know why. Deduced by trial and error.
4930 */
4931 if (sctx->chip_class <= CIK) {
4932 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4933 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4934 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4935 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4936 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4937 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4938 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4939 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4940 }
4941
4942 if (!has_clear_state) {
4943 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4944 S_028230_ER_TRI(0xA) |
4945 S_028230_ER_POINT(0xA) |
4946 S_028230_ER_RECT(0xA) |
4947 /* Required by DX10_DIAMOND_TEST_ENA: */
4948 S_028230_ER_LINE_LR(0x1A) |
4949 S_028230_ER_LINE_RL(0x26) |
4950 S_028230_ER_LINE_TB(0xA) |
4951 S_028230_ER_LINE_BT(0xA));
4952 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4953 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4954 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4955 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4956 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4957 }
4958
4959 if (sctx->chip_class >= GFX9) {
4960 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4961 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4962 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4963 } else {
4964 /* These registers, when written, also overwrite the CLEAR_STATE
4965 * context, so we can't rely on CLEAR_STATE setting them.
4966 * It would be an issue if there was another UMD changing them.
4967 */
4968 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4969 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4970 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4971 }
4972
4973 if (sctx->chip_class >= CIK) {
4974 if (sctx->chip_class >= GFX9) {
4975 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4976 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4977 } else {
4978 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4979 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4980 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4981 S_00B41C_WAVE_LIMIT(0x3F));
4982 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4983 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4984
4985 /* If this is 0, Bonaire can hang even if GS isn't being used.
4986 * Other chips are unaffected. These are suboptimal values,
4987 * but we don't use on-chip GS.
4988 */
4989 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4990 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4991 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4992 }
4993 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4994 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4995
4996 /* Compute LATE_ALLOC_VS.LIMIT. */
4997 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
4998 unsigned late_alloc_limit; /* The limit is per SH. */
4999
5000 if (sctx->family == CHIP_KABINI) {
5001 late_alloc_limit = 0; /* Potential hang on Kabini. */
5002 } else if (num_cu_per_sh <= 4) {
5003 /* Too few available compute units per SH. Disallowing
5004 * VS to run on one CU could hurt us more than late VS
5005 * allocation would help.
5006 *
5007 * 2 is the highest safe number that allows us to keep
5008 * all CUs enabled.
5009 */
5010 late_alloc_limit = 2;
5011 } else {
5012 /* This is a good initial value, allowing 1 late_alloc
5013 * wave per SIMD on num_cu - 2.
5014 */
5015 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5016
5017 /* The limit is 0-based, so 0 means 1. */
5018 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5019 late_alloc_limit -= 1;
5020 }
5021
5022 /* VS can't execute on one CU if the limit is > 2. */
5023 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5024 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5025 S_00B118_WAVE_LIMIT(0x3F));
5026 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5027 S_00B11C_LIMIT(late_alloc_limit));
5028 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5029 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5030 }
5031
5032 if (sctx->chip_class >= VI) {
5033 unsigned vgt_tess_distribution;
5034
5035 vgt_tess_distribution =
5036 S_028B50_ACCUM_ISOLINE(32) |
5037 S_028B50_ACCUM_TRI(11) |
5038 S_028B50_ACCUM_QUAD(11) |
5039 S_028B50_DONUT_SPLIT(16);
5040
5041 /* Testing with Unigine Heaven extreme tesselation yielded best results
5042 * with TRAP_SPLIT = 3.
5043 */
5044 if (sctx->family == CHIP_FIJI ||
5045 sctx->family >= CHIP_POLARIS10)
5046 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5047
5048 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5049 } else if (!has_clear_state) {
5050 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5051 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5052 }
5053
5054 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5055 if (sctx->chip_class >= CIK) {
5056 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5057 S_028084_ADDRESS(border_color_va >> 40));
5058 }
5059 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5060 RADEON_PRIO_BORDER_COLORS);
5061
5062 if (sctx->chip_class >= GFX9) {
5063 unsigned num_se = sscreen->info.max_se;
5064 unsigned pc_lines = 0;
5065
5066 switch (sctx->family) {
5067 case CHIP_VEGA10:
5068 case CHIP_VEGA12:
5069 case CHIP_VEGA20:
5070 pc_lines = 4096;
5071 break;
5072 case CHIP_RAVEN:
5073 pc_lines = 1024;
5074 break;
5075 default:
5076 assert(0);
5077 }
5078
5079 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5080 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5081 S_028C48_MAX_PRIM_PER_BATCH(1023));
5082 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5083 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5084 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5085 }
5086
5087 si_pm4_upload_indirect_buffer(sctx, pm4);
5088 sctx->init_config = pm4;
5089 }