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radeonsi: inline struct r600_cmask_info
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_cmdbuf *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
91 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
92
93 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
94 * I think we don't have to do anything between IBs.
95 */
96 if (sctx->screen->dfsm_allowed &&
97 sctx->last_cb_target_mask != cb_target_mask) {
98 sctx->last_cb_target_mask = cb_target_mask;
99
100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
102 }
103
104 if (sctx->chip_class >= VI) {
105 /* DCC MSAA workaround for blending.
106 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
107 * COMBINER_DISABLE, but that would be more complicated.
108 */
109 bool oc_disable = (sctx->chip_class == VI ||
110 sctx->chip_class == GFX9) &&
111 blend &&
112 blend->blend_enable_4bit & cb_target_mask &&
113 sctx->framebuffer.nr_samples >= 2;
114
115 radeon_opt_set_context_reg(
116 sctx, R_028424_CB_DCC_CONTROL,
117 SI_TRACKED_CB_DCC_CONTROL,
118 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
119 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
120 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
121 }
122
123 /* RB+ register settings. */
124 if (sctx->screen->rbplus_allowed) {
125 unsigned spi_shader_col_format =
126 sctx->ps_shader.cso ?
127 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
128 unsigned sx_ps_downconvert = 0;
129 unsigned sx_blend_opt_epsilon = 0;
130 unsigned sx_blend_opt_control = 0;
131
132 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
133 struct si_surface *surf =
134 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
135 unsigned format, swap, spi_format, colormask;
136 bool has_alpha, has_rgb;
137
138 if (!surf)
139 continue;
140
141 format = G_028C70_FORMAT(surf->cb_color_info);
142 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
143 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
144 colormask = (cb_target_mask >> (i * 4)) & 0xf;
145
146 /* Set if RGB and A are present. */
147 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
148
149 if (format == V_028C70_COLOR_8 ||
150 format == V_028C70_COLOR_16 ||
151 format == V_028C70_COLOR_32)
152 has_rgb = !has_alpha;
153 else
154 has_rgb = true;
155
156 /* Check the colormask and export format. */
157 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
158 has_rgb = false;
159 if (!(colormask & PIPE_MASK_A))
160 has_alpha = false;
161
162 if (spi_format == V_028714_SPI_SHADER_ZERO) {
163 has_rgb = false;
164 has_alpha = false;
165 }
166
167 /* Disable value checking for disabled channels. */
168 if (!has_rgb)
169 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
170 if (!has_alpha)
171 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
172
173 /* Enable down-conversion for 32bpp and smaller formats. */
174 switch (format) {
175 case V_028C70_COLOR_8:
176 case V_028C70_COLOR_8_8:
177 case V_028C70_COLOR_8_8_8_8:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
180 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
182 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
183 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
184 }
185 break;
186
187 case V_028C70_COLOR_5_6_5:
188 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
189 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
190 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
191 }
192 break;
193
194 case V_028C70_COLOR_1_5_5_5:
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
196 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
197 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
198 }
199 break;
200
201 case V_028C70_COLOR_4_4_4_4:
202 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
203 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
204 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
205 }
206 break;
207
208 case V_028C70_COLOR_32:
209 if (swap == V_028C70_SWAP_STD &&
210 spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV &&
213 spi_format == V_028714_SPI_SHADER_32_AR)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
215 break;
216
217 case V_028C70_COLOR_16:
218 case V_028C70_COLOR_16_16:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
224 if (swap == V_028C70_SWAP_STD ||
225 swap == V_028C70_SWAP_STD_REV)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
227 else
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
229 }
230 break;
231
232 case V_028C70_COLOR_10_11_11:
233 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
235 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
236 }
237 break;
238
239 case V_028C70_COLOR_2_10_10_10:
240 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
242 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
243 }
244 break;
245 }
246 }
247
248 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
249 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
250 SI_TRACKED_SX_PS_DOWNCONVERT,
251 sx_ps_downconvert, sx_blend_opt_epsilon,
252 sx_blend_opt_control);
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 PRINT_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 static void si_blend_check_commutativity(struct si_screen *sscreen,
374 struct si_state_blend *blend,
375 enum pipe_blend_func func,
376 enum pipe_blendfactor src,
377 enum pipe_blendfactor dst,
378 unsigned chanmask)
379 {
380 /* Src factor is allowed when it does not depend on Dst */
381 static const uint32_t src_allowed =
382 (1u << PIPE_BLENDFACTOR_ONE) |
383 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
384 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
386 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
387 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
389 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
397
398 if (dst == PIPE_BLENDFACTOR_ONE &&
399 (src_allowed & (1u << src))) {
400 /* Addition is commutative, but floating point addition isn't
401 * associative: subtle changes can be introduced via different
402 * rounding.
403 *
404 * Out-of-order is also non-deterministic, which means that
405 * this breaks OpenGL invariance requirements. So only enable
406 * out-of-order additive blending if explicitly allowed by a
407 * setting.
408 */
409 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
410 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
411 blend->commutative_4bit |= chanmask;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
425 *src_factor = PIPE_BLENDFACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == PIPE_BLEND_SUBTRACT)
430 *func = PIPE_BLEND_REVERSE_SUBTRACT;
431 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
432 *func = PIPE_BLEND_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
439 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
440 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
441 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
442 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
443 }
444
445 static void *si_create_blend_state_mode(struct pipe_context *ctx,
446 const struct pipe_blend_state *state,
447 unsigned mode)
448 {
449 struct si_context *sctx = (struct si_context*)ctx;
450 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
451 struct si_pm4_state *pm4 = &blend->pm4;
452 uint32_t sx_mrt_blend_opt[8] = {0};
453 uint32_t color_control = 0;
454
455 if (!blend)
456 return NULL;
457
458 blend->alpha_to_coverage = state->alpha_to_coverage;
459 blend->alpha_to_one = state->alpha_to_one;
460 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
461 blend->logicop_enable = state->logicop_enable;
462
463 if (state->logicop_enable) {
464 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
465 } else {
466 color_control |= S_028808_ROP3(0xcc);
467 }
468
469 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
472 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
475
476 if (state->alpha_to_coverage)
477 blend->need_src_alpha_4bit |= 0xf;
478
479 blend->cb_target_mask = 0;
480 blend->cb_target_enabled_4bit = 0;
481
482 for (int i = 0; i < 8; i++) {
483 /* state->rt entries > 0 only written if independent blending */
484 const int j = state->independent_blend_enable ? i : 0;
485
486 unsigned eqRGB = state->rt[j].rgb_func;
487 unsigned srcRGB = state->rt[j].rgb_src_factor;
488 unsigned dstRGB = state->rt[j].rgb_dst_factor;
489 unsigned eqA = state->rt[j].alpha_func;
490 unsigned srcA = state->rt[j].alpha_src_factor;
491 unsigned dstA = state->rt[j].alpha_dst_factor;
492
493 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
494 unsigned blend_cntl = 0;
495
496 sx_mrt_blend_opt[i] =
497 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
498 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
499
500 /* Only set dual source blending for MRT0 to avoid a hang. */
501 if (i >= 1 && blend->dual_src_blend) {
502 /* Vulkan does this for dual source blending. */
503 if (i == 1)
504 blend_cntl |= S_028780_ENABLE(1);
505
506 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
507 continue;
508 }
509
510 /* Only addition and subtraction equations are supported with
511 * dual source blending.
512 */
513 if (blend->dual_src_blend &&
514 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
515 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
518 continue;
519 }
520
521 /* cb_render_state will disable unused ones */
522 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
523 if (state->rt[j].colormask)
524 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
525
526 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 si_blend_check_commutativity(sctx->screen, blend,
532 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
533 si_blend_check_commutativity(sctx->screen, blend,
534 eqA, srcA, dstA, 0x8 << (4 * i));
535
536 /* Blending optimizations for RB+.
537 * These transformations don't change the behavior.
538 *
539 * First, get rid of DST in the blend factors:
540 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
541 */
542 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
543 PIPE_BLENDFACTOR_DST_COLOR,
544 PIPE_BLENDFACTOR_SRC_COLOR);
545 si_blend_remove_dst(&eqA, &srcA, &dstA,
546 PIPE_BLENDFACTOR_DST_COLOR,
547 PIPE_BLENDFACTOR_SRC_COLOR);
548 si_blend_remove_dst(&eqA, &srcA, &dstA,
549 PIPE_BLENDFACTOR_DST_ALPHA,
550 PIPE_BLENDFACTOR_SRC_ALPHA);
551
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
554 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
555 srcA_opt = si_translate_blend_opt_factor(srcA, true);
556 dstA_opt = si_translate_blend_opt_factor(dstA, true);
557
558 /* Handle interdependencies. */
559 if (si_blend_factor_uses_dst(srcRGB))
560 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
561 if (si_blend_factor_uses_dst(srcA))
562 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
563
564 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
565 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
566 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
567 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
568 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
569
570 /* Set the final value. */
571 sx_mrt_blend_opt[i] =
572 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
573 S_028760_COLOR_DST_OPT(dstRGB_opt) |
574 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
575 S_028760_ALPHA_SRC_OPT(srcA_opt) |
576 S_028760_ALPHA_DST_OPT(dstA_opt) |
577 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
578
579 /* Set blend state. */
580 blend_cntl |= S_028780_ENABLE(1);
581 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
582 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
583 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
584
585 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
586 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
587 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
588 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
589 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
590 }
591 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
592
593 blend->blend_enable_4bit |= 0xfu << (i * 4);
594
595 /* This is only important for formats without alpha. */
596 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
598 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
599 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
600 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
601 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
602 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
603 }
604
605 if (blend->cb_target_mask) {
606 color_control |= S_028808_MODE(mode);
607 } else {
608 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
609 }
610
611 if (sctx->screen->rbplus_allowed) {
612 /* Disable RB+ blend optimizations for dual source blending.
613 * Vulkan does this.
614 */
615 if (blend->dual_src_blend) {
616 for (int i = 0; i < 8; i++) {
617 sx_mrt_blend_opt[i] =
618 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
620 }
621 }
622
623 for (int i = 0; i < 8; i++)
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
625 sx_mrt_blend_opt[i]);
626
627 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
628 if (blend->dual_src_blend || state->logicop_enable ||
629 mode == V_028808_CB_RESOLVE)
630 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
631 }
632
633 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
634 return blend;
635 }
636
637 static void *si_create_blend_state(struct pipe_context *ctx,
638 const struct pipe_blend_state *state)
639 {
640 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
641 }
642
643 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 struct si_state_blend *old_blend = sctx->queued.named.blend;
647 struct si_state_blend *blend = (struct si_state_blend *)state;
648
649 if (!state)
650 return;
651
652 si_pm4_bind_state(sctx, blend, state);
653
654 if (!old_blend ||
655 old_blend->cb_target_mask != blend->cb_target_mask ||
656 old_blend->dual_src_blend != blend->dual_src_blend ||
657 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
658 sctx->framebuffer.nr_samples >= 2 &&
659 sctx->screen->dcc_msaa_allowed))
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
661
662 if (!old_blend ||
663 old_blend->cb_target_mask != blend->cb_target_mask ||
664 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
665 old_blend->alpha_to_one != blend->alpha_to_one ||
666 old_blend->dual_src_blend != blend->dual_src_blend ||
667 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
668 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
669 sctx->do_update_shaders = true;
670
671 if (sctx->screen->dpbb_allowed &&
672 (!old_blend ||
673 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
676 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
677
678 if (sctx->screen->has_out_of_order_rast &&
679 (!old_blend ||
680 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
681 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
682 old_blend->commutative_4bit != blend->commutative_4bit ||
683 old_blend->logicop_enable != blend->logicop_enable)))
684 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
685 }
686
687 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
691 }
692
693 static void si_set_blend_color(struct pipe_context *ctx,
694 const struct pipe_blend_color *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 static const struct pipe_blend_color zeros;
698
699 sctx->blend_color.state = *state;
700 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
701 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
702 }
703
704 static void si_emit_blend_color(struct si_context *sctx)
705 {
706 struct radeon_cmdbuf *cs = sctx->gfx_cs;
707
708 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
709 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
710 }
711
712 /*
713 * Clipping
714 */
715
716 static void si_set_clip_state(struct pipe_context *ctx,
717 const struct pipe_clip_state *state)
718 {
719 struct si_context *sctx = (struct si_context *)ctx;
720 struct pipe_constant_buffer cb;
721 static const struct pipe_clip_state zeros;
722
723 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
724 return;
725
726 sctx->clip_state.state = *state;
727 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
728 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
729
730 cb.buffer = NULL;
731 cb.user_buffer = state->ucp;
732 cb.buffer_offset = 0;
733 cb.buffer_size = 4*4*8;
734 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
735 pipe_resource_reference(&cb.buffer, NULL);
736 }
737
738 static void si_emit_clip_state(struct si_context *sctx)
739 {
740 struct radeon_cmdbuf *cs = sctx->gfx_cs;
741
742 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
743 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
744 }
745
746 static void si_emit_clip_regs(struct si_context *sctx)
747 {
748 struct si_shader *vs = si_get_vs_state(sctx);
749 struct si_shader_selector *vs_sel = vs->selector;
750 struct tgsi_shader_info *info = &vs_sel->info;
751 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
752 unsigned window_space =
753 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
754 unsigned clipdist_mask = vs_sel->clipdist_mask;
755 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
756 unsigned culldist_mask = vs_sel->culldist_mask;
757 unsigned total_mask;
758
759 if (vs->key.opt.clip_disable) {
760 assert(!info->culldist_writemask);
761 clipdist_mask = 0;
762 culldist_mask = 0;
763 }
764 total_mask = clipdist_mask | culldist_mask;
765
766 /* Clip distances on points have no effect, so need to be implemented
767 * as cull distances. This applies for the clipvertex case as well.
768 *
769 * Setting this for primitives other than points should have no adverse
770 * effects.
771 */
772 clipdist_mask &= rs->clip_plane_enable;
773 culldist_mask |= clipdist_mask;
774
775 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
776 SI_TRACKED_PA_CL_VS_OUT_CNTL,
777 vs_sel->pa_cl_vs_out_cntl |
778 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
779 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
780 clipdist_mask | (culldist_mask << 8));
781 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
782 SI_TRACKED_PA_CL_CLIP_CNTL,
783 rs->pa_cl_clip_cntl |
784 ucp_mask |
785 S_028810_CLIP_DISABLE(window_space));
786 }
787
788 /*
789 * inferred state between framebuffer and rasterizer
790 */
791 static void si_update_poly_offset_state(struct si_context *sctx)
792 {
793 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
794
795 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
796 si_pm4_bind_state(sctx, poly_offset, NULL);
797 return;
798 }
799
800 /* Use the user format, not db_render_format, so that the polygon
801 * offset behaves as expected by applications.
802 */
803 switch (sctx->framebuffer.state.zsbuf->texture->format) {
804 case PIPE_FORMAT_Z16_UNORM:
805 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
806 break;
807 default: /* 24-bit */
808 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
809 break;
810 case PIPE_FORMAT_Z32_FLOAT:
811 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
812 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
813 break;
814 }
815 }
816
817 /*
818 * Rasterizer
819 */
820
821 static uint32_t si_translate_fill(uint32_t func)
822 {
823 switch(func) {
824 case PIPE_POLYGON_MODE_FILL:
825 return V_028814_X_DRAW_TRIANGLES;
826 case PIPE_POLYGON_MODE_LINE:
827 return V_028814_X_DRAW_LINES;
828 case PIPE_POLYGON_MODE_POINT:
829 return V_028814_X_DRAW_POINTS;
830 default:
831 assert(0);
832 return V_028814_X_DRAW_POINTS;
833 }
834 }
835
836 static void *si_create_rs_state(struct pipe_context *ctx,
837 const struct pipe_rasterizer_state *state)
838 {
839 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
840 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
841 struct si_pm4_state *pm4 = &rs->pm4;
842 unsigned tmp, i;
843 float psize_min, psize_max;
844
845 if (!rs) {
846 return NULL;
847 }
848
849 rs->scissor_enable = state->scissor;
850 rs->clip_halfz = state->clip_halfz;
851 rs->two_side = state->light_twoside;
852 rs->multisample_enable = state->multisample;
853 rs->force_persample_interp = state->force_persample_interp;
854 rs->clip_plane_enable = state->clip_plane_enable;
855 rs->line_stipple_enable = state->line_stipple_enable;
856 rs->poly_stipple_enable = state->poly_stipple_enable;
857 rs->line_smooth = state->line_smooth;
858 rs->line_width = state->line_width;
859 rs->poly_smooth = state->poly_smooth;
860 rs->uses_poly_offset = state->offset_point || state->offset_line ||
861 state->offset_tri;
862 rs->clamp_fragment_color = state->clamp_fragment_color;
863 rs->clamp_vertex_color = state->clamp_vertex_color;
864 rs->flatshade = state->flatshade;
865 rs->sprite_coord_enable = state->sprite_coord_enable;
866 rs->rasterizer_discard = state->rasterizer_discard;
867 rs->pa_sc_line_stipple = state->line_stipple_enable ?
868 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
869 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
870 rs->pa_cl_clip_cntl =
871 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
872 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
873 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
874 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
875 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
876
877 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
878 S_0286D4_FLAT_SHADE_ENA(1) |
879 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
880 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
883 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
884 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
885
886 /* point size 12.4 fixed point */
887 tmp = (unsigned)(state->point_size * 8.0);
888 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
889
890 if (state->point_size_per_vertex) {
891 psize_min = util_get_min_point_size(state);
892 psize_max = 8192;
893 } else {
894 /* Force the point size to be as if the vertex output was disabled. */
895 psize_min = state->point_size;
896 psize_max = state->point_size;
897 }
898 rs->max_point_size = psize_max;
899
900 /* Divide by two, because 0.5 = 1 pixel. */
901 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
902 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
903 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
904
905 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
906 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
907 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
908 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
909 S_028A48_MSAA_ENABLE(state->multisample ||
910 state->poly_smooth ||
911 state->line_smooth) |
912 S_028A48_VPORT_SCISSOR_ENABLE(1) |
913 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
914
915 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
916 S_028BE4_PIX_CENTER(state->half_pixel_center) |
917 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
918
919 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
920 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
921 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
922 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
923 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
924 S_028814_FACE(!state->front_ccw) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
928 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
929 state->fill_back != PIPE_POLYGON_MODE_FILL) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
932
933 if (!rs->uses_poly_offset)
934 return rs;
935
936 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
937 if (!rs->pm4_poly_offset) {
938 FREE(rs);
939 return NULL;
940 }
941
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i = 0; i < 3; i++) {
944 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
945 float offset_units = state->offset_units;
946 float offset_scale = state->offset_scale * 16.0f;
947 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
948
949 if (!state->offset_units_unscaled) {
950 switch (i) {
951 case 0: /* 16-bit zbuffer */
952 offset_units *= 4.0f;
953 pa_su_poly_offset_db_fmt_cntl =
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
955 break;
956 case 1: /* 24-bit zbuffer */
957 offset_units *= 2.0f;
958 pa_su_poly_offset_db_fmt_cntl =
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
960 break;
961 case 2: /* 32-bit zbuffer */
962 offset_units *= 1.0f;
963 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
964 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
965 break;
966 }
967 }
968
969 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
970 fui(offset_scale));
971 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
972 fui(offset_units));
973 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
974 fui(offset_scale));
975 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
976 fui(offset_units));
977 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
978 pa_su_poly_offset_db_fmt_cntl);
979 }
980
981 return rs;
982 }
983
984 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
985 {
986 struct si_context *sctx = (struct si_context *)ctx;
987 struct si_state_rasterizer *old_rs =
988 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
989 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
990
991 if (!state)
992 return;
993
994 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
995 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
996
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx->screen->has_msaa_sample_loc_bug &&
999 sctx->framebuffer.nr_samples > 1)
1000 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
1001 }
1002
1003 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1004 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1005
1006 si_pm4_bind_state(sctx, rasterizer, rs);
1007 si_update_poly_offset_state(sctx);
1008
1009 if (!old_rs ||
1010 old_rs->scissor_enable != rs->scissor_enable) {
1011 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1012 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1013 }
1014
1015 if (!old_rs ||
1016 old_rs->line_width != rs->line_width ||
1017 old_rs->max_point_size != rs->max_point_size)
1018 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1019
1020 if (!old_rs ||
1021 old_rs->clip_halfz != rs->clip_halfz) {
1022 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1023 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1024 }
1025
1026 if (!old_rs ||
1027 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1028 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1029 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1030
1031 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1032 rs->line_stipple_enable;
1033
1034 if (!old_rs ||
1035 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1036 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1037 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1038 old_rs->flatshade != rs->flatshade ||
1039 old_rs->two_side != rs->two_side ||
1040 old_rs->multisample_enable != rs->multisample_enable ||
1041 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1042 old_rs->poly_smooth != rs->poly_smooth ||
1043 old_rs->line_smooth != rs->line_smooth ||
1044 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1045 old_rs->force_persample_interp != rs->force_persample_interp)
1046 sctx->do_update_shaders = true;
1047 }
1048
1049 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1050 {
1051 struct si_context *sctx = (struct si_context *)ctx;
1052 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1053
1054 if (sctx->queued.named.rasterizer == state)
1055 si_pm4_bind_state(sctx, poly_offset, NULL);
1056
1057 FREE(rs->pm4_poly_offset);
1058 si_pm4_delete_state(sctx, rasterizer, rs);
1059 }
1060
1061 /*
1062 * infeered state between dsa and stencil ref
1063 */
1064 static void si_emit_stencil_ref(struct si_context *sctx)
1065 {
1066 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1067 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1068 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1069
1070 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1071 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1072 S_028430_STENCILMASK(dsa->valuemask[0]) |
1073 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1074 S_028430_STENCILOPVAL(1));
1075 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1076 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1077 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1078 S_028434_STENCILOPVAL_BF(1));
1079 }
1080
1081 static void si_set_stencil_ref(struct pipe_context *ctx,
1082 const struct pipe_stencil_ref *state)
1083 {
1084 struct si_context *sctx = (struct si_context *)ctx;
1085
1086 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1087 return;
1088
1089 sctx->stencil_ref.state = *state;
1090 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1091 }
1092
1093
1094 /*
1095 * DSA
1096 */
1097
1098 static uint32_t si_translate_stencil_op(int s_op)
1099 {
1100 switch (s_op) {
1101 case PIPE_STENCIL_OP_KEEP:
1102 return V_02842C_STENCIL_KEEP;
1103 case PIPE_STENCIL_OP_ZERO:
1104 return V_02842C_STENCIL_ZERO;
1105 case PIPE_STENCIL_OP_REPLACE:
1106 return V_02842C_STENCIL_REPLACE_TEST;
1107 case PIPE_STENCIL_OP_INCR:
1108 return V_02842C_STENCIL_ADD_CLAMP;
1109 case PIPE_STENCIL_OP_DECR:
1110 return V_02842C_STENCIL_SUB_CLAMP;
1111 case PIPE_STENCIL_OP_INCR_WRAP:
1112 return V_02842C_STENCIL_ADD_WRAP;
1113 case PIPE_STENCIL_OP_DECR_WRAP:
1114 return V_02842C_STENCIL_SUB_WRAP;
1115 case PIPE_STENCIL_OP_INVERT:
1116 return V_02842C_STENCIL_INVERT;
1117 default:
1118 PRINT_ERR("Unknown stencil op %d", s_op);
1119 assert(0);
1120 break;
1121 }
1122 return 0;
1123 }
1124
1125 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1126 {
1127 return s->enabled && s->writemask &&
1128 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1129 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1130 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1131 }
1132
1133 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1134 {
1135 /* REPLACE is normally order invariant, except when the stencil
1136 * reference value is written by the fragment shader. Tracking this
1137 * interaction does not seem worth the effort, so be conservative. */
1138 return op != PIPE_STENCIL_OP_INCR &&
1139 op != PIPE_STENCIL_OP_DECR &&
1140 op != PIPE_STENCIL_OP_REPLACE;
1141 }
1142
1143 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1144 * invariant in the sense that the set of passing fragments as well as the
1145 * final stencil buffer result does not depend on the order of fragments. */
1146 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1147 {
1148 return !state->enabled || !state->writemask ||
1149 /* The following assumes that Z writes are disabled. */
1150 (state->func == PIPE_FUNC_ALWAYS &&
1151 si_order_invariant_stencil_op(state->zpass_op) &&
1152 si_order_invariant_stencil_op(state->zfail_op)) ||
1153 (state->func == PIPE_FUNC_NEVER &&
1154 si_order_invariant_stencil_op(state->fail_op));
1155 }
1156
1157 static void *si_create_dsa_state(struct pipe_context *ctx,
1158 const struct pipe_depth_stencil_alpha_state *state)
1159 {
1160 struct si_context *sctx = (struct si_context *)ctx;
1161 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1162 struct si_pm4_state *pm4 = &dsa->pm4;
1163 unsigned db_depth_control;
1164 uint32_t db_stencil_control = 0;
1165
1166 if (!dsa) {
1167 return NULL;
1168 }
1169
1170 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1171 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1172 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1173 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1174
1175 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1176 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1177 S_028800_ZFUNC(state->depth.func) |
1178 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1179
1180 /* stencil */
1181 if (state->stencil[0].enabled) {
1182 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1183 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1184 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1185 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1186 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1187
1188 if (state->stencil[1].enabled) {
1189 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1190 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1191 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1192 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1193 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1194 }
1195 }
1196
1197 /* alpha */
1198 if (state->alpha.enabled) {
1199 dsa->alpha_func = state->alpha.func;
1200
1201 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1202 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1203 } else {
1204 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1205 }
1206
1207 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1208 if (state->stencil[0].enabled)
1209 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1210 if (state->depth.bounds_test) {
1211 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1212 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1213 }
1214
1215 dsa->depth_enabled = state->depth.enabled;
1216 dsa->depth_write_enabled = state->depth.enabled &&
1217 state->depth.writemask;
1218 dsa->stencil_enabled = state->stencil[0].enabled;
1219 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1220 (si_dsa_writes_stencil(&state->stencil[0]) ||
1221 si_dsa_writes_stencil(&state->stencil[1]));
1222 dsa->db_can_write = dsa->depth_write_enabled ||
1223 dsa->stencil_write_enabled;
1224
1225 bool zfunc_is_ordered =
1226 state->depth.func == PIPE_FUNC_NEVER ||
1227 state->depth.func == PIPE_FUNC_LESS ||
1228 state->depth.func == PIPE_FUNC_LEQUAL ||
1229 state->depth.func == PIPE_FUNC_GREATER ||
1230 state->depth.func == PIPE_FUNC_GEQUAL;
1231
1232 bool nozwrite_and_order_invariant_stencil =
1233 !dsa->db_can_write ||
1234 (!dsa->depth_write_enabled &&
1235 si_order_invariant_stencil_state(&state->stencil[0]) &&
1236 si_order_invariant_stencil_state(&state->stencil[1]));
1237
1238 dsa->order_invariance[1].zs =
1239 nozwrite_and_order_invariant_stencil ||
1240 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1241 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1242
1243 dsa->order_invariance[1].pass_set =
1244 nozwrite_and_order_invariant_stencil ||
1245 (!dsa->stencil_write_enabled &&
1246 (state->depth.func == PIPE_FUNC_ALWAYS ||
1247 state->depth.func == PIPE_FUNC_NEVER));
1248 dsa->order_invariance[0].pass_set =
1249 !dsa->depth_write_enabled ||
1250 (state->depth.func == PIPE_FUNC_ALWAYS ||
1251 state->depth.func == PIPE_FUNC_NEVER);
1252
1253 dsa->order_invariance[1].pass_last =
1254 sctx->screen->assume_no_z_fights &&
1255 !dsa->stencil_write_enabled &&
1256 dsa->depth_write_enabled && zfunc_is_ordered;
1257 dsa->order_invariance[0].pass_last =
1258 sctx->screen->assume_no_z_fights &&
1259 dsa->depth_write_enabled && zfunc_is_ordered;
1260
1261 return dsa;
1262 }
1263
1264 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1265 {
1266 struct si_context *sctx = (struct si_context *)ctx;
1267 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1268 struct si_state_dsa *dsa = state;
1269
1270 if (!state)
1271 return;
1272
1273 si_pm4_bind_state(sctx, dsa, dsa);
1274
1275 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1276 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1277 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1278 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1279 }
1280
1281 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1282 sctx->do_update_shaders = true;
1283
1284 if (sctx->screen->dpbb_allowed &&
1285 (!old_dsa ||
1286 (old_dsa->depth_enabled != dsa->depth_enabled ||
1287 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1288 old_dsa->db_can_write != dsa->db_can_write)))
1289 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1290
1291 if (sctx->screen->has_out_of_order_rast &&
1292 (!old_dsa ||
1293 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1294 sizeof(old_dsa->order_invariance))))
1295 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1296 }
1297
1298 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1299 {
1300 struct si_context *sctx = (struct si_context *)ctx;
1301 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1302 }
1303
1304 static void *si_create_db_flush_dsa(struct si_context *sctx)
1305 {
1306 struct pipe_depth_stencil_alpha_state dsa = {};
1307
1308 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1309 }
1310
1311 /* DB RENDER STATE */
1312
1313 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1314 {
1315 struct si_context *sctx = (struct si_context*)ctx;
1316
1317 /* Pipeline stat & streamout queries. */
1318 if (enable) {
1319 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1320 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1321 } else {
1322 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1323 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1324 }
1325
1326 /* Occlusion queries. */
1327 if (sctx->occlusion_queries_disabled != !enable) {
1328 sctx->occlusion_queries_disabled = !enable;
1329 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1330 }
1331 }
1332
1333 void si_set_occlusion_query_state(struct si_context *sctx,
1334 bool old_perfect_enable)
1335 {
1336 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1337
1338 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1339
1340 if (perfect_enable != old_perfect_enable)
1341 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1342 }
1343
1344 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1345 {
1346 st->saved_compute = sctx->cs_shader_state.program;
1347
1348 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1349 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1350 }
1351
1352 static void si_emit_db_render_state(struct si_context *sctx)
1353 {
1354 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1355 unsigned db_shader_control, db_render_control, db_count_control;
1356
1357 /* DB_RENDER_CONTROL */
1358 if (sctx->dbcb_depth_copy_enabled ||
1359 sctx->dbcb_stencil_copy_enabled) {
1360 db_render_control =
1361 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1362 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1363 S_028000_COPY_CENTROID(1) |
1364 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1365 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1366 db_render_control =
1367 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1368 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1369 } else {
1370 db_render_control =
1371 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1372 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1373 }
1374
1375 /* DB_COUNT_CONTROL (occlusion queries) */
1376 if (sctx->num_occlusion_queries > 0 &&
1377 !sctx->occlusion_queries_disabled) {
1378 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1379
1380 if (sctx->chip_class >= CIK) {
1381 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1382
1383 /* Stoney doesn't increment occlusion query counters
1384 * if the sample rate is 16x. Use 8x sample rate instead.
1385 */
1386 if (sctx->family == CHIP_STONEY)
1387 log_sample_rate = MIN2(log_sample_rate, 3);
1388
1389 db_count_control =
1390 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1391 S_028004_SAMPLE_RATE(log_sample_rate) |
1392 S_028004_ZPASS_ENABLE(1) |
1393 S_028004_SLICE_EVEN_ENABLE(1) |
1394 S_028004_SLICE_ODD_ENABLE(1);
1395 } else {
1396 db_count_control =
1397 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1398 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1399 }
1400 } else {
1401 /* Disable occlusion queries. */
1402 if (sctx->chip_class >= CIK) {
1403 db_count_control = 0;
1404 } else {
1405 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1406 }
1407 }
1408
1409 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1410 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1411 db_count_control);
1412
1413 /* DB_RENDER_OVERRIDE2 */
1414 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1415 SI_TRACKED_DB_RENDER_OVERRIDE2,
1416 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1417 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1418 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1419
1420 db_shader_control = sctx->ps_db_shader_control;
1421
1422 /* Bug workaround for smoothing (overrasterization) on SI. */
1423 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1424 db_shader_control &= C_02880C_Z_ORDER;
1425 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1426 }
1427
1428 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1429 if (!rs->multisample_enable)
1430 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1431
1432 if (sctx->screen->has_rbplus &&
1433 !sctx->screen->rbplus_allowed)
1434 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1435
1436 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1437 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1438 }
1439
1440 /*
1441 * format translation
1442 */
1443 static uint32_t si_translate_colorformat(enum pipe_format format)
1444 {
1445 const struct util_format_description *desc = util_format_description(format);
1446 if (!desc)
1447 return V_028C70_COLOR_INVALID;
1448
1449 #define HAS_SIZE(x,y,z,w) \
1450 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1451 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1452
1453 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1454 return V_028C70_COLOR_10_11_11;
1455
1456 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1457 return V_028C70_COLOR_INVALID;
1458
1459 /* hw cannot support mixed formats (except depth/stencil, since
1460 * stencil is not written to). */
1461 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1462 return V_028C70_COLOR_INVALID;
1463
1464 switch (desc->nr_channels) {
1465 case 1:
1466 switch (desc->channel[0].size) {
1467 case 8:
1468 return V_028C70_COLOR_8;
1469 case 16:
1470 return V_028C70_COLOR_16;
1471 case 32:
1472 return V_028C70_COLOR_32;
1473 }
1474 break;
1475 case 2:
1476 if (desc->channel[0].size == desc->channel[1].size) {
1477 switch (desc->channel[0].size) {
1478 case 8:
1479 return V_028C70_COLOR_8_8;
1480 case 16:
1481 return V_028C70_COLOR_16_16;
1482 case 32:
1483 return V_028C70_COLOR_32_32;
1484 }
1485 } else if (HAS_SIZE(8,24,0,0)) {
1486 return V_028C70_COLOR_24_8;
1487 } else if (HAS_SIZE(24,8,0,0)) {
1488 return V_028C70_COLOR_8_24;
1489 }
1490 break;
1491 case 3:
1492 if (HAS_SIZE(5,6,5,0)) {
1493 return V_028C70_COLOR_5_6_5;
1494 } else if (HAS_SIZE(32,8,24,0)) {
1495 return V_028C70_COLOR_X24_8_32_FLOAT;
1496 }
1497 break;
1498 case 4:
1499 if (desc->channel[0].size == desc->channel[1].size &&
1500 desc->channel[0].size == desc->channel[2].size &&
1501 desc->channel[0].size == desc->channel[3].size) {
1502 switch (desc->channel[0].size) {
1503 case 4:
1504 return V_028C70_COLOR_4_4_4_4;
1505 case 8:
1506 return V_028C70_COLOR_8_8_8_8;
1507 case 16:
1508 return V_028C70_COLOR_16_16_16_16;
1509 case 32:
1510 return V_028C70_COLOR_32_32_32_32;
1511 }
1512 } else if (HAS_SIZE(5,5,5,1)) {
1513 return V_028C70_COLOR_1_5_5_5;
1514 } else if (HAS_SIZE(1,5,5,5)) {
1515 return V_028C70_COLOR_5_5_5_1;
1516 } else if (HAS_SIZE(10,10,10,2)) {
1517 return V_028C70_COLOR_2_10_10_10;
1518 }
1519 break;
1520 }
1521 return V_028C70_COLOR_INVALID;
1522 }
1523
1524 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1525 {
1526 if (SI_BIG_ENDIAN) {
1527 switch(colorformat) {
1528 /* 8-bit buffers. */
1529 case V_028C70_COLOR_8:
1530 return V_028C70_ENDIAN_NONE;
1531
1532 /* 16-bit buffers. */
1533 case V_028C70_COLOR_5_6_5:
1534 case V_028C70_COLOR_1_5_5_5:
1535 case V_028C70_COLOR_4_4_4_4:
1536 case V_028C70_COLOR_16:
1537 case V_028C70_COLOR_8_8:
1538 return V_028C70_ENDIAN_8IN16;
1539
1540 /* 32-bit buffers. */
1541 case V_028C70_COLOR_8_8_8_8:
1542 case V_028C70_COLOR_2_10_10_10:
1543 case V_028C70_COLOR_8_24:
1544 case V_028C70_COLOR_24_8:
1545 case V_028C70_COLOR_16_16:
1546 return V_028C70_ENDIAN_8IN32;
1547
1548 /* 64-bit buffers. */
1549 case V_028C70_COLOR_16_16_16_16:
1550 return V_028C70_ENDIAN_8IN16;
1551
1552 case V_028C70_COLOR_32_32:
1553 return V_028C70_ENDIAN_8IN32;
1554
1555 /* 128-bit buffers. */
1556 case V_028C70_COLOR_32_32_32_32:
1557 return V_028C70_ENDIAN_8IN32;
1558 default:
1559 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1560 }
1561 } else {
1562 return V_028C70_ENDIAN_NONE;
1563 }
1564 }
1565
1566 static uint32_t si_translate_dbformat(enum pipe_format format)
1567 {
1568 switch (format) {
1569 case PIPE_FORMAT_Z16_UNORM:
1570 return V_028040_Z_16;
1571 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1572 case PIPE_FORMAT_X8Z24_UNORM:
1573 case PIPE_FORMAT_Z24X8_UNORM:
1574 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1575 return V_028040_Z_24; /* deprecated on SI */
1576 case PIPE_FORMAT_Z32_FLOAT:
1577 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1578 return V_028040_Z_32_FLOAT;
1579 default:
1580 return V_028040_Z_INVALID;
1581 }
1582 }
1583
1584 /*
1585 * Texture translation
1586 */
1587
1588 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1589 enum pipe_format format,
1590 const struct util_format_description *desc,
1591 int first_non_void)
1592 {
1593 struct si_screen *sscreen = (struct si_screen*)screen;
1594 bool uniform = true;
1595 int i;
1596
1597 /* Colorspace (return non-RGB formats directly). */
1598 switch (desc->colorspace) {
1599 /* Depth stencil formats */
1600 case UTIL_FORMAT_COLORSPACE_ZS:
1601 switch (format) {
1602 case PIPE_FORMAT_Z16_UNORM:
1603 return V_008F14_IMG_DATA_FORMAT_16;
1604 case PIPE_FORMAT_X24S8_UINT:
1605 case PIPE_FORMAT_S8X24_UINT:
1606 /*
1607 * Implemented as an 8_8_8_8 data format to fix texture
1608 * gathers in stencil sampling. This affects at least
1609 * GL45-CTS.texture_cube_map_array.sampling on VI.
1610 */
1611 if (sscreen->info.chip_class <= VI)
1612 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1613
1614 if (format == PIPE_FORMAT_X24S8_UINT)
1615 return V_008F14_IMG_DATA_FORMAT_8_24;
1616 else
1617 return V_008F14_IMG_DATA_FORMAT_24_8;
1618 case PIPE_FORMAT_Z24X8_UNORM:
1619 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1620 return V_008F14_IMG_DATA_FORMAT_8_24;
1621 case PIPE_FORMAT_X8Z24_UNORM:
1622 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1623 return V_008F14_IMG_DATA_FORMAT_24_8;
1624 case PIPE_FORMAT_S8_UINT:
1625 return V_008F14_IMG_DATA_FORMAT_8;
1626 case PIPE_FORMAT_Z32_FLOAT:
1627 return V_008F14_IMG_DATA_FORMAT_32;
1628 case PIPE_FORMAT_X32_S8X24_UINT:
1629 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1630 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1631 default:
1632 goto out_unknown;
1633 }
1634
1635 case UTIL_FORMAT_COLORSPACE_YUV:
1636 goto out_unknown; /* TODO */
1637
1638 case UTIL_FORMAT_COLORSPACE_SRGB:
1639 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1640 goto out_unknown;
1641 break;
1642
1643 default:
1644 break;
1645 }
1646
1647 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1648 if (!sscreen->info.has_format_bc1_through_bc7)
1649 goto out_unknown;
1650
1651 switch (format) {
1652 case PIPE_FORMAT_RGTC1_SNORM:
1653 case PIPE_FORMAT_LATC1_SNORM:
1654 case PIPE_FORMAT_RGTC1_UNORM:
1655 case PIPE_FORMAT_LATC1_UNORM:
1656 return V_008F14_IMG_DATA_FORMAT_BC4;
1657 case PIPE_FORMAT_RGTC2_SNORM:
1658 case PIPE_FORMAT_LATC2_SNORM:
1659 case PIPE_FORMAT_RGTC2_UNORM:
1660 case PIPE_FORMAT_LATC2_UNORM:
1661 return V_008F14_IMG_DATA_FORMAT_BC5;
1662 default:
1663 goto out_unknown;
1664 }
1665 }
1666
1667 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1668 (sscreen->info.family == CHIP_STONEY ||
1669 sscreen->info.family == CHIP_VEGA10 ||
1670 sscreen->info.family == CHIP_RAVEN)) {
1671 switch (format) {
1672 case PIPE_FORMAT_ETC1_RGB8:
1673 case PIPE_FORMAT_ETC2_RGB8:
1674 case PIPE_FORMAT_ETC2_SRGB8:
1675 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1676 case PIPE_FORMAT_ETC2_RGB8A1:
1677 case PIPE_FORMAT_ETC2_SRGB8A1:
1678 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1679 case PIPE_FORMAT_ETC2_RGBA8:
1680 case PIPE_FORMAT_ETC2_SRGBA8:
1681 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1682 case PIPE_FORMAT_ETC2_R11_UNORM:
1683 case PIPE_FORMAT_ETC2_R11_SNORM:
1684 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1685 case PIPE_FORMAT_ETC2_RG11_UNORM:
1686 case PIPE_FORMAT_ETC2_RG11_SNORM:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1688 default:
1689 goto out_unknown;
1690 }
1691 }
1692
1693 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1694 if (!sscreen->info.has_format_bc1_through_bc7)
1695 goto out_unknown;
1696
1697 switch (format) {
1698 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1699 case PIPE_FORMAT_BPTC_SRGBA:
1700 return V_008F14_IMG_DATA_FORMAT_BC7;
1701 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1702 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1703 return V_008F14_IMG_DATA_FORMAT_BC6;
1704 default:
1705 goto out_unknown;
1706 }
1707 }
1708
1709 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1710 switch (format) {
1711 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1712 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1713 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1714 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1715 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1716 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1717 default:
1718 goto out_unknown;
1719 }
1720 }
1721
1722 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1723 if (!sscreen->info.has_format_bc1_through_bc7)
1724 goto out_unknown;
1725
1726 switch (format) {
1727 case PIPE_FORMAT_DXT1_RGB:
1728 case PIPE_FORMAT_DXT1_RGBA:
1729 case PIPE_FORMAT_DXT1_SRGB:
1730 case PIPE_FORMAT_DXT1_SRGBA:
1731 return V_008F14_IMG_DATA_FORMAT_BC1;
1732 case PIPE_FORMAT_DXT3_RGBA:
1733 case PIPE_FORMAT_DXT3_SRGBA:
1734 return V_008F14_IMG_DATA_FORMAT_BC2;
1735 case PIPE_FORMAT_DXT5_RGBA:
1736 case PIPE_FORMAT_DXT5_SRGBA:
1737 return V_008F14_IMG_DATA_FORMAT_BC3;
1738 default:
1739 goto out_unknown;
1740 }
1741 }
1742
1743 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1744 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1745 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1746 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1747 }
1748
1749 /* R8G8Bx_SNORM - TODO CxV8U8 */
1750
1751 /* hw cannot support mixed formats (except depth/stencil, since only
1752 * depth is read).*/
1753 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1754 goto out_unknown;
1755
1756 /* See whether the components are of the same size. */
1757 for (i = 1; i < desc->nr_channels; i++) {
1758 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1759 }
1760
1761 /* Non-uniform formats. */
1762 if (!uniform) {
1763 switch(desc->nr_channels) {
1764 case 3:
1765 if (desc->channel[0].size == 5 &&
1766 desc->channel[1].size == 6 &&
1767 desc->channel[2].size == 5) {
1768 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1769 }
1770 goto out_unknown;
1771 case 4:
1772 if (desc->channel[0].size == 5 &&
1773 desc->channel[1].size == 5 &&
1774 desc->channel[2].size == 5 &&
1775 desc->channel[3].size == 1) {
1776 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1777 }
1778 if (desc->channel[0].size == 1 &&
1779 desc->channel[1].size == 5 &&
1780 desc->channel[2].size == 5 &&
1781 desc->channel[3].size == 5) {
1782 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1783 }
1784 if (desc->channel[0].size == 10 &&
1785 desc->channel[1].size == 10 &&
1786 desc->channel[2].size == 10 &&
1787 desc->channel[3].size == 2) {
1788 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1789 }
1790 goto out_unknown;
1791 }
1792 goto out_unknown;
1793 }
1794
1795 if (first_non_void < 0 || first_non_void > 3)
1796 goto out_unknown;
1797
1798 /* uniform formats */
1799 switch (desc->channel[first_non_void].size) {
1800 case 4:
1801 switch (desc->nr_channels) {
1802 #if 0 /* Not supported for render targets */
1803 case 2:
1804 return V_008F14_IMG_DATA_FORMAT_4_4;
1805 #endif
1806 case 4:
1807 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1808 }
1809 break;
1810 case 8:
1811 switch (desc->nr_channels) {
1812 case 1:
1813 return V_008F14_IMG_DATA_FORMAT_8;
1814 case 2:
1815 return V_008F14_IMG_DATA_FORMAT_8_8;
1816 case 4:
1817 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1818 }
1819 break;
1820 case 16:
1821 switch (desc->nr_channels) {
1822 case 1:
1823 return V_008F14_IMG_DATA_FORMAT_16;
1824 case 2:
1825 return V_008F14_IMG_DATA_FORMAT_16_16;
1826 case 4:
1827 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1828 }
1829 break;
1830 case 32:
1831 switch (desc->nr_channels) {
1832 case 1:
1833 return V_008F14_IMG_DATA_FORMAT_32;
1834 case 2:
1835 return V_008F14_IMG_DATA_FORMAT_32_32;
1836 #if 0 /* Not supported for render targets */
1837 case 3:
1838 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1839 #endif
1840 case 4:
1841 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1842 }
1843 }
1844
1845 out_unknown:
1846 return ~0;
1847 }
1848
1849 static unsigned si_tex_wrap(unsigned wrap)
1850 {
1851 switch (wrap) {
1852 default:
1853 case PIPE_TEX_WRAP_REPEAT:
1854 return V_008F30_SQ_TEX_WRAP;
1855 case PIPE_TEX_WRAP_CLAMP:
1856 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1857 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1858 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1859 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1860 return V_008F30_SQ_TEX_CLAMP_BORDER;
1861 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1862 return V_008F30_SQ_TEX_MIRROR;
1863 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1864 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1865 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1866 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1867 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1868 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1869 }
1870 }
1871
1872 static unsigned si_tex_mipfilter(unsigned filter)
1873 {
1874 switch (filter) {
1875 case PIPE_TEX_MIPFILTER_NEAREST:
1876 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1877 case PIPE_TEX_MIPFILTER_LINEAR:
1878 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1879 default:
1880 case PIPE_TEX_MIPFILTER_NONE:
1881 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1882 }
1883 }
1884
1885 static unsigned si_tex_compare(unsigned compare)
1886 {
1887 switch (compare) {
1888 default:
1889 case PIPE_FUNC_NEVER:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1891 case PIPE_FUNC_LESS:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1893 case PIPE_FUNC_EQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1895 case PIPE_FUNC_LEQUAL:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1897 case PIPE_FUNC_GREATER:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1899 case PIPE_FUNC_NOTEQUAL:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1901 case PIPE_FUNC_GEQUAL:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1903 case PIPE_FUNC_ALWAYS:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1905 }
1906 }
1907
1908 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1909 unsigned view_target, unsigned nr_samples)
1910 {
1911 unsigned res_target = tex->buffer.b.b.target;
1912
1913 if (view_target == PIPE_TEXTURE_CUBE ||
1914 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1915 res_target = view_target;
1916 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1917 else if (res_target == PIPE_TEXTURE_CUBE ||
1918 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1919 res_target = PIPE_TEXTURE_2D_ARRAY;
1920
1921 /* GFX9 allocates 1D textures as 2D. */
1922 if ((res_target == PIPE_TEXTURE_1D ||
1923 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1924 sscreen->info.chip_class >= GFX9 &&
1925 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1926 if (res_target == PIPE_TEXTURE_1D)
1927 res_target = PIPE_TEXTURE_2D;
1928 else
1929 res_target = PIPE_TEXTURE_2D_ARRAY;
1930 }
1931
1932 switch (res_target) {
1933 default:
1934 case PIPE_TEXTURE_1D:
1935 return V_008F1C_SQ_RSRC_IMG_1D;
1936 case PIPE_TEXTURE_1D_ARRAY:
1937 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1938 case PIPE_TEXTURE_2D:
1939 case PIPE_TEXTURE_RECT:
1940 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1941 V_008F1C_SQ_RSRC_IMG_2D;
1942 case PIPE_TEXTURE_2D_ARRAY:
1943 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1944 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1945 case PIPE_TEXTURE_3D:
1946 return V_008F1C_SQ_RSRC_IMG_3D;
1947 case PIPE_TEXTURE_CUBE:
1948 case PIPE_TEXTURE_CUBE_ARRAY:
1949 return V_008F1C_SQ_RSRC_IMG_CUBE;
1950 }
1951 }
1952
1953 /*
1954 * Format support testing
1955 */
1956
1957 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1958 {
1959 const struct util_format_description *desc = util_format_description(format);
1960 if (!desc)
1961 return false;
1962
1963 return si_translate_texformat(screen, format, desc,
1964 util_format_get_first_non_void_channel(format)) != ~0U;
1965 }
1966
1967 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1968 const struct util_format_description *desc,
1969 int first_non_void)
1970 {
1971 int i;
1972
1973 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1974 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1975
1976 assert(first_non_void >= 0);
1977
1978 if (desc->nr_channels == 4 &&
1979 desc->channel[0].size == 10 &&
1980 desc->channel[1].size == 10 &&
1981 desc->channel[2].size == 10 &&
1982 desc->channel[3].size == 2)
1983 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1984
1985 /* See whether the components are of the same size. */
1986 for (i = 0; i < desc->nr_channels; i++) {
1987 if (desc->channel[first_non_void].size != desc->channel[i].size)
1988 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1989 }
1990
1991 switch (desc->channel[first_non_void].size) {
1992 case 8:
1993 switch (desc->nr_channels) {
1994 case 1:
1995 case 3: /* 3 loads */
1996 return V_008F0C_BUF_DATA_FORMAT_8;
1997 case 2:
1998 return V_008F0C_BUF_DATA_FORMAT_8_8;
1999 case 4:
2000 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2001 }
2002 break;
2003 case 16:
2004 switch (desc->nr_channels) {
2005 case 1:
2006 case 3: /* 3 loads */
2007 return V_008F0C_BUF_DATA_FORMAT_16;
2008 case 2:
2009 return V_008F0C_BUF_DATA_FORMAT_16_16;
2010 case 4:
2011 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2012 }
2013 break;
2014 case 32:
2015 switch (desc->nr_channels) {
2016 case 1:
2017 return V_008F0C_BUF_DATA_FORMAT_32;
2018 case 2:
2019 return V_008F0C_BUF_DATA_FORMAT_32_32;
2020 case 3:
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2022 case 4:
2023 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2024 }
2025 break;
2026 case 64:
2027 /* Legacy double formats. */
2028 switch (desc->nr_channels) {
2029 case 1: /* 1 load */
2030 return V_008F0C_BUF_DATA_FORMAT_32_32;
2031 case 2: /* 1 load */
2032 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2033 case 3: /* 3 loads */
2034 return V_008F0C_BUF_DATA_FORMAT_32_32;
2035 case 4: /* 2 loads */
2036 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2037 }
2038 break;
2039 }
2040
2041 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2042 }
2043
2044 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2045 const struct util_format_description *desc,
2046 int first_non_void)
2047 {
2048 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2049 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2050
2051 assert(first_non_void >= 0);
2052
2053 switch (desc->channel[first_non_void].type) {
2054 case UTIL_FORMAT_TYPE_SIGNED:
2055 case UTIL_FORMAT_TYPE_FIXED:
2056 if (desc->channel[first_non_void].size >= 32 ||
2057 desc->channel[first_non_void].pure_integer)
2058 return V_008F0C_BUF_NUM_FORMAT_SINT;
2059 else if (desc->channel[first_non_void].normalized)
2060 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2061 else
2062 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2063 break;
2064 case UTIL_FORMAT_TYPE_UNSIGNED:
2065 if (desc->channel[first_non_void].size >= 32 ||
2066 desc->channel[first_non_void].pure_integer)
2067 return V_008F0C_BUF_NUM_FORMAT_UINT;
2068 else if (desc->channel[first_non_void].normalized)
2069 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2070 else
2071 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2072 break;
2073 case UTIL_FORMAT_TYPE_FLOAT:
2074 default:
2075 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2076 }
2077 }
2078
2079 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2080 enum pipe_format format,
2081 unsigned usage)
2082 {
2083 const struct util_format_description *desc;
2084 int first_non_void;
2085 unsigned data_format;
2086
2087 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2088 PIPE_BIND_SAMPLER_VIEW |
2089 PIPE_BIND_VERTEX_BUFFER)) == 0);
2090
2091 desc = util_format_description(format);
2092 if (!desc)
2093 return 0;
2094
2095 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2096 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2097 * for read-only access (with caveats surrounding bounds checks), but
2098 * obviously fails for write access which we have to implement for
2099 * shader images. Luckily, OpenGL doesn't expect this to be supported
2100 * anyway, and so the only impact is on PBO uploads / downloads, which
2101 * shouldn't be expected to be fast for GL_RGB anyway.
2102 */
2103 if (desc->block.bits == 3 * 8 ||
2104 desc->block.bits == 3 * 16) {
2105 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2106 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2107 if (!usage)
2108 return 0;
2109 }
2110 }
2111
2112 first_non_void = util_format_get_first_non_void_channel(format);
2113 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2114 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2115 return 0;
2116
2117 return usage;
2118 }
2119
2120 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2121 {
2122 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2123 si_translate_colorswap(format, false) != ~0U;
2124 }
2125
2126 static bool si_is_zs_format_supported(enum pipe_format format)
2127 {
2128 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2129 }
2130
2131 static boolean si_is_format_supported(struct pipe_screen *screen,
2132 enum pipe_format format,
2133 enum pipe_texture_target target,
2134 unsigned sample_count,
2135 unsigned usage)
2136 {
2137 struct si_screen *sscreen = (struct si_screen *)screen;
2138 unsigned retval = 0;
2139
2140 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2141 PRINT_ERR("r600: unsupported texture type %d\n", target);
2142 return false;
2143 }
2144
2145 if (!util_format_is_supported(format, usage))
2146 return false;
2147
2148 if (sample_count > 1) {
2149 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2150 return false;
2151
2152 if (usage & PIPE_BIND_SHADER_IMAGE)
2153 return false;
2154
2155 switch (sample_count) {
2156 case 2:
2157 case 4:
2158 case 8:
2159 break;
2160 case 16:
2161 /* Allow resource_copy_region with nr_samples == 16. */
2162 if (sscreen->eqaa_force_coverage_samples == 16 &&
2163 !util_format_is_depth_or_stencil(format))
2164 return true;
2165 if (format == PIPE_FORMAT_NONE)
2166 return true;
2167 else
2168 return false;
2169 default:
2170 return false;
2171 }
2172 }
2173
2174 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2175 PIPE_BIND_SHADER_IMAGE)) {
2176 if (target == PIPE_BUFFER) {
2177 retval |= si_is_vertex_format_supported(
2178 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2179 PIPE_BIND_SHADER_IMAGE));
2180 } else {
2181 if (si_is_sampler_format_supported(screen, format))
2182 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2183 PIPE_BIND_SHADER_IMAGE);
2184 }
2185 }
2186
2187 if ((usage & (PIPE_BIND_RENDER_TARGET |
2188 PIPE_BIND_DISPLAY_TARGET |
2189 PIPE_BIND_SCANOUT |
2190 PIPE_BIND_SHARED |
2191 PIPE_BIND_BLENDABLE)) &&
2192 si_is_colorbuffer_format_supported(format)) {
2193 retval |= usage &
2194 (PIPE_BIND_RENDER_TARGET |
2195 PIPE_BIND_DISPLAY_TARGET |
2196 PIPE_BIND_SCANOUT |
2197 PIPE_BIND_SHARED);
2198 if (!util_format_is_pure_integer(format) &&
2199 !util_format_is_depth_or_stencil(format))
2200 retval |= usage & PIPE_BIND_BLENDABLE;
2201 }
2202
2203 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2204 si_is_zs_format_supported(format)) {
2205 retval |= PIPE_BIND_DEPTH_STENCIL;
2206 }
2207
2208 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2209 retval |= si_is_vertex_format_supported(screen, format,
2210 PIPE_BIND_VERTEX_BUFFER);
2211 }
2212
2213 if ((usage & PIPE_BIND_LINEAR) &&
2214 !util_format_is_compressed(format) &&
2215 !(usage & PIPE_BIND_DEPTH_STENCIL))
2216 retval |= PIPE_BIND_LINEAR;
2217
2218 return retval == usage;
2219 }
2220
2221 /*
2222 * framebuffer handling
2223 */
2224
2225 static void si_choose_spi_color_formats(struct si_surface *surf,
2226 unsigned format, unsigned swap,
2227 unsigned ntype, bool is_depth)
2228 {
2229 /* Alpha is needed for alpha-to-coverage.
2230 * Blending may be with or without alpha.
2231 */
2232 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2233 unsigned alpha = 0; /* exports alpha, but may not support blending */
2234 unsigned blend = 0; /* supports blending, but may not export alpha */
2235 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2236
2237 /* Choose the SPI color formats. These are required values for RB+.
2238 * Other chips have multiple choices, though they are not necessarily better.
2239 */
2240 switch (format) {
2241 case V_028C70_COLOR_5_6_5:
2242 case V_028C70_COLOR_1_5_5_5:
2243 case V_028C70_COLOR_5_5_5_1:
2244 case V_028C70_COLOR_4_4_4_4:
2245 case V_028C70_COLOR_10_11_11:
2246 case V_028C70_COLOR_11_11_10:
2247 case V_028C70_COLOR_8:
2248 case V_028C70_COLOR_8_8:
2249 case V_028C70_COLOR_8_8_8_8:
2250 case V_028C70_COLOR_10_10_10_2:
2251 case V_028C70_COLOR_2_10_10_10:
2252 if (ntype == V_028C70_NUMBER_UINT)
2253 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2254 else if (ntype == V_028C70_NUMBER_SINT)
2255 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2256 else
2257 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2258 break;
2259
2260 case V_028C70_COLOR_16:
2261 case V_028C70_COLOR_16_16:
2262 case V_028C70_COLOR_16_16_16_16:
2263 if (ntype == V_028C70_NUMBER_UNORM ||
2264 ntype == V_028C70_NUMBER_SNORM) {
2265 /* UNORM16 and SNORM16 don't support blending */
2266 if (ntype == V_028C70_NUMBER_UNORM)
2267 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2268 else
2269 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2270
2271 /* Use 32 bits per channel for blending. */
2272 if (format == V_028C70_COLOR_16) {
2273 if (swap == V_028C70_SWAP_STD) { /* R */
2274 blend = V_028714_SPI_SHADER_32_R;
2275 blend_alpha = V_028714_SPI_SHADER_32_AR;
2276 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2277 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2278 else
2279 assert(0);
2280 } else if (format == V_028C70_COLOR_16_16) {
2281 if (swap == V_028C70_SWAP_STD) { /* RG */
2282 blend = V_028714_SPI_SHADER_32_GR;
2283 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2284 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2285 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2286 else
2287 assert(0);
2288 } else /* 16_16_16_16 */
2289 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2290 } else if (ntype == V_028C70_NUMBER_UINT)
2291 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2292 else if (ntype == V_028C70_NUMBER_SINT)
2293 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2294 else if (ntype == V_028C70_NUMBER_FLOAT)
2295 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2296 else
2297 assert(0);
2298 break;
2299
2300 case V_028C70_COLOR_32:
2301 if (swap == V_028C70_SWAP_STD) { /* R */
2302 blend = normal = V_028714_SPI_SHADER_32_R;
2303 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2304 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2305 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2306 else
2307 assert(0);
2308 break;
2309
2310 case V_028C70_COLOR_32_32:
2311 if (swap == V_028C70_SWAP_STD) { /* RG */
2312 blend = normal = V_028714_SPI_SHADER_32_GR;
2313 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2314 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2315 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2316 else
2317 assert(0);
2318 break;
2319
2320 case V_028C70_COLOR_32_32_32_32:
2321 case V_028C70_COLOR_8_24:
2322 case V_028C70_COLOR_24_8:
2323 case V_028C70_COLOR_X24_8_32_FLOAT:
2324 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2325 break;
2326
2327 default:
2328 assert(0);
2329 return;
2330 }
2331
2332 /* The DB->CB copy needs 32_ABGR. */
2333 if (is_depth)
2334 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2335
2336 surf->spi_shader_col_format = normal;
2337 surf->spi_shader_col_format_alpha = alpha;
2338 surf->spi_shader_col_format_blend = blend;
2339 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2340 }
2341
2342 static void si_initialize_color_surface(struct si_context *sctx,
2343 struct si_surface *surf)
2344 {
2345 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2346 unsigned color_info, color_attrib;
2347 unsigned format, swap, ntype, endian;
2348 const struct util_format_description *desc;
2349 int firstchan;
2350 unsigned blend_clamp = 0, blend_bypass = 0;
2351
2352 desc = util_format_description(surf->base.format);
2353 for (firstchan = 0; firstchan < 4; firstchan++) {
2354 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2355 break;
2356 }
2357 }
2358 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2359 ntype = V_028C70_NUMBER_FLOAT;
2360 } else {
2361 ntype = V_028C70_NUMBER_UNORM;
2362 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2363 ntype = V_028C70_NUMBER_SRGB;
2364 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2365 if (desc->channel[firstchan].pure_integer) {
2366 ntype = V_028C70_NUMBER_SINT;
2367 } else {
2368 assert(desc->channel[firstchan].normalized);
2369 ntype = V_028C70_NUMBER_SNORM;
2370 }
2371 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2372 if (desc->channel[firstchan].pure_integer) {
2373 ntype = V_028C70_NUMBER_UINT;
2374 } else {
2375 assert(desc->channel[firstchan].normalized);
2376 ntype = V_028C70_NUMBER_UNORM;
2377 }
2378 }
2379 }
2380
2381 format = si_translate_colorformat(surf->base.format);
2382 if (format == V_028C70_COLOR_INVALID) {
2383 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2384 }
2385 assert(format != V_028C70_COLOR_INVALID);
2386 swap = si_translate_colorswap(surf->base.format, false);
2387 endian = si_colorformat_endian_swap(format);
2388
2389 /* blend clamp should be set for all NORM/SRGB types */
2390 if (ntype == V_028C70_NUMBER_UNORM ||
2391 ntype == V_028C70_NUMBER_SNORM ||
2392 ntype == V_028C70_NUMBER_SRGB)
2393 blend_clamp = 1;
2394
2395 /* set blend bypass according to docs if SINT/UINT or
2396 8/24 COLOR variants */
2397 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2398 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2399 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2400 blend_clamp = 0;
2401 blend_bypass = 1;
2402 }
2403
2404 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2405 if (format == V_028C70_COLOR_8 ||
2406 format == V_028C70_COLOR_8_8 ||
2407 format == V_028C70_COLOR_8_8_8_8)
2408 surf->color_is_int8 = true;
2409 else if (format == V_028C70_COLOR_10_10_10_2 ||
2410 format == V_028C70_COLOR_2_10_10_10)
2411 surf->color_is_int10 = true;
2412 }
2413
2414 color_info = S_028C70_FORMAT(format) |
2415 S_028C70_COMP_SWAP(swap) |
2416 S_028C70_BLEND_CLAMP(blend_clamp) |
2417 S_028C70_BLEND_BYPASS(blend_bypass) |
2418 S_028C70_SIMPLE_FLOAT(1) |
2419 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2420 ntype != V_028C70_NUMBER_SNORM &&
2421 ntype != V_028C70_NUMBER_SRGB &&
2422 format != V_028C70_COLOR_8_24 &&
2423 format != V_028C70_COLOR_24_8) |
2424 S_028C70_NUMBER_TYPE(ntype) |
2425 S_028C70_ENDIAN(endian);
2426
2427 /* Intensity is implemented as Red, so treat it that way. */
2428 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2429 util_format_is_intensity(surf->base.format));
2430
2431 if (tex->buffer.b.b.nr_samples > 1) {
2432 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2433 unsigned log_fragments = util_logbase2(tex->num_color_samples);
2434
2435 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2436 S_028C74_NUM_FRAGMENTS(log_fragments);
2437
2438 if (tex->surface.fmask_size) {
2439 color_info |= S_028C70_COMPRESSION(1);
2440 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2441
2442 if (sctx->chip_class == SI) {
2443 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2444 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2445 }
2446 }
2447 }
2448
2449 if (sctx->chip_class >= VI) {
2450 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2451 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2452
2453 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2454 64 for APU because all of our APUs to date use DIMMs which have
2455 a request granularity size of 64B while all other chips have a
2456 32B request size */
2457 if (!sctx->screen->info.has_dedicated_vram)
2458 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2459
2460 if (tex->num_color_samples > 1) {
2461 if (tex->surface.bpe == 1)
2462 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2463 else if (tex->surface.bpe == 2)
2464 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2465 }
2466
2467 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2468 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2469 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2470 }
2471
2472 /* This must be set for fast clear to work without FMASK. */
2473 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2474 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2475 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2476 }
2477
2478 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2479 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2480
2481 if (sctx->chip_class >= GFX9) {
2482 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2483
2484 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2485 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2486 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2487 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2488 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2489 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2490 }
2491
2492 surf->cb_color_view = color_view;
2493 surf->cb_color_info = color_info;
2494 surf->cb_color_attrib = color_attrib;
2495
2496 /* Determine pixel shader export format */
2497 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2498
2499 surf->color_initialized = true;
2500 }
2501
2502 static void si_init_depth_surface(struct si_context *sctx,
2503 struct si_surface *surf)
2504 {
2505 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2506 unsigned level = surf->base.u.tex.level;
2507 unsigned format, stencil_format;
2508 uint32_t z_info, s_info;
2509
2510 format = si_translate_dbformat(tex->db_render_format);
2511 stencil_format = tex->surface.has_stencil ?
2512 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2513
2514 assert(format != V_028040_Z_INVALID);
2515 if (format == V_028040_Z_INVALID)
2516 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2517
2518 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2519 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2520 surf->db_htile_data_base = 0;
2521 surf->db_htile_surface = 0;
2522
2523 if (sctx->chip_class >= GFX9) {
2524 assert(tex->surface.u.gfx9.surf_offset == 0);
2525 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2526 surf->db_stencil_base = (tex->buffer.gpu_address +
2527 tex->surface.u.gfx9.stencil_offset) >> 8;
2528 z_info = S_028038_FORMAT(format) |
2529 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2530 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2531 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2532 s_info = S_02803C_FORMAT(stencil_format) |
2533 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2534 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2535 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2536 surf->db_depth_view |= S_028008_MIPID(level);
2537 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2538 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2539
2540 if (si_htile_enabled(tex, level)) {
2541 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2542 S_028038_ALLOW_EXPCLEAR(1);
2543
2544 if (tex->tc_compatible_htile) {
2545 unsigned max_zplanes = 4;
2546
2547 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2548 tex->buffer.b.b.nr_samples > 1)
2549 max_zplanes = 2;
2550
2551 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2552 S_028038_ITERATE_FLUSH(1);
2553 s_info |= S_02803C_ITERATE_FLUSH(1);
2554 }
2555
2556 if (tex->surface.has_stencil) {
2557 /* Stencil buffer workaround ported from the SI-CI-VI code.
2558 * See that for explanation.
2559 */
2560 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2561 } else {
2562 /* Use all HTILE for depth if there's no stencil. */
2563 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2564 }
2565
2566 surf->db_htile_data_base = (tex->buffer.gpu_address +
2567 tex->htile_offset) >> 8;
2568 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2569 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2570 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2571 }
2572 } else {
2573 /* SI-CI-VI */
2574 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2575
2576 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2577
2578 surf->db_depth_base = (tex->buffer.gpu_address +
2579 tex->surface.u.legacy.level[level].offset) >> 8;
2580 surf->db_stencil_base = (tex->buffer.gpu_address +
2581 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2582
2583 z_info = S_028040_FORMAT(format) |
2584 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2585 s_info = S_028044_FORMAT(stencil_format);
2586 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2587
2588 if (sctx->chip_class >= CIK) {
2589 struct radeon_info *info = &sctx->screen->info;
2590 unsigned index = tex->surface.u.legacy.tiling_index[level];
2591 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2592 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2593 unsigned tile_mode = info->si_tile_mode_array[index];
2594 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2595 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2596
2597 surf->db_depth_info |=
2598 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2599 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2600 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2601 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2602 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2603 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2604 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2605 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2606 } else {
2607 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2608 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2609 tile_mode_index = si_tile_mode_index(tex, level, true);
2610 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2611 }
2612
2613 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2614 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2615 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2616 levelinfo->nblk_y) / 64 - 1);
2617
2618 if (si_htile_enabled(tex, level)) {
2619 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2620 S_028040_ALLOW_EXPCLEAR(1);
2621
2622 if (tex->surface.has_stencil) {
2623 /* Workaround: For a not yet understood reason, the
2624 * combination of MSAA, fast stencil clear and stencil
2625 * decompress messes with subsequent stencil buffer
2626 * uses. Problem was reproduced on Verde, Bonaire,
2627 * Tonga, and Carrizo.
2628 *
2629 * Disabling EXPCLEAR works around the problem.
2630 *
2631 * Check piglit's arb_texture_multisample-stencil-clear
2632 * test if you want to try changing this.
2633 */
2634 if (tex->buffer.b.b.nr_samples <= 1)
2635 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2636 } else if (!tex->tc_compatible_htile) {
2637 /* Use all of the htile_buffer for depth if there's no stencil.
2638 * This must not be set when TC-compatible HTILE is enabled
2639 * due to a hw bug.
2640 */
2641 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2642 }
2643
2644 surf->db_htile_data_base = (tex->buffer.gpu_address +
2645 tex->htile_offset) >> 8;
2646 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2647
2648 if (tex->tc_compatible_htile) {
2649 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2650
2651 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2652 if (tex->buffer.b.b.nr_samples <= 1)
2653 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2654 else if (tex->buffer.b.b.nr_samples <= 4)
2655 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2656 else
2657 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2658 }
2659 }
2660 }
2661
2662 surf->db_z_info = z_info;
2663 surf->db_stencil_info = s_info;
2664
2665 surf->depth_initialized = true;
2666 }
2667
2668 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2669 {
2670 if (sctx->decompression_enabled)
2671 return;
2672
2673 if (sctx->framebuffer.state.zsbuf) {
2674 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2675 struct si_texture *tex = (struct si_texture *)surf->texture;
2676
2677 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2678
2679 if (tex->surface.has_stencil)
2680 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2681 }
2682
2683 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2684 while (compressed_cb_mask) {
2685 unsigned i = u_bit_scan(&compressed_cb_mask);
2686 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2687 struct si_texture *tex = (struct si_texture*)surf->texture;
2688
2689 if (tex->surface.fmask_size)
2690 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2691 if (tex->dcc_gather_statistics)
2692 tex->separate_dcc_dirty = true;
2693 }
2694 }
2695
2696 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2697 {
2698 for (int i = 0; i < state->nr_cbufs; ++i) {
2699 struct si_surface *surf = NULL;
2700 struct si_texture *tex;
2701
2702 if (!state->cbufs[i])
2703 continue;
2704 surf = (struct si_surface*)state->cbufs[i];
2705 tex = (struct si_texture*)surf->base.texture;
2706
2707 p_atomic_dec(&tex->framebuffers_bound);
2708 }
2709 }
2710
2711 static void si_set_framebuffer_state(struct pipe_context *ctx,
2712 const struct pipe_framebuffer_state *state)
2713 {
2714 struct si_context *sctx = (struct si_context *)ctx;
2715 struct pipe_constant_buffer constbuf = {0};
2716 struct si_surface *surf = NULL;
2717 struct si_texture *tex;
2718 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2719 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2720 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2721 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2722 bool old_has_stencil =
2723 old_has_zsbuf &&
2724 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2725 bool unbound = false;
2726 int i;
2727
2728 si_update_fb_dirtiness_after_rendering(sctx);
2729
2730 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2731 if (!sctx->framebuffer.state.cbufs[i])
2732 continue;
2733
2734 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2735 if (tex->dcc_gather_statistics)
2736 vi_separate_dcc_stop_query(sctx, tex);
2737 }
2738
2739 /* Disable DCC if the formats are incompatible. */
2740 for (i = 0; i < state->nr_cbufs; i++) {
2741 if (!state->cbufs[i])
2742 continue;
2743
2744 surf = (struct si_surface*)state->cbufs[i];
2745 tex = (struct si_texture*)surf->base.texture;
2746
2747 if (!surf->dcc_incompatible)
2748 continue;
2749
2750 /* Since the DCC decompression calls back into set_framebuffer-
2751 * _state, we need to unbind the framebuffer, so that
2752 * vi_separate_dcc_stop_query isn't called twice with the same
2753 * color buffer.
2754 */
2755 if (!unbound) {
2756 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2757 unbound = true;
2758 }
2759
2760 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2761 if (!si_texture_disable_dcc(sctx, tex))
2762 si_decompress_dcc(sctx, tex);
2763
2764 surf->dcc_incompatible = false;
2765 }
2766
2767 /* Only flush TC when changing the framebuffer state, because
2768 * the only client not using TC that can change textures is
2769 * the framebuffer.
2770 *
2771 * Wait for compute shaders because of possible transitions:
2772 * - FB write -> shader read
2773 * - shader write -> FB read
2774 *
2775 * DB caches are flushed on demand (using si_decompress_textures).
2776 *
2777 * When MSAA is enabled, CB and TC caches are flushed on demand
2778 * (after FMASK decompression). Shader write -> FB read transitions
2779 * cannot happen for MSAA textures, because MSAA shader images are
2780 * not supported.
2781 *
2782 * Only flush and wait for CB if there is actually a bound color buffer.
2783 */
2784 if (sctx->framebuffer.uncompressed_cb_mask)
2785 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2786 sctx->framebuffer.CB_has_shader_readable_metadata);
2787
2788 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2789
2790 /* u_blitter doesn't invoke depth decompression when it does multiple
2791 * blits in a row, but the only case when it matters for DB is when
2792 * doing generate_mipmap. So here we flush DB manually between
2793 * individual generate_mipmap blits.
2794 * Note that lower mipmap levels aren't compressed.
2795 */
2796 if (sctx->generate_mipmap_for_depth) {
2797 si_make_DB_shader_coherent(sctx, 1, false,
2798 sctx->framebuffer.DB_has_shader_readable_metadata);
2799 } else if (sctx->chip_class == GFX9) {
2800 /* It appears that DB metadata "leaks" in a sequence of:
2801 * - depth clear
2802 * - DCC decompress for shader image writes (with DB disabled)
2803 * - render with DEPTH_BEFORE_SHADER=1
2804 * Flushing DB metadata works around the problem.
2805 */
2806 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2807 }
2808
2809 /* Take the maximum of the old and new count. If the new count is lower,
2810 * dirtying is needed to disable the unbound colorbuffers.
2811 */
2812 sctx->framebuffer.dirty_cbufs |=
2813 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2814 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2815
2816 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2817 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2818
2819 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2820 sctx->framebuffer.spi_shader_col_format = 0;
2821 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2822 sctx->framebuffer.spi_shader_col_format_blend = 0;
2823 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2824 sctx->framebuffer.color_is_int8 = 0;
2825 sctx->framebuffer.color_is_int10 = 0;
2826
2827 sctx->framebuffer.compressed_cb_mask = 0;
2828 sctx->framebuffer.uncompressed_cb_mask = 0;
2829 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2830 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2831 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2832 sctx->framebuffer.any_dst_linear = false;
2833 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2834 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2835
2836 for (i = 0; i < state->nr_cbufs; i++) {
2837 if (!state->cbufs[i])
2838 continue;
2839
2840 surf = (struct si_surface*)state->cbufs[i];
2841 tex = (struct si_texture*)surf->base.texture;
2842
2843 if (!surf->color_initialized) {
2844 si_initialize_color_surface(sctx, surf);
2845 }
2846
2847 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2848 sctx->framebuffer.spi_shader_col_format |=
2849 surf->spi_shader_col_format << (i * 4);
2850 sctx->framebuffer.spi_shader_col_format_alpha |=
2851 surf->spi_shader_col_format_alpha << (i * 4);
2852 sctx->framebuffer.spi_shader_col_format_blend |=
2853 surf->spi_shader_col_format_blend << (i * 4);
2854 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2855 surf->spi_shader_col_format_blend_alpha << (i * 4);
2856
2857 if (surf->color_is_int8)
2858 sctx->framebuffer.color_is_int8 |= 1 << i;
2859 if (surf->color_is_int10)
2860 sctx->framebuffer.color_is_int10 |= 1 << i;
2861
2862 if (tex->surface.fmask_size)
2863 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2864 else
2865 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2866
2867 /* Don't update nr_color_samples for non-AA buffers.
2868 * (e.g. destination of MSAA resolve)
2869 */
2870 if (tex->buffer.b.b.nr_samples >= 2 &&
2871 tex->num_color_samples < tex->buffer.b.b.nr_samples) {
2872 sctx->framebuffer.nr_color_samples =
2873 MIN2(sctx->framebuffer.nr_color_samples,
2874 tex->num_color_samples);
2875 }
2876
2877 if (tex->surface.is_linear)
2878 sctx->framebuffer.any_dst_linear = true;
2879
2880 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2881 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2882
2883 si_context_add_resource_size(sctx, surf->base.texture);
2884
2885 p_atomic_inc(&tex->framebuffers_bound);
2886
2887 if (tex->dcc_gather_statistics) {
2888 /* Dirty tracking must be enabled for DCC usage analysis. */
2889 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2890 vi_separate_dcc_start_query(sctx, tex);
2891 }
2892 }
2893
2894 struct si_texture *zstex = NULL;
2895
2896 if (state->zsbuf) {
2897 surf = (struct si_surface*)state->zsbuf;
2898 zstex = (struct si_texture*)surf->base.texture;
2899
2900 if (!surf->depth_initialized) {
2901 si_init_depth_surface(sctx, surf);
2902 }
2903
2904 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2905 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2906
2907 si_context_add_resource_size(sctx, surf->base.texture);
2908 }
2909
2910 si_update_ps_colorbuf0_slot(sctx);
2911 si_update_poly_offset_state(sctx);
2912 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2913 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2914
2915 if (sctx->screen->dpbb_allowed)
2916 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2917
2918 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2919 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2920
2921 if (sctx->screen->has_out_of_order_rast &&
2922 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2923 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2924 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2925 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2926
2927 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2928 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2929 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2930
2931 /* Set sample locations as fragment shader constants. */
2932 switch (sctx->framebuffer.nr_samples) {
2933 case 1:
2934 constbuf.user_buffer = sctx->sample_locations_1x;
2935 break;
2936 case 2:
2937 constbuf.user_buffer = sctx->sample_locations_2x;
2938 break;
2939 case 4:
2940 constbuf.user_buffer = sctx->sample_locations_4x;
2941 break;
2942 case 8:
2943 constbuf.user_buffer = sctx->sample_locations_8x;
2944 break;
2945 case 16:
2946 constbuf.user_buffer = sctx->sample_locations_16x;
2947 break;
2948 default:
2949 PRINT_ERR("Requested an invalid number of samples %i.\n",
2950 sctx->framebuffer.nr_samples);
2951 assert(0);
2952 }
2953 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2954 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2955
2956 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2957 }
2958
2959 sctx->do_update_shaders = true;
2960
2961 if (!sctx->decompression_enabled) {
2962 /* Prevent textures decompression when the framebuffer state
2963 * changes come from the decompression passes themselves.
2964 */
2965 sctx->need_check_render_feedback = true;
2966 }
2967 }
2968
2969 static void si_emit_framebuffer_state(struct si_context *sctx)
2970 {
2971 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2972 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2973 unsigned i, nr_cbufs = state->nr_cbufs;
2974 struct si_texture *tex = NULL;
2975 struct si_surface *cb = NULL;
2976 unsigned cb_color_info = 0;
2977
2978 /* Colorbuffers. */
2979 for (i = 0; i < nr_cbufs; i++) {
2980 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
2981 unsigned cb_color_attrib;
2982
2983 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2984 continue;
2985
2986 cb = (struct si_surface*)state->cbufs[i];
2987 if (!cb) {
2988 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2989 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2990 continue;
2991 }
2992
2993 tex = (struct si_texture *)cb->base.texture;
2994 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
2995 &tex->buffer, RADEON_USAGE_READWRITE,
2996 tex->buffer.b.b.nr_samples > 1 ?
2997 RADEON_PRIO_COLOR_BUFFER_MSAA :
2998 RADEON_PRIO_COLOR_BUFFER);
2999
3000 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3001 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3002 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3003 RADEON_PRIO_CMASK);
3004 }
3005
3006 if (tex->dcc_separate_buffer)
3007 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3008 tex->dcc_separate_buffer,
3009 RADEON_USAGE_READWRITE,
3010 RADEON_PRIO_DCC);
3011
3012 /* Compute mutable surface parameters. */
3013 cb_color_base = tex->buffer.gpu_address >> 8;
3014 cb_color_fmask = 0;
3015 cb_color_cmask = tex->cmask_base_address_reg;
3016 cb_dcc_base = 0;
3017 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3018 cb_color_attrib = cb->cb_color_attrib;
3019
3020 if (cb->base.u.tex.level > 0)
3021 cb_color_info &= C_028C70_FAST_CLEAR;
3022
3023 if (tex->surface.fmask_size) {
3024 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3025 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3026 }
3027
3028 /* Set up DCC. */
3029 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3030 bool is_msaa_resolve_dst = state->cbufs[0] &&
3031 state->cbufs[0]->texture->nr_samples > 1 &&
3032 state->cbufs[1] == &cb->base &&
3033 state->cbufs[1]->texture->nr_samples <= 1;
3034
3035 if (!is_msaa_resolve_dst)
3036 cb_color_info |= S_028C70_DCC_ENABLE(1);
3037
3038 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3039 tex->dcc_offset) >> 8;
3040 cb_dcc_base |= tex->surface.tile_swizzle;
3041 }
3042
3043 if (sctx->chip_class >= GFX9) {
3044 struct gfx9_surf_meta_flags meta;
3045
3046 if (tex->dcc_offset)
3047 meta = tex->surface.u.gfx9.dcc;
3048 else
3049 meta = tex->surface.u.gfx9.cmask;
3050
3051 /* Set mutable surface parameters. */
3052 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3053 cb_color_base |= tex->surface.tile_swizzle;
3054 if (!tex->surface.fmask_size)
3055 cb_color_fmask = cb_color_base;
3056 if (cb->base.u.tex.level > 0)
3057 cb_color_cmask = cb_color_base;
3058 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3059 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3060 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3061 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3062
3063 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3064 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3065 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3066 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3067 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3068 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3069 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3070 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3071 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3072 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3073 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3074 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3075 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3076 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3077 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3078 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3079
3080 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3081 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3082 } else {
3083 /* Compute mutable surface parameters (SI-CI-VI). */
3084 const struct legacy_surf_level *level_info =
3085 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3086 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3087 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3088
3089 cb_color_base += level_info->offset >> 8;
3090 /* Only macrotiled modes can set tile swizzle. */
3091 if (level_info->mode == RADEON_SURF_MODE_2D)
3092 cb_color_base |= tex->surface.tile_swizzle;
3093
3094 if (!tex->surface.fmask_size)
3095 cb_color_fmask = cb_color_base;
3096 if (cb->base.u.tex.level > 0)
3097 cb_color_cmask = cb_color_base;
3098 if (cb_dcc_base)
3099 cb_dcc_base += level_info->dcc_offset >> 8;
3100
3101 pitch_tile_max = level_info->nblk_x / 8 - 1;
3102 slice_tile_max = level_info->nblk_x *
3103 level_info->nblk_y / 64 - 1;
3104 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3105
3106 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3107 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3108 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3109
3110 if (tex->surface.fmask_size) {
3111 if (sctx->chip_class >= CIK)
3112 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3113 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3114 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3115 } else {
3116 /* This must be set for fast clear to work without FMASK. */
3117 if (sctx->chip_class >= CIK)
3118 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3119 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3120 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3121 }
3122
3123 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3124 sctx->chip_class >= VI ? 14 : 13);
3125 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3126 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3127 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3128 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3129 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3130 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3131 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3132 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3133 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3134 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3135 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3136 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3137 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3138
3139 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3140 radeon_emit(cs, cb_dcc_base);
3141 }
3142 }
3143 for (; i < 8 ; i++)
3144 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3145 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3146
3147 /* ZS buffer. */
3148 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3149 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3150 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3151
3152 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3153 &tex->buffer, RADEON_USAGE_READWRITE,
3154 zb->base.texture->nr_samples > 1 ?
3155 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3156 RADEON_PRIO_DEPTH_BUFFER);
3157
3158 if (sctx->chip_class >= GFX9) {
3159 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3160 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3161 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3162 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3163
3164 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3165 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3166 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3167 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3168 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3169 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3170 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3171 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3172 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3173 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3174 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3175 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3176
3177 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3178 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3179 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3180 } else {
3181 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3182
3183 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3184 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3185 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3186 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3187 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3188 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3189 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3190 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3191 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3192 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3193 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3194 }
3195
3196 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3197 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3198 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3199
3200 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3201 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3202 } else if (sctx->framebuffer.dirty_zsbuf) {
3203 if (sctx->chip_class >= GFX9)
3204 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3205 else
3206 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3207
3208 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3209 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3210 }
3211
3212 /* Framebuffer dimensions. */
3213 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3214 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3215 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3216
3217 if (sctx->screen->dfsm_allowed) {
3218 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3219 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3220 }
3221
3222 sctx->framebuffer.dirty_cbufs = 0;
3223 sctx->framebuffer.dirty_zsbuf = false;
3224 }
3225
3226 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3227 {
3228 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3229 unsigned nr_samples = sctx->framebuffer.nr_samples;
3230 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3231
3232 /* Smoothing (only possible with nr_samples == 1) uses the same
3233 * sample locations as the MSAA it simulates.
3234 */
3235 if (nr_samples <= 1 && sctx->smoothing_enabled)
3236 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3237
3238 /* On Polaris, the small primitive filter uses the sample locations
3239 * even when MSAA is off, so we need to make sure they're set to 0.
3240 */
3241 if (has_msaa_sample_loc_bug)
3242 nr_samples = MAX2(nr_samples, 1);
3243
3244 if (nr_samples != sctx->sample_locs_num_samples) {
3245 sctx->sample_locs_num_samples = nr_samples;
3246 si_emit_sample_locations(cs, nr_samples);
3247 }
3248
3249 if (sctx->family >= CHIP_POLARIS10) {
3250 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3251 unsigned small_prim_filter_cntl =
3252 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3253 /* line bug */
3254 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3255
3256 /* The alternative of setting sample locations to 0 would
3257 * require a DB flush to avoid Z errors, see
3258 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3259 */
3260 if (has_msaa_sample_loc_bug &&
3261 sctx->framebuffer.nr_samples > 1 &&
3262 !rs->multisample_enable)
3263 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3264
3265 radeon_opt_set_context_reg(sctx,
3266 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3267 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3268 small_prim_filter_cntl);
3269 }
3270 }
3271
3272 static bool si_out_of_order_rasterization(struct si_context *sctx)
3273 {
3274 struct si_state_blend *blend = sctx->queued.named.blend;
3275 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3276
3277 if (!sctx->screen->has_out_of_order_rast)
3278 return false;
3279
3280 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3281
3282 if (blend) {
3283 colormask &= blend->cb_target_enabled_4bit;
3284 } else {
3285 colormask = 0;
3286 }
3287
3288 /* Conservative: No logic op. */
3289 if (colormask && blend->logicop_enable)
3290 return false;
3291
3292 struct si_dsa_order_invariance dsa_order_invariant = {
3293 .zs = true, .pass_set = true, .pass_last = false
3294 };
3295
3296 if (sctx->framebuffer.state.zsbuf) {
3297 struct si_texture *zstex =
3298 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3299 bool has_stencil = zstex->surface.has_stencil;
3300 dsa_order_invariant = dsa->order_invariance[has_stencil];
3301 if (!dsa_order_invariant.zs)
3302 return false;
3303
3304 /* The set of PS invocations is always order invariant,
3305 * except when early Z/S tests are requested. */
3306 if (sctx->ps_shader.cso &&
3307 sctx->ps_shader.cso->info.writes_memory &&
3308 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3309 !dsa_order_invariant.pass_set)
3310 return false;
3311
3312 if (sctx->num_perfect_occlusion_queries != 0 &&
3313 !dsa_order_invariant.pass_set)
3314 return false;
3315 }
3316
3317 if (!colormask)
3318 return true;
3319
3320 unsigned blendmask = colormask & blend->blend_enable_4bit;
3321
3322 if (blendmask) {
3323 /* Only commutative blending. */
3324 if (blendmask & ~blend->commutative_4bit)
3325 return false;
3326
3327 if (!dsa_order_invariant.pass_set)
3328 return false;
3329 }
3330
3331 if (colormask & ~blendmask) {
3332 if (!dsa_order_invariant.pass_last)
3333 return false;
3334 }
3335
3336 return true;
3337 }
3338
3339 static void si_emit_msaa_config(struct si_context *sctx)
3340 {
3341 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3342 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3343 /* 33% faster rendering to linear color buffers */
3344 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3345 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3346 unsigned sc_mode_cntl_1 =
3347 S_028A4C_WALK_SIZE(dst_is_linear) |
3348 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3349 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3350 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3351 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3352 /* always 1: */
3353 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3354 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3355 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3356 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3357 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3358 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3359 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3360 S_028804_INCOHERENT_EQAA_READS(1) |
3361 S_028804_INTERPOLATE_COMP_Z(1) |
3362 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3363 unsigned coverage_samples, color_samples, z_samples;
3364
3365 /* S: Coverage samples (up to 16x):
3366 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3367 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3368 *
3369 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3370 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3371 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3372 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3373 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3374 * # Z samples).
3375 *
3376 * F: Color samples (up to 8x, must be <= coverage samples):
3377 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3378 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3379 *
3380 * Can be anything between coverage and color samples:
3381 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3382 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3383 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3384 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3385 * # All are currently set the same as coverage samples.
3386 *
3387 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3388 * flag for undefined color samples. A shader-based resolve must handle unknowns
3389 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3390 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3391 * useful. The CB resolve always drops unknowns.
3392 *
3393 * Sensible AA configurations:
3394 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3395 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3396 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3397 * EQAA 8s 8z 8f = 8x MSAA
3398 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3399 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3400 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3401 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3402 * EQAA 4s 4z 4f = 4x MSAA
3403 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3404 * EQAA 2s 2z 2f = 2x MSAA
3405 */
3406 if (sctx->framebuffer.nr_samples > 1) {
3407 coverage_samples = sctx->framebuffer.nr_samples;
3408 color_samples = sctx->framebuffer.nr_color_samples;
3409
3410 if (sctx->framebuffer.state.zsbuf) {
3411 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3412 z_samples = MAX2(1, z_samples);
3413 } else {
3414 z_samples = coverage_samples;
3415 }
3416 } else if (sctx->smoothing_enabled) {
3417 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3418 } else {
3419 coverage_samples = color_samples = z_samples = 1;
3420 }
3421
3422 /* Required by OpenGL line rasterization.
3423 *
3424 * TODO: We should also enable perpendicular endcaps for AA lines,
3425 * but that requires implementing line stippling in the pixel
3426 * shader. SC can only do line stippling with axis-aligned
3427 * endcaps.
3428 */
3429 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3430 unsigned sc_aa_config = 0;
3431
3432 if (coverage_samples > 1) {
3433 /* distance from the pixel center, indexed by log2(nr_samples) */
3434 static unsigned max_dist[] = {
3435 0, /* unused */
3436 4, /* 2x MSAA */
3437 6, /* 4x MSAA */
3438 7, /* 8x MSAA */
3439 8, /* 16x MSAA */
3440 };
3441 unsigned log_samples = util_logbase2(coverage_samples);
3442 unsigned log_z_samples = util_logbase2(z_samples);
3443 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3444 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3445
3446 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3447 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3448 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3449 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3450
3451 if (sctx->framebuffer.nr_samples > 1) {
3452 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3453 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3454 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3455 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3456 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3457 } else if (sctx->smoothing_enabled) {
3458 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3459 }
3460 }
3461
3462 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3463 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3464 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3465 sc_aa_config);
3466 /* R_028804_DB_EQAA */
3467 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3468 db_eqaa);
3469 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3470 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3471 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3472
3473 /* GFX9: Flush DFSM when the AA mode changes. */
3474 if (sctx->screen->dfsm_allowed) {
3475 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3476 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3477 }
3478 }
3479
3480 void si_update_ps_iter_samples(struct si_context *sctx)
3481 {
3482 if (sctx->framebuffer.nr_samples > 1)
3483 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3484 if (sctx->screen->dpbb_allowed)
3485 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3486 }
3487
3488 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3489 {
3490 struct si_context *sctx = (struct si_context *)ctx;
3491
3492 /* The hardware can only do sample shading with 2^n samples. */
3493 min_samples = util_next_power_of_two(min_samples);
3494
3495 if (sctx->ps_iter_samples == min_samples)
3496 return;
3497
3498 sctx->ps_iter_samples = min_samples;
3499 sctx->do_update_shaders = true;
3500
3501 si_update_ps_iter_samples(sctx);
3502 }
3503
3504 /*
3505 * Samplers
3506 */
3507
3508 /**
3509 * Build the sampler view descriptor for a buffer texture.
3510 * @param state 256-bit descriptor; only the high 128 bits are filled in
3511 */
3512 void
3513 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3514 enum pipe_format format,
3515 unsigned offset, unsigned size,
3516 uint32_t *state)
3517 {
3518 const struct util_format_description *desc;
3519 int first_non_void;
3520 unsigned stride;
3521 unsigned num_records;
3522 unsigned num_format, data_format;
3523
3524 desc = util_format_description(format);
3525 first_non_void = util_format_get_first_non_void_channel(format);
3526 stride = desc->block.bits / 8;
3527 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3528 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3529
3530 num_records = size / stride;
3531 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3532
3533 /* The NUM_RECORDS field has a different meaning depending on the chip,
3534 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3535 *
3536 * SI-CIK:
3537 * - If STRIDE == 0, it's in byte units.
3538 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3539 *
3540 * VI:
3541 * - For SMEM and STRIDE == 0, it's in byte units.
3542 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3543 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3544 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3545 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3546 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3547 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3548 * That way the same descriptor can be used by both SMEM and VMEM.
3549 *
3550 * GFX9:
3551 * - For SMEM and STRIDE == 0, it's in byte units.
3552 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3553 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3554 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3555 */
3556 if (screen->info.chip_class >= GFX9)
3557 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3558 * from STRIDE to bytes. This works around it by setting
3559 * NUM_RECORDS to at least the size of one element, so that
3560 * the first element is readable when IDXEN == 0.
3561 *
3562 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3563 * IDXEN is enforced?
3564 */
3565 num_records = num_records ? MAX2(num_records, stride) : 0;
3566 else if (screen->info.chip_class == VI)
3567 num_records *= stride;
3568
3569 state[4] = 0;
3570 state[5] = S_008F04_STRIDE(stride);
3571 state[6] = num_records;
3572 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3573 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3574 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3575 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3576 S_008F0C_NUM_FORMAT(num_format) |
3577 S_008F0C_DATA_FORMAT(data_format);
3578 }
3579
3580 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3581 {
3582 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3583
3584 if (swizzle[3] == PIPE_SWIZZLE_X) {
3585 /* For the pre-defined border color values (white, opaque
3586 * black, transparent black), the only thing that matters is
3587 * that the alpha channel winds up in the correct place
3588 * (because the RGB channels are all the same) so either of
3589 * these enumerations will work.
3590 */
3591 if (swizzle[2] == PIPE_SWIZZLE_Y)
3592 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3593 else
3594 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3595 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3596 if (swizzle[1] == PIPE_SWIZZLE_Y)
3597 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3598 else
3599 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3600 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3601 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3602 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3603 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3604 }
3605
3606 return bc_swizzle;
3607 }
3608
3609 /**
3610 * Build the sampler view descriptor for a texture.
3611 */
3612 void
3613 si_make_texture_descriptor(struct si_screen *screen,
3614 struct si_texture *tex,
3615 bool sampler,
3616 enum pipe_texture_target target,
3617 enum pipe_format pipe_format,
3618 const unsigned char state_swizzle[4],
3619 unsigned first_level, unsigned last_level,
3620 unsigned first_layer, unsigned last_layer,
3621 unsigned width, unsigned height, unsigned depth,
3622 uint32_t *state,
3623 uint32_t *fmask_state)
3624 {
3625 struct pipe_resource *res = &tex->buffer.b.b;
3626 const struct util_format_description *desc;
3627 unsigned char swizzle[4];
3628 int first_non_void;
3629 unsigned num_format, data_format, type, num_samples;
3630 uint64_t va;
3631
3632 desc = util_format_description(pipe_format);
3633
3634 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3635 MAX2(1, res->nr_samples) : tex->num_color_samples;
3636
3637 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3638 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3639 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3640 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3641
3642 switch (pipe_format) {
3643 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3644 case PIPE_FORMAT_X32_S8X24_UINT:
3645 case PIPE_FORMAT_X8Z24_UNORM:
3646 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3647 break;
3648 case PIPE_FORMAT_X24S8_UINT:
3649 /*
3650 * X24S8 is implemented as an 8_8_8_8 data format, to
3651 * fix texture gathers. This affects at least
3652 * GL45-CTS.texture_cube_map_array.sampling on VI.
3653 */
3654 if (screen->info.chip_class <= VI)
3655 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3656 else
3657 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3658 break;
3659 default:
3660 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3661 }
3662 } else {
3663 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3664 }
3665
3666 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3667
3668 switch (pipe_format) {
3669 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3670 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3671 break;
3672 default:
3673 if (first_non_void < 0) {
3674 if (util_format_is_compressed(pipe_format)) {
3675 switch (pipe_format) {
3676 case PIPE_FORMAT_DXT1_SRGB:
3677 case PIPE_FORMAT_DXT1_SRGBA:
3678 case PIPE_FORMAT_DXT3_SRGBA:
3679 case PIPE_FORMAT_DXT5_SRGBA:
3680 case PIPE_FORMAT_BPTC_SRGBA:
3681 case PIPE_FORMAT_ETC2_SRGB8:
3682 case PIPE_FORMAT_ETC2_SRGB8A1:
3683 case PIPE_FORMAT_ETC2_SRGBA8:
3684 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3685 break;
3686 case PIPE_FORMAT_RGTC1_SNORM:
3687 case PIPE_FORMAT_LATC1_SNORM:
3688 case PIPE_FORMAT_RGTC2_SNORM:
3689 case PIPE_FORMAT_LATC2_SNORM:
3690 case PIPE_FORMAT_ETC2_R11_SNORM:
3691 case PIPE_FORMAT_ETC2_RG11_SNORM:
3692 /* implies float, so use SNORM/UNORM to determine
3693 whether data is signed or not */
3694 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3695 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3696 break;
3697 default:
3698 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3699 break;
3700 }
3701 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3702 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3703 } else {
3704 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3705 }
3706 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3707 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3708 } else {
3709 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3710
3711 switch (desc->channel[first_non_void].type) {
3712 case UTIL_FORMAT_TYPE_FLOAT:
3713 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3714 break;
3715 case UTIL_FORMAT_TYPE_SIGNED:
3716 if (desc->channel[first_non_void].normalized)
3717 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3718 else if (desc->channel[first_non_void].pure_integer)
3719 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3720 else
3721 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3722 break;
3723 case UTIL_FORMAT_TYPE_UNSIGNED:
3724 if (desc->channel[first_non_void].normalized)
3725 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3726 else if (desc->channel[first_non_void].pure_integer)
3727 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3728 else
3729 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3730 }
3731 }
3732 }
3733
3734 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3735 if (data_format == ~0) {
3736 data_format = 0;
3737 }
3738
3739 /* S8 with Z32 HTILE needs a special format. */
3740 if (screen->info.chip_class >= GFX9 &&
3741 pipe_format == PIPE_FORMAT_S8_UINT &&
3742 tex->tc_compatible_htile)
3743 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3744
3745 if (!sampler &&
3746 (res->target == PIPE_TEXTURE_CUBE ||
3747 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3748 (screen->info.chip_class <= VI &&
3749 res->target == PIPE_TEXTURE_3D))) {
3750 /* For the purpose of shader images, treat cube maps and 3D
3751 * textures as 2D arrays. For 3D textures, the address
3752 * calculations for mipmaps are different, so we rely on the
3753 * caller to effectively disable mipmaps.
3754 */
3755 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3756
3757 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3758 } else {
3759 type = si_tex_dim(screen, tex, target, num_samples);
3760 }
3761
3762 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3763 height = 1;
3764 depth = res->array_size;
3765 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3766 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3767 if (sampler || res->target != PIPE_TEXTURE_3D)
3768 depth = res->array_size;
3769 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3770 depth = res->array_size / 6;
3771
3772 state[0] = 0;
3773 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3774 S_008F14_NUM_FORMAT_GFX6(num_format));
3775 state[2] = (S_008F18_WIDTH(width - 1) |
3776 S_008F18_HEIGHT(height - 1) |
3777 S_008F18_PERF_MOD(4));
3778 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3779 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3780 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3781 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3782 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3783 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3784 util_logbase2(num_samples) :
3785 last_level) |
3786 S_008F1C_TYPE(type));
3787 state[4] = 0;
3788 state[5] = S_008F24_BASE_ARRAY(first_layer);
3789 state[6] = 0;
3790 state[7] = 0;
3791
3792 if (screen->info.chip_class >= GFX9) {
3793 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3794
3795 /* Depth is the the last accessible layer on Gfx9.
3796 * The hw doesn't need to know the total number of layers.
3797 */
3798 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3799 state[4] |= S_008F20_DEPTH(depth - 1);
3800 else
3801 state[4] |= S_008F20_DEPTH(last_layer);
3802
3803 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3804 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3805 util_logbase2(num_samples) :
3806 tex->buffer.b.b.last_level);
3807 } else {
3808 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3809 state[4] |= S_008F20_DEPTH(depth - 1);
3810 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3811 }
3812
3813 if (tex->dcc_offset) {
3814 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3815 } else {
3816 /* The last dword is unused by hw. The shader uses it to clear
3817 * bits in the first dword of sampler state.
3818 */
3819 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3820 if (first_level == last_level)
3821 state[7] = C_008F30_MAX_ANISO_RATIO;
3822 else
3823 state[7] = 0xffffffff;
3824 }
3825 }
3826
3827 /* Initialize the sampler view for FMASK. */
3828 if (tex->surface.fmask_size) {
3829 uint32_t data_format, num_format;
3830
3831 va = tex->buffer.gpu_address + tex->fmask_offset;
3832
3833 #define FMASK(s,f) (((unsigned)(s) * 16) + (f))
3834 if (screen->info.chip_class >= GFX9) {
3835 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3836 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3837 case FMASK(2,1):
3838 num_format = V_008F14_IMG_FMASK_8_2_1;
3839 break;
3840 case FMASK(2,2):
3841 num_format = V_008F14_IMG_FMASK_8_2_2;
3842 break;
3843 case FMASK(4,1):
3844 num_format = V_008F14_IMG_FMASK_8_4_1;
3845 break;
3846 case FMASK(4,2):
3847 num_format = V_008F14_IMG_FMASK_8_4_2;
3848 break;
3849 case FMASK(4,4):
3850 num_format = V_008F14_IMG_FMASK_8_4_4;
3851 break;
3852 case FMASK(8,1):
3853 num_format = V_008F14_IMG_FMASK_8_8_1;
3854 break;
3855 case FMASK(8,2):
3856 num_format = V_008F14_IMG_FMASK_16_8_2;
3857 break;
3858 case FMASK(8,4):
3859 num_format = V_008F14_IMG_FMASK_32_8_4;
3860 break;
3861 case FMASK(8,8):
3862 num_format = V_008F14_IMG_FMASK_32_8_8;
3863 break;
3864 case FMASK(16,1):
3865 num_format = V_008F14_IMG_FMASK_16_16_1;
3866 break;
3867 case FMASK(16,2):
3868 num_format = V_008F14_IMG_FMASK_32_16_2;
3869 break;
3870 case FMASK(16,4):
3871 num_format = V_008F14_IMG_FMASK_64_16_4;
3872 break;
3873 case FMASK(16,8):
3874 num_format = V_008F14_IMG_FMASK_64_16_8;
3875 break;
3876 default:
3877 unreachable("invalid nr_samples");
3878 }
3879 } else {
3880 switch (FMASK(res->nr_samples, tex->num_color_samples)) {
3881 case FMASK(2,1):
3882 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3883 break;
3884 case FMASK(2,2):
3885 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3886 break;
3887 case FMASK(4,1):
3888 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3889 break;
3890 case FMASK(4,2):
3891 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3892 break;
3893 case FMASK(4,4):
3894 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3895 break;
3896 case FMASK(8,1):
3897 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3898 break;
3899 case FMASK(8,2):
3900 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3901 break;
3902 case FMASK(8,4):
3903 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3904 break;
3905 case FMASK(8,8):
3906 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3907 break;
3908 case FMASK(16,1):
3909 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3910 break;
3911 case FMASK(16,2):
3912 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3913 break;
3914 case FMASK(16,4):
3915 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3916 break;
3917 case FMASK(16,8):
3918 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3919 break;
3920 default:
3921 unreachable("invalid nr_samples");
3922 }
3923 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3924 }
3925 #undef FMASK
3926
3927 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3928 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3929 S_008F14_DATA_FORMAT_GFX6(data_format) |
3930 S_008F14_NUM_FORMAT_GFX6(num_format);
3931 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3932 S_008F18_HEIGHT(height - 1);
3933 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3934 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3935 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3936 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3937 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3938 fmask_state[4] = 0;
3939 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3940 fmask_state[6] = 0;
3941 fmask_state[7] = 0;
3942
3943 if (screen->info.chip_class >= GFX9) {
3944 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3945 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3946 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3947 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3948 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3949 } else {
3950 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3951 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3952 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3953 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3954 }
3955 }
3956 }
3957
3958 /**
3959 * Create a sampler view.
3960 *
3961 * @param ctx context
3962 * @param texture texture
3963 * @param state sampler view template
3964 * @param width0 width0 override (for compressed textures as int)
3965 * @param height0 height0 override (for compressed textures as int)
3966 * @param force_level set the base address to the level (for compressed textures)
3967 */
3968 struct pipe_sampler_view *
3969 si_create_sampler_view_custom(struct pipe_context *ctx,
3970 struct pipe_resource *texture,
3971 const struct pipe_sampler_view *state,
3972 unsigned width0, unsigned height0,
3973 unsigned force_level)
3974 {
3975 struct si_context *sctx = (struct si_context*)ctx;
3976 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3977 struct si_texture *tex = (struct si_texture*)texture;
3978 unsigned base_level, first_level, last_level;
3979 unsigned char state_swizzle[4];
3980 unsigned height, depth, width;
3981 unsigned last_layer = state->u.tex.last_layer;
3982 enum pipe_format pipe_format;
3983 const struct legacy_surf_level *surflevel;
3984
3985 if (!view)
3986 return NULL;
3987
3988 /* initialize base object */
3989 view->base = *state;
3990 view->base.texture = NULL;
3991 view->base.reference.count = 1;
3992 view->base.context = ctx;
3993
3994 assert(texture);
3995 pipe_resource_reference(&view->base.texture, texture);
3996
3997 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3998 state->format == PIPE_FORMAT_S8X24_UINT ||
3999 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4000 state->format == PIPE_FORMAT_S8_UINT)
4001 view->is_stencil_sampler = true;
4002
4003 /* Buffer resource. */
4004 if (texture->target == PIPE_BUFFER) {
4005 si_make_buffer_descriptor(sctx->screen,
4006 r600_resource(texture),
4007 state->format,
4008 state->u.buf.offset,
4009 state->u.buf.size,
4010 view->state);
4011 return &view->base;
4012 }
4013
4014 state_swizzle[0] = state->swizzle_r;
4015 state_swizzle[1] = state->swizzle_g;
4016 state_swizzle[2] = state->swizzle_b;
4017 state_swizzle[3] = state->swizzle_a;
4018
4019 base_level = 0;
4020 first_level = state->u.tex.first_level;
4021 last_level = state->u.tex.last_level;
4022 width = width0;
4023 height = height0;
4024 depth = texture->depth0;
4025
4026 if (sctx->chip_class <= VI && force_level) {
4027 assert(force_level == first_level &&
4028 force_level == last_level);
4029 base_level = force_level;
4030 first_level = 0;
4031 last_level = 0;
4032 width = u_minify(width, force_level);
4033 height = u_minify(height, force_level);
4034 depth = u_minify(depth, force_level);
4035 }
4036
4037 /* This is not needed if state trackers set last_layer correctly. */
4038 if (state->target == PIPE_TEXTURE_1D ||
4039 state->target == PIPE_TEXTURE_2D ||
4040 state->target == PIPE_TEXTURE_RECT ||
4041 state->target == PIPE_TEXTURE_CUBE)
4042 last_layer = state->u.tex.first_layer;
4043
4044 /* Texturing with separate depth and stencil. */
4045 pipe_format = state->format;
4046
4047 /* Depth/stencil texturing sometimes needs separate texture. */
4048 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4049 if (!tex->flushed_depth_texture &&
4050 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4051 pipe_resource_reference(&view->base.texture, NULL);
4052 FREE(view);
4053 return NULL;
4054 }
4055
4056 assert(tex->flushed_depth_texture);
4057
4058 /* Override format for the case where the flushed texture
4059 * contains only Z or only S.
4060 */
4061 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4062 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4063
4064 tex = tex->flushed_depth_texture;
4065 }
4066
4067 surflevel = tex->surface.u.legacy.level;
4068
4069 if (tex->db_compatible) {
4070 if (!view->is_stencil_sampler)
4071 pipe_format = tex->db_render_format;
4072
4073 switch (pipe_format) {
4074 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4075 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4076 break;
4077 case PIPE_FORMAT_X8Z24_UNORM:
4078 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4079 /* Z24 is always stored like this for DB
4080 * compatibility.
4081 */
4082 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4083 break;
4084 case PIPE_FORMAT_X24S8_UINT:
4085 case PIPE_FORMAT_S8X24_UINT:
4086 case PIPE_FORMAT_X32_S8X24_UINT:
4087 pipe_format = PIPE_FORMAT_S8_UINT;
4088 surflevel = tex->surface.u.legacy.stencil_level;
4089 break;
4090 default:;
4091 }
4092 }
4093
4094 view->dcc_incompatible =
4095 vi_dcc_formats_are_incompatible(texture,
4096 state->u.tex.first_level,
4097 state->format);
4098
4099 si_make_texture_descriptor(sctx->screen, tex, true,
4100 state->target, pipe_format, state_swizzle,
4101 first_level, last_level,
4102 state->u.tex.first_layer, last_layer,
4103 width, height, depth,
4104 view->state, view->fmask_state);
4105
4106 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4107 view->is_integer =
4108 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4109 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4110 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4111 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4112 view->base_level_info = &surflevel[base_level];
4113 view->base_level = base_level;
4114 view->block_width = util_format_get_blockwidth(pipe_format);
4115 return &view->base;
4116 }
4117
4118 static struct pipe_sampler_view *
4119 si_create_sampler_view(struct pipe_context *ctx,
4120 struct pipe_resource *texture,
4121 const struct pipe_sampler_view *state)
4122 {
4123 return si_create_sampler_view_custom(ctx, texture, state,
4124 texture ? texture->width0 : 0,
4125 texture ? texture->height0 : 0, 0);
4126 }
4127
4128 static void si_sampler_view_destroy(struct pipe_context *ctx,
4129 struct pipe_sampler_view *state)
4130 {
4131 struct si_sampler_view *view = (struct si_sampler_view *)state;
4132
4133 pipe_resource_reference(&state->texture, NULL);
4134 FREE(view);
4135 }
4136
4137 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4138 {
4139 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4140 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4141 (linear_filter &&
4142 (wrap == PIPE_TEX_WRAP_CLAMP ||
4143 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4144 }
4145
4146 static uint32_t si_translate_border_color(struct si_context *sctx,
4147 const struct pipe_sampler_state *state,
4148 const union pipe_color_union *color,
4149 bool is_integer)
4150 {
4151 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4152 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4153
4154 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4155 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4156 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4157 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4158
4159 #define simple_border_types(elt) \
4160 do { \
4161 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4162 color->elt[2] == 0 && color->elt[3] == 0) \
4163 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4164 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4165 color->elt[2] == 0 && color->elt[3] == 1) \
4166 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4167 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4168 color->elt[2] == 1 && color->elt[3] == 1) \
4169 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4170 } while (false)
4171
4172 if (is_integer)
4173 simple_border_types(ui);
4174 else
4175 simple_border_types(f);
4176
4177 #undef simple_border_types
4178
4179 int i;
4180
4181 /* Check if the border has been uploaded already. */
4182 for (i = 0; i < sctx->border_color_count; i++)
4183 if (memcmp(&sctx->border_color_table[i], color,
4184 sizeof(*color)) == 0)
4185 break;
4186
4187 if (i >= SI_MAX_BORDER_COLORS) {
4188 /* Getting 4096 unique border colors is very unlikely. */
4189 fprintf(stderr, "radeonsi: The border color table is full. "
4190 "Any new border colors will be just black. "
4191 "Please file a bug.\n");
4192 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4193 }
4194
4195 if (i == sctx->border_color_count) {
4196 /* Upload a new border color. */
4197 memcpy(&sctx->border_color_table[i], color,
4198 sizeof(*color));
4199 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4200 color, sizeof(*color));
4201 sctx->border_color_count++;
4202 }
4203
4204 return S_008F3C_BORDER_COLOR_PTR(i) |
4205 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4206 }
4207
4208 static inline int S_FIXED(float value, unsigned frac_bits)
4209 {
4210 return value * (1 << frac_bits);
4211 }
4212
4213 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4214 {
4215 if (filter == PIPE_TEX_FILTER_LINEAR)
4216 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4217 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4218 else
4219 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4220 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4221 }
4222
4223 static inline unsigned si_tex_aniso_filter(unsigned filter)
4224 {
4225 if (filter < 2)
4226 return 0;
4227 if (filter < 4)
4228 return 1;
4229 if (filter < 8)
4230 return 2;
4231 if (filter < 16)
4232 return 3;
4233 return 4;
4234 }
4235
4236 static void *si_create_sampler_state(struct pipe_context *ctx,
4237 const struct pipe_sampler_state *state)
4238 {
4239 struct si_context *sctx = (struct si_context *)ctx;
4240 struct si_screen *sscreen = sctx->screen;
4241 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4242 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4243 : state->max_anisotropy;
4244 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4245 union pipe_color_union clamped_border_color;
4246
4247 if (!rstate) {
4248 return NULL;
4249 }
4250
4251 #ifdef DEBUG
4252 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4253 #endif
4254 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4255 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4256 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4257 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4258 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4259 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4260 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4261 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4262 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4263 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4264 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4265 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4266 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4267 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4268 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4269 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4270 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4271 S_008F38_MIP_POINT_PRECLAMP(0) |
4272 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4273 S_008F38_FILTER_PREC_FIX(1) |
4274 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4275 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4276
4277 /* Create sampler resource for integer textures. */
4278 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4279 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4280
4281 /* Create sampler resource for upgraded depth textures. */
4282 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4283
4284 for (unsigned i = 0; i < 4; ++i) {
4285 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4286 * when the border color is 1.0. */
4287 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4288 }
4289
4290 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4291 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4292 else
4293 rstate->upgraded_depth_val[3] =
4294 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4295 S_008F3C_UPGRADED_DEPTH(1);
4296
4297 return rstate;
4298 }
4299
4300 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4301 {
4302 struct si_context *sctx = (struct si_context *)ctx;
4303
4304 if (sctx->sample_mask == (uint16_t)sample_mask)
4305 return;
4306
4307 sctx->sample_mask = sample_mask;
4308 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4309 }
4310
4311 static void si_emit_sample_mask(struct si_context *sctx)
4312 {
4313 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4314 unsigned mask = sctx->sample_mask;
4315
4316 /* Needed for line and polygon smoothing as well as for the Polaris
4317 * small primitive filter. We expect the state tracker to take care of
4318 * this for us.
4319 */
4320 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4321 (mask & 1 && sctx->blitter->running));
4322
4323 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4324 radeon_emit(cs, mask | (mask << 16));
4325 radeon_emit(cs, mask | (mask << 16));
4326 }
4327
4328 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4329 {
4330 #ifdef DEBUG
4331 struct si_sampler_state *s = state;
4332
4333 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4334 s->magic = 0;
4335 #endif
4336 free(state);
4337 }
4338
4339 /*
4340 * Vertex elements & buffers
4341 */
4342
4343 static void *si_create_vertex_elements(struct pipe_context *ctx,
4344 unsigned count,
4345 const struct pipe_vertex_element *elements)
4346 {
4347 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4348 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4349 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4350 int i;
4351
4352 assert(count <= SI_MAX_ATTRIBS);
4353 if (!v)
4354 return NULL;
4355
4356 v->count = count;
4357 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4358
4359 for (i = 0; i < count; ++i) {
4360 const struct util_format_description *desc;
4361 const struct util_format_channel_description *channel;
4362 unsigned data_format, num_format;
4363 int first_non_void;
4364 unsigned vbo_index = elements[i].vertex_buffer_index;
4365 unsigned char swizzle[4];
4366
4367 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4368 FREE(v);
4369 return NULL;
4370 }
4371
4372 if (elements[i].instance_divisor) {
4373 v->uses_instance_divisors = true;
4374 v->instance_divisors[i] = elements[i].instance_divisor;
4375
4376 if (v->instance_divisors[i] == 1)
4377 v->instance_divisor_is_one |= 1u << i;
4378 else
4379 v->instance_divisor_is_fetched |= 1u << i;
4380 }
4381
4382 if (!used[vbo_index]) {
4383 v->first_vb_use_mask |= 1 << i;
4384 used[vbo_index] = true;
4385 }
4386
4387 desc = util_format_description(elements[i].src_format);
4388 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4389 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4390 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4391 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4392 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4393
4394 v->format_size[i] = desc->block.bits / 8;
4395 v->src_offset[i] = elements[i].src_offset;
4396 v->vertex_buffer_index[i] = vbo_index;
4397
4398 /* The hardware always treats the 2-bit alpha channel as
4399 * unsigned, so a shader workaround is needed. The affected
4400 * chips are VI and older except Stoney (GFX8.1).
4401 */
4402 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4403 sscreen->info.chip_class <= VI &&
4404 sscreen->info.family != CHIP_STONEY) {
4405 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4406 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4407 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4408 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4409 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4410 /* This isn't actually used in OpenGL. */
4411 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4412 }
4413 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4414 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4415 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4416 else
4417 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4418 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4419 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4420 if (channel->normalized) {
4421 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4422 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4423 else
4424 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4425 } else {
4426 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4427 }
4428 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4429 if (channel->normalized) {
4430 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4431 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4432 else
4433 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4434 } else {
4435 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4436 }
4437 }
4438 } else if (channel && channel->size == 64 &&
4439 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4440 switch (desc->nr_channels) {
4441 case 1:
4442 case 2:
4443 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4444 swizzle[0] = PIPE_SWIZZLE_X;
4445 swizzle[1] = PIPE_SWIZZLE_Y;
4446 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4447 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4448 break;
4449 case 3:
4450 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4451 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4452 swizzle[1] = PIPE_SWIZZLE_Y;
4453 swizzle[2] = PIPE_SWIZZLE_0;
4454 swizzle[3] = PIPE_SWIZZLE_0;
4455 break;
4456 case 4:
4457 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4458 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4459 swizzle[1] = PIPE_SWIZZLE_Y;
4460 swizzle[2] = PIPE_SWIZZLE_Z;
4461 swizzle[3] = PIPE_SWIZZLE_W;
4462 break;
4463 default:
4464 assert(0);
4465 }
4466 } else if (channel && desc->nr_channels == 3) {
4467 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4468
4469 if (channel->size == 8) {
4470 if (channel->pure_integer)
4471 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4472 else
4473 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4474 } else if (channel->size == 16) {
4475 if (channel->pure_integer)
4476 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4477 else
4478 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4479 }
4480 }
4481
4482 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4483 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4484 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4485 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4486 S_008F0C_NUM_FORMAT(num_format) |
4487 S_008F0C_DATA_FORMAT(data_format);
4488 }
4489 return v;
4490 }
4491
4492 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4493 {
4494 struct si_context *sctx = (struct si_context *)ctx;
4495 struct si_vertex_elements *old = sctx->vertex_elements;
4496 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4497
4498 sctx->vertex_elements = v;
4499 sctx->vertex_buffers_dirty = true;
4500
4501 if (v &&
4502 (!old ||
4503 old->count != v->count ||
4504 old->uses_instance_divisors != v->uses_instance_divisors ||
4505 v->uses_instance_divisors || /* we don't check which divisors changed */
4506 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4507 sctx->do_update_shaders = true;
4508
4509 if (v && v->instance_divisor_is_fetched) {
4510 struct pipe_constant_buffer cb;
4511
4512 cb.buffer = NULL;
4513 cb.user_buffer = v->instance_divisors;
4514 cb.buffer_offset = 0;
4515 cb.buffer_size = sizeof(uint32_t) * v->count;
4516 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4517 }
4518 }
4519
4520 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4521 {
4522 struct si_context *sctx = (struct si_context *)ctx;
4523
4524 if (sctx->vertex_elements == state)
4525 sctx->vertex_elements = NULL;
4526 FREE(state);
4527 }
4528
4529 static void si_set_vertex_buffers(struct pipe_context *ctx,
4530 unsigned start_slot, unsigned count,
4531 const struct pipe_vertex_buffer *buffers)
4532 {
4533 struct si_context *sctx = (struct si_context *)ctx;
4534 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4535 int i;
4536
4537 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4538
4539 if (buffers) {
4540 for (i = 0; i < count; i++) {
4541 const struct pipe_vertex_buffer *src = buffers + i;
4542 struct pipe_vertex_buffer *dsti = dst + i;
4543 struct pipe_resource *buf = src->buffer.resource;
4544
4545 pipe_resource_reference(&dsti->buffer.resource, buf);
4546 dsti->buffer_offset = src->buffer_offset;
4547 dsti->stride = src->stride;
4548 si_context_add_resource_size(sctx, buf);
4549 if (buf)
4550 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4551 }
4552 } else {
4553 for (i = 0; i < count; i++) {
4554 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4555 }
4556 }
4557 sctx->vertex_buffers_dirty = true;
4558 }
4559
4560 /*
4561 * Misc
4562 */
4563
4564 static void si_set_tess_state(struct pipe_context *ctx,
4565 const float default_outer_level[4],
4566 const float default_inner_level[2])
4567 {
4568 struct si_context *sctx = (struct si_context *)ctx;
4569 struct pipe_constant_buffer cb;
4570 float array[8];
4571
4572 memcpy(array, default_outer_level, sizeof(float) * 4);
4573 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4574
4575 cb.buffer = NULL;
4576 cb.user_buffer = NULL;
4577 cb.buffer_size = sizeof(array);
4578
4579 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4580 (void*)array, sizeof(array),
4581 &cb.buffer_offset);
4582
4583 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4584 pipe_resource_reference(&cb.buffer, NULL);
4585 }
4586
4587 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4588 {
4589 struct si_context *sctx = (struct si_context *)ctx;
4590
4591 si_update_fb_dirtiness_after_rendering(sctx);
4592
4593 /* Multisample surfaces are flushed in si_decompress_textures. */
4594 if (sctx->framebuffer.uncompressed_cb_mask)
4595 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4596 sctx->framebuffer.CB_has_shader_readable_metadata);
4597 }
4598
4599 /* This only ensures coherency for shader image/buffer stores. */
4600 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4601 {
4602 struct si_context *sctx = (struct si_context *)ctx;
4603
4604 /* Subsequent commands must wait for all shader invocations to
4605 * complete. */
4606 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4607 SI_CONTEXT_CS_PARTIAL_FLUSH;
4608
4609 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4610 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4611 SI_CONTEXT_INV_VMEM_L1;
4612
4613 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4614 PIPE_BARRIER_SHADER_BUFFER |
4615 PIPE_BARRIER_TEXTURE |
4616 PIPE_BARRIER_IMAGE |
4617 PIPE_BARRIER_STREAMOUT_BUFFER |
4618 PIPE_BARRIER_GLOBAL_BUFFER)) {
4619 /* As far as I can tell, L1 contents are written back to L2
4620 * automatically at end of shader, but the contents of other
4621 * L1 caches might still be stale. */
4622 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4623 }
4624
4625 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4626 /* Indices are read through TC L2 since VI.
4627 * L1 isn't used.
4628 */
4629 if (sctx->screen->info.chip_class <= CIK)
4630 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4631 }
4632
4633 /* MSAA color, any depth and any stencil are flushed in
4634 * si_decompress_textures when needed.
4635 */
4636 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4637 sctx->framebuffer.uncompressed_cb_mask) {
4638 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4639
4640 if (sctx->chip_class <= VI)
4641 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4642 }
4643
4644 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4645 if (sctx->screen->info.chip_class <= VI &&
4646 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4647 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4648 }
4649
4650 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4651 {
4652 struct pipe_blend_state blend;
4653
4654 memset(&blend, 0, sizeof(blend));
4655 blend.independent_blend_enable = true;
4656 blend.rt[0].colormask = 0xf;
4657 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4658 }
4659
4660 static void si_init_config(struct si_context *sctx);
4661
4662 void si_init_state_functions(struct si_context *sctx)
4663 {
4664 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4665 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4666 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4667 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4668 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4669 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4670 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4671 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4672 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4673 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4674 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4675
4676 sctx->b.create_blend_state = si_create_blend_state;
4677 sctx->b.bind_blend_state = si_bind_blend_state;
4678 sctx->b.delete_blend_state = si_delete_blend_state;
4679 sctx->b.set_blend_color = si_set_blend_color;
4680
4681 sctx->b.create_rasterizer_state = si_create_rs_state;
4682 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4683 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4684
4685 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4686 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4687 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4688
4689 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4690 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4691 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4692 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4693 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4694
4695 sctx->b.set_clip_state = si_set_clip_state;
4696 sctx->b.set_stencil_ref = si_set_stencil_ref;
4697
4698 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4699
4700 sctx->b.create_sampler_state = si_create_sampler_state;
4701 sctx->b.delete_sampler_state = si_delete_sampler_state;
4702
4703 sctx->b.create_sampler_view = si_create_sampler_view;
4704 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4705
4706 sctx->b.set_sample_mask = si_set_sample_mask;
4707
4708 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4709 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4710 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4711 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4712
4713 sctx->b.texture_barrier = si_texture_barrier;
4714 sctx->b.memory_barrier = si_memory_barrier;
4715 sctx->b.set_min_samples = si_set_min_samples;
4716 sctx->b.set_tess_state = si_set_tess_state;
4717
4718 sctx->b.set_active_query_state = si_set_active_query_state;
4719
4720 sctx->b.draw_vbo = si_draw_vbo;
4721
4722 si_init_config(sctx);
4723 }
4724
4725 void si_init_screen_state_functions(struct si_screen *sscreen)
4726 {
4727 sscreen->b.is_format_supported = si_is_format_supported;
4728 }
4729
4730 static void si_set_grbm_gfx_index(struct si_context *sctx,
4731 struct si_pm4_state *pm4, unsigned value)
4732 {
4733 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4734 R_00802C_GRBM_GFX_INDEX;
4735 si_pm4_set_reg(pm4, reg, value);
4736 }
4737
4738 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4739 struct si_pm4_state *pm4, unsigned se)
4740 {
4741 assert(se == ~0 || se < sctx->screen->info.max_se);
4742 si_set_grbm_gfx_index(sctx, pm4,
4743 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4744 S_030800_SE_INDEX(se)) |
4745 S_030800_SH_BROADCAST_WRITES(1) |
4746 S_030800_INSTANCE_BROADCAST_WRITES(1));
4747 }
4748
4749 static void
4750 si_write_harvested_raster_configs(struct si_context *sctx,
4751 struct si_pm4_state *pm4,
4752 unsigned raster_config,
4753 unsigned raster_config_1)
4754 {
4755 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4756 unsigned raster_config_se[4];
4757 unsigned se;
4758
4759 ac_get_harvested_configs(&sctx->screen->info,
4760 raster_config,
4761 &raster_config_1,
4762 raster_config_se);
4763
4764 for (se = 0; se < num_se; se++) {
4765 si_set_grbm_gfx_index_se(sctx, pm4, se);
4766 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4767 }
4768 si_set_grbm_gfx_index(sctx, pm4, ~0);
4769
4770 if (sctx->chip_class >= CIK) {
4771 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4772 }
4773 }
4774
4775 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4776 {
4777 unsigned num_rb = MIN2(sctx->screen->info.num_render_backends, 16);
4778 unsigned rb_mask = sctx->screen->info.enabled_rb_mask;
4779 unsigned raster_config, raster_config_1;
4780
4781 ac_get_raster_config(&sctx->screen->info,
4782 &raster_config,
4783 &raster_config_1);
4784
4785 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4786 /* Always use the default config when all backends are enabled
4787 * (or when we failed to determine the enabled backends).
4788 */
4789 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4790 raster_config);
4791 if (sctx->chip_class >= CIK)
4792 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4793 raster_config_1);
4794 } else {
4795 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4796 }
4797 }
4798
4799 static void si_init_config(struct si_context *sctx)
4800 {
4801 struct si_screen *sscreen = sctx->screen;
4802 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4803 bool has_clear_state = sscreen->has_clear_state;
4804 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4805
4806 /* Only SI can disable CLEAR_STATE for now. */
4807 assert(has_clear_state || sscreen->info.chip_class == SI);
4808
4809 if (!pm4)
4810 return;
4811
4812 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4813 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4814 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4815 si_pm4_cmd_end(pm4, false);
4816
4817 if (has_clear_state) {
4818 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4819 si_pm4_cmd_add(pm4, 0);
4820 si_pm4_cmd_end(pm4, false);
4821 }
4822
4823 if (sctx->chip_class <= VI)
4824 si_set_raster_config(sctx, pm4);
4825
4826 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4827 if (!has_clear_state)
4828 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4829
4830 /* FIXME calculate these values somehow ??? */
4831 if (sctx->chip_class <= VI) {
4832 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4833 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4834 }
4835
4836 if (!has_clear_state) {
4837 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4838 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4839 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4840 }
4841
4842 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4843 if (!has_clear_state)
4844 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4845 if (sctx->chip_class < CIK)
4846 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4847 S_008A14_CLIP_VTX_REORDER_ENA(1));
4848
4849 if (!has_clear_state)
4850 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4851
4852 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4853 * I don't know why. Deduced by trial and error.
4854 */
4855 if (sctx->chip_class <= CIK) {
4856 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4857 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4858 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4859 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4860 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4861 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4862 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4863 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4864 }
4865
4866 if (!has_clear_state) {
4867 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4868 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4869 S_028230_ER_TRI(0xA) |
4870 S_028230_ER_POINT(0xA) |
4871 S_028230_ER_RECT(0xA) |
4872 /* Required by DX10_DIAMOND_TEST_ENA: */
4873 S_028230_ER_LINE_LR(0x1A) |
4874 S_028230_ER_LINE_RL(0x26) |
4875 S_028230_ER_LINE_TB(0xA) |
4876 S_028230_ER_LINE_BT(0xA));
4877 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4878 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4879 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4880 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4881 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4882 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4883 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4884 }
4885
4886 if (sctx->chip_class >= GFX9) {
4887 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4888 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4889 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4890 } else {
4891 /* These registers, when written, also overwrite the CLEAR_STATE
4892 * context, so we can't rely on CLEAR_STATE setting them.
4893 * It would be an issue if there was another UMD changing them.
4894 */
4895 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4896 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4897 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4898 }
4899
4900 if (sctx->chip_class >= CIK) {
4901 if (sctx->chip_class >= GFX9) {
4902 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4903 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4904 } else {
4905 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4906 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4907 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4908 S_00B41C_WAVE_LIMIT(0x3F));
4909 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4910 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4911
4912 /* If this is 0, Bonaire can hang even if GS isn't being used.
4913 * Other chips are unaffected. These are suboptimal values,
4914 * but we don't use on-chip GS.
4915 */
4916 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4917 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4918 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4919 }
4920 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4921 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4922
4923 /* Compute LATE_ALLOC_VS.LIMIT. */
4924 unsigned num_cu_per_sh = sscreen->info.num_good_compute_units /
4925 (sscreen->info.max_se *
4926 sscreen->info.max_sh_per_se);
4927 unsigned late_alloc_limit; /* The limit is per SH. */
4928
4929 if (sctx->family == CHIP_KABINI) {
4930 late_alloc_limit = 0; /* Potential hang on Kabini. */
4931 } else if (num_cu_per_sh <= 4) {
4932 /* Too few available compute units per SH. Disallowing
4933 * VS to run on one CU could hurt us more than late VS
4934 * allocation would help.
4935 *
4936 * 2 is the highest safe number that allows us to keep
4937 * all CUs enabled.
4938 */
4939 late_alloc_limit = 2;
4940 } else {
4941 /* This is a good initial value, allowing 1 late_alloc
4942 * wave per SIMD on num_cu - 2.
4943 */
4944 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4945
4946 /* The limit is 0-based, so 0 means 1. */
4947 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4948 late_alloc_limit -= 1;
4949 }
4950
4951 /* VS can't execute on one CU if the limit is > 2. */
4952 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4953 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4954 S_00B118_WAVE_LIMIT(0x3F));
4955 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4956 S_00B11C_LIMIT(late_alloc_limit));
4957 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4958 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4959 }
4960
4961 if (sctx->chip_class >= VI) {
4962 unsigned vgt_tess_distribution;
4963
4964 vgt_tess_distribution =
4965 S_028B50_ACCUM_ISOLINE(32) |
4966 S_028B50_ACCUM_TRI(11) |
4967 S_028B50_ACCUM_QUAD(11) |
4968 S_028B50_DONUT_SPLIT(16);
4969
4970 /* Testing with Unigine Heaven extreme tesselation yielded best results
4971 * with TRAP_SPLIT = 3.
4972 */
4973 if (sctx->family == CHIP_FIJI ||
4974 sctx->family >= CHIP_POLARIS10)
4975 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4976
4977 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4978 } else if (!has_clear_state) {
4979 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4980 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4981 }
4982
4983 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4984 if (sctx->chip_class >= CIK) {
4985 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
4986 S_028084_ADDRESS(border_color_va >> 40));
4987 }
4988 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4989 RADEON_PRIO_BORDER_COLORS);
4990
4991 if (sctx->chip_class >= GFX9) {
4992 unsigned num_se = sscreen->info.max_se;
4993 unsigned pc_lines = 0;
4994
4995 switch (sctx->family) {
4996 case CHIP_VEGA10:
4997 case CHIP_VEGA12:
4998 pc_lines = 4096;
4999 break;
5000 case CHIP_RAVEN:
5001 pc_lines = 1024;
5002 break;
5003 default:
5004 assert(0);
5005 }
5006
5007 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5008 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5009 S_028C48_MAX_PRIM_PER_BATCH(1023));
5010 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5011 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5012 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5013 }
5014
5015 si_pm4_upload_indirect_buffer(sctx, pm4);
5016 sctx->init_config = pm4;
5017 }