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radeonsi: precompute some fields for PA_CL_VS_OUT_CNTL in si_shader_selector
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
607 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
608 sctx->do_update_shaders = true;
609 }
610
611 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
612 {
613 struct si_context *sctx = (struct si_context *)ctx;
614 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
615 }
616
617 static void si_set_blend_color(struct pipe_context *ctx,
618 const struct pipe_blend_color *state)
619 {
620 struct si_context *sctx = (struct si_context *)ctx;
621
622 sctx->blend_color.state = *state;
623 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
624 }
625
626 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
627 {
628 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
629
630 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
631 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
632 }
633
634 /*
635 * Clipping
636 */
637
638 static void si_set_clip_state(struct pipe_context *ctx,
639 const struct pipe_clip_state *state)
640 {
641 struct si_context *sctx = (struct si_context *)ctx;
642 struct pipe_constant_buffer cb;
643
644 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
645 return;
646
647 sctx->clip_state.state = *state;
648 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
649
650 cb.buffer = NULL;
651 cb.user_buffer = state->ucp;
652 cb.buffer_offset = 0;
653 cb.buffer_size = 4*4*8;
654 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
655 pipe_resource_reference(&cb.buffer, NULL);
656 }
657
658 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
659 {
660 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
661
662 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
663 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
664 }
665
666 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
667 {
668 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
669 struct si_shader *vs = si_get_vs_state(sctx);
670 struct si_shader_selector *vs_sel = vs->selector;
671 struct tgsi_shader_info *info = &vs_sel->info;
672 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
673 unsigned window_space =
674 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
675 unsigned clipdist_mask = vs_sel->clipdist_mask;
676 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
677 unsigned culldist_mask = vs_sel->culldist_mask;
678 unsigned total_mask;
679
680 if (vs->key.opt.hw_vs.clip_disable) {
681 assert(!info->culldist_writemask);
682 clipdist_mask = 0;
683 culldist_mask = 0;
684 }
685 total_mask = clipdist_mask | culldist_mask;
686
687 /* Clip distances on points have no effect, so need to be implemented
688 * as cull distances. This applies for the clipvertex case as well.
689 *
690 * Setting this for primitives other than points should have no adverse
691 * effects.
692 */
693 clipdist_mask &= rs->clip_plane_enable;
694 culldist_mask |= clipdist_mask;
695
696 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
697 vs_sel->pa_cl_vs_out_cntl |
698 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
699 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
700 clipdist_mask | (culldist_mask << 8));
701 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
702 rs->pa_cl_clip_cntl |
703 ucp_mask |
704 S_028810_CLIP_DISABLE(window_space));
705
706 if (sctx->b.chip_class <= VI) {
707 /* reuse needs to be set off if we write oViewport */
708 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
709 S_028AB4_REUSE_OFF(info->writes_viewport_index));
710 }
711 }
712
713 /*
714 * inferred state between framebuffer and rasterizer
715 */
716 static void si_update_poly_offset_state(struct si_context *sctx)
717 {
718 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
719
720 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
721 si_pm4_bind_state(sctx, poly_offset, NULL);
722 return;
723 }
724
725 /* Use the user format, not db_render_format, so that the polygon
726 * offset behaves as expected by applications.
727 */
728 switch (sctx->framebuffer.state.zsbuf->texture->format) {
729 case PIPE_FORMAT_Z16_UNORM:
730 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
731 break;
732 default: /* 24-bit */
733 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
734 break;
735 case PIPE_FORMAT_Z32_FLOAT:
736 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
737 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
738 break;
739 }
740 }
741
742 /*
743 * Rasterizer
744 */
745
746 static uint32_t si_translate_fill(uint32_t func)
747 {
748 switch(func) {
749 case PIPE_POLYGON_MODE_FILL:
750 return V_028814_X_DRAW_TRIANGLES;
751 case PIPE_POLYGON_MODE_LINE:
752 return V_028814_X_DRAW_LINES;
753 case PIPE_POLYGON_MODE_POINT:
754 return V_028814_X_DRAW_POINTS;
755 default:
756 assert(0);
757 return V_028814_X_DRAW_POINTS;
758 }
759 }
760
761 static void *si_create_rs_state(struct pipe_context *ctx,
762 const struct pipe_rasterizer_state *state)
763 {
764 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
765 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
766 struct si_pm4_state *pm4 = &rs->pm4;
767 unsigned tmp, i;
768 float psize_min, psize_max;
769
770 if (!rs) {
771 return NULL;
772 }
773
774 rs->scissor_enable = state->scissor;
775 rs->clip_halfz = state->clip_halfz;
776 rs->two_side = state->light_twoside;
777 rs->multisample_enable = state->multisample;
778 rs->force_persample_interp = state->force_persample_interp;
779 rs->clip_plane_enable = state->clip_plane_enable;
780 rs->line_stipple_enable = state->line_stipple_enable;
781 rs->poly_stipple_enable = state->poly_stipple_enable;
782 rs->line_smooth = state->line_smooth;
783 rs->poly_smooth = state->poly_smooth;
784 rs->uses_poly_offset = state->offset_point || state->offset_line ||
785 state->offset_tri;
786 rs->clamp_fragment_color = state->clamp_fragment_color;
787 rs->clamp_vertex_color = state->clamp_vertex_color;
788 rs->flatshade = state->flatshade;
789 rs->sprite_coord_enable = state->sprite_coord_enable;
790 rs->rasterizer_discard = state->rasterizer_discard;
791 rs->pa_sc_line_stipple = state->line_stipple_enable ?
792 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
793 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
794 rs->pa_cl_clip_cntl =
795 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
796 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
797 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
798 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
799 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
800
801 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
802 S_0286D4_FLAT_SHADE_ENA(1) |
803 S_0286D4_PNT_SPRITE_ENA(1) |
804 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
805 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
806 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
807 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
808 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
809
810 /* point size 12.4 fixed point */
811 tmp = (unsigned)(state->point_size * 8.0);
812 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
813
814 if (state->point_size_per_vertex) {
815 psize_min = util_get_min_point_size(state);
816 psize_max = 8192;
817 } else {
818 /* Force the point size to be as if the vertex output was disabled. */
819 psize_min = state->point_size;
820 psize_max = state->point_size;
821 }
822 /* Divide by two, because 0.5 = 1 pixel. */
823 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
824 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
825 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
826
827 tmp = (unsigned)state->line_width * 8;
828 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
829 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
830 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
831 S_028A48_MSAA_ENABLE(state->multisample ||
832 state->poly_smooth ||
833 state->line_smooth) |
834 S_028A48_VPORT_SCISSOR_ENABLE(1) |
835 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
836
837 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
838 S_028BE4_PIX_CENTER(state->half_pixel_center) |
839 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
840
841 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
842 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
843 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
844 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
845 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
846 S_028814_FACE(!state->front_ccw) |
847 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
848 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
849 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
850 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
851 state->fill_back != PIPE_POLYGON_MODE_FILL) |
852 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
853 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
854
855 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
856 for (i = 0; i < 3; i++) {
857 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
858 float offset_units = state->offset_units;
859 float offset_scale = state->offset_scale * 16.0f;
860 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
861
862 if (!state->offset_units_unscaled) {
863 switch (i) {
864 case 0: /* 16-bit zbuffer */
865 offset_units *= 4.0f;
866 pa_su_poly_offset_db_fmt_cntl =
867 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
868 break;
869 case 1: /* 24-bit zbuffer */
870 offset_units *= 2.0f;
871 pa_su_poly_offset_db_fmt_cntl =
872 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
873 break;
874 case 2: /* 32-bit zbuffer */
875 offset_units *= 1.0f;
876 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
877 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
878 break;
879 }
880 }
881
882 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
883 fui(offset_scale));
884 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
885 fui(offset_units));
886 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
887 fui(offset_scale));
888 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
889 fui(offset_units));
890 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
891 pa_su_poly_offset_db_fmt_cntl);
892 }
893
894 return rs;
895 }
896
897 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
898 {
899 struct si_context *sctx = (struct si_context *)ctx;
900 struct si_state_rasterizer *old_rs =
901 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
902 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
903
904 if (!state)
905 return;
906
907 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
908 si_mark_atom_dirty(sctx, &sctx->db_render_state);
909
910 /* Update the small primitive filter workaround if necessary. */
911 if (sctx->screen->has_msaa_sample_loc_bug &&
912 sctx->framebuffer.nr_samples > 1)
913 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
914 }
915
916 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
917 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
918
919 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
920
921 si_pm4_bind_state(sctx, rasterizer, rs);
922 si_update_poly_offset_state(sctx);
923
924 si_mark_atom_dirty(sctx, &sctx->clip_regs);
925 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
926 rs->line_stipple_enable;
927 sctx->do_update_shaders = true;
928 }
929
930 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
931 {
932 struct si_context *sctx = (struct si_context *)ctx;
933
934 if (sctx->queued.named.rasterizer == state)
935 si_pm4_bind_state(sctx, poly_offset, NULL);
936 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
937 }
938
939 /*
940 * infeered state between dsa and stencil ref
941 */
942 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
943 {
944 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
945 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
946 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
947
948 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
949 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
950 S_028430_STENCILMASK(dsa->valuemask[0]) |
951 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
952 S_028430_STENCILOPVAL(1));
953 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
954 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
955 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
956 S_028434_STENCILOPVAL_BF(1));
957 }
958
959 static void si_set_stencil_ref(struct pipe_context *ctx,
960 const struct pipe_stencil_ref *state)
961 {
962 struct si_context *sctx = (struct si_context *)ctx;
963
964 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
965 return;
966
967 sctx->stencil_ref.state = *state;
968 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
969 }
970
971
972 /*
973 * DSA
974 */
975
976 static uint32_t si_translate_stencil_op(int s_op)
977 {
978 switch (s_op) {
979 case PIPE_STENCIL_OP_KEEP:
980 return V_02842C_STENCIL_KEEP;
981 case PIPE_STENCIL_OP_ZERO:
982 return V_02842C_STENCIL_ZERO;
983 case PIPE_STENCIL_OP_REPLACE:
984 return V_02842C_STENCIL_REPLACE_TEST;
985 case PIPE_STENCIL_OP_INCR:
986 return V_02842C_STENCIL_ADD_CLAMP;
987 case PIPE_STENCIL_OP_DECR:
988 return V_02842C_STENCIL_SUB_CLAMP;
989 case PIPE_STENCIL_OP_INCR_WRAP:
990 return V_02842C_STENCIL_ADD_WRAP;
991 case PIPE_STENCIL_OP_DECR_WRAP:
992 return V_02842C_STENCIL_SUB_WRAP;
993 case PIPE_STENCIL_OP_INVERT:
994 return V_02842C_STENCIL_INVERT;
995 default:
996 R600_ERR("Unknown stencil op %d", s_op);
997 assert(0);
998 break;
999 }
1000 return 0;
1001 }
1002
1003 static void *si_create_dsa_state(struct pipe_context *ctx,
1004 const struct pipe_depth_stencil_alpha_state *state)
1005 {
1006 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1007 struct si_pm4_state *pm4 = &dsa->pm4;
1008 unsigned db_depth_control;
1009 uint32_t db_stencil_control = 0;
1010
1011 if (!dsa) {
1012 return NULL;
1013 }
1014
1015 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1016 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1017 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1018 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1019
1020 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1021 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1022 S_028800_ZFUNC(state->depth.func) |
1023 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1024
1025 /* stencil */
1026 if (state->stencil[0].enabled) {
1027 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1028 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1029 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1030 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1031 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1032
1033 if (state->stencil[1].enabled) {
1034 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1035 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1036 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1037 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1038 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1039 }
1040 }
1041
1042 /* alpha */
1043 if (state->alpha.enabled) {
1044 dsa->alpha_func = state->alpha.func;
1045
1046 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1047 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1048 } else {
1049 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1050 }
1051
1052 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1053 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1054 if (state->depth.bounds_test) {
1055 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1056 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1057 }
1058
1059 return dsa;
1060 }
1061
1062 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1063 {
1064 struct si_context *sctx = (struct si_context *)ctx;
1065 struct si_state_dsa *dsa = state;
1066
1067 if (!state)
1068 return;
1069
1070 si_pm4_bind_state(sctx, dsa, dsa);
1071
1072 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1073 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1074 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1075 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1076 }
1077 sctx->do_update_shaders = true;
1078 }
1079
1080 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1081 {
1082 struct si_context *sctx = (struct si_context *)ctx;
1083 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1084 }
1085
1086 static void *si_create_db_flush_dsa(struct si_context *sctx)
1087 {
1088 struct pipe_depth_stencil_alpha_state dsa = {};
1089
1090 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1091 }
1092
1093 /* DB RENDER STATE */
1094
1095 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1096 {
1097 struct si_context *sctx = (struct si_context*)ctx;
1098
1099 /* Pipeline stat & streamout queries. */
1100 if (enable) {
1101 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1102 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1103 } else {
1104 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1105 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1106 }
1107
1108 /* Occlusion queries. */
1109 if (sctx->occlusion_queries_disabled != !enable) {
1110 sctx->occlusion_queries_disabled = !enable;
1111 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1112 }
1113 }
1114
1115 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1116 {
1117 struct si_context *sctx = (struct si_context*)ctx;
1118
1119 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1120 }
1121
1122 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1123 {
1124 struct si_context *sctx = (struct si_context*)ctx;
1125
1126 st->saved_compute = sctx->cs_shader_state.program;
1127
1128 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1129 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1130 }
1131
1132 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1133 {
1134 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1135 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1136 unsigned db_shader_control;
1137
1138 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1139
1140 /* DB_RENDER_CONTROL */
1141 if (sctx->dbcb_depth_copy_enabled ||
1142 sctx->dbcb_stencil_copy_enabled) {
1143 radeon_emit(cs,
1144 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1145 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1146 S_028000_COPY_CENTROID(1) |
1147 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1148 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1149 radeon_emit(cs,
1150 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1151 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1152 } else {
1153 radeon_emit(cs,
1154 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1155 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1156 }
1157
1158 /* DB_COUNT_CONTROL (occlusion queries) */
1159 if (sctx->b.num_occlusion_queries > 0 &&
1160 !sctx->occlusion_queries_disabled) {
1161 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1162
1163 if (sctx->b.chip_class >= CIK) {
1164 radeon_emit(cs,
1165 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1166 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1167 S_028004_ZPASS_ENABLE(1) |
1168 S_028004_SLICE_EVEN_ENABLE(1) |
1169 S_028004_SLICE_ODD_ENABLE(1));
1170 } else {
1171 radeon_emit(cs,
1172 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1173 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1174 }
1175 } else {
1176 /* Disable occlusion queries. */
1177 if (sctx->b.chip_class >= CIK) {
1178 radeon_emit(cs, 0);
1179 } else {
1180 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1181 }
1182 }
1183
1184 /* DB_RENDER_OVERRIDE2 */
1185 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1186 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1187 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1188 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1189
1190 db_shader_control = sctx->ps_db_shader_control;
1191
1192 /* Bug workaround for smoothing (overrasterization) on SI. */
1193 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1194 db_shader_control &= C_02880C_Z_ORDER;
1195 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1196 }
1197
1198 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1199 if (!rs || !rs->multisample_enable)
1200 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1201
1202 if (sctx->screen->b.has_rbplus &&
1203 !sctx->screen->b.rbplus_allowed)
1204 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1205
1206 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1207 db_shader_control);
1208 }
1209
1210 /*
1211 * format translation
1212 */
1213 static uint32_t si_translate_colorformat(enum pipe_format format)
1214 {
1215 const struct util_format_description *desc = util_format_description(format);
1216
1217 #define HAS_SIZE(x,y,z,w) \
1218 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1219 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1220
1221 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1222 return V_028C70_COLOR_10_11_11;
1223
1224 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1225 return V_028C70_COLOR_INVALID;
1226
1227 /* hw cannot support mixed formats (except depth/stencil, since
1228 * stencil is not written to). */
1229 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1230 return V_028C70_COLOR_INVALID;
1231
1232 switch (desc->nr_channels) {
1233 case 1:
1234 switch (desc->channel[0].size) {
1235 case 8:
1236 return V_028C70_COLOR_8;
1237 case 16:
1238 return V_028C70_COLOR_16;
1239 case 32:
1240 return V_028C70_COLOR_32;
1241 }
1242 break;
1243 case 2:
1244 if (desc->channel[0].size == desc->channel[1].size) {
1245 switch (desc->channel[0].size) {
1246 case 8:
1247 return V_028C70_COLOR_8_8;
1248 case 16:
1249 return V_028C70_COLOR_16_16;
1250 case 32:
1251 return V_028C70_COLOR_32_32;
1252 }
1253 } else if (HAS_SIZE(8,24,0,0)) {
1254 return V_028C70_COLOR_24_8;
1255 } else if (HAS_SIZE(24,8,0,0)) {
1256 return V_028C70_COLOR_8_24;
1257 }
1258 break;
1259 case 3:
1260 if (HAS_SIZE(5,6,5,0)) {
1261 return V_028C70_COLOR_5_6_5;
1262 } else if (HAS_SIZE(32,8,24,0)) {
1263 return V_028C70_COLOR_X24_8_32_FLOAT;
1264 }
1265 break;
1266 case 4:
1267 if (desc->channel[0].size == desc->channel[1].size &&
1268 desc->channel[0].size == desc->channel[2].size &&
1269 desc->channel[0].size == desc->channel[3].size) {
1270 switch (desc->channel[0].size) {
1271 case 4:
1272 return V_028C70_COLOR_4_4_4_4;
1273 case 8:
1274 return V_028C70_COLOR_8_8_8_8;
1275 case 16:
1276 return V_028C70_COLOR_16_16_16_16;
1277 case 32:
1278 return V_028C70_COLOR_32_32_32_32;
1279 }
1280 } else if (HAS_SIZE(5,5,5,1)) {
1281 return V_028C70_COLOR_1_5_5_5;
1282 } else if (HAS_SIZE(10,10,10,2)) {
1283 return V_028C70_COLOR_2_10_10_10;
1284 }
1285 break;
1286 }
1287 return V_028C70_COLOR_INVALID;
1288 }
1289
1290 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1291 {
1292 if (SI_BIG_ENDIAN) {
1293 switch(colorformat) {
1294 /* 8-bit buffers. */
1295 case V_028C70_COLOR_8:
1296 return V_028C70_ENDIAN_NONE;
1297
1298 /* 16-bit buffers. */
1299 case V_028C70_COLOR_5_6_5:
1300 case V_028C70_COLOR_1_5_5_5:
1301 case V_028C70_COLOR_4_4_4_4:
1302 case V_028C70_COLOR_16:
1303 case V_028C70_COLOR_8_8:
1304 return V_028C70_ENDIAN_8IN16;
1305
1306 /* 32-bit buffers. */
1307 case V_028C70_COLOR_8_8_8_8:
1308 case V_028C70_COLOR_2_10_10_10:
1309 case V_028C70_COLOR_8_24:
1310 case V_028C70_COLOR_24_8:
1311 case V_028C70_COLOR_16_16:
1312 return V_028C70_ENDIAN_8IN32;
1313
1314 /* 64-bit buffers. */
1315 case V_028C70_COLOR_16_16_16_16:
1316 return V_028C70_ENDIAN_8IN16;
1317
1318 case V_028C70_COLOR_32_32:
1319 return V_028C70_ENDIAN_8IN32;
1320
1321 /* 128-bit buffers. */
1322 case V_028C70_COLOR_32_32_32_32:
1323 return V_028C70_ENDIAN_8IN32;
1324 default:
1325 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1326 }
1327 } else {
1328 return V_028C70_ENDIAN_NONE;
1329 }
1330 }
1331
1332 static uint32_t si_translate_dbformat(enum pipe_format format)
1333 {
1334 switch (format) {
1335 case PIPE_FORMAT_Z16_UNORM:
1336 return V_028040_Z_16;
1337 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1338 case PIPE_FORMAT_X8Z24_UNORM:
1339 case PIPE_FORMAT_Z24X8_UNORM:
1340 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1341 return V_028040_Z_24; /* deprecated on SI */
1342 case PIPE_FORMAT_Z32_FLOAT:
1343 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1344 return V_028040_Z_32_FLOAT;
1345 default:
1346 return V_028040_Z_INVALID;
1347 }
1348 }
1349
1350 /*
1351 * Texture translation
1352 */
1353
1354 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1355 enum pipe_format format,
1356 const struct util_format_description *desc,
1357 int first_non_void)
1358 {
1359 struct si_screen *sscreen = (struct si_screen*)screen;
1360 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1361 sscreen->b.info.drm_minor >= 31) ||
1362 sscreen->b.info.drm_major == 3;
1363 bool uniform = true;
1364 int i;
1365
1366 /* Colorspace (return non-RGB formats directly). */
1367 switch (desc->colorspace) {
1368 /* Depth stencil formats */
1369 case UTIL_FORMAT_COLORSPACE_ZS:
1370 switch (format) {
1371 case PIPE_FORMAT_Z16_UNORM:
1372 return V_008F14_IMG_DATA_FORMAT_16;
1373 case PIPE_FORMAT_X24S8_UINT:
1374 case PIPE_FORMAT_S8X24_UINT:
1375 /*
1376 * Implemented as an 8_8_8_8 data format to fix texture
1377 * gathers in stencil sampling. This affects at least
1378 * GL45-CTS.texture_cube_map_array.sampling on VI.
1379 */
1380 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1381 case PIPE_FORMAT_Z24X8_UNORM:
1382 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1383 return V_008F14_IMG_DATA_FORMAT_8_24;
1384 case PIPE_FORMAT_X8Z24_UNORM:
1385 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1386 return V_008F14_IMG_DATA_FORMAT_24_8;
1387 case PIPE_FORMAT_S8_UINT:
1388 return V_008F14_IMG_DATA_FORMAT_8;
1389 case PIPE_FORMAT_Z32_FLOAT:
1390 return V_008F14_IMG_DATA_FORMAT_32;
1391 case PIPE_FORMAT_X32_S8X24_UINT:
1392 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1393 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1394 default:
1395 goto out_unknown;
1396 }
1397
1398 case UTIL_FORMAT_COLORSPACE_YUV:
1399 goto out_unknown; /* TODO */
1400
1401 case UTIL_FORMAT_COLORSPACE_SRGB:
1402 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1403 goto out_unknown;
1404 break;
1405
1406 default:
1407 break;
1408 }
1409
1410 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1411 if (!enable_compressed_formats)
1412 goto out_unknown;
1413
1414 switch (format) {
1415 case PIPE_FORMAT_RGTC1_SNORM:
1416 case PIPE_FORMAT_LATC1_SNORM:
1417 case PIPE_FORMAT_RGTC1_UNORM:
1418 case PIPE_FORMAT_LATC1_UNORM:
1419 return V_008F14_IMG_DATA_FORMAT_BC4;
1420 case PIPE_FORMAT_RGTC2_SNORM:
1421 case PIPE_FORMAT_LATC2_SNORM:
1422 case PIPE_FORMAT_RGTC2_UNORM:
1423 case PIPE_FORMAT_LATC2_UNORM:
1424 return V_008F14_IMG_DATA_FORMAT_BC5;
1425 default:
1426 goto out_unknown;
1427 }
1428 }
1429
1430 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1431 (sscreen->b.family == CHIP_STONEY ||
1432 sscreen->b.chip_class >= GFX9)) {
1433 switch (format) {
1434 case PIPE_FORMAT_ETC1_RGB8:
1435 case PIPE_FORMAT_ETC2_RGB8:
1436 case PIPE_FORMAT_ETC2_SRGB8:
1437 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1438 case PIPE_FORMAT_ETC2_RGB8A1:
1439 case PIPE_FORMAT_ETC2_SRGB8A1:
1440 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1441 case PIPE_FORMAT_ETC2_RGBA8:
1442 case PIPE_FORMAT_ETC2_SRGBA8:
1443 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1444 case PIPE_FORMAT_ETC2_R11_UNORM:
1445 case PIPE_FORMAT_ETC2_R11_SNORM:
1446 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1447 case PIPE_FORMAT_ETC2_RG11_UNORM:
1448 case PIPE_FORMAT_ETC2_RG11_SNORM:
1449 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1450 default:
1451 goto out_unknown;
1452 }
1453 }
1454
1455 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1456 if (!enable_compressed_formats)
1457 goto out_unknown;
1458
1459 switch (format) {
1460 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1461 case PIPE_FORMAT_BPTC_SRGBA:
1462 return V_008F14_IMG_DATA_FORMAT_BC7;
1463 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1464 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1465 return V_008F14_IMG_DATA_FORMAT_BC6;
1466 default:
1467 goto out_unknown;
1468 }
1469 }
1470
1471 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1472 switch (format) {
1473 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1474 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1475 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1476 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1477 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1478 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1479 default:
1480 goto out_unknown;
1481 }
1482 }
1483
1484 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1485 if (!enable_compressed_formats)
1486 goto out_unknown;
1487
1488 if (!util_format_s3tc_enabled) {
1489 goto out_unknown;
1490 }
1491
1492 switch (format) {
1493 case PIPE_FORMAT_DXT1_RGB:
1494 case PIPE_FORMAT_DXT1_RGBA:
1495 case PIPE_FORMAT_DXT1_SRGB:
1496 case PIPE_FORMAT_DXT1_SRGBA:
1497 return V_008F14_IMG_DATA_FORMAT_BC1;
1498 case PIPE_FORMAT_DXT3_RGBA:
1499 case PIPE_FORMAT_DXT3_SRGBA:
1500 return V_008F14_IMG_DATA_FORMAT_BC2;
1501 case PIPE_FORMAT_DXT5_RGBA:
1502 case PIPE_FORMAT_DXT5_SRGBA:
1503 return V_008F14_IMG_DATA_FORMAT_BC3;
1504 default:
1505 goto out_unknown;
1506 }
1507 }
1508
1509 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1510 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1511 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1512 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1513 }
1514
1515 /* R8G8Bx_SNORM - TODO CxV8U8 */
1516
1517 /* hw cannot support mixed formats (except depth/stencil, since only
1518 * depth is read).*/
1519 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1520 goto out_unknown;
1521
1522 /* See whether the components are of the same size. */
1523 for (i = 1; i < desc->nr_channels; i++) {
1524 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1525 }
1526
1527 /* Non-uniform formats. */
1528 if (!uniform) {
1529 switch(desc->nr_channels) {
1530 case 3:
1531 if (desc->channel[0].size == 5 &&
1532 desc->channel[1].size == 6 &&
1533 desc->channel[2].size == 5) {
1534 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1535 }
1536 goto out_unknown;
1537 case 4:
1538 if (desc->channel[0].size == 5 &&
1539 desc->channel[1].size == 5 &&
1540 desc->channel[2].size == 5 &&
1541 desc->channel[3].size == 1) {
1542 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1543 }
1544 if (desc->channel[0].size == 10 &&
1545 desc->channel[1].size == 10 &&
1546 desc->channel[2].size == 10 &&
1547 desc->channel[3].size == 2) {
1548 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1549 }
1550 goto out_unknown;
1551 }
1552 goto out_unknown;
1553 }
1554
1555 if (first_non_void < 0 || first_non_void > 3)
1556 goto out_unknown;
1557
1558 /* uniform formats */
1559 switch (desc->channel[first_non_void].size) {
1560 case 4:
1561 switch (desc->nr_channels) {
1562 #if 0 /* Not supported for render targets */
1563 case 2:
1564 return V_008F14_IMG_DATA_FORMAT_4_4;
1565 #endif
1566 case 4:
1567 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1568 }
1569 break;
1570 case 8:
1571 switch (desc->nr_channels) {
1572 case 1:
1573 return V_008F14_IMG_DATA_FORMAT_8;
1574 case 2:
1575 return V_008F14_IMG_DATA_FORMAT_8_8;
1576 case 4:
1577 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1578 }
1579 break;
1580 case 16:
1581 switch (desc->nr_channels) {
1582 case 1:
1583 return V_008F14_IMG_DATA_FORMAT_16;
1584 case 2:
1585 return V_008F14_IMG_DATA_FORMAT_16_16;
1586 case 4:
1587 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1588 }
1589 break;
1590 case 32:
1591 switch (desc->nr_channels) {
1592 case 1:
1593 return V_008F14_IMG_DATA_FORMAT_32;
1594 case 2:
1595 return V_008F14_IMG_DATA_FORMAT_32_32;
1596 #if 0 /* Not supported for render targets */
1597 case 3:
1598 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1599 #endif
1600 case 4:
1601 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1602 }
1603 }
1604
1605 out_unknown:
1606 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1607 return ~0;
1608 }
1609
1610 static unsigned si_tex_wrap(unsigned wrap)
1611 {
1612 switch (wrap) {
1613 default:
1614 case PIPE_TEX_WRAP_REPEAT:
1615 return V_008F30_SQ_TEX_WRAP;
1616 case PIPE_TEX_WRAP_CLAMP:
1617 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1618 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1619 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1620 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1621 return V_008F30_SQ_TEX_CLAMP_BORDER;
1622 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1623 return V_008F30_SQ_TEX_MIRROR;
1624 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1625 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1626 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1627 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1628 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1629 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1630 }
1631 }
1632
1633 static unsigned si_tex_mipfilter(unsigned filter)
1634 {
1635 switch (filter) {
1636 case PIPE_TEX_MIPFILTER_NEAREST:
1637 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1638 case PIPE_TEX_MIPFILTER_LINEAR:
1639 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1640 default:
1641 case PIPE_TEX_MIPFILTER_NONE:
1642 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1643 }
1644 }
1645
1646 static unsigned si_tex_compare(unsigned compare)
1647 {
1648 switch (compare) {
1649 default:
1650 case PIPE_FUNC_NEVER:
1651 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1652 case PIPE_FUNC_LESS:
1653 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1654 case PIPE_FUNC_EQUAL:
1655 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1656 case PIPE_FUNC_LEQUAL:
1657 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1658 case PIPE_FUNC_GREATER:
1659 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1660 case PIPE_FUNC_NOTEQUAL:
1661 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1662 case PIPE_FUNC_GEQUAL:
1663 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1664 case PIPE_FUNC_ALWAYS:
1665 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1666 }
1667 }
1668
1669 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1670 unsigned view_target, unsigned nr_samples)
1671 {
1672 unsigned res_target = rtex->resource.b.b.target;
1673
1674 if (view_target == PIPE_TEXTURE_CUBE ||
1675 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1676 res_target = view_target;
1677 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1678 else if (res_target == PIPE_TEXTURE_CUBE ||
1679 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1680 res_target = PIPE_TEXTURE_2D_ARRAY;
1681
1682 /* GFX9 allocates 1D textures as 2D. */
1683 if ((res_target == PIPE_TEXTURE_1D ||
1684 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1685 sscreen->b.chip_class >= GFX9 &&
1686 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1687 if (res_target == PIPE_TEXTURE_1D)
1688 res_target = PIPE_TEXTURE_2D;
1689 else
1690 res_target = PIPE_TEXTURE_2D_ARRAY;
1691 }
1692
1693 switch (res_target) {
1694 default:
1695 case PIPE_TEXTURE_1D:
1696 return V_008F1C_SQ_RSRC_IMG_1D;
1697 case PIPE_TEXTURE_1D_ARRAY:
1698 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1699 case PIPE_TEXTURE_2D:
1700 case PIPE_TEXTURE_RECT:
1701 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1702 V_008F1C_SQ_RSRC_IMG_2D;
1703 case PIPE_TEXTURE_2D_ARRAY:
1704 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1705 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1706 case PIPE_TEXTURE_3D:
1707 return V_008F1C_SQ_RSRC_IMG_3D;
1708 case PIPE_TEXTURE_CUBE:
1709 case PIPE_TEXTURE_CUBE_ARRAY:
1710 return V_008F1C_SQ_RSRC_IMG_CUBE;
1711 }
1712 }
1713
1714 /*
1715 * Format support testing
1716 */
1717
1718 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1719 {
1720 return si_translate_texformat(screen, format, util_format_description(format),
1721 util_format_get_first_non_void_channel(format)) != ~0U;
1722 }
1723
1724 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1725 const struct util_format_description *desc,
1726 int first_non_void)
1727 {
1728 int i;
1729
1730 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1731 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1732
1733 assert(first_non_void >= 0);
1734
1735 if (desc->nr_channels == 4 &&
1736 desc->channel[0].size == 10 &&
1737 desc->channel[1].size == 10 &&
1738 desc->channel[2].size == 10 &&
1739 desc->channel[3].size == 2)
1740 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1741
1742 /* See whether the components are of the same size. */
1743 for (i = 0; i < desc->nr_channels; i++) {
1744 if (desc->channel[first_non_void].size != desc->channel[i].size)
1745 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1746 }
1747
1748 switch (desc->channel[first_non_void].size) {
1749 case 8:
1750 switch (desc->nr_channels) {
1751 case 1:
1752 case 3: /* 3 loads */
1753 return V_008F0C_BUF_DATA_FORMAT_8;
1754 case 2:
1755 return V_008F0C_BUF_DATA_FORMAT_8_8;
1756 case 4:
1757 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1758 }
1759 break;
1760 case 16:
1761 switch (desc->nr_channels) {
1762 case 1:
1763 case 3: /* 3 loads */
1764 return V_008F0C_BUF_DATA_FORMAT_16;
1765 case 2:
1766 return V_008F0C_BUF_DATA_FORMAT_16_16;
1767 case 4:
1768 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1769 }
1770 break;
1771 case 32:
1772 switch (desc->nr_channels) {
1773 case 1:
1774 return V_008F0C_BUF_DATA_FORMAT_32;
1775 case 2:
1776 return V_008F0C_BUF_DATA_FORMAT_32_32;
1777 case 3:
1778 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1779 case 4:
1780 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1781 }
1782 break;
1783 case 64:
1784 /* Legacy double formats. */
1785 switch (desc->nr_channels) {
1786 case 1: /* 1 load */
1787 return V_008F0C_BUF_DATA_FORMAT_32_32;
1788 case 2: /* 1 load */
1789 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1790 case 3: /* 3 loads */
1791 return V_008F0C_BUF_DATA_FORMAT_32_32;
1792 case 4: /* 2 loads */
1793 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1794 }
1795 break;
1796 }
1797
1798 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1799 }
1800
1801 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1802 const struct util_format_description *desc,
1803 int first_non_void)
1804 {
1805 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1806 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1807
1808 assert(first_non_void >= 0);
1809
1810 switch (desc->channel[first_non_void].type) {
1811 case UTIL_FORMAT_TYPE_SIGNED:
1812 case UTIL_FORMAT_TYPE_FIXED:
1813 if (desc->channel[first_non_void].size >= 32 ||
1814 desc->channel[first_non_void].pure_integer)
1815 return V_008F0C_BUF_NUM_FORMAT_SINT;
1816 else if (desc->channel[first_non_void].normalized)
1817 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1818 else
1819 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1820 break;
1821 case UTIL_FORMAT_TYPE_UNSIGNED:
1822 if (desc->channel[first_non_void].size >= 32 ||
1823 desc->channel[first_non_void].pure_integer)
1824 return V_008F0C_BUF_NUM_FORMAT_UINT;
1825 else if (desc->channel[first_non_void].normalized)
1826 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1827 else
1828 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1829 break;
1830 case UTIL_FORMAT_TYPE_FLOAT:
1831 default:
1832 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1833 }
1834 }
1835
1836 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1837 enum pipe_format format,
1838 unsigned usage)
1839 {
1840 const struct util_format_description *desc;
1841 int first_non_void;
1842 unsigned data_format;
1843
1844 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1845 PIPE_BIND_SAMPLER_VIEW |
1846 PIPE_BIND_VERTEX_BUFFER)) == 0);
1847
1848 desc = util_format_description(format);
1849
1850 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1851 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1852 * for read-only access (with caveats surrounding bounds checks), but
1853 * obviously fails for write access which we have to implement for
1854 * shader images. Luckily, OpenGL doesn't expect this to be supported
1855 * anyway, and so the only impact is on PBO uploads / downloads, which
1856 * shouldn't be expected to be fast for GL_RGB anyway.
1857 */
1858 if (desc->block.bits == 3 * 8 ||
1859 desc->block.bits == 3 * 16) {
1860 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1861 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1862 if (!usage)
1863 return 0;
1864 }
1865 }
1866
1867 first_non_void = util_format_get_first_non_void_channel(format);
1868 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1869 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1870 return 0;
1871
1872 return usage;
1873 }
1874
1875 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1876 {
1877 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1878 r600_translate_colorswap(format, false) != ~0U;
1879 }
1880
1881 static bool si_is_zs_format_supported(enum pipe_format format)
1882 {
1883 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1884 }
1885
1886 static boolean si_is_format_supported(struct pipe_screen *screen,
1887 enum pipe_format format,
1888 enum pipe_texture_target target,
1889 unsigned sample_count,
1890 unsigned usage)
1891 {
1892 unsigned retval = 0;
1893
1894 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1895 R600_ERR("r600: unsupported texture type %d\n", target);
1896 return false;
1897 }
1898
1899 if (!util_format_is_supported(format, usage))
1900 return false;
1901
1902 if (sample_count > 1) {
1903 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1904 return false;
1905
1906 if (usage & PIPE_BIND_SHADER_IMAGE)
1907 return false;
1908
1909 switch (sample_count) {
1910 case 2:
1911 case 4:
1912 case 8:
1913 break;
1914 case 16:
1915 if (format == PIPE_FORMAT_NONE)
1916 return true;
1917 else
1918 return false;
1919 default:
1920 return false;
1921 }
1922 }
1923
1924 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1925 PIPE_BIND_SHADER_IMAGE)) {
1926 if (target == PIPE_BUFFER) {
1927 retval |= si_is_vertex_format_supported(
1928 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1929 PIPE_BIND_SHADER_IMAGE));
1930 } else {
1931 if (si_is_sampler_format_supported(screen, format))
1932 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1933 PIPE_BIND_SHADER_IMAGE);
1934 }
1935 }
1936
1937 if ((usage & (PIPE_BIND_RENDER_TARGET |
1938 PIPE_BIND_DISPLAY_TARGET |
1939 PIPE_BIND_SCANOUT |
1940 PIPE_BIND_SHARED |
1941 PIPE_BIND_BLENDABLE)) &&
1942 si_is_colorbuffer_format_supported(format)) {
1943 retval |= usage &
1944 (PIPE_BIND_RENDER_TARGET |
1945 PIPE_BIND_DISPLAY_TARGET |
1946 PIPE_BIND_SCANOUT |
1947 PIPE_BIND_SHARED);
1948 if (!util_format_is_pure_integer(format) &&
1949 !util_format_is_depth_or_stencil(format))
1950 retval |= usage & PIPE_BIND_BLENDABLE;
1951 }
1952
1953 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1954 si_is_zs_format_supported(format)) {
1955 retval |= PIPE_BIND_DEPTH_STENCIL;
1956 }
1957
1958 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1959 retval |= si_is_vertex_format_supported(screen, format,
1960 PIPE_BIND_VERTEX_BUFFER);
1961 }
1962
1963 if ((usage & PIPE_BIND_LINEAR) &&
1964 !util_format_is_compressed(format) &&
1965 !(usage & PIPE_BIND_DEPTH_STENCIL))
1966 retval |= PIPE_BIND_LINEAR;
1967
1968 return retval == usage;
1969 }
1970
1971 /*
1972 * framebuffer handling
1973 */
1974
1975 static void si_choose_spi_color_formats(struct r600_surface *surf,
1976 unsigned format, unsigned swap,
1977 unsigned ntype, bool is_depth)
1978 {
1979 /* Alpha is needed for alpha-to-coverage.
1980 * Blending may be with or without alpha.
1981 */
1982 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1983 unsigned alpha = 0; /* exports alpha, but may not support blending */
1984 unsigned blend = 0; /* supports blending, but may not export alpha */
1985 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1986
1987 /* Choose the SPI color formats. These are required values for RB+.
1988 * Other chips have multiple choices, though they are not necessarily better.
1989 */
1990 switch (format) {
1991 case V_028C70_COLOR_5_6_5:
1992 case V_028C70_COLOR_1_5_5_5:
1993 case V_028C70_COLOR_5_5_5_1:
1994 case V_028C70_COLOR_4_4_4_4:
1995 case V_028C70_COLOR_10_11_11:
1996 case V_028C70_COLOR_11_11_10:
1997 case V_028C70_COLOR_8:
1998 case V_028C70_COLOR_8_8:
1999 case V_028C70_COLOR_8_8_8_8:
2000 case V_028C70_COLOR_10_10_10_2:
2001 case V_028C70_COLOR_2_10_10_10:
2002 if (ntype == V_028C70_NUMBER_UINT)
2003 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2004 else if (ntype == V_028C70_NUMBER_SINT)
2005 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2006 else
2007 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2008 break;
2009
2010 case V_028C70_COLOR_16:
2011 case V_028C70_COLOR_16_16:
2012 case V_028C70_COLOR_16_16_16_16:
2013 if (ntype == V_028C70_NUMBER_UNORM ||
2014 ntype == V_028C70_NUMBER_SNORM) {
2015 /* UNORM16 and SNORM16 don't support blending */
2016 if (ntype == V_028C70_NUMBER_UNORM)
2017 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2018 else
2019 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2020
2021 /* Use 32 bits per channel for blending. */
2022 if (format == V_028C70_COLOR_16) {
2023 if (swap == V_028C70_SWAP_STD) { /* R */
2024 blend = V_028714_SPI_SHADER_32_R;
2025 blend_alpha = V_028714_SPI_SHADER_32_AR;
2026 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2027 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2028 else
2029 assert(0);
2030 } else if (format == V_028C70_COLOR_16_16) {
2031 if (swap == V_028C70_SWAP_STD) { /* RG */
2032 blend = V_028714_SPI_SHADER_32_GR;
2033 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2034 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2035 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2036 else
2037 assert(0);
2038 } else /* 16_16_16_16 */
2039 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2040 } else if (ntype == V_028C70_NUMBER_UINT)
2041 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2042 else if (ntype == V_028C70_NUMBER_SINT)
2043 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2044 else if (ntype == V_028C70_NUMBER_FLOAT)
2045 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2046 else
2047 assert(0);
2048 break;
2049
2050 case V_028C70_COLOR_32:
2051 if (swap == V_028C70_SWAP_STD) { /* R */
2052 blend = normal = V_028714_SPI_SHADER_32_R;
2053 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2054 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2055 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2056 else
2057 assert(0);
2058 break;
2059
2060 case V_028C70_COLOR_32_32:
2061 if (swap == V_028C70_SWAP_STD) { /* RG */
2062 blend = normal = V_028714_SPI_SHADER_32_GR;
2063 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2064 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2065 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2066 else
2067 assert(0);
2068 break;
2069
2070 case V_028C70_COLOR_32_32_32_32:
2071 case V_028C70_COLOR_8_24:
2072 case V_028C70_COLOR_24_8:
2073 case V_028C70_COLOR_X24_8_32_FLOAT:
2074 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2075 break;
2076
2077 default:
2078 assert(0);
2079 return;
2080 }
2081
2082 /* The DB->CB copy needs 32_ABGR. */
2083 if (is_depth)
2084 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2085
2086 surf->spi_shader_col_format = normal;
2087 surf->spi_shader_col_format_alpha = alpha;
2088 surf->spi_shader_col_format_blend = blend;
2089 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2090 }
2091
2092 static void si_initialize_color_surface(struct si_context *sctx,
2093 struct r600_surface *surf)
2094 {
2095 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2096 unsigned color_info, color_attrib, color_view;
2097 unsigned format, swap, ntype, endian;
2098 const struct util_format_description *desc;
2099 int i;
2100 unsigned blend_clamp = 0, blend_bypass = 0;
2101
2102 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2103 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2104
2105 desc = util_format_description(surf->base.format);
2106 for (i = 0; i < 4; i++) {
2107 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2108 break;
2109 }
2110 }
2111 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2112 ntype = V_028C70_NUMBER_FLOAT;
2113 } else {
2114 ntype = V_028C70_NUMBER_UNORM;
2115 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2116 ntype = V_028C70_NUMBER_SRGB;
2117 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2118 if (desc->channel[i].pure_integer) {
2119 ntype = V_028C70_NUMBER_SINT;
2120 } else {
2121 assert(desc->channel[i].normalized);
2122 ntype = V_028C70_NUMBER_SNORM;
2123 }
2124 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2125 if (desc->channel[i].pure_integer) {
2126 ntype = V_028C70_NUMBER_UINT;
2127 } else {
2128 assert(desc->channel[i].normalized);
2129 ntype = V_028C70_NUMBER_UNORM;
2130 }
2131 }
2132 }
2133
2134 format = si_translate_colorformat(surf->base.format);
2135 if (format == V_028C70_COLOR_INVALID) {
2136 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2137 }
2138 assert(format != V_028C70_COLOR_INVALID);
2139 swap = r600_translate_colorswap(surf->base.format, false);
2140 endian = si_colorformat_endian_swap(format);
2141
2142 /* blend clamp should be set for all NORM/SRGB types */
2143 if (ntype == V_028C70_NUMBER_UNORM ||
2144 ntype == V_028C70_NUMBER_SNORM ||
2145 ntype == V_028C70_NUMBER_SRGB)
2146 blend_clamp = 1;
2147
2148 /* set blend bypass according to docs if SINT/UINT or
2149 8/24 COLOR variants */
2150 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2151 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2152 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2153 blend_clamp = 0;
2154 blend_bypass = 1;
2155 }
2156
2157 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2158 if (format == V_028C70_COLOR_8 ||
2159 format == V_028C70_COLOR_8_8 ||
2160 format == V_028C70_COLOR_8_8_8_8)
2161 surf->color_is_int8 = true;
2162 else if (format == V_028C70_COLOR_10_10_10_2 ||
2163 format == V_028C70_COLOR_2_10_10_10)
2164 surf->color_is_int10 = true;
2165 }
2166
2167 color_info = S_028C70_FORMAT(format) |
2168 S_028C70_COMP_SWAP(swap) |
2169 S_028C70_BLEND_CLAMP(blend_clamp) |
2170 S_028C70_BLEND_BYPASS(blend_bypass) |
2171 S_028C70_SIMPLE_FLOAT(1) |
2172 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2173 ntype != V_028C70_NUMBER_SNORM &&
2174 ntype != V_028C70_NUMBER_SRGB &&
2175 format != V_028C70_COLOR_8_24 &&
2176 format != V_028C70_COLOR_24_8) |
2177 S_028C70_NUMBER_TYPE(ntype) |
2178 S_028C70_ENDIAN(endian);
2179
2180 /* Intensity is implemented as Red, so treat it that way. */
2181 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2182 util_format_is_intensity(surf->base.format));
2183
2184 if (rtex->resource.b.b.nr_samples > 1) {
2185 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2186
2187 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2188 S_028C74_NUM_FRAGMENTS(log_samples);
2189
2190 if (rtex->fmask.size) {
2191 color_info |= S_028C70_COMPRESSION(1);
2192 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2193
2194 if (sctx->b.chip_class == SI) {
2195 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2196 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2197 }
2198 }
2199 }
2200
2201 surf->cb_color_view = color_view;
2202 surf->cb_color_info = color_info;
2203 surf->cb_color_attrib = color_attrib;
2204
2205 if (sctx->b.chip_class >= VI) {
2206 unsigned max_uncompressed_block_size = 2;
2207
2208 if (rtex->resource.b.b.nr_samples > 1) {
2209 if (rtex->surface.bpe == 1)
2210 max_uncompressed_block_size = 0;
2211 else if (rtex->surface.bpe == 2)
2212 max_uncompressed_block_size = 1;
2213 }
2214
2215 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2216 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2217 }
2218
2219 /* This must be set for fast clear to work without FMASK. */
2220 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2221 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2222 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2223 }
2224
2225 if (sctx->b.chip_class >= GFX9) {
2226 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2227
2228 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2229 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2230 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2231 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2232 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2233 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2234 }
2235
2236 /* Determine pixel shader export format */
2237 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2238
2239 surf->color_initialized = true;
2240 }
2241
2242 static void si_init_depth_surface(struct si_context *sctx,
2243 struct r600_surface *surf)
2244 {
2245 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2246 unsigned level = surf->base.u.tex.level;
2247 unsigned format, stencil_format;
2248 uint32_t z_info, s_info;
2249
2250 format = si_translate_dbformat(rtex->db_render_format);
2251 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2252 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2253
2254 assert(format != V_028040_Z_INVALID);
2255 if (format == V_028040_Z_INVALID)
2256 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2257
2258 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2259 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2260 surf->db_htile_data_base = 0;
2261 surf->db_htile_surface = 0;
2262
2263 if (sctx->b.chip_class >= GFX9) {
2264 assert(rtex->surface.u.gfx9.surf_offset == 0);
2265 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2266 surf->db_stencil_base = (rtex->resource.gpu_address +
2267 rtex->surface.u.gfx9.stencil_offset) >> 8;
2268 z_info = S_028038_FORMAT(format) |
2269 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2270 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2271 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2272 s_info = S_02803C_FORMAT(stencil_format) |
2273 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2274 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2275 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2276 surf->db_depth_view |= S_028008_MIPID(level);
2277 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2278 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2279
2280 /* Only use HTILE for the first level. */
2281 if (rtex->htile_buffer && !level) {
2282 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2283 S_028038_ALLOW_EXPCLEAR(1);
2284
2285 if (rtex->tc_compatible_htile) {
2286 unsigned max_zplanes = 4;
2287
2288 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2289 rtex->resource.b.b.nr_samples > 1)
2290 max_zplanes = 2;
2291
2292 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2293 S_028038_ITERATE_FLUSH(1);
2294 s_info |= S_02803C_ITERATE_FLUSH(1);
2295 }
2296
2297 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2298 /* Stencil buffer workaround ported from the SI-CI-VI code.
2299 * See that for explanation.
2300 */
2301 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2302 } else {
2303 /* Use all HTILE for depth if there's no stencil. */
2304 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2305 }
2306
2307 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2308 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2309 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2310 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2311 }
2312 } else {
2313 /* SI-CI-VI */
2314 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2315
2316 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2317
2318 surf->db_depth_base = (rtex->resource.gpu_address +
2319 rtex->surface.u.legacy.level[level].offset) >> 8;
2320 surf->db_stencil_base = (rtex->resource.gpu_address +
2321 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2322
2323 z_info = S_028040_FORMAT(format) |
2324 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2325 s_info = S_028044_FORMAT(stencil_format);
2326 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2327
2328 if (sctx->b.chip_class >= CIK) {
2329 struct radeon_info *info = &sctx->screen->b.info;
2330 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2331 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2332 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2333 unsigned tile_mode = info->si_tile_mode_array[index];
2334 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2335 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2336
2337 surf->db_depth_info |=
2338 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2339 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2340 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2341 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2342 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2343 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2344 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2345 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2346 } else {
2347 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2348 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2349 tile_mode_index = si_tile_mode_index(rtex, level, true);
2350 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2351 }
2352
2353 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2354 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2355 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2356 levelinfo->nblk_y) / 64 - 1);
2357
2358 /* Only use HTILE for the first level. */
2359 if (rtex->htile_buffer && !level) {
2360 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2361 S_028040_ALLOW_EXPCLEAR(1);
2362
2363 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2364 /* Workaround: For a not yet understood reason, the
2365 * combination of MSAA, fast stencil clear and stencil
2366 * decompress messes with subsequent stencil buffer
2367 * uses. Problem was reproduced on Verde, Bonaire,
2368 * Tonga, and Carrizo.
2369 *
2370 * Disabling EXPCLEAR works around the problem.
2371 *
2372 * Check piglit's arb_texture_multisample-stencil-clear
2373 * test if you want to try changing this.
2374 */
2375 if (rtex->resource.b.b.nr_samples <= 1)
2376 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2377 } else if (!rtex->tc_compatible_htile) {
2378 /* Use all of the htile_buffer for depth if there's no stencil.
2379 * This must not be set when TC-compatible HTILE is enabled
2380 * due to a hw bug.
2381 */
2382 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2383 }
2384
2385 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2386 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2387
2388 if (rtex->tc_compatible_htile) {
2389 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2390
2391 if (rtex->resource.b.b.nr_samples <= 1)
2392 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2393 else if (rtex->resource.b.b.nr_samples <= 4)
2394 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2395 else
2396 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2397 }
2398 }
2399 }
2400
2401 surf->db_z_info = z_info;
2402 surf->db_stencil_info = s_info;
2403
2404 surf->depth_initialized = true;
2405 }
2406
2407 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2408 {
2409 for (int i = 0; i < state->nr_cbufs; ++i) {
2410 struct r600_surface *surf = NULL;
2411 struct r600_texture *rtex;
2412
2413 if (!state->cbufs[i])
2414 continue;
2415 surf = (struct r600_surface*)state->cbufs[i];
2416 rtex = (struct r600_texture*)surf->base.texture;
2417
2418 p_atomic_dec(&rtex->framebuffers_bound);
2419 }
2420 }
2421
2422 static void si_set_framebuffer_state(struct pipe_context *ctx,
2423 const struct pipe_framebuffer_state *state)
2424 {
2425 struct si_context *sctx = (struct si_context *)ctx;
2426 struct pipe_constant_buffer constbuf = {0};
2427 struct r600_surface *surf = NULL;
2428 struct r600_texture *rtex;
2429 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2430 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2431 bool unbound = false;
2432 int i;
2433
2434 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2435 if (!sctx->framebuffer.state.cbufs[i])
2436 continue;
2437
2438 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2439 if (rtex->dcc_gather_statistics)
2440 vi_separate_dcc_stop_query(ctx, rtex);
2441 }
2442
2443 /* Disable DCC if the formats are incompatible. */
2444 for (i = 0; i < state->nr_cbufs; i++) {
2445 if (!state->cbufs[i])
2446 continue;
2447
2448 surf = (struct r600_surface*)state->cbufs[i];
2449 rtex = (struct r600_texture*)surf->base.texture;
2450
2451 if (!surf->dcc_incompatible)
2452 continue;
2453
2454 /* Since the DCC decompression calls back into set_framebuffer-
2455 * _state, we need to unbind the framebuffer, so that
2456 * vi_separate_dcc_stop_query isn't called twice with the same
2457 * color buffer.
2458 */
2459 if (!unbound) {
2460 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2461 unbound = true;
2462 }
2463
2464 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2465 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2466 sctx->b.decompress_dcc(ctx, rtex);
2467
2468 surf->dcc_incompatible = false;
2469 }
2470
2471 /* Only flush TC when changing the framebuffer state, because
2472 * the only client not using TC that can change textures is
2473 * the framebuffer.
2474 *
2475 * Flush all CB and DB caches here because all buffers can be used
2476 * for write by both TC (with shader image stores) and CB/DB.
2477 */
2478 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2479 SI_CONTEXT_INV_GLOBAL_L2 |
2480 SI_CONTEXT_FLUSH_AND_INV_CB |
2481 SI_CONTEXT_FLUSH_AND_INV_DB |
2482 SI_CONTEXT_CS_PARTIAL_FLUSH;
2483
2484 /* Take the maximum of the old and new count. If the new count is lower,
2485 * dirtying is needed to disable the unbound colorbuffers.
2486 */
2487 sctx->framebuffer.dirty_cbufs |=
2488 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2489 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2490
2491 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2492 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2493
2494 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2495 sctx->framebuffer.spi_shader_col_format = 0;
2496 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2497 sctx->framebuffer.spi_shader_col_format_blend = 0;
2498 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2499 sctx->framebuffer.color_is_int8 = 0;
2500 sctx->framebuffer.color_is_int10 = 0;
2501
2502 sctx->framebuffer.compressed_cb_mask = 0;
2503 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2504 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2505 sctx->framebuffer.any_dst_linear = false;
2506
2507 for (i = 0; i < state->nr_cbufs; i++) {
2508 if (!state->cbufs[i])
2509 continue;
2510
2511 surf = (struct r600_surface*)state->cbufs[i];
2512 rtex = (struct r600_texture*)surf->base.texture;
2513
2514 if (!surf->color_initialized) {
2515 si_initialize_color_surface(sctx, surf);
2516 }
2517
2518 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2519 sctx->framebuffer.spi_shader_col_format |=
2520 surf->spi_shader_col_format << (i * 4);
2521 sctx->framebuffer.spi_shader_col_format_alpha |=
2522 surf->spi_shader_col_format_alpha << (i * 4);
2523 sctx->framebuffer.spi_shader_col_format_blend |=
2524 surf->spi_shader_col_format_blend << (i * 4);
2525 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2526 surf->spi_shader_col_format_blend_alpha << (i * 4);
2527
2528 if (surf->color_is_int8)
2529 sctx->framebuffer.color_is_int8 |= 1 << i;
2530 if (surf->color_is_int10)
2531 sctx->framebuffer.color_is_int10 |= 1 << i;
2532
2533 if (rtex->fmask.size) {
2534 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2535 }
2536
2537 if (rtex->surface.is_linear)
2538 sctx->framebuffer.any_dst_linear = true;
2539
2540 r600_context_add_resource_size(ctx, surf->base.texture);
2541
2542 p_atomic_inc(&rtex->framebuffers_bound);
2543
2544 if (rtex->dcc_gather_statistics) {
2545 /* Dirty tracking must be enabled for DCC usage analysis. */
2546 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2547 vi_separate_dcc_start_query(ctx, rtex);
2548 }
2549 }
2550
2551 if (state->zsbuf) {
2552 surf = (struct r600_surface*)state->zsbuf;
2553 rtex = (struct r600_texture*)surf->base.texture;
2554
2555 if (!surf->depth_initialized) {
2556 si_init_depth_surface(sctx, surf);
2557 }
2558 r600_context_add_resource_size(ctx, surf->base.texture);
2559 }
2560
2561 si_update_poly_offset_state(sctx);
2562 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2563 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2564
2565 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2566 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2567
2568 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2569 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2570 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2571
2572 /* Set sample locations as fragment shader constants. */
2573 switch (sctx->framebuffer.nr_samples) {
2574 case 1:
2575 constbuf.user_buffer = sctx->b.sample_locations_1x;
2576 break;
2577 case 2:
2578 constbuf.user_buffer = sctx->b.sample_locations_2x;
2579 break;
2580 case 4:
2581 constbuf.user_buffer = sctx->b.sample_locations_4x;
2582 break;
2583 case 8:
2584 constbuf.user_buffer = sctx->b.sample_locations_8x;
2585 break;
2586 case 16:
2587 constbuf.user_buffer = sctx->b.sample_locations_16x;
2588 break;
2589 default:
2590 R600_ERR("Requested an invalid number of samples %i.\n",
2591 sctx->framebuffer.nr_samples);
2592 assert(0);
2593 }
2594 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2595 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2596
2597 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2598 }
2599
2600 sctx->do_update_shaders = true;
2601
2602 if (!sctx->decompression_enabled) {
2603 /* Prevent textures decompression when the framebuffer state
2604 * changes come from the decompression passes themselves.
2605 */
2606 sctx->need_check_render_feedback = true;
2607 sctx->framebuffer.do_update_surf_dirtiness = true;
2608 }
2609 }
2610
2611 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2612 {
2613 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2614 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2615 unsigned i, nr_cbufs = state->nr_cbufs;
2616 struct r600_texture *tex = NULL;
2617 struct r600_surface *cb = NULL;
2618 unsigned cb_color_info = 0;
2619
2620 /* Colorbuffers. */
2621 for (i = 0; i < nr_cbufs; i++) {
2622 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2623 unsigned cb_color_attrib;
2624
2625 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2626 continue;
2627
2628 cb = (struct r600_surface*)state->cbufs[i];
2629 if (!cb) {
2630 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2631 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2632 continue;
2633 }
2634
2635 tex = (struct r600_texture *)cb->base.texture;
2636 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2637 &tex->resource, RADEON_USAGE_READWRITE,
2638 tex->resource.b.b.nr_samples > 1 ?
2639 RADEON_PRIO_COLOR_BUFFER_MSAA :
2640 RADEON_PRIO_COLOR_BUFFER);
2641
2642 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2643 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2644 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2645 RADEON_PRIO_CMASK);
2646 }
2647
2648 if (tex->dcc_separate_buffer)
2649 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2650 tex->dcc_separate_buffer,
2651 RADEON_USAGE_READWRITE,
2652 RADEON_PRIO_DCC);
2653
2654 /* Compute mutable surface parameters. */
2655 cb_color_base = tex->resource.gpu_address >> 8;
2656 cb_color_fmask = cb_color_base;
2657 cb_dcc_base = 0;
2658 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2659 cb_color_attrib = cb->cb_color_attrib;
2660
2661 if (tex->fmask.size)
2662 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2663
2664 /* Set up DCC. */
2665 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2666 bool is_msaa_resolve_dst = state->cbufs[0] &&
2667 state->cbufs[0]->texture->nr_samples > 1 &&
2668 state->cbufs[1] == &cb->base &&
2669 state->cbufs[1]->texture->nr_samples <= 1;
2670
2671 if (!is_msaa_resolve_dst)
2672 cb_color_info |= S_028C70_DCC_ENABLE(1);
2673
2674 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2675 tex->dcc_offset) >> 8;
2676 }
2677
2678 if (sctx->b.chip_class >= GFX9) {
2679 struct gfx9_surf_meta_flags meta;
2680
2681 if (tex->dcc_offset)
2682 meta = tex->surface.u.gfx9.dcc;
2683 else
2684 meta = tex->surface.u.gfx9.cmask;
2685
2686 /* Set mutable surface parameters. */
2687 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2688 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2689 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2690 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2691 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2692
2693 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2694 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2695 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2696 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2697 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2698 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2699 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2700 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2701 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2702 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2703 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2704 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2705 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2706 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2707 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2708 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2709
2710 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2711 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2712 } else {
2713 /* Compute mutable surface parameters (SI-CI-VI). */
2714 const struct legacy_surf_level *level_info =
2715 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2716 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2717 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2718
2719 cb_color_base += level_info->offset >> 8;
2720 if (cb_dcc_base)
2721 cb_dcc_base += level_info->dcc_offset >> 8;
2722
2723 pitch_tile_max = level_info->nblk_x / 8 - 1;
2724 slice_tile_max = level_info->nblk_x *
2725 level_info->nblk_y / 64 - 1;
2726 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2727
2728 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2729 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2730 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2731
2732 if (tex->fmask.size) {
2733 if (sctx->b.chip_class >= CIK)
2734 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2735 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2736 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2737 } else {
2738 /* This must be set for fast clear to work without FMASK. */
2739 if (sctx->b.chip_class >= CIK)
2740 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2741 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2742 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2743 }
2744
2745 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2746 sctx->b.chip_class >= VI ? 14 : 13);
2747 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2748 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2749 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2750 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2751 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2752 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2753 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2754 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2755 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2756 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2757 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2758 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2759 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2760
2761 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2762 radeon_emit(cs, cb_dcc_base);
2763 }
2764 }
2765 for (; i < 8 ; i++)
2766 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2767 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2768
2769 /* ZS buffer. */
2770 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2771 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2772 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2773
2774 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2775 &rtex->resource, RADEON_USAGE_READWRITE,
2776 zb->base.texture->nr_samples > 1 ?
2777 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2778 RADEON_PRIO_DEPTH_BUFFER);
2779
2780 if (zb->db_htile_data_base) {
2781 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2782 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2783 RADEON_PRIO_HTILE);
2784 }
2785
2786 if (sctx->b.chip_class >= GFX9) {
2787 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2788 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2789 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2790 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2791
2792 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2793 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2794 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2795 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2796 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2797 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2798 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2799 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2800 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2801 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2802 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2803 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2804
2805 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2806 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2807 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2808 } else {
2809 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2810
2811 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2812 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2813 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2814 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2815 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2816 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2817 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2818 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2819 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2820 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2821 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2822 }
2823
2824 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2825 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2826 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2827
2828 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2829 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2830 } else if (sctx->framebuffer.dirty_zsbuf) {
2831 if (sctx->b.chip_class >= GFX9)
2832 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2833 else
2834 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2835
2836 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2837 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2838 }
2839
2840 /* Framebuffer dimensions. */
2841 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2842 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2843 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2844
2845 if (sctx->b.chip_class >= GFX9) {
2846 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2847 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2848 }
2849
2850 sctx->framebuffer.dirty_cbufs = 0;
2851 sctx->framebuffer.dirty_zsbuf = false;
2852 }
2853
2854 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2855 struct r600_atom *atom)
2856 {
2857 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2858 unsigned nr_samples = sctx->framebuffer.nr_samples;
2859 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2860
2861 /* Smoothing (only possible with nr_samples == 1) uses the same
2862 * sample locations as the MSAA it simulates.
2863 */
2864 if (nr_samples <= 1 && sctx->smoothing_enabled)
2865 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2866
2867 /* On Polaris, the small primitive filter uses the sample locations
2868 * even when MSAA is off, so we need to make sure they're set to 0.
2869 */
2870 if (has_msaa_sample_loc_bug)
2871 nr_samples = MAX2(nr_samples, 1);
2872
2873 if (nr_samples >= 1 &&
2874 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2875 sctx->msaa_sample_locs.nr_samples = nr_samples;
2876 cayman_emit_msaa_sample_locs(cs, nr_samples);
2877 }
2878
2879 if (sctx->b.family >= CHIP_POLARIS10) {
2880 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2881 unsigned small_prim_filter_cntl =
2882 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2883 /* line bug */
2884 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2885
2886 /* The alternative of setting sample locations to 0 would
2887 * require a DB flush to avoid Z errors, see
2888 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2889 */
2890 if (has_msaa_sample_loc_bug &&
2891 sctx->framebuffer.nr_samples > 1 &&
2892 rs && !rs->multisample_enable)
2893 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2894
2895 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2896 small_prim_filter_cntl);
2897 }
2898 }
2899
2900 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2901 {
2902 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2903 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2904 /* 33% faster rendering to linear color buffers */
2905 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2906 unsigned sc_mode_cntl_1 =
2907 S_028A4C_WALK_SIZE(dst_is_linear) |
2908 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2909 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2910 /* always 1: */
2911 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2912 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2913 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2914 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2915 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2916 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2917
2918 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2919 sctx->ps_iter_samples,
2920 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2921 sc_mode_cntl_1);
2922
2923 /* GFX9: Flush DFSM when the AA mode changes. */
2924 if (sctx->b.chip_class >= GFX9) {
2925 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2926 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2927 }
2928 }
2929
2930 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2931 {
2932 struct si_context *sctx = (struct si_context *)ctx;
2933
2934 if (sctx->ps_iter_samples == min_samples)
2935 return;
2936
2937 sctx->ps_iter_samples = min_samples;
2938 sctx->do_update_shaders = true;
2939
2940 if (sctx->framebuffer.nr_samples > 1)
2941 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2942 }
2943
2944 /*
2945 * Samplers
2946 */
2947
2948 /**
2949 * Build the sampler view descriptor for a buffer texture.
2950 * @param state 256-bit descriptor; only the high 128 bits are filled in
2951 */
2952 void
2953 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2954 enum pipe_format format,
2955 unsigned offset, unsigned size,
2956 uint32_t *state)
2957 {
2958 const struct util_format_description *desc;
2959 int first_non_void;
2960 unsigned stride;
2961 unsigned num_records;
2962 unsigned num_format, data_format;
2963
2964 desc = util_format_description(format);
2965 first_non_void = util_format_get_first_non_void_channel(format);
2966 stride = desc->block.bits / 8;
2967 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2968 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2969
2970 num_records = size / stride;
2971 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2972
2973 /* The NUM_RECORDS field has a different meaning depending on the chip,
2974 * instruction type, STRIDE, and SWIZZLE_ENABLE.
2975 *
2976 * SI-CIK:
2977 * - If STRIDE == 0, it's in byte units.
2978 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
2979 *
2980 * VI:
2981 * - For SMEM and STRIDE == 0, it's in byte units.
2982 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
2983 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
2984 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
2985 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
2986 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
2987 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
2988 * That way the same descriptor can be used by both SMEM and VMEM.
2989 *
2990 * GFX9:
2991 * - For SMEM and STRIDE == 0, it's in byte units.
2992 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
2993 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
2994 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
2995 */
2996 if (screen->b.chip_class >= GFX9)
2997 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
2998 * from STRIDE to bytes. This works around it by setting
2999 * NUM_RECORDS to at least the size of one element, so that
3000 * the first element is readable when IDXEN == 0.
3001 *
3002 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3003 * IDXEN is enforced?
3004 */
3005 num_records = num_records ? MAX2(num_records, stride) : 0;
3006 else if (screen->b.chip_class == VI)
3007 num_records *= stride;
3008
3009 state[4] = 0;
3010 state[5] = S_008F04_STRIDE(stride);
3011 state[6] = num_records;
3012 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3013 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3014 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3015 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3016 S_008F0C_NUM_FORMAT(num_format) |
3017 S_008F0C_DATA_FORMAT(data_format);
3018 }
3019
3020 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3021 {
3022 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3023
3024 if (swizzle[3] == PIPE_SWIZZLE_X) {
3025 /* For the pre-defined border color values (white, opaque
3026 * black, transparent black), the only thing that matters is
3027 * that the alpha channel winds up in the correct place
3028 * (because the RGB channels are all the same) so either of
3029 * these enumerations will work.
3030 */
3031 if (swizzle[2] == PIPE_SWIZZLE_Y)
3032 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3033 else
3034 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3035 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3036 if (swizzle[1] == PIPE_SWIZZLE_Y)
3037 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3038 else
3039 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3040 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3041 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3042 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3043 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3044 }
3045
3046 return bc_swizzle;
3047 }
3048
3049 /**
3050 * Build the sampler view descriptor for a texture.
3051 */
3052 void
3053 si_make_texture_descriptor(struct si_screen *screen,
3054 struct r600_texture *tex,
3055 bool sampler,
3056 enum pipe_texture_target target,
3057 enum pipe_format pipe_format,
3058 const unsigned char state_swizzle[4],
3059 unsigned first_level, unsigned last_level,
3060 unsigned first_layer, unsigned last_layer,
3061 unsigned width, unsigned height, unsigned depth,
3062 uint32_t *state,
3063 uint32_t *fmask_state)
3064 {
3065 struct pipe_resource *res = &tex->resource.b.b;
3066 const struct util_format_description *base_desc, *desc;
3067 unsigned char swizzle[4];
3068 int first_non_void;
3069 unsigned num_format, data_format, type;
3070 uint64_t va;
3071
3072 desc = util_format_description(pipe_format);
3073 base_desc = util_format_description(res->format);
3074
3075 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3076 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3077 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3078 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3079
3080 switch (pipe_format) {
3081 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3082 case PIPE_FORMAT_X32_S8X24_UINT:
3083 case PIPE_FORMAT_X8Z24_UNORM:
3084 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3085 break;
3086 case PIPE_FORMAT_X24S8_UINT:
3087 /*
3088 * X24S8 is implemented as an 8_8_8_8 data format, to
3089 * fix texture gathers. This affects at least
3090 * GL45-CTS.texture_cube_map_array.sampling on VI.
3091 */
3092 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3093 break;
3094 default:
3095 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3096 }
3097 } else {
3098 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3099 }
3100
3101 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3102
3103 switch (pipe_format) {
3104 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3105 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3106 break;
3107 default:
3108 if (first_non_void < 0) {
3109 if (util_format_is_compressed(pipe_format)) {
3110 switch (pipe_format) {
3111 case PIPE_FORMAT_DXT1_SRGB:
3112 case PIPE_FORMAT_DXT1_SRGBA:
3113 case PIPE_FORMAT_DXT3_SRGBA:
3114 case PIPE_FORMAT_DXT5_SRGBA:
3115 case PIPE_FORMAT_BPTC_SRGBA:
3116 case PIPE_FORMAT_ETC2_SRGB8:
3117 case PIPE_FORMAT_ETC2_SRGB8A1:
3118 case PIPE_FORMAT_ETC2_SRGBA8:
3119 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3120 break;
3121 case PIPE_FORMAT_RGTC1_SNORM:
3122 case PIPE_FORMAT_LATC1_SNORM:
3123 case PIPE_FORMAT_RGTC2_SNORM:
3124 case PIPE_FORMAT_LATC2_SNORM:
3125 case PIPE_FORMAT_ETC2_R11_SNORM:
3126 case PIPE_FORMAT_ETC2_RG11_SNORM:
3127 /* implies float, so use SNORM/UNORM to determine
3128 whether data is signed or not */
3129 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3130 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3131 break;
3132 default:
3133 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3134 break;
3135 }
3136 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3137 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3138 } else {
3139 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3140 }
3141 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3142 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3143 } else {
3144 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3145
3146 switch (desc->channel[first_non_void].type) {
3147 case UTIL_FORMAT_TYPE_FLOAT:
3148 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3149 break;
3150 case UTIL_FORMAT_TYPE_SIGNED:
3151 if (desc->channel[first_non_void].normalized)
3152 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3153 else if (desc->channel[first_non_void].pure_integer)
3154 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3155 else
3156 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3157 break;
3158 case UTIL_FORMAT_TYPE_UNSIGNED:
3159 if (desc->channel[first_non_void].normalized)
3160 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3161 else if (desc->channel[first_non_void].pure_integer)
3162 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3163 else
3164 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3165 }
3166 }
3167 }
3168
3169 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3170 if (data_format == ~0) {
3171 data_format = 0;
3172 }
3173
3174 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3175 if (screen->b.chip_class >= GFX9 &&
3176 util_format_has_depth(desc) &&
3177 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3178 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3179 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3180 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3181 }
3182
3183 if (!sampler &&
3184 (res->target == PIPE_TEXTURE_CUBE ||
3185 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3186 (screen->b.chip_class <= VI &&
3187 res->target == PIPE_TEXTURE_3D))) {
3188 /* For the purpose of shader images, treat cube maps and 3D
3189 * textures as 2D arrays. For 3D textures, the address
3190 * calculations for mipmaps are different, so we rely on the
3191 * caller to effectively disable mipmaps.
3192 */
3193 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3194
3195 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3196 } else {
3197 type = si_tex_dim(screen, tex, target, res->nr_samples);
3198 }
3199
3200 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3201 height = 1;
3202 depth = res->array_size;
3203 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3204 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3205 if (sampler || res->target != PIPE_TEXTURE_3D)
3206 depth = res->array_size;
3207 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3208 depth = res->array_size / 6;
3209
3210 state[0] = 0;
3211 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3212 S_008F14_NUM_FORMAT_GFX6(num_format));
3213 state[2] = (S_008F18_WIDTH(width - 1) |
3214 S_008F18_HEIGHT(height - 1) |
3215 S_008F18_PERF_MOD(4));
3216 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3217 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3218 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3219 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3220 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3221 0 : first_level) |
3222 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3223 util_logbase2(res->nr_samples) :
3224 last_level) |
3225 S_008F1C_TYPE(type));
3226 state[4] = 0;
3227 state[5] = S_008F24_BASE_ARRAY(first_layer);
3228 state[6] = 0;
3229 state[7] = 0;
3230
3231 if (screen->b.chip_class >= GFX9) {
3232 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3233
3234 /* Depth is the the last accessible layer on Gfx9.
3235 * The hw doesn't need to know the total number of layers.
3236 */
3237 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3238 state[4] |= S_008F20_DEPTH(depth - 1);
3239 else
3240 state[4] |= S_008F20_DEPTH(last_layer);
3241
3242 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3243 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3244 util_logbase2(res->nr_samples) :
3245 tex->resource.b.b.last_level);
3246 } else {
3247 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3248 state[4] |= S_008F20_DEPTH(depth - 1);
3249 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3250 }
3251
3252 if (tex->dcc_offset) {
3253 unsigned swap = r600_translate_colorswap(pipe_format, false);
3254
3255 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3256 } else {
3257 /* The last dword is unused by hw. The shader uses it to clear
3258 * bits in the first dword of sampler state.
3259 */
3260 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3261 if (first_level == last_level)
3262 state[7] = C_008F30_MAX_ANISO_RATIO;
3263 else
3264 state[7] = 0xffffffff;
3265 }
3266 }
3267
3268 /* Initialize the sampler view for FMASK. */
3269 if (tex->fmask.size) {
3270 uint32_t data_format, num_format;
3271
3272 va = tex->resource.gpu_address + tex->fmask.offset;
3273
3274 if (screen->b.chip_class >= GFX9) {
3275 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3276 switch (res->nr_samples) {
3277 case 2:
3278 num_format = V_008F14_IMG_FMASK_8_2_2;
3279 break;
3280 case 4:
3281 num_format = V_008F14_IMG_FMASK_8_4_4;
3282 break;
3283 case 8:
3284 num_format = V_008F14_IMG_FMASK_32_8_8;
3285 break;
3286 default:
3287 unreachable("invalid nr_samples");
3288 }
3289 } else {
3290 switch (res->nr_samples) {
3291 case 2:
3292 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3293 break;
3294 case 4:
3295 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3296 break;
3297 case 8:
3298 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3299 break;
3300 default:
3301 unreachable("invalid nr_samples");
3302 }
3303 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3304 }
3305
3306 fmask_state[0] = va >> 8;
3307 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3308 S_008F14_DATA_FORMAT_GFX6(data_format) |
3309 S_008F14_NUM_FORMAT_GFX6(num_format);
3310 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3311 S_008F18_HEIGHT(height - 1);
3312 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3313 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3314 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3315 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3316 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3317 fmask_state[4] = 0;
3318 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3319 fmask_state[6] = 0;
3320 fmask_state[7] = 0;
3321
3322 if (screen->b.chip_class >= GFX9) {
3323 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3324 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3325 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3326 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3327 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3328 } else {
3329 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3330 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3331 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3332 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3333 }
3334 }
3335 }
3336
3337 /**
3338 * Create a sampler view.
3339 *
3340 * @param ctx context
3341 * @param texture texture
3342 * @param state sampler view template
3343 * @param width0 width0 override (for compressed textures as int)
3344 * @param height0 height0 override (for compressed textures as int)
3345 * @param force_level set the base address to the level (for compressed textures)
3346 */
3347 struct pipe_sampler_view *
3348 si_create_sampler_view_custom(struct pipe_context *ctx,
3349 struct pipe_resource *texture,
3350 const struct pipe_sampler_view *state,
3351 unsigned width0, unsigned height0,
3352 unsigned force_level)
3353 {
3354 struct si_context *sctx = (struct si_context*)ctx;
3355 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3356 struct r600_texture *tmp = (struct r600_texture*)texture;
3357 unsigned base_level, first_level, last_level;
3358 unsigned char state_swizzle[4];
3359 unsigned height, depth, width;
3360 unsigned last_layer = state->u.tex.last_layer;
3361 enum pipe_format pipe_format;
3362 const struct legacy_surf_level *surflevel;
3363
3364 if (!view)
3365 return NULL;
3366
3367 /* initialize base object */
3368 view->base = *state;
3369 view->base.texture = NULL;
3370 view->base.reference.count = 1;
3371 view->base.context = ctx;
3372
3373 assert(texture);
3374 pipe_resource_reference(&view->base.texture, texture);
3375
3376 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3377 state->format == PIPE_FORMAT_S8X24_UINT ||
3378 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3379 state->format == PIPE_FORMAT_S8_UINT)
3380 view->is_stencil_sampler = true;
3381
3382 /* Buffer resource. */
3383 if (texture->target == PIPE_BUFFER) {
3384 si_make_buffer_descriptor(sctx->screen,
3385 (struct r600_resource *)texture,
3386 state->format,
3387 state->u.buf.offset,
3388 state->u.buf.size,
3389 view->state);
3390 return &view->base;
3391 }
3392
3393 state_swizzle[0] = state->swizzle_r;
3394 state_swizzle[1] = state->swizzle_g;
3395 state_swizzle[2] = state->swizzle_b;
3396 state_swizzle[3] = state->swizzle_a;
3397
3398 base_level = 0;
3399 first_level = state->u.tex.first_level;
3400 last_level = state->u.tex.last_level;
3401 width = width0;
3402 height = height0;
3403 depth = texture->depth0;
3404
3405 if (sctx->b.chip_class <= VI && force_level) {
3406 assert(force_level == first_level &&
3407 force_level == last_level);
3408 base_level = force_level;
3409 first_level = 0;
3410 last_level = 0;
3411 width = u_minify(width, force_level);
3412 height = u_minify(height, force_level);
3413 depth = u_minify(depth, force_level);
3414 }
3415
3416 /* This is not needed if state trackers set last_layer correctly. */
3417 if (state->target == PIPE_TEXTURE_1D ||
3418 state->target == PIPE_TEXTURE_2D ||
3419 state->target == PIPE_TEXTURE_RECT ||
3420 state->target == PIPE_TEXTURE_CUBE)
3421 last_layer = state->u.tex.first_layer;
3422
3423 /* Texturing with separate depth and stencil. */
3424 pipe_format = state->format;
3425
3426 /* Depth/stencil texturing sometimes needs separate texture. */
3427 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3428 if (!tmp->flushed_depth_texture &&
3429 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3430 pipe_resource_reference(&view->base.texture, NULL);
3431 FREE(view);
3432 return NULL;
3433 }
3434
3435 assert(tmp->flushed_depth_texture);
3436
3437 /* Override format for the case where the flushed texture
3438 * contains only Z or only S.
3439 */
3440 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3441 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3442
3443 tmp = tmp->flushed_depth_texture;
3444 }
3445
3446 surflevel = tmp->surface.u.legacy.level;
3447
3448 if (tmp->db_compatible) {
3449 if (!view->is_stencil_sampler)
3450 pipe_format = tmp->db_render_format;
3451
3452 switch (pipe_format) {
3453 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3454 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3455 break;
3456 case PIPE_FORMAT_X8Z24_UNORM:
3457 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3458 /* Z24 is always stored like this for DB
3459 * compatibility.
3460 */
3461 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3462 break;
3463 case PIPE_FORMAT_X24S8_UINT:
3464 case PIPE_FORMAT_S8X24_UINT:
3465 case PIPE_FORMAT_X32_S8X24_UINT:
3466 pipe_format = PIPE_FORMAT_S8_UINT;
3467 surflevel = tmp->surface.u.legacy.stencil_level;
3468 break;
3469 default:;
3470 }
3471 }
3472
3473 view->dcc_incompatible =
3474 vi_dcc_formats_are_incompatible(texture,
3475 state->u.tex.first_level,
3476 state->format);
3477
3478 si_make_texture_descriptor(sctx->screen, tmp, true,
3479 state->target, pipe_format, state_swizzle,
3480 first_level, last_level,
3481 state->u.tex.first_layer, last_layer,
3482 width, height, depth,
3483 view->state, view->fmask_state);
3484
3485 view->base_level_info = &surflevel[base_level];
3486 view->base_level = base_level;
3487 view->block_width = util_format_get_blockwidth(pipe_format);
3488 return &view->base;
3489 }
3490
3491 static struct pipe_sampler_view *
3492 si_create_sampler_view(struct pipe_context *ctx,
3493 struct pipe_resource *texture,
3494 const struct pipe_sampler_view *state)
3495 {
3496 return si_create_sampler_view_custom(ctx, texture, state,
3497 texture ? texture->width0 : 0,
3498 texture ? texture->height0 : 0, 0);
3499 }
3500
3501 static void si_sampler_view_destroy(struct pipe_context *ctx,
3502 struct pipe_sampler_view *state)
3503 {
3504 struct si_sampler_view *view = (struct si_sampler_view *)state;
3505
3506 pipe_resource_reference(&state->texture, NULL);
3507 FREE(view);
3508 }
3509
3510 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3511 {
3512 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3513 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3514 (linear_filter &&
3515 (wrap == PIPE_TEX_WRAP_CLAMP ||
3516 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3517 }
3518
3519 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3520 {
3521 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3522 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3523
3524 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3525 state->border_color.ui[2] || state->border_color.ui[3]) &&
3526 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3527 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3528 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3529 }
3530
3531 static void *si_create_sampler_state(struct pipe_context *ctx,
3532 const struct pipe_sampler_state *state)
3533 {
3534 struct si_context *sctx = (struct si_context *)ctx;
3535 struct r600_common_screen *rscreen = sctx->b.screen;
3536 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3537 unsigned border_color_type, border_color_index = 0;
3538 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3539 : state->max_anisotropy;
3540 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3541
3542 if (!rstate) {
3543 return NULL;
3544 }
3545
3546 if (!sampler_state_needs_border_color(state))
3547 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3548 else if (state->border_color.f[0] == 0 &&
3549 state->border_color.f[1] == 0 &&
3550 state->border_color.f[2] == 0 &&
3551 state->border_color.f[3] == 0)
3552 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3553 else if (state->border_color.f[0] == 0 &&
3554 state->border_color.f[1] == 0 &&
3555 state->border_color.f[2] == 0 &&
3556 state->border_color.f[3] == 1)
3557 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3558 else if (state->border_color.f[0] == 1 &&
3559 state->border_color.f[1] == 1 &&
3560 state->border_color.f[2] == 1 &&
3561 state->border_color.f[3] == 1)
3562 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3563 else {
3564 int i;
3565
3566 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3567
3568 /* Check if the border has been uploaded already. */
3569 for (i = 0; i < sctx->border_color_count; i++)
3570 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3571 sizeof(state->border_color)) == 0)
3572 break;
3573
3574 if (i >= SI_MAX_BORDER_COLORS) {
3575 /* Getting 4096 unique border colors is very unlikely. */
3576 fprintf(stderr, "radeonsi: The border color table is full. "
3577 "Any new border colors will be just black. "
3578 "Please file a bug.\n");
3579 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3580 } else {
3581 if (i == sctx->border_color_count) {
3582 /* Upload a new border color. */
3583 memcpy(&sctx->border_color_table[i], &state->border_color,
3584 sizeof(state->border_color));
3585 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3586 &state->border_color,
3587 sizeof(state->border_color));
3588 sctx->border_color_count++;
3589 }
3590
3591 border_color_index = i;
3592 }
3593 }
3594
3595 #ifdef DEBUG
3596 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3597 #endif
3598 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3599 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3600 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3601 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3602 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3603 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3604 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3605 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3606 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3607 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3608 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3609 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3610 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3611 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3612 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3613 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3614 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3615 S_008F38_MIP_POINT_PRECLAMP(1) |
3616 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3617 S_008F38_FILTER_PREC_FIX(1) |
3618 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3619 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3620 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3621 return rstate;
3622 }
3623
3624 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3625 {
3626 struct si_context *sctx = (struct si_context *)ctx;
3627
3628 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3629 return;
3630
3631 sctx->sample_mask.sample_mask = sample_mask;
3632 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3633 }
3634
3635 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3636 {
3637 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3638 unsigned mask = sctx->sample_mask.sample_mask;
3639
3640 /* Needed for line and polygon smoothing as well as for the Polaris
3641 * small primitive filter. We expect the state tracker to take care of
3642 * this for us.
3643 */
3644 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3645 (mask & 1 && sctx->blitter->running));
3646
3647 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3648 radeon_emit(cs, mask | (mask << 16));
3649 radeon_emit(cs, mask | (mask << 16));
3650 }
3651
3652 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3653 {
3654 #ifdef DEBUG
3655 struct si_sampler_state *s = state;
3656
3657 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3658 s->magic = 0;
3659 #endif
3660 free(state);
3661 }
3662
3663 /*
3664 * Vertex elements & buffers
3665 */
3666
3667 static void *si_create_vertex_elements(struct pipe_context *ctx,
3668 unsigned count,
3669 const struct pipe_vertex_element *elements)
3670 {
3671 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3672 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3673 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3674 int i;
3675
3676 assert(count <= SI_MAX_ATTRIBS);
3677 if (!v)
3678 return NULL;
3679
3680 v->count = count;
3681 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3682
3683 for (i = 0; i < count; ++i) {
3684 const struct util_format_description *desc;
3685 const struct util_format_channel_description *channel;
3686 unsigned data_format, num_format;
3687 int first_non_void;
3688 unsigned vbo_index = elements[i].vertex_buffer_index;
3689 unsigned char swizzle[4];
3690
3691 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3692 FREE(v);
3693 return NULL;
3694 }
3695
3696 if (!used[vbo_index]) {
3697 v->first_vb_use_mask |= 1 << i;
3698 used[vbo_index] = true;
3699 }
3700
3701 desc = util_format_description(elements[i].src_format);
3702 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3703 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3704 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3705 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3706 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3707
3708 v->format_size[i] = desc->block.bits / 8;
3709
3710 /* The hardware always treats the 2-bit alpha channel as
3711 * unsigned, so a shader workaround is needed. The affected
3712 * chips are VI and older except Stoney (GFX8.1).
3713 */
3714 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3715 sscreen->b.chip_class <= VI &&
3716 sscreen->b.family != CHIP_STONEY) {
3717 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3718 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3719 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3720 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3721 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3722 /* This isn't actually used in OpenGL. */
3723 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3724 }
3725 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3726 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3727 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3728 else
3729 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3730 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3731 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3732 if (channel->normalized) {
3733 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3734 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3735 else
3736 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3737 } else {
3738 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3739 }
3740 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3741 if (channel->normalized) {
3742 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3743 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3744 else
3745 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3746 } else {
3747 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3748 }
3749 }
3750 } else if (channel && channel->size == 64 &&
3751 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3752 switch (desc->nr_channels) {
3753 case 1:
3754 case 2:
3755 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3756 swizzle[0] = PIPE_SWIZZLE_X;
3757 swizzle[1] = PIPE_SWIZZLE_Y;
3758 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3759 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3760 break;
3761 case 3:
3762 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3763 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3764 swizzle[1] = PIPE_SWIZZLE_Y;
3765 swizzle[2] = PIPE_SWIZZLE_0;
3766 swizzle[3] = PIPE_SWIZZLE_0;
3767 break;
3768 case 4:
3769 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3770 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3771 swizzle[1] = PIPE_SWIZZLE_Y;
3772 swizzle[2] = PIPE_SWIZZLE_Z;
3773 swizzle[3] = PIPE_SWIZZLE_W;
3774 break;
3775 default:
3776 assert(0);
3777 }
3778 } else if (channel && desc->nr_channels == 3) {
3779 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3780
3781 if (channel->size == 8) {
3782 if (channel->pure_integer)
3783 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3784 else
3785 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3786 } else if (channel->size == 16) {
3787 if (channel->pure_integer)
3788 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3789 else
3790 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3791 }
3792 }
3793
3794 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3795 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3796 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3797 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3798 S_008F0C_NUM_FORMAT(num_format) |
3799 S_008F0C_DATA_FORMAT(data_format);
3800 }
3801 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3802
3803 return v;
3804 }
3805
3806 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3807 {
3808 struct si_context *sctx = (struct si_context *)ctx;
3809 struct si_vertex_element *v = (struct si_vertex_element*)state;
3810
3811 sctx->vertex_elements = v;
3812 sctx->vertex_buffers_dirty = true;
3813 sctx->do_update_shaders = true;
3814 }
3815
3816 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3817 {
3818 struct si_context *sctx = (struct si_context *)ctx;
3819
3820 if (sctx->vertex_elements == state)
3821 sctx->vertex_elements = NULL;
3822 FREE(state);
3823 }
3824
3825 static void si_set_vertex_buffers(struct pipe_context *ctx,
3826 unsigned start_slot, unsigned count,
3827 const struct pipe_vertex_buffer *buffers)
3828 {
3829 struct si_context *sctx = (struct si_context *)ctx;
3830 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3831 int i;
3832
3833 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3834
3835 if (buffers) {
3836 for (i = 0; i < count; i++) {
3837 const struct pipe_vertex_buffer *src = buffers + i;
3838 struct pipe_vertex_buffer *dsti = dst + i;
3839 struct pipe_resource *buf = src->buffer.resource;
3840
3841 pipe_resource_reference(&dsti->buffer.resource, buf);
3842 dsti->buffer_offset = src->buffer_offset;
3843 dsti->stride = src->stride;
3844 r600_context_add_resource_size(ctx, buf);
3845 if (buf)
3846 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3847 }
3848 } else {
3849 for (i = 0; i < count; i++) {
3850 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3851 }
3852 }
3853 sctx->vertex_buffers_dirty = true;
3854 }
3855
3856 /*
3857 * Misc
3858 */
3859
3860 static void si_set_tess_state(struct pipe_context *ctx,
3861 const float default_outer_level[4],
3862 const float default_inner_level[2])
3863 {
3864 struct si_context *sctx = (struct si_context *)ctx;
3865 struct pipe_constant_buffer cb;
3866 float array[8];
3867
3868 memcpy(array, default_outer_level, sizeof(float) * 4);
3869 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3870
3871 cb.buffer = NULL;
3872 cb.user_buffer = NULL;
3873 cb.buffer_size = sizeof(array);
3874
3875 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3876 (void*)array, sizeof(array),
3877 &cb.buffer_offset);
3878
3879 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3880 pipe_resource_reference(&cb.buffer, NULL);
3881 }
3882
3883 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3884 {
3885 struct si_context *sctx = (struct si_context *)ctx;
3886
3887 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3888 SI_CONTEXT_INV_GLOBAL_L2 |
3889 SI_CONTEXT_FLUSH_AND_INV_CB;
3890 sctx->framebuffer.do_update_surf_dirtiness = true;
3891 }
3892
3893 /* This only ensures coherency for shader image/buffer stores. */
3894 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3895 {
3896 struct si_context *sctx = (struct si_context *)ctx;
3897
3898 /* Subsequent commands must wait for all shader invocations to
3899 * complete. */
3900 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3901 SI_CONTEXT_CS_PARTIAL_FLUSH;
3902
3903 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3904 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3905 SI_CONTEXT_INV_VMEM_L1;
3906
3907 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3908 PIPE_BARRIER_SHADER_BUFFER |
3909 PIPE_BARRIER_TEXTURE |
3910 PIPE_BARRIER_IMAGE |
3911 PIPE_BARRIER_STREAMOUT_BUFFER |
3912 PIPE_BARRIER_GLOBAL_BUFFER)) {
3913 /* As far as I can tell, L1 contents are written back to L2
3914 * automatically at end of shader, but the contents of other
3915 * L1 caches might still be stale. */
3916 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3917 }
3918
3919 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3920 /* Indices are read through TC L2 since VI.
3921 * L1 isn't used.
3922 */
3923 if (sctx->screen->b.chip_class <= CIK)
3924 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3925 }
3926
3927 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3928 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3929 SI_CONTEXT_FLUSH_AND_INV_DB;
3930
3931 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3932 PIPE_BARRIER_INDIRECT_BUFFER))
3933 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3934 }
3935
3936 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3937 {
3938 struct pipe_blend_state blend;
3939
3940 memset(&blend, 0, sizeof(blend));
3941 blend.independent_blend_enable = true;
3942 blend.rt[0].colormask = 0xf;
3943 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3944 }
3945
3946 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3947 bool include_draw_vbo)
3948 {
3949 si_need_cs_space((struct si_context*)ctx);
3950 }
3951
3952 static void si_init_config(struct si_context *sctx);
3953
3954 void si_init_state_functions(struct si_context *sctx)
3955 {
3956 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3957 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3958 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3959 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3960 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3961
3962 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3963 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3964 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3965 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3966 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3967 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3968 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3969 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3970 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3971 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3972
3973 sctx->b.b.create_blend_state = si_create_blend_state;
3974 sctx->b.b.bind_blend_state = si_bind_blend_state;
3975 sctx->b.b.delete_blend_state = si_delete_blend_state;
3976 sctx->b.b.set_blend_color = si_set_blend_color;
3977
3978 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3979 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3980 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3981
3982 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3983 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3984 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3985
3986 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3987 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3988 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3989 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3990 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3991
3992 sctx->b.b.set_clip_state = si_set_clip_state;
3993 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3994
3995 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3996 sctx->b.b.get_sample_position = cayman_get_sample_position;
3997
3998 sctx->b.b.create_sampler_state = si_create_sampler_state;
3999 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4000
4001 sctx->b.b.create_sampler_view = si_create_sampler_view;
4002 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4003
4004 sctx->b.b.set_sample_mask = si_set_sample_mask;
4005
4006 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4007 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4008 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4009 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4010
4011 sctx->b.b.texture_barrier = si_texture_barrier;
4012 sctx->b.b.memory_barrier = si_memory_barrier;
4013 sctx->b.b.set_min_samples = si_set_min_samples;
4014 sctx->b.b.set_tess_state = si_set_tess_state;
4015
4016 sctx->b.b.set_active_query_state = si_set_active_query_state;
4017 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4018 sctx->b.save_qbo_state = si_save_qbo_state;
4019 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4020
4021 sctx->b.b.draw_vbo = si_draw_vbo;
4022
4023 si_init_config(sctx);
4024 }
4025
4026 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4027 {
4028 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4029 }
4030
4031 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4032 struct r600_texture *rtex,
4033 struct radeon_bo_metadata *md)
4034 {
4035 struct si_screen *sscreen = (struct si_screen*)rscreen;
4036 struct pipe_resource *res = &rtex->resource.b.b;
4037 static const unsigned char swizzle[] = {
4038 PIPE_SWIZZLE_X,
4039 PIPE_SWIZZLE_Y,
4040 PIPE_SWIZZLE_Z,
4041 PIPE_SWIZZLE_W
4042 };
4043 uint32_t desc[8], i;
4044 bool is_array = util_resource_is_array_texture(res);
4045
4046 /* DRM 2.x.x doesn't support this. */
4047 if (rscreen->info.drm_major != 3)
4048 return;
4049
4050 assert(rtex->dcc_separate_buffer == NULL);
4051 assert(rtex->fmask.size == 0);
4052
4053 /* Metadata image format format version 1:
4054 * [0] = 1 (metadata format identifier)
4055 * [1] = (VENDOR_ID << 16) | PCI_ID
4056 * [2:9] = image descriptor for the whole resource
4057 * [2] is always 0, because the base address is cleared
4058 * [9] is the DCC offset bits [39:8] from the beginning of
4059 * the buffer
4060 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4061 */
4062
4063 md->metadata[0] = 1; /* metadata image format version 1 */
4064
4065 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4066 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4067
4068 si_make_texture_descriptor(sscreen, rtex, true,
4069 res->target, res->format,
4070 swizzle, 0, res->last_level, 0,
4071 is_array ? res->array_size - 1 : 0,
4072 res->width0, res->height0, res->depth0,
4073 desc, NULL);
4074
4075 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4076 0, 0, rtex->surface.blk_w, false, desc);
4077
4078 /* Clear the base address and set the relative DCC offset. */
4079 desc[0] = 0;
4080 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4081 desc[7] = rtex->dcc_offset >> 8;
4082
4083 /* Dwords [2:9] contain the image descriptor. */
4084 memcpy(&md->metadata[2], desc, sizeof(desc));
4085 md->size_metadata = 10 * 4;
4086
4087 /* Dwords [10:..] contain the mipmap level offsets. */
4088 if (rscreen->chip_class <= VI) {
4089 for (i = 0; i <= res->last_level; i++)
4090 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4091
4092 md->size_metadata += (1 + res->last_level) * 4;
4093 }
4094 }
4095
4096 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4097 struct r600_texture *rtex,
4098 struct radeon_bo_metadata *md)
4099 {
4100 uint32_t *desc = &md->metadata[2];
4101
4102 if (rscreen->chip_class < VI)
4103 return;
4104
4105 /* Return if DCC is enabled. The texture should be set up with it
4106 * already.
4107 */
4108 if (md->size_metadata >= 11 * 4 &&
4109 md->metadata[0] != 0 &&
4110 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4111 G_008F28_COMPRESSION_EN(desc[6])) {
4112 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4113 return;
4114 }
4115
4116 /* Disable DCC. These are always set by texture_from_handle and must
4117 * be cleared here.
4118 */
4119 rtex->dcc_offset = 0;
4120 }
4121
4122 void si_init_screen_state_functions(struct si_screen *sscreen)
4123 {
4124 sscreen->b.b.is_format_supported = si_is_format_supported;
4125 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4126 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4127 }
4128
4129 static void
4130 si_write_harvested_raster_configs(struct si_context *sctx,
4131 struct si_pm4_state *pm4,
4132 unsigned raster_config,
4133 unsigned raster_config_1)
4134 {
4135 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4136 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4137 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4138 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4139 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4140 unsigned rb_per_se = num_rb / num_se;
4141 unsigned se_mask[4];
4142 unsigned se;
4143
4144 se_mask[0] = ((1 << rb_per_se) - 1);
4145 se_mask[1] = (se_mask[0] << rb_per_se);
4146 se_mask[2] = (se_mask[1] << rb_per_se);
4147 se_mask[3] = (se_mask[2] << rb_per_se);
4148
4149 se_mask[0] &= rb_mask;
4150 se_mask[1] &= rb_mask;
4151 se_mask[2] &= rb_mask;
4152 se_mask[3] &= rb_mask;
4153
4154 assert(num_se == 1 || num_se == 2 || num_se == 4);
4155 assert(sh_per_se == 1 || sh_per_se == 2);
4156 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4157
4158 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4159 * fields are for, so I'm leaving them as their default
4160 * values. */
4161
4162 for (se = 0; se < num_se; se++) {
4163 unsigned raster_config_se = raster_config;
4164 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4165 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4166 int idx = (se / 2) * 2;
4167
4168 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4169 raster_config_se &= C_028350_SE_MAP;
4170
4171 if (!se_mask[idx]) {
4172 raster_config_se |=
4173 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4174 } else {
4175 raster_config_se |=
4176 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4177 }
4178 }
4179
4180 pkr0_mask &= rb_mask;
4181 pkr1_mask &= rb_mask;
4182 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4183 raster_config_se &= C_028350_PKR_MAP;
4184
4185 if (!pkr0_mask) {
4186 raster_config_se |=
4187 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4188 } else {
4189 raster_config_se |=
4190 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4191 }
4192 }
4193
4194 if (rb_per_se >= 2) {
4195 unsigned rb0_mask = 1 << (se * rb_per_se);
4196 unsigned rb1_mask = rb0_mask << 1;
4197
4198 rb0_mask &= rb_mask;
4199 rb1_mask &= rb_mask;
4200 if (!rb0_mask || !rb1_mask) {
4201 raster_config_se &= C_028350_RB_MAP_PKR0;
4202
4203 if (!rb0_mask) {
4204 raster_config_se |=
4205 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4206 } else {
4207 raster_config_se |=
4208 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4209 }
4210 }
4211
4212 if (rb_per_se > 2) {
4213 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4214 rb1_mask = rb0_mask << 1;
4215 rb0_mask &= rb_mask;
4216 rb1_mask &= rb_mask;
4217 if (!rb0_mask || !rb1_mask) {
4218 raster_config_se &= C_028350_RB_MAP_PKR1;
4219
4220 if (!rb0_mask) {
4221 raster_config_se |=
4222 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4223 } else {
4224 raster_config_se |=
4225 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4226 }
4227 }
4228 }
4229 }
4230
4231 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4232 if (sctx->b.chip_class < CIK)
4233 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4234 SE_INDEX(se) | SH_BROADCAST_WRITES |
4235 INSTANCE_BROADCAST_WRITES);
4236 else
4237 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4238 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4239 S_030800_INSTANCE_BROADCAST_WRITES(1));
4240 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4241 }
4242
4243 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4244 if (sctx->b.chip_class < CIK)
4245 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4246 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4247 INSTANCE_BROADCAST_WRITES);
4248 else {
4249 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4250 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4251 S_030800_INSTANCE_BROADCAST_WRITES(1));
4252
4253 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4254 (!se_mask[2] && !se_mask[3]))) {
4255 raster_config_1 &= C_028354_SE_PAIR_MAP;
4256
4257 if (!se_mask[0] && !se_mask[1]) {
4258 raster_config_1 |=
4259 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4260 } else {
4261 raster_config_1 |=
4262 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4263 }
4264 }
4265
4266 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4267 }
4268 }
4269
4270 static void si_init_config(struct si_context *sctx)
4271 {
4272 struct si_screen *sscreen = sctx->screen;
4273 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4274 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4275 unsigned raster_config, raster_config_1;
4276 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4277 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4278
4279 if (!pm4)
4280 return;
4281
4282 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4283 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4284 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4285 si_pm4_cmd_end(pm4, false);
4286
4287 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4288 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4289
4290 /* FIXME calculate these values somehow ??? */
4291 if (sctx->b.chip_class <= VI) {
4292 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4293 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4294 }
4295 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4296
4297 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4298 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4299
4300 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4301 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4302 if (sctx->b.chip_class >= GFX9)
4303 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4304 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4305 if (sctx->b.chip_class < CIK)
4306 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4307 S_008A14_CLIP_VTX_REORDER_ENA(1));
4308
4309 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4310 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4311
4312 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4313
4314 switch (sctx->screen->b.family) {
4315 case CHIP_TAHITI:
4316 case CHIP_PITCAIRN:
4317 raster_config = 0x2a00126a;
4318 raster_config_1 = 0x00000000;
4319 break;
4320 case CHIP_VERDE:
4321 raster_config = 0x0000124a;
4322 raster_config_1 = 0x00000000;
4323 break;
4324 case CHIP_OLAND:
4325 raster_config = 0x00000082;
4326 raster_config_1 = 0x00000000;
4327 break;
4328 case CHIP_HAINAN:
4329 raster_config = 0x00000000;
4330 raster_config_1 = 0x00000000;
4331 break;
4332 case CHIP_BONAIRE:
4333 raster_config = 0x16000012;
4334 raster_config_1 = 0x00000000;
4335 break;
4336 case CHIP_HAWAII:
4337 raster_config = 0x3a00161a;
4338 raster_config_1 = 0x0000002e;
4339 break;
4340 case CHIP_FIJI:
4341 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4342 /* old kernels with old tiling config */
4343 raster_config = 0x16000012;
4344 raster_config_1 = 0x0000002a;
4345 } else {
4346 raster_config = 0x3a00161a;
4347 raster_config_1 = 0x0000002e;
4348 }
4349 break;
4350 case CHIP_POLARIS10:
4351 raster_config = 0x16000012;
4352 raster_config_1 = 0x0000002a;
4353 break;
4354 case CHIP_POLARIS11:
4355 case CHIP_POLARIS12:
4356 raster_config = 0x16000012;
4357 raster_config_1 = 0x00000000;
4358 break;
4359 case CHIP_TONGA:
4360 raster_config = 0x16000012;
4361 raster_config_1 = 0x0000002a;
4362 break;
4363 case CHIP_ICELAND:
4364 if (num_rb == 1)
4365 raster_config = 0x00000000;
4366 else
4367 raster_config = 0x00000002;
4368 raster_config_1 = 0x00000000;
4369 break;
4370 case CHIP_CARRIZO:
4371 raster_config = 0x00000002;
4372 raster_config_1 = 0x00000000;
4373 break;
4374 case CHIP_KAVERI:
4375 /* KV should be 0x00000002, but that causes problems with radeon */
4376 raster_config = 0x00000000; /* 0x00000002 */
4377 raster_config_1 = 0x00000000;
4378 break;
4379 case CHIP_KABINI:
4380 case CHIP_MULLINS:
4381 case CHIP_STONEY:
4382 raster_config = 0x00000000;
4383 raster_config_1 = 0x00000000;
4384 break;
4385 default:
4386 if (sctx->b.chip_class <= VI) {
4387 fprintf(stderr,
4388 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4389 raster_config = 0x00000000;
4390 raster_config_1 = 0x00000000;
4391 }
4392 break;
4393 }
4394
4395 if (sctx->b.chip_class <= VI) {
4396 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4397 /* Always use the default config when all backends are enabled
4398 * (or when we failed to determine the enabled backends).
4399 */
4400 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4401 raster_config);
4402 if (sctx->b.chip_class >= CIK)
4403 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4404 raster_config_1);
4405 } else {
4406 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4407 }
4408 }
4409
4410 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4411 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4412 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4413 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4414 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4415 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4416 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4417
4418 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4419 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4420 S_028230_ER_TRI(0xA) |
4421 S_028230_ER_POINT(0xA) |
4422 S_028230_ER_RECT(0xA) |
4423 /* Required by DX10_DIAMOND_TEST_ENA: */
4424 S_028230_ER_LINE_LR(0x1A) |
4425 S_028230_ER_LINE_RL(0x26) |
4426 S_028230_ER_LINE_TB(0xA) |
4427 S_028230_ER_LINE_BT(0xA));
4428 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4429 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4430 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4431 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4432 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4433 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4434 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4435
4436 if (sctx->b.chip_class >= GFX9) {
4437 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4438 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4439 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4440 } else {
4441 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4442 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4443 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4444 }
4445
4446 if (sctx->b.chip_class >= CIK) {
4447 if (sctx->b.chip_class >= GFX9) {
4448 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4449 } else {
4450 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4451 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4452 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4453
4454 /* If this is 0, Bonaire can hang even if GS isn't being used.
4455 * Other chips are unaffected. These are suboptimal values,
4456 * but we don't use on-chip GS.
4457 */
4458 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4459 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4460 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4461 }
4462 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4463
4464 if (sscreen->b.info.num_good_compute_units /
4465 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4466 /* Too few available compute units per SH. Disallowing
4467 * VS to run on CU0 could hurt us more than late VS
4468 * allocation would help.
4469 *
4470 * LATE_ALLOC_VS = 2 is the highest safe number.
4471 */
4472 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4473 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4474 } else {
4475 /* Set LATE_ALLOC_VS == 31. It should be less than
4476 * the number of scratch waves. Limitations:
4477 * - VS can't execute on CU0.
4478 * - If HS writes outputs to LDS, LS can't execute on CU0.
4479 */
4480 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4481 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4482 }
4483
4484 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4485 }
4486
4487 if (sctx->b.chip_class >= VI) {
4488 unsigned vgt_tess_distribution;
4489
4490 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4491 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4492 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4493 if (sctx->b.family < CHIP_POLARIS10)
4494 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4495 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4496
4497 vgt_tess_distribution =
4498 S_028B50_ACCUM_ISOLINE(32) |
4499 S_028B50_ACCUM_TRI(11) |
4500 S_028B50_ACCUM_QUAD(11) |
4501 S_028B50_DONUT_SPLIT(16);
4502
4503 /* Testing with Unigine Heaven extreme tesselation yielded best results
4504 * with TRAP_SPLIT = 3.
4505 */
4506 if (sctx->b.family == CHIP_FIJI ||
4507 sctx->b.family >= CHIP_POLARIS10)
4508 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4509
4510 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4511 } else {
4512 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4513 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4514 }
4515
4516 if (sctx->screen->b.has_rbplus)
4517 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4518
4519 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4520 if (sctx->b.chip_class >= CIK)
4521 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4522 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4523 RADEON_PRIO_BORDER_COLORS);
4524
4525 if (sctx->b.chip_class >= GFX9) {
4526 unsigned num_se = sscreen->b.info.max_se;
4527 unsigned pc_lines = 0;
4528
4529 switch (sctx->b.family) {
4530 case CHIP_VEGA10:
4531 pc_lines = 4096;
4532 break;
4533 case CHIP_RAVEN:
4534 pc_lines = 1024;
4535 break;
4536 default:
4537 assert(0);
4538 }
4539
4540 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4541 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4542 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4543 /* TODO: We can use this to disable RBs for rendering to GART: */
4544 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4545 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4546 /* TODO: Enable the binner: */
4547 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4548 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4549 S_028C44_DISABLE_START_OF_PRIM(1));
4550 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4551 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4552 S_028C48_MAX_PRIM_PER_BATCH(1023));
4553 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4554 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4555 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4556 }
4557
4558 si_pm4_upload_indirect_buffer(sctx, pm4);
4559 sctx->init_config = pm4;
4560 }