2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
28 #include "si_shader.h"
30 #include "radeon/r600_cs.h"
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
39 /* Initialize an external atom (owned by ../radeon). */
41 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
42 struct r600_atom
**list_elem
)
44 atom
->id
= list_elem
- sctx
->atoms
.array
+ 1;
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
50 struct r600_atom
**list_elem
,
51 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
53 atom
->emit
= (void*)emit_func
;
54 atom
->id
= list_elem
- sctx
->atoms
.array
+ 1; /* index+1 in the atom array */
58 unsigned si_array_mode(unsigned mode
)
61 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
62 return V_009910_ARRAY_LINEAR_ALIGNED
;
63 case RADEON_SURF_MODE_1D
:
64 return V_009910_ARRAY_1D_TILED_THIN1
;
65 case RADEON_SURF_MODE_2D
:
66 return V_009910_ARRAY_2D_TILED_THIN1
;
68 case RADEON_SURF_MODE_LINEAR
:
69 return V_009910_ARRAY_LINEAR_GENERAL
;
73 uint32_t si_num_banks(struct si_screen
*sscreen
, struct r600_texture
*tex
)
75 if (sscreen
->b
.chip_class
>= CIK
&&
76 sscreen
->b
.info
.cik_macrotile_mode_array_valid
) {
77 unsigned index
, tileb
;
79 tileb
= 8 * 8 * tex
->surface
.bpe
;
80 tileb
= MIN2(tex
->surface
.tile_split
, tileb
);
82 for (index
= 0; tileb
> 64; index
++) {
87 return (sscreen
->b
.info
.cik_macrotile_mode_array
[index
] >> 6) & 0x3;
90 if (sscreen
->b
.chip_class
== SI
&&
91 sscreen
->b
.info
.si_tile_mode_array_valid
) {
92 /* Don't use stencil_tiling_index, because num_banks is always
93 * read from the depth mode. */
94 unsigned tile_mode_index
= tex
->surface
.tiling_index
[0];
95 assert(tile_mode_index
< 32);
97 return G_009910_NUM_BANKS(sscreen
->b
.info
.si_tile_mode_array
[tile_mode_index
]);
101 switch (sscreen
->b
.info
.r600_num_banks
) {
103 return V_02803C_ADDR_SURF_2_BANK
;
105 return V_02803C_ADDR_SURF_4_BANK
;
108 return V_02803C_ADDR_SURF_8_BANK
;
110 return V_02803C_ADDR_SURF_16_BANK
;
114 unsigned cik_tile_split(unsigned tile_split
)
116 switch (tile_split
) {
118 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_64B
;
121 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_128B
;
124 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_256B
;
127 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_512B
;
131 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_1KB
;
134 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_2KB
;
137 tile_split
= V_028040_ADDR_SURF_TILE_SPLIT_4KB
;
143 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect
)
145 switch (macro_tile_aspect
) {
148 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_1
;
151 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_2
;
154 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_4
;
157 macro_tile_aspect
= V_02803C_ADDR_SURF_MACRO_ASPECT_8
;
160 return macro_tile_aspect
;
163 unsigned cik_bank_wh(unsigned bankwh
)
168 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_1
;
171 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_2
;
174 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_4
;
177 bankwh
= V_02803C_ADDR_SURF_BANK_WIDTH_8
;
183 unsigned cik_db_pipe_config(struct si_screen
*sscreen
, unsigned tile_mode
)
185 if (sscreen
->b
.info
.si_tile_mode_array_valid
) {
186 uint32_t gb_tile_mode
= sscreen
->b
.info
.si_tile_mode_array
[tile_mode
];
188 return G_009910_PIPE_CONFIG(gb_tile_mode
);
191 /* This is probably broken for a lot of chips, but it's only used
192 * if the kernel cannot return the tile mode array for CIK. */
193 switch (sscreen
->b
.info
.num_tile_pipes
) {
195 return V_02803C_X_ADDR_SURF_P16_32X32_16X16
;
197 return V_02803C_X_ADDR_SURF_P8_32X32_16X16
;
200 if (sscreen
->b
.info
.num_render_backends
== 4)
201 return V_02803C_X_ADDR_SURF_P4_16X16
;
203 return V_02803C_X_ADDR_SURF_P4_8X16
;
205 return V_02803C_ADDR_SURF_P2
;
209 static unsigned si_map_swizzle(unsigned swizzle
)
212 case UTIL_FORMAT_SWIZZLE_Y
:
213 return V_008F0C_SQ_SEL_Y
;
214 case UTIL_FORMAT_SWIZZLE_Z
:
215 return V_008F0C_SQ_SEL_Z
;
216 case UTIL_FORMAT_SWIZZLE_W
:
217 return V_008F0C_SQ_SEL_W
;
218 case UTIL_FORMAT_SWIZZLE_0
:
219 return V_008F0C_SQ_SEL_0
;
220 case UTIL_FORMAT_SWIZZLE_1
:
221 return V_008F0C_SQ_SEL_1
;
222 default: /* UTIL_FORMAT_SWIZZLE_X */
223 return V_008F0C_SQ_SEL_X
;
227 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
229 return value
* (1 << frac_bits
);
232 /* 12.4 fixed-point */
233 static unsigned si_pack_float_12p4(float x
)
236 x
>= 4096 ? 0xffff : x
* 16;
240 * Inferred framebuffer and blender state.
242 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
244 * - The blend state mask is 0xf most of the time.
245 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
246 * so COLOR1 is enabled pretty much all the time.
247 * So CB_TARGET_MASK is the only register that can disable COLOR1.
249 * Another reason is to avoid a hang with dual source blending.
251 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
253 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
254 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
255 uint32_t cb_target_mask
= 0, i
;
257 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++)
258 if (sctx
->framebuffer
.state
.cbufs
[i
])
259 cb_target_mask
|= 0xf << (4*i
);
262 cb_target_mask
&= blend
->cb_target_mask
;
264 /* Avoid a hang that happens when dual source blending is enabled
265 * but there is not enough color outputs. This is undefined behavior,
266 * so disable color writes completely.
268 * Reproducible with Unigine Heaven 4.0 and drirc missing.
270 if (blend
&& blend
->dual_src_blend
&&
271 sctx
->ps_shader
.cso
&&
272 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
275 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
277 /* STONEY-specific register settings. */
278 if (sctx
->b
.family
== CHIP_STONEY
) {
279 unsigned spi_shader_col_format
=
280 sctx
->ps_shader
.cso
?
281 sctx
->ps_shader
.current
->key
.ps
.epilog
.spi_shader_col_format
: 0;
282 unsigned sx_ps_downconvert
= 0;
283 unsigned sx_blend_opt_epsilon
= 0;
284 unsigned sx_blend_opt_control
= 0;
286 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
287 struct r600_surface
*surf
=
288 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
289 unsigned format
, swap
, spi_format
, colormask
;
290 bool has_alpha
, has_rgb
;
295 format
= G_028C70_FORMAT(surf
->cb_color_info
);
296 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
297 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
298 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
300 /* Set if RGB and A are present. */
301 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
303 if (format
== V_028C70_COLOR_8
||
304 format
== V_028C70_COLOR_16
||
305 format
== V_028C70_COLOR_32
)
306 has_rgb
= !has_alpha
;
310 /* Check the colormask and export format. */
311 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
313 if (!(colormask
& PIPE_MASK_A
))
316 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
321 /* Disable value checking for disabled channels. */
323 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
325 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
327 /* Enable down-conversion for 32bpp and smaller formats. */
329 case V_028C70_COLOR_8
:
330 case V_028C70_COLOR_8_8
:
331 case V_028C70_COLOR_8_8_8_8
:
332 /* For 1 and 2-channel formats, use the superset thereof. */
333 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
334 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
335 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
336 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
337 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
341 case V_028C70_COLOR_5_6_5
:
342 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
343 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
344 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
348 case V_028C70_COLOR_1_5_5_5
:
349 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
350 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
351 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
355 case V_028C70_COLOR_4_4_4_4
:
356 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
357 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
358 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
362 case V_028C70_COLOR_32
:
363 if (swap
== V_0280A0_SWAP_STD
&&
364 spi_format
== V_028714_SPI_SHADER_32_R
)
365 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
366 else if (swap
== V_0280A0_SWAP_ALT_REV
&&
367 spi_format
== V_028714_SPI_SHADER_32_AR
)
368 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
371 case V_028C70_COLOR_16
:
372 case V_028C70_COLOR_16_16
:
373 /* For 1-channel formats, use the superset thereof. */
374 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
375 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
376 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
377 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
378 if (swap
== V_0280A0_SWAP_STD
||
379 swap
== V_0280A0_SWAP_STD_REV
)
380 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
382 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
386 case V_028C70_COLOR_10_11_11
:
387 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
388 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
389 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
393 case V_028C70_COLOR_2_10_10_10
:
394 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
395 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
396 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
402 if (sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
) {
403 sx_ps_downconvert
= 0;
404 sx_blend_opt_epsilon
= 0;
405 sx_blend_opt_control
= 0;
408 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
409 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
410 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
411 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
419 static uint32_t si_translate_blend_function(int blend_func
)
421 switch (blend_func
) {
423 return V_028780_COMB_DST_PLUS_SRC
;
424 case PIPE_BLEND_SUBTRACT
:
425 return V_028780_COMB_SRC_MINUS_DST
;
426 case PIPE_BLEND_REVERSE_SUBTRACT
:
427 return V_028780_COMB_DST_MINUS_SRC
;
429 return V_028780_COMB_MIN_DST_SRC
;
431 return V_028780_COMB_MAX_DST_SRC
;
433 R600_ERR("Unknown blend function %d\n", blend_func
);
440 static uint32_t si_translate_blend_factor(int blend_fact
)
442 switch (blend_fact
) {
443 case PIPE_BLENDFACTOR_ONE
:
444 return V_028780_BLEND_ONE
;
445 case PIPE_BLENDFACTOR_SRC_COLOR
:
446 return V_028780_BLEND_SRC_COLOR
;
447 case PIPE_BLENDFACTOR_SRC_ALPHA
:
448 return V_028780_BLEND_SRC_ALPHA
;
449 case PIPE_BLENDFACTOR_DST_ALPHA
:
450 return V_028780_BLEND_DST_ALPHA
;
451 case PIPE_BLENDFACTOR_DST_COLOR
:
452 return V_028780_BLEND_DST_COLOR
;
453 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
454 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
455 case PIPE_BLENDFACTOR_CONST_COLOR
:
456 return V_028780_BLEND_CONSTANT_COLOR
;
457 case PIPE_BLENDFACTOR_CONST_ALPHA
:
458 return V_028780_BLEND_CONSTANT_ALPHA
;
459 case PIPE_BLENDFACTOR_ZERO
:
460 return V_028780_BLEND_ZERO
;
461 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
462 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
463 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
464 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
465 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
466 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
467 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
468 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
469 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
470 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
471 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
472 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
473 case PIPE_BLENDFACTOR_SRC1_COLOR
:
474 return V_028780_BLEND_SRC1_COLOR
;
475 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
476 return V_028780_BLEND_SRC1_ALPHA
;
477 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
478 return V_028780_BLEND_INV_SRC1_COLOR
;
479 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
480 return V_028780_BLEND_INV_SRC1_ALPHA
;
482 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
489 static uint32_t si_translate_blend_opt_function(int blend_func
)
491 switch (blend_func
) {
493 return V_028760_OPT_COMB_ADD
;
494 case PIPE_BLEND_SUBTRACT
:
495 return V_028760_OPT_COMB_SUBTRACT
;
496 case PIPE_BLEND_REVERSE_SUBTRACT
:
497 return V_028760_OPT_COMB_REVSUBTRACT
;
499 return V_028760_OPT_COMB_MIN
;
501 return V_028760_OPT_COMB_MAX
;
503 return V_028760_OPT_COMB_BLEND_DISABLED
;
507 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
509 switch (blend_fact
) {
510 case PIPE_BLENDFACTOR_ZERO
:
511 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
512 case PIPE_BLENDFACTOR_ONE
:
513 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
514 case PIPE_BLENDFACTOR_SRC_COLOR
:
515 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
516 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
517 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
518 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
519 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
520 case PIPE_BLENDFACTOR_SRC_ALPHA
:
521 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
522 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
523 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
524 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
525 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
526 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
528 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
533 * Get rid of DST in the blend factors by commuting the operands:
534 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
536 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
537 unsigned *dst_factor
, unsigned expected_dst
,
538 unsigned replacement_src
)
540 if (*src_factor
== expected_dst
&&
541 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
542 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
543 *dst_factor
= replacement_src
;
545 /* Commuting the operands requires reversing subtractions. */
546 if (*func
== PIPE_BLEND_SUBTRACT
)
547 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
548 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
549 *func
= PIPE_BLEND_SUBTRACT
;
553 static bool si_blend_factor_uses_dst(unsigned factor
)
555 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
556 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
557 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
558 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
559 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
562 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
563 const struct pipe_blend_state
*state
,
566 struct si_context
*sctx
= (struct si_context
*)ctx
;
567 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
568 struct si_pm4_state
*pm4
= &blend
->pm4
;
569 uint32_t sx_mrt_blend_opt
[8] = {0};
570 uint32_t color_control
= 0;
575 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
576 blend
->alpha_to_one
= state
->alpha_to_one
;
577 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
579 if (state
->logicop_enable
) {
580 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
582 color_control
|= S_028808_ROP3(0xcc);
585 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
586 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
587 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
588 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
589 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
590 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
592 if (state
->alpha_to_coverage
)
593 blend
->need_src_alpha_4bit
|= 0xf;
595 blend
->cb_target_mask
= 0;
596 for (int i
= 0; i
< 8; i
++) {
597 /* state->rt entries > 0 only written if independent blending */
598 const int j
= state
->independent_blend_enable
? i
: 0;
600 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
601 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
602 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
603 unsigned eqA
= state
->rt
[j
].alpha_func
;
604 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
605 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
607 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
608 unsigned blend_cntl
= 0;
610 sx_mrt_blend_opt
[i
] =
611 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
612 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
614 if (!state
->rt
[j
].colormask
)
617 /* cb_render_state will disable unused ones */
618 blend
->cb_target_mask
|= state
->rt
[j
].colormask
<< (4 * i
);
620 if (!state
->rt
[j
].blend_enable
) {
621 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
625 /* Blending optimizations for Stoney.
626 * These transformations don't change the behavior.
628 * First, get rid of DST in the blend factors:
629 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
631 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
632 PIPE_BLENDFACTOR_DST_COLOR
,
633 PIPE_BLENDFACTOR_SRC_COLOR
);
634 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
635 PIPE_BLENDFACTOR_DST_COLOR
,
636 PIPE_BLENDFACTOR_SRC_COLOR
);
637 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
638 PIPE_BLENDFACTOR_DST_ALPHA
,
639 PIPE_BLENDFACTOR_SRC_ALPHA
);
641 /* Look up the ideal settings from tables. */
642 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
643 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
644 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
645 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
647 /* Handle interdependencies. */
648 if (si_blend_factor_uses_dst(srcRGB
))
649 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
650 if (si_blend_factor_uses_dst(srcA
))
651 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
653 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
654 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
655 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
656 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
657 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
659 /* Set the final value. */
660 sx_mrt_blend_opt
[i
] =
661 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
662 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
663 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
664 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
665 S_028760_ALPHA_DST_OPT(dstA_opt
) |
666 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
668 /* Set blend state. */
669 blend_cntl
|= S_028780_ENABLE(1);
670 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
671 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
672 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
674 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
675 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
676 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
677 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
678 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
680 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
682 blend
->blend_enable_4bit
|= 0xf << (i
* 4);
684 /* This is only important for formats without alpha. */
685 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
686 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
687 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
688 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
689 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
690 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
691 blend
->need_src_alpha_4bit
|= 0xf << (i
* 4);
694 if (blend
->cb_target_mask
) {
695 color_control
|= S_028808_MODE(mode
);
697 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
700 if (sctx
->b
.family
== CHIP_STONEY
) {
701 for (int i
= 0; i
< 8; i
++)
702 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
703 sx_mrt_blend_opt
[i
]);
705 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
706 if (blend
->dual_src_blend
|| state
->logicop_enable
||
707 mode
== V_028808_CB_RESOLVE
)
708 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
711 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
715 static void *si_create_blend_state(struct pipe_context
*ctx
,
716 const struct pipe_blend_state
*state
)
718 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
721 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
723 struct si_context
*sctx
= (struct si_context
*)ctx
;
724 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
725 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
728 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
730 struct si_context
*sctx
= (struct si_context
*)ctx
;
731 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
734 static void si_set_blend_color(struct pipe_context
*ctx
,
735 const struct pipe_blend_color
*state
)
737 struct si_context
*sctx
= (struct si_context
*)ctx
;
739 if (memcmp(&sctx
->blend_color
.state
, state
, sizeof(*state
)) == 0)
742 sctx
->blend_color
.state
= *state
;
743 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
746 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
748 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
750 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
751 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
758 static void si_set_clip_state(struct pipe_context
*ctx
,
759 const struct pipe_clip_state
*state
)
761 struct si_context
*sctx
= (struct si_context
*)ctx
;
762 struct pipe_constant_buffer cb
;
764 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
767 sctx
->clip_state
.state
= *state
;
768 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
771 cb
.user_buffer
= state
->ucp
;
772 cb
.buffer_offset
= 0;
773 cb
.buffer_size
= 4*4*8;
774 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_VERTEX
, SI_DRIVER_STATE_CONST_BUF
, &cb
);
775 pipe_resource_reference(&cb
.buffer
, NULL
);
778 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
780 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
782 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
783 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
786 #define SIX_BITS 0x3F
788 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
790 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
791 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
792 unsigned window_space
=
793 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
794 unsigned clipdist_mask
=
795 info
->writes_clipvertex
? SIX_BITS
: info
->clipdist_writemask
;
797 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
798 S_02881C_USE_VTX_POINT_SIZE(info
->writes_psize
) |
799 S_02881C_USE_VTX_EDGE_FLAG(info
->writes_edgeflag
) |
800 S_02881C_USE_VTX_RENDER_TARGET_INDX(info
->writes_layer
) |
801 S_02881C_USE_VTX_VIEWPORT_INDX(info
->writes_viewport_index
) |
802 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask
& 0x0F) != 0) |
803 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask
& 0xF0) != 0) |
804 S_02881C_VS_OUT_MISC_VEC_ENA(info
->writes_psize
||
805 info
->writes_edgeflag
||
806 info
->writes_layer
||
807 info
->writes_viewport_index
) |
808 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
809 (sctx
->queued
.named
.rasterizer
->clip_plane_enable
&
811 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
812 sctx
->queued
.named
.rasterizer
->pa_cl_clip_cntl
|
814 sctx
->queued
.named
.rasterizer
->clip_plane_enable
& SIX_BITS
) |
815 S_028810_CLIP_DISABLE(window_space
));
817 /* reuse needs to be set off if we write oViewport */
818 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
819 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
823 * inferred state between framebuffer and rasterizer
825 static void si_update_poly_offset_state(struct si_context
*sctx
)
827 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
829 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
)
832 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
833 case PIPE_FORMAT_Z16_UNORM
:
834 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
836 default: /* 24-bit */
837 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
839 case PIPE_FORMAT_Z32_FLOAT
:
840 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
841 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
850 static uint32_t si_translate_fill(uint32_t func
)
853 case PIPE_POLYGON_MODE_FILL
:
854 return V_028814_X_DRAW_TRIANGLES
;
855 case PIPE_POLYGON_MODE_LINE
:
856 return V_028814_X_DRAW_LINES
;
857 case PIPE_POLYGON_MODE_POINT
:
858 return V_028814_X_DRAW_POINTS
;
861 return V_028814_X_DRAW_POINTS
;
865 static void *si_create_rs_state(struct pipe_context
*ctx
,
866 const struct pipe_rasterizer_state
*state
)
868 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
869 struct si_pm4_state
*pm4
= &rs
->pm4
;
871 float psize_min
, psize_max
;
877 rs
->scissor_enable
= state
->scissor
;
878 rs
->two_side
= state
->light_twoside
;
879 rs
->multisample_enable
= state
->multisample
;
880 rs
->force_persample_interp
= state
->force_persample_interp
;
881 rs
->clip_plane_enable
= state
->clip_plane_enable
;
882 rs
->line_stipple_enable
= state
->line_stipple_enable
;
883 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
884 rs
->line_smooth
= state
->line_smooth
;
885 rs
->poly_smooth
= state
->poly_smooth
;
886 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
888 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
889 rs
->flatshade
= state
->flatshade
;
890 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
891 rs
->rasterizer_discard
= state
->rasterizer_discard
;
892 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
893 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
894 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
895 rs
->pa_cl_clip_cntl
=
896 S_028810_PS_UCP_MODE(3) |
897 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
898 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
899 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
900 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
901 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
903 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
904 S_0286D4_FLAT_SHADE_ENA(1) |
905 S_0286D4_PNT_SPRITE_ENA(1) |
906 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
907 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
908 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
909 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
910 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
912 /* point size 12.4 fixed point */
913 tmp
= (unsigned)(state
->point_size
* 8.0);
914 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
916 if (state
->point_size_per_vertex
) {
917 psize_min
= util_get_min_point_size(state
);
920 /* Force the point size to be as if the vertex output was disabled. */
921 psize_min
= state
->point_size
;
922 psize_max
= state
->point_size
;
924 /* Divide by two, because 0.5 = 1 pixel. */
925 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
926 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
927 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
929 tmp
= (unsigned)state
->line_width
* 8;
930 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
931 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
932 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
933 S_028A48_MSAA_ENABLE(state
->multisample
||
934 state
->poly_smooth
||
935 state
->line_smooth
) |
936 S_028A48_VPORT_SCISSOR_ENABLE(1));
938 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
939 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
940 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
942 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
943 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
944 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
945 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
946 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
947 S_028814_FACE(!state
->front_ccw
) |
948 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
949 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
950 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
951 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
952 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
953 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
954 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
955 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+
956 SI_SGPR_VS_STATE_BITS
* 4, state
->clamp_vertex_color
);
958 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
959 for (i
= 0; i
< 3; i
++) {
960 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
961 float offset_units
= state
->offset_units
;
962 float offset_scale
= state
->offset_scale
* 16.0f
;
965 case 0: /* 16-bit zbuffer */
966 offset_units
*= 4.0f
;
968 case 1: /* 24-bit zbuffer */
969 offset_units
*= 2.0f
;
971 case 2: /* 32-bit zbuffer */
972 offset_units
*= 1.0f
;
976 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
978 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
980 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
982 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
989 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
991 struct si_context
*sctx
= (struct si_context
*)ctx
;
992 struct si_state_rasterizer
*old_rs
=
993 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
994 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
999 if (sctx
->framebuffer
.nr_samples
> 1 &&
1000 (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
))
1001 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1003 r600_set_scissor_enable(&sctx
->b
, rs
->scissor_enable
);
1005 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1006 si_update_poly_offset_state(sctx
);
1008 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1011 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1013 struct si_context
*sctx
= (struct si_context
*)ctx
;
1015 if (sctx
->queued
.named
.rasterizer
== state
)
1016 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1017 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
1021 * infeered state between dsa and stencil ref
1023 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
1025 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1026 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1027 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1029 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1030 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1031 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1032 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1033 S_028430_STENCILOPVAL(1));
1034 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1035 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1036 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1037 S_028434_STENCILOPVAL_BF(1));
1040 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1041 const struct pipe_stencil_ref
*state
)
1043 struct si_context
*sctx
= (struct si_context
*)ctx
;
1045 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1048 sctx
->stencil_ref
.state
= *state
;
1049 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1057 static uint32_t si_translate_stencil_op(int s_op
)
1060 case PIPE_STENCIL_OP_KEEP
:
1061 return V_02842C_STENCIL_KEEP
;
1062 case PIPE_STENCIL_OP_ZERO
:
1063 return V_02842C_STENCIL_ZERO
;
1064 case PIPE_STENCIL_OP_REPLACE
:
1065 return V_02842C_STENCIL_REPLACE_TEST
;
1066 case PIPE_STENCIL_OP_INCR
:
1067 return V_02842C_STENCIL_ADD_CLAMP
;
1068 case PIPE_STENCIL_OP_DECR
:
1069 return V_02842C_STENCIL_SUB_CLAMP
;
1070 case PIPE_STENCIL_OP_INCR_WRAP
:
1071 return V_02842C_STENCIL_ADD_WRAP
;
1072 case PIPE_STENCIL_OP_DECR_WRAP
:
1073 return V_02842C_STENCIL_SUB_WRAP
;
1074 case PIPE_STENCIL_OP_INVERT
:
1075 return V_02842C_STENCIL_INVERT
;
1077 R600_ERR("Unknown stencil op %d", s_op
);
1084 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1085 const struct pipe_depth_stencil_alpha_state
*state
)
1087 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1088 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1089 unsigned db_depth_control
;
1090 uint32_t db_stencil_control
= 0;
1096 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1097 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1098 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1099 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1101 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1102 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1103 S_028800_ZFUNC(state
->depth
.func
) |
1104 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1107 if (state
->stencil
[0].enabled
) {
1108 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1109 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1110 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1111 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1112 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1114 if (state
->stencil
[1].enabled
) {
1115 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1116 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1117 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1118 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1119 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1124 if (state
->alpha
.enabled
) {
1125 dsa
->alpha_func
= state
->alpha
.func
;
1127 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1128 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1130 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1133 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1134 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1135 if (state
->depth
.bounds_test
) {
1136 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1137 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1143 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1145 struct si_context
*sctx
= (struct si_context
*)ctx
;
1146 struct si_state_dsa
*dsa
= state
;
1151 si_pm4_bind_state(sctx
, dsa
, dsa
);
1153 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1154 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1155 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1156 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1160 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1162 struct si_context
*sctx
= (struct si_context
*)ctx
;
1163 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1166 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1168 struct pipe_depth_stencil_alpha_state dsa
= {};
1170 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1173 /* DB RENDER STATE */
1175 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1177 struct si_context
*sctx
= (struct si_context
*)ctx
;
1179 /* Pipeline stat & streamout queries. */
1181 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1182 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1184 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1185 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1188 /* Occlusion queries. */
1189 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1190 sctx
->occlusion_queries_disabled
= !enable
;
1191 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1195 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
1197 struct si_context
*sctx
= (struct si_context
*)ctx
;
1199 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1202 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1204 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1205 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1206 unsigned db_shader_control
;
1208 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1210 /* DB_RENDER_CONTROL */
1211 if (sctx
->dbcb_depth_copy_enabled
||
1212 sctx
->dbcb_stencil_copy_enabled
) {
1214 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1215 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1216 S_028000_COPY_CENTROID(1) |
1217 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1218 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1220 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1221 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1224 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1225 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1228 /* DB_COUNT_CONTROL (occlusion queries) */
1229 if (sctx
->b
.num_occlusion_queries
> 0 &&
1230 !sctx
->occlusion_queries_disabled
) {
1231 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1233 if (sctx
->b
.chip_class
>= CIK
) {
1235 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1236 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1237 S_028004_ZPASS_ENABLE(1) |
1238 S_028004_SLICE_EVEN_ENABLE(1) |
1239 S_028004_SLICE_ODD_ENABLE(1));
1242 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1243 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1246 /* Disable occlusion queries. */
1247 if (sctx
->b
.chip_class
>= CIK
) {
1250 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1254 /* DB_RENDER_OVERRIDE2 */
1255 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1256 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1257 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
));
1259 db_shader_control
= S_02880C_ALPHA_TO_MASK_DISABLE(sctx
->framebuffer
.cb0_is_integer
) |
1260 sctx
->ps_db_shader_control
;
1262 /* Bug workaround for smoothing (overrasterization) on SI. */
1263 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1264 db_shader_control
&= C_02880C_Z_ORDER
;
1265 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1268 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1269 if (sctx
->framebuffer
.nr_samples
<= 1 || (rs
&& !rs
->multisample_enable
))
1270 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1272 if (sctx
->b
.family
== CHIP_STONEY
&&
1273 sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
)
1274 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1276 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1281 * format translation
1283 static uint32_t si_translate_colorformat(enum pipe_format format
)
1285 const struct util_format_description
*desc
= util_format_description(format
);
1287 #define HAS_SIZE(x,y,z,w) \
1288 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1289 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1291 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1292 return V_028C70_COLOR_10_11_11
;
1294 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1295 return V_028C70_COLOR_INVALID
;
1297 switch (desc
->nr_channels
) {
1299 switch (desc
->channel
[0].size
) {
1301 return V_028C70_COLOR_8
;
1303 return V_028C70_COLOR_16
;
1305 return V_028C70_COLOR_32
;
1309 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1310 switch (desc
->channel
[0].size
) {
1312 return V_028C70_COLOR_8_8
;
1314 return V_028C70_COLOR_16_16
;
1316 return V_028C70_COLOR_32_32
;
1318 } else if (HAS_SIZE(8,24,0,0)) {
1319 return V_028C70_COLOR_24_8
;
1320 } else if (HAS_SIZE(24,8,0,0)) {
1321 return V_028C70_COLOR_8_24
;
1325 if (HAS_SIZE(5,6,5,0)) {
1326 return V_028C70_COLOR_5_6_5
;
1327 } else if (HAS_SIZE(32,8,24,0)) {
1328 return V_028C70_COLOR_X24_8_32_FLOAT
;
1332 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1333 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1334 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1335 switch (desc
->channel
[0].size
) {
1337 return V_028C70_COLOR_4_4_4_4
;
1339 return V_028C70_COLOR_8_8_8_8
;
1341 return V_028C70_COLOR_16_16_16_16
;
1343 return V_028C70_COLOR_32_32_32_32
;
1345 } else if (HAS_SIZE(5,5,5,1)) {
1346 return V_028C70_COLOR_1_5_5_5
;
1347 } else if (HAS_SIZE(10,10,10,2)) {
1348 return V_028C70_COLOR_2_10_10_10
;
1352 return V_028C70_COLOR_INVALID
;
1355 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1357 if (SI_BIG_ENDIAN
) {
1358 switch(colorformat
) {
1359 /* 8-bit buffers. */
1360 case V_028C70_COLOR_8
:
1361 return V_028C70_ENDIAN_NONE
;
1363 /* 16-bit buffers. */
1364 case V_028C70_COLOR_5_6_5
:
1365 case V_028C70_COLOR_1_5_5_5
:
1366 case V_028C70_COLOR_4_4_4_4
:
1367 case V_028C70_COLOR_16
:
1368 case V_028C70_COLOR_8_8
:
1369 return V_028C70_ENDIAN_8IN16
;
1371 /* 32-bit buffers. */
1372 case V_028C70_COLOR_8_8_8_8
:
1373 case V_028C70_COLOR_2_10_10_10
:
1374 case V_028C70_COLOR_8_24
:
1375 case V_028C70_COLOR_24_8
:
1376 case V_028C70_COLOR_16_16
:
1377 return V_028C70_ENDIAN_8IN32
;
1379 /* 64-bit buffers. */
1380 case V_028C70_COLOR_16_16_16_16
:
1381 return V_028C70_ENDIAN_8IN16
;
1383 case V_028C70_COLOR_32_32
:
1384 return V_028C70_ENDIAN_8IN32
;
1386 /* 128-bit buffers. */
1387 case V_028C70_COLOR_32_32_32_32
:
1388 return V_028C70_ENDIAN_8IN32
;
1390 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1393 return V_028C70_ENDIAN_NONE
;
1397 static uint32_t si_translate_dbformat(enum pipe_format format
)
1400 case PIPE_FORMAT_Z16_UNORM
:
1401 return V_028040_Z_16
;
1402 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1403 case PIPE_FORMAT_X8Z24_UNORM
:
1404 case PIPE_FORMAT_Z24X8_UNORM
:
1405 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1406 return V_028040_Z_24
; /* deprecated on SI */
1407 case PIPE_FORMAT_Z32_FLOAT
:
1408 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1409 return V_028040_Z_32_FLOAT
;
1411 return V_028040_Z_INVALID
;
1416 * Texture translation
1419 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1420 enum pipe_format format
,
1421 const struct util_format_description
*desc
,
1424 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1425 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1426 sscreen
->b
.info
.drm_minor
>= 31) ||
1427 sscreen
->b
.info
.drm_major
== 3;
1428 boolean uniform
= TRUE
;
1431 /* Colorspace (return non-RGB formats directly). */
1432 switch (desc
->colorspace
) {
1433 /* Depth stencil formats */
1434 case UTIL_FORMAT_COLORSPACE_ZS
:
1436 case PIPE_FORMAT_Z16_UNORM
:
1437 return V_008F14_IMG_DATA_FORMAT_16
;
1438 case PIPE_FORMAT_X24S8_UINT
:
1439 case PIPE_FORMAT_Z24X8_UNORM
:
1440 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1441 return V_008F14_IMG_DATA_FORMAT_8_24
;
1442 case PIPE_FORMAT_X8Z24_UNORM
:
1443 case PIPE_FORMAT_S8X24_UINT
:
1444 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1445 return V_008F14_IMG_DATA_FORMAT_24_8
;
1446 case PIPE_FORMAT_S8_UINT
:
1447 return V_008F14_IMG_DATA_FORMAT_8
;
1448 case PIPE_FORMAT_Z32_FLOAT
:
1449 return V_008F14_IMG_DATA_FORMAT_32
;
1450 case PIPE_FORMAT_X32_S8X24_UINT
:
1451 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1452 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1457 case UTIL_FORMAT_COLORSPACE_YUV
:
1458 goto out_unknown
; /* TODO */
1460 case UTIL_FORMAT_COLORSPACE_SRGB
:
1461 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1469 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1470 if (!enable_compressed_formats
)
1474 case PIPE_FORMAT_RGTC1_SNORM
:
1475 case PIPE_FORMAT_LATC1_SNORM
:
1476 case PIPE_FORMAT_RGTC1_UNORM
:
1477 case PIPE_FORMAT_LATC1_UNORM
:
1478 return V_008F14_IMG_DATA_FORMAT_BC4
;
1479 case PIPE_FORMAT_RGTC2_SNORM
:
1480 case PIPE_FORMAT_LATC2_SNORM
:
1481 case PIPE_FORMAT_RGTC2_UNORM
:
1482 case PIPE_FORMAT_LATC2_UNORM
:
1483 return V_008F14_IMG_DATA_FORMAT_BC5
;
1489 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1490 sscreen
->b
.family
>= CHIP_STONEY
) {
1492 case PIPE_FORMAT_ETC1_RGB8
:
1493 case PIPE_FORMAT_ETC2_RGB8
:
1494 case PIPE_FORMAT_ETC2_SRGB8
:
1495 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1496 case PIPE_FORMAT_ETC2_RGB8A1
:
1497 case PIPE_FORMAT_ETC2_SRGB8A1
:
1498 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1499 case PIPE_FORMAT_ETC2_RGBA8
:
1500 case PIPE_FORMAT_ETC2_SRGBA8
:
1501 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1502 case PIPE_FORMAT_ETC2_R11_UNORM
:
1503 case PIPE_FORMAT_ETC2_R11_SNORM
:
1504 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1505 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1506 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1507 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1513 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1514 if (!enable_compressed_formats
)
1518 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1519 case PIPE_FORMAT_BPTC_SRGBA
:
1520 return V_008F14_IMG_DATA_FORMAT_BC7
;
1521 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1522 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1523 return V_008F14_IMG_DATA_FORMAT_BC6
;
1529 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1531 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1532 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1533 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1534 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1535 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1536 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1542 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1543 if (!enable_compressed_formats
)
1546 if (!util_format_s3tc_enabled
) {
1551 case PIPE_FORMAT_DXT1_RGB
:
1552 case PIPE_FORMAT_DXT1_RGBA
:
1553 case PIPE_FORMAT_DXT1_SRGB
:
1554 case PIPE_FORMAT_DXT1_SRGBA
:
1555 return V_008F14_IMG_DATA_FORMAT_BC1
;
1556 case PIPE_FORMAT_DXT3_RGBA
:
1557 case PIPE_FORMAT_DXT3_SRGBA
:
1558 return V_008F14_IMG_DATA_FORMAT_BC2
;
1559 case PIPE_FORMAT_DXT5_RGBA
:
1560 case PIPE_FORMAT_DXT5_SRGBA
:
1561 return V_008F14_IMG_DATA_FORMAT_BC3
;
1567 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1568 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1569 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1570 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1573 /* R8G8Bx_SNORM - TODO CxV8U8 */
1575 /* See whether the components are of the same size. */
1576 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1577 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1580 /* Non-uniform formats. */
1582 switch(desc
->nr_channels
) {
1584 if (desc
->channel
[0].size
== 5 &&
1585 desc
->channel
[1].size
== 6 &&
1586 desc
->channel
[2].size
== 5) {
1587 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1591 if (desc
->channel
[0].size
== 5 &&
1592 desc
->channel
[1].size
== 5 &&
1593 desc
->channel
[2].size
== 5 &&
1594 desc
->channel
[3].size
== 1) {
1595 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1597 if (desc
->channel
[0].size
== 10 &&
1598 desc
->channel
[1].size
== 10 &&
1599 desc
->channel
[2].size
== 10 &&
1600 desc
->channel
[3].size
== 2) {
1601 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1608 if (first_non_void
< 0 || first_non_void
> 3)
1611 /* uniform formats */
1612 switch (desc
->channel
[first_non_void
].size
) {
1614 switch (desc
->nr_channels
) {
1615 #if 0 /* Not supported for render targets */
1617 return V_008F14_IMG_DATA_FORMAT_4_4
;
1620 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1624 switch (desc
->nr_channels
) {
1626 return V_008F14_IMG_DATA_FORMAT_8
;
1628 return V_008F14_IMG_DATA_FORMAT_8_8
;
1630 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1634 switch (desc
->nr_channels
) {
1636 return V_008F14_IMG_DATA_FORMAT_16
;
1638 return V_008F14_IMG_DATA_FORMAT_16_16
;
1640 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1644 switch (desc
->nr_channels
) {
1646 return V_008F14_IMG_DATA_FORMAT_32
;
1648 return V_008F14_IMG_DATA_FORMAT_32_32
;
1649 #if 0 /* Not supported for render targets */
1651 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1654 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1659 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1663 static unsigned si_tex_wrap(unsigned wrap
)
1667 case PIPE_TEX_WRAP_REPEAT
:
1668 return V_008F30_SQ_TEX_WRAP
;
1669 case PIPE_TEX_WRAP_CLAMP
:
1670 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1671 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1672 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1673 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1674 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1675 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1676 return V_008F30_SQ_TEX_MIRROR
;
1677 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1678 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1679 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1680 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1681 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1682 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1686 static unsigned si_tex_mipfilter(unsigned filter
)
1689 case PIPE_TEX_MIPFILTER_NEAREST
:
1690 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1691 case PIPE_TEX_MIPFILTER_LINEAR
:
1692 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1694 case PIPE_TEX_MIPFILTER_NONE
:
1695 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1699 static unsigned si_tex_compare(unsigned compare
)
1703 case PIPE_FUNC_NEVER
:
1704 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1705 case PIPE_FUNC_LESS
:
1706 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1707 case PIPE_FUNC_EQUAL
:
1708 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1709 case PIPE_FUNC_LEQUAL
:
1710 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1711 case PIPE_FUNC_GREATER
:
1712 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1713 case PIPE_FUNC_NOTEQUAL
:
1714 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1715 case PIPE_FUNC_GEQUAL
:
1716 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1717 case PIPE_FUNC_ALWAYS
:
1718 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1722 static unsigned si_tex_dim(unsigned res_target
, unsigned view_target
,
1723 unsigned nr_samples
)
1725 if (view_target
== PIPE_TEXTURE_CUBE
||
1726 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1727 res_target
= view_target
;
1729 switch (res_target
) {
1731 case PIPE_TEXTURE_1D
:
1732 return V_008F1C_SQ_RSRC_IMG_1D
;
1733 case PIPE_TEXTURE_1D_ARRAY
:
1734 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1735 case PIPE_TEXTURE_2D
:
1736 case PIPE_TEXTURE_RECT
:
1737 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1738 V_008F1C_SQ_RSRC_IMG_2D
;
1739 case PIPE_TEXTURE_2D_ARRAY
:
1740 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1741 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1742 case PIPE_TEXTURE_3D
:
1743 return V_008F1C_SQ_RSRC_IMG_3D
;
1744 case PIPE_TEXTURE_CUBE
:
1745 case PIPE_TEXTURE_CUBE_ARRAY
:
1746 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1751 * Format support testing
1754 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1756 return si_translate_texformat(screen
, format
, util_format_description(format
),
1757 util_format_get_first_non_void_channel(format
)) != ~0U;
1760 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1761 const struct util_format_description
*desc
,
1764 unsigned type
= desc
->channel
[first_non_void
].type
;
1767 if (type
== UTIL_FORMAT_TYPE_FIXED
)
1768 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1770 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1771 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1773 if (desc
->nr_channels
== 4 &&
1774 desc
->channel
[0].size
== 10 &&
1775 desc
->channel
[1].size
== 10 &&
1776 desc
->channel
[2].size
== 10 &&
1777 desc
->channel
[3].size
== 2)
1778 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1780 /* See whether the components are of the same size. */
1781 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1782 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1783 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1786 switch (desc
->channel
[first_non_void
].size
) {
1788 switch (desc
->nr_channels
) {
1790 return V_008F0C_BUF_DATA_FORMAT_8
;
1792 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1795 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1799 switch (desc
->nr_channels
) {
1801 return V_008F0C_BUF_DATA_FORMAT_16
;
1803 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1806 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1810 /* From the Southern Islands ISA documentation about MTBUF:
1811 * 'Memory reads of data in memory that is 32 or 64 bits do not
1812 * undergo any format conversion.'
1814 if (type
!= UTIL_FORMAT_TYPE_FLOAT
&&
1815 !desc
->channel
[first_non_void
].pure_integer
)
1816 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1818 switch (desc
->nr_channels
) {
1820 return V_008F0C_BUF_DATA_FORMAT_32
;
1822 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1824 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1826 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1831 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1834 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1835 const struct util_format_description
*desc
,
1838 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1839 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1841 switch (desc
->channel
[first_non_void
].type
) {
1842 case UTIL_FORMAT_TYPE_SIGNED
:
1843 if (desc
->channel
[first_non_void
].normalized
)
1844 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1845 else if (desc
->channel
[first_non_void
].pure_integer
)
1846 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1848 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1850 case UTIL_FORMAT_TYPE_UNSIGNED
:
1851 if (desc
->channel
[first_non_void
].normalized
)
1852 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1853 else if (desc
->channel
[first_non_void
].pure_integer
)
1854 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1856 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1858 case UTIL_FORMAT_TYPE_FLOAT
:
1860 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1864 static bool si_is_vertex_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1866 const struct util_format_description
*desc
;
1868 unsigned data_format
;
1870 desc
= util_format_description(format
);
1871 first_non_void
= util_format_get_first_non_void_channel(format
);
1872 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1873 return data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
;
1876 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1878 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1879 r600_translate_colorswap(format
) != ~0U;
1882 static bool si_is_zs_format_supported(enum pipe_format format
)
1884 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1887 boolean
si_is_format_supported(struct pipe_screen
*screen
,
1888 enum pipe_format format
,
1889 enum pipe_texture_target target
,
1890 unsigned sample_count
,
1893 unsigned retval
= 0;
1895 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1896 R600_ERR("r600: unsupported texture type %d\n", target
);
1900 if (!util_format_is_supported(format
, usage
))
1903 if (sample_count
> 1) {
1904 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1907 switch (sample_count
) {
1913 if (format
== PIPE_FORMAT_NONE
)
1922 if (usage
& PIPE_BIND_SAMPLER_VIEW
) {
1923 if (target
== PIPE_BUFFER
) {
1924 if (si_is_vertex_format_supported(screen
, format
))
1925 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1927 if (si_is_sampler_format_supported(screen
, format
))
1928 retval
|= PIPE_BIND_SAMPLER_VIEW
;
1932 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1933 PIPE_BIND_DISPLAY_TARGET
|
1936 PIPE_BIND_BLENDABLE
)) &&
1937 si_is_colorbuffer_format_supported(format
)) {
1939 (PIPE_BIND_RENDER_TARGET
|
1940 PIPE_BIND_DISPLAY_TARGET
|
1943 if (!util_format_is_pure_integer(format
) &&
1944 !util_format_is_depth_or_stencil(format
))
1945 retval
|= usage
& PIPE_BIND_BLENDABLE
;
1948 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1949 si_is_zs_format_supported(format
)) {
1950 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1953 if ((usage
& PIPE_BIND_VERTEX_BUFFER
) &&
1954 si_is_vertex_format_supported(screen
, format
)) {
1955 retval
|= PIPE_BIND_VERTEX_BUFFER
;
1958 if (usage
& PIPE_BIND_TRANSFER_READ
)
1959 retval
|= PIPE_BIND_TRANSFER_READ
;
1960 if (usage
& PIPE_BIND_TRANSFER_WRITE
)
1961 retval
|= PIPE_BIND_TRANSFER_WRITE
;
1963 if ((usage
& PIPE_BIND_LINEAR
) &&
1964 !util_format_is_compressed(format
) &&
1965 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
1966 retval
|= PIPE_BIND_LINEAR
;
1968 return retval
== usage
;
1971 unsigned si_tile_mode_index(struct r600_texture
*rtex
, unsigned level
, bool stencil
)
1973 unsigned tile_mode_index
= 0;
1976 tile_mode_index
= rtex
->surface
.stencil_tiling_index
[level
];
1978 tile_mode_index
= rtex
->surface
.tiling_index
[level
];
1980 return tile_mode_index
;
1984 * framebuffer handling
1987 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
1988 unsigned format
, unsigned swap
,
1989 unsigned ntype
, bool is_depth
)
1991 /* Alpha is needed for alpha-to-coverage.
1992 * Blending may be with or without alpha.
1994 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
1995 unsigned alpha
= 0; /* exports alpha, but may not support blending */
1996 unsigned blend
= 0; /* supports blending, but may not export alpha */
1997 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
1999 /* Choose the SPI color formats. These are required values for Stoney/RB+.
2000 * Other chips have multiple choices, though they are not necessarily better.
2003 case V_028C70_COLOR_5_6_5
:
2004 case V_028C70_COLOR_1_5_5_5
:
2005 case V_028C70_COLOR_5_5_5_1
:
2006 case V_028C70_COLOR_4_4_4_4
:
2007 case V_028C70_COLOR_10_11_11
:
2008 case V_028C70_COLOR_11_11_10
:
2009 case V_028C70_COLOR_8
:
2010 case V_028C70_COLOR_8_8
:
2011 case V_028C70_COLOR_8_8_8_8
:
2012 case V_028C70_COLOR_10_10_10_2
:
2013 case V_028C70_COLOR_2_10_10_10
:
2014 if (ntype
== V_028C70_NUMBER_UINT
)
2015 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2016 else if (ntype
== V_028C70_NUMBER_SINT
)
2017 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2019 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2022 case V_028C70_COLOR_16
:
2023 case V_028C70_COLOR_16_16
:
2024 case V_028C70_COLOR_16_16_16_16
:
2025 if (ntype
== V_028C70_NUMBER_UNORM
||
2026 ntype
== V_028C70_NUMBER_SNORM
) {
2027 /* UNORM16 and SNORM16 don't support blending */
2028 if (ntype
== V_028C70_NUMBER_UNORM
)
2029 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2031 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2033 /* Use 32 bits per channel for blending. */
2034 if (format
== V_028C70_COLOR_16
) {
2035 if (swap
== V_028C70_SWAP_STD
) { /* R */
2036 blend
= V_028714_SPI_SHADER_32_R
;
2037 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2038 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2039 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2042 } else if (format
== V_028C70_COLOR_16_16
) {
2043 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2044 blend
= V_028714_SPI_SHADER_32_GR
;
2045 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2046 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2047 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2050 } else /* 16_16_16_16 */
2051 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2052 } else if (ntype
== V_028C70_NUMBER_UINT
)
2053 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2054 else if (ntype
== V_028C70_NUMBER_SINT
)
2055 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2056 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2057 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2062 case V_028C70_COLOR_32
:
2063 if (swap
== V_028C70_SWAP_STD
) { /* R */
2064 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2065 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2066 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2067 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2072 case V_028C70_COLOR_32_32
:
2073 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2074 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2075 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2076 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2077 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2082 case V_028C70_COLOR_32_32_32_32
:
2083 case V_028C70_COLOR_8_24
:
2084 case V_028C70_COLOR_24_8
:
2085 case V_028C70_COLOR_X24_8_32_FLOAT
:
2086 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2094 /* The DB->CB copy needs 32_ABGR. */
2096 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2098 surf
->spi_shader_col_format
= normal
;
2099 surf
->spi_shader_col_format_alpha
= alpha
;
2100 surf
->spi_shader_col_format_blend
= blend
;
2101 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2104 static void si_initialize_color_surface(struct si_context
*sctx
,
2105 struct r600_surface
*surf
)
2107 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2108 unsigned level
= surf
->base
.u
.tex
.level
;
2109 uint64_t offset
= rtex
->surface
.level
[level
].offset
;
2110 unsigned pitch
, slice
;
2111 unsigned color_info
, color_attrib
, color_pitch
, color_view
;
2112 unsigned tile_mode_index
;
2113 unsigned format
, swap
, ntype
, endian
;
2114 const struct util_format_description
*desc
;
2116 unsigned blend_clamp
= 0, blend_bypass
= 0;
2118 /* Layered rendering doesn't work with LINEAR_GENERAL.
2119 * (LINEAR_ALIGNED and others work) */
2120 if (rtex
->surface
.level
[level
].mode
== RADEON_SURF_MODE_LINEAR
) {
2121 assert(surf
->base
.u
.tex
.first_layer
== surf
->base
.u
.tex
.last_layer
);
2122 offset
+= rtex
->surface
.level
[level
].slice_size
*
2123 surf
->base
.u
.tex
.first_layer
;
2126 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2127 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2130 pitch
= (rtex
->surface
.level
[level
].nblk_x
) / 8 - 1;
2131 slice
= (rtex
->surface
.level
[level
].nblk_x
* rtex
->surface
.level
[level
].nblk_y
) / 64;
2136 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2138 desc
= util_format_description(surf
->base
.format
);
2139 for (i
= 0; i
< 4; i
++) {
2140 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2144 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2145 ntype
= V_028C70_NUMBER_FLOAT
;
2147 ntype
= V_028C70_NUMBER_UNORM
;
2148 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2149 ntype
= V_028C70_NUMBER_SRGB
;
2150 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2151 if (desc
->channel
[i
].pure_integer
) {
2152 ntype
= V_028C70_NUMBER_SINT
;
2154 assert(desc
->channel
[i
].normalized
);
2155 ntype
= V_028C70_NUMBER_SNORM
;
2157 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2158 if (desc
->channel
[i
].pure_integer
) {
2159 ntype
= V_028C70_NUMBER_UINT
;
2161 assert(desc
->channel
[i
].normalized
);
2162 ntype
= V_028C70_NUMBER_UNORM
;
2167 format
= si_translate_colorformat(surf
->base
.format
);
2168 if (format
== V_028C70_COLOR_INVALID
) {
2169 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2171 assert(format
!= V_028C70_COLOR_INVALID
);
2172 swap
= r600_translate_colorswap(surf
->base
.format
);
2173 endian
= si_colorformat_endian_swap(format
);
2175 /* blend clamp should be set for all NORM/SRGB types */
2176 if (ntype
== V_028C70_NUMBER_UNORM
||
2177 ntype
== V_028C70_NUMBER_SNORM
||
2178 ntype
== V_028C70_NUMBER_SRGB
)
2181 /* set blend bypass according to docs if SINT/UINT or
2182 8/24 COLOR variants */
2183 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2184 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2185 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2190 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2191 (format
== V_028C70_COLOR_8
||
2192 format
== V_028C70_COLOR_8_8
||
2193 format
== V_028C70_COLOR_8_8_8_8
))
2194 surf
->color_is_int8
= true;
2196 color_info
= S_028C70_FORMAT(format
) |
2197 S_028C70_COMP_SWAP(swap
) |
2198 S_028C70_BLEND_CLAMP(blend_clamp
) |
2199 S_028C70_BLEND_BYPASS(blend_bypass
) |
2200 S_028C70_NUMBER_TYPE(ntype
) |
2201 S_028C70_ENDIAN(endian
);
2203 color_pitch
= S_028C64_TILE_MAX(pitch
);
2205 /* Intensity is implemented as Red, so treat it that way. */
2206 color_attrib
= S_028C74_TILE_MODE_INDEX(tile_mode_index
) |
2207 S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == UTIL_FORMAT_SWIZZLE_1
||
2208 util_format_is_intensity(surf
->base
.format
));
2210 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2211 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2213 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2214 S_028C74_NUM_FRAGMENTS(log_samples
);
2216 if (rtex
->fmask
.size
) {
2217 color_info
|= S_028C70_COMPRESSION(1);
2218 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2220 color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(rtex
->fmask
.tile_mode_index
);
2222 if (sctx
->b
.chip_class
== SI
) {
2223 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2224 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2226 if (sctx
->b
.chip_class
>= CIK
) {
2227 color_pitch
|= S_028C64_FMASK_TILE_MAX(rtex
->fmask
.pitch_in_pixels
/ 8 - 1);
2232 offset
+= rtex
->resource
.gpu_address
;
2234 surf
->cb_color_base
= offset
>> 8;
2235 surf
->cb_color_pitch
= color_pitch
;
2236 surf
->cb_color_slice
= S_028C68_TILE_MAX(slice
);
2237 surf
->cb_color_view
= color_view
;
2238 surf
->cb_color_info
= color_info
;
2239 surf
->cb_color_attrib
= color_attrib
;
2241 if (sctx
->b
.chip_class
>= VI
&& rtex
->dcc_offset
) {
2242 unsigned max_uncompressed_block_size
= 2;
2244 if (rtex
->surface
.nsamples
> 1) {
2245 if (rtex
->surface
.bpe
== 1)
2246 max_uncompressed_block_size
= 0;
2247 else if (rtex
->surface
.bpe
== 2)
2248 max_uncompressed_block_size
= 1;
2251 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2252 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2253 surf
->cb_dcc_base
= (rtex
->resource
.gpu_address
+
2255 rtex
->surface
.level
[level
].dcc_offset
) >> 8;
2258 if (rtex
->fmask
.size
) {
2259 surf
->cb_color_fmask
= (offset
+ rtex
->fmask
.offset
) >> 8;
2260 surf
->cb_color_fmask_slice
= S_028C88_TILE_MAX(rtex
->fmask
.slice_tile_max
);
2262 /* This must be set for fast clear to work without FMASK. */
2263 surf
->cb_color_fmask
= surf
->cb_color_base
;
2264 surf
->cb_color_fmask_slice
= surf
->cb_color_slice
;
2265 surf
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2267 if (sctx
->b
.chip_class
== SI
) {
2268 unsigned bankh
= util_logbase2(rtex
->surface
.bankh
);
2269 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2272 if (sctx
->b
.chip_class
>= CIK
) {
2273 surf
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch
);
2277 /* Determine pixel shader export format */
2278 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2280 surf
->color_initialized
= true;
2283 static void si_init_depth_surface(struct si_context
*sctx
,
2284 struct r600_surface
*surf
)
2286 struct si_screen
*sscreen
= sctx
->screen
;
2287 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2288 unsigned level
= surf
->base
.u
.tex
.level
;
2289 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
2290 unsigned format
, tile_mode_index
, array_mode
;
2291 unsigned macro_aspect
, tile_split
, stile_split
, bankh
, bankw
, nbanks
, pipe_config
;
2292 uint32_t z_info
, s_info
, db_depth_info
;
2293 uint64_t z_offs
, s_offs
;
2294 uint32_t db_htile_data_base
, db_htile_surface
, pa_su_poly_offset_db_fmt_cntl
= 0;
2296 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
2297 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2298 case PIPE_FORMAT_X8Z24_UNORM
:
2299 case PIPE_FORMAT_Z24X8_UNORM
:
2300 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
2301 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2303 case PIPE_FORMAT_Z32_FLOAT
:
2304 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2305 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2306 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2308 case PIPE_FORMAT_Z16_UNORM
:
2309 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2315 format
= si_translate_dbformat(rtex
->resource
.b
.b
.format
);
2317 if (format
== V_028040_Z_INVALID
) {
2318 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2320 assert(format
!= V_028040_Z_INVALID
);
2322 s_offs
= z_offs
= rtex
->resource
.gpu_address
;
2323 z_offs
+= rtex
->surface
.level
[level
].offset
;
2324 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
2326 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(1);
2328 z_info
= S_028040_FORMAT(format
);
2329 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2330 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2333 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2334 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2336 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2338 if (sctx
->b
.chip_class
>= CIK
) {
2339 switch (rtex
->surface
.level
[level
].mode
) {
2340 case RADEON_SURF_MODE_2D
:
2341 array_mode
= V_02803C_ARRAY_2D_TILED_THIN1
;
2343 case RADEON_SURF_MODE_1D
:
2344 case RADEON_SURF_MODE_LINEAR_ALIGNED
:
2345 case RADEON_SURF_MODE_LINEAR
:
2347 array_mode
= V_02803C_ARRAY_1D_TILED_THIN1
;
2350 tile_split
= rtex
->surface
.tile_split
;
2351 stile_split
= rtex
->surface
.stencil_tile_split
;
2352 macro_aspect
= rtex
->surface
.mtilea
;
2353 bankw
= rtex
->surface
.bankw
;
2354 bankh
= rtex
->surface
.bankh
;
2355 tile_split
= cik_tile_split(tile_split
);
2356 stile_split
= cik_tile_split(stile_split
);
2357 macro_aspect
= cik_macro_tile_aspect(macro_aspect
);
2358 bankw
= cik_bank_wh(bankw
);
2359 bankh
= cik_bank_wh(bankh
);
2360 nbanks
= si_num_banks(sscreen
, rtex
);
2361 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2362 pipe_config
= cik_db_pipe_config(sscreen
, tile_mode_index
);
2364 db_depth_info
|= S_02803C_ARRAY_MODE(array_mode
) |
2365 S_02803C_PIPE_CONFIG(pipe_config
) |
2366 S_02803C_BANK_WIDTH(bankw
) |
2367 S_02803C_BANK_HEIGHT(bankh
) |
2368 S_02803C_MACRO_TILE_ASPECT(macro_aspect
) |
2369 S_02803C_NUM_BANKS(nbanks
);
2370 z_info
|= S_028040_TILE_SPLIT(tile_split
);
2371 s_info
|= S_028044_TILE_SPLIT(stile_split
);
2373 tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2374 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2375 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2376 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2379 /* HiZ aka depth buffer htile */
2380 /* use htile only for first level */
2381 if (rtex
->htile_buffer
&& !level
) {
2382 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2383 S_028040_ALLOW_EXPCLEAR(1);
2385 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2386 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2388 /* Use all of the htile_buffer for depth if there's no stencil. */
2389 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2391 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
2392 db_htile_data_base
= va
>> 8;
2393 db_htile_surface
= S_028ABC_FULL_CACHE(1);
2395 db_htile_data_base
= 0;
2396 db_htile_surface
= 0;
2399 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2401 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2402 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2403 surf
->db_htile_data_base
= db_htile_data_base
;
2404 surf
->db_depth_info
= db_depth_info
;
2405 surf
->db_z_info
= z_info
;
2406 surf
->db_stencil_info
= s_info
;
2407 surf
->db_depth_base
= z_offs
>> 8;
2408 surf
->db_stencil_base
= s_offs
>> 8;
2409 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2410 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2411 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2412 levelinfo
->nblk_y
) / 64 - 1);
2413 surf
->db_htile_surface
= db_htile_surface
;
2414 surf
->pa_su_poly_offset_db_fmt_cntl
= pa_su_poly_offset_db_fmt_cntl
;
2416 surf
->depth_initialized
= true;
2419 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2420 const struct pipe_framebuffer_state
*state
)
2422 struct si_context
*sctx
= (struct si_context
*)ctx
;
2423 struct pipe_constant_buffer constbuf
= {0};
2424 struct r600_surface
*surf
= NULL
;
2425 struct r600_texture
*rtex
;
2426 bool old_cb0_is_integer
= sctx
->framebuffer
.cb0_is_integer
;
2427 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2430 /* Only flush TC when changing the framebuffer state, because
2431 * the only client not using TC that can change textures is
2434 * Flush all CB and DB caches here because all buffers can be used
2435 * for write by both TC (with shader image stores) and CB/DB.
2437 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2438 SI_CONTEXT_INV_GLOBAL_L2
|
2439 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
;
2441 /* Take the maximum of the old and new count. If the new count is lower,
2442 * dirtying is needed to disable the unbound colorbuffers.
2444 sctx
->framebuffer
.dirty_cbufs
|=
2445 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2446 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2448 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2450 sctx
->framebuffer
.spi_shader_col_format
= 0;
2451 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2452 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2453 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2454 sctx
->framebuffer
.color_is_int8
= 0;
2456 sctx
->framebuffer
.compressed_cb_mask
= 0;
2457 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2458 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2459 sctx
->framebuffer
.cb0_is_integer
= state
->nr_cbufs
&& state
->cbufs
[0] &&
2460 util_format_is_pure_integer(state
->cbufs
[0]->format
);
2462 if (sctx
->framebuffer
.cb0_is_integer
!= old_cb0_is_integer
)
2463 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2465 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2466 if (!state
->cbufs
[i
])
2469 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2470 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2472 if (!surf
->color_initialized
) {
2473 si_initialize_color_surface(sctx
, surf
);
2476 sctx
->framebuffer
.spi_shader_col_format
|=
2477 surf
->spi_shader_col_format
<< (i
* 4);
2478 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2479 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2480 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2481 surf
->spi_shader_col_format_blend
<< (i
* 4);
2482 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2483 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2485 if (surf
->color_is_int8
)
2486 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2488 if (rtex
->fmask
.size
&& rtex
->cmask
.size
) {
2489 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2491 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2493 /* Set the second SPI format for possible dual-src blending. */
2494 if (i
== 1 && surf
) {
2495 sctx
->framebuffer
.spi_shader_col_format
|=
2496 surf
->spi_shader_col_format
<< (i
* 4);
2497 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2498 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2499 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2500 surf
->spi_shader_col_format_blend
<< (i
* 4);
2501 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2502 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2506 surf
= (struct r600_surface
*)state
->zsbuf
;
2508 if (!surf
->depth_initialized
) {
2509 si_init_depth_surface(sctx
, surf
);
2511 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2514 si_update_poly_offset_state(sctx
);
2515 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2516 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2518 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2519 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2520 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2522 /* Set sample locations as fragment shader constants. */
2523 switch (sctx
->framebuffer
.nr_samples
) {
2525 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2528 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2531 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2534 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2537 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2540 R600_ERR("Requested an invalid number of samples %i.\n",
2541 sctx
->framebuffer
.nr_samples
);
2544 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2545 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_FRAGMENT
,
2546 SI_DRIVER_STATE_CONST_BUF
, &constbuf
);
2548 /* Smoothing (only possible with nr_samples == 1) uses the same
2549 * sample locations as the MSAA it simulates.
2551 * Therefore, don't update the sample locations when
2552 * transitioning from no AA to smoothing-equivalent AA, and
2555 if ((sctx
->framebuffer
.nr_samples
!= 1 ||
2556 old_nr_samples
!= SI_NUM_SMOOTH_AA_SAMPLES
) &&
2557 (sctx
->framebuffer
.nr_samples
!= SI_NUM_SMOOTH_AA_SAMPLES
||
2558 old_nr_samples
!= 1))
2559 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
);
2563 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2565 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2566 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2567 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2568 struct r600_texture
*tex
= NULL
;
2569 struct r600_surface
*cb
= NULL
;
2572 for (i
= 0; i
< nr_cbufs
; i
++) {
2573 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2576 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2578 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2579 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2583 tex
= (struct r600_texture
*)cb
->base
.texture
;
2584 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2585 &tex
->resource
, RADEON_USAGE_READWRITE
,
2586 tex
->surface
.nsamples
> 1 ?
2587 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2588 RADEON_PRIO_COLOR_BUFFER
);
2590 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2591 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2592 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2596 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2597 sctx
->b
.chip_class
>= VI
? 14 : 13);
2598 radeon_emit(cs
, cb
->cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2599 radeon_emit(cs
, cb
->cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2600 radeon_emit(cs
, cb
->cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2601 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2602 radeon_emit(cs
, cb
->cb_color_info
| tex
->cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2603 radeon_emit(cs
, cb
->cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2604 radeon_emit(cs
, cb
->cb_dcc_control
); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2605 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
2606 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2607 radeon_emit(cs
, cb
->cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2608 radeon_emit(cs
, cb
->cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2609 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2610 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2612 if (sctx
->b
.chip_class
>= VI
)
2613 radeon_emit(cs
, cb
->cb_dcc_base
); /* R_028C94_CB_COLOR0_DCC_BASE */
2615 /* set CB_COLOR1_INFO for possible dual-src blending */
2616 if (i
== 1 && state
->cbufs
[0] &&
2617 sctx
->framebuffer
.dirty_cbufs
& (1 << 0)) {
2618 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ 1 * 0x3C,
2619 cb
->cb_color_info
| tex
->cb_color_info
);
2623 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
2624 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2627 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
2628 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2629 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2631 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2632 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2633 zb
->base
.texture
->nr_samples
> 1 ?
2634 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2635 RADEON_PRIO_DEPTH_BUFFER
);
2637 if (zb
->db_htile_data_base
) {
2638 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2639 rtex
->htile_buffer
, RADEON_USAGE_READWRITE
,
2643 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2644 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2646 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2647 radeon_emit(cs
, zb
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
2648 radeon_emit(cs
, zb
->db_z_info
| /* R_028040_DB_Z_INFO */
2649 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2650 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2651 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2652 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2653 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2654 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2655 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2656 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2658 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
2659 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
2660 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
2662 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2663 radeon_set_context_reg(cs
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
2664 zb
->pa_su_poly_offset_db_fmt_cntl
);
2665 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
2666 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2667 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2668 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2671 /* Framebuffer dimensions. */
2672 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2673 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2674 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2676 sctx
->framebuffer
.dirty_cbufs
= 0;
2677 sctx
->framebuffer
.dirty_zsbuf
= false;
2680 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
2681 struct r600_atom
*atom
)
2683 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2684 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2686 cayman_emit_msaa_sample_locs(cs
, nr_samples
> 1 ? nr_samples
:
2687 SI_NUM_SMOOTH_AA_SAMPLES
);
2690 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
2692 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2694 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2695 sctx
->ps_iter_samples
,
2696 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0);
2700 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
2702 struct si_context
*sctx
= (struct si_context
*)ctx
;
2704 if (sctx
->ps_iter_samples
== min_samples
)
2707 sctx
->ps_iter_samples
= min_samples
;
2709 if (sctx
->framebuffer
.nr_samples
> 1)
2710 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2718 * Build the sampler view descriptor for a buffer texture.
2719 * @param state 256-bit descriptor; only the high 128 bits are filled in
2722 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
2723 enum pipe_format format
,
2724 unsigned first_element
, unsigned last_element
,
2727 const struct util_format_description
*desc
;
2731 unsigned num_records
;
2732 unsigned num_format
, data_format
;
2734 desc
= util_format_description(format
);
2735 first_non_void
= util_format_get_first_non_void_channel(format
);
2736 stride
= desc
->block
.bits
/ 8;
2737 va
= buf
->gpu_address
+ first_element
* stride
;
2738 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
2739 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
2741 num_records
= last_element
+ 1 - first_element
;
2742 num_records
= MIN2(num_records
, buf
->b
.b
.width0
/ stride
);
2744 if (screen
->b
.chip_class
>= VI
)
2745 num_records
*= stride
;
2748 state
[5] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
2749 S_008F04_STRIDE(stride
);
2750 state
[6] = num_records
;
2751 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2752 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2753 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2754 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2755 S_008F0C_NUM_FORMAT(num_format
) |
2756 S_008F0C_DATA_FORMAT(data_format
);
2760 * Build the sampler view descriptor for a texture.
2763 si_make_texture_descriptor(struct si_screen
*screen
,
2764 struct r600_texture
*tex
,
2766 enum pipe_texture_target target
,
2767 enum pipe_format pipe_format
,
2768 const unsigned char state_swizzle
[4],
2769 unsigned base_level
, unsigned first_level
, unsigned last_level
,
2770 unsigned first_layer
, unsigned last_layer
,
2771 unsigned width
, unsigned height
, unsigned depth
,
2773 uint32_t *fmask_state
)
2775 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
2776 const struct radeon_surf_level
*surflevel
= tex
->surface
.level
;
2777 const struct util_format_description
*desc
;
2778 unsigned char swizzle
[4];
2780 unsigned num_format
, data_format
, type
;
2784 /* Texturing with separate depth and stencil. */
2785 if (tex
->is_depth
&& !tex
->is_flushing_texture
) {
2786 switch (pipe_format
) {
2787 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
2788 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
2790 case PIPE_FORMAT_X8Z24_UNORM
:
2791 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2792 /* Z24 is always stored like this. */
2793 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
2795 case PIPE_FORMAT_X24S8_UINT
:
2796 case PIPE_FORMAT_S8X24_UINT
:
2797 case PIPE_FORMAT_X32_S8X24_UINT
:
2798 pipe_format
= PIPE_FORMAT_S8_UINT
;
2799 surflevel
= tex
->surface
.stencil_level
;
2805 desc
= util_format_description(pipe_format
);
2807 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2808 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2809 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2811 switch (pipe_format
) {
2812 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2813 case PIPE_FORMAT_X24S8_UINT
:
2814 case PIPE_FORMAT_X32_S8X24_UINT
:
2815 case PIPE_FORMAT_X8Z24_UNORM
:
2816 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2819 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2822 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2825 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2827 switch (pipe_format
) {
2828 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2829 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2832 if (first_non_void
< 0) {
2833 if (util_format_is_compressed(pipe_format
)) {
2834 switch (pipe_format
) {
2835 case PIPE_FORMAT_DXT1_SRGB
:
2836 case PIPE_FORMAT_DXT1_SRGBA
:
2837 case PIPE_FORMAT_DXT3_SRGBA
:
2838 case PIPE_FORMAT_DXT5_SRGBA
:
2839 case PIPE_FORMAT_BPTC_SRGBA
:
2840 case PIPE_FORMAT_ETC2_SRGB8
:
2841 case PIPE_FORMAT_ETC2_SRGB8A1
:
2842 case PIPE_FORMAT_ETC2_SRGBA8
:
2843 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2845 case PIPE_FORMAT_RGTC1_SNORM
:
2846 case PIPE_FORMAT_LATC1_SNORM
:
2847 case PIPE_FORMAT_RGTC2_SNORM
:
2848 case PIPE_FORMAT_LATC2_SNORM
:
2849 case PIPE_FORMAT_ETC2_R11_SNORM
:
2850 case PIPE_FORMAT_ETC2_RG11_SNORM
:
2851 /* implies float, so use SNORM/UNORM to determine
2852 whether data is signed or not */
2853 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2854 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2857 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2860 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2861 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2863 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2865 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2866 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2868 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2870 switch (desc
->channel
[first_non_void
].type
) {
2871 case UTIL_FORMAT_TYPE_FLOAT
:
2872 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2874 case UTIL_FORMAT_TYPE_SIGNED
:
2875 if (desc
->channel
[first_non_void
].normalized
)
2876 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2877 else if (desc
->channel
[first_non_void
].pure_integer
)
2878 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2880 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2882 case UTIL_FORMAT_TYPE_UNSIGNED
:
2883 if (desc
->channel
[first_non_void
].normalized
)
2884 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2885 else if (desc
->channel
[first_non_void
].pure_integer
)
2886 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2888 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2893 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
2894 if (data_format
== ~0) {
2899 (res
->target
== PIPE_TEXTURE_CUBE
||
2900 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2901 res
->target
== PIPE_TEXTURE_3D
)) {
2902 /* For the purpose of shader images, treat cube maps and 3D
2903 * textures as 2D arrays. For 3D textures, the address
2904 * calculations for mipmaps are different, so we rely on the
2905 * caller to effectively disable mipmaps.
2907 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2909 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
2911 type
= si_tex_dim(res
->target
, target
, res
->nr_samples
);
2914 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
2916 depth
= res
->array_size
;
2917 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
2918 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
2919 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
2920 depth
= res
->array_size
;
2921 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
2922 depth
= res
->array_size
/ 6;
2924 pitch
= surflevel
[base_level
].nblk_x
* util_format_get_blockwidth(pipe_format
);
2925 va
= tex
->resource
.gpu_address
+ surflevel
[base_level
].offset
;
2928 state
[1] = (S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2929 S_008F14_DATA_FORMAT(data_format
) |
2930 S_008F14_NUM_FORMAT(num_format
));
2931 state
[2] = (S_008F18_WIDTH(width
- 1) |
2932 S_008F18_HEIGHT(height
- 1));
2933 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2934 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2935 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2936 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2937 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
2939 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
2940 util_logbase2(res
->nr_samples
) :
2942 S_008F1C_TILING_INDEX(si_tile_mode_index(tex
, base_level
, false)) |
2943 S_008F1C_POW2_PAD(res
->last_level
> 0) |
2944 S_008F1C_TYPE(type
));
2945 state
[4] = (S_008F20_DEPTH(depth
- 1) | S_008F20_PITCH(pitch
- 1));
2946 state
[5] = (S_008F24_BASE_ARRAY(first_layer
) |
2947 S_008F24_LAST_ARRAY(last_layer
));
2949 if (tex
->dcc_offset
) {
2950 unsigned swap
= r600_translate_colorswap(pipe_format
);
2952 state
[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
2953 state
[7] = (tex
->resource
.gpu_address
+
2955 surflevel
[base_level
].dcc_offset
) >> 8;
2960 /* The last dword is unused by hw. The shader uses it to clear
2961 * bits in the first dword of sampler state.
2963 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
2964 if (first_level
== last_level
)
2965 state
[7] = C_008F30_MAX_ANISO_RATIO
;
2967 state
[7] = 0xffffffff;
2971 /* Initialize the sampler view for FMASK. */
2972 if (tex
->fmask
.size
) {
2973 uint32_t fmask_format
;
2975 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
2977 switch (res
->nr_samples
) {
2979 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2982 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2985 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
2989 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
2992 fmask_state
[0] = va
>> 8;
2993 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
2994 S_008F14_DATA_FORMAT(fmask_format
) |
2995 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
2996 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
2997 S_008F18_HEIGHT(height
- 1);
2998 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
2999 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3000 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3001 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3002 S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
) |
3003 S_008F1C_TYPE(si_tex_dim(res
->target
, target
, 0));
3004 fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
3005 S_008F20_PITCH(tex
->fmask
.pitch_in_pixels
- 1);
3006 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
) |
3007 S_008F24_LAST_ARRAY(last_layer
);
3014 * Create a sampler view.
3016 * @param ctx context
3017 * @param texture texture
3018 * @param state sampler view template
3019 * @param width0 width0 override (for compressed textures as int)
3020 * @param height0 height0 override (for compressed textures as int)
3021 * @param force_level set the base address to the level (for compressed textures)
3023 struct pipe_sampler_view
*
3024 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3025 struct pipe_resource
*texture
,
3026 const struct pipe_sampler_view
*state
,
3027 unsigned width0
, unsigned height0
,
3028 unsigned force_level
)
3030 struct si_context
*sctx
= (struct si_context
*)ctx
;
3031 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3032 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3033 unsigned base_level
, first_level
, last_level
;
3034 unsigned char state_swizzle
[4];
3035 unsigned height
, depth
, width
;
3036 unsigned last_layer
= state
->u
.tex
.last_layer
;
3041 /* initialize base object */
3042 view
->base
= *state
;
3043 view
->base
.texture
= NULL
;
3044 view
->base
.reference
.count
= 1;
3045 view
->base
.context
= ctx
;
3047 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
3049 view
->state
[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state
->swizzle_r
)) |
3050 S_008F1C_DST_SEL_Y(si_map_swizzle(state
->swizzle_g
)) |
3051 S_008F1C_DST_SEL_Z(si_map_swizzle(state
->swizzle_b
)) |
3052 S_008F1C_DST_SEL_W(si_map_swizzle(state
->swizzle_a
)) |
3053 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D
);
3057 pipe_resource_reference(&view
->base
.texture
, texture
);
3059 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3060 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3061 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3062 state
->format
== PIPE_FORMAT_S8_UINT
)
3063 view
->is_stencil_sampler
= true;
3065 /* Buffer resource. */
3066 if (texture
->target
== PIPE_BUFFER
) {
3067 si_make_buffer_descriptor(sctx
->screen
,
3068 (struct r600_resource
*)texture
,
3070 state
->u
.buf
.first_element
,
3071 state
->u
.buf
.last_element
,
3074 LIST_ADDTAIL(&view
->list
, &sctx
->b
.texture_buffers
);
3078 state_swizzle
[0] = state
->swizzle_r
;
3079 state_swizzle
[1] = state
->swizzle_g
;
3080 state_swizzle
[2] = state
->swizzle_b
;
3081 state_swizzle
[3] = state
->swizzle_a
;
3084 first_level
= state
->u
.tex
.first_level
;
3085 last_level
= state
->u
.tex
.last_level
;
3088 depth
= texture
->depth0
;
3091 assert(force_level
== first_level
&&
3092 force_level
== last_level
);
3093 base_level
= force_level
;
3096 width
= u_minify(width
, force_level
);
3097 height
= u_minify(height
, force_level
);
3098 depth
= u_minify(depth
, force_level
);
3101 /* This is not needed if state trackers set last_layer correctly. */
3102 if (state
->target
== PIPE_TEXTURE_1D
||
3103 state
->target
== PIPE_TEXTURE_2D
||
3104 state
->target
== PIPE_TEXTURE_RECT
||
3105 state
->target
== PIPE_TEXTURE_CUBE
)
3106 last_layer
= state
->u
.tex
.first_layer
;
3108 si_make_texture_descriptor(sctx
->screen
, tmp
, true, state
->target
,
3109 state
->format
, state_swizzle
,
3110 base_level
, first_level
, last_level
,
3111 state
->u
.tex
.first_layer
, last_layer
,
3112 width
, height
, depth
,
3113 view
->state
, view
->fmask_state
);
3118 static struct pipe_sampler_view
*
3119 si_create_sampler_view(struct pipe_context
*ctx
,
3120 struct pipe_resource
*texture
,
3121 const struct pipe_sampler_view
*state
)
3123 return si_create_sampler_view_custom(ctx
, texture
, state
,
3124 texture
? texture
->width0
: 0,
3125 texture
? texture
->height0
: 0, 0);
3128 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3129 struct pipe_sampler_view
*state
)
3131 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3133 if (state
->texture
&& state
->texture
->target
== PIPE_BUFFER
)
3134 LIST_DELINIT(&view
->list
);
3136 pipe_resource_reference(&state
->texture
, NULL
);
3140 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3142 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3143 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3145 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3146 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3149 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
3151 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3152 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3154 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
3155 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
3156 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
3157 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
3158 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
3161 static void *si_create_sampler_state(struct pipe_context
*ctx
,
3162 const struct pipe_sampler_state
*state
)
3164 struct si_context
*sctx
= (struct si_context
*)ctx
;
3165 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
3166 unsigned border_color_type
, border_color_index
= 0;
3172 if (!sampler_state_needs_border_color(state
))
3173 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3174 else if (state
->border_color
.f
[0] == 0 &&
3175 state
->border_color
.f
[1] == 0 &&
3176 state
->border_color
.f
[2] == 0 &&
3177 state
->border_color
.f
[3] == 0)
3178 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3179 else if (state
->border_color
.f
[0] == 0 &&
3180 state
->border_color
.f
[1] == 0 &&
3181 state
->border_color
.f
[2] == 0 &&
3182 state
->border_color
.f
[3] == 1)
3183 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3184 else if (state
->border_color
.f
[0] == 1 &&
3185 state
->border_color
.f
[1] == 1 &&
3186 state
->border_color
.f
[2] == 1 &&
3187 state
->border_color
.f
[3] == 1)
3188 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3192 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
3194 /* Check if the border has been uploaded already. */
3195 for (i
= 0; i
< sctx
->border_color_count
; i
++)
3196 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
3197 sizeof(state
->border_color
)) == 0)
3200 if (i
>= SI_MAX_BORDER_COLORS
) {
3201 /* Getting 4096 unique border colors is very unlikely. */
3202 fprintf(stderr
, "radeonsi: The border color table is full. "
3203 "Any new border colors will be just black. "
3204 "Please file a bug.\n");
3205 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3207 if (i
== sctx
->border_color_count
) {
3208 /* Upload a new border color. */
3209 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
3210 sizeof(state
->border_color
));
3211 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
3212 &state
->border_color
,
3213 sizeof(state
->border_color
));
3214 sctx
->border_color_count
++;
3217 border_color_index
= i
;
3221 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
3222 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
3223 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
3224 S_008F30_MAX_ANISO_RATIO(r600_tex_aniso_filter(state
->max_anisotropy
)) |
3225 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
3226 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
3227 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
3228 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
3229 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
3230 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)));
3231 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
3232 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, state
->max_anisotropy
)) |
3233 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, state
->max_anisotropy
)) |
3234 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
3235 S_008F38_MIP_POINT_PRECLAMP(1) |
3236 S_008F38_DISABLE_LSB_CEIL(1) |
3237 S_008F38_FILTER_PREC_FIX(1) |
3238 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
3239 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
3240 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
3244 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
3246 struct si_context
*sctx
= (struct si_context
*)ctx
;
3248 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
3251 sctx
->sample_mask
.sample_mask
= sample_mask
;
3252 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
3255 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
3257 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3258 unsigned mask
= sctx
->sample_mask
.sample_mask
;
3260 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3261 radeon_emit(cs
, mask
| (mask
<< 16));
3262 radeon_emit(cs
, mask
| (mask
<< 16));
3265 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3271 * Vertex elements & buffers
3274 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3276 const struct pipe_vertex_element
*elements
)
3278 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
3281 assert(count
< SI_MAX_ATTRIBS
);
3286 for (i
= 0; i
< count
; ++i
) {
3287 const struct util_format_description
*desc
;
3288 unsigned data_format
, num_format
;
3291 desc
= util_format_description(elements
[i
].src_format
);
3292 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3293 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3294 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3296 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3297 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3298 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3299 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3300 S_008F0C_NUM_FORMAT(num_format
) |
3301 S_008F0C_DATA_FORMAT(data_format
);
3302 v
->format_size
[i
] = desc
->block
.bits
/ 8;
3304 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3309 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3311 struct si_context
*sctx
= (struct si_context
*)ctx
;
3312 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3314 sctx
->vertex_elements
= v
;
3315 sctx
->vertex_buffers_dirty
= true;
3318 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3320 struct si_context
*sctx
= (struct si_context
*)ctx
;
3322 if (sctx
->vertex_elements
== state
)
3323 sctx
->vertex_elements
= NULL
;
3327 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
3328 unsigned start_slot
, unsigned count
,
3329 const struct pipe_vertex_buffer
*buffers
)
3331 struct si_context
*sctx
= (struct si_context
*)ctx
;
3332 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
3335 assert(start_slot
+ count
<= Elements(sctx
->vertex_buffer
));
3338 for (i
= 0; i
< count
; i
++) {
3339 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
3340 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
3342 pipe_resource_reference(&dsti
->buffer
, src
->buffer
);
3343 dsti
->buffer_offset
= src
->buffer_offset
;
3344 dsti
->stride
= src
->stride
;
3345 r600_context_add_resource_size(ctx
, src
->buffer
);
3348 for (i
= 0; i
< count
; i
++) {
3349 pipe_resource_reference(&dst
[i
].buffer
, NULL
);
3352 sctx
->vertex_buffers_dirty
= true;
3355 static void si_set_index_buffer(struct pipe_context
*ctx
,
3356 const struct pipe_index_buffer
*ib
)
3358 struct si_context
*sctx
= (struct si_context
*)ctx
;
3361 pipe_resource_reference(&sctx
->index_buffer
.buffer
, ib
->buffer
);
3362 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3363 r600_context_add_resource_size(ctx
, ib
->buffer
);
3365 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3372 static void si_set_polygon_stipple(struct pipe_context
*ctx
,
3373 const struct pipe_poly_stipple
*state
)
3375 struct si_context
*sctx
= (struct si_context
*)ctx
;
3376 struct pipe_resource
*tex
;
3377 struct pipe_sampler_view
*view
;
3378 bool is_zero
= true;
3382 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
3383 * the resource is NULL/invalid. Take advantage of this fact and skip
3384 * texture allocation if the stipple pattern is constant.
3386 * This is an optimization for the common case when stippling isn't
3387 * used but set_polygon_stipple is still called by st/mesa.
3389 for (i
= 0; i
< Elements(state
->stipple
); i
++) {
3390 is_zero
= is_zero
&& state
->stipple
[i
] == 0;
3391 is_one
= is_one
&& state
->stipple
[i
] == 0xffffffff;
3394 if (is_zero
|| is_one
) {
3395 struct pipe_sampler_view templ
= {{0}};
3397 templ
.swizzle_r
= PIPE_SWIZZLE_ZERO
;
3398 templ
.swizzle_g
= PIPE_SWIZZLE_ZERO
;
3399 templ
.swizzle_b
= PIPE_SWIZZLE_ZERO
;
3400 /* The pattern should be inverted in the texture. */
3401 templ
.swizzle_a
= is_zero
? PIPE_SWIZZLE_ONE
: PIPE_SWIZZLE_ZERO
;
3403 view
= ctx
->create_sampler_view(ctx
, NULL
, &templ
);
3405 /* Create a new texture. */
3406 tex
= util_pstipple_create_stipple_texture(ctx
, state
->stipple
);
3410 view
= util_pstipple_create_sampler_view(ctx
, tex
);
3411 pipe_resource_reference(&tex
, NULL
);
3414 ctx
->set_sampler_views(ctx
, PIPE_SHADER_FRAGMENT
,
3415 SI_POLY_STIPPLE_SAMPLER
, 1, &view
);
3416 pipe_sampler_view_reference(&view
, NULL
);
3418 /* Bind the sampler state if needed. */
3419 if (!sctx
->pstipple_sampler_state
) {
3420 sctx
->pstipple_sampler_state
= util_pstipple_create_sampler(ctx
);
3421 ctx
->bind_sampler_states(ctx
, PIPE_SHADER_FRAGMENT
,
3422 SI_POLY_STIPPLE_SAMPLER
, 1,
3423 &sctx
->pstipple_sampler_state
);
3427 static void si_set_tess_state(struct pipe_context
*ctx
,
3428 const float default_outer_level
[4],
3429 const float default_inner_level
[2])
3431 struct si_context
*sctx
= (struct si_context
*)ctx
;
3432 struct pipe_constant_buffer cb
;
3435 memcpy(array
, default_outer_level
, sizeof(float) * 4);
3436 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
3439 cb
.user_buffer
= NULL
;
3440 cb
.buffer_size
= sizeof(array
);
3442 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
3443 (void*)array
, sizeof(array
),
3446 ctx
->set_constant_buffer(ctx
, PIPE_SHADER_TESS_CTRL
,
3447 SI_DRIVER_STATE_CONST_BUF
, &cb
);
3448 pipe_resource_reference(&cb
.buffer
, NULL
);
3451 static void si_texture_barrier(struct pipe_context
*ctx
)
3453 struct si_context
*sctx
= (struct si_context
*)ctx
;
3455 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
3456 SI_CONTEXT_INV_GLOBAL_L2
|
3457 SI_CONTEXT_FLUSH_AND_INV_CB
;
3460 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
3462 struct si_context
*sctx
= (struct si_context
*)ctx
;
3464 /* Subsequent commands must wait for all shader invocations to
3466 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
;
3468 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
3469 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
3470 SI_CONTEXT_INV_VMEM_L1
;
3472 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
3473 PIPE_BARRIER_SHADER_BUFFER
|
3474 PIPE_BARRIER_TEXTURE
|
3475 PIPE_BARRIER_IMAGE
|
3476 PIPE_BARRIER_STREAMOUT_BUFFER
)) {
3477 /* As far as I can tell, L1 contents are written back to L2
3478 * automatically at end of shader, but the contents of other
3479 * L1 caches might still be stale. */
3480 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
3483 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
3484 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
3486 /* Indices are read through TC L2 since VI. */
3487 if (sctx
->screen
->b
.chip_class
<= CIK
)
3488 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
3491 if (flags
& PIPE_BARRIER_FRAMEBUFFER
)
3492 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
;
3494 if (flags
& (PIPE_BARRIER_MAPPED_BUFFER
|
3495 PIPE_BARRIER_FRAMEBUFFER
|
3496 PIPE_BARRIER_INDIRECT_BUFFER
)) {
3497 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3499 * We need to make sure that TC L1 & L2 are written back to
3500 * memory, because neither CPU accesses nor CB fetches consider
3501 * TC, but there's no need to invalidate any TC cache lines. */
3502 sctx
->b
.flags
|= SI_CONTEXT_INV_GLOBAL_L2
;
3506 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3508 struct pipe_blend_state blend
;
3510 memset(&blend
, 0, sizeof(blend
));
3511 blend
.independent_blend_enable
= true;
3512 blend
.rt
[0].colormask
= 0xf;
3513 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3516 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3517 bool include_draw_vbo
)
3519 si_need_cs_space((struct si_context
*)ctx
);
3522 static void si_init_config(struct si_context
*sctx
);
3524 void si_init_state_functions(struct si_context
*sctx
)
3526 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
3527 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
3528 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
3529 si_init_external_atom(sctx
, &sctx
->b
.scissors
.atom
, &sctx
->atoms
.s
.scissors
);
3530 si_init_external_atom(sctx
, &sctx
->b
.viewports
.atom
, &sctx
->atoms
.s
.viewports
);
3532 si_init_atom(sctx
, &sctx
->cache_flush
, &sctx
->atoms
.s
.cache_flush
, si_emit_cache_flush
);
3533 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
3534 si_init_atom(sctx
, &sctx
->msaa_sample_locs
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
3535 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
3536 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
3537 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
3538 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
3539 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
3540 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
3541 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
3542 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
3544 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3545 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3546 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3547 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3549 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3550 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3551 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3553 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3554 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3555 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3557 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
3558 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3559 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3560 sctx
->custom_blend_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
3561 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
3563 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3564 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
3566 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3567 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3569 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3570 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3572 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3573 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3575 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3577 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3578 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3579 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3580 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3581 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3583 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3584 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
3585 sctx
->b
.b
.set_polygon_stipple
= si_set_polygon_stipple
;
3586 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
3587 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
3589 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
3590 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3591 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3593 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3595 if (sctx
->b
.chip_class
>= CIK
) {
3596 sctx
->b
.dma_copy
= cik_sdma_copy
;
3598 sctx
->b
.dma_copy
= si_dma_copy
;
3601 si_init_config(sctx
);
3604 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
3605 struct r600_texture
*rtex
,
3606 struct radeon_bo_metadata
*md
)
3608 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
3609 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
3610 static const unsigned char swizzle
[] = {
3616 uint32_t desc
[8], i
;
3617 bool is_array
= util_resource_is_array_texture(res
);
3619 /* DRM 2.x.x doesn't support this. */
3620 if (rscreen
->info
.drm_major
!= 3)
3623 assert(rtex
->fmask
.size
== 0);
3625 /* Metadata image format format version 1:
3626 * [0] = 1 (metadata format identifier)
3627 * [1] = (VENDOR_ID << 16) | PCI_ID
3628 * [2:9] = image descriptor for the whole resource
3629 * [2] is always 0, because the base address is cleared
3630 * [9] is the DCC offset bits [39:8] from the beginning of
3632 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3635 md
->metadata
[0] = 1; /* metadata image format version 1 */
3637 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3638 md
->metadata
[1] = (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
3640 si_make_texture_descriptor(sscreen
, rtex
, true,
3641 res
->target
, res
->format
,
3642 swizzle
, 0, 0, res
->last_level
, 0,
3643 is_array
? res
->array_size
- 1 : 0,
3644 res
->width0
, res
->height0
, res
->depth0
,
3647 /* Clear the base address and set the relative DCC offset. */
3649 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
3650 desc
[7] = rtex
->dcc_offset
>> 8;
3652 /* Dwords [2:9] contain the image descriptor. */
3653 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
3655 /* Dwords [10:..] contain the mipmap level offsets. */
3656 for (i
= 0; i
<= res
->last_level
; i
++)
3657 md
->metadata
[10+i
] = rtex
->surface
.level
[i
].offset
>> 8;
3659 md
->size_metadata
= (11 + res
->last_level
) * 4;
3662 void si_init_screen_state_functions(struct si_screen
*sscreen
)
3664 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
3668 si_write_harvested_raster_configs(struct si_context
*sctx
,
3669 struct si_pm4_state
*pm4
,
3670 unsigned raster_config
,
3671 unsigned raster_config_1
)
3673 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
3674 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
3675 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
3676 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
3677 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
3678 unsigned rb_per_se
= num_rb
/ num_se
;
3679 unsigned se_mask
[4];
3682 se_mask
[0] = ((1 << rb_per_se
) - 1) & rb_mask
;
3683 se_mask
[1] = (se_mask
[0] << rb_per_se
) & rb_mask
;
3684 se_mask
[2] = (se_mask
[1] << rb_per_se
) & rb_mask
;
3685 se_mask
[3] = (se_mask
[2] << rb_per_se
) & rb_mask
;
3687 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
3688 assert(sh_per_se
== 1 || sh_per_se
== 2);
3689 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
3691 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3692 * fields are for, so I'm leaving them as their default
3695 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
3696 (!se_mask
[2] && !se_mask
[3]))) {
3697 raster_config_1
&= C_028354_SE_PAIR_MAP
;
3699 if (!se_mask
[0] && !se_mask
[1]) {
3701 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
3704 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
3708 for (se
= 0; se
< num_se
; se
++) {
3709 unsigned raster_config_se
= raster_config
;
3710 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
3711 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
3712 int idx
= (se
/ 2) * 2;
3714 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
3715 raster_config_se
&= C_028350_SE_MAP
;
3717 if (!se_mask
[idx
]) {
3719 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
3722 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
3726 pkr0_mask
&= rb_mask
;
3727 pkr1_mask
&= rb_mask
;
3728 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
3729 raster_config_se
&= C_028350_PKR_MAP
;
3733 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
3736 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
3740 if (rb_per_se
>= 2) {
3741 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
3742 unsigned rb1_mask
= rb0_mask
<< 1;
3744 rb0_mask
&= rb_mask
;
3745 rb1_mask
&= rb_mask
;
3746 if (!rb0_mask
|| !rb1_mask
) {
3747 raster_config_se
&= C_028350_RB_MAP_PKR0
;
3751 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
3754 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
3758 if (rb_per_se
> 2) {
3759 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
3760 rb1_mask
= rb0_mask
<< 1;
3761 rb0_mask
&= rb_mask
;
3762 rb1_mask
&= rb_mask
;
3763 if (!rb0_mask
|| !rb1_mask
) {
3764 raster_config_se
&= C_028350_RB_MAP_PKR1
;
3768 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
3771 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
3777 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3778 if (sctx
->b
.chip_class
< CIK
)
3779 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3780 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
3781 INSTANCE_BROADCAST_WRITES
);
3783 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3784 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
3785 S_030800_INSTANCE_BROADCAST_WRITES(1));
3786 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
3787 if (sctx
->b
.chip_class
>= CIK
)
3788 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
3791 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3792 if (sctx
->b
.chip_class
< CIK
)
3793 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3794 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
3795 INSTANCE_BROADCAST_WRITES
);
3797 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3798 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3799 S_030800_INSTANCE_BROADCAST_WRITES(1));
3802 static void si_init_config(struct si_context
*sctx
)
3804 struct si_screen
*sscreen
= sctx
->screen
;
3805 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
3806 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
3807 unsigned raster_config
, raster_config_1
;
3808 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
3809 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3815 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
3816 si_pm4_cmd_add(pm4
, 0x80000000);
3817 si_pm4_cmd_add(pm4
, 0x80000000);
3818 si_pm4_cmd_end(pm4
, false);
3820 /* This enables pipeline stat & streamout queries.
3821 * They are only disabled by blits.
3823 si_pm4_cmd_begin(pm4
, PKT3_EVENT_WRITE
);
3824 si_pm4_cmd_add(pm4
, EVENT_TYPE(V_028A90_PIPELINESTAT_START
) |
3826 si_pm4_cmd_end(pm4
, false);
3828 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
3829 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
3831 /* FIXME calculate these values somehow ??? */
3832 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
3833 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3834 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3836 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3837 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3839 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3840 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3841 if (sctx
->b
.chip_class
< CIK
)
3842 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3843 S_008A14_CLIP_VTX_REORDER_ENA(1));
3845 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3846 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
3848 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
3850 for (i
= 0; i
< 16; i
++) {
3851 si_pm4_set_reg(pm4
, R_0282D0_PA_SC_VPORT_ZMIN_0
+ i
*8, 0);
3852 si_pm4_set_reg(pm4
, R_0282D4_PA_SC_VPORT_ZMAX_0
+ i
*8, fui(1.0));
3855 switch (sctx
->screen
->b
.family
) {
3858 raster_config
= 0x2a00126a;
3859 raster_config_1
= 0x00000000;
3862 raster_config
= 0x0000124a;
3863 raster_config_1
= 0x00000000;
3866 raster_config
= 0x00000082;
3867 raster_config_1
= 0x00000000;
3870 raster_config
= 0x00000000;
3871 raster_config_1
= 0x00000000;
3874 raster_config
= 0x16000012;
3875 raster_config_1
= 0x00000000;
3878 raster_config
= 0x3a00161a;
3879 raster_config_1
= 0x0000002e;
3882 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
3883 /* old kernels with old tiling config */
3884 raster_config
= 0x16000012;
3885 raster_config_1
= 0x0000002a;
3887 raster_config
= 0x3a00161a;
3888 raster_config_1
= 0x0000002e;
3891 case CHIP_POLARIS10
:
3892 raster_config
= 0x16000012;
3893 raster_config_1
= 0x0000002a;
3895 case CHIP_POLARIS11
:
3896 raster_config
= 0x16000012;
3897 raster_config_1
= 0x00000000;
3900 raster_config
= 0x16000012;
3901 raster_config_1
= 0x0000002a;
3904 raster_config
= 0x00000002;
3905 raster_config_1
= 0x00000000;
3908 raster_config
= 0x00000002;
3909 raster_config_1
= 0x00000000;
3912 /* KV should be 0x00000002, but that causes problems with radeon */
3913 raster_config
= 0x00000000; /* 0x00000002 */
3914 raster_config_1
= 0x00000000;
3919 raster_config
= 0x00000000;
3920 raster_config_1
= 0x00000000;
3924 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3925 raster_config
= 0x00000000;
3926 raster_config_1
= 0x00000000;
3930 /* Always use the default config when all backends are enabled
3931 * (or when we failed to determine the enabled backends).
3933 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
3934 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
3936 if (sctx
->b
.chip_class
>= CIK
)
3937 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
3940 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
3943 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
3944 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
3945 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
3946 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3947 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
3948 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
3949 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3951 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
3952 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
, 0xAAAAAAAA);
3953 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3954 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
3955 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
3956 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
3957 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
3958 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
3959 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
,
3960 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3961 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
));
3963 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
3964 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
3965 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
3967 if (sctx
->b
.chip_class
>= CIK
) {
3968 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
3969 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
3970 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
3972 if (sscreen
->b
.info
.num_good_compute_units
/
3973 (sscreen
->b
.info
.max_se
* sscreen
->b
.info
.max_sh_per_se
) <= 4) {
3974 /* Too few available compute units per SH. Disallowing
3975 * VS to run on CU0 could hurt us more than late VS
3976 * allocation would help.
3978 * LATE_ALLOC_VS = 2 is the highest safe number.
3980 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
3981 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
3982 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
3984 /* Set LATE_ALLOC_VS == 31. It should be less than
3985 * the number of scratch waves. Limitations:
3986 * - VS can't execute on CU0.
3987 * - If HS writes outputs to LDS, LS can't execute on CU0.
3989 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xfffe));
3990 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
3991 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
3994 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
3997 if (sctx
->b
.chip_class
>= VI
) {
3998 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
3999 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4000 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4001 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
4002 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
4005 if (sctx
->b
.family
== CHIP_STONEY
)
4006 si_pm4_set_reg(pm4
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
4008 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4009 if (sctx
->b
.chip_class
>= CIK
)
4010 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
4011 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4012 RADEON_PRIO_BORDER_COLORS
);
4014 si_pm4_upload_indirect_buffer(sctx
, pm4
);
4015 sctx
->init_config
= pm4
;