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radeonsi: Decompress DCC textures in a render feedback loop.
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_pstipple.h"
37 #include "util/u_resource.h"
38
39 /* Initialize an external atom (owned by ../radeon). */
40 static void
41 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
42 struct r600_atom **list_elem)
43 {
44 atom->id = list_elem - sctx->atoms.array + 1;
45 *list_elem = atom;
46 }
47
48 /* Initialize an atom owned by radeonsi. */
49 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
50 struct r600_atom **list_elem,
51 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
52 {
53 atom->emit = (void*)emit_func;
54 atom->id = list_elem - sctx->atoms.array + 1; /* index+1 in the atom array */
55 *list_elem = atom;
56 }
57
58 static unsigned si_map_swizzle(unsigned swizzle)
59 {
60 switch (swizzle) {
61 case PIPE_SWIZZLE_Y:
62 return V_008F0C_SQ_SEL_Y;
63 case PIPE_SWIZZLE_Z:
64 return V_008F0C_SQ_SEL_Z;
65 case PIPE_SWIZZLE_W:
66 return V_008F0C_SQ_SEL_W;
67 case PIPE_SWIZZLE_0:
68 return V_008F0C_SQ_SEL_0;
69 case PIPE_SWIZZLE_1:
70 return V_008F0C_SQ_SEL_1;
71 default: /* PIPE_SWIZZLE_X */
72 return V_008F0C_SQ_SEL_X;
73 }
74 }
75
76 static uint32_t S_FIXED(float value, uint32_t frac_bits)
77 {
78 return value * (1 << frac_bits);
79 }
80
81 /* 12.4 fixed-point */
82 static unsigned si_pack_float_12p4(float x)
83 {
84 return x <= 0 ? 0 :
85 x >= 4096 ? 0xffff : x * 16;
86 }
87
88 /*
89 * Inferred framebuffer and blender state.
90 *
91 * One of the reasons CB_TARGET_MASK must be derived from the framebuffer state
92 * is that:
93 * - The blend state mask is 0xf most of the time.
94 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
95 * so COLOR1 is enabled pretty much all the time.
96 * So CB_TARGET_MASK is the only register that can disable COLOR1.
97 *
98 * Another reason is to avoid a hang with dual source blending.
99 */
100 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
101 {
102 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
103 struct si_state_blend *blend = sctx->queued.named.blend;
104 uint32_t cb_target_mask = 0, i;
105
106 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
107 if (sctx->framebuffer.state.cbufs[i])
108 cb_target_mask |= 0xf << (4*i);
109
110 if (blend)
111 cb_target_mask &= blend->cb_target_mask;
112
113 /* Avoid a hang that happens when dual source blending is enabled
114 * but there is not enough color outputs. This is undefined behavior,
115 * so disable color writes completely.
116 *
117 * Reproducible with Unigine Heaven 4.0 and drirc missing.
118 */
119 if (blend && blend->dual_src_blend &&
120 sctx->ps_shader.cso &&
121 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
122 cb_target_mask = 0;
123
124 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
125
126 /* STONEY-specific register settings. */
127 if (sctx->b.family == CHIP_STONEY) {
128 unsigned spi_shader_col_format =
129 sctx->ps_shader.cso ?
130 sctx->ps_shader.current->key.ps.epilog.spi_shader_col_format : 0;
131 unsigned sx_ps_downconvert = 0;
132 unsigned sx_blend_opt_epsilon = 0;
133 unsigned sx_blend_opt_control = 0;
134
135 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
136 struct r600_surface *surf =
137 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
138 unsigned format, swap, spi_format, colormask;
139 bool has_alpha, has_rgb;
140
141 if (!surf)
142 continue;
143
144 format = G_028C70_FORMAT(surf->cb_color_info);
145 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
146 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
147 colormask = (cb_target_mask >> (i * 4)) & 0xf;
148
149 /* Set if RGB and A are present. */
150 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
151
152 if (format == V_028C70_COLOR_8 ||
153 format == V_028C70_COLOR_16 ||
154 format == V_028C70_COLOR_32)
155 has_rgb = !has_alpha;
156 else
157 has_rgb = true;
158
159 /* Check the colormask and export format. */
160 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
161 has_rgb = false;
162 if (!(colormask & PIPE_MASK_A))
163 has_alpha = false;
164
165 if (spi_format == V_028714_SPI_SHADER_ZERO) {
166 has_rgb = false;
167 has_alpha = false;
168 }
169
170 /* Disable value checking for disabled channels. */
171 if (!has_rgb)
172 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
173 if (!has_alpha)
174 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
175
176 /* Enable down-conversion for 32bpp and smaller formats. */
177 switch (format) {
178 case V_028C70_COLOR_8:
179 case V_028C70_COLOR_8_8:
180 case V_028C70_COLOR_8_8_8_8:
181 /* For 1 and 2-channel formats, use the superset thereof. */
182 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
183 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
184 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
185 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
186 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
187 }
188 break;
189
190 case V_028C70_COLOR_5_6_5:
191 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
192 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
193 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
194 }
195 break;
196
197 case V_028C70_COLOR_1_5_5_5:
198 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_4_4_4_4:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_32:
212 if (swap == V_0280A0_SWAP_STD &&
213 spi_format == V_028714_SPI_SHADER_32_R)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
215 else if (swap == V_0280A0_SWAP_ALT_REV &&
216 spi_format == V_028714_SPI_SHADER_32_AR)
217 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
218 break;
219
220 case V_028C70_COLOR_16:
221 case V_028C70_COLOR_16_16:
222 /* For 1-channel formats, use the superset thereof. */
223 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
224 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
225 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
226 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
227 if (swap == V_0280A0_SWAP_STD ||
228 swap == V_0280A0_SWAP_STD_REV)
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
230 else
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
232 }
233 break;
234
235 case V_028C70_COLOR_10_11_11:
236 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
237 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
238 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
239 }
240 break;
241
242 case V_028C70_COLOR_2_10_10_10:
243 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
244 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
245 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
246 }
247 break;
248 }
249 }
250
251 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
252 sx_ps_downconvert = 0;
253 sx_blend_opt_epsilon = 0;
254 sx_blend_opt_control = 0;
255 }
256
257 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
258 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
259 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
260 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
261 }
262 }
263
264 /*
265 * Blender functions
266 */
267
268 static uint32_t si_translate_blend_function(int blend_func)
269 {
270 switch (blend_func) {
271 case PIPE_BLEND_ADD:
272 return V_028780_COMB_DST_PLUS_SRC;
273 case PIPE_BLEND_SUBTRACT:
274 return V_028780_COMB_SRC_MINUS_DST;
275 case PIPE_BLEND_REVERSE_SUBTRACT:
276 return V_028780_COMB_DST_MINUS_SRC;
277 case PIPE_BLEND_MIN:
278 return V_028780_COMB_MIN_DST_SRC;
279 case PIPE_BLEND_MAX:
280 return V_028780_COMB_MAX_DST_SRC;
281 default:
282 R600_ERR("Unknown blend function %d\n", blend_func);
283 assert(0);
284 break;
285 }
286 return 0;
287 }
288
289 static uint32_t si_translate_blend_factor(int blend_fact)
290 {
291 switch (blend_fact) {
292 case PIPE_BLENDFACTOR_ONE:
293 return V_028780_BLEND_ONE;
294 case PIPE_BLENDFACTOR_SRC_COLOR:
295 return V_028780_BLEND_SRC_COLOR;
296 case PIPE_BLENDFACTOR_SRC_ALPHA:
297 return V_028780_BLEND_SRC_ALPHA;
298 case PIPE_BLENDFACTOR_DST_ALPHA:
299 return V_028780_BLEND_DST_ALPHA;
300 case PIPE_BLENDFACTOR_DST_COLOR:
301 return V_028780_BLEND_DST_COLOR;
302 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
303 return V_028780_BLEND_SRC_ALPHA_SATURATE;
304 case PIPE_BLENDFACTOR_CONST_COLOR:
305 return V_028780_BLEND_CONSTANT_COLOR;
306 case PIPE_BLENDFACTOR_CONST_ALPHA:
307 return V_028780_BLEND_CONSTANT_ALPHA;
308 case PIPE_BLENDFACTOR_ZERO:
309 return V_028780_BLEND_ZERO;
310 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
311 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
312 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
314 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
315 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
316 case PIPE_BLENDFACTOR_INV_DST_COLOR:
317 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
318 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
319 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
320 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
321 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
322 case PIPE_BLENDFACTOR_SRC1_COLOR:
323 return V_028780_BLEND_SRC1_COLOR;
324 case PIPE_BLENDFACTOR_SRC1_ALPHA:
325 return V_028780_BLEND_SRC1_ALPHA;
326 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
327 return V_028780_BLEND_INV_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
329 return V_028780_BLEND_INV_SRC1_ALPHA;
330 default:
331 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
332 assert(0);
333 break;
334 }
335 return 0;
336 }
337
338 static uint32_t si_translate_blend_opt_function(int blend_func)
339 {
340 switch (blend_func) {
341 case PIPE_BLEND_ADD:
342 return V_028760_OPT_COMB_ADD;
343 case PIPE_BLEND_SUBTRACT:
344 return V_028760_OPT_COMB_SUBTRACT;
345 case PIPE_BLEND_REVERSE_SUBTRACT:
346 return V_028760_OPT_COMB_REVSUBTRACT;
347 case PIPE_BLEND_MIN:
348 return V_028760_OPT_COMB_MIN;
349 case PIPE_BLEND_MAX:
350 return V_028760_OPT_COMB_MAX;
351 default:
352 return V_028760_OPT_COMB_BLEND_DISABLED;
353 }
354 }
355
356 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
357 {
358 switch (blend_fact) {
359 case PIPE_BLENDFACTOR_ZERO:
360 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
361 case PIPE_BLENDFACTOR_ONE:
362 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
363 case PIPE_BLENDFACTOR_SRC_COLOR:
364 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
365 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
366 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
367 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
368 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
369 case PIPE_BLENDFACTOR_SRC_ALPHA:
370 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
371 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
372 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
374 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
375 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
376 default:
377 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
378 }
379 }
380
381 /**
382 * Get rid of DST in the blend factors by commuting the operands:
383 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
384 */
385 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
386 unsigned *dst_factor, unsigned expected_dst,
387 unsigned replacement_src)
388 {
389 if (*src_factor == expected_dst &&
390 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
391 *src_factor = PIPE_BLENDFACTOR_ZERO;
392 *dst_factor = replacement_src;
393
394 /* Commuting the operands requires reversing subtractions. */
395 if (*func == PIPE_BLEND_SUBTRACT)
396 *func = PIPE_BLEND_REVERSE_SUBTRACT;
397 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
398 *func = PIPE_BLEND_SUBTRACT;
399 }
400 }
401
402 static bool si_blend_factor_uses_dst(unsigned factor)
403 {
404 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
405 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
406 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
407 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
408 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
409 }
410
411 static void *si_create_blend_state_mode(struct pipe_context *ctx,
412 const struct pipe_blend_state *state,
413 unsigned mode)
414 {
415 struct si_context *sctx = (struct si_context*)ctx;
416 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
417 struct si_pm4_state *pm4 = &blend->pm4;
418 uint32_t sx_mrt_blend_opt[8] = {0};
419 uint32_t color_control = 0;
420
421 if (!blend)
422 return NULL;
423
424 blend->alpha_to_coverage = state->alpha_to_coverage;
425 blend->alpha_to_one = state->alpha_to_one;
426 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
427
428 if (state->logicop_enable) {
429 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
430 } else {
431 color_control |= S_028808_ROP3(0xcc);
432 }
433
434 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
435 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
436 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
437 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
438 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
439 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
440
441 if (state->alpha_to_coverage)
442 blend->need_src_alpha_4bit |= 0xf;
443
444 blend->cb_target_mask = 0;
445 for (int i = 0; i < 8; i++) {
446 /* state->rt entries > 0 only written if independent blending */
447 const int j = state->independent_blend_enable ? i : 0;
448
449 unsigned eqRGB = state->rt[j].rgb_func;
450 unsigned srcRGB = state->rt[j].rgb_src_factor;
451 unsigned dstRGB = state->rt[j].rgb_dst_factor;
452 unsigned eqA = state->rt[j].alpha_func;
453 unsigned srcA = state->rt[j].alpha_src_factor;
454 unsigned dstA = state->rt[j].alpha_dst_factor;
455
456 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
457 unsigned blend_cntl = 0;
458
459 sx_mrt_blend_opt[i] =
460 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
461 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
462
463 if (!state->rt[j].colormask)
464 continue;
465
466 /* cb_render_state will disable unused ones */
467 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
468
469 if (!state->rt[j].blend_enable) {
470 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
471 continue;
472 }
473
474 /* Blending optimizations for Stoney.
475 * These transformations don't change the behavior.
476 *
477 * First, get rid of DST in the blend factors:
478 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
479 */
480 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
481 PIPE_BLENDFACTOR_DST_COLOR,
482 PIPE_BLENDFACTOR_SRC_COLOR);
483 si_blend_remove_dst(&eqA, &srcA, &dstA,
484 PIPE_BLENDFACTOR_DST_COLOR,
485 PIPE_BLENDFACTOR_SRC_COLOR);
486 si_blend_remove_dst(&eqA, &srcA, &dstA,
487 PIPE_BLENDFACTOR_DST_ALPHA,
488 PIPE_BLENDFACTOR_SRC_ALPHA);
489
490 /* Look up the ideal settings from tables. */
491 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
492 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
493 srcA_opt = si_translate_blend_opt_factor(srcA, true);
494 dstA_opt = si_translate_blend_opt_factor(dstA, true);
495
496 /* Handle interdependencies. */
497 if (si_blend_factor_uses_dst(srcRGB))
498 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
499 if (si_blend_factor_uses_dst(srcA))
500 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
501
502 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
503 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
504 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
505 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
506 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
507
508 /* Set the final value. */
509 sx_mrt_blend_opt[i] =
510 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
511 S_028760_COLOR_DST_OPT(dstRGB_opt) |
512 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
513 S_028760_ALPHA_SRC_OPT(srcA_opt) |
514 S_028760_ALPHA_DST_OPT(dstA_opt) |
515 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
516
517 /* Set blend state. */
518 blend_cntl |= S_028780_ENABLE(1);
519 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
520 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
521 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
522
523 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
524 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
525 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
526 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
527 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
528 }
529 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
530
531 blend->blend_enable_4bit |= 0xfu << (i * 4);
532
533 /* This is only important for formats without alpha. */
534 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
535 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
536 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
537 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
538 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
539 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
540 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
541 }
542
543 if (blend->cb_target_mask) {
544 color_control |= S_028808_MODE(mode);
545 } else {
546 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
547 }
548
549 if (sctx->b.family == CHIP_STONEY) {
550 for (int i = 0; i < 8; i++)
551 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
552 sx_mrt_blend_opt[i]);
553
554 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
555 if (blend->dual_src_blend || state->logicop_enable ||
556 mode == V_028808_CB_RESOLVE)
557 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
558 }
559
560 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
561 return blend;
562 }
563
564 static void *si_create_blend_state(struct pipe_context *ctx,
565 const struct pipe_blend_state *state)
566 {
567 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
568 }
569
570 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
571 {
572 struct si_context *sctx = (struct si_context *)ctx;
573 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
574 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
575 }
576
577 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
578 {
579 struct si_context *sctx = (struct si_context *)ctx;
580 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
581 }
582
583 static void si_set_blend_color(struct pipe_context *ctx,
584 const struct pipe_blend_color *state)
585 {
586 struct si_context *sctx = (struct si_context *)ctx;
587
588 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
589 return;
590
591 sctx->blend_color.state = *state;
592 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
593 }
594
595 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
596 {
597 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
598
599 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
600 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
601 }
602
603 /*
604 * Clipping
605 */
606
607 static void si_set_clip_state(struct pipe_context *ctx,
608 const struct pipe_clip_state *state)
609 {
610 struct si_context *sctx = (struct si_context *)ctx;
611 struct pipe_constant_buffer cb;
612
613 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
614 return;
615
616 sctx->clip_state.state = *state;
617 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
618
619 cb.buffer = NULL;
620 cb.user_buffer = state->ucp;
621 cb.buffer_offset = 0;
622 cb.buffer_size = 4*4*8;
623 si_set_constant_buffer(sctx, &sctx->rw_buffers,
624 SI_VS_CONST_CLIP_PLANES, &cb);
625 pipe_resource_reference(&cb.buffer, NULL);
626 }
627
628 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
629 {
630 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
631
632 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
633 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
634 }
635
636 #define SIX_BITS 0x3F
637
638 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
639 {
640 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
641 struct tgsi_shader_info *info = si_get_vs_info(sctx);
642 unsigned window_space =
643 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
644 unsigned clipdist_mask =
645 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
646
647 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
648 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
649 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
650 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
651 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
652 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
653 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
654 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
655 info->writes_edgeflag ||
656 info->writes_layer ||
657 info->writes_viewport_index) |
658 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(1) |
659 (sctx->queued.named.rasterizer->clip_plane_enable &
660 clipdist_mask));
661 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
662 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
663 (clipdist_mask ? 0 :
664 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
665 S_028810_CLIP_DISABLE(window_space));
666
667 /* reuse needs to be set off if we write oViewport */
668 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
669 S_028AB4_REUSE_OFF(info->writes_viewport_index));
670 }
671
672 /*
673 * inferred state between framebuffer and rasterizer
674 */
675 static void si_update_poly_offset_state(struct si_context *sctx)
676 {
677 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
678
679 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf)
680 return;
681
682 switch (sctx->framebuffer.state.zsbuf->texture->format) {
683 case PIPE_FORMAT_Z16_UNORM:
684 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
685 break;
686 default: /* 24-bit */
687 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
688 break;
689 case PIPE_FORMAT_Z32_FLOAT:
690 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
691 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
692 break;
693 }
694 }
695
696 /*
697 * Rasterizer
698 */
699
700 static uint32_t si_translate_fill(uint32_t func)
701 {
702 switch(func) {
703 case PIPE_POLYGON_MODE_FILL:
704 return V_028814_X_DRAW_TRIANGLES;
705 case PIPE_POLYGON_MODE_LINE:
706 return V_028814_X_DRAW_LINES;
707 case PIPE_POLYGON_MODE_POINT:
708 return V_028814_X_DRAW_POINTS;
709 default:
710 assert(0);
711 return V_028814_X_DRAW_POINTS;
712 }
713 }
714
715 static void *si_create_rs_state(struct pipe_context *ctx,
716 const struct pipe_rasterizer_state *state)
717 {
718 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
719 struct si_pm4_state *pm4 = &rs->pm4;
720 unsigned tmp, i;
721 float psize_min, psize_max;
722
723 if (!rs) {
724 return NULL;
725 }
726
727 rs->scissor_enable = state->scissor;
728 rs->two_side = state->light_twoside;
729 rs->multisample_enable = state->multisample;
730 rs->force_persample_interp = state->force_persample_interp;
731 rs->clip_plane_enable = state->clip_plane_enable;
732 rs->line_stipple_enable = state->line_stipple_enable;
733 rs->poly_stipple_enable = state->poly_stipple_enable;
734 rs->line_smooth = state->line_smooth;
735 rs->poly_smooth = state->poly_smooth;
736 rs->uses_poly_offset = state->offset_point || state->offset_line ||
737 state->offset_tri;
738 rs->clamp_fragment_color = state->clamp_fragment_color;
739 rs->flatshade = state->flatshade;
740 rs->sprite_coord_enable = state->sprite_coord_enable;
741 rs->rasterizer_discard = state->rasterizer_discard;
742 rs->pa_sc_line_stipple = state->line_stipple_enable ?
743 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
744 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
745 rs->pa_cl_clip_cntl =
746 S_028810_PS_UCP_MODE(3) |
747 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
748 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
749 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
750 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
751 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
752
753 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
754 S_0286D4_FLAT_SHADE_ENA(1) |
755 S_0286D4_PNT_SPRITE_ENA(1) |
756 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
757 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
758 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
759 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
760 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
761
762 /* point size 12.4 fixed point */
763 tmp = (unsigned)(state->point_size * 8.0);
764 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
765
766 if (state->point_size_per_vertex) {
767 psize_min = util_get_min_point_size(state);
768 psize_max = 8192;
769 } else {
770 /* Force the point size to be as if the vertex output was disabled. */
771 psize_min = state->point_size;
772 psize_max = state->point_size;
773 }
774 /* Divide by two, because 0.5 = 1 pixel. */
775 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
776 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
777 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
778
779 tmp = (unsigned)state->line_width * 8;
780 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
781 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
782 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
783 S_028A48_MSAA_ENABLE(state->multisample ||
784 state->poly_smooth ||
785 state->line_smooth) |
786 S_028A48_VPORT_SCISSOR_ENABLE(1));
787
788 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
789 S_028BE4_PIX_CENTER(state->half_pixel_center) |
790 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
791
792 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
793 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
794 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
795 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
796 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
797 S_028814_FACE(!state->front_ccw) |
798 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
799 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
800 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
801 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
802 state->fill_back != PIPE_POLYGON_MODE_FILL) |
803 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
804 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
805 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
806 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
807
808 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
809 for (i = 0; i < 3; i++) {
810 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
811 float offset_units = state->offset_units;
812 float offset_scale = state->offset_scale * 16.0f;
813
814 switch (i) {
815 case 0: /* 16-bit zbuffer */
816 offset_units *= 4.0f;
817 break;
818 case 1: /* 24-bit zbuffer */
819 offset_units *= 2.0f;
820 break;
821 case 2: /* 32-bit zbuffer */
822 offset_units *= 1.0f;
823 break;
824 }
825
826 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
827 fui(offset_scale));
828 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
829 fui(offset_units));
830 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
831 fui(offset_scale));
832 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
833 fui(offset_units));
834 }
835
836 return rs;
837 }
838
839 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
840 {
841 struct si_context *sctx = (struct si_context *)ctx;
842 struct si_state_rasterizer *old_rs =
843 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
844 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
845
846 if (!state)
847 return;
848
849 if (sctx->framebuffer.nr_samples > 1 &&
850 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
851 si_mark_atom_dirty(sctx, &sctx->db_render_state);
852
853 r600_set_scissor_enable(&sctx->b, rs->scissor_enable);
854
855 si_pm4_bind_state(sctx, rasterizer, rs);
856 si_update_poly_offset_state(sctx);
857
858 si_mark_atom_dirty(sctx, &sctx->clip_regs);
859 }
860
861 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
862 {
863 struct si_context *sctx = (struct si_context *)ctx;
864
865 if (sctx->queued.named.rasterizer == state)
866 si_pm4_bind_state(sctx, poly_offset, NULL);
867 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
868 }
869
870 /*
871 * infeered state between dsa and stencil ref
872 */
873 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
874 {
875 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
876 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
877 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
878
879 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
880 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
881 S_028430_STENCILMASK(dsa->valuemask[0]) |
882 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
883 S_028430_STENCILOPVAL(1));
884 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
885 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
886 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
887 S_028434_STENCILOPVAL_BF(1));
888 }
889
890 static void si_set_stencil_ref(struct pipe_context *ctx,
891 const struct pipe_stencil_ref *state)
892 {
893 struct si_context *sctx = (struct si_context *)ctx;
894
895 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
896 return;
897
898 sctx->stencil_ref.state = *state;
899 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
900 }
901
902
903 /*
904 * DSA
905 */
906
907 static uint32_t si_translate_stencil_op(int s_op)
908 {
909 switch (s_op) {
910 case PIPE_STENCIL_OP_KEEP:
911 return V_02842C_STENCIL_KEEP;
912 case PIPE_STENCIL_OP_ZERO:
913 return V_02842C_STENCIL_ZERO;
914 case PIPE_STENCIL_OP_REPLACE:
915 return V_02842C_STENCIL_REPLACE_TEST;
916 case PIPE_STENCIL_OP_INCR:
917 return V_02842C_STENCIL_ADD_CLAMP;
918 case PIPE_STENCIL_OP_DECR:
919 return V_02842C_STENCIL_SUB_CLAMP;
920 case PIPE_STENCIL_OP_INCR_WRAP:
921 return V_02842C_STENCIL_ADD_WRAP;
922 case PIPE_STENCIL_OP_DECR_WRAP:
923 return V_02842C_STENCIL_SUB_WRAP;
924 case PIPE_STENCIL_OP_INVERT:
925 return V_02842C_STENCIL_INVERT;
926 default:
927 R600_ERR("Unknown stencil op %d", s_op);
928 assert(0);
929 break;
930 }
931 return 0;
932 }
933
934 static void *si_create_dsa_state(struct pipe_context *ctx,
935 const struct pipe_depth_stencil_alpha_state *state)
936 {
937 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
938 struct si_pm4_state *pm4 = &dsa->pm4;
939 unsigned db_depth_control;
940 uint32_t db_stencil_control = 0;
941
942 if (!dsa) {
943 return NULL;
944 }
945
946 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
947 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
948 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
949 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
950
951 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
952 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
953 S_028800_ZFUNC(state->depth.func) |
954 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
955
956 /* stencil */
957 if (state->stencil[0].enabled) {
958 db_depth_control |= S_028800_STENCIL_ENABLE(1);
959 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
960 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
961 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
962 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
963
964 if (state->stencil[1].enabled) {
965 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
966 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
967 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
968 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
969 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
970 }
971 }
972
973 /* alpha */
974 if (state->alpha.enabled) {
975 dsa->alpha_func = state->alpha.func;
976
977 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
978 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
979 } else {
980 dsa->alpha_func = PIPE_FUNC_ALWAYS;
981 }
982
983 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
984 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
985 if (state->depth.bounds_test) {
986 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
987 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
988 }
989
990 return dsa;
991 }
992
993 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
994 {
995 struct si_context *sctx = (struct si_context *)ctx;
996 struct si_state_dsa *dsa = state;
997
998 if (!state)
999 return;
1000
1001 si_pm4_bind_state(sctx, dsa, dsa);
1002
1003 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1004 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1005 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1006 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1007 }
1008 }
1009
1010 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1011 {
1012 struct si_context *sctx = (struct si_context *)ctx;
1013 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1014 }
1015
1016 static void *si_create_db_flush_dsa(struct si_context *sctx)
1017 {
1018 struct pipe_depth_stencil_alpha_state dsa = {};
1019
1020 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1021 }
1022
1023 /* DB RENDER STATE */
1024
1025 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1026 {
1027 struct si_context *sctx = (struct si_context*)ctx;
1028
1029 /* Pipeline stat & streamout queries. */
1030 if (enable) {
1031 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1032 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1033 } else {
1034 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1035 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1036 }
1037
1038 /* Occlusion queries. */
1039 if (sctx->occlusion_queries_disabled != !enable) {
1040 sctx->occlusion_queries_disabled = !enable;
1041 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1042 }
1043 }
1044
1045 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1046 {
1047 struct si_context *sctx = (struct si_context*)ctx;
1048
1049 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1050 }
1051
1052 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1053 {
1054 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1055 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1056 unsigned db_shader_control;
1057
1058 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1059
1060 /* DB_RENDER_CONTROL */
1061 if (sctx->dbcb_depth_copy_enabled ||
1062 sctx->dbcb_stencil_copy_enabled) {
1063 radeon_emit(cs,
1064 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1065 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1066 S_028000_COPY_CENTROID(1) |
1067 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1068 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1069 radeon_emit(cs,
1070 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1071 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1072 } else {
1073 radeon_emit(cs,
1074 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1075 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1076 }
1077
1078 /* DB_COUNT_CONTROL (occlusion queries) */
1079 if (sctx->b.num_occlusion_queries > 0 &&
1080 !sctx->occlusion_queries_disabled) {
1081 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1082
1083 if (sctx->b.chip_class >= CIK) {
1084 radeon_emit(cs,
1085 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1086 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1087 S_028004_ZPASS_ENABLE(1) |
1088 S_028004_SLICE_EVEN_ENABLE(1) |
1089 S_028004_SLICE_ODD_ENABLE(1));
1090 } else {
1091 radeon_emit(cs,
1092 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1093 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1094 }
1095 } else {
1096 /* Disable occlusion queries. */
1097 if (sctx->b.chip_class >= CIK) {
1098 radeon_emit(cs, 0);
1099 } else {
1100 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1101 }
1102 }
1103
1104 /* DB_RENDER_OVERRIDE2 */
1105 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1106 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1107 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1108 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1109
1110 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
1111 sctx->ps_db_shader_control;
1112
1113 /* Bug workaround for smoothing (overrasterization) on SI. */
1114 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1115 db_shader_control &= C_02880C_Z_ORDER;
1116 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1117 }
1118
1119 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1120 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
1121 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1122
1123 if (sctx->b.family == CHIP_STONEY &&
1124 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1125 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1126
1127 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1128 db_shader_control);
1129 }
1130
1131 /*
1132 * format translation
1133 */
1134 static uint32_t si_translate_colorformat(enum pipe_format format)
1135 {
1136 const struct util_format_description *desc = util_format_description(format);
1137
1138 #define HAS_SIZE(x,y,z,w) \
1139 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1140 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1141
1142 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1143 return V_028C70_COLOR_10_11_11;
1144
1145 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1146 return V_028C70_COLOR_INVALID;
1147
1148 /* hw cannot support mixed formats (except depth/stencil, since
1149 * stencil is not written to). */
1150 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1151 return V_028C70_COLOR_INVALID;
1152
1153 switch (desc->nr_channels) {
1154 case 1:
1155 switch (desc->channel[0].size) {
1156 case 8:
1157 return V_028C70_COLOR_8;
1158 case 16:
1159 return V_028C70_COLOR_16;
1160 case 32:
1161 return V_028C70_COLOR_32;
1162 }
1163 break;
1164 case 2:
1165 if (desc->channel[0].size == desc->channel[1].size) {
1166 switch (desc->channel[0].size) {
1167 case 8:
1168 return V_028C70_COLOR_8_8;
1169 case 16:
1170 return V_028C70_COLOR_16_16;
1171 case 32:
1172 return V_028C70_COLOR_32_32;
1173 }
1174 } else if (HAS_SIZE(8,24,0,0)) {
1175 return V_028C70_COLOR_24_8;
1176 } else if (HAS_SIZE(24,8,0,0)) {
1177 return V_028C70_COLOR_8_24;
1178 }
1179 break;
1180 case 3:
1181 if (HAS_SIZE(5,6,5,0)) {
1182 return V_028C70_COLOR_5_6_5;
1183 } else if (HAS_SIZE(32,8,24,0)) {
1184 return V_028C70_COLOR_X24_8_32_FLOAT;
1185 }
1186 break;
1187 case 4:
1188 if (desc->channel[0].size == desc->channel[1].size &&
1189 desc->channel[0].size == desc->channel[2].size &&
1190 desc->channel[0].size == desc->channel[3].size) {
1191 switch (desc->channel[0].size) {
1192 case 4:
1193 return V_028C70_COLOR_4_4_4_4;
1194 case 8:
1195 return V_028C70_COLOR_8_8_8_8;
1196 case 16:
1197 return V_028C70_COLOR_16_16_16_16;
1198 case 32:
1199 return V_028C70_COLOR_32_32_32_32;
1200 }
1201 } else if (HAS_SIZE(5,5,5,1)) {
1202 return V_028C70_COLOR_1_5_5_5;
1203 } else if (HAS_SIZE(10,10,10,2)) {
1204 return V_028C70_COLOR_2_10_10_10;
1205 }
1206 break;
1207 }
1208 return V_028C70_COLOR_INVALID;
1209 }
1210
1211 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1212 {
1213 if (SI_BIG_ENDIAN) {
1214 switch(colorformat) {
1215 /* 8-bit buffers. */
1216 case V_028C70_COLOR_8:
1217 return V_028C70_ENDIAN_NONE;
1218
1219 /* 16-bit buffers. */
1220 case V_028C70_COLOR_5_6_5:
1221 case V_028C70_COLOR_1_5_5_5:
1222 case V_028C70_COLOR_4_4_4_4:
1223 case V_028C70_COLOR_16:
1224 case V_028C70_COLOR_8_8:
1225 return V_028C70_ENDIAN_8IN16;
1226
1227 /* 32-bit buffers. */
1228 case V_028C70_COLOR_8_8_8_8:
1229 case V_028C70_COLOR_2_10_10_10:
1230 case V_028C70_COLOR_8_24:
1231 case V_028C70_COLOR_24_8:
1232 case V_028C70_COLOR_16_16:
1233 return V_028C70_ENDIAN_8IN32;
1234
1235 /* 64-bit buffers. */
1236 case V_028C70_COLOR_16_16_16_16:
1237 return V_028C70_ENDIAN_8IN16;
1238
1239 case V_028C70_COLOR_32_32:
1240 return V_028C70_ENDIAN_8IN32;
1241
1242 /* 128-bit buffers. */
1243 case V_028C70_COLOR_32_32_32_32:
1244 return V_028C70_ENDIAN_8IN32;
1245 default:
1246 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1247 }
1248 } else {
1249 return V_028C70_ENDIAN_NONE;
1250 }
1251 }
1252
1253 static uint32_t si_translate_dbformat(enum pipe_format format)
1254 {
1255 switch (format) {
1256 case PIPE_FORMAT_Z16_UNORM:
1257 return V_028040_Z_16;
1258 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1259 case PIPE_FORMAT_X8Z24_UNORM:
1260 case PIPE_FORMAT_Z24X8_UNORM:
1261 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1262 return V_028040_Z_24; /* deprecated on SI */
1263 case PIPE_FORMAT_Z32_FLOAT:
1264 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1265 return V_028040_Z_32_FLOAT;
1266 default:
1267 return V_028040_Z_INVALID;
1268 }
1269 }
1270
1271 /*
1272 * Texture translation
1273 */
1274
1275 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1276 enum pipe_format format,
1277 const struct util_format_description *desc,
1278 int first_non_void)
1279 {
1280 struct si_screen *sscreen = (struct si_screen*)screen;
1281 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1282 sscreen->b.info.drm_minor >= 31) ||
1283 sscreen->b.info.drm_major == 3;
1284 boolean uniform = TRUE;
1285 int i;
1286
1287 /* Colorspace (return non-RGB formats directly). */
1288 switch (desc->colorspace) {
1289 /* Depth stencil formats */
1290 case UTIL_FORMAT_COLORSPACE_ZS:
1291 switch (format) {
1292 case PIPE_FORMAT_Z16_UNORM:
1293 return V_008F14_IMG_DATA_FORMAT_16;
1294 case PIPE_FORMAT_X24S8_UINT:
1295 case PIPE_FORMAT_Z24X8_UNORM:
1296 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1297 return V_008F14_IMG_DATA_FORMAT_8_24;
1298 case PIPE_FORMAT_X8Z24_UNORM:
1299 case PIPE_FORMAT_S8X24_UINT:
1300 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1301 return V_008F14_IMG_DATA_FORMAT_24_8;
1302 case PIPE_FORMAT_S8_UINT:
1303 return V_008F14_IMG_DATA_FORMAT_8;
1304 case PIPE_FORMAT_Z32_FLOAT:
1305 return V_008F14_IMG_DATA_FORMAT_32;
1306 case PIPE_FORMAT_X32_S8X24_UINT:
1307 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1308 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1309 default:
1310 goto out_unknown;
1311 }
1312
1313 case UTIL_FORMAT_COLORSPACE_YUV:
1314 goto out_unknown; /* TODO */
1315
1316 case UTIL_FORMAT_COLORSPACE_SRGB:
1317 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1318 goto out_unknown;
1319 break;
1320
1321 default:
1322 break;
1323 }
1324
1325 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1326 if (!enable_compressed_formats)
1327 goto out_unknown;
1328
1329 switch (format) {
1330 case PIPE_FORMAT_RGTC1_SNORM:
1331 case PIPE_FORMAT_LATC1_SNORM:
1332 case PIPE_FORMAT_RGTC1_UNORM:
1333 case PIPE_FORMAT_LATC1_UNORM:
1334 return V_008F14_IMG_DATA_FORMAT_BC4;
1335 case PIPE_FORMAT_RGTC2_SNORM:
1336 case PIPE_FORMAT_LATC2_SNORM:
1337 case PIPE_FORMAT_RGTC2_UNORM:
1338 case PIPE_FORMAT_LATC2_UNORM:
1339 return V_008F14_IMG_DATA_FORMAT_BC5;
1340 default:
1341 goto out_unknown;
1342 }
1343 }
1344
1345 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1346 sscreen->b.family == CHIP_STONEY) {
1347 switch (format) {
1348 case PIPE_FORMAT_ETC1_RGB8:
1349 case PIPE_FORMAT_ETC2_RGB8:
1350 case PIPE_FORMAT_ETC2_SRGB8:
1351 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1352 case PIPE_FORMAT_ETC2_RGB8A1:
1353 case PIPE_FORMAT_ETC2_SRGB8A1:
1354 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1355 case PIPE_FORMAT_ETC2_RGBA8:
1356 case PIPE_FORMAT_ETC2_SRGBA8:
1357 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1358 case PIPE_FORMAT_ETC2_R11_UNORM:
1359 case PIPE_FORMAT_ETC2_R11_SNORM:
1360 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1361 case PIPE_FORMAT_ETC2_RG11_UNORM:
1362 case PIPE_FORMAT_ETC2_RG11_SNORM:
1363 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1364 default:
1365 goto out_unknown;
1366 }
1367 }
1368
1369 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1370 if (!enable_compressed_formats)
1371 goto out_unknown;
1372
1373 switch (format) {
1374 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1375 case PIPE_FORMAT_BPTC_SRGBA:
1376 return V_008F14_IMG_DATA_FORMAT_BC7;
1377 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1378 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1379 return V_008F14_IMG_DATA_FORMAT_BC6;
1380 default:
1381 goto out_unknown;
1382 }
1383 }
1384
1385 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1386 switch (format) {
1387 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1388 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1389 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1390 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1391 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1392 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1393 default:
1394 goto out_unknown;
1395 }
1396 }
1397
1398 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1399 if (!enable_compressed_formats)
1400 goto out_unknown;
1401
1402 if (!util_format_s3tc_enabled) {
1403 goto out_unknown;
1404 }
1405
1406 switch (format) {
1407 case PIPE_FORMAT_DXT1_RGB:
1408 case PIPE_FORMAT_DXT1_RGBA:
1409 case PIPE_FORMAT_DXT1_SRGB:
1410 case PIPE_FORMAT_DXT1_SRGBA:
1411 return V_008F14_IMG_DATA_FORMAT_BC1;
1412 case PIPE_FORMAT_DXT3_RGBA:
1413 case PIPE_FORMAT_DXT3_SRGBA:
1414 return V_008F14_IMG_DATA_FORMAT_BC2;
1415 case PIPE_FORMAT_DXT5_RGBA:
1416 case PIPE_FORMAT_DXT5_SRGBA:
1417 return V_008F14_IMG_DATA_FORMAT_BC3;
1418 default:
1419 goto out_unknown;
1420 }
1421 }
1422
1423 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1424 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1425 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1426 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1427 }
1428
1429 /* R8G8Bx_SNORM - TODO CxV8U8 */
1430
1431 /* hw cannot support mixed formats (except depth/stencil, since only
1432 * depth is read).*/
1433 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1434 goto out_unknown;
1435
1436 /* See whether the components are of the same size. */
1437 for (i = 1; i < desc->nr_channels; i++) {
1438 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1439 }
1440
1441 /* Non-uniform formats. */
1442 if (!uniform) {
1443 switch(desc->nr_channels) {
1444 case 3:
1445 if (desc->channel[0].size == 5 &&
1446 desc->channel[1].size == 6 &&
1447 desc->channel[2].size == 5) {
1448 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1449 }
1450 goto out_unknown;
1451 case 4:
1452 if (desc->channel[0].size == 5 &&
1453 desc->channel[1].size == 5 &&
1454 desc->channel[2].size == 5 &&
1455 desc->channel[3].size == 1) {
1456 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1457 }
1458 if (desc->channel[0].size == 10 &&
1459 desc->channel[1].size == 10 &&
1460 desc->channel[2].size == 10 &&
1461 desc->channel[3].size == 2) {
1462 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1463 }
1464 goto out_unknown;
1465 }
1466 goto out_unknown;
1467 }
1468
1469 if (first_non_void < 0 || first_non_void > 3)
1470 goto out_unknown;
1471
1472 /* uniform formats */
1473 switch (desc->channel[first_non_void].size) {
1474 case 4:
1475 switch (desc->nr_channels) {
1476 #if 0 /* Not supported for render targets */
1477 case 2:
1478 return V_008F14_IMG_DATA_FORMAT_4_4;
1479 #endif
1480 case 4:
1481 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1482 }
1483 break;
1484 case 8:
1485 switch (desc->nr_channels) {
1486 case 1:
1487 return V_008F14_IMG_DATA_FORMAT_8;
1488 case 2:
1489 return V_008F14_IMG_DATA_FORMAT_8_8;
1490 case 4:
1491 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1492 }
1493 break;
1494 case 16:
1495 switch (desc->nr_channels) {
1496 case 1:
1497 return V_008F14_IMG_DATA_FORMAT_16;
1498 case 2:
1499 return V_008F14_IMG_DATA_FORMAT_16_16;
1500 case 4:
1501 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1502 }
1503 break;
1504 case 32:
1505 switch (desc->nr_channels) {
1506 case 1:
1507 return V_008F14_IMG_DATA_FORMAT_32;
1508 case 2:
1509 return V_008F14_IMG_DATA_FORMAT_32_32;
1510 #if 0 /* Not supported for render targets */
1511 case 3:
1512 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1513 #endif
1514 case 4:
1515 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1516 }
1517 }
1518
1519 out_unknown:
1520 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1521 return ~0;
1522 }
1523
1524 static unsigned si_tex_wrap(unsigned wrap)
1525 {
1526 switch (wrap) {
1527 default:
1528 case PIPE_TEX_WRAP_REPEAT:
1529 return V_008F30_SQ_TEX_WRAP;
1530 case PIPE_TEX_WRAP_CLAMP:
1531 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1532 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1533 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1534 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1535 return V_008F30_SQ_TEX_CLAMP_BORDER;
1536 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1537 return V_008F30_SQ_TEX_MIRROR;
1538 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1539 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1540 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1541 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1542 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1543 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1544 }
1545 }
1546
1547 static unsigned si_tex_mipfilter(unsigned filter)
1548 {
1549 switch (filter) {
1550 case PIPE_TEX_MIPFILTER_NEAREST:
1551 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1552 case PIPE_TEX_MIPFILTER_LINEAR:
1553 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1554 default:
1555 case PIPE_TEX_MIPFILTER_NONE:
1556 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1557 }
1558 }
1559
1560 static unsigned si_tex_compare(unsigned compare)
1561 {
1562 switch (compare) {
1563 default:
1564 case PIPE_FUNC_NEVER:
1565 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1566 case PIPE_FUNC_LESS:
1567 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1568 case PIPE_FUNC_EQUAL:
1569 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1570 case PIPE_FUNC_LEQUAL:
1571 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1572 case PIPE_FUNC_GREATER:
1573 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1574 case PIPE_FUNC_NOTEQUAL:
1575 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1576 case PIPE_FUNC_GEQUAL:
1577 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1578 case PIPE_FUNC_ALWAYS:
1579 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1580 }
1581 }
1582
1583 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1584 unsigned nr_samples)
1585 {
1586 if (view_target == PIPE_TEXTURE_CUBE ||
1587 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1588 res_target = view_target;
1589
1590 switch (res_target) {
1591 default:
1592 case PIPE_TEXTURE_1D:
1593 return V_008F1C_SQ_RSRC_IMG_1D;
1594 case PIPE_TEXTURE_1D_ARRAY:
1595 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1596 case PIPE_TEXTURE_2D:
1597 case PIPE_TEXTURE_RECT:
1598 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1599 V_008F1C_SQ_RSRC_IMG_2D;
1600 case PIPE_TEXTURE_2D_ARRAY:
1601 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1602 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1603 case PIPE_TEXTURE_3D:
1604 return V_008F1C_SQ_RSRC_IMG_3D;
1605 case PIPE_TEXTURE_CUBE:
1606 case PIPE_TEXTURE_CUBE_ARRAY:
1607 return V_008F1C_SQ_RSRC_IMG_CUBE;
1608 }
1609 }
1610
1611 /*
1612 * Format support testing
1613 */
1614
1615 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1616 {
1617 return si_translate_texformat(screen, format, util_format_description(format),
1618 util_format_get_first_non_void_channel(format)) != ~0U;
1619 }
1620
1621 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1622 const struct util_format_description *desc,
1623 int first_non_void)
1624 {
1625 unsigned type;
1626 int i;
1627
1628 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1629 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1630
1631 assert(first_non_void >= 0);
1632 type = desc->channel[first_non_void].type;
1633
1634 if (type == UTIL_FORMAT_TYPE_FIXED)
1635 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1636
1637 if (desc->nr_channels == 4 &&
1638 desc->channel[0].size == 10 &&
1639 desc->channel[1].size == 10 &&
1640 desc->channel[2].size == 10 &&
1641 desc->channel[3].size == 2)
1642 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1643
1644 /* See whether the components are of the same size. */
1645 for (i = 0; i < desc->nr_channels; i++) {
1646 if (desc->channel[first_non_void].size != desc->channel[i].size)
1647 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1648 }
1649
1650 switch (desc->channel[first_non_void].size) {
1651 case 8:
1652 switch (desc->nr_channels) {
1653 case 1:
1654 return V_008F0C_BUF_DATA_FORMAT_8;
1655 case 2:
1656 return V_008F0C_BUF_DATA_FORMAT_8_8;
1657 case 3:
1658 case 4:
1659 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1660 }
1661 break;
1662 case 16:
1663 switch (desc->nr_channels) {
1664 case 1:
1665 return V_008F0C_BUF_DATA_FORMAT_16;
1666 case 2:
1667 return V_008F0C_BUF_DATA_FORMAT_16_16;
1668 case 3:
1669 case 4:
1670 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1671 }
1672 break;
1673 case 32:
1674 /* From the Southern Islands ISA documentation about MTBUF:
1675 * 'Memory reads of data in memory that is 32 or 64 bits do not
1676 * undergo any format conversion.'
1677 */
1678 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1679 !desc->channel[first_non_void].pure_integer)
1680 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1681
1682 switch (desc->nr_channels) {
1683 case 1:
1684 return V_008F0C_BUF_DATA_FORMAT_32;
1685 case 2:
1686 return V_008F0C_BUF_DATA_FORMAT_32_32;
1687 case 3:
1688 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1689 case 4:
1690 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1691 }
1692 break;
1693 }
1694
1695 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1696 }
1697
1698 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1699 const struct util_format_description *desc,
1700 int first_non_void)
1701 {
1702 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1703 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1704
1705 assert(first_non_void >= 0);
1706
1707 switch (desc->channel[first_non_void].type) {
1708 case UTIL_FORMAT_TYPE_SIGNED:
1709 if (desc->channel[first_non_void].normalized)
1710 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1711 else if (desc->channel[first_non_void].pure_integer)
1712 return V_008F0C_BUF_NUM_FORMAT_SINT;
1713 else
1714 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1715 break;
1716 case UTIL_FORMAT_TYPE_UNSIGNED:
1717 if (desc->channel[first_non_void].normalized)
1718 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1719 else if (desc->channel[first_non_void].pure_integer)
1720 return V_008F0C_BUF_NUM_FORMAT_UINT;
1721 else
1722 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1723 break;
1724 case UTIL_FORMAT_TYPE_FLOAT:
1725 default:
1726 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1727 }
1728 }
1729
1730 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1731 {
1732 const struct util_format_description *desc;
1733 int first_non_void;
1734 unsigned data_format;
1735
1736 desc = util_format_description(format);
1737 first_non_void = util_format_get_first_non_void_channel(format);
1738 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1739 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1740 }
1741
1742 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1743 {
1744 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1745 r600_translate_colorswap(format, FALSE) != ~0U;
1746 }
1747
1748 static bool si_is_zs_format_supported(enum pipe_format format)
1749 {
1750 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1751 }
1752
1753 boolean si_is_format_supported(struct pipe_screen *screen,
1754 enum pipe_format format,
1755 enum pipe_texture_target target,
1756 unsigned sample_count,
1757 unsigned usage)
1758 {
1759 unsigned retval = 0;
1760
1761 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1762 R600_ERR("r600: unsupported texture type %d\n", target);
1763 return FALSE;
1764 }
1765
1766 if (!util_format_is_supported(format, usage))
1767 return FALSE;
1768
1769 if (sample_count > 1) {
1770 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1771 return FALSE;
1772
1773 switch (sample_count) {
1774 case 2:
1775 case 4:
1776 case 8:
1777 break;
1778 case 16:
1779 if (format == PIPE_FORMAT_NONE)
1780 return TRUE;
1781 else
1782 return FALSE;
1783 default:
1784 return FALSE;
1785 }
1786 }
1787
1788 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1789 if (target == PIPE_BUFFER) {
1790 if (si_is_vertex_format_supported(screen, format))
1791 retval |= PIPE_BIND_SAMPLER_VIEW;
1792 } else {
1793 if (si_is_sampler_format_supported(screen, format))
1794 retval |= PIPE_BIND_SAMPLER_VIEW;
1795 }
1796 }
1797
1798 if ((usage & (PIPE_BIND_RENDER_TARGET |
1799 PIPE_BIND_DISPLAY_TARGET |
1800 PIPE_BIND_SCANOUT |
1801 PIPE_BIND_SHARED |
1802 PIPE_BIND_BLENDABLE)) &&
1803 si_is_colorbuffer_format_supported(format)) {
1804 retval |= usage &
1805 (PIPE_BIND_RENDER_TARGET |
1806 PIPE_BIND_DISPLAY_TARGET |
1807 PIPE_BIND_SCANOUT |
1808 PIPE_BIND_SHARED);
1809 if (!util_format_is_pure_integer(format) &&
1810 !util_format_is_depth_or_stencil(format))
1811 retval |= usage & PIPE_BIND_BLENDABLE;
1812 }
1813
1814 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1815 si_is_zs_format_supported(format)) {
1816 retval |= PIPE_BIND_DEPTH_STENCIL;
1817 }
1818
1819 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1820 si_is_vertex_format_supported(screen, format)) {
1821 retval |= PIPE_BIND_VERTEX_BUFFER;
1822 }
1823
1824 if (usage & PIPE_BIND_TRANSFER_READ)
1825 retval |= PIPE_BIND_TRANSFER_READ;
1826 if (usage & PIPE_BIND_TRANSFER_WRITE)
1827 retval |= PIPE_BIND_TRANSFER_WRITE;
1828
1829 if ((usage & PIPE_BIND_LINEAR) &&
1830 !util_format_is_compressed(format) &&
1831 !(usage & PIPE_BIND_DEPTH_STENCIL))
1832 retval |= PIPE_BIND_LINEAR;
1833
1834 return retval == usage;
1835 }
1836
1837 static unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level,
1838 bool stencil)
1839 {
1840 unsigned tile_mode_index = 0;
1841
1842 if (stencil) {
1843 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1844 } else {
1845 tile_mode_index = rtex->surface.tiling_index[level];
1846 }
1847 return tile_mode_index;
1848 }
1849
1850 /*
1851 * framebuffer handling
1852 */
1853
1854 static void si_choose_spi_color_formats(struct r600_surface *surf,
1855 unsigned format, unsigned swap,
1856 unsigned ntype, bool is_depth)
1857 {
1858 /* Alpha is needed for alpha-to-coverage.
1859 * Blending may be with or without alpha.
1860 */
1861 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1862 unsigned alpha = 0; /* exports alpha, but may not support blending */
1863 unsigned blend = 0; /* supports blending, but may not export alpha */
1864 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1865
1866 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1867 * Other chips have multiple choices, though they are not necessarily better.
1868 */
1869 switch (format) {
1870 case V_028C70_COLOR_5_6_5:
1871 case V_028C70_COLOR_1_5_5_5:
1872 case V_028C70_COLOR_5_5_5_1:
1873 case V_028C70_COLOR_4_4_4_4:
1874 case V_028C70_COLOR_10_11_11:
1875 case V_028C70_COLOR_11_11_10:
1876 case V_028C70_COLOR_8:
1877 case V_028C70_COLOR_8_8:
1878 case V_028C70_COLOR_8_8_8_8:
1879 case V_028C70_COLOR_10_10_10_2:
1880 case V_028C70_COLOR_2_10_10_10:
1881 if (ntype == V_028C70_NUMBER_UINT)
1882 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1883 else if (ntype == V_028C70_NUMBER_SINT)
1884 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1885 else
1886 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1887 break;
1888
1889 case V_028C70_COLOR_16:
1890 case V_028C70_COLOR_16_16:
1891 case V_028C70_COLOR_16_16_16_16:
1892 if (ntype == V_028C70_NUMBER_UNORM ||
1893 ntype == V_028C70_NUMBER_SNORM) {
1894 /* UNORM16 and SNORM16 don't support blending */
1895 if (ntype == V_028C70_NUMBER_UNORM)
1896 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1897 else
1898 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1899
1900 /* Use 32 bits per channel for blending. */
1901 if (format == V_028C70_COLOR_16) {
1902 if (swap == V_028C70_SWAP_STD) { /* R */
1903 blend = V_028714_SPI_SHADER_32_R;
1904 blend_alpha = V_028714_SPI_SHADER_32_AR;
1905 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1906 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1907 else
1908 assert(0);
1909 } else if (format == V_028C70_COLOR_16_16) {
1910 if (swap == V_028C70_SWAP_STD) { /* RG */
1911 blend = V_028714_SPI_SHADER_32_GR;
1912 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1913 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1914 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1915 else
1916 assert(0);
1917 } else /* 16_16_16_16 */
1918 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1919 } else if (ntype == V_028C70_NUMBER_UINT)
1920 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1921 else if (ntype == V_028C70_NUMBER_SINT)
1922 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1923 else if (ntype == V_028C70_NUMBER_FLOAT)
1924 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1925 else
1926 assert(0);
1927 break;
1928
1929 case V_028C70_COLOR_32:
1930 if (swap == V_028C70_SWAP_STD) { /* R */
1931 blend = normal = V_028714_SPI_SHADER_32_R;
1932 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
1933 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1934 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1935 else
1936 assert(0);
1937 break;
1938
1939 case V_028C70_COLOR_32_32:
1940 if (swap == V_028C70_SWAP_STD) { /* RG */
1941 blend = normal = V_028714_SPI_SHADER_32_GR;
1942 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
1943 } else if (swap == V_028C70_SWAP_ALT) /* RA */
1944 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
1945 else
1946 assert(0);
1947 break;
1948
1949 case V_028C70_COLOR_32_32_32_32:
1950 case V_028C70_COLOR_8_24:
1951 case V_028C70_COLOR_24_8:
1952 case V_028C70_COLOR_X24_8_32_FLOAT:
1953 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1954 break;
1955
1956 default:
1957 assert(0);
1958 return;
1959 }
1960
1961 /* The DB->CB copy needs 32_ABGR. */
1962 if (is_depth)
1963 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
1964
1965 surf->spi_shader_col_format = normal;
1966 surf->spi_shader_col_format_alpha = alpha;
1967 surf->spi_shader_col_format_blend = blend;
1968 surf->spi_shader_col_format_blend_alpha = blend_alpha;
1969 }
1970
1971 static void si_initialize_color_surface(struct si_context *sctx,
1972 struct r600_surface *surf)
1973 {
1974 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1975 unsigned level = surf->base.u.tex.level;
1976 uint64_t offset = rtex->surface.level[level].offset;
1977 unsigned pitch, slice;
1978 unsigned color_info, color_attrib, color_pitch, color_view;
1979 unsigned tile_mode_index;
1980 unsigned format, swap, ntype, endian;
1981 const struct util_format_description *desc;
1982 int i;
1983 unsigned blend_clamp = 0, blend_bypass = 0;
1984
1985 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1986 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1987
1988 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1989 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1990 if (slice) {
1991 slice = slice - 1;
1992 }
1993
1994 tile_mode_index = si_tile_mode_index(rtex, level, false);
1995
1996 desc = util_format_description(surf->base.format);
1997 for (i = 0; i < 4; i++) {
1998 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1999 break;
2000 }
2001 }
2002 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2003 ntype = V_028C70_NUMBER_FLOAT;
2004 } else {
2005 ntype = V_028C70_NUMBER_UNORM;
2006 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2007 ntype = V_028C70_NUMBER_SRGB;
2008 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2009 if (desc->channel[i].pure_integer) {
2010 ntype = V_028C70_NUMBER_SINT;
2011 } else {
2012 assert(desc->channel[i].normalized);
2013 ntype = V_028C70_NUMBER_SNORM;
2014 }
2015 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2016 if (desc->channel[i].pure_integer) {
2017 ntype = V_028C70_NUMBER_UINT;
2018 } else {
2019 assert(desc->channel[i].normalized);
2020 ntype = V_028C70_NUMBER_UNORM;
2021 }
2022 }
2023 }
2024
2025 format = si_translate_colorformat(surf->base.format);
2026 if (format == V_028C70_COLOR_INVALID) {
2027 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2028 }
2029 assert(format != V_028C70_COLOR_INVALID);
2030 swap = r600_translate_colorswap(surf->base.format, FALSE);
2031 endian = si_colorformat_endian_swap(format);
2032
2033 /* blend clamp should be set for all NORM/SRGB types */
2034 if (ntype == V_028C70_NUMBER_UNORM ||
2035 ntype == V_028C70_NUMBER_SNORM ||
2036 ntype == V_028C70_NUMBER_SRGB)
2037 blend_clamp = 1;
2038
2039 /* set blend bypass according to docs if SINT/UINT or
2040 8/24 COLOR variants */
2041 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2042 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2043 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2044 blend_clamp = 0;
2045 blend_bypass = 1;
2046 }
2047
2048 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2049 (format == V_028C70_COLOR_8 ||
2050 format == V_028C70_COLOR_8_8 ||
2051 format == V_028C70_COLOR_8_8_8_8))
2052 surf->color_is_int8 = true;
2053
2054 color_info = S_028C70_FORMAT(format) |
2055 S_028C70_COMP_SWAP(swap) |
2056 S_028C70_BLEND_CLAMP(blend_clamp) |
2057 S_028C70_BLEND_BYPASS(blend_bypass) |
2058 S_028C70_NUMBER_TYPE(ntype) |
2059 S_028C70_ENDIAN(endian);
2060
2061 color_pitch = S_028C64_TILE_MAX(pitch);
2062
2063 /* Intensity is implemented as Red, so treat it that way. */
2064 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
2065 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2066 util_format_is_intensity(surf->base.format));
2067
2068 if (rtex->resource.b.b.nr_samples > 1) {
2069 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2070
2071 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2072 S_028C74_NUM_FRAGMENTS(log_samples);
2073
2074 if (rtex->fmask.size) {
2075 color_info |= S_028C70_COMPRESSION(1);
2076 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2077
2078 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
2079
2080 if (sctx->b.chip_class == SI) {
2081 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2082 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2083 }
2084 if (sctx->b.chip_class >= CIK) {
2085 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch_in_pixels / 8 - 1);
2086 }
2087 }
2088 }
2089
2090 offset += rtex->resource.gpu_address;
2091
2092 surf->cb_color_base = offset >> 8;
2093 surf->cb_color_pitch = color_pitch;
2094 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
2095 surf->cb_color_view = color_view;
2096 surf->cb_color_info = color_info;
2097 surf->cb_color_attrib = color_attrib;
2098
2099 if (sctx->b.chip_class >= VI && rtex->dcc_offset) {
2100 unsigned max_uncompressed_block_size = 2;
2101
2102 if (rtex->surface.nsamples > 1) {
2103 if (rtex->surface.bpe == 1)
2104 max_uncompressed_block_size = 0;
2105 else if (rtex->surface.bpe == 2)
2106 max_uncompressed_block_size = 1;
2107 }
2108
2109 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2110 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2111 surf->cb_dcc_base = (rtex->resource.gpu_address +
2112 rtex->dcc_offset +
2113 rtex->surface.level[level].dcc_offset) >> 8;
2114 }
2115
2116 if (rtex->fmask.size) {
2117 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
2118 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
2119 } else {
2120 /* This must be set for fast clear to work without FMASK. */
2121 surf->cb_color_fmask = surf->cb_color_base;
2122 surf->cb_color_fmask_slice = surf->cb_color_slice;
2123 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2124
2125 if (sctx->b.chip_class == SI) {
2126 unsigned bankh = util_logbase2(rtex->surface.bankh);
2127 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2128 }
2129
2130 if (sctx->b.chip_class >= CIK) {
2131 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
2132 }
2133 }
2134
2135 /* Determine pixel shader export format */
2136 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2137
2138 surf->color_initialized = true;
2139 }
2140
2141 static void si_init_depth_surface(struct si_context *sctx,
2142 struct r600_surface *surf)
2143 {
2144 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2145 unsigned level = surf->base.u.tex.level;
2146 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2147 unsigned format;
2148 uint32_t z_info, s_info, db_depth_info;
2149 uint64_t z_offs, s_offs;
2150 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
2151
2152 switch (sctx->framebuffer.state.zsbuf->texture->format) {
2153 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2154 case PIPE_FORMAT_X8Z24_UNORM:
2155 case PIPE_FORMAT_Z24X8_UNORM:
2156 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
2157 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2158 break;
2159 case PIPE_FORMAT_Z32_FLOAT:
2160 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2161 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2162 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2163 break;
2164 case PIPE_FORMAT_Z16_UNORM:
2165 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2166 break;
2167 default:
2168 assert(0);
2169 }
2170
2171 format = si_translate_dbformat(rtex->resource.b.b.format);
2172
2173 if (format == V_028040_Z_INVALID) {
2174 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2175 }
2176 assert(format != V_028040_Z_INVALID);
2177
2178 s_offs = z_offs = rtex->resource.gpu_address;
2179 z_offs += rtex->surface.level[level].offset;
2180 s_offs += rtex->surface.stencil_level[level].offset;
2181
2182 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2183
2184 z_info = S_028040_FORMAT(format);
2185 if (rtex->resource.b.b.nr_samples > 1) {
2186 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2187 }
2188
2189 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2190 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2191 else
2192 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2193
2194 if (sctx->b.chip_class >= CIK) {
2195 struct radeon_info *info = &sctx->screen->b.info;
2196 unsigned index = rtex->surface.tiling_index[level];
2197 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2198 unsigned macro_index = rtex->surface.macro_tile_index;
2199 unsigned tile_mode = info->si_tile_mode_array[index];
2200 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2201 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2202
2203 db_depth_info |=
2204 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2205 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2206 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2207 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2208 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2209 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2210 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2211 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2212 } else {
2213 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2214 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2215 tile_mode_index = si_tile_mode_index(rtex, level, true);
2216 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2217 }
2218
2219 /* HiZ aka depth buffer htile */
2220 /* use htile only for first level */
2221 if (rtex->htile_buffer && !level) {
2222 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2223 S_028040_ALLOW_EXPCLEAR(1);
2224
2225 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2226 /* Workaround: For a not yet understood reason, the
2227 * combination of MSAA, fast stencil clear and stencil
2228 * decompress messes with subsequent stencil buffer
2229 * uses. Problem was reproduced on Verde, Bonaire,
2230 * Tonga, and Carrizo.
2231 *
2232 * Disabling EXPCLEAR works around the problem.
2233 *
2234 * Check piglit's arb_texture_multisample-stencil-clear
2235 * test if you want to try changing this.
2236 */
2237 if (rtex->resource.b.b.nr_samples <= 1)
2238 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2239 } else
2240 /* Use all of the htile_buffer for depth if there's no stencil. */
2241 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2242
2243 uint64_t va = rtex->htile_buffer->gpu_address;
2244 db_htile_data_base = va >> 8;
2245 db_htile_surface = S_028ABC_FULL_CACHE(1);
2246 } else {
2247 db_htile_data_base = 0;
2248 db_htile_surface = 0;
2249 }
2250
2251 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2252
2253 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2254 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2255 surf->db_htile_data_base = db_htile_data_base;
2256 surf->db_depth_info = db_depth_info;
2257 surf->db_z_info = z_info;
2258 surf->db_stencil_info = s_info;
2259 surf->db_depth_base = z_offs >> 8;
2260 surf->db_stencil_base = s_offs >> 8;
2261 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2262 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2263 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2264 levelinfo->nblk_y) / 64 - 1);
2265 surf->db_htile_surface = db_htile_surface;
2266 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2267
2268 surf->depth_initialized = true;
2269 }
2270
2271 void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2272 {
2273 for (int i = 0; i < state->nr_cbufs; ++i) {
2274 struct r600_surface *surf = NULL;
2275 struct r600_texture *rtex;
2276
2277 if (!state->cbufs[i])
2278 continue;
2279 surf = (struct r600_surface*)state->cbufs[i];
2280 rtex = (struct r600_texture*)surf->base.texture;
2281
2282 p_atomic_dec(&rtex->framebuffers_bound);
2283 }
2284 }
2285
2286 static void si_set_framebuffer_state(struct pipe_context *ctx,
2287 const struct pipe_framebuffer_state *state)
2288 {
2289 struct si_context *sctx = (struct si_context *)ctx;
2290 struct pipe_constant_buffer constbuf = {0};
2291 struct r600_surface *surf = NULL;
2292 struct r600_texture *rtex;
2293 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2294 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2295 int i;
2296
2297 /* Only flush TC when changing the framebuffer state, because
2298 * the only client not using TC that can change textures is
2299 * the framebuffer.
2300 *
2301 * Flush all CB and DB caches here because all buffers can be used
2302 * for write by both TC (with shader image stores) and CB/DB.
2303 */
2304 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2305 SI_CONTEXT_INV_GLOBAL_L2 |
2306 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER |
2307 SI_CONTEXT_CS_PARTIAL_FLUSH;
2308
2309 /* Take the maximum of the old and new count. If the new count is lower,
2310 * dirtying is needed to disable the unbound colorbuffers.
2311 */
2312 sctx->framebuffer.dirty_cbufs |=
2313 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2314 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2315
2316 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2317 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2318
2319 sctx->framebuffer.spi_shader_col_format = 0;
2320 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2321 sctx->framebuffer.spi_shader_col_format_blend = 0;
2322 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2323 sctx->framebuffer.color_is_int8 = 0;
2324
2325 sctx->framebuffer.compressed_cb_mask = 0;
2326 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2327 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2328 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2329 util_format_is_pure_integer(state->cbufs[0]->format);
2330
2331 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2332 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2333
2334 for (i = 0; i < state->nr_cbufs; i++) {
2335 if (!state->cbufs[i])
2336 continue;
2337
2338 surf = (struct r600_surface*)state->cbufs[i];
2339 rtex = (struct r600_texture*)surf->base.texture;
2340
2341 if (!surf->color_initialized) {
2342 si_initialize_color_surface(sctx, surf);
2343 }
2344
2345 sctx->framebuffer.spi_shader_col_format |=
2346 surf->spi_shader_col_format << (i * 4);
2347 sctx->framebuffer.spi_shader_col_format_alpha |=
2348 surf->spi_shader_col_format_alpha << (i * 4);
2349 sctx->framebuffer.spi_shader_col_format_blend |=
2350 surf->spi_shader_col_format_blend << (i * 4);
2351 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2352 surf->spi_shader_col_format_blend_alpha << (i * 4);
2353
2354 if (surf->color_is_int8)
2355 sctx->framebuffer.color_is_int8 |= 1 << i;
2356
2357 if (rtex->fmask.size && rtex->cmask.size) {
2358 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2359 }
2360 r600_context_add_resource_size(ctx, surf->base.texture);
2361
2362 p_atomic_inc(&rtex->framebuffers_bound);
2363 }
2364 /* Set the second SPI format for possible dual-src blending. */
2365 if (i == 1 && surf) {
2366 sctx->framebuffer.spi_shader_col_format |=
2367 surf->spi_shader_col_format << (i * 4);
2368 sctx->framebuffer.spi_shader_col_format_alpha |=
2369 surf->spi_shader_col_format_alpha << (i * 4);
2370 sctx->framebuffer.spi_shader_col_format_blend |=
2371 surf->spi_shader_col_format_blend << (i * 4);
2372 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2373 surf->spi_shader_col_format_blend_alpha << (i * 4);
2374 }
2375
2376 if (state->zsbuf) {
2377 surf = (struct r600_surface*)state->zsbuf;
2378
2379 if (!surf->depth_initialized) {
2380 si_init_depth_surface(sctx, surf);
2381 }
2382 r600_context_add_resource_size(ctx, surf->base.texture);
2383 }
2384
2385 si_update_poly_offset_state(sctx);
2386 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2387 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2388
2389 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2390 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2391 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2392
2393 /* Set sample locations as fragment shader constants. */
2394 switch (sctx->framebuffer.nr_samples) {
2395 case 1:
2396 constbuf.user_buffer = sctx->b.sample_locations_1x;
2397 break;
2398 case 2:
2399 constbuf.user_buffer = sctx->b.sample_locations_2x;
2400 break;
2401 case 4:
2402 constbuf.user_buffer = sctx->b.sample_locations_4x;
2403 break;
2404 case 8:
2405 constbuf.user_buffer = sctx->b.sample_locations_8x;
2406 break;
2407 case 16:
2408 constbuf.user_buffer = sctx->b.sample_locations_16x;
2409 break;
2410 default:
2411 R600_ERR("Requested an invalid number of samples %i.\n",
2412 sctx->framebuffer.nr_samples);
2413 assert(0);
2414 }
2415 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2416 si_set_constant_buffer(sctx, &sctx->rw_buffers,
2417 SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2418
2419 /* Smoothing (only possible with nr_samples == 1) uses the same
2420 * sample locations as the MSAA it simulates.
2421 *
2422 * Therefore, don't update the sample locations when
2423 * transitioning from no AA to smoothing-equivalent AA, and
2424 * vice versa.
2425 */
2426 if ((sctx->framebuffer.nr_samples != 1 ||
2427 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2428 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2429 old_nr_samples != 1))
2430 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs);
2431 }
2432
2433 sctx->need_check_render_feedback = true;
2434 }
2435
2436 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2437 {
2438 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2439 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2440 unsigned i, nr_cbufs = state->nr_cbufs;
2441 struct r600_texture *tex = NULL;
2442 struct r600_surface *cb = NULL;
2443
2444 /* Colorbuffers. */
2445 for (i = 0; i < nr_cbufs; i++) {
2446 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2447 continue;
2448
2449 cb = (struct r600_surface*)state->cbufs[i];
2450 if (!cb) {
2451 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2452 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2453 continue;
2454 }
2455
2456 tex = (struct r600_texture *)cb->base.texture;
2457 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2458 &tex->resource, RADEON_USAGE_READWRITE,
2459 tex->surface.nsamples > 1 ?
2460 RADEON_PRIO_COLOR_BUFFER_MSAA :
2461 RADEON_PRIO_COLOR_BUFFER);
2462
2463 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2464 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2465 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2466 RADEON_PRIO_CMASK);
2467 }
2468
2469 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2470 sctx->b.chip_class >= VI ? 14 : 13);
2471 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2472 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2473 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2474 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2475 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2476 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2477 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2478 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2479 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2480 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2481 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2482 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2483 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2484
2485 if (sctx->b.chip_class >= VI)
2486 radeon_emit(cs, cb->cb_dcc_base); /* R_028C94_CB_COLOR0_DCC_BASE */
2487 }
2488 /* set CB_COLOR1_INFO for possible dual-src blending */
2489 if (i == 1 && state->cbufs[0] &&
2490 sctx->framebuffer.dirty_cbufs & (1 << 0)) {
2491 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2492 cb->cb_color_info | tex->cb_color_info);
2493 i++;
2494 }
2495 for (; i < 8 ; i++)
2496 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2497 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2498
2499 /* ZS buffer. */
2500 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2501 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2502 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2503
2504 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2505 &rtex->resource, RADEON_USAGE_READWRITE,
2506 zb->base.texture->nr_samples > 1 ?
2507 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2508 RADEON_PRIO_DEPTH_BUFFER);
2509
2510 if (zb->db_htile_data_base) {
2511 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2512 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2513 RADEON_PRIO_HTILE);
2514 }
2515
2516 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2517 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2518
2519 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2520 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2521 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2522 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2523 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2524 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2525 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2526 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2527 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2528 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2529 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2530
2531 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2532 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2533 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2534
2535 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2536 radeon_set_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2537 zb->pa_su_poly_offset_db_fmt_cntl);
2538 } else if (sctx->framebuffer.dirty_zsbuf) {
2539 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2540 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2541 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2542 }
2543
2544 /* Framebuffer dimensions. */
2545 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2546 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2547 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2548
2549 sctx->framebuffer.dirty_cbufs = 0;
2550 sctx->framebuffer.dirty_zsbuf = false;
2551 }
2552
2553 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2554 struct r600_atom *atom)
2555 {
2556 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2557 unsigned nr_samples = sctx->framebuffer.nr_samples;
2558
2559 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2560 SI_NUM_SMOOTH_AA_SAMPLES);
2561 }
2562
2563 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2564 {
2565 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2566
2567 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2568 sctx->ps_iter_samples,
2569 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2570 }
2571
2572
2573 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2574 {
2575 struct si_context *sctx = (struct si_context *)ctx;
2576
2577 if (sctx->ps_iter_samples == min_samples)
2578 return;
2579
2580 sctx->ps_iter_samples = min_samples;
2581
2582 if (sctx->framebuffer.nr_samples > 1)
2583 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2584 }
2585
2586 /*
2587 * Samplers
2588 */
2589
2590 /**
2591 * Build the sampler view descriptor for a buffer texture.
2592 * @param state 256-bit descriptor; only the high 128 bits are filled in
2593 */
2594 void
2595 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2596 enum pipe_format format,
2597 unsigned first_element, unsigned last_element,
2598 uint32_t *state)
2599 {
2600 const struct util_format_description *desc;
2601 int first_non_void;
2602 uint64_t va;
2603 unsigned stride;
2604 unsigned num_records;
2605 unsigned num_format, data_format;
2606
2607 desc = util_format_description(format);
2608 first_non_void = util_format_get_first_non_void_channel(format);
2609 stride = desc->block.bits / 8;
2610 va = buf->gpu_address + first_element * stride;
2611 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2612 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2613
2614 num_records = last_element + 1 - first_element;
2615 num_records = MIN2(num_records, buf->b.b.width0 / stride);
2616
2617 if (screen->b.chip_class >= VI)
2618 num_records *= stride;
2619
2620 state[4] = va;
2621 state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2622 S_008F04_STRIDE(stride);
2623 state[6] = num_records;
2624 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2625 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2626 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2627 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2628 S_008F0C_NUM_FORMAT(num_format) |
2629 S_008F0C_DATA_FORMAT(data_format);
2630 }
2631
2632 /**
2633 * Build the sampler view descriptor for a texture.
2634 */
2635 void
2636 si_make_texture_descriptor(struct si_screen *screen,
2637 struct r600_texture *tex,
2638 bool sampler,
2639 enum pipe_texture_target target,
2640 enum pipe_format pipe_format,
2641 const unsigned char state_swizzle[4],
2642 unsigned base_level, unsigned first_level, unsigned last_level,
2643 unsigned first_layer, unsigned last_layer,
2644 unsigned width, unsigned height, unsigned depth,
2645 uint32_t *state,
2646 uint32_t *fmask_state)
2647 {
2648 struct pipe_resource *res = &tex->resource.b.b;
2649 const struct radeon_surf_level *surflevel = tex->surface.level;
2650 const struct util_format_description *desc;
2651 unsigned char swizzle[4];
2652 int first_non_void;
2653 unsigned num_format, data_format, type;
2654 uint32_t pitch;
2655 uint64_t va;
2656
2657 /* Texturing with separate depth and stencil. */
2658 if (tex->is_depth && !tex->is_flushing_texture) {
2659 switch (pipe_format) {
2660 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2661 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2662 break;
2663 case PIPE_FORMAT_X8Z24_UNORM:
2664 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2665 /* Z24 is always stored like this. */
2666 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2667 break;
2668 case PIPE_FORMAT_X24S8_UINT:
2669 case PIPE_FORMAT_S8X24_UINT:
2670 case PIPE_FORMAT_X32_S8X24_UINT:
2671 pipe_format = PIPE_FORMAT_S8_UINT;
2672 surflevel = tex->surface.stencil_level;
2673 break;
2674 default:;
2675 }
2676 }
2677
2678 desc = util_format_description(pipe_format);
2679
2680 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2681 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2682 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2683
2684 switch (pipe_format) {
2685 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2686 case PIPE_FORMAT_X24S8_UINT:
2687 case PIPE_FORMAT_X32_S8X24_UINT:
2688 case PIPE_FORMAT_X8Z24_UNORM:
2689 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2690 break;
2691 default:
2692 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2693 }
2694 } else {
2695 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2696 }
2697
2698 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2699
2700 switch (pipe_format) {
2701 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2702 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2703 break;
2704 default:
2705 if (first_non_void < 0) {
2706 if (util_format_is_compressed(pipe_format)) {
2707 switch (pipe_format) {
2708 case PIPE_FORMAT_DXT1_SRGB:
2709 case PIPE_FORMAT_DXT1_SRGBA:
2710 case PIPE_FORMAT_DXT3_SRGBA:
2711 case PIPE_FORMAT_DXT5_SRGBA:
2712 case PIPE_FORMAT_BPTC_SRGBA:
2713 case PIPE_FORMAT_ETC2_SRGB8:
2714 case PIPE_FORMAT_ETC2_SRGB8A1:
2715 case PIPE_FORMAT_ETC2_SRGBA8:
2716 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2717 break;
2718 case PIPE_FORMAT_RGTC1_SNORM:
2719 case PIPE_FORMAT_LATC1_SNORM:
2720 case PIPE_FORMAT_RGTC2_SNORM:
2721 case PIPE_FORMAT_LATC2_SNORM:
2722 case PIPE_FORMAT_ETC2_R11_SNORM:
2723 case PIPE_FORMAT_ETC2_RG11_SNORM:
2724 /* implies float, so use SNORM/UNORM to determine
2725 whether data is signed or not */
2726 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2727 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2728 break;
2729 default:
2730 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2731 break;
2732 }
2733 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2734 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2735 } else {
2736 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2737 }
2738 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2739 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2740 } else {
2741 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2742
2743 switch (desc->channel[first_non_void].type) {
2744 case UTIL_FORMAT_TYPE_FLOAT:
2745 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2746 break;
2747 case UTIL_FORMAT_TYPE_SIGNED:
2748 if (desc->channel[first_non_void].normalized)
2749 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2750 else if (desc->channel[first_non_void].pure_integer)
2751 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2752 else
2753 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2754 break;
2755 case UTIL_FORMAT_TYPE_UNSIGNED:
2756 if (desc->channel[first_non_void].normalized)
2757 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2758 else if (desc->channel[first_non_void].pure_integer)
2759 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2760 else
2761 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2762 }
2763 }
2764 }
2765
2766 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2767 if (data_format == ~0) {
2768 data_format = 0;
2769 }
2770
2771 if (!sampler &&
2772 (res->target == PIPE_TEXTURE_CUBE ||
2773 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2774 res->target == PIPE_TEXTURE_3D)) {
2775 /* For the purpose of shader images, treat cube maps and 3D
2776 * textures as 2D arrays. For 3D textures, the address
2777 * calculations for mipmaps are different, so we rely on the
2778 * caller to effectively disable mipmaps.
2779 */
2780 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2781
2782 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2783 } else {
2784 type = si_tex_dim(res->target, target, res->nr_samples);
2785 }
2786
2787 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2788 height = 1;
2789 depth = res->array_size;
2790 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2791 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2792 if (sampler || res->target != PIPE_TEXTURE_3D)
2793 depth = res->array_size;
2794 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2795 depth = res->array_size / 6;
2796
2797 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2798 va = tex->resource.gpu_address + surflevel[base_level].offset;
2799
2800 state[0] = va >> 8;
2801 state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2802 S_008F14_DATA_FORMAT(data_format) |
2803 S_008F14_NUM_FORMAT(num_format));
2804 state[2] = (S_008F18_WIDTH(width - 1) |
2805 S_008F18_HEIGHT(height - 1));
2806 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2807 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2808 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2809 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2810 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2811 0 : first_level) |
2812 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2813 util_logbase2(res->nr_samples) :
2814 last_level) |
2815 S_008F1C_TILING_INDEX(si_tile_mode_index(tex, base_level, false)) |
2816 S_008F1C_POW2_PAD(res->last_level > 0) |
2817 S_008F1C_TYPE(type));
2818 state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2819 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2820 S_008F24_LAST_ARRAY(last_layer));
2821
2822 if (tex->dcc_offset) {
2823 unsigned swap = r600_translate_colorswap(pipe_format, FALSE);
2824
2825 state[6] = S_008F28_COMPRESSION_EN(1) | S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2826 state[7] = (tex->resource.gpu_address +
2827 tex->dcc_offset +
2828 surflevel[base_level].dcc_offset) >> 8;
2829 } else {
2830 state[6] = 0;
2831 state[7] = 0;
2832
2833 /* The last dword is unused by hw. The shader uses it to clear
2834 * bits in the first dword of sampler state.
2835 */
2836 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2837 if (first_level == last_level)
2838 state[7] = C_008F30_MAX_ANISO_RATIO;
2839 else
2840 state[7] = 0xffffffff;
2841 }
2842 }
2843
2844 /* Initialize the sampler view for FMASK. */
2845 if (tex->fmask.size) {
2846 uint32_t fmask_format;
2847
2848 va = tex->resource.gpu_address + tex->fmask.offset;
2849
2850 switch (res->nr_samples) {
2851 case 2:
2852 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2853 break;
2854 case 4:
2855 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2856 break;
2857 case 8:
2858 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2859 break;
2860 default:
2861 assert(0);
2862 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2863 }
2864
2865 fmask_state[0] = va >> 8;
2866 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2867 S_008F14_DATA_FORMAT(fmask_format) |
2868 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2869 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2870 S_008F18_HEIGHT(height - 1);
2871 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2872 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2873 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2874 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2875 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
2876 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
2877 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2878 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
2879 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
2880 S_008F24_LAST_ARRAY(last_layer);
2881 fmask_state[6] = 0;
2882 fmask_state[7] = 0;
2883 }
2884 }
2885
2886 /**
2887 * Create a sampler view.
2888 *
2889 * @param ctx context
2890 * @param texture texture
2891 * @param state sampler view template
2892 * @param width0 width0 override (for compressed textures as int)
2893 * @param height0 height0 override (for compressed textures as int)
2894 * @param force_level set the base address to the level (for compressed textures)
2895 */
2896 struct pipe_sampler_view *
2897 si_create_sampler_view_custom(struct pipe_context *ctx,
2898 struct pipe_resource *texture,
2899 const struct pipe_sampler_view *state,
2900 unsigned width0, unsigned height0,
2901 unsigned force_level)
2902 {
2903 struct si_context *sctx = (struct si_context*)ctx;
2904 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2905 struct r600_texture *tmp = (struct r600_texture*)texture;
2906 unsigned base_level, first_level, last_level;
2907 unsigned char state_swizzle[4];
2908 unsigned height, depth, width;
2909 unsigned last_layer = state->u.tex.last_layer;
2910
2911 if (!view)
2912 return NULL;
2913
2914 /* initialize base object */
2915 view->base = *state;
2916 view->base.texture = NULL;
2917 view->base.reference.count = 1;
2918 view->base.context = ctx;
2919
2920 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2921 if (!texture) {
2922 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2923 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2924 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2925 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2926 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2927 return &view->base;
2928 }
2929
2930 pipe_resource_reference(&view->base.texture, texture);
2931
2932 if (state->format == PIPE_FORMAT_X24S8_UINT ||
2933 state->format == PIPE_FORMAT_S8X24_UINT ||
2934 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
2935 state->format == PIPE_FORMAT_S8_UINT)
2936 view->is_stencil_sampler = true;
2937
2938 /* Buffer resource. */
2939 if (texture->target == PIPE_BUFFER) {
2940 si_make_buffer_descriptor(sctx->screen,
2941 (struct r600_resource *)texture,
2942 state->format,
2943 state->u.buf.first_element,
2944 state->u.buf.last_element,
2945 view->state);
2946
2947 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2948 return &view->base;
2949 }
2950
2951 state_swizzle[0] = state->swizzle_r;
2952 state_swizzle[1] = state->swizzle_g;
2953 state_swizzle[2] = state->swizzle_b;
2954 state_swizzle[3] = state->swizzle_a;
2955
2956 base_level = 0;
2957 first_level = state->u.tex.first_level;
2958 last_level = state->u.tex.last_level;
2959 width = width0;
2960 height = height0;
2961 depth = texture->depth0;
2962
2963 if (force_level) {
2964 assert(force_level == first_level &&
2965 force_level == last_level);
2966 base_level = force_level;
2967 first_level = 0;
2968 last_level = 0;
2969 width = u_minify(width, force_level);
2970 height = u_minify(height, force_level);
2971 depth = u_minify(depth, force_level);
2972 }
2973
2974 /* This is not needed if state trackers set last_layer correctly. */
2975 if (state->target == PIPE_TEXTURE_1D ||
2976 state->target == PIPE_TEXTURE_2D ||
2977 state->target == PIPE_TEXTURE_RECT ||
2978 state->target == PIPE_TEXTURE_CUBE)
2979 last_layer = state->u.tex.first_layer;
2980
2981 si_make_texture_descriptor(sctx->screen, tmp, true, state->target,
2982 state->format, state_swizzle,
2983 base_level, first_level, last_level,
2984 state->u.tex.first_layer, last_layer,
2985 width, height, depth,
2986 view->state, view->fmask_state);
2987
2988 return &view->base;
2989 }
2990
2991 static struct pipe_sampler_view *
2992 si_create_sampler_view(struct pipe_context *ctx,
2993 struct pipe_resource *texture,
2994 const struct pipe_sampler_view *state)
2995 {
2996 return si_create_sampler_view_custom(ctx, texture, state,
2997 texture ? texture->width0 : 0,
2998 texture ? texture->height0 : 0, 0);
2999 }
3000
3001 static void si_sampler_view_destroy(struct pipe_context *ctx,
3002 struct pipe_sampler_view *state)
3003 {
3004 struct si_sampler_view *view = (struct si_sampler_view *)state;
3005
3006 if (state->texture && state->texture->target == PIPE_BUFFER)
3007 LIST_DELINIT(&view->list);
3008
3009 pipe_resource_reference(&state->texture, NULL);
3010 FREE(view);
3011 }
3012
3013 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3014 {
3015 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3016 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3017 (linear_filter &&
3018 (wrap == PIPE_TEX_WRAP_CLAMP ||
3019 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3020 }
3021
3022 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3023 {
3024 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3025 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3026
3027 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3028 state->border_color.ui[2] || state->border_color.ui[3]) &&
3029 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3030 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3031 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3032 }
3033
3034 static void *si_create_sampler_state(struct pipe_context *ctx,
3035 const struct pipe_sampler_state *state)
3036 {
3037 struct si_context *sctx = (struct si_context *)ctx;
3038 struct r600_common_screen *rscreen = sctx->b.screen;
3039 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3040 unsigned border_color_type, border_color_index = 0;
3041 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3042 : state->max_anisotropy;
3043 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3044
3045 if (!rstate) {
3046 return NULL;
3047 }
3048
3049 if (!sampler_state_needs_border_color(state))
3050 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3051 else if (state->border_color.f[0] == 0 &&
3052 state->border_color.f[1] == 0 &&
3053 state->border_color.f[2] == 0 &&
3054 state->border_color.f[3] == 0)
3055 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3056 else if (state->border_color.f[0] == 0 &&
3057 state->border_color.f[1] == 0 &&
3058 state->border_color.f[2] == 0 &&
3059 state->border_color.f[3] == 1)
3060 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3061 else if (state->border_color.f[0] == 1 &&
3062 state->border_color.f[1] == 1 &&
3063 state->border_color.f[2] == 1 &&
3064 state->border_color.f[3] == 1)
3065 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3066 else {
3067 int i;
3068
3069 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3070
3071 /* Check if the border has been uploaded already. */
3072 for (i = 0; i < sctx->border_color_count; i++)
3073 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3074 sizeof(state->border_color)) == 0)
3075 break;
3076
3077 if (i >= SI_MAX_BORDER_COLORS) {
3078 /* Getting 4096 unique border colors is very unlikely. */
3079 fprintf(stderr, "radeonsi: The border color table is full. "
3080 "Any new border colors will be just black. "
3081 "Please file a bug.\n");
3082 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3083 } else {
3084 if (i == sctx->border_color_count) {
3085 /* Upload a new border color. */
3086 memcpy(&sctx->border_color_table[i], &state->border_color,
3087 sizeof(state->border_color));
3088 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3089 &state->border_color,
3090 sizeof(state->border_color));
3091 sctx->border_color_count++;
3092 }
3093
3094 border_color_index = i;
3095 }
3096 }
3097
3098 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3099 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3100 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3101 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3102 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3103 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3104 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3105 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3106 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3107 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
3108 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3109 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3110 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3111 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3112 S_008F38_MIP_POINT_PRECLAMP(1) |
3113 S_008F38_DISABLE_LSB_CEIL(1) |
3114 S_008F38_FILTER_PREC_FIX(1) |
3115 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3116 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3117 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3118 return rstate;
3119 }
3120
3121 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3122 {
3123 struct si_context *sctx = (struct si_context *)ctx;
3124
3125 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3126 return;
3127
3128 sctx->sample_mask.sample_mask = sample_mask;
3129 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3130 }
3131
3132 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3133 {
3134 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3135 unsigned mask = sctx->sample_mask.sample_mask;
3136
3137 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3138 radeon_emit(cs, mask | (mask << 16));
3139 radeon_emit(cs, mask | (mask << 16));
3140 }
3141
3142 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3143 {
3144 free(state);
3145 }
3146
3147 /*
3148 * Vertex elements & buffers
3149 */
3150
3151 static void *si_create_vertex_elements(struct pipe_context *ctx,
3152 unsigned count,
3153 const struct pipe_vertex_element *elements)
3154 {
3155 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3156 int i;
3157
3158 assert(count <= SI_MAX_ATTRIBS);
3159 if (!v)
3160 return NULL;
3161
3162 v->count = count;
3163 for (i = 0; i < count; ++i) {
3164 const struct util_format_description *desc;
3165 unsigned data_format, num_format;
3166 int first_non_void;
3167
3168 desc = util_format_description(elements[i].src_format);
3169 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3170 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3171 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3172
3173 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3174 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3175 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3176 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3177 S_008F0C_NUM_FORMAT(num_format) |
3178 S_008F0C_DATA_FORMAT(data_format);
3179 v->format_size[i] = desc->block.bits / 8;
3180 }
3181 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3182
3183 return v;
3184 }
3185
3186 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3187 {
3188 struct si_context *sctx = (struct si_context *)ctx;
3189 struct si_vertex_element *v = (struct si_vertex_element*)state;
3190
3191 sctx->vertex_elements = v;
3192 sctx->vertex_buffers_dirty = true;
3193 }
3194
3195 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3196 {
3197 struct si_context *sctx = (struct si_context *)ctx;
3198
3199 if (sctx->vertex_elements == state)
3200 sctx->vertex_elements = NULL;
3201 FREE(state);
3202 }
3203
3204 static void si_set_vertex_buffers(struct pipe_context *ctx,
3205 unsigned start_slot, unsigned count,
3206 const struct pipe_vertex_buffer *buffers)
3207 {
3208 struct si_context *sctx = (struct si_context *)ctx;
3209 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3210 int i;
3211
3212 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3213
3214 if (buffers) {
3215 for (i = 0; i < count; i++) {
3216 const struct pipe_vertex_buffer *src = buffers + i;
3217 struct pipe_vertex_buffer *dsti = dst + i;
3218
3219 pipe_resource_reference(&dsti->buffer, src->buffer);
3220 dsti->buffer_offset = src->buffer_offset;
3221 dsti->stride = src->stride;
3222 r600_context_add_resource_size(ctx, src->buffer);
3223 }
3224 } else {
3225 for (i = 0; i < count; i++) {
3226 pipe_resource_reference(&dst[i].buffer, NULL);
3227 }
3228 }
3229 sctx->vertex_buffers_dirty = true;
3230 }
3231
3232 static void si_set_index_buffer(struct pipe_context *ctx,
3233 const struct pipe_index_buffer *ib)
3234 {
3235 struct si_context *sctx = (struct si_context *)ctx;
3236
3237 if (ib) {
3238 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
3239 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3240 r600_context_add_resource_size(ctx, ib->buffer);
3241 } else {
3242 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3243 }
3244 }
3245
3246 /*
3247 * Misc
3248 */
3249
3250 static void si_set_tess_state(struct pipe_context *ctx,
3251 const float default_outer_level[4],
3252 const float default_inner_level[2])
3253 {
3254 struct si_context *sctx = (struct si_context *)ctx;
3255 struct pipe_constant_buffer cb;
3256 float array[8];
3257
3258 memcpy(array, default_outer_level, sizeof(float) * 4);
3259 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3260
3261 cb.buffer = NULL;
3262 cb.user_buffer = NULL;
3263 cb.buffer_size = sizeof(array);
3264
3265 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3266 (void*)array, sizeof(array),
3267 &cb.buffer_offset);
3268
3269 si_set_constant_buffer(sctx, &sctx->rw_buffers,
3270 SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3271 pipe_resource_reference(&cb.buffer, NULL);
3272 }
3273
3274 static void si_texture_barrier(struct pipe_context *ctx)
3275 {
3276 struct si_context *sctx = (struct si_context *)ctx;
3277
3278 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3279 SI_CONTEXT_INV_GLOBAL_L2 |
3280 SI_CONTEXT_FLUSH_AND_INV_CB |
3281 SI_CONTEXT_CS_PARTIAL_FLUSH;
3282 }
3283
3284 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3285 {
3286 struct si_context *sctx = (struct si_context *)ctx;
3287
3288 /* Subsequent commands must wait for all shader invocations to
3289 * complete. */
3290 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3291 SI_CONTEXT_CS_PARTIAL_FLUSH;
3292
3293 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3294 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3295 SI_CONTEXT_INV_VMEM_L1;
3296
3297 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3298 PIPE_BARRIER_SHADER_BUFFER |
3299 PIPE_BARRIER_TEXTURE |
3300 PIPE_BARRIER_IMAGE |
3301 PIPE_BARRIER_STREAMOUT_BUFFER |
3302 PIPE_BARRIER_GLOBAL_BUFFER)) {
3303 /* As far as I can tell, L1 contents are written back to L2
3304 * automatically at end of shader, but the contents of other
3305 * L1 caches might still be stale. */
3306 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3307 }
3308
3309 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3310 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3311
3312 /* Indices are read through TC L2 since VI. */
3313 if (sctx->screen->b.chip_class <= CIK)
3314 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3315 }
3316
3317 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3318 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
3319
3320 if (flags & (PIPE_BARRIER_MAPPED_BUFFER |
3321 PIPE_BARRIER_FRAMEBUFFER |
3322 PIPE_BARRIER_INDIRECT_BUFFER)) {
3323 /* Not sure if INV_GLOBAL_L2 is the best thing here.
3324 *
3325 * We need to make sure that TC L1 & L2 are written back to
3326 * memory, because neither CPU accesses nor CB fetches consider
3327 * TC, but there's no need to invalidate any TC cache lines. */
3328 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
3329 }
3330 }
3331
3332 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3333 {
3334 struct pipe_blend_state blend;
3335
3336 memset(&blend, 0, sizeof(blend));
3337 blend.independent_blend_enable = true;
3338 blend.rt[0].colormask = 0xf;
3339 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3340 }
3341
3342 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3343 bool include_draw_vbo)
3344 {
3345 si_need_cs_space((struct si_context*)ctx);
3346 }
3347
3348 static void si_init_config(struct si_context *sctx);
3349
3350 void si_init_state_functions(struct si_context *sctx)
3351 {
3352 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3353 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3354 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3355 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3356 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3357
3358 si_init_atom(sctx, &sctx->cache_flush, &sctx->atoms.s.cache_flush, si_emit_cache_flush);
3359 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3360 si_init_atom(sctx, &sctx->msaa_sample_locs, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3361 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3362 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3363 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3364 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3365 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3366 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3367 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3368 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3369
3370 sctx->b.b.create_blend_state = si_create_blend_state;
3371 sctx->b.b.bind_blend_state = si_bind_blend_state;
3372 sctx->b.b.delete_blend_state = si_delete_blend_state;
3373 sctx->b.b.set_blend_color = si_set_blend_color;
3374
3375 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3376 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3377 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3378
3379 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3380 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3381 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3382
3383 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3384 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3385 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3386 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3387 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3388
3389 sctx->b.b.set_clip_state = si_set_clip_state;
3390 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3391
3392 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3393 sctx->b.b.get_sample_position = cayman_get_sample_position;
3394
3395 sctx->b.b.create_sampler_state = si_create_sampler_state;
3396 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3397
3398 sctx->b.b.create_sampler_view = si_create_sampler_view;
3399 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3400
3401 sctx->b.b.set_sample_mask = si_set_sample_mask;
3402
3403 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3404 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3405 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3406 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3407 sctx->b.b.set_index_buffer = si_set_index_buffer;
3408
3409 sctx->b.b.texture_barrier = si_texture_barrier;
3410 sctx->b.b.memory_barrier = si_memory_barrier;
3411 sctx->b.b.set_min_samples = si_set_min_samples;
3412 sctx->b.b.set_tess_state = si_set_tess_state;
3413
3414 sctx->b.b.set_active_query_state = si_set_active_query_state;
3415 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3416 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3417
3418 sctx->b.b.draw_vbo = si_draw_vbo;
3419
3420 si_init_config(sctx);
3421 }
3422
3423 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3424 struct r600_texture *rtex,
3425 struct radeon_bo_metadata *md)
3426 {
3427 struct si_screen *sscreen = (struct si_screen*)rscreen;
3428 struct pipe_resource *res = &rtex->resource.b.b;
3429 static const unsigned char swizzle[] = {
3430 PIPE_SWIZZLE_X,
3431 PIPE_SWIZZLE_Y,
3432 PIPE_SWIZZLE_Z,
3433 PIPE_SWIZZLE_W
3434 };
3435 uint32_t desc[8], i;
3436 bool is_array = util_resource_is_array_texture(res);
3437
3438 /* DRM 2.x.x doesn't support this. */
3439 if (rscreen->info.drm_major != 3)
3440 return;
3441
3442 assert(rtex->fmask.size == 0);
3443
3444 /* Metadata image format format version 1:
3445 * [0] = 1 (metadata format identifier)
3446 * [1] = (VENDOR_ID << 16) | PCI_ID
3447 * [2:9] = image descriptor for the whole resource
3448 * [2] is always 0, because the base address is cleared
3449 * [9] is the DCC offset bits [39:8] from the beginning of
3450 * the buffer
3451 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3452 */
3453
3454 md->metadata[0] = 1; /* metadata image format version 1 */
3455
3456 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3457 md->metadata[1] = (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3458
3459 si_make_texture_descriptor(sscreen, rtex, true,
3460 res->target, res->format,
3461 swizzle, 0, 0, res->last_level, 0,
3462 is_array ? res->array_size - 1 : 0,
3463 res->width0, res->height0, res->depth0,
3464 desc, NULL);
3465
3466 /* Clear the base address and set the relative DCC offset. */
3467 desc[0] = 0;
3468 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3469 desc[7] = rtex->dcc_offset >> 8;
3470
3471 /* Dwords [2:9] contain the image descriptor. */
3472 memcpy(&md->metadata[2], desc, sizeof(desc));
3473
3474 /* Dwords [10:..] contain the mipmap level offsets. */
3475 for (i = 0; i <= res->last_level; i++)
3476 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3477
3478 md->size_metadata = (11 + res->last_level) * 4;
3479 }
3480
3481 void si_init_screen_state_functions(struct si_screen *sscreen)
3482 {
3483 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3484 }
3485
3486 static void
3487 si_write_harvested_raster_configs(struct si_context *sctx,
3488 struct si_pm4_state *pm4,
3489 unsigned raster_config,
3490 unsigned raster_config_1)
3491 {
3492 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3493 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3494 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3495 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3496 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3497 unsigned rb_per_se = num_rb / num_se;
3498 unsigned se_mask[4];
3499 unsigned se;
3500
3501 se_mask[0] = ((1 << rb_per_se) - 1) & rb_mask;
3502 se_mask[1] = (se_mask[0] << rb_per_se) & rb_mask;
3503 se_mask[2] = (se_mask[1] << rb_per_se) & rb_mask;
3504 se_mask[3] = (se_mask[2] << rb_per_se) & rb_mask;
3505
3506 assert(num_se == 1 || num_se == 2 || num_se == 4);
3507 assert(sh_per_se == 1 || sh_per_se == 2);
3508 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3509
3510 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3511 * fields are for, so I'm leaving them as their default
3512 * values. */
3513
3514 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3515 (!se_mask[2] && !se_mask[3]))) {
3516 raster_config_1 &= C_028354_SE_PAIR_MAP;
3517
3518 if (!se_mask[0] && !se_mask[1]) {
3519 raster_config_1 |=
3520 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3521 } else {
3522 raster_config_1 |=
3523 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3524 }
3525 }
3526
3527 for (se = 0; se < num_se; se++) {
3528 unsigned raster_config_se = raster_config;
3529 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3530 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3531 int idx = (se / 2) * 2;
3532
3533 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3534 raster_config_se &= C_028350_SE_MAP;
3535
3536 if (!se_mask[idx]) {
3537 raster_config_se |=
3538 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3539 } else {
3540 raster_config_se |=
3541 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3542 }
3543 }
3544
3545 pkr0_mask &= rb_mask;
3546 pkr1_mask &= rb_mask;
3547 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3548 raster_config_se &= C_028350_PKR_MAP;
3549
3550 if (!pkr0_mask) {
3551 raster_config_se |=
3552 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3553 } else {
3554 raster_config_se |=
3555 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3556 }
3557 }
3558
3559 if (rb_per_se >= 2) {
3560 unsigned rb0_mask = 1 << (se * rb_per_se);
3561 unsigned rb1_mask = rb0_mask << 1;
3562
3563 rb0_mask &= rb_mask;
3564 rb1_mask &= rb_mask;
3565 if (!rb0_mask || !rb1_mask) {
3566 raster_config_se &= C_028350_RB_MAP_PKR0;
3567
3568 if (!rb0_mask) {
3569 raster_config_se |=
3570 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3571 } else {
3572 raster_config_se |=
3573 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3574 }
3575 }
3576
3577 if (rb_per_se > 2) {
3578 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3579 rb1_mask = rb0_mask << 1;
3580 rb0_mask &= rb_mask;
3581 rb1_mask &= rb_mask;
3582 if (!rb0_mask || !rb1_mask) {
3583 raster_config_se &= C_028350_RB_MAP_PKR1;
3584
3585 if (!rb0_mask) {
3586 raster_config_se |=
3587 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3588 } else {
3589 raster_config_se |=
3590 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3591 }
3592 }
3593 }
3594 }
3595
3596 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3597 if (sctx->b.chip_class < CIK)
3598 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3599 SE_INDEX(se) | SH_BROADCAST_WRITES |
3600 INSTANCE_BROADCAST_WRITES);
3601 else
3602 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3603 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3604 S_030800_INSTANCE_BROADCAST_WRITES(1));
3605 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3606 if (sctx->b.chip_class >= CIK)
3607 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3608 }
3609
3610 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3611 if (sctx->b.chip_class < CIK)
3612 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3613 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3614 INSTANCE_BROADCAST_WRITES);
3615 else
3616 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3617 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3618 S_030800_INSTANCE_BROADCAST_WRITES(1));
3619 }
3620
3621 static void si_init_config(struct si_context *sctx)
3622 {
3623 struct si_screen *sscreen = sctx->screen;
3624 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3625 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3626 unsigned raster_config, raster_config_1;
3627 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3628 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3629 int i;
3630
3631 if (!pm4)
3632 return;
3633
3634 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3635 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3636 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3637 si_pm4_cmd_end(pm4, false);
3638
3639 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3640 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3641
3642 /* FIXME calculate these values somehow ??? */
3643 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3644 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3645 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3646
3647 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3648 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3649
3650 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3651 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3652 if (sctx->b.chip_class < CIK)
3653 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3654 S_008A14_CLIP_VTX_REORDER_ENA(1));
3655
3656 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3657 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3658
3659 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3660
3661 for (i = 0; i < 16; i++) {
3662 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0 + i*8, 0);
3663 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0 + i*8, fui(1.0));
3664 }
3665
3666 switch (sctx->screen->b.family) {
3667 case CHIP_TAHITI:
3668 case CHIP_PITCAIRN:
3669 raster_config = 0x2a00126a;
3670 raster_config_1 = 0x00000000;
3671 break;
3672 case CHIP_VERDE:
3673 raster_config = 0x0000124a;
3674 raster_config_1 = 0x00000000;
3675 break;
3676 case CHIP_OLAND:
3677 raster_config = 0x00000082;
3678 raster_config_1 = 0x00000000;
3679 break;
3680 case CHIP_HAINAN:
3681 raster_config = 0x00000000;
3682 raster_config_1 = 0x00000000;
3683 break;
3684 case CHIP_BONAIRE:
3685 raster_config = 0x16000012;
3686 raster_config_1 = 0x00000000;
3687 break;
3688 case CHIP_HAWAII:
3689 raster_config = 0x3a00161a;
3690 raster_config_1 = 0x0000002e;
3691 break;
3692 case CHIP_FIJI:
3693 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3694 /* old kernels with old tiling config */
3695 raster_config = 0x16000012;
3696 raster_config_1 = 0x0000002a;
3697 } else {
3698 raster_config = 0x3a00161a;
3699 raster_config_1 = 0x0000002e;
3700 }
3701 break;
3702 case CHIP_POLARIS10:
3703 raster_config = 0x16000012;
3704 raster_config_1 = 0x0000002a;
3705 break;
3706 case CHIP_POLARIS11:
3707 raster_config = 0x16000012;
3708 raster_config_1 = 0x00000000;
3709 break;
3710 case CHIP_TONGA:
3711 raster_config = 0x16000012;
3712 raster_config_1 = 0x0000002a;
3713 break;
3714 case CHIP_ICELAND:
3715 raster_config = 0x00000002;
3716 raster_config_1 = 0x00000000;
3717 break;
3718 case CHIP_CARRIZO:
3719 raster_config = 0x00000002;
3720 raster_config_1 = 0x00000000;
3721 break;
3722 case CHIP_KAVERI:
3723 /* KV should be 0x00000002, but that causes problems with radeon */
3724 raster_config = 0x00000000; /* 0x00000002 */
3725 raster_config_1 = 0x00000000;
3726 break;
3727 case CHIP_KABINI:
3728 case CHIP_MULLINS:
3729 case CHIP_STONEY:
3730 raster_config = 0x00000000;
3731 raster_config_1 = 0x00000000;
3732 break;
3733 default:
3734 fprintf(stderr,
3735 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3736 raster_config = 0x00000000;
3737 raster_config_1 = 0x00000000;
3738 break;
3739 }
3740
3741 /* Always use the default config when all backends are enabled
3742 * (or when we failed to determine the enabled backends).
3743 */
3744 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3745 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3746 raster_config);
3747 if (sctx->b.chip_class >= CIK)
3748 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
3749 raster_config_1);
3750 } else {
3751 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
3752 }
3753
3754 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3755 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3756 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3757 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3758 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3759 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3760 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3761
3762 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3763 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3764 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3765 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3766 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3767 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3768 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3769 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3770 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3771 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3772 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE));
3773
3774 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3775 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3776 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3777
3778 if (sctx->b.chip_class >= CIK) {
3779 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
3780 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
3781 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
3782
3783 if (sscreen->b.info.num_good_compute_units /
3784 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
3785 /* Too few available compute units per SH. Disallowing
3786 * VS to run on CU0 could hurt us more than late VS
3787 * allocation would help.
3788 *
3789 * LATE_ALLOC_VS = 2 is the highest safe number.
3790 */
3791 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
3792 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3793 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
3794 } else {
3795 /* Set LATE_ALLOC_VS == 31. It should be less than
3796 * the number of scratch waves. Limitations:
3797 * - VS can't execute on CU0.
3798 * - If HS writes outputs to LDS, LS can't execute on CU0.
3799 */
3800 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xfffe));
3801 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
3802 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
3803 }
3804
3805 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3806 }
3807
3808 if (sctx->b.chip_class >= VI) {
3809 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
3810 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
3811 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
3812 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
3813 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
3814 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
3815 S_028B50_ACCUM_ISOLINE(32) |
3816 S_028B50_ACCUM_TRI(11) |
3817 S_028B50_ACCUM_QUAD(11) |
3818 S_028B50_DONUT_SPLIT(16));
3819 }
3820
3821 if (sctx->b.family == CHIP_STONEY)
3822 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
3823
3824 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
3825 if (sctx->b.chip_class >= CIK)
3826 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
3827 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
3828 RADEON_PRIO_BORDER_COLORS);
3829
3830 si_pm4_upload_indirect_buffer(sctx, pm4);
3831 sctx->init_config = pm4;
3832 }