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radeonsi: fix crash while binding a NULL constant buffer
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "util/u_memory.h"
28 #include "util/u_framebuffer.h"
29 #include "util/u_blitter.h"
30 #include "util/u_helpers.h"
31 #include "util/u_math.h"
32 #include "util/u_pack_color.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "radeonsi_pipe.h"
35 #include "radeonsi_shader.h"
36 #include "si_state.h"
37 #include "sid.h"
38
39 /*
40 * inferred framebuffer and blender state
41 */
42 static void si_update_fb_blend_state(struct r600_context *rctx)
43 {
44 struct si_pm4_state *pm4;
45 struct si_state_blend *blend = rctx->queued.named.blend;
46 uint32_t mask;
47
48 if (blend == NULL)
49 return;
50
51 pm4 = CALLOC_STRUCT(si_pm4_state);
52 if (pm4 == NULL)
53 return;
54
55 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
56 mask &= blend->cb_target_mask;
57 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
58
59 si_pm4_set_state(rctx, fb_blend, pm4);
60 }
61
62 /*
63 * Blender functions
64 */
65
66 static uint32_t si_translate_blend_function(int blend_func)
67 {
68 switch (blend_func) {
69 case PIPE_BLEND_ADD:
70 return V_028780_COMB_DST_PLUS_SRC;
71 case PIPE_BLEND_SUBTRACT:
72 return V_028780_COMB_SRC_MINUS_DST;
73 case PIPE_BLEND_REVERSE_SUBTRACT:
74 return V_028780_COMB_DST_MINUS_SRC;
75 case PIPE_BLEND_MIN:
76 return V_028780_COMB_MIN_DST_SRC;
77 case PIPE_BLEND_MAX:
78 return V_028780_COMB_MAX_DST_SRC;
79 default:
80 R600_ERR("Unknown blend function %d\n", blend_func);
81 assert(0);
82 break;
83 }
84 return 0;
85 }
86
87 static uint32_t si_translate_blend_factor(int blend_fact)
88 {
89 switch (blend_fact) {
90 case PIPE_BLENDFACTOR_ONE:
91 return V_028780_BLEND_ONE;
92 case PIPE_BLENDFACTOR_SRC_COLOR:
93 return V_028780_BLEND_SRC_COLOR;
94 case PIPE_BLENDFACTOR_SRC_ALPHA:
95 return V_028780_BLEND_SRC_ALPHA;
96 case PIPE_BLENDFACTOR_DST_ALPHA:
97 return V_028780_BLEND_DST_ALPHA;
98 case PIPE_BLENDFACTOR_DST_COLOR:
99 return V_028780_BLEND_DST_COLOR;
100 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
101 return V_028780_BLEND_SRC_ALPHA_SATURATE;
102 case PIPE_BLENDFACTOR_CONST_COLOR:
103 return V_028780_BLEND_CONSTANT_COLOR;
104 case PIPE_BLENDFACTOR_CONST_ALPHA:
105 return V_028780_BLEND_CONSTANT_ALPHA;
106 case PIPE_BLENDFACTOR_ZERO:
107 return V_028780_BLEND_ZERO;
108 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
109 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
110 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
111 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
112 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
113 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
114 case PIPE_BLENDFACTOR_INV_DST_COLOR:
115 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
116 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
117 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
118 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
119 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
120 case PIPE_BLENDFACTOR_SRC1_COLOR:
121 return V_028780_BLEND_SRC1_COLOR;
122 case PIPE_BLENDFACTOR_SRC1_ALPHA:
123 return V_028780_BLEND_SRC1_ALPHA;
124 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
125 return V_028780_BLEND_INV_SRC1_COLOR;
126 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
127 return V_028780_BLEND_INV_SRC1_ALPHA;
128 default:
129 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
130 assert(0);
131 break;
132 }
133 return 0;
134 }
135
136 static void *si_create_blend_state(struct pipe_context *ctx,
137 const struct pipe_blend_state *state)
138 {
139 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
140 struct si_pm4_state *pm4 = &blend->pm4;
141
142 uint32_t color_control;
143
144 if (blend == NULL)
145 return NULL;
146
147 color_control = S_028808_MODE(V_028808_CB_NORMAL);
148 if (state->logicop_enable) {
149 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
150 } else {
151 color_control |= S_028808_ROP3(0xcc);
152 }
153 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
154
155 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, ~0);
156 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, ~0);
157
158 blend->cb_target_mask = 0;
159 for (int i = 0; i < 8; i++) {
160 /* state->rt entries > 0 only written if independent blending */
161 const int j = state->independent_blend_enable ? i : 0;
162
163 unsigned eqRGB = state->rt[j].rgb_func;
164 unsigned srcRGB = state->rt[j].rgb_src_factor;
165 unsigned dstRGB = state->rt[j].rgb_dst_factor;
166 unsigned eqA = state->rt[j].alpha_func;
167 unsigned srcA = state->rt[j].alpha_src_factor;
168 unsigned dstA = state->rt[j].alpha_dst_factor;
169
170 unsigned blend_cntl = 0;
171
172 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
173 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
174
175 if (!state->rt[j].blend_enable) {
176 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
177 continue;
178 }
179
180 blend_cntl |= S_028780_ENABLE(1);
181 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
182 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
183 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
184
185 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
186 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
187 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
188 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
189 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
190 }
191 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
192 }
193
194 return blend;
195 }
196
197 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
198 {
199 struct r600_context *rctx = (struct r600_context *)ctx;
200 si_pm4_bind_state(rctx, blend, (struct si_state_blend *)state);
201 si_update_fb_blend_state(rctx);
202 }
203
204 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
205 {
206 struct r600_context *rctx = (struct r600_context *)ctx;
207 si_pm4_delete_state(rctx, blend, (struct si_state_blend *)state);
208 }
209
210 static void si_set_blend_color(struct pipe_context *ctx,
211 const struct pipe_blend_color *state)
212 {
213 struct r600_context *rctx = (struct r600_context *)ctx;
214 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
215
216 if (pm4 == NULL)
217 return;
218
219 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
220 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
221 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
222 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
223
224 si_pm4_set_state(rctx, blend_color, pm4);
225 }
226
227 /*
228 * Clipping, scissors and viewport
229 */
230
231 static void si_set_clip_state(struct pipe_context *ctx,
232 const struct pipe_clip_state *state)
233 {
234 struct r600_context *rctx = (struct r600_context *)ctx;
235 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
236
237 if (pm4 == NULL)
238 return;
239
240 for (int i = 0; i < 6; i++) {
241 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
242 fui(state->ucp[i][0]));
243 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
244 fui(state->ucp[i][1]));
245 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
246 fui(state->ucp[i][2]));
247 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
248 fui(state->ucp[i][3]));
249 }
250
251 si_pm4_set_state(rctx, clip, pm4);
252 }
253
254 static void si_set_scissor_state(struct pipe_context *ctx,
255 const struct pipe_scissor_state *state)
256 {
257 struct r600_context *rctx = (struct r600_context *)ctx;
258 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
259 uint32_t tl, br;
260
261 if (pm4 == NULL)
262 return;
263
264 tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny);
265 br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
266 si_pm4_set_reg(pm4, R_028210_PA_SC_CLIPRECT_0_TL, tl);
267 si_pm4_set_reg(pm4, R_028214_PA_SC_CLIPRECT_0_BR, br);
268 si_pm4_set_reg(pm4, R_028218_PA_SC_CLIPRECT_1_TL, tl);
269 si_pm4_set_reg(pm4, R_02821C_PA_SC_CLIPRECT_1_BR, br);
270 si_pm4_set_reg(pm4, R_028220_PA_SC_CLIPRECT_2_TL, tl);
271 si_pm4_set_reg(pm4, R_028224_PA_SC_CLIPRECT_2_BR, br);
272 si_pm4_set_reg(pm4, R_028228_PA_SC_CLIPRECT_3_TL, tl);
273 si_pm4_set_reg(pm4, R_02822C_PA_SC_CLIPRECT_3_BR, br);
274
275 si_pm4_set_state(rctx, scissor, pm4);
276 }
277
278 static void si_set_viewport_state(struct pipe_context *ctx,
279 const struct pipe_viewport_state *state)
280 {
281 struct r600_context *rctx = (struct r600_context *)ctx;
282 struct si_state_viewport *viewport = CALLOC_STRUCT(si_state_viewport);
283 struct si_pm4_state *pm4 = &viewport->pm4;
284
285 if (viewport == NULL)
286 return;
287
288 viewport->viewport = *state;
289 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000);
290 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000);
291 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
292 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
293 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
294 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
295 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
296 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
297 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL, 0x0000043F);
298
299 si_pm4_set_state(rctx, viewport, viewport);
300 }
301
302 /*
303 * inferred state between framebuffer and rasterizer
304 */
305 static void si_update_fb_rs_state(struct r600_context *rctx)
306 {
307 struct si_state_rasterizer *rs = rctx->queued.named.rasterizer;
308 struct si_pm4_state *pm4;
309 unsigned offset_db_fmt_cntl = 0, depth;
310 float offset_units;
311
312 if (!rs || !rctx->framebuffer.zsbuf)
313 return;
314
315 offset_units = rctx->queued.named.rasterizer->offset_units;
316 switch (rctx->framebuffer.zsbuf->texture->format) {
317 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
318 case PIPE_FORMAT_X8Z24_UNORM:
319 case PIPE_FORMAT_Z24X8_UNORM:
320 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
321 depth = -24;
322 offset_units *= 2.0f;
323 break;
324 case PIPE_FORMAT_Z32_FLOAT:
325 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
326 depth = -23;
327 offset_units *= 1.0f;
328 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
329 break;
330 case PIPE_FORMAT_Z16_UNORM:
331 depth = -16;
332 offset_units *= 4.0f;
333 break;
334 default:
335 return;
336 }
337
338 pm4 = CALLOC_STRUCT(si_pm4_state);
339 /* FIXME some of those reg can be computed with cso */
340 offset_db_fmt_cntl |= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
341 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
342 fui(rctx->queued.named.rasterizer->offset_scale));
343 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
344 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
345 fui(rctx->queued.named.rasterizer->offset_scale));
346 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
347 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL, offset_db_fmt_cntl);
348
349 si_pm4_set_state(rctx, fb_rs, pm4);
350 }
351
352 /*
353 * Rasterizer
354 */
355
356 static uint32_t si_translate_fill(uint32_t func)
357 {
358 switch(func) {
359 case PIPE_POLYGON_MODE_FILL:
360 return V_028814_X_DRAW_TRIANGLES;
361 case PIPE_POLYGON_MODE_LINE:
362 return V_028814_X_DRAW_LINES;
363 case PIPE_POLYGON_MODE_POINT:
364 return V_028814_X_DRAW_POINTS;
365 default:
366 assert(0);
367 return V_028814_X_DRAW_POINTS;
368 }
369 }
370
371 static void *si_create_rs_state(struct pipe_context *ctx,
372 const struct pipe_rasterizer_state *state)
373 {
374 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
375 struct si_pm4_state *pm4 = &rs->pm4;
376 unsigned tmp;
377 unsigned prov_vtx = 1, polygon_dual_mode;
378 unsigned clip_rule;
379 float psize_min, psize_max;
380
381 if (rs == NULL) {
382 return NULL;
383 }
384
385 rs->two_side = state->light_twoside;
386
387 polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
388 state->fill_back != PIPE_POLYGON_MODE_FILL);
389
390 if (state->flatshade_first)
391 prov_vtx = 0;
392
393 rs->flatshade = state->flatshade;
394 rs->sprite_coord_enable = state->sprite_coord_enable;
395 rs->pa_sc_line_stipple = state->line_stipple_enable ?
396 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
397 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
398 rs->pa_su_sc_mode_cntl =
399 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
400 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
401 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
402 S_028814_FACE(!state->front_ccw) |
403 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
404 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
405 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
406 S_028814_POLY_MODE(polygon_dual_mode) |
407 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
408 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back));
409 rs->pa_cl_clip_cntl =
410 S_028810_PS_UCP_MODE(3) |
411 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
412 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
413 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
414 rs->pa_cl_vs_out_cntl =
415 S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
416 S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex);
417
418 clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
419
420 /* offset */
421 rs->offset_units = state->offset_units;
422 rs->offset_scale = state->offset_scale * 12.0f;
423
424 tmp = S_0286D4_FLAT_SHADE_ENA(1);
425 if (state->sprite_coord_enable) {
426 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
427 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
428 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
429 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
430 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1);
431 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
432 tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
433 }
434 }
435 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
436
437 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0x00000000);
438 /* point size 12.4 fixed point */
439 tmp = (unsigned)(state->point_size * 8.0);
440 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
441
442 if (state->point_size_per_vertex) {
443 psize_min = util_get_min_point_size(state);
444 psize_max = 8192;
445 } else {
446 /* Force the point size to be as if the vertex output was disabled. */
447 psize_min = state->point_size;
448 psize_max = state->point_size;
449 }
450 /* Divide by two, because 0.5 = 1 pixel. */
451 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
452 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
453 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
454
455 tmp = (unsigned)state->line_width * 8;
456 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
457 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
458 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable));
459
460 si_pm4_set_reg(pm4, R_028BDC_PA_SC_LINE_CNTL, 0x00000400);
461 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
462 S_028BE4_PIX_CENTER(state->gl_rasterization_rules));
463 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000);
464 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000);
465 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000);
466 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000);
467
468 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
469 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule);
470
471 return rs;
472 }
473
474 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
475 {
476 struct r600_context *rctx = (struct r600_context *)ctx;
477 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
478
479 if (state == NULL)
480 return;
481
482 // TODO
483 rctx->sprite_coord_enable = rs->sprite_coord_enable;
484 rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
485 rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
486 rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
487 rctx->pa_cl_vs_out_cntl = rs->pa_cl_vs_out_cntl;
488
489 si_pm4_bind_state(rctx, rasterizer, rs);
490 si_update_fb_rs_state(rctx);
491 }
492
493 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
494 {
495 struct r600_context *rctx = (struct r600_context *)ctx;
496 si_pm4_delete_state(rctx, rasterizer, (struct si_state_rasterizer *)state);
497 }
498
499 /*
500 * infeered state between dsa and stencil ref
501 */
502 static void si_update_dsa_stencil_ref(struct r600_context *rctx)
503 {
504 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
505 struct pipe_stencil_ref *ref = &rctx->stencil_ref;
506 struct si_state_dsa *dsa = rctx->queued.named.dsa;
507
508 if (pm4 == NULL)
509 return;
510
511 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
512 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
513 S_028430_STENCILMASK(dsa->valuemask[0]) |
514 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
515 S_028430_STENCILOPVAL(1));
516 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
517 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
518 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
519 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
520 S_028434_STENCILOPVAL_BF(1));
521
522 si_pm4_set_state(rctx, dsa_stencil_ref, pm4);
523 }
524
525 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
526 const struct pipe_stencil_ref *state)
527 {
528 struct r600_context *rctx = (struct r600_context *)ctx;
529 rctx->stencil_ref = *state;
530 si_update_dsa_stencil_ref(rctx);
531 }
532
533
534 /*
535 * DSA
536 */
537
538 static uint32_t si_translate_stencil_op(int s_op)
539 {
540 switch (s_op) {
541 case PIPE_STENCIL_OP_KEEP:
542 return V_02842C_STENCIL_KEEP;
543 case PIPE_STENCIL_OP_ZERO:
544 return V_02842C_STENCIL_ZERO;
545 case PIPE_STENCIL_OP_REPLACE:
546 return V_02842C_STENCIL_REPLACE_TEST;
547 case PIPE_STENCIL_OP_INCR:
548 return V_02842C_STENCIL_ADD_CLAMP;
549 case PIPE_STENCIL_OP_DECR:
550 return V_02842C_STENCIL_SUB_CLAMP;
551 case PIPE_STENCIL_OP_INCR_WRAP:
552 return V_02842C_STENCIL_ADD_WRAP;
553 case PIPE_STENCIL_OP_DECR_WRAP:
554 return V_02842C_STENCIL_SUB_WRAP;
555 case PIPE_STENCIL_OP_INVERT:
556 return V_02842C_STENCIL_INVERT;
557 default:
558 R600_ERR("Unknown stencil op %d", s_op);
559 assert(0);
560 break;
561 }
562 return 0;
563 }
564
565 static void *si_create_dsa_state(struct pipe_context *ctx,
566 const struct pipe_depth_stencil_alpha_state *state)
567 {
568 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
569 struct si_pm4_state *pm4 = &dsa->pm4;
570 unsigned db_depth_control;
571 unsigned db_render_override, db_render_control;
572 uint32_t db_stencil_control = 0;
573
574 if (dsa == NULL) {
575 return NULL;
576 }
577
578 dsa->valuemask[0] = state->stencil[0].valuemask;
579 dsa->valuemask[1] = state->stencil[1].valuemask;
580 dsa->writemask[0] = state->stencil[0].writemask;
581 dsa->writemask[1] = state->stencil[1].writemask;
582
583 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
584 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
585 S_028800_ZFUNC(state->depth.func);
586
587 /* stencil */
588 if (state->stencil[0].enabled) {
589 db_depth_control |= S_028800_STENCIL_ENABLE(1);
590 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
591 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
592 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
593 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
594
595 if (state->stencil[1].enabled) {
596 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
597 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
598 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
599 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
600 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
601 }
602 }
603
604 /* alpha */
605 if (state->alpha.enabled) {
606 dsa->alpha_func = state->alpha.func;
607 dsa->alpha_ref = state->alpha.ref_value;
608 } else {
609 dsa->alpha_func = PIPE_FUNC_ALWAYS;
610 }
611
612 /* misc */
613 db_render_control = 0;
614 db_render_override = S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
615 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
616 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
617 /* TODO db_render_override depends on query */
618 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0x00000000);
619 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0x00000000);
620 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0x00000000);
621 si_pm4_set_reg(pm4, R_02802C_DB_DEPTH_CLEAR, 0x3F800000);
622 //si_pm4_set_reg(pm4, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control);
623 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
624 si_pm4_set_reg(pm4, R_028000_DB_RENDER_CONTROL, db_render_control);
625 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
626 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
627 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
628 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
629 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
630 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK, 0x0000AA00);
631 dsa->db_render_override = db_render_override;
632
633 return dsa;
634 }
635
636 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
637 {
638 struct r600_context *rctx = (struct r600_context *)ctx;
639 struct si_state_dsa *dsa = state;
640
641 if (state == NULL)
642 return;
643
644 si_pm4_bind_state(rctx, dsa, dsa);
645 si_update_dsa_stencil_ref(rctx);
646 }
647
648 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
649 {
650 struct r600_context *rctx = (struct r600_context *)ctx;
651 si_pm4_delete_state(rctx, dsa, (struct si_state_dsa *)state);
652 }
653
654 static void *si_create_db_flush_dsa(struct r600_context *rctx, bool copy_depth,
655 bool copy_stencil)
656 {
657 struct pipe_depth_stencil_alpha_state dsa;
658 struct si_state_dsa *state;
659
660 memset(&dsa, 0, sizeof(dsa));
661
662 state = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
663 if (copy_depth || copy_stencil) {
664 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
665 S_028000_DEPTH_COPY(copy_depth) |
666 S_028000_STENCIL_COPY(copy_stencil) |
667 S_028000_COPY_CENTROID(1));
668 } else {
669 si_pm4_set_reg(&state->pm4, R_028000_DB_RENDER_CONTROL,
670 S_028000_DEPTH_COMPRESS_DISABLE(1) |
671 S_028000_STENCIL_COMPRESS_DISABLE(1));
672 si_pm4_set_reg(&state->pm4, R_02800C_DB_RENDER_OVERRIDE,
673 S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE) |
674 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
675 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
676 S_02800C_DISABLE_TILE_RATE_TILES(1));
677 }
678
679 return state;
680 }
681
682 /*
683 * format translation
684 */
685 static uint32_t si_translate_colorformat(enum pipe_format format)
686 {
687 switch (format) {
688 /* 8-bit buffers. */
689 case PIPE_FORMAT_A8_UNORM:
690 case PIPE_FORMAT_A8_SNORM:
691 case PIPE_FORMAT_A8_UINT:
692 case PIPE_FORMAT_A8_SINT:
693 case PIPE_FORMAT_I8_UNORM:
694 case PIPE_FORMAT_I8_SNORM:
695 case PIPE_FORMAT_I8_UINT:
696 case PIPE_FORMAT_I8_SINT:
697 case PIPE_FORMAT_L8_UNORM:
698 case PIPE_FORMAT_L8_SNORM:
699 case PIPE_FORMAT_L8_UINT:
700 case PIPE_FORMAT_L8_SINT:
701 case PIPE_FORMAT_L8_SRGB:
702 case PIPE_FORMAT_R8_UNORM:
703 case PIPE_FORMAT_R8_SNORM:
704 case PIPE_FORMAT_R8_UINT:
705 case PIPE_FORMAT_R8_SINT:
706 return V_028C70_COLOR_8;
707
708 /* 16-bit buffers. */
709 case PIPE_FORMAT_B5G6R5_UNORM:
710 return V_028C70_COLOR_5_6_5;
711
712 case PIPE_FORMAT_B5G5R5A1_UNORM:
713 case PIPE_FORMAT_B5G5R5X1_UNORM:
714 return V_028C70_COLOR_1_5_5_5;
715
716 case PIPE_FORMAT_B4G4R4A4_UNORM:
717 case PIPE_FORMAT_B4G4R4X4_UNORM:
718 return V_028C70_COLOR_4_4_4_4;
719
720 case PIPE_FORMAT_L8A8_UNORM:
721 case PIPE_FORMAT_L8A8_SNORM:
722 case PIPE_FORMAT_L8A8_UINT:
723 case PIPE_FORMAT_L8A8_SINT:
724 case PIPE_FORMAT_R8G8_SNORM:
725 case PIPE_FORMAT_R8G8_UNORM:
726 case PIPE_FORMAT_R8G8_UINT:
727 case PIPE_FORMAT_R8G8_SINT:
728 return V_028C70_COLOR_8_8;
729
730 case PIPE_FORMAT_Z16_UNORM:
731 case PIPE_FORMAT_R16_UNORM:
732 case PIPE_FORMAT_R16_SNORM:
733 case PIPE_FORMAT_R16_UINT:
734 case PIPE_FORMAT_R16_SINT:
735 case PIPE_FORMAT_R16_FLOAT:
736 case PIPE_FORMAT_L16_UNORM:
737 case PIPE_FORMAT_L16_SNORM:
738 case PIPE_FORMAT_L16_FLOAT:
739 case PIPE_FORMAT_I16_UNORM:
740 case PIPE_FORMAT_I16_SNORM:
741 case PIPE_FORMAT_I16_FLOAT:
742 case PIPE_FORMAT_A16_UNORM:
743 case PIPE_FORMAT_A16_SNORM:
744 case PIPE_FORMAT_A16_FLOAT:
745 return V_028C70_COLOR_16;
746
747 /* 32-bit buffers. */
748 case PIPE_FORMAT_A8B8G8R8_SRGB:
749 case PIPE_FORMAT_A8B8G8R8_UNORM:
750 case PIPE_FORMAT_A8R8G8B8_UNORM:
751 case PIPE_FORMAT_B8G8R8A8_SRGB:
752 case PIPE_FORMAT_B8G8R8A8_UNORM:
753 case PIPE_FORMAT_B8G8R8X8_UNORM:
754 case PIPE_FORMAT_R8G8B8A8_SNORM:
755 case PIPE_FORMAT_R8G8B8A8_UNORM:
756 case PIPE_FORMAT_R8G8B8X8_UNORM:
757 case PIPE_FORMAT_R8G8B8X8_SNORM:
758 case PIPE_FORMAT_R8G8B8X8_SRGB:
759 case PIPE_FORMAT_R8G8B8X8_UINT:
760 case PIPE_FORMAT_R8G8B8X8_SINT:
761 case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
762 case PIPE_FORMAT_X8B8G8R8_UNORM:
763 case PIPE_FORMAT_X8R8G8B8_UNORM:
764 case PIPE_FORMAT_R8G8B8A8_SSCALED:
765 case PIPE_FORMAT_R8G8B8A8_USCALED:
766 case PIPE_FORMAT_R8G8B8A8_SINT:
767 case PIPE_FORMAT_R8G8B8A8_UINT:
768 return V_028C70_COLOR_8_8_8_8;
769
770 case PIPE_FORMAT_R10G10B10A2_UNORM:
771 case PIPE_FORMAT_R10G10B10X2_SNORM:
772 case PIPE_FORMAT_B10G10R10A2_UNORM:
773 case PIPE_FORMAT_B10G10R10A2_UINT:
774 case PIPE_FORMAT_B10G10R10X2_UNORM:
775 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
776 return V_028C70_COLOR_2_10_10_10;
777
778 case PIPE_FORMAT_Z24X8_UNORM:
779 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
780 return V_028C70_COLOR_8_24;
781
782 case PIPE_FORMAT_S8X24_UINT:
783 case PIPE_FORMAT_X8Z24_UNORM:
784 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
785 return V_028C70_COLOR_24_8;
786
787 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
788 return V_028C70_COLOR_X24_8_32_FLOAT;
789
790 case PIPE_FORMAT_I32_FLOAT:
791 case PIPE_FORMAT_L32_FLOAT:
792 case PIPE_FORMAT_R32_FLOAT:
793 case PIPE_FORMAT_A32_FLOAT:
794 case PIPE_FORMAT_Z32_FLOAT:
795 return V_028C70_COLOR_32;
796
797 case PIPE_FORMAT_L16A16_UNORM:
798 case PIPE_FORMAT_L16A16_SNORM:
799 case PIPE_FORMAT_L16A16_FLOAT:
800 case PIPE_FORMAT_R16G16_SSCALED:
801 case PIPE_FORMAT_R16G16_UNORM:
802 case PIPE_FORMAT_R16G16_SNORM:
803 case PIPE_FORMAT_R16G16_UINT:
804 case PIPE_FORMAT_R16G16_SINT:
805 case PIPE_FORMAT_R16G16_FLOAT:
806 return V_028C70_COLOR_16_16;
807
808 case PIPE_FORMAT_R11G11B10_FLOAT:
809 return V_028C70_COLOR_10_11_11;
810
811 /* 64-bit buffers. */
812 case PIPE_FORMAT_R16G16B16A16_UINT:
813 case PIPE_FORMAT_R16G16B16A16_SINT:
814 case PIPE_FORMAT_R16G16B16A16_USCALED:
815 case PIPE_FORMAT_R16G16B16A16_SSCALED:
816 case PIPE_FORMAT_R16G16B16A16_UNORM:
817 case PIPE_FORMAT_R16G16B16A16_SNORM:
818 case PIPE_FORMAT_R16G16B16A16_FLOAT:
819 case PIPE_FORMAT_R16G16B16X16_UNORM:
820 case PIPE_FORMAT_R16G16B16X16_SNORM:
821 case PIPE_FORMAT_R16G16B16X16_FLOAT:
822 case PIPE_FORMAT_R16G16B16X16_UINT:
823 case PIPE_FORMAT_R16G16B16X16_SINT:
824 return V_028C70_COLOR_16_16_16_16;
825
826 case PIPE_FORMAT_L32A32_FLOAT:
827 case PIPE_FORMAT_L32A32_UINT:
828 case PIPE_FORMAT_L32A32_SINT:
829 case PIPE_FORMAT_R32G32_FLOAT:
830 case PIPE_FORMAT_R32G32_USCALED:
831 case PIPE_FORMAT_R32G32_SSCALED:
832 case PIPE_FORMAT_R32G32_SINT:
833 case PIPE_FORMAT_R32G32_UINT:
834 return V_028C70_COLOR_32_32;
835
836 /* 128-bit buffers. */
837 case PIPE_FORMAT_R32G32B32A32_SNORM:
838 case PIPE_FORMAT_R32G32B32A32_UNORM:
839 case PIPE_FORMAT_R32G32B32A32_SSCALED:
840 case PIPE_FORMAT_R32G32B32A32_USCALED:
841 case PIPE_FORMAT_R32G32B32A32_SINT:
842 case PIPE_FORMAT_R32G32B32A32_UINT:
843 case PIPE_FORMAT_R32G32B32A32_FLOAT:
844 case PIPE_FORMAT_R32G32B32X32_FLOAT:
845 case PIPE_FORMAT_R32G32B32X32_UINT:
846 case PIPE_FORMAT_R32G32B32X32_SINT:
847 return V_028C70_COLOR_32_32_32_32;
848
849 /* YUV buffers. */
850 case PIPE_FORMAT_UYVY:
851 case PIPE_FORMAT_YUYV:
852 /* 96-bit buffers. */
853 case PIPE_FORMAT_R32G32B32_FLOAT:
854 /* 8-bit buffers. */
855 case PIPE_FORMAT_L4A4_UNORM:
856 case PIPE_FORMAT_R4A4_UNORM:
857 case PIPE_FORMAT_A4R4_UNORM:
858 default:
859 return V_028C70_COLOR_INVALID; /* Unsupported. */
860 }
861 }
862
863 static uint32_t si_translate_colorswap(enum pipe_format format)
864 {
865 switch (format) {
866 /* 8-bit buffers. */
867 case PIPE_FORMAT_L4A4_UNORM:
868 case PIPE_FORMAT_A4R4_UNORM:
869 return V_028C70_SWAP_ALT;
870
871 case PIPE_FORMAT_A8_UNORM:
872 case PIPE_FORMAT_A8_SNORM:
873 case PIPE_FORMAT_A8_UINT:
874 case PIPE_FORMAT_A8_SINT:
875 case PIPE_FORMAT_R4A4_UNORM:
876 return V_028C70_SWAP_ALT_REV;
877 case PIPE_FORMAT_I8_UNORM:
878 case PIPE_FORMAT_I8_SNORM:
879 case PIPE_FORMAT_L8_UNORM:
880 case PIPE_FORMAT_L8_SNORM:
881 case PIPE_FORMAT_I8_UINT:
882 case PIPE_FORMAT_I8_SINT:
883 case PIPE_FORMAT_L8_UINT:
884 case PIPE_FORMAT_L8_SINT:
885 case PIPE_FORMAT_L8_SRGB:
886 case PIPE_FORMAT_R8_UNORM:
887 case PIPE_FORMAT_R8_SNORM:
888 case PIPE_FORMAT_R8_UINT:
889 case PIPE_FORMAT_R8_SINT:
890 return V_028C70_SWAP_STD;
891
892 /* 16-bit buffers. */
893 case PIPE_FORMAT_B5G6R5_UNORM:
894 return V_028C70_SWAP_STD_REV;
895
896 case PIPE_FORMAT_B5G5R5A1_UNORM:
897 case PIPE_FORMAT_B5G5R5X1_UNORM:
898 return V_028C70_SWAP_ALT;
899
900 case PIPE_FORMAT_B4G4R4A4_UNORM:
901 case PIPE_FORMAT_B4G4R4X4_UNORM:
902 return V_028C70_SWAP_ALT;
903
904 case PIPE_FORMAT_Z16_UNORM:
905 return V_028C70_SWAP_STD;
906
907 case PIPE_FORMAT_L8A8_UNORM:
908 case PIPE_FORMAT_L8A8_SNORM:
909 case PIPE_FORMAT_L8A8_UINT:
910 case PIPE_FORMAT_L8A8_SINT:
911 return V_028C70_SWAP_ALT;
912 case PIPE_FORMAT_R8G8_SNORM:
913 case PIPE_FORMAT_R8G8_UNORM:
914 case PIPE_FORMAT_R8G8_UINT:
915 case PIPE_FORMAT_R8G8_SINT:
916 return V_028C70_SWAP_STD;
917
918 case PIPE_FORMAT_I16_UNORM:
919 case PIPE_FORMAT_I16_SNORM:
920 case PIPE_FORMAT_I16_FLOAT:
921 case PIPE_FORMAT_L16_UNORM:
922 case PIPE_FORMAT_L16_SNORM:
923 case PIPE_FORMAT_L16_FLOAT:
924 case PIPE_FORMAT_R16_UNORM:
925 case PIPE_FORMAT_R16_SNORM:
926 case PIPE_FORMAT_R16_UINT:
927 case PIPE_FORMAT_R16_SINT:
928 case PIPE_FORMAT_R16_FLOAT:
929 return V_028C70_SWAP_STD;
930
931 case PIPE_FORMAT_A16_UNORM:
932 case PIPE_FORMAT_A16_SNORM:
933 case PIPE_FORMAT_A16_FLOAT:
934 return V_028C70_SWAP_ALT_REV;
935
936 /* 32-bit buffers. */
937 case PIPE_FORMAT_A8B8G8R8_SRGB:
938 return V_028C70_SWAP_STD_REV;
939 case PIPE_FORMAT_B8G8R8A8_SRGB:
940 return V_028C70_SWAP_ALT;
941
942 case PIPE_FORMAT_B8G8R8A8_UNORM:
943 case PIPE_FORMAT_B8G8R8X8_UNORM:
944 return V_028C70_SWAP_ALT;
945
946 case PIPE_FORMAT_A8R8G8B8_UNORM:
947 case PIPE_FORMAT_X8R8G8B8_UNORM:
948 return V_028C70_SWAP_ALT_REV;
949 case PIPE_FORMAT_R8G8B8A8_SNORM:
950 case PIPE_FORMAT_R8G8B8A8_UNORM:
951 case PIPE_FORMAT_R8G8B8A8_SSCALED:
952 case PIPE_FORMAT_R8G8B8A8_USCALED:
953 case PIPE_FORMAT_R8G8B8A8_SINT:
954 case PIPE_FORMAT_R8G8B8A8_UINT:
955 case PIPE_FORMAT_R8G8B8X8_UNORM:
956 case PIPE_FORMAT_R8G8B8X8_SNORM:
957 case PIPE_FORMAT_R8G8B8X8_SRGB:
958 case PIPE_FORMAT_R8G8B8X8_UINT:
959 case PIPE_FORMAT_R8G8B8X8_SINT:
960 return V_028C70_SWAP_STD;
961
962 case PIPE_FORMAT_A8B8G8R8_UNORM:
963 case PIPE_FORMAT_X8B8G8R8_UNORM:
964 /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
965 return V_028C70_SWAP_STD_REV;
966
967 case PIPE_FORMAT_Z24X8_UNORM:
968 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
969 return V_028C70_SWAP_STD;
970
971 case PIPE_FORMAT_S8X24_UINT:
972 case PIPE_FORMAT_X8Z24_UNORM:
973 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
974 return V_028C70_SWAP_STD_REV;
975
976 case PIPE_FORMAT_R10G10B10A2_UNORM:
977 case PIPE_FORMAT_R10G10B10X2_SNORM:
978 case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
979 return V_028C70_SWAP_STD;
980
981 case PIPE_FORMAT_B10G10R10A2_UNORM:
982 case PIPE_FORMAT_B10G10R10A2_UINT:
983 case PIPE_FORMAT_B10G10R10X2_UNORM:
984 return V_028C70_SWAP_ALT;
985
986 case PIPE_FORMAT_R11G11B10_FLOAT:
987 case PIPE_FORMAT_I32_FLOAT:
988 case PIPE_FORMAT_L32_FLOAT:
989 case PIPE_FORMAT_R32_FLOAT:
990 case PIPE_FORMAT_R32_UINT:
991 case PIPE_FORMAT_R32_SINT:
992 case PIPE_FORMAT_Z32_FLOAT:
993 case PIPE_FORMAT_R16G16_FLOAT:
994 case PIPE_FORMAT_R16G16_UNORM:
995 case PIPE_FORMAT_R16G16_SNORM:
996 case PIPE_FORMAT_R16G16_UINT:
997 case PIPE_FORMAT_R16G16_SINT:
998 return V_028C70_SWAP_STD;
999
1000 case PIPE_FORMAT_L16A16_UNORM:
1001 case PIPE_FORMAT_L16A16_SNORM:
1002 case PIPE_FORMAT_L16A16_FLOAT:
1003 return V_028C70_SWAP_ALT;
1004
1005 case PIPE_FORMAT_A32_FLOAT:
1006 return V_028C70_SWAP_ALT_REV;
1007
1008 /* 64-bit buffers. */
1009 case PIPE_FORMAT_R32G32_FLOAT:
1010 case PIPE_FORMAT_R32G32_UINT:
1011 case PIPE_FORMAT_R32G32_SINT:
1012 case PIPE_FORMAT_R16G16B16A16_UNORM:
1013 case PIPE_FORMAT_R16G16B16A16_SNORM:
1014 case PIPE_FORMAT_R16G16B16A16_USCALED:
1015 case PIPE_FORMAT_R16G16B16A16_SSCALED:
1016 case PIPE_FORMAT_R16G16B16A16_UINT:
1017 case PIPE_FORMAT_R16G16B16A16_SINT:
1018 case PIPE_FORMAT_R16G16B16A16_FLOAT:
1019 case PIPE_FORMAT_R16G16B16X16_UNORM:
1020 case PIPE_FORMAT_R16G16B16X16_SNORM:
1021 case PIPE_FORMAT_R16G16B16X16_FLOAT:
1022 case PIPE_FORMAT_R16G16B16X16_UINT:
1023 case PIPE_FORMAT_R16G16B16X16_SINT:
1024 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1025 return V_028C70_SWAP_STD;
1026
1027 case PIPE_FORMAT_L32A32_FLOAT:
1028 case PIPE_FORMAT_L32A32_UINT:
1029 case PIPE_FORMAT_L32A32_SINT:
1030 return V_028C70_SWAP_ALT;
1031
1032 /* 128-bit buffers. */
1033 case PIPE_FORMAT_R32G32B32A32_FLOAT:
1034 case PIPE_FORMAT_R32G32B32A32_SNORM:
1035 case PIPE_FORMAT_R32G32B32A32_UNORM:
1036 case PIPE_FORMAT_R32G32B32A32_SSCALED:
1037 case PIPE_FORMAT_R32G32B32A32_USCALED:
1038 case PIPE_FORMAT_R32G32B32A32_SINT:
1039 case PIPE_FORMAT_R32G32B32A32_UINT:
1040 case PIPE_FORMAT_R32G32B32X32_FLOAT:
1041 case PIPE_FORMAT_R32G32B32X32_UINT:
1042 case PIPE_FORMAT_R32G32B32X32_SINT:
1043 return V_028C70_SWAP_STD;
1044 default:
1045 R600_ERR("unsupported colorswap format %d\n", format);
1046 return ~0U;
1047 }
1048 return ~0U;
1049 }
1050
1051 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1052 {
1053 if (R600_BIG_ENDIAN) {
1054 switch(colorformat) {
1055 /* 8-bit buffers. */
1056 case V_028C70_COLOR_8:
1057 return V_028C70_ENDIAN_NONE;
1058
1059 /* 16-bit buffers. */
1060 case V_028C70_COLOR_5_6_5:
1061 case V_028C70_COLOR_1_5_5_5:
1062 case V_028C70_COLOR_4_4_4_4:
1063 case V_028C70_COLOR_16:
1064 case V_028C70_COLOR_8_8:
1065 return V_028C70_ENDIAN_8IN16;
1066
1067 /* 32-bit buffers. */
1068 case V_028C70_COLOR_8_8_8_8:
1069 case V_028C70_COLOR_2_10_10_10:
1070 case V_028C70_COLOR_8_24:
1071 case V_028C70_COLOR_24_8:
1072 case V_028C70_COLOR_16_16:
1073 return V_028C70_ENDIAN_8IN32;
1074
1075 /* 64-bit buffers. */
1076 case V_028C70_COLOR_16_16_16_16:
1077 return V_028C70_ENDIAN_8IN16;
1078
1079 case V_028C70_COLOR_32_32:
1080 return V_028C70_ENDIAN_8IN32;
1081
1082 /* 128-bit buffers. */
1083 case V_028C70_COLOR_32_32_32_32:
1084 return V_028C70_ENDIAN_8IN32;
1085 default:
1086 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1087 }
1088 } else {
1089 return V_028C70_ENDIAN_NONE;
1090 }
1091 }
1092
1093 /* Returns the size in bits of the widest component of a CB format */
1094 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1095 {
1096 switch(colorformat) {
1097 case V_028C70_COLOR_4_4_4_4:
1098 return 4;
1099
1100 case V_028C70_COLOR_1_5_5_5:
1101 case V_028C70_COLOR_5_5_5_1:
1102 return 5;
1103
1104 case V_028C70_COLOR_5_6_5:
1105 return 6;
1106
1107 case V_028C70_COLOR_8:
1108 case V_028C70_COLOR_8_8:
1109 case V_028C70_COLOR_8_8_8_8:
1110 return 8;
1111
1112 case V_028C70_COLOR_10_10_10_2:
1113 case V_028C70_COLOR_2_10_10_10:
1114 return 10;
1115
1116 case V_028C70_COLOR_10_11_11:
1117 case V_028C70_COLOR_11_11_10:
1118 return 11;
1119
1120 case V_028C70_COLOR_16:
1121 case V_028C70_COLOR_16_16:
1122 case V_028C70_COLOR_16_16_16_16:
1123 return 16;
1124
1125 case V_028C70_COLOR_8_24:
1126 case V_028C70_COLOR_24_8:
1127 return 24;
1128
1129 case V_028C70_COLOR_32:
1130 case V_028C70_COLOR_32_32:
1131 case V_028C70_COLOR_32_32_32_32:
1132 case V_028C70_COLOR_X24_8_32_FLOAT:
1133 return 32;
1134 }
1135
1136 assert(!"Unknown maximum component size");
1137 return 0;
1138 }
1139
1140 static uint32_t si_translate_dbformat(enum pipe_format format)
1141 {
1142 switch (format) {
1143 case PIPE_FORMAT_Z16_UNORM:
1144 return V_028040_Z_16;
1145 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1146 case PIPE_FORMAT_X8Z24_UNORM:
1147 case PIPE_FORMAT_Z24X8_UNORM:
1148 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1149 return V_028040_Z_24; /* deprecated on SI */
1150 case PIPE_FORMAT_Z32_FLOAT:
1151 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1152 return V_028040_Z_32_FLOAT;
1153 default:
1154 return V_028040_Z_INVALID;
1155 }
1156 }
1157
1158 /*
1159 * Texture translation
1160 */
1161
1162 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1163 enum pipe_format format,
1164 const struct util_format_description *desc,
1165 int first_non_void)
1166 {
1167 boolean uniform = TRUE;
1168 int i;
1169
1170 /* Colorspace (return non-RGB formats directly). */
1171 switch (desc->colorspace) {
1172 /* Depth stencil formats */
1173 case UTIL_FORMAT_COLORSPACE_ZS:
1174 switch (format) {
1175 case PIPE_FORMAT_Z16_UNORM:
1176 return V_008F14_IMG_DATA_FORMAT_16;
1177 case PIPE_FORMAT_X24S8_UINT:
1178 case PIPE_FORMAT_Z24X8_UNORM:
1179 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1180 return V_008F14_IMG_DATA_FORMAT_8_24;
1181 case PIPE_FORMAT_X8Z24_UNORM:
1182 case PIPE_FORMAT_S8X24_UINT:
1183 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1184 return V_008F14_IMG_DATA_FORMAT_24_8;
1185 case PIPE_FORMAT_S8_UINT:
1186 return V_008F14_IMG_DATA_FORMAT_8;
1187 case PIPE_FORMAT_Z32_FLOAT:
1188 return V_008F14_IMG_DATA_FORMAT_32;
1189 case PIPE_FORMAT_X32_S8X24_UINT:
1190 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1191 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1192 default:
1193 goto out_unknown;
1194 }
1195
1196 case UTIL_FORMAT_COLORSPACE_YUV:
1197 goto out_unknown; /* TODO */
1198
1199 case UTIL_FORMAT_COLORSPACE_SRGB:
1200 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1201 goto out_unknown;
1202 break;
1203
1204 default:
1205 break;
1206 }
1207
1208 /* TODO compressed formats */
1209
1210 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1211 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1212 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1213 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1214 }
1215
1216 /* R8G8Bx_SNORM - TODO CxV8U8 */
1217
1218 /* See whether the components are of the same size. */
1219 for (i = 1; i < desc->nr_channels; i++) {
1220 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1221 }
1222
1223 /* Non-uniform formats. */
1224 if (!uniform) {
1225 switch(desc->nr_channels) {
1226 case 3:
1227 if (desc->channel[0].size == 5 &&
1228 desc->channel[1].size == 6 &&
1229 desc->channel[2].size == 5) {
1230 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1231 }
1232 goto out_unknown;
1233 case 4:
1234 if (desc->channel[0].size == 5 &&
1235 desc->channel[1].size == 5 &&
1236 desc->channel[2].size == 5 &&
1237 desc->channel[3].size == 1) {
1238 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1239 }
1240 if (desc->channel[0].size == 10 &&
1241 desc->channel[1].size == 10 &&
1242 desc->channel[2].size == 10 &&
1243 desc->channel[3].size == 2) {
1244 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1245 }
1246 goto out_unknown;
1247 }
1248 goto out_unknown;
1249 }
1250
1251 if (first_non_void < 0 || first_non_void > 3)
1252 goto out_unknown;
1253
1254 /* uniform formats */
1255 switch (desc->channel[first_non_void].size) {
1256 case 4:
1257 switch (desc->nr_channels) {
1258 #if 0 /* Not supported for render targets */
1259 case 2:
1260 return V_008F14_IMG_DATA_FORMAT_4_4;
1261 #endif
1262 case 4:
1263 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1264 }
1265 break;
1266 case 8:
1267 switch (desc->nr_channels) {
1268 case 1:
1269 return V_008F14_IMG_DATA_FORMAT_8;
1270 case 2:
1271 return V_008F14_IMG_DATA_FORMAT_8_8;
1272 case 4:
1273 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1274 }
1275 break;
1276 case 16:
1277 switch (desc->nr_channels) {
1278 case 1:
1279 return V_008F14_IMG_DATA_FORMAT_16;
1280 case 2:
1281 return V_008F14_IMG_DATA_FORMAT_16_16;
1282 case 4:
1283 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1284 }
1285 break;
1286 case 32:
1287 switch (desc->nr_channels) {
1288 case 1:
1289 return V_008F14_IMG_DATA_FORMAT_32;
1290 case 2:
1291 return V_008F14_IMG_DATA_FORMAT_32_32;
1292 #if 0 /* Not supported for render targets */
1293 case 3:
1294 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1295 #endif
1296 case 4:
1297 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1298 }
1299 }
1300
1301 out_unknown:
1302 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1303 return ~0;
1304 }
1305
1306 static unsigned si_tex_wrap(unsigned wrap)
1307 {
1308 switch (wrap) {
1309 default:
1310 case PIPE_TEX_WRAP_REPEAT:
1311 return V_008F30_SQ_TEX_WRAP;
1312 case PIPE_TEX_WRAP_CLAMP:
1313 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1314 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1315 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1316 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1317 return V_008F30_SQ_TEX_CLAMP_BORDER;
1318 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1319 return V_008F30_SQ_TEX_MIRROR;
1320 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1321 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1322 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1323 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1324 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1325 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1326 }
1327 }
1328
1329 static unsigned si_tex_filter(unsigned filter)
1330 {
1331 switch (filter) {
1332 default:
1333 case PIPE_TEX_FILTER_NEAREST:
1334 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1335 case PIPE_TEX_FILTER_LINEAR:
1336 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1337 }
1338 }
1339
1340 static unsigned si_tex_mipfilter(unsigned filter)
1341 {
1342 switch (filter) {
1343 case PIPE_TEX_MIPFILTER_NEAREST:
1344 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1345 case PIPE_TEX_MIPFILTER_LINEAR:
1346 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1347 default:
1348 case PIPE_TEX_MIPFILTER_NONE:
1349 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1350 }
1351 }
1352
1353 static unsigned si_tex_compare(unsigned compare)
1354 {
1355 switch (compare) {
1356 default:
1357 case PIPE_FUNC_NEVER:
1358 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1359 case PIPE_FUNC_LESS:
1360 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1361 case PIPE_FUNC_EQUAL:
1362 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1363 case PIPE_FUNC_LEQUAL:
1364 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1365 case PIPE_FUNC_GREATER:
1366 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1367 case PIPE_FUNC_NOTEQUAL:
1368 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1369 case PIPE_FUNC_GEQUAL:
1370 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1371 case PIPE_FUNC_ALWAYS:
1372 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1373 }
1374 }
1375
1376 static unsigned si_tex_dim(unsigned dim)
1377 {
1378 switch (dim) {
1379 default:
1380 case PIPE_TEXTURE_1D:
1381 return V_008F1C_SQ_RSRC_IMG_1D;
1382 case PIPE_TEXTURE_1D_ARRAY:
1383 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1384 case PIPE_TEXTURE_2D:
1385 case PIPE_TEXTURE_RECT:
1386 return V_008F1C_SQ_RSRC_IMG_2D;
1387 case PIPE_TEXTURE_2D_ARRAY:
1388 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1389 case PIPE_TEXTURE_3D:
1390 return V_008F1C_SQ_RSRC_IMG_3D;
1391 case PIPE_TEXTURE_CUBE:
1392 return V_008F1C_SQ_RSRC_IMG_CUBE;
1393 }
1394 }
1395
1396 /*
1397 * Format support testing
1398 */
1399
1400 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1401 {
1402 return si_translate_texformat(screen, format, util_format_description(format),
1403 util_format_get_first_non_void_channel(format)) != ~0U;
1404 }
1405
1406 static uint32_t si_translate_vertexformat(struct pipe_screen *screen,
1407 enum pipe_format format,
1408 const struct util_format_description *desc,
1409 int first_non_void)
1410 {
1411 unsigned type = desc->channel[first_non_void].type;
1412 int i;
1413
1414 if (type == UTIL_FORMAT_TYPE_FIXED)
1415 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1416
1417 /* See whether the components are of the same size. */
1418 for (i = 0; i < desc->nr_channels; i++) {
1419 if (desc->channel[first_non_void].size != desc->channel[i].size)
1420 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1421 }
1422
1423 switch (desc->channel[first_non_void].size) {
1424 case 8:
1425 switch (desc->nr_channels) {
1426 case 1:
1427 return V_008F0C_BUF_DATA_FORMAT_8;
1428 case 2:
1429 return V_008F0C_BUF_DATA_FORMAT_8_8;
1430 case 3:
1431 case 4:
1432 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1433 }
1434 break;
1435 case 16:
1436 switch (desc->nr_channels) {
1437 case 1:
1438 return V_008F0C_BUF_DATA_FORMAT_16;
1439 case 2:
1440 return V_008F0C_BUF_DATA_FORMAT_16_16;
1441 case 3:
1442 case 4:
1443 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1444 }
1445 break;
1446 case 32:
1447 if (type != UTIL_FORMAT_TYPE_FLOAT)
1448 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1449
1450 switch (desc->nr_channels) {
1451 case 1:
1452 return V_008F0C_BUF_DATA_FORMAT_32;
1453 case 2:
1454 return V_008F0C_BUF_DATA_FORMAT_32_32;
1455 case 3:
1456 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1457 case 4:
1458 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1459 }
1460 break;
1461 }
1462
1463 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1464 }
1465
1466 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1467 {
1468 const struct util_format_description *desc;
1469 int first_non_void;
1470 unsigned data_format;
1471
1472 desc = util_format_description(format);
1473 first_non_void = util_format_get_first_non_void_channel(format);
1474 data_format = si_translate_vertexformat(screen, format, desc, first_non_void);
1475 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1476 }
1477
1478 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1479 {
1480 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1481 si_translate_colorswap(format) != ~0U;
1482 }
1483
1484 static bool si_is_zs_format_supported(enum pipe_format format)
1485 {
1486 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1487 }
1488
1489 boolean si_is_format_supported(struct pipe_screen *screen,
1490 enum pipe_format format,
1491 enum pipe_texture_target target,
1492 unsigned sample_count,
1493 unsigned usage)
1494 {
1495 unsigned retval = 0;
1496
1497 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1498 R600_ERR("r600: unsupported texture type %d\n", target);
1499 return FALSE;
1500 }
1501
1502 if (!util_format_is_supported(format, usage))
1503 return FALSE;
1504
1505 /* Multisample */
1506 if (sample_count > 1)
1507 return FALSE;
1508
1509 if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
1510 si_is_sampler_format_supported(screen, format)) {
1511 retval |= PIPE_BIND_SAMPLER_VIEW;
1512 }
1513
1514 if ((usage & (PIPE_BIND_RENDER_TARGET |
1515 PIPE_BIND_DISPLAY_TARGET |
1516 PIPE_BIND_SCANOUT |
1517 PIPE_BIND_SHARED)) &&
1518 si_is_colorbuffer_format_supported(format)) {
1519 retval |= usage &
1520 (PIPE_BIND_RENDER_TARGET |
1521 PIPE_BIND_DISPLAY_TARGET |
1522 PIPE_BIND_SCANOUT |
1523 PIPE_BIND_SHARED);
1524 }
1525
1526 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1527 si_is_zs_format_supported(format)) {
1528 retval |= PIPE_BIND_DEPTH_STENCIL;
1529 }
1530
1531 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1532 si_is_vertex_format_supported(screen, format)) {
1533 retval |= PIPE_BIND_VERTEX_BUFFER;
1534 }
1535
1536 if (usage & PIPE_BIND_TRANSFER_READ)
1537 retval |= PIPE_BIND_TRANSFER_READ;
1538 if (usage & PIPE_BIND_TRANSFER_WRITE)
1539 retval |= PIPE_BIND_TRANSFER_WRITE;
1540
1541 return retval == usage;
1542 }
1543
1544 static unsigned si_tile_mode_index(struct r600_resource_texture *rtex, unsigned level)
1545 {
1546 if (util_format_is_depth_or_stencil(rtex->real_format)) {
1547 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_1D) {
1548 return 4;
1549 } else if (rtex->surface.level[level].mode == RADEON_SURF_MODE_2D) {
1550 switch (rtex->real_format) {
1551 case PIPE_FORMAT_Z16_UNORM:
1552 return 5;
1553 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1554 case PIPE_FORMAT_X8Z24_UNORM:
1555 case PIPE_FORMAT_Z24X8_UNORM:
1556 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1557 case PIPE_FORMAT_Z32_FLOAT:
1558 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1559 return 6;
1560 default:
1561 return 7;
1562 }
1563 }
1564 }
1565
1566 switch (rtex->surface.level[level].mode) {
1567 default:
1568 assert(!"Invalid surface mode");
1569 /* Fall through */
1570 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1571 return 8;
1572 case RADEON_SURF_MODE_1D:
1573 if (rtex->surface.flags & RADEON_SURF_SCANOUT)
1574 return 9;
1575 else
1576 return 13;
1577 case RADEON_SURF_MODE_2D:
1578 if (rtex->surface.flags & RADEON_SURF_SCANOUT) {
1579 switch (util_format_get_blocksize(rtex->real_format)) {
1580 case 1:
1581 return 10;
1582 case 2:
1583 return 11;
1584 default:
1585 assert(!"Invalid block size");
1586 /* Fall through */
1587 case 4:
1588 return 12;
1589 }
1590 } else {
1591 switch (util_format_get_blocksize(rtex->real_format)) {
1592 case 1:
1593 return 14;
1594 case 2:
1595 return 15;
1596 case 4:
1597 return 16;
1598 case 8:
1599 return 17;
1600 default:
1601 return 13;
1602 }
1603 }
1604 }
1605 }
1606
1607 /*
1608 * framebuffer handling
1609 */
1610
1611 static void si_cb(struct r600_context *rctx, struct si_pm4_state *pm4,
1612 const struct pipe_framebuffer_state *state, int cb)
1613 {
1614 struct r600_resource_texture *rtex;
1615 struct r600_surface *surf;
1616 unsigned level = state->cbufs[cb]->u.tex.level;
1617 unsigned pitch, slice;
1618 unsigned color_info, color_attrib;
1619 unsigned tile_mode_index;
1620 unsigned format, swap, ntype, endian;
1621 uint64_t offset;
1622 const struct util_format_description *desc;
1623 int i;
1624 unsigned blend_clamp = 0, blend_bypass = 0;
1625 unsigned max_comp_size;
1626
1627 surf = (struct r600_surface *)state->cbufs[cb];
1628 rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1629
1630 offset = rtex->surface.level[level].offset;
1631 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1632 offset += rtex->surface.level[level].slice_size *
1633 state->cbufs[cb]->u.tex.first_layer;
1634 }
1635 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1636 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1637 if (slice) {
1638 slice = slice - 1;
1639 }
1640
1641 tile_mode_index = si_tile_mode_index(rtex, level);
1642
1643 desc = util_format_description(surf->base.format);
1644 for (i = 0; i < 4; i++) {
1645 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1646 break;
1647 }
1648 }
1649 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1650 ntype = V_028C70_NUMBER_FLOAT;
1651 } else {
1652 ntype = V_028C70_NUMBER_UNORM;
1653 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1654 ntype = V_028C70_NUMBER_SRGB;
1655 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1656 if (desc->channel[i].pure_integer) {
1657 ntype = V_028C70_NUMBER_SINT;
1658 } else {
1659 assert(desc->channel[i].normalized);
1660 ntype = V_028C70_NUMBER_SNORM;
1661 }
1662 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1663 if (desc->channel[i].pure_integer) {
1664 ntype = V_028C70_NUMBER_UINT;
1665 } else {
1666 assert(desc->channel[i].normalized);
1667 ntype = V_028C70_NUMBER_UNORM;
1668 }
1669 }
1670 }
1671
1672 format = si_translate_colorformat(surf->base.format);
1673 if (format == V_028C70_COLOR_INVALID) {
1674 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1675 }
1676 assert(format != V_028C70_COLOR_INVALID);
1677 swap = si_translate_colorswap(surf->base.format);
1678 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1679 endian = V_028C70_ENDIAN_NONE;
1680 } else {
1681 endian = si_colorformat_endian_swap(format);
1682 }
1683
1684 /* blend clamp should be set for all NORM/SRGB types */
1685 if (ntype == V_028C70_NUMBER_UNORM ||
1686 ntype == V_028C70_NUMBER_SNORM ||
1687 ntype == V_028C70_NUMBER_SRGB)
1688 blend_clamp = 1;
1689
1690 /* set blend bypass according to docs if SINT/UINT or
1691 8/24 COLOR variants */
1692 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1693 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1694 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1695 blend_clamp = 0;
1696 blend_bypass = 1;
1697 }
1698
1699 color_info = S_028C70_FORMAT(format) |
1700 S_028C70_COMP_SWAP(swap) |
1701 S_028C70_BLEND_CLAMP(blend_clamp) |
1702 S_028C70_BLEND_BYPASS(blend_bypass) |
1703 S_028C70_NUMBER_TYPE(ntype) |
1704 S_028C70_ENDIAN(endian);
1705
1706 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1707 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1708
1709 offset += r600_resource_va(rctx->context.screen, state->cbufs[cb]->texture);
1710 offset >>= 8;
1711
1712 /* FIXME handle enabling of CB beyond BASE8 which has different offset */
1713 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1714 si_pm4_set_reg(pm4, R_028C60_CB_COLOR0_BASE + cb * 0x3C, offset);
1715 si_pm4_set_reg(pm4, R_028C64_CB_COLOR0_PITCH + cb * 0x3C, S_028C64_TILE_MAX(pitch));
1716 si_pm4_set_reg(pm4, R_028C68_CB_COLOR0_SLICE + cb * 0x3C, S_028C68_TILE_MAX(slice));
1717
1718 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1719 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C, 0x00000000);
1720 } else {
1721 si_pm4_set_reg(pm4, R_028C6C_CB_COLOR0_VIEW + cb * 0x3C,
1722 S_028C6C_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1723 S_028C6C_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1724 }
1725 si_pm4_set_reg(pm4, R_028C70_CB_COLOR0_INFO + cb * 0x3C, color_info);
1726 si_pm4_set_reg(pm4, R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C, color_attrib);
1727
1728 /* Determine pixel shader export format */
1729 max_comp_size = si_colorformat_max_comp_size(format);
1730 if (ntype == V_028C70_NUMBER_SRGB ||
1731 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1732 max_comp_size <= 10) ||
1733 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1734 rctx->export_16bpc |= 1 << cb;
1735 }
1736 }
1737
1738 static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
1739 const struct pipe_framebuffer_state *state)
1740 {
1741 struct r600_resource_texture *rtex;
1742 struct r600_surface *surf;
1743 unsigned level, pitch, slice, format, tile_mode_index;
1744 uint32_t z_info, s_info;
1745 uint64_t z_offs, s_offs;
1746
1747 if (state->zsbuf == NULL) {
1748 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1749 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1750 return;
1751 }
1752
1753 surf = (struct r600_surface *)state->zsbuf;
1754 level = surf->base.u.tex.level;
1755 rtex = (struct r600_resource_texture*)surf->base.texture;
1756
1757 format = si_translate_dbformat(rtex->real_format);
1758
1759 if (format == V_028040_Z_INVALID) {
1760 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->real_format);
1761 }
1762 assert(format != V_028040_Z_INVALID);
1763
1764 s_offs = z_offs = r600_resource_va(rctx->context.screen, surf->base.texture);
1765 z_offs += rtex->surface.level[level].offset;
1766 s_offs += rtex->surface.stencil_level[level].offset;
1767
1768 z_offs >>= 8;
1769 s_offs >>= 8;
1770
1771 pitch = (rtex->surface.level[level].nblk_x / 8) - 1;
1772 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1773 if (slice) {
1774 slice = slice - 1;
1775 }
1776
1777 z_info = S_028040_FORMAT(format);
1778 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1779 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1780 else
1781 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1782
1783 tile_mode_index = si_tile_mode_index(rtex, level);
1784 if (tile_mode_index < 4 || tile_mode_index > 7) {
1785 R600_ERR("Invalid DB tiling mode %d!\n",
1786 rtex->surface.level[level].mode);
1787 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, S_028040_FORMAT(V_028040_Z_INVALID));
1788 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, S_028044_FORMAT(V_028044_STENCIL_INVALID));
1789 return;
1790 }
1791 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1792 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1793
1794 si_pm4_set_reg(pm4, R_028008_DB_DEPTH_VIEW,
1795 S_028008_SLICE_START(state->zsbuf->u.tex.first_layer) |
1796 S_028008_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1797
1798 si_pm4_set_reg(pm4, R_02803C_DB_DEPTH_INFO, S_02803C_ADDR5_SWIZZLE_MASK(1));
1799 si_pm4_set_reg(pm4, R_028040_DB_Z_INFO, z_info);
1800 si_pm4_set_reg(pm4, R_028044_DB_STENCIL_INFO, s_info);
1801
1802 si_pm4_add_bo(pm4, &rtex->resource, RADEON_USAGE_READWRITE);
1803 si_pm4_set_reg(pm4, R_028048_DB_Z_READ_BASE, z_offs);
1804 si_pm4_set_reg(pm4, R_02804C_DB_STENCIL_READ_BASE, s_offs);
1805 si_pm4_set_reg(pm4, R_028050_DB_Z_WRITE_BASE, z_offs);
1806 si_pm4_set_reg(pm4, R_028054_DB_STENCIL_WRITE_BASE, s_offs);
1807
1808 si_pm4_set_reg(pm4, R_028058_DB_DEPTH_SIZE, S_028058_PITCH_TILE_MAX(pitch));
1809 si_pm4_set_reg(pm4, R_02805C_DB_DEPTH_SLICE, S_02805C_SLICE_TILE_MAX(slice));
1810 }
1811
1812 static void si_set_framebuffer_state(struct pipe_context *ctx,
1813 const struct pipe_framebuffer_state *state)
1814 {
1815 struct r600_context *rctx = (struct r600_context *)ctx;
1816 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
1817 uint32_t shader_mask, tl, br;
1818 int tl_x, tl_y, br_x, br_y;
1819
1820 if (pm4 == NULL)
1821 return;
1822
1823 si_pm4_inval_fb_cache(pm4, state->nr_cbufs);
1824
1825 if (state->zsbuf)
1826 si_pm4_inval_zsbuf_cache(pm4);
1827
1828 util_copy_framebuffer_state(&rctx->framebuffer, state);
1829
1830 /* build states */
1831 rctx->export_16bpc = 0;
1832 for (int i = 0; i < state->nr_cbufs; i++) {
1833 si_cb(rctx, pm4, state, i);
1834 }
1835 assert(!(rctx->export_16bpc & ~0xff));
1836 si_db(rctx, pm4, state);
1837
1838 shader_mask = 0;
1839 for (int i = 0; i < state->nr_cbufs; i++) {
1840 shader_mask |= 0xf << (i * 4);
1841 }
1842 tl_x = 0;
1843 tl_y = 0;
1844 br_x = state->width;
1845 br_y = state->height;
1846
1847 tl = S_028240_TL_X(tl_x) | S_028240_TL_Y(tl_y);
1848 br = S_028244_BR_X(br_x) | S_028244_BR_Y(br_y);
1849
1850 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, tl);
1851 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR, br);
1852 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1853 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1854 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, tl);
1855 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR, br);
1856 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1857 si_pm4_set_reg(pm4, R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1858 si_pm4_set_reg(pm4, R_028200_PA_SC_WINDOW_OFFSET, 0x00000000);
1859 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
1860 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader_mask);
1861 si_pm4_set_reg(pm4, R_028BE0_PA_SC_AA_CONFIG, 0x00000000);
1862
1863 si_pm4_set_state(rctx, framebuffer, pm4);
1864 si_update_fb_rs_state(rctx);
1865 si_update_fb_blend_state(rctx);
1866 }
1867
1868 /*
1869 * shaders
1870 */
1871
1872 /* Compute the key for the hw shader variant */
1873 static INLINE struct si_shader_key si_shader_selector_key(struct pipe_context *ctx,
1874 struct si_pipe_shader_selector *sel)
1875 {
1876 struct r600_context *rctx = (struct r600_context *)ctx;
1877 struct si_shader_key key;
1878 memset(&key, 0, sizeof(key));
1879
1880 if (sel->type == PIPE_SHADER_FRAGMENT) {
1881 if (sel->fs_write_all)
1882 key.nr_cbufs = rctx->framebuffer.nr_cbufs;
1883 key.export_16bpc = rctx->export_16bpc;
1884 if (rctx->queued.named.rasterizer) {
1885 key.color_two_side = rctx->queued.named.rasterizer->two_side;
1886 key.flatshade = rctx->queued.named.rasterizer->flatshade;
1887 }
1888 if (rctx->queued.named.dsa) {
1889 key.alpha_func = rctx->queued.named.dsa->alpha_func;
1890 key.alpha_ref = rctx->queued.named.dsa->alpha_ref;
1891 } else {
1892 key.alpha_func = PIPE_FUNC_ALWAYS;
1893 }
1894 }
1895
1896 return key;
1897 }
1898
1899 /* Select the hw shader variant depending on the current state.
1900 * (*dirty) is set to 1 if current variant was changed */
1901 int si_shader_select(struct pipe_context *ctx,
1902 struct si_pipe_shader_selector *sel,
1903 unsigned *dirty)
1904 {
1905 struct si_shader_key key;
1906 struct si_pipe_shader * shader = NULL;
1907 int r;
1908
1909 key = si_shader_selector_key(ctx, sel);
1910
1911 /* Check if we don't need to change anything.
1912 * This path is also used for most shaders that don't need multiple
1913 * variants, it will cost just a computation of the key and this
1914 * test. */
1915 if (likely(sel->current && memcmp(&sel->current->key, &key, sizeof(key)) == 0)) {
1916 return 0;
1917 }
1918
1919 /* lookup if we have other variants in the list */
1920 if (sel->num_shaders > 1) {
1921 struct si_pipe_shader *p = sel->current, *c = p->next_variant;
1922
1923 while (c && memcmp(&c->key, &key, sizeof(key)) != 0) {
1924 p = c;
1925 c = c->next_variant;
1926 }
1927
1928 if (c) {
1929 p->next_variant = c->next_variant;
1930 shader = c;
1931 }
1932 }
1933
1934 if (unlikely(!shader)) {
1935 shader = CALLOC(1, sizeof(struct si_pipe_shader));
1936 shader->selector = sel;
1937
1938 r = si_pipe_shader_create(ctx, shader, key);
1939 if (unlikely(r)) {
1940 R600_ERR("Failed to build shader variant (type=%u) %d\n",
1941 sel->type, r);
1942 sel->current = NULL;
1943 FREE(shader);
1944 return r;
1945 }
1946
1947 /* We don't know the value of fs_write_all property until we built
1948 * at least one variant, so we may need to recompute the key (include
1949 * rctx->framebuffer.nr_cbufs) after building first variant. */
1950 if (sel->type == PIPE_SHADER_FRAGMENT &&
1951 sel->num_shaders == 0 &&
1952 shader->shader.fs_write_all) {
1953 sel->fs_write_all = 1;
1954 key = si_shader_selector_key(ctx, sel);
1955 }
1956
1957 shader->key = key;
1958 sel->num_shaders++;
1959 }
1960
1961 if (dirty)
1962 *dirty = 1;
1963
1964 shader->next_variant = sel->current;
1965 sel->current = shader;
1966
1967 return 0;
1968 }
1969
1970 static void *si_create_shader_state(struct pipe_context *ctx,
1971 const struct pipe_shader_state *state,
1972 unsigned pipe_shader_type)
1973 {
1974 struct si_pipe_shader_selector *sel = CALLOC_STRUCT(si_pipe_shader_selector);
1975 int r;
1976
1977 sel->type = pipe_shader_type;
1978 sel->tokens = tgsi_dup_tokens(state->tokens);
1979 sel->so = state->stream_output;
1980
1981 r = si_shader_select(ctx, sel, NULL);
1982 if (r) {
1983 free(sel);
1984 return NULL;
1985 }
1986
1987 return sel;
1988 }
1989
1990 static void *si_create_fs_state(struct pipe_context *ctx,
1991 const struct pipe_shader_state *state)
1992 {
1993 return si_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
1994 }
1995
1996 static void *si_create_vs_state(struct pipe_context *ctx,
1997 const struct pipe_shader_state *state)
1998 {
1999 return si_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
2000 }
2001
2002 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2003 {
2004 struct r600_context *rctx = (struct r600_context *)ctx;
2005 struct si_pipe_shader_selector *sel = state;
2006
2007 if (rctx->vs_shader == sel)
2008 return;
2009
2010 rctx->vs_shader = sel;
2011
2012 if (sel && sel->current)
2013 si_pm4_bind_state(rctx, vs, sel->current->pm4);
2014 else
2015 si_pm4_bind_state(rctx, vs, rctx->dummy_pixel_shader->pm4);
2016 }
2017
2018 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
2019 {
2020 struct r600_context *rctx = (struct r600_context *)ctx;
2021 struct si_pipe_shader_selector *sel = state;
2022
2023 if (rctx->ps_shader == sel)
2024 return;
2025
2026 rctx->ps_shader = sel;
2027
2028 if (sel && sel->current)
2029 si_pm4_bind_state(rctx, ps, sel->current->pm4);
2030 else
2031 si_pm4_bind_state(rctx, ps, rctx->dummy_pixel_shader->pm4);
2032 }
2033
2034 static void si_delete_shader_selector(struct pipe_context *ctx,
2035 struct si_pipe_shader_selector *sel)
2036 {
2037 struct r600_context *rctx = (struct r600_context *)ctx;
2038 struct si_pipe_shader *p = sel->current, *c;
2039
2040 while (p) {
2041 c = p->next_variant;
2042 si_pm4_delete_state(rctx, vs, p->pm4);
2043 si_pipe_shader_destroy(ctx, p);
2044 free(p);
2045 p = c;
2046 }
2047
2048 free(sel->tokens);
2049 free(sel);
2050 }
2051
2052 static void si_delete_vs_shader(struct pipe_context *ctx, void *state)
2053 {
2054 struct r600_context *rctx = (struct r600_context *)ctx;
2055 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2056
2057 if (rctx->vs_shader == sel) {
2058 rctx->vs_shader = NULL;
2059 }
2060
2061 si_delete_shader_selector(ctx, sel);
2062 }
2063
2064 static void si_delete_ps_shader(struct pipe_context *ctx, void *state)
2065 {
2066 struct r600_context *rctx = (struct r600_context *)ctx;
2067 struct si_pipe_shader_selector *sel = (struct si_pipe_shader_selector *)state;
2068
2069 if (rctx->ps_shader == sel) {
2070 rctx->ps_shader = NULL;
2071 }
2072
2073 si_delete_shader_selector(ctx, sel);
2074 }
2075
2076 /*
2077 * Samplers
2078 */
2079
2080 static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx,
2081 struct pipe_resource *texture,
2082 const struct pipe_sampler_view *state)
2083 {
2084 struct si_pipe_sampler_view *view = CALLOC_STRUCT(si_pipe_sampler_view);
2085 struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
2086 const struct util_format_description *desc;
2087 unsigned format, num_format;
2088 uint32_t pitch = 0;
2089 unsigned char state_swizzle[4], swizzle[4];
2090 unsigned height, depth, width;
2091 enum pipe_format pipe_format = state->format;
2092 struct radeon_surface_level *surflevel;
2093 int first_non_void;
2094 uint64_t va;
2095
2096 if (view == NULL)
2097 return NULL;
2098
2099 /* initialize base object */
2100 view->base = *state;
2101 view->base.texture = NULL;
2102 pipe_reference(NULL, &texture->reference);
2103 view->base.texture = texture;
2104 view->base.reference.count = 1;
2105 view->base.context = ctx;
2106
2107 state_swizzle[0] = state->swizzle_r;
2108 state_swizzle[1] = state->swizzle_g;
2109 state_swizzle[2] = state->swizzle_b;
2110 state_swizzle[3] = state->swizzle_a;
2111
2112 surflevel = tmp->surface.level;
2113
2114 /* Texturing with separate depth and stencil. */
2115 if (tmp->is_depth && !tmp->is_flushing_texture) {
2116 switch (pipe_format) {
2117 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2118 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2119 break;
2120 case PIPE_FORMAT_X8Z24_UNORM:
2121 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2122 /* Z24 is always stored like this. */
2123 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2124 break;
2125 case PIPE_FORMAT_X24S8_UINT:
2126 case PIPE_FORMAT_S8X24_UINT:
2127 case PIPE_FORMAT_X32_S8X24_UINT:
2128 pipe_format = PIPE_FORMAT_S8_UINT;
2129 surflevel = tmp->surface.stencil_level;
2130 break;
2131 default:;
2132 }
2133 }
2134
2135 desc = util_format_description(pipe_format);
2136
2137 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2138 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2139 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2140
2141 switch (pipe_format) {
2142 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2143 case PIPE_FORMAT_X24S8_UINT:
2144 case PIPE_FORMAT_X32_S8X24_UINT:
2145 case PIPE_FORMAT_X8Z24_UNORM:
2146 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2147 break;
2148 default:
2149 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2150 }
2151 } else {
2152 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2153 }
2154
2155 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2156
2157 switch (pipe_format) {
2158 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2159 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2160 break;
2161 default:
2162 if (first_non_void < 0) {
2163 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2164 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2165 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2166 } else {
2167 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2168
2169 switch (desc->channel[first_non_void].type) {
2170 case UTIL_FORMAT_TYPE_FLOAT:
2171 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2172 break;
2173 case UTIL_FORMAT_TYPE_SIGNED:
2174 if (desc->channel[first_non_void].normalized)
2175 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2176 else if (desc->channel[first_non_void].pure_integer)
2177 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2178 else
2179 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2180 break;
2181 case UTIL_FORMAT_TYPE_UNSIGNED:
2182 if (desc->channel[first_non_void].normalized)
2183 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2184 else if (desc->channel[first_non_void].pure_integer)
2185 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2186 else
2187 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2188 }
2189 }
2190 }
2191
2192 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2193 if (format == ~0) {
2194 format = 0;
2195 }
2196
2197 view->resource = &tmp->resource;
2198
2199 /* not supported any more */
2200 //endian = si_colorformat_endian_swap(format);
2201
2202 width = surflevel[0].npix_x;
2203 height = surflevel[0].npix_y;
2204 depth = surflevel[0].npix_z;
2205 pitch = surflevel[0].nblk_x * util_format_get_blockwidth(pipe_format);
2206
2207 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2208 height = 1;
2209 depth = texture->array_size;
2210 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2211 depth = texture->array_size;
2212 }
2213
2214 va = r600_resource_va(ctx->screen, texture);
2215 va += surflevel[0].offset;
2216 view->state[0] = va >> 8;
2217 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2218 S_008F14_DATA_FORMAT(format) |
2219 S_008F14_NUM_FORMAT(num_format));
2220 view->state[2] = (S_008F18_WIDTH(width - 1) |
2221 S_008F18_HEIGHT(height - 1));
2222 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2223 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2224 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2225 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2226 S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
2227 S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
2228 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0)) |
2229 S_008F1C_POW2_PAD(texture->last_level > 0) |
2230 S_008F1C_TYPE(si_tex_dim(texture->target)));
2231 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2232 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2233 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2234 view->state[6] = 0;
2235 view->state[7] = 0;
2236
2237 return &view->base;
2238 }
2239
2240 static void si_sampler_view_destroy(struct pipe_context *ctx,
2241 struct pipe_sampler_view *state)
2242 {
2243 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
2244
2245 pipe_resource_reference(&state->texture, NULL);
2246 FREE(resource);
2247 }
2248
2249 static void *si_create_sampler_state(struct pipe_context *ctx,
2250 const struct pipe_sampler_state *state)
2251 {
2252 struct si_pipe_sampler_state *rstate = CALLOC_STRUCT(si_pipe_sampler_state);
2253 union util_color uc;
2254 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2255 unsigned border_color_type;
2256
2257 if (rstate == NULL) {
2258 return NULL;
2259 }
2260
2261 util_pack_color(state->border_color.f, PIPE_FORMAT_A8R8G8B8_UNORM, &uc);
2262 switch (uc.ui) {
2263 case 0x000000FF:
2264 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2265 break;
2266 case 0x00000000:
2267 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2268 break;
2269 case 0xFFFFFFFF:
2270 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2271 break;
2272 default: /* Use border color pointer */
2273 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2274 }
2275
2276 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2277 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2278 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2279 (state->max_anisotropy & 0x7) << 9 | /* XXX */
2280 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2281 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2282 aniso_flag_offset << 16 | /* XXX */
2283 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2284 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2285 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2286 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2287 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter)) |
2288 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter)) |
2289 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2290 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2291
2292 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2293 memcpy(rstate->border_color, state->border_color.f,
2294 sizeof(rstate->border_color));
2295 }
2296
2297 return rstate;
2298 }
2299
2300 static struct si_pm4_state *si_set_sampler_view(struct r600_context *rctx,
2301 unsigned count,
2302 struct pipe_sampler_view **views,
2303 struct r600_textures_info *samplers,
2304 unsigned user_data_reg)
2305 {
2306 struct si_pipe_sampler_view **resource = (struct si_pipe_sampler_view **)views;
2307 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2308 int i, j;
2309
2310 if (!count)
2311 goto out;
2312
2313 si_pm4_inval_texture_cache(pm4);
2314
2315 si_pm4_sh_data_begin(pm4);
2316 for (i = 0; i < count; i++) {
2317 pipe_sampler_view_reference(
2318 (struct pipe_sampler_view **)&samplers->views[i],
2319 views[i]);
2320
2321 if (views[i]) {
2322 struct r600_resource_texture *rtex =
2323 (struct r600_resource_texture*)views[i]->texture;
2324
2325 if (rtex->is_depth && !rtex->is_flushing_texture) {
2326 samplers->depth_texture_mask |= 1 << i;
2327 } else {
2328 samplers->depth_texture_mask &= ~(1 << i);
2329 }
2330
2331 si_pm4_add_bo(pm4, resource[i]->resource, RADEON_USAGE_READ);
2332 } else {
2333 samplers->depth_texture_mask &= ~(1 << i);
2334 }
2335
2336 for (j = 0; j < Elements(resource[i]->state); ++j) {
2337 si_pm4_sh_data_add(pm4, resource[i] ? resource[i]->state[j] : 0);
2338 }
2339 }
2340
2341 for (i = count; i < NUM_TEX_UNITS; i++) {
2342 if (samplers->views[i])
2343 pipe_sampler_view_reference((struct pipe_sampler_view **)&samplers->views[i], NULL);
2344 }
2345
2346 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_RESOURCE);
2347
2348 out:
2349 rctx->ps_samplers.n_views = count;
2350 return pm4;
2351 }
2352
2353 static void si_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
2354 struct pipe_sampler_view **views)
2355 {
2356 struct r600_context *rctx = (struct r600_context *)ctx;
2357 struct si_pm4_state *pm4;
2358
2359 pm4 = si_set_sampler_view(rctx, count, views, &rctx->vs_samplers,
2360 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2361 si_pm4_set_state(rctx, vs_sampler_views, pm4);
2362 }
2363
2364 static void si_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
2365 struct pipe_sampler_view **views)
2366 {
2367 struct r600_context *rctx = (struct r600_context *)ctx;
2368 struct si_pm4_state *pm4;
2369
2370 pm4 = si_set_sampler_view(rctx, count, views, &rctx->ps_samplers,
2371 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2372 si_pm4_set_state(rctx, ps_sampler_views, pm4);
2373 }
2374
2375 static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned count,
2376 void **states,
2377 struct r600_textures_info *samplers,
2378 unsigned user_data_reg)
2379 {
2380 struct si_pipe_sampler_state **rstates = (struct si_pipe_sampler_state **)states;
2381 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2382 uint32_t *border_color_table = NULL;
2383 int i, j;
2384
2385 if (!count)
2386 goto out;
2387
2388 si_pm4_inval_texture_cache(pm4);
2389
2390 si_pm4_sh_data_begin(pm4);
2391 for (i = 0; i < count; i++) {
2392 if (rstates[i] &&
2393 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2394 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2395 if (!rctx->border_color_table ||
2396 ((rctx->border_color_offset + count - i) &
2397 C_008F3C_BORDER_COLOR_PTR)) {
2398 si_resource_reference(&rctx->border_color_table, NULL);
2399 rctx->border_color_offset = 0;
2400
2401 rctx->border_color_table =
2402 si_resource_create_custom(&rctx->screen->screen,
2403 PIPE_USAGE_STAGING,
2404 4096 * 4 * 4);
2405 }
2406
2407 if (!border_color_table) {
2408 border_color_table =
2409 rctx->ws->buffer_map(rctx->border_color_table->cs_buf,
2410 rctx->cs,
2411 PIPE_TRANSFER_WRITE |
2412 PIPE_TRANSFER_UNSYNCHRONIZED);
2413 }
2414
2415 for (j = 0; j < 4; j++) {
2416 union fi border_color;
2417
2418 border_color.f = rstates[i]->border_color[j];
2419 border_color_table[4 * rctx->border_color_offset + j] =
2420 util_le32_to_cpu(border_color.i);
2421 }
2422
2423 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2424 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(rctx->border_color_offset++);
2425 }
2426
2427 for (j = 0; j < Elements(rstates[i]->val); ++j) {
2428 si_pm4_sh_data_add(pm4, rstates[i] ? rstates[i]->val[j] : 0);
2429 }
2430 }
2431 si_pm4_sh_data_end(pm4, user_data_reg, SI_SGPR_SAMPLER);
2432
2433 if (border_color_table) {
2434 uint64_t va_offset =
2435 r600_resource_va(&rctx->screen->screen,
2436 (void*)rctx->border_color_table);
2437
2438 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2439 rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf);
2440 si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ);
2441 }
2442
2443 memcpy(samplers->samplers, states, sizeof(void*) * count);
2444
2445 out:
2446 samplers->n_samplers = count;
2447 return pm4;
2448 }
2449
2450 static void si_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
2451 {
2452 struct r600_context *rctx = (struct r600_context *)ctx;
2453 struct si_pm4_state *pm4;
2454
2455 pm4 = si_bind_sampler(rctx, count, states, &rctx->vs_samplers,
2456 R_00B130_SPI_SHADER_USER_DATA_VS_0);
2457 si_pm4_set_state(rctx, vs_sampler, pm4);
2458 }
2459
2460 static void si_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
2461 {
2462 struct r600_context *rctx = (struct r600_context *)ctx;
2463 struct si_pm4_state *pm4;
2464
2465 pm4 = si_bind_sampler(rctx, count, states, &rctx->ps_samplers,
2466 R_00B030_SPI_SHADER_USER_DATA_PS_0);
2467 si_pm4_set_state(rctx, ps_sampler, pm4);
2468 }
2469
2470 static void si_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
2471 {
2472 }
2473
2474 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2475 {
2476 free(state);
2477 }
2478
2479 /*
2480 * Constants
2481 */
2482 static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
2483 struct pipe_constant_buffer *cb)
2484 {
2485 struct r600_context *rctx = (struct r600_context *)ctx;
2486 struct si_resource *rbuffer = cb ? si_resource(cb->buffer) : NULL;
2487 struct si_pm4_state *pm4;
2488 uint32_t offset;
2489 uint64_t va;
2490
2491 /* Note that the state tracker can unbind constant buffers by
2492 * passing NULL here.
2493 */
2494 if (cb == NULL || (!cb->buffer && !cb->user_buffer))
2495 return;
2496
2497 pm4 = CALLOC_STRUCT(si_pm4_state);
2498 si_pm4_inval_shader_cache(pm4);
2499
2500 if (cb->user_buffer)
2501 r600_upload_const_buffer(rctx, &rbuffer, cb->user_buffer, cb->buffer_size, &offset);
2502 else
2503 offset = 0;
2504 va = r600_resource_va(ctx->screen, (void*)rbuffer);
2505 va += offset;
2506
2507 si_pm4_add_bo(pm4, rbuffer, RADEON_USAGE_READ);
2508
2509 si_pm4_sh_data_begin(pm4);
2510
2511 /* Fill in a T# buffer resource description */
2512 si_pm4_sh_data_add(pm4, va);
2513 si_pm4_sh_data_add(pm4, (S_008F04_BASE_ADDRESS_HI(va >> 32) |
2514 S_008F04_STRIDE(0)));
2515 si_pm4_sh_data_add(pm4, cb->buffer_size);
2516 si_pm4_sh_data_add(pm4, S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2517 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2518 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2519 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2520 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2521 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32));
2522
2523 switch (shader) {
2524 case PIPE_SHADER_VERTEX:
2525 si_pm4_sh_data_end(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0, SI_SGPR_CONST);
2526 si_pm4_set_state(rctx, vs_const, pm4);
2527 break;
2528
2529 case PIPE_SHADER_FRAGMENT:
2530 si_pm4_sh_data_end(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0, SI_SGPR_CONST);
2531 si_pm4_set_state(rctx, ps_const, pm4);
2532 break;
2533
2534 default:
2535 R600_ERR("unsupported %d\n", shader);
2536 FREE(pm4);
2537 }
2538
2539 if (cb->buffer != &rbuffer->b.b)
2540 si_resource_reference(&rbuffer, NULL);
2541 }
2542
2543 /*
2544 * Vertex elements & buffers
2545 */
2546
2547 static void *si_create_vertex_elements(struct pipe_context *ctx,
2548 unsigned count,
2549 const struct pipe_vertex_element *elements)
2550 {
2551 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2552 int i;
2553
2554 assert(count < PIPE_MAX_ATTRIBS);
2555 if (!v)
2556 return NULL;
2557
2558 v->count = count;
2559 for (i = 0; i < count; ++i) {
2560 const struct util_format_description *desc;
2561 unsigned data_format, num_format;
2562 int first_non_void;
2563
2564 desc = util_format_description(elements[i].src_format);
2565 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2566 data_format = si_translate_vertexformat(ctx->screen, elements[i].src_format,
2567 desc, first_non_void);
2568
2569 switch (desc->channel[first_non_void].type) {
2570 case UTIL_FORMAT_TYPE_FIXED:
2571 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED; /* XXX */
2572 break;
2573 case UTIL_FORMAT_TYPE_SIGNED:
2574 if (desc->channel[first_non_void].normalized)
2575 num_format = V_008F0C_BUF_NUM_FORMAT_SNORM;
2576 else if (desc->channel[first_non_void].pure_integer)
2577 num_format = V_008F0C_BUF_NUM_FORMAT_SINT;
2578 else
2579 num_format = V_008F0C_BUF_NUM_FORMAT_SSCALED;
2580 break;
2581 case UTIL_FORMAT_TYPE_UNSIGNED:
2582 if (desc->channel[first_non_void].normalized)
2583 num_format = V_008F0C_BUF_NUM_FORMAT_UNORM;
2584 else if (desc->channel[first_non_void].pure_integer)
2585 num_format = V_008F0C_BUF_NUM_FORMAT_UINT;
2586 else
2587 num_format = V_008F0C_BUF_NUM_FORMAT_USCALED;
2588 break;
2589 case UTIL_FORMAT_TYPE_FLOAT:
2590 default:
2591 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2592 }
2593
2594 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2595 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2596 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2597 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2598 S_008F0C_NUM_FORMAT(num_format) |
2599 S_008F0C_DATA_FORMAT(data_format);
2600 }
2601 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2602
2603 return v;
2604 }
2605
2606 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2607 {
2608 struct r600_context *rctx = (struct r600_context *)ctx;
2609 struct si_vertex_element *v = (struct si_vertex_element*)state;
2610
2611 rctx->vertex_elements = v;
2612 }
2613
2614 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2615 {
2616 struct r600_context *rctx = (struct r600_context *)ctx;
2617
2618 if (rctx->vertex_elements == state)
2619 rctx->vertex_elements = NULL;
2620 FREE(state);
2621 }
2622
2623 static void si_set_vertex_buffers(struct pipe_context *ctx, unsigned start_slot, unsigned count,
2624 const struct pipe_vertex_buffer *buffers)
2625 {
2626 struct r600_context *rctx = (struct r600_context *)ctx;
2627
2628 util_set_vertex_buffers_count(rctx->vertex_buffer, &rctx->nr_vertex_buffers, buffers, start_slot, count);
2629 }
2630
2631 static void si_set_index_buffer(struct pipe_context *ctx,
2632 const struct pipe_index_buffer *ib)
2633 {
2634 struct r600_context *rctx = (struct r600_context *)ctx;
2635
2636 if (ib) {
2637 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
2638 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
2639 } else {
2640 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
2641 }
2642 }
2643
2644 /*
2645 * Misc
2646 */
2647 static void si_set_polygon_stipple(struct pipe_context *ctx,
2648 const struct pipe_poly_stipple *state)
2649 {
2650 }
2651
2652 static void si_texture_barrier(struct pipe_context *ctx)
2653 {
2654 struct r600_context *rctx = (struct r600_context *)ctx;
2655 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2656
2657 si_pm4_inval_texture_cache(pm4);
2658 si_pm4_inval_fb_cache(pm4, rctx->framebuffer.nr_cbufs);
2659 si_pm4_set_state(rctx, texture_barrier, pm4);
2660 }
2661
2662 void si_init_state_functions(struct r600_context *rctx)
2663 {
2664 rctx->context.create_blend_state = si_create_blend_state;
2665 rctx->context.bind_blend_state = si_bind_blend_state;
2666 rctx->context.delete_blend_state = si_delete_blend_state;
2667 rctx->context.set_blend_color = si_set_blend_color;
2668
2669 rctx->context.create_rasterizer_state = si_create_rs_state;
2670 rctx->context.bind_rasterizer_state = si_bind_rs_state;
2671 rctx->context.delete_rasterizer_state = si_delete_rs_state;
2672
2673 rctx->context.create_depth_stencil_alpha_state = si_create_dsa_state;
2674 rctx->context.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2675 rctx->context.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2676 rctx->custom_dsa_flush_depth_stencil = si_create_db_flush_dsa(rctx, true, true);
2677 rctx->custom_dsa_flush_depth = si_create_db_flush_dsa(rctx, true, false);
2678 rctx->custom_dsa_flush_stencil = si_create_db_flush_dsa(rctx, false, true);
2679 rctx->custom_dsa_flush_inplace = si_create_db_flush_dsa(rctx, false, false);
2680
2681 rctx->context.set_clip_state = si_set_clip_state;
2682 rctx->context.set_scissor_state = si_set_scissor_state;
2683 rctx->context.set_viewport_state = si_set_viewport_state;
2684 rctx->context.set_stencil_ref = si_set_pipe_stencil_ref;
2685
2686 rctx->context.set_framebuffer_state = si_set_framebuffer_state;
2687
2688 rctx->context.create_vs_state = si_create_vs_state;
2689 rctx->context.create_fs_state = si_create_fs_state;
2690 rctx->context.bind_vs_state = si_bind_vs_shader;
2691 rctx->context.bind_fs_state = si_bind_ps_shader;
2692 rctx->context.delete_vs_state = si_delete_vs_shader;
2693 rctx->context.delete_fs_state = si_delete_ps_shader;
2694
2695 rctx->context.create_sampler_state = si_create_sampler_state;
2696 rctx->context.bind_vertex_sampler_states = si_bind_vs_sampler;
2697 rctx->context.bind_fragment_sampler_states = si_bind_ps_sampler;
2698 rctx->context.delete_sampler_state = si_delete_sampler_state;
2699
2700 rctx->context.create_sampler_view = si_create_sampler_view;
2701 rctx->context.set_vertex_sampler_views = si_set_vs_sampler_view;
2702 rctx->context.set_fragment_sampler_views = si_set_ps_sampler_view;
2703 rctx->context.sampler_view_destroy = si_sampler_view_destroy;
2704
2705 rctx->context.set_sample_mask = si_set_sample_mask;
2706
2707 rctx->context.set_constant_buffer = si_set_constant_buffer;
2708
2709 rctx->context.create_vertex_elements_state = si_create_vertex_elements;
2710 rctx->context.bind_vertex_elements_state = si_bind_vertex_elements;
2711 rctx->context.delete_vertex_elements_state = si_delete_vertex_element;
2712 rctx->context.set_vertex_buffers = si_set_vertex_buffers;
2713 rctx->context.set_index_buffer = si_set_index_buffer;
2714
2715 rctx->context.create_stream_output_target = si_create_so_target;
2716 rctx->context.stream_output_target_destroy = si_so_target_destroy;
2717 rctx->context.set_stream_output_targets = si_set_so_targets;
2718
2719 rctx->context.texture_barrier = si_texture_barrier;
2720 rctx->context.set_polygon_stipple = si_set_polygon_stipple;
2721
2722 rctx->context.draw_vbo = si_draw_vbo;
2723 }
2724
2725 void si_init_config(struct r600_context *rctx)
2726 {
2727 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2728
2729 si_cmd_context_control(pm4);
2730
2731 si_pm4_set_reg(pm4, R_028A4C_PA_SC_MODE_CNTL_1, 0x0);
2732
2733 si_pm4_set_reg(pm4, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x0);
2734 si_pm4_set_reg(pm4, R_028A14_VGT_HOS_CNTL, 0x0);
2735 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
2736 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
2737 si_pm4_set_reg(pm4, R_028A20_VGT_HOS_REUSE_DEPTH, 0x0);
2738 si_pm4_set_reg(pm4, R_028A24_VGT_GROUP_PRIM_TYPE, 0x0);
2739 si_pm4_set_reg(pm4, R_028A28_VGT_GROUP_FIRST_DECR, 0x0);
2740 si_pm4_set_reg(pm4, R_028A2C_VGT_GROUP_DECR, 0x0);
2741 si_pm4_set_reg(pm4, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x0);
2742 si_pm4_set_reg(pm4, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x0);
2743 si_pm4_set_reg(pm4, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x0);
2744 si_pm4_set_reg(pm4, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x0);
2745 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, 0x0);
2746 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
2747 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
2748 si_pm4_set_reg(pm4, R_028B94_VGT_STRMOUT_CONFIG, 0x0);
2749 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
2750 si_pm4_set_reg(pm4, R_028AA8_IA_MULTI_VGT_PARAM,
2751 S_028AA8_SWITCH_ON_EOP(1) |
2752 S_028AA8_PARTIAL_VS_WAVE_ON(1) |
2753 S_028AA8_PRIMGROUP_SIZE(63));
2754 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x00000000);
2755 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
2756 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
2757 S_008A14_CLIP_VTX_REORDER_ENA(1));
2758
2759 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0);
2760 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
2761 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
2762
2763 si_pm4_set_reg(pm4, R_028804_DB_EQAA, 0x110000);
2764
2765 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
2766
2767 switch (rctx->screen->family) {
2768 case CHIP_TAHITI:
2769 case CHIP_PITCAIRN:
2770 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
2771 break;
2772 case CHIP_VERDE:
2773 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0000124a);
2774 break;
2775 case CHIP_OLAND:
2776 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000082);
2777 break;
2778 default:
2779 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x00000000);
2780 break;
2781 }
2782
2783 si_pm4_set_state(rctx, init, pm4);
2784 }