projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: add a workaround for blending with DCC and MSAA
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #include "si_pipe.h"
25 #include "sid.h"
26 #include "gfx9d.h"
27 #include "radeon/r600_cs.h"
28 #include "radeon/r600_query.h"
29
30 #include "util/u_dual_blend.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34 #include "util/u_resource.h"
35 #include "util/u_upload_mgr.h"
36
37 /* Initialize an external atom (owned by ../radeon). */
38 static void
39 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
40 struct r600_atom **list_elem)
41 {
42 atom->id = list_elem - sctx->atoms.array;
43 *list_elem = atom;
44 }
45
46 /* Initialize an atom owned by radeonsi. */
47 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
48 struct r600_atom **list_elem,
49 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
50 {
51 atom->emit = (void*)emit_func;
52 atom->id = list_elem - sctx->atoms.array;
53 *list_elem = atom;
54 }
55
56 static unsigned si_map_swizzle(unsigned swizzle)
57 {
58 switch (swizzle) {
59 case PIPE_SWIZZLE_Y:
60 return V_008F0C_SQ_SEL_Y;
61 case PIPE_SWIZZLE_Z:
62 return V_008F0C_SQ_SEL_Z;
63 case PIPE_SWIZZLE_W:
64 return V_008F0C_SQ_SEL_W;
65 case PIPE_SWIZZLE_0:
66 return V_008F0C_SQ_SEL_0;
67 case PIPE_SWIZZLE_1:
68 return V_008F0C_SQ_SEL_1;
69 default: /* PIPE_SWIZZLE_X */
70 return V_008F0C_SQ_SEL_X;
71 }
72 }
73
74 /* 12.4 fixed-point */
75 static unsigned si_pack_float_12p4(float x)
76 {
77 return x <= 0 ? 0 :
78 x >= 4096 ? 0xffff : x * 16;
79 }
80
81 /*
82 * Inferred framebuffer and blender state.
83 *
84 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
85 * if there is not enough PS outputs.
86 */
87 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
88 {
89 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
90 struct si_state_blend *blend = sctx->queued.named.blend;
91 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
92 * but you never know. */
93 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
94 unsigned i;
95
96 if (blend)
97 cb_target_mask &= blend->cb_target_mask;
98
99 /* Avoid a hang that happens when dual source blending is enabled
100 * but there is not enough color outputs. This is undefined behavior,
101 * so disable color writes completely.
102 *
103 * Reproducible with Unigine Heaven 4.0 and drirc missing.
104 */
105 if (blend && blend->dual_src_blend &&
106 sctx->ps_shader.cso &&
107 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
108 cb_target_mask = 0;
109
110 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
111
112 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
113 * I think we don't have to do anything between IBs.
114 */
115 if (sctx->screen->dfsm_allowed &&
116 sctx->last_cb_target_mask != cb_target_mask) {
117 sctx->last_cb_target_mask = cb_target_mask;
118
119 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
120 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
121 }
122
123 if (sctx->b.chip_class >= VI) {
124 /* DCC MSAA workaround for blending.
125 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
126 * COMBINER_DISABLE, but that would be more complicated.
127 */
128 bool oc_disable = (sctx->b.chip_class == VI ||
129 sctx->b.chip_class == GFX9) &&
130 blend &&
131 blend->blend_enable_4bit & cb_target_mask &&
132 sctx->framebuffer.nr_samples >= 2;
133
134 radeon_set_context_reg(cs, R_028424_CB_DCC_CONTROL,
135 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
136 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
137 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
138 }
139
140 /* RB+ register settings. */
141 if (sctx->screen->b.rbplus_allowed) {
142 unsigned spi_shader_col_format =
143 sctx->ps_shader.cso ?
144 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
145 unsigned sx_ps_downconvert = 0;
146 unsigned sx_blend_opt_epsilon = 0;
147 unsigned sx_blend_opt_control = 0;
148
149 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
150 struct r600_surface *surf =
151 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
152 unsigned format, swap, spi_format, colormask;
153 bool has_alpha, has_rgb;
154
155 if (!surf)
156 continue;
157
158 format = G_028C70_FORMAT(surf->cb_color_info);
159 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
160 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
161 colormask = (cb_target_mask >> (i * 4)) & 0xf;
162
163 /* Set if RGB and A are present. */
164 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
165
166 if (format == V_028C70_COLOR_8 ||
167 format == V_028C70_COLOR_16 ||
168 format == V_028C70_COLOR_32)
169 has_rgb = !has_alpha;
170 else
171 has_rgb = true;
172
173 /* Check the colormask and export format. */
174 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
175 has_rgb = false;
176 if (!(colormask & PIPE_MASK_A))
177 has_alpha = false;
178
179 if (spi_format == V_028714_SPI_SHADER_ZERO) {
180 has_rgb = false;
181 has_alpha = false;
182 }
183
184 /* Disable value checking for disabled channels. */
185 if (!has_rgb)
186 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
187 if (!has_alpha)
188 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
189
190 /* Enable down-conversion for 32bpp and smaller formats. */
191 switch (format) {
192 case V_028C70_COLOR_8:
193 case V_028C70_COLOR_8_8:
194 case V_028C70_COLOR_8_8_8_8:
195 /* For 1 and 2-channel formats, use the superset thereof. */
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
197 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
198 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
199 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
200 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
201 }
202 break;
203
204 case V_028C70_COLOR_5_6_5:
205 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
207 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
208 }
209 break;
210
211 case V_028C70_COLOR_1_5_5_5:
212 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
213 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
214 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
215 }
216 break;
217
218 case V_028C70_COLOR_4_4_4_4:
219 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
220 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
221 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
222 }
223 break;
224
225 case V_028C70_COLOR_32:
226 if (swap == V_028C70_SWAP_STD &&
227 spi_format == V_028714_SPI_SHADER_32_R)
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
229 else if (swap == V_028C70_SWAP_ALT_REV &&
230 spi_format == V_028714_SPI_SHADER_32_AR)
231 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
232 break;
233
234 case V_028C70_COLOR_16:
235 case V_028C70_COLOR_16_16:
236 /* For 1-channel formats, use the superset thereof. */
237 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
238 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
239 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
240 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
241 if (swap == V_028C70_SWAP_STD ||
242 swap == V_028C70_SWAP_STD_REV)
243 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
244 else
245 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
246 }
247 break;
248
249 case V_028C70_COLOR_10_11_11:
250 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
251 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
252 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
253 }
254 break;
255
256 case V_028C70_COLOR_2_10_10_10:
257 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
258 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
259 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
260 }
261 break;
262 }
263 }
264
265 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
266 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
267 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
268 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
269 } else if (sctx->screen->b.has_rbplus) {
270 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
271 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
272 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
273 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
274 }
275 }
276
277 /*
278 * Blender functions
279 */
280
281 static uint32_t si_translate_blend_function(int blend_func)
282 {
283 switch (blend_func) {
284 case PIPE_BLEND_ADD:
285 return V_028780_COMB_DST_PLUS_SRC;
286 case PIPE_BLEND_SUBTRACT:
287 return V_028780_COMB_SRC_MINUS_DST;
288 case PIPE_BLEND_REVERSE_SUBTRACT:
289 return V_028780_COMB_DST_MINUS_SRC;
290 case PIPE_BLEND_MIN:
291 return V_028780_COMB_MIN_DST_SRC;
292 case PIPE_BLEND_MAX:
293 return V_028780_COMB_MAX_DST_SRC;
294 default:
295 R600_ERR("Unknown blend function %d\n", blend_func);
296 assert(0);
297 break;
298 }
299 return 0;
300 }
301
302 static uint32_t si_translate_blend_factor(int blend_fact)
303 {
304 switch (blend_fact) {
305 case PIPE_BLENDFACTOR_ONE:
306 return V_028780_BLEND_ONE;
307 case PIPE_BLENDFACTOR_SRC_COLOR:
308 return V_028780_BLEND_SRC_COLOR;
309 case PIPE_BLENDFACTOR_SRC_ALPHA:
310 return V_028780_BLEND_SRC_ALPHA;
311 case PIPE_BLENDFACTOR_DST_ALPHA:
312 return V_028780_BLEND_DST_ALPHA;
313 case PIPE_BLENDFACTOR_DST_COLOR:
314 return V_028780_BLEND_DST_COLOR;
315 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
316 return V_028780_BLEND_SRC_ALPHA_SATURATE;
317 case PIPE_BLENDFACTOR_CONST_COLOR:
318 return V_028780_BLEND_CONSTANT_COLOR;
319 case PIPE_BLENDFACTOR_CONST_ALPHA:
320 return V_028780_BLEND_CONSTANT_ALPHA;
321 case PIPE_BLENDFACTOR_ZERO:
322 return V_028780_BLEND_ZERO;
323 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
324 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
325 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
326 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
327 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
328 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
329 case PIPE_BLENDFACTOR_INV_DST_COLOR:
330 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
331 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
333 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
334 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
335 case PIPE_BLENDFACTOR_SRC1_COLOR:
336 return V_028780_BLEND_SRC1_COLOR;
337 case PIPE_BLENDFACTOR_SRC1_ALPHA:
338 return V_028780_BLEND_SRC1_ALPHA;
339 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
340 return V_028780_BLEND_INV_SRC1_COLOR;
341 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
342 return V_028780_BLEND_INV_SRC1_ALPHA;
343 default:
344 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
345 assert(0);
346 break;
347 }
348 return 0;
349 }
350
351 static uint32_t si_translate_blend_opt_function(int blend_func)
352 {
353 switch (blend_func) {
354 case PIPE_BLEND_ADD:
355 return V_028760_OPT_COMB_ADD;
356 case PIPE_BLEND_SUBTRACT:
357 return V_028760_OPT_COMB_SUBTRACT;
358 case PIPE_BLEND_REVERSE_SUBTRACT:
359 return V_028760_OPT_COMB_REVSUBTRACT;
360 case PIPE_BLEND_MIN:
361 return V_028760_OPT_COMB_MIN;
362 case PIPE_BLEND_MAX:
363 return V_028760_OPT_COMB_MAX;
364 default:
365 return V_028760_OPT_COMB_BLEND_DISABLED;
366 }
367 }
368
369 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
370 {
371 switch (blend_fact) {
372 case PIPE_BLENDFACTOR_ZERO:
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
374 case PIPE_BLENDFACTOR_ONE:
375 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
376 case PIPE_BLENDFACTOR_SRC_COLOR:
377 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
378 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
379 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
380 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
381 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
382 case PIPE_BLENDFACTOR_SRC_ALPHA:
383 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
384 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
385 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
386 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
387 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
388 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
389 default:
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
391 }
392 }
393
394 static void si_blend_check_commutativity(struct si_screen *sscreen,
395 struct si_state_blend *blend,
396 enum pipe_blend_func func,
397 enum pipe_blendfactor src,
398 enum pipe_blendfactor dst,
399 unsigned chanmask)
400 {
401 /* Src factor is allowed when it does not depend on Dst */
402 static const uint32_t src_allowed =
403 (1u << PIPE_BLENDFACTOR_ONE) |
404 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
405 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
406 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
407 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
408 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
409 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
410 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
411 (1u << PIPE_BLENDFACTOR_ZERO) |
412 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
413 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
414 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
415 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
416 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
417 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
418
419 if (dst == PIPE_BLENDFACTOR_ONE &&
420 (src_allowed & (1u << src))) {
421 /* Addition is commutative, but floating point addition isn't
422 * associative: subtle changes can be introduced via different
423 * rounding.
424 *
425 * Out-of-order is also non-deterministic, which means that
426 * this breaks OpenGL invariance requirements. So only enable
427 * out-of-order additive blending if explicitly allowed by a
428 * setting.
429 */
430 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
431 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
432 blend->commutative_4bit |= chanmask;
433 }
434 }
435
436 /**
437 * Get rid of DST in the blend factors by commuting the operands:
438 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
439 */
440 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
441 unsigned *dst_factor, unsigned expected_dst,
442 unsigned replacement_src)
443 {
444 if (*src_factor == expected_dst &&
445 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
446 *src_factor = PIPE_BLENDFACTOR_ZERO;
447 *dst_factor = replacement_src;
448
449 /* Commuting the operands requires reversing subtractions. */
450 if (*func == PIPE_BLEND_SUBTRACT)
451 *func = PIPE_BLEND_REVERSE_SUBTRACT;
452 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
453 *func = PIPE_BLEND_SUBTRACT;
454 }
455 }
456
457 static bool si_blend_factor_uses_dst(unsigned factor)
458 {
459 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
460 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
461 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
462 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
463 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
464 }
465
466 static void *si_create_blend_state_mode(struct pipe_context *ctx,
467 const struct pipe_blend_state *state,
468 unsigned mode)
469 {
470 struct si_context *sctx = (struct si_context*)ctx;
471 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
472 struct si_pm4_state *pm4 = &blend->pm4;
473 uint32_t sx_mrt_blend_opt[8] = {0};
474 uint32_t color_control = 0;
475
476 if (!blend)
477 return NULL;
478
479 blend->alpha_to_coverage = state->alpha_to_coverage;
480 blend->alpha_to_one = state->alpha_to_one;
481 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
482 blend->logicop_enable = state->logicop_enable;
483
484 if (state->logicop_enable) {
485 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
486 } else {
487 color_control |= S_028808_ROP3(0xcc);
488 }
489
490 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
491 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
492 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
493 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
494 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
495 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
496
497 if (state->alpha_to_coverage)
498 blend->need_src_alpha_4bit |= 0xf;
499
500 blend->cb_target_mask = 0;
501 blend->cb_target_enabled_4bit = 0;
502
503 for (int i = 0; i < 8; i++) {
504 /* state->rt entries > 0 only written if independent blending */
505 const int j = state->independent_blend_enable ? i : 0;
506
507 unsigned eqRGB = state->rt[j].rgb_func;
508 unsigned srcRGB = state->rt[j].rgb_src_factor;
509 unsigned dstRGB = state->rt[j].rgb_dst_factor;
510 unsigned eqA = state->rt[j].alpha_func;
511 unsigned srcA = state->rt[j].alpha_src_factor;
512 unsigned dstA = state->rt[j].alpha_dst_factor;
513
514 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
515 unsigned blend_cntl = 0;
516
517 sx_mrt_blend_opt[i] =
518 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
519 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
520
521 /* Only set dual source blending for MRT0 to avoid a hang. */
522 if (i >= 1 && blend->dual_src_blend) {
523 /* Vulkan does this for dual source blending. */
524 if (i == 1)
525 blend_cntl |= S_028780_ENABLE(1);
526
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 /* Only addition and subtraction equations are supported with
532 * dual source blending.
533 */
534 if (blend->dual_src_blend &&
535 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
536 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
537 assert(!"Unsupported equation for dual source blending");
538 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
539 continue;
540 }
541
542 /* cb_render_state will disable unused ones */
543 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
544 if (state->rt[j].colormask)
545 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
546
547 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
548 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
549 continue;
550 }
551
552 si_blend_check_commutativity(sctx->screen, blend,
553 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
554 si_blend_check_commutativity(sctx->screen, blend,
555 eqA, srcA, dstA, 0x8 << (4 * i));
556
557 /* Blending optimizations for RB+.
558 * These transformations don't change the behavior.
559 *
560 * First, get rid of DST in the blend factors:
561 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
562 */
563 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
564 PIPE_BLENDFACTOR_DST_COLOR,
565 PIPE_BLENDFACTOR_SRC_COLOR);
566 si_blend_remove_dst(&eqA, &srcA, &dstA,
567 PIPE_BLENDFACTOR_DST_COLOR,
568 PIPE_BLENDFACTOR_SRC_COLOR);
569 si_blend_remove_dst(&eqA, &srcA, &dstA,
570 PIPE_BLENDFACTOR_DST_ALPHA,
571 PIPE_BLENDFACTOR_SRC_ALPHA);
572
573 /* Look up the ideal settings from tables. */
574 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
575 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
576 srcA_opt = si_translate_blend_opt_factor(srcA, true);
577 dstA_opt = si_translate_blend_opt_factor(dstA, true);
578
579 /* Handle interdependencies. */
580 if (si_blend_factor_uses_dst(srcRGB))
581 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
582 if (si_blend_factor_uses_dst(srcA))
583 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
584
585 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
586 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
587 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
588 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
589 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
590
591 /* Set the final value. */
592 sx_mrt_blend_opt[i] =
593 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
594 S_028760_COLOR_DST_OPT(dstRGB_opt) |
595 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
596 S_028760_ALPHA_SRC_OPT(srcA_opt) |
597 S_028760_ALPHA_DST_OPT(dstA_opt) |
598 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
599
600 /* Set blend state. */
601 blend_cntl |= S_028780_ENABLE(1);
602 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
603 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
604 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
605
606 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
607 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
608 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
609 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
610 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
611 }
612 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
613
614 blend->blend_enable_4bit |= 0xfu << (i * 4);
615
616 /* This is only important for formats without alpha. */
617 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
618 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
619 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
620 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
621 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
622 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
623 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
624 }
625
626 if (blend->cb_target_mask) {
627 color_control |= S_028808_MODE(mode);
628 } else {
629 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
630 }
631
632 if (sctx->screen->b.has_rbplus) {
633 /* Disable RB+ blend optimizations for dual source blending.
634 * Vulkan does this.
635 */
636 if (blend->dual_src_blend) {
637 for (int i = 0; i < 8; i++) {
638 sx_mrt_blend_opt[i] =
639 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
640 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
641 }
642 }
643
644 for (int i = 0; i < 8; i++)
645 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
646 sx_mrt_blend_opt[i]);
647
648 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
649 if (blend->dual_src_blend || state->logicop_enable ||
650 mode == V_028808_CB_RESOLVE)
651 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
652 }
653
654 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
655 return blend;
656 }
657
658 static void *si_create_blend_state(struct pipe_context *ctx,
659 const struct pipe_blend_state *state)
660 {
661 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
662 }
663
664 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
665 {
666 struct si_context *sctx = (struct si_context *)ctx;
667 struct si_state_blend *old_blend = sctx->queued.named.blend;
668 struct si_state_blend *blend = (struct si_state_blend *)state;
669
670 if (!state)
671 return;
672
673 si_pm4_bind_state(sctx, blend, state);
674
675 if (!old_blend ||
676 old_blend->cb_target_mask != blend->cb_target_mask ||
677 old_blend->dual_src_blend != blend->dual_src_blend ||
678 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
679 sctx->framebuffer.nr_samples >= 2))
680 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
681
682 if (!old_blend ||
683 old_blend->cb_target_mask != blend->cb_target_mask ||
684 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
685 old_blend->alpha_to_one != blend->alpha_to_one ||
686 old_blend->dual_src_blend != blend->dual_src_blend ||
687 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
688 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
689 sctx->do_update_shaders = true;
690
691 if (sctx->screen->dpbb_allowed &&
692 (!old_blend ||
693 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
694 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
695 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
696 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
697
698 if (sctx->screen->has_out_of_order_rast &&
699 (!old_blend ||
700 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
701 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
702 old_blend->commutative_4bit != blend->commutative_4bit ||
703 old_blend->logicop_enable != blend->logicop_enable)))
704 si_mark_atom_dirty(sctx, &sctx->msaa_config);
705 }
706
707 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
708 {
709 struct si_context *sctx = (struct si_context *)ctx;
710 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
711 }
712
713 static void si_set_blend_color(struct pipe_context *ctx,
714 const struct pipe_blend_color *state)
715 {
716 struct si_context *sctx = (struct si_context *)ctx;
717 static const struct pipe_blend_color zeros;
718
719 sctx->blend_color.state = *state;
720 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
721 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
722 }
723
724 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
725 {
726 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
727
728 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
729 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
730 }
731
732 /*
733 * Clipping
734 */
735
736 static void si_set_clip_state(struct pipe_context *ctx,
737 const struct pipe_clip_state *state)
738 {
739 struct si_context *sctx = (struct si_context *)ctx;
740 struct pipe_constant_buffer cb;
741 static const struct pipe_clip_state zeros;
742
743 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
744 return;
745
746 sctx->clip_state.state = *state;
747 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
748 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
749
750 cb.buffer = NULL;
751 cb.user_buffer = state->ucp;
752 cb.buffer_offset = 0;
753 cb.buffer_size = 4*4*8;
754 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
755 pipe_resource_reference(&cb.buffer, NULL);
756 }
757
758 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
759 {
760 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
761
762 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
763 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
764 }
765
766 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
767 {
768 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
769 struct si_shader *vs = si_get_vs_state(sctx);
770 struct si_shader_selector *vs_sel = vs->selector;
771 struct tgsi_shader_info *info = &vs_sel->info;
772 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
773 unsigned window_space =
774 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
775 unsigned clipdist_mask = vs_sel->clipdist_mask;
776 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
777 unsigned culldist_mask = vs_sel->culldist_mask;
778 unsigned total_mask;
779
780 if (vs->key.opt.clip_disable) {
781 assert(!info->culldist_writemask);
782 clipdist_mask = 0;
783 culldist_mask = 0;
784 }
785 total_mask = clipdist_mask | culldist_mask;
786
787 /* Clip distances on points have no effect, so need to be implemented
788 * as cull distances. This applies for the clipvertex case as well.
789 *
790 * Setting this for primitives other than points should have no adverse
791 * effects.
792 */
793 clipdist_mask &= rs->clip_plane_enable;
794 culldist_mask |= clipdist_mask;
795
796 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
797 vs_sel->pa_cl_vs_out_cntl |
798 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
799 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
800 clipdist_mask | (culldist_mask << 8));
801 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
802 rs->pa_cl_clip_cntl |
803 ucp_mask |
804 S_028810_CLIP_DISABLE(window_space));
805 }
806
807 /*
808 * inferred state between framebuffer and rasterizer
809 */
810 static void si_update_poly_offset_state(struct si_context *sctx)
811 {
812 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
813
814 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
815 si_pm4_bind_state(sctx, poly_offset, NULL);
816 return;
817 }
818
819 /* Use the user format, not db_render_format, so that the polygon
820 * offset behaves as expected by applications.
821 */
822 switch (sctx->framebuffer.state.zsbuf->texture->format) {
823 case PIPE_FORMAT_Z16_UNORM:
824 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
825 break;
826 default: /* 24-bit */
827 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
828 break;
829 case PIPE_FORMAT_Z32_FLOAT:
830 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
831 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
832 break;
833 }
834 }
835
836 /*
837 * Rasterizer
838 */
839
840 static uint32_t si_translate_fill(uint32_t func)
841 {
842 switch(func) {
843 case PIPE_POLYGON_MODE_FILL:
844 return V_028814_X_DRAW_TRIANGLES;
845 case PIPE_POLYGON_MODE_LINE:
846 return V_028814_X_DRAW_LINES;
847 case PIPE_POLYGON_MODE_POINT:
848 return V_028814_X_DRAW_POINTS;
849 default:
850 assert(0);
851 return V_028814_X_DRAW_POINTS;
852 }
853 }
854
855 static void *si_create_rs_state(struct pipe_context *ctx,
856 const struct pipe_rasterizer_state *state)
857 {
858 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
859 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
860 struct si_pm4_state *pm4 = &rs->pm4;
861 unsigned tmp, i;
862 float psize_min, psize_max;
863
864 if (!rs) {
865 return NULL;
866 }
867
868 rs->scissor_enable = state->scissor;
869 rs->clip_halfz = state->clip_halfz;
870 rs->two_side = state->light_twoside;
871 rs->multisample_enable = state->multisample;
872 rs->force_persample_interp = state->force_persample_interp;
873 rs->clip_plane_enable = state->clip_plane_enable;
874 rs->line_stipple_enable = state->line_stipple_enable;
875 rs->poly_stipple_enable = state->poly_stipple_enable;
876 rs->line_smooth = state->line_smooth;
877 rs->line_width = state->line_width;
878 rs->poly_smooth = state->poly_smooth;
879 rs->uses_poly_offset = state->offset_point || state->offset_line ||
880 state->offset_tri;
881 rs->clamp_fragment_color = state->clamp_fragment_color;
882 rs->clamp_vertex_color = state->clamp_vertex_color;
883 rs->flatshade = state->flatshade;
884 rs->sprite_coord_enable = state->sprite_coord_enable;
885 rs->rasterizer_discard = state->rasterizer_discard;
886 rs->pa_sc_line_stipple = state->line_stipple_enable ?
887 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
888 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
889 rs->pa_cl_clip_cntl =
890 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
891 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
892 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
893 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
894 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
895
896 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
897 S_0286D4_FLAT_SHADE_ENA(1) |
898 S_0286D4_PNT_SPRITE_ENA(1) |
899 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
900 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
901 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
902 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
903 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
904
905 /* point size 12.4 fixed point */
906 tmp = (unsigned)(state->point_size * 8.0);
907 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
908
909 if (state->point_size_per_vertex) {
910 psize_min = util_get_min_point_size(state);
911 psize_max = 8192;
912 } else {
913 /* Force the point size to be as if the vertex output was disabled. */
914 psize_min = state->point_size;
915 psize_max = state->point_size;
916 }
917 rs->max_point_size = psize_max;
918
919 /* Divide by two, because 0.5 = 1 pixel. */
920 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
921 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
922 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
923
924 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
925 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
926 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
927 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
928 S_028A48_MSAA_ENABLE(state->multisample ||
929 state->poly_smooth ||
930 state->line_smooth) |
931 S_028A48_VPORT_SCISSOR_ENABLE(1) |
932 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
933
934 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
935 S_028BE4_PIX_CENTER(state->half_pixel_center) |
936 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
937
938 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
939 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
940 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
941 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
942 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
943 S_028814_FACE(!state->front_ccw) |
944 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
945 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
946 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
947 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
948 state->fill_back != PIPE_POLYGON_MODE_FILL) |
949 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
950 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
951
952 if (!rs->uses_poly_offset)
953 return rs;
954
955 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
956 if (!rs->pm4_poly_offset) {
957 FREE(rs);
958 return NULL;
959 }
960
961 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
962 for (i = 0; i < 3; i++) {
963 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
964 float offset_units = state->offset_units;
965 float offset_scale = state->offset_scale * 16.0f;
966 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
967
968 if (!state->offset_units_unscaled) {
969 switch (i) {
970 case 0: /* 16-bit zbuffer */
971 offset_units *= 4.0f;
972 pa_su_poly_offset_db_fmt_cntl =
973 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
974 break;
975 case 1: /* 24-bit zbuffer */
976 offset_units *= 2.0f;
977 pa_su_poly_offset_db_fmt_cntl =
978 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
979 break;
980 case 2: /* 32-bit zbuffer */
981 offset_units *= 1.0f;
982 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
983 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
984 break;
985 }
986 }
987
988 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
989 fui(offset_scale));
990 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
991 fui(offset_units));
992 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
993 fui(offset_scale));
994 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
995 fui(offset_units));
996 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
997 pa_su_poly_offset_db_fmt_cntl);
998 }
999
1000 return rs;
1001 }
1002
1003 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
1004 {
1005 struct si_context *sctx = (struct si_context *)ctx;
1006 struct si_state_rasterizer *old_rs =
1007 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
1008 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1009
1010 if (!state)
1011 return;
1012
1013 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
1014 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1015
1016 /* Update the small primitive filter workaround if necessary. */
1017 if (sctx->screen->has_msaa_sample_loc_bug &&
1018 sctx->framebuffer.nr_samples > 1)
1019 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
1020 }
1021
1022 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1023 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1024
1025 si_pm4_bind_state(sctx, rasterizer, rs);
1026 si_update_poly_offset_state(sctx);
1027
1028 if (!old_rs ||
1029 (old_rs->scissor_enable != rs->scissor_enable ||
1030 old_rs->line_width != rs->line_width ||
1031 old_rs->max_point_size != rs->max_point_size)) {
1032 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1033 si_mark_atom_dirty(sctx, &sctx->scissors.atom);
1034 }
1035
1036 if (!old_rs ||
1037 old_rs->clip_halfz != rs->clip_halfz) {
1038 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1039 si_mark_atom_dirty(sctx, &sctx->viewports.atom);
1040 }
1041
1042 if (!old_rs ||
1043 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1044 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1045 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1046
1047 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1048 rs->line_stipple_enable;
1049
1050 if (!old_rs ||
1051 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1052 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1053 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1054 old_rs->flatshade != rs->flatshade ||
1055 old_rs->two_side != rs->two_side ||
1056 old_rs->multisample_enable != rs->multisample_enable ||
1057 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1058 old_rs->poly_smooth != rs->poly_smooth ||
1059 old_rs->line_smooth != rs->line_smooth ||
1060 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1061 old_rs->force_persample_interp != rs->force_persample_interp)
1062 sctx->do_update_shaders = true;
1063 }
1064
1065 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1066 {
1067 struct si_context *sctx = (struct si_context *)ctx;
1068 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1069
1070 if (sctx->queued.named.rasterizer == state)
1071 si_pm4_bind_state(sctx, poly_offset, NULL);
1072
1073 FREE(rs->pm4_poly_offset);
1074 si_pm4_delete_state(sctx, rasterizer, rs);
1075 }
1076
1077 /*
1078 * infeered state between dsa and stencil ref
1079 */
1080 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
1081 {
1082 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1083 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1084 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1085
1086 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1087 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1088 S_028430_STENCILMASK(dsa->valuemask[0]) |
1089 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1090 S_028430_STENCILOPVAL(1));
1091 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1092 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1093 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1094 S_028434_STENCILOPVAL_BF(1));
1095 }
1096
1097 static void si_set_stencil_ref(struct pipe_context *ctx,
1098 const struct pipe_stencil_ref *state)
1099 {
1100 struct si_context *sctx = (struct si_context *)ctx;
1101
1102 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1103 return;
1104
1105 sctx->stencil_ref.state = *state;
1106 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1107 }
1108
1109
1110 /*
1111 * DSA
1112 */
1113
1114 static uint32_t si_translate_stencil_op(int s_op)
1115 {
1116 switch (s_op) {
1117 case PIPE_STENCIL_OP_KEEP:
1118 return V_02842C_STENCIL_KEEP;
1119 case PIPE_STENCIL_OP_ZERO:
1120 return V_02842C_STENCIL_ZERO;
1121 case PIPE_STENCIL_OP_REPLACE:
1122 return V_02842C_STENCIL_REPLACE_TEST;
1123 case PIPE_STENCIL_OP_INCR:
1124 return V_02842C_STENCIL_ADD_CLAMP;
1125 case PIPE_STENCIL_OP_DECR:
1126 return V_02842C_STENCIL_SUB_CLAMP;
1127 case PIPE_STENCIL_OP_INCR_WRAP:
1128 return V_02842C_STENCIL_ADD_WRAP;
1129 case PIPE_STENCIL_OP_DECR_WRAP:
1130 return V_02842C_STENCIL_SUB_WRAP;
1131 case PIPE_STENCIL_OP_INVERT:
1132 return V_02842C_STENCIL_INVERT;
1133 default:
1134 R600_ERR("Unknown stencil op %d", s_op);
1135 assert(0);
1136 break;
1137 }
1138 return 0;
1139 }
1140
1141 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1142 {
1143 return s->enabled && s->writemask &&
1144 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1145 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1146 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1147 }
1148
1149 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1150 {
1151 /* REPLACE is normally order invariant, except when the stencil
1152 * reference value is written by the fragment shader. Tracking this
1153 * interaction does not seem worth the effort, so be conservative. */
1154 return op != PIPE_STENCIL_OP_INCR &&
1155 op != PIPE_STENCIL_OP_DECR &&
1156 op != PIPE_STENCIL_OP_REPLACE;
1157 }
1158
1159 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1160 * invariant in the sense that the set of passing fragments as well as the
1161 * final stencil buffer result does not depend on the order of fragments. */
1162 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1163 {
1164 return !state->enabled || !state->writemask ||
1165 /* The following assumes that Z writes are disabled. */
1166 (state->func == PIPE_FUNC_ALWAYS &&
1167 si_order_invariant_stencil_op(state->zpass_op) &&
1168 si_order_invariant_stencil_op(state->zfail_op)) ||
1169 (state->func == PIPE_FUNC_NEVER &&
1170 si_order_invariant_stencil_op(state->fail_op));
1171 }
1172
1173 static void *si_create_dsa_state(struct pipe_context *ctx,
1174 const struct pipe_depth_stencil_alpha_state *state)
1175 {
1176 struct si_context *sctx = (struct si_context *)ctx;
1177 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1178 struct si_pm4_state *pm4 = &dsa->pm4;
1179 unsigned db_depth_control;
1180 uint32_t db_stencil_control = 0;
1181
1182 if (!dsa) {
1183 return NULL;
1184 }
1185
1186 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1187 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1188 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1189 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1190
1191 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1192 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1193 S_028800_ZFUNC(state->depth.func) |
1194 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1195
1196 /* stencil */
1197 if (state->stencil[0].enabled) {
1198 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1199 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1200 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1201 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1202 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1203
1204 if (state->stencil[1].enabled) {
1205 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1206 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1207 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1208 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1209 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1210 }
1211 }
1212
1213 /* alpha */
1214 if (state->alpha.enabled) {
1215 dsa->alpha_func = state->alpha.func;
1216
1217 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1218 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1219 } else {
1220 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1221 }
1222
1223 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1224 if (state->stencil[0].enabled)
1225 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1226 if (state->depth.bounds_test) {
1227 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1228 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1229 }
1230
1231 dsa->depth_enabled = state->depth.enabled;
1232 dsa->depth_write_enabled = state->depth.enabled &&
1233 state->depth.writemask;
1234 dsa->stencil_enabled = state->stencil[0].enabled;
1235 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1236 (si_dsa_writes_stencil(&state->stencil[0]) ||
1237 si_dsa_writes_stencil(&state->stencil[1]));
1238 dsa->db_can_write = dsa->depth_write_enabled ||
1239 dsa->stencil_write_enabled;
1240
1241 bool zfunc_is_ordered =
1242 state->depth.func == PIPE_FUNC_NEVER ||
1243 state->depth.func == PIPE_FUNC_LESS ||
1244 state->depth.func == PIPE_FUNC_LEQUAL ||
1245 state->depth.func == PIPE_FUNC_GREATER ||
1246 state->depth.func == PIPE_FUNC_GEQUAL;
1247
1248 bool nozwrite_and_order_invariant_stencil =
1249 !dsa->db_can_write ||
1250 (!dsa->depth_write_enabled &&
1251 si_order_invariant_stencil_state(&state->stencil[0]) &&
1252 si_order_invariant_stencil_state(&state->stencil[1]));
1253
1254 dsa->order_invariance[1].zs =
1255 nozwrite_and_order_invariant_stencil ||
1256 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1257 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1258
1259 dsa->order_invariance[1].pass_set =
1260 nozwrite_and_order_invariant_stencil ||
1261 (!dsa->stencil_write_enabled &&
1262 (state->depth.func == PIPE_FUNC_ALWAYS ||
1263 state->depth.func == PIPE_FUNC_NEVER));
1264 dsa->order_invariance[0].pass_set =
1265 !dsa->depth_write_enabled ||
1266 (state->depth.func == PIPE_FUNC_ALWAYS ||
1267 state->depth.func == PIPE_FUNC_NEVER);
1268
1269 dsa->order_invariance[1].pass_last =
1270 sctx->screen->assume_no_z_fights &&
1271 !dsa->stencil_write_enabled &&
1272 dsa->depth_write_enabled && zfunc_is_ordered;
1273 dsa->order_invariance[0].pass_last =
1274 sctx->screen->assume_no_z_fights &&
1275 dsa->depth_write_enabled && zfunc_is_ordered;
1276
1277 return dsa;
1278 }
1279
1280 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1281 {
1282 struct si_context *sctx = (struct si_context *)ctx;
1283 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1284 struct si_state_dsa *dsa = state;
1285
1286 if (!state)
1287 return;
1288
1289 si_pm4_bind_state(sctx, dsa, dsa);
1290
1291 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1292 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1293 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1294 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1295 }
1296
1297 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1298 sctx->do_update_shaders = true;
1299
1300 if (sctx->screen->dpbb_allowed &&
1301 (!old_dsa ||
1302 (old_dsa->depth_enabled != dsa->depth_enabled ||
1303 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1304 old_dsa->db_can_write != dsa->db_can_write)))
1305 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
1306
1307 if (sctx->screen->has_out_of_order_rast &&
1308 (!old_dsa ||
1309 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1310 sizeof(old_dsa->order_invariance))))
1311 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1312 }
1313
1314 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1315 {
1316 struct si_context *sctx = (struct si_context *)ctx;
1317 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1318 }
1319
1320 static void *si_create_db_flush_dsa(struct si_context *sctx)
1321 {
1322 struct pipe_depth_stencil_alpha_state dsa = {};
1323
1324 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1325 }
1326
1327 /* DB RENDER STATE */
1328
1329 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1330 {
1331 struct si_context *sctx = (struct si_context*)ctx;
1332
1333 /* Pipeline stat & streamout queries. */
1334 if (enable) {
1335 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1336 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1337 } else {
1338 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1339 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1340 }
1341
1342 /* Occlusion queries. */
1343 if (sctx->occlusion_queries_disabled != !enable) {
1344 sctx->occlusion_queries_disabled = !enable;
1345 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1346 }
1347 }
1348
1349 static void si_set_occlusion_query_state(struct pipe_context *ctx,
1350 bool old_enable,
1351 bool old_perfect_enable)
1352 {
1353 struct si_context *sctx = (struct si_context*)ctx;
1354
1355 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1356
1357 bool perfect_enable = sctx->b.num_perfect_occlusion_queries != 0;
1358
1359 if (perfect_enable != old_perfect_enable)
1360 si_mark_atom_dirty(sctx, &sctx->msaa_config);
1361 }
1362
1363 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1364 {
1365 struct si_context *sctx = (struct si_context*)ctx;
1366
1367 st->saved_compute = sctx->cs_shader_state.program;
1368
1369 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1370 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1371 }
1372
1373 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1374 {
1375 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1376 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1377 unsigned db_shader_control;
1378
1379 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1380
1381 /* DB_RENDER_CONTROL */
1382 if (sctx->dbcb_depth_copy_enabled ||
1383 sctx->dbcb_stencil_copy_enabled) {
1384 radeon_emit(cs,
1385 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1386 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1387 S_028000_COPY_CENTROID(1) |
1388 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1389 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1390 radeon_emit(cs,
1391 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1392 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1393 } else {
1394 radeon_emit(cs,
1395 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1396 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1397 }
1398
1399 /* DB_COUNT_CONTROL (occlusion queries) */
1400 if (sctx->b.num_occlusion_queries > 0 &&
1401 !sctx->occlusion_queries_disabled) {
1402 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1403
1404 if (sctx->b.chip_class >= CIK) {
1405 radeon_emit(cs,
1406 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1407 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1408 S_028004_ZPASS_ENABLE(1) |
1409 S_028004_SLICE_EVEN_ENABLE(1) |
1410 S_028004_SLICE_ODD_ENABLE(1));
1411 } else {
1412 radeon_emit(cs,
1413 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1414 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1415 }
1416 } else {
1417 /* Disable occlusion queries. */
1418 if (sctx->b.chip_class >= CIK) {
1419 radeon_emit(cs, 0);
1420 } else {
1421 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1422 }
1423 }
1424
1425 /* DB_RENDER_OVERRIDE2 */
1426 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1427 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1428 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1429 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1430
1431 db_shader_control = sctx->ps_db_shader_control;
1432
1433 /* Bug workaround for smoothing (overrasterization) on SI. */
1434 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1435 db_shader_control &= C_02880C_Z_ORDER;
1436 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1437 }
1438
1439 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1440 if (!rs || !rs->multisample_enable)
1441 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1442
1443 if (sctx->screen->b.has_rbplus &&
1444 !sctx->screen->b.rbplus_allowed)
1445 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1446
1447 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1448 db_shader_control);
1449 }
1450
1451 /*
1452 * format translation
1453 */
1454 static uint32_t si_translate_colorformat(enum pipe_format format)
1455 {
1456 const struct util_format_description *desc = util_format_description(format);
1457 if (!desc)
1458 return V_028C70_COLOR_INVALID;
1459
1460 #define HAS_SIZE(x,y,z,w) \
1461 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1462 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1463
1464 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1465 return V_028C70_COLOR_10_11_11;
1466
1467 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1468 return V_028C70_COLOR_INVALID;
1469
1470 /* hw cannot support mixed formats (except depth/stencil, since
1471 * stencil is not written to). */
1472 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1473 return V_028C70_COLOR_INVALID;
1474
1475 switch (desc->nr_channels) {
1476 case 1:
1477 switch (desc->channel[0].size) {
1478 case 8:
1479 return V_028C70_COLOR_8;
1480 case 16:
1481 return V_028C70_COLOR_16;
1482 case 32:
1483 return V_028C70_COLOR_32;
1484 }
1485 break;
1486 case 2:
1487 if (desc->channel[0].size == desc->channel[1].size) {
1488 switch (desc->channel[0].size) {
1489 case 8:
1490 return V_028C70_COLOR_8_8;
1491 case 16:
1492 return V_028C70_COLOR_16_16;
1493 case 32:
1494 return V_028C70_COLOR_32_32;
1495 }
1496 } else if (HAS_SIZE(8,24,0,0)) {
1497 return V_028C70_COLOR_24_8;
1498 } else if (HAS_SIZE(24,8,0,0)) {
1499 return V_028C70_COLOR_8_24;
1500 }
1501 break;
1502 case 3:
1503 if (HAS_SIZE(5,6,5,0)) {
1504 return V_028C70_COLOR_5_6_5;
1505 } else if (HAS_SIZE(32,8,24,0)) {
1506 return V_028C70_COLOR_X24_8_32_FLOAT;
1507 }
1508 break;
1509 case 4:
1510 if (desc->channel[0].size == desc->channel[1].size &&
1511 desc->channel[0].size == desc->channel[2].size &&
1512 desc->channel[0].size == desc->channel[3].size) {
1513 switch (desc->channel[0].size) {
1514 case 4:
1515 return V_028C70_COLOR_4_4_4_4;
1516 case 8:
1517 return V_028C70_COLOR_8_8_8_8;
1518 case 16:
1519 return V_028C70_COLOR_16_16_16_16;
1520 case 32:
1521 return V_028C70_COLOR_32_32_32_32;
1522 }
1523 } else if (HAS_SIZE(5,5,5,1)) {
1524 return V_028C70_COLOR_1_5_5_5;
1525 } else if (HAS_SIZE(1,5,5,5)) {
1526 return V_028C70_COLOR_5_5_5_1;
1527 } else if (HAS_SIZE(10,10,10,2)) {
1528 return V_028C70_COLOR_2_10_10_10;
1529 }
1530 break;
1531 }
1532 return V_028C70_COLOR_INVALID;
1533 }
1534
1535 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1536 {
1537 if (SI_BIG_ENDIAN) {
1538 switch(colorformat) {
1539 /* 8-bit buffers. */
1540 case V_028C70_COLOR_8:
1541 return V_028C70_ENDIAN_NONE;
1542
1543 /* 16-bit buffers. */
1544 case V_028C70_COLOR_5_6_5:
1545 case V_028C70_COLOR_1_5_5_5:
1546 case V_028C70_COLOR_4_4_4_4:
1547 case V_028C70_COLOR_16:
1548 case V_028C70_COLOR_8_8:
1549 return V_028C70_ENDIAN_8IN16;
1550
1551 /* 32-bit buffers. */
1552 case V_028C70_COLOR_8_8_8_8:
1553 case V_028C70_COLOR_2_10_10_10:
1554 case V_028C70_COLOR_8_24:
1555 case V_028C70_COLOR_24_8:
1556 case V_028C70_COLOR_16_16:
1557 return V_028C70_ENDIAN_8IN32;
1558
1559 /* 64-bit buffers. */
1560 case V_028C70_COLOR_16_16_16_16:
1561 return V_028C70_ENDIAN_8IN16;
1562
1563 case V_028C70_COLOR_32_32:
1564 return V_028C70_ENDIAN_8IN32;
1565
1566 /* 128-bit buffers. */
1567 case V_028C70_COLOR_32_32_32_32:
1568 return V_028C70_ENDIAN_8IN32;
1569 default:
1570 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1571 }
1572 } else {
1573 return V_028C70_ENDIAN_NONE;
1574 }
1575 }
1576
1577 static uint32_t si_translate_dbformat(enum pipe_format format)
1578 {
1579 switch (format) {
1580 case PIPE_FORMAT_Z16_UNORM:
1581 return V_028040_Z_16;
1582 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1583 case PIPE_FORMAT_X8Z24_UNORM:
1584 case PIPE_FORMAT_Z24X8_UNORM:
1585 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1586 return V_028040_Z_24; /* deprecated on SI */
1587 case PIPE_FORMAT_Z32_FLOAT:
1588 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1589 return V_028040_Z_32_FLOAT;
1590 default:
1591 return V_028040_Z_INVALID;
1592 }
1593 }
1594
1595 /*
1596 * Texture translation
1597 */
1598
1599 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1600 enum pipe_format format,
1601 const struct util_format_description *desc,
1602 int first_non_void)
1603 {
1604 struct si_screen *sscreen = (struct si_screen*)screen;
1605 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1606 sscreen->b.info.drm_minor >= 31) ||
1607 sscreen->b.info.drm_major == 3;
1608 bool uniform = true;
1609 int i;
1610
1611 /* Colorspace (return non-RGB formats directly). */
1612 switch (desc->colorspace) {
1613 /* Depth stencil formats */
1614 case UTIL_FORMAT_COLORSPACE_ZS:
1615 switch (format) {
1616 case PIPE_FORMAT_Z16_UNORM:
1617 return V_008F14_IMG_DATA_FORMAT_16;
1618 case PIPE_FORMAT_X24S8_UINT:
1619 case PIPE_FORMAT_S8X24_UINT:
1620 /*
1621 * Implemented as an 8_8_8_8 data format to fix texture
1622 * gathers in stencil sampling. This affects at least
1623 * GL45-CTS.texture_cube_map_array.sampling on VI.
1624 */
1625 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1626 case PIPE_FORMAT_Z24X8_UNORM:
1627 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1628 return V_008F14_IMG_DATA_FORMAT_8_24;
1629 case PIPE_FORMAT_X8Z24_UNORM:
1630 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1631 return V_008F14_IMG_DATA_FORMAT_24_8;
1632 case PIPE_FORMAT_S8_UINT:
1633 return V_008F14_IMG_DATA_FORMAT_8;
1634 case PIPE_FORMAT_Z32_FLOAT:
1635 return V_008F14_IMG_DATA_FORMAT_32;
1636 case PIPE_FORMAT_X32_S8X24_UINT:
1637 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1638 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1639 default:
1640 goto out_unknown;
1641 }
1642
1643 case UTIL_FORMAT_COLORSPACE_YUV:
1644 goto out_unknown; /* TODO */
1645
1646 case UTIL_FORMAT_COLORSPACE_SRGB:
1647 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1648 goto out_unknown;
1649 break;
1650
1651 default:
1652 break;
1653 }
1654
1655 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1656 if (!enable_compressed_formats)
1657 goto out_unknown;
1658
1659 switch (format) {
1660 case PIPE_FORMAT_RGTC1_SNORM:
1661 case PIPE_FORMAT_LATC1_SNORM:
1662 case PIPE_FORMAT_RGTC1_UNORM:
1663 case PIPE_FORMAT_LATC1_UNORM:
1664 return V_008F14_IMG_DATA_FORMAT_BC4;
1665 case PIPE_FORMAT_RGTC2_SNORM:
1666 case PIPE_FORMAT_LATC2_SNORM:
1667 case PIPE_FORMAT_RGTC2_UNORM:
1668 case PIPE_FORMAT_LATC2_UNORM:
1669 return V_008F14_IMG_DATA_FORMAT_BC5;
1670 default:
1671 goto out_unknown;
1672 }
1673 }
1674
1675 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1676 (sscreen->b.family == CHIP_STONEY ||
1677 sscreen->b.chip_class >= GFX9)) {
1678 switch (format) {
1679 case PIPE_FORMAT_ETC1_RGB8:
1680 case PIPE_FORMAT_ETC2_RGB8:
1681 case PIPE_FORMAT_ETC2_SRGB8:
1682 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1683 case PIPE_FORMAT_ETC2_RGB8A1:
1684 case PIPE_FORMAT_ETC2_SRGB8A1:
1685 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1686 case PIPE_FORMAT_ETC2_RGBA8:
1687 case PIPE_FORMAT_ETC2_SRGBA8:
1688 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1689 case PIPE_FORMAT_ETC2_R11_UNORM:
1690 case PIPE_FORMAT_ETC2_R11_SNORM:
1691 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1692 case PIPE_FORMAT_ETC2_RG11_UNORM:
1693 case PIPE_FORMAT_ETC2_RG11_SNORM:
1694 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1695 default:
1696 goto out_unknown;
1697 }
1698 }
1699
1700 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1701 if (!enable_compressed_formats)
1702 goto out_unknown;
1703
1704 switch (format) {
1705 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1706 case PIPE_FORMAT_BPTC_SRGBA:
1707 return V_008F14_IMG_DATA_FORMAT_BC7;
1708 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1709 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1710 return V_008F14_IMG_DATA_FORMAT_BC6;
1711 default:
1712 goto out_unknown;
1713 }
1714 }
1715
1716 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1717 switch (format) {
1718 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1719 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1720 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1721 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1722 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1723 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1724 default:
1725 goto out_unknown;
1726 }
1727 }
1728
1729 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1730 if (!enable_compressed_formats)
1731 goto out_unknown;
1732
1733 switch (format) {
1734 case PIPE_FORMAT_DXT1_RGB:
1735 case PIPE_FORMAT_DXT1_RGBA:
1736 case PIPE_FORMAT_DXT1_SRGB:
1737 case PIPE_FORMAT_DXT1_SRGBA:
1738 return V_008F14_IMG_DATA_FORMAT_BC1;
1739 case PIPE_FORMAT_DXT3_RGBA:
1740 case PIPE_FORMAT_DXT3_SRGBA:
1741 return V_008F14_IMG_DATA_FORMAT_BC2;
1742 case PIPE_FORMAT_DXT5_RGBA:
1743 case PIPE_FORMAT_DXT5_SRGBA:
1744 return V_008F14_IMG_DATA_FORMAT_BC3;
1745 default:
1746 goto out_unknown;
1747 }
1748 }
1749
1750 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1751 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1752 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1753 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1754 }
1755
1756 /* R8G8Bx_SNORM - TODO CxV8U8 */
1757
1758 /* hw cannot support mixed formats (except depth/stencil, since only
1759 * depth is read).*/
1760 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1761 goto out_unknown;
1762
1763 /* See whether the components are of the same size. */
1764 for (i = 1; i < desc->nr_channels; i++) {
1765 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1766 }
1767
1768 /* Non-uniform formats. */
1769 if (!uniform) {
1770 switch(desc->nr_channels) {
1771 case 3:
1772 if (desc->channel[0].size == 5 &&
1773 desc->channel[1].size == 6 &&
1774 desc->channel[2].size == 5) {
1775 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1776 }
1777 goto out_unknown;
1778 case 4:
1779 if (desc->channel[0].size == 5 &&
1780 desc->channel[1].size == 5 &&
1781 desc->channel[2].size == 5 &&
1782 desc->channel[3].size == 1) {
1783 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1784 }
1785 if (desc->channel[0].size == 1 &&
1786 desc->channel[1].size == 5 &&
1787 desc->channel[2].size == 5 &&
1788 desc->channel[3].size == 5) {
1789 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1790 }
1791 if (desc->channel[0].size == 10 &&
1792 desc->channel[1].size == 10 &&
1793 desc->channel[2].size == 10 &&
1794 desc->channel[3].size == 2) {
1795 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1796 }
1797 goto out_unknown;
1798 }
1799 goto out_unknown;
1800 }
1801
1802 if (first_non_void < 0 || first_non_void > 3)
1803 goto out_unknown;
1804
1805 /* uniform formats */
1806 switch (desc->channel[first_non_void].size) {
1807 case 4:
1808 switch (desc->nr_channels) {
1809 #if 0 /* Not supported for render targets */
1810 case 2:
1811 return V_008F14_IMG_DATA_FORMAT_4_4;
1812 #endif
1813 case 4:
1814 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1815 }
1816 break;
1817 case 8:
1818 switch (desc->nr_channels) {
1819 case 1:
1820 return V_008F14_IMG_DATA_FORMAT_8;
1821 case 2:
1822 return V_008F14_IMG_DATA_FORMAT_8_8;
1823 case 4:
1824 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1825 }
1826 break;
1827 case 16:
1828 switch (desc->nr_channels) {
1829 case 1:
1830 return V_008F14_IMG_DATA_FORMAT_16;
1831 case 2:
1832 return V_008F14_IMG_DATA_FORMAT_16_16;
1833 case 4:
1834 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1835 }
1836 break;
1837 case 32:
1838 switch (desc->nr_channels) {
1839 case 1:
1840 return V_008F14_IMG_DATA_FORMAT_32;
1841 case 2:
1842 return V_008F14_IMG_DATA_FORMAT_32_32;
1843 #if 0 /* Not supported for render targets */
1844 case 3:
1845 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1846 #endif
1847 case 4:
1848 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1849 }
1850 }
1851
1852 out_unknown:
1853 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1854 return ~0;
1855 }
1856
1857 static unsigned si_tex_wrap(unsigned wrap)
1858 {
1859 switch (wrap) {
1860 default:
1861 case PIPE_TEX_WRAP_REPEAT:
1862 return V_008F30_SQ_TEX_WRAP;
1863 case PIPE_TEX_WRAP_CLAMP:
1864 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1865 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1866 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1867 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1868 return V_008F30_SQ_TEX_CLAMP_BORDER;
1869 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1870 return V_008F30_SQ_TEX_MIRROR;
1871 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1872 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1873 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1874 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1875 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1876 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1877 }
1878 }
1879
1880 static unsigned si_tex_mipfilter(unsigned filter)
1881 {
1882 switch (filter) {
1883 case PIPE_TEX_MIPFILTER_NEAREST:
1884 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1885 case PIPE_TEX_MIPFILTER_LINEAR:
1886 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1887 default:
1888 case PIPE_TEX_MIPFILTER_NONE:
1889 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1890 }
1891 }
1892
1893 static unsigned si_tex_compare(unsigned compare)
1894 {
1895 switch (compare) {
1896 default:
1897 case PIPE_FUNC_NEVER:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1899 case PIPE_FUNC_LESS:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1901 case PIPE_FUNC_EQUAL:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1903 case PIPE_FUNC_LEQUAL:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1905 case PIPE_FUNC_GREATER:
1906 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1907 case PIPE_FUNC_NOTEQUAL:
1908 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1909 case PIPE_FUNC_GEQUAL:
1910 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1911 case PIPE_FUNC_ALWAYS:
1912 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1913 }
1914 }
1915
1916 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1917 unsigned view_target, unsigned nr_samples)
1918 {
1919 unsigned res_target = rtex->resource.b.b.target;
1920
1921 if (view_target == PIPE_TEXTURE_CUBE ||
1922 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1923 res_target = view_target;
1924 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1925 else if (res_target == PIPE_TEXTURE_CUBE ||
1926 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1927 res_target = PIPE_TEXTURE_2D_ARRAY;
1928
1929 /* GFX9 allocates 1D textures as 2D. */
1930 if ((res_target == PIPE_TEXTURE_1D ||
1931 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1932 sscreen->b.chip_class >= GFX9 &&
1933 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1934 if (res_target == PIPE_TEXTURE_1D)
1935 res_target = PIPE_TEXTURE_2D;
1936 else
1937 res_target = PIPE_TEXTURE_2D_ARRAY;
1938 }
1939
1940 switch (res_target) {
1941 default:
1942 case PIPE_TEXTURE_1D:
1943 return V_008F1C_SQ_RSRC_IMG_1D;
1944 case PIPE_TEXTURE_1D_ARRAY:
1945 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1946 case PIPE_TEXTURE_2D:
1947 case PIPE_TEXTURE_RECT:
1948 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1949 V_008F1C_SQ_RSRC_IMG_2D;
1950 case PIPE_TEXTURE_2D_ARRAY:
1951 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1952 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1953 case PIPE_TEXTURE_3D:
1954 return V_008F1C_SQ_RSRC_IMG_3D;
1955 case PIPE_TEXTURE_CUBE:
1956 case PIPE_TEXTURE_CUBE_ARRAY:
1957 return V_008F1C_SQ_RSRC_IMG_CUBE;
1958 }
1959 }
1960
1961 /*
1962 * Format support testing
1963 */
1964
1965 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1966 {
1967 const struct util_format_description *desc = util_format_description(format);
1968 if (!desc)
1969 return false;
1970
1971 return si_translate_texformat(screen, format, desc,
1972 util_format_get_first_non_void_channel(format)) != ~0U;
1973 }
1974
1975 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1976 const struct util_format_description *desc,
1977 int first_non_void)
1978 {
1979 int i;
1980
1981 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1982 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1983
1984 assert(first_non_void >= 0);
1985
1986 if (desc->nr_channels == 4 &&
1987 desc->channel[0].size == 10 &&
1988 desc->channel[1].size == 10 &&
1989 desc->channel[2].size == 10 &&
1990 desc->channel[3].size == 2)
1991 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1992
1993 /* See whether the components are of the same size. */
1994 for (i = 0; i < desc->nr_channels; i++) {
1995 if (desc->channel[first_non_void].size != desc->channel[i].size)
1996 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1997 }
1998
1999 switch (desc->channel[first_non_void].size) {
2000 case 8:
2001 switch (desc->nr_channels) {
2002 case 1:
2003 case 3: /* 3 loads */
2004 return V_008F0C_BUF_DATA_FORMAT_8;
2005 case 2:
2006 return V_008F0C_BUF_DATA_FORMAT_8_8;
2007 case 4:
2008 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
2009 }
2010 break;
2011 case 16:
2012 switch (desc->nr_channels) {
2013 case 1:
2014 case 3: /* 3 loads */
2015 return V_008F0C_BUF_DATA_FORMAT_16;
2016 case 2:
2017 return V_008F0C_BUF_DATA_FORMAT_16_16;
2018 case 4:
2019 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2020 }
2021 break;
2022 case 32:
2023 switch (desc->nr_channels) {
2024 case 1:
2025 return V_008F0C_BUF_DATA_FORMAT_32;
2026 case 2:
2027 return V_008F0C_BUF_DATA_FORMAT_32_32;
2028 case 3:
2029 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2030 case 4:
2031 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2032 }
2033 break;
2034 case 64:
2035 /* Legacy double formats. */
2036 switch (desc->nr_channels) {
2037 case 1: /* 1 load */
2038 return V_008F0C_BUF_DATA_FORMAT_32_32;
2039 case 2: /* 1 load */
2040 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2041 case 3: /* 3 loads */
2042 return V_008F0C_BUF_DATA_FORMAT_32_32;
2043 case 4: /* 2 loads */
2044 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2045 }
2046 break;
2047 }
2048
2049 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2050 }
2051
2052 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2053 const struct util_format_description *desc,
2054 int first_non_void)
2055 {
2056 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2057 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2058
2059 assert(first_non_void >= 0);
2060
2061 switch (desc->channel[first_non_void].type) {
2062 case UTIL_FORMAT_TYPE_SIGNED:
2063 case UTIL_FORMAT_TYPE_FIXED:
2064 if (desc->channel[first_non_void].size >= 32 ||
2065 desc->channel[first_non_void].pure_integer)
2066 return V_008F0C_BUF_NUM_FORMAT_SINT;
2067 else if (desc->channel[first_non_void].normalized)
2068 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2069 else
2070 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2071 break;
2072 case UTIL_FORMAT_TYPE_UNSIGNED:
2073 if (desc->channel[first_non_void].size >= 32 ||
2074 desc->channel[first_non_void].pure_integer)
2075 return V_008F0C_BUF_NUM_FORMAT_UINT;
2076 else if (desc->channel[first_non_void].normalized)
2077 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2078 else
2079 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2080 break;
2081 case UTIL_FORMAT_TYPE_FLOAT:
2082 default:
2083 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2084 }
2085 }
2086
2087 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2088 enum pipe_format format,
2089 unsigned usage)
2090 {
2091 const struct util_format_description *desc;
2092 int first_non_void;
2093 unsigned data_format;
2094
2095 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2096 PIPE_BIND_SAMPLER_VIEW |
2097 PIPE_BIND_VERTEX_BUFFER)) == 0);
2098
2099 desc = util_format_description(format);
2100 if (!desc)
2101 return 0;
2102
2103 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2104 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2105 * for read-only access (with caveats surrounding bounds checks), but
2106 * obviously fails for write access which we have to implement for
2107 * shader images. Luckily, OpenGL doesn't expect this to be supported
2108 * anyway, and so the only impact is on PBO uploads / downloads, which
2109 * shouldn't be expected to be fast for GL_RGB anyway.
2110 */
2111 if (desc->block.bits == 3 * 8 ||
2112 desc->block.bits == 3 * 16) {
2113 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2114 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2115 if (!usage)
2116 return 0;
2117 }
2118 }
2119
2120 first_non_void = util_format_get_first_non_void_channel(format);
2121 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2122 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2123 return 0;
2124
2125 return usage;
2126 }
2127
2128 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2129 {
2130 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2131 si_translate_colorswap(format, false) != ~0U;
2132 }
2133
2134 static bool si_is_zs_format_supported(enum pipe_format format)
2135 {
2136 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2137 }
2138
2139 static boolean si_is_format_supported(struct pipe_screen *screen,
2140 enum pipe_format format,
2141 enum pipe_texture_target target,
2142 unsigned sample_count,
2143 unsigned usage)
2144 {
2145 unsigned retval = 0;
2146
2147 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2148 R600_ERR("r600: unsupported texture type %d\n", target);
2149 return false;
2150 }
2151
2152 if (!util_format_is_supported(format, usage))
2153 return false;
2154
2155 if (sample_count > 1) {
2156 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2157 return false;
2158
2159 if (usage & PIPE_BIND_SHADER_IMAGE)
2160 return false;
2161
2162 switch (sample_count) {
2163 case 2:
2164 case 4:
2165 case 8:
2166 break;
2167 case 16:
2168 if (format == PIPE_FORMAT_NONE)
2169 return true;
2170 else
2171 return false;
2172 default:
2173 return false;
2174 }
2175 }
2176
2177 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2178 PIPE_BIND_SHADER_IMAGE)) {
2179 if (target == PIPE_BUFFER) {
2180 retval |= si_is_vertex_format_supported(
2181 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2182 PIPE_BIND_SHADER_IMAGE));
2183 } else {
2184 if (si_is_sampler_format_supported(screen, format))
2185 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2186 PIPE_BIND_SHADER_IMAGE);
2187 }
2188 }
2189
2190 if ((usage & (PIPE_BIND_RENDER_TARGET |
2191 PIPE_BIND_DISPLAY_TARGET |
2192 PIPE_BIND_SCANOUT |
2193 PIPE_BIND_SHARED |
2194 PIPE_BIND_BLENDABLE)) &&
2195 si_is_colorbuffer_format_supported(format)) {
2196 retval |= usage &
2197 (PIPE_BIND_RENDER_TARGET |
2198 PIPE_BIND_DISPLAY_TARGET |
2199 PIPE_BIND_SCANOUT |
2200 PIPE_BIND_SHARED);
2201 if (!util_format_is_pure_integer(format) &&
2202 !util_format_is_depth_or_stencil(format))
2203 retval |= usage & PIPE_BIND_BLENDABLE;
2204 }
2205
2206 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2207 si_is_zs_format_supported(format)) {
2208 retval |= PIPE_BIND_DEPTH_STENCIL;
2209 }
2210
2211 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2212 retval |= si_is_vertex_format_supported(screen, format,
2213 PIPE_BIND_VERTEX_BUFFER);
2214 }
2215
2216 if ((usage & PIPE_BIND_LINEAR) &&
2217 !util_format_is_compressed(format) &&
2218 !(usage & PIPE_BIND_DEPTH_STENCIL))
2219 retval |= PIPE_BIND_LINEAR;
2220
2221 return retval == usage;
2222 }
2223
2224 /*
2225 * framebuffer handling
2226 */
2227
2228 static void si_choose_spi_color_formats(struct r600_surface *surf,
2229 unsigned format, unsigned swap,
2230 unsigned ntype, bool is_depth)
2231 {
2232 /* Alpha is needed for alpha-to-coverage.
2233 * Blending may be with or without alpha.
2234 */
2235 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2236 unsigned alpha = 0; /* exports alpha, but may not support blending */
2237 unsigned blend = 0; /* supports blending, but may not export alpha */
2238 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2239
2240 /* Choose the SPI color formats. These are required values for RB+.
2241 * Other chips have multiple choices, though they are not necessarily better.
2242 */
2243 switch (format) {
2244 case V_028C70_COLOR_5_6_5:
2245 case V_028C70_COLOR_1_5_5_5:
2246 case V_028C70_COLOR_5_5_5_1:
2247 case V_028C70_COLOR_4_4_4_4:
2248 case V_028C70_COLOR_10_11_11:
2249 case V_028C70_COLOR_11_11_10:
2250 case V_028C70_COLOR_8:
2251 case V_028C70_COLOR_8_8:
2252 case V_028C70_COLOR_8_8_8_8:
2253 case V_028C70_COLOR_10_10_10_2:
2254 case V_028C70_COLOR_2_10_10_10:
2255 if (ntype == V_028C70_NUMBER_UINT)
2256 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2257 else if (ntype == V_028C70_NUMBER_SINT)
2258 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2259 else
2260 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2261 break;
2262
2263 case V_028C70_COLOR_16:
2264 case V_028C70_COLOR_16_16:
2265 case V_028C70_COLOR_16_16_16_16:
2266 if (ntype == V_028C70_NUMBER_UNORM ||
2267 ntype == V_028C70_NUMBER_SNORM) {
2268 /* UNORM16 and SNORM16 don't support blending */
2269 if (ntype == V_028C70_NUMBER_UNORM)
2270 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2271 else
2272 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2273
2274 /* Use 32 bits per channel for blending. */
2275 if (format == V_028C70_COLOR_16) {
2276 if (swap == V_028C70_SWAP_STD) { /* R */
2277 blend = V_028714_SPI_SHADER_32_R;
2278 blend_alpha = V_028714_SPI_SHADER_32_AR;
2279 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2280 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2281 else
2282 assert(0);
2283 } else if (format == V_028C70_COLOR_16_16) {
2284 if (swap == V_028C70_SWAP_STD) { /* RG */
2285 blend = V_028714_SPI_SHADER_32_GR;
2286 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2287 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2288 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2289 else
2290 assert(0);
2291 } else /* 16_16_16_16 */
2292 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2293 } else if (ntype == V_028C70_NUMBER_UINT)
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2295 else if (ntype == V_028C70_NUMBER_SINT)
2296 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2297 else if (ntype == V_028C70_NUMBER_FLOAT)
2298 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2299 else
2300 assert(0);
2301 break;
2302
2303 case V_028C70_COLOR_32:
2304 if (swap == V_028C70_SWAP_STD) { /* R */
2305 blend = normal = V_028714_SPI_SHADER_32_R;
2306 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2307 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2308 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2309 else
2310 assert(0);
2311 break;
2312
2313 case V_028C70_COLOR_32_32:
2314 if (swap == V_028C70_SWAP_STD) { /* RG */
2315 blend = normal = V_028714_SPI_SHADER_32_GR;
2316 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2317 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2318 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2319 else
2320 assert(0);
2321 break;
2322
2323 case V_028C70_COLOR_32_32_32_32:
2324 case V_028C70_COLOR_8_24:
2325 case V_028C70_COLOR_24_8:
2326 case V_028C70_COLOR_X24_8_32_FLOAT:
2327 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2328 break;
2329
2330 default:
2331 assert(0);
2332 return;
2333 }
2334
2335 /* The DB->CB copy needs 32_ABGR. */
2336 if (is_depth)
2337 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2338
2339 surf->spi_shader_col_format = normal;
2340 surf->spi_shader_col_format_alpha = alpha;
2341 surf->spi_shader_col_format_blend = blend;
2342 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2343 }
2344
2345 static void si_initialize_color_surface(struct si_context *sctx,
2346 struct r600_surface *surf)
2347 {
2348 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2349 unsigned color_info, color_attrib;
2350 unsigned format, swap, ntype, endian;
2351 const struct util_format_description *desc;
2352 int firstchan;
2353 unsigned blend_clamp = 0, blend_bypass = 0;
2354
2355 desc = util_format_description(surf->base.format);
2356 for (firstchan = 0; firstchan < 4; firstchan++) {
2357 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2358 break;
2359 }
2360 }
2361 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2362 ntype = V_028C70_NUMBER_FLOAT;
2363 } else {
2364 ntype = V_028C70_NUMBER_UNORM;
2365 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2366 ntype = V_028C70_NUMBER_SRGB;
2367 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2368 if (desc->channel[firstchan].pure_integer) {
2369 ntype = V_028C70_NUMBER_SINT;
2370 } else {
2371 assert(desc->channel[firstchan].normalized);
2372 ntype = V_028C70_NUMBER_SNORM;
2373 }
2374 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2375 if (desc->channel[firstchan].pure_integer) {
2376 ntype = V_028C70_NUMBER_UINT;
2377 } else {
2378 assert(desc->channel[firstchan].normalized);
2379 ntype = V_028C70_NUMBER_UNORM;
2380 }
2381 }
2382 }
2383
2384 format = si_translate_colorformat(surf->base.format);
2385 if (format == V_028C70_COLOR_INVALID) {
2386 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2387 }
2388 assert(format != V_028C70_COLOR_INVALID);
2389 swap = si_translate_colorswap(surf->base.format, false);
2390 endian = si_colorformat_endian_swap(format);
2391
2392 /* blend clamp should be set for all NORM/SRGB types */
2393 if (ntype == V_028C70_NUMBER_UNORM ||
2394 ntype == V_028C70_NUMBER_SNORM ||
2395 ntype == V_028C70_NUMBER_SRGB)
2396 blend_clamp = 1;
2397
2398 /* set blend bypass according to docs if SINT/UINT or
2399 8/24 COLOR variants */
2400 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2401 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2402 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2403 blend_clamp = 0;
2404 blend_bypass = 1;
2405 }
2406
2407 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2408 if (format == V_028C70_COLOR_8 ||
2409 format == V_028C70_COLOR_8_8 ||
2410 format == V_028C70_COLOR_8_8_8_8)
2411 surf->color_is_int8 = true;
2412 else if (format == V_028C70_COLOR_10_10_10_2 ||
2413 format == V_028C70_COLOR_2_10_10_10)
2414 surf->color_is_int10 = true;
2415 }
2416
2417 color_info = S_028C70_FORMAT(format) |
2418 S_028C70_COMP_SWAP(swap) |
2419 S_028C70_BLEND_CLAMP(blend_clamp) |
2420 S_028C70_BLEND_BYPASS(blend_bypass) |
2421 S_028C70_SIMPLE_FLOAT(1) |
2422 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2423 ntype != V_028C70_NUMBER_SNORM &&
2424 ntype != V_028C70_NUMBER_SRGB &&
2425 format != V_028C70_COLOR_8_24 &&
2426 format != V_028C70_COLOR_24_8) |
2427 S_028C70_NUMBER_TYPE(ntype) |
2428 S_028C70_ENDIAN(endian);
2429
2430 /* Intensity is implemented as Red, so treat it that way. */
2431 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2432 util_format_is_intensity(surf->base.format));
2433
2434 if (rtex->resource.b.b.nr_samples > 1) {
2435 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2436
2437 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2438 S_028C74_NUM_FRAGMENTS(log_samples);
2439
2440 if (rtex->fmask.size) {
2441 color_info |= S_028C70_COMPRESSION(1);
2442 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2443
2444 if (sctx->b.chip_class == SI) {
2445 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2446 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2447 }
2448 }
2449 }
2450
2451 if (sctx->b.chip_class >= VI) {
2452 unsigned max_uncompressed_block_size = 2;
2453
2454 if (rtex->resource.b.b.nr_samples > 1) {
2455 if (rtex->surface.bpe == 1)
2456 max_uncompressed_block_size = 0;
2457 else if (rtex->surface.bpe == 2)
2458 max_uncompressed_block_size = 1;
2459 }
2460
2461 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2462 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2463 }
2464
2465 /* This must be set for fast clear to work without FMASK. */
2466 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2467 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2468 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2469 }
2470
2471 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2472 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2473
2474 if (sctx->b.chip_class >= GFX9) {
2475 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2476
2477 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2478 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2479 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2480 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2481 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2482 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2483 }
2484
2485 surf->cb_color_view = color_view;
2486 surf->cb_color_info = color_info;
2487 surf->cb_color_attrib = color_attrib;
2488
2489 /* Determine pixel shader export format */
2490 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2491
2492 surf->color_initialized = true;
2493 }
2494
2495 static void si_init_depth_surface(struct si_context *sctx,
2496 struct r600_surface *surf)
2497 {
2498 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2499 unsigned level = surf->base.u.tex.level;
2500 unsigned format, stencil_format;
2501 uint32_t z_info, s_info;
2502
2503 format = si_translate_dbformat(rtex->db_render_format);
2504 stencil_format = rtex->surface.has_stencil ?
2505 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2506
2507 assert(format != V_028040_Z_INVALID);
2508 if (format == V_028040_Z_INVALID)
2509 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2510
2511 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2512 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2513 surf->db_htile_data_base = 0;
2514 surf->db_htile_surface = 0;
2515
2516 if (sctx->b.chip_class >= GFX9) {
2517 assert(rtex->surface.u.gfx9.surf_offset == 0);
2518 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2519 surf->db_stencil_base = (rtex->resource.gpu_address +
2520 rtex->surface.u.gfx9.stencil_offset) >> 8;
2521 z_info = S_028038_FORMAT(format) |
2522 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2523 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2524 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2525 s_info = S_02803C_FORMAT(stencil_format) |
2526 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2527 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2528 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2529 surf->db_depth_view |= S_028008_MIPID(level);
2530 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2531 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2532
2533 if (r600_htile_enabled(rtex, level)) {
2534 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2535 S_028038_ALLOW_EXPCLEAR(1);
2536
2537 if (rtex->tc_compatible_htile) {
2538 unsigned max_zplanes = 4;
2539
2540 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2541 rtex->resource.b.b.nr_samples > 1)
2542 max_zplanes = 2;
2543
2544 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2545 S_028038_ITERATE_FLUSH(1);
2546 s_info |= S_02803C_ITERATE_FLUSH(1);
2547 }
2548
2549 if (rtex->surface.has_stencil) {
2550 /* Stencil buffer workaround ported from the SI-CI-VI code.
2551 * See that for explanation.
2552 */
2553 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2554 } else {
2555 /* Use all HTILE for depth if there's no stencil. */
2556 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2557 }
2558
2559 surf->db_htile_data_base = (rtex->resource.gpu_address +
2560 rtex->htile_offset) >> 8;
2561 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2562 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2563 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2564 }
2565 } else {
2566 /* SI-CI-VI */
2567 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2568
2569 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2570
2571 surf->db_depth_base = (rtex->resource.gpu_address +
2572 rtex->surface.u.legacy.level[level].offset) >> 8;
2573 surf->db_stencil_base = (rtex->resource.gpu_address +
2574 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2575
2576 z_info = S_028040_FORMAT(format) |
2577 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2578 s_info = S_028044_FORMAT(stencil_format);
2579 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2580
2581 if (sctx->b.chip_class >= CIK) {
2582 struct radeon_info *info = &sctx->screen->b.info;
2583 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2584 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2585 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2586 unsigned tile_mode = info->si_tile_mode_array[index];
2587 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2588 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2589
2590 surf->db_depth_info |=
2591 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2592 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2593 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2594 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2595 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2596 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2597 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2598 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2599 } else {
2600 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2601 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2602 tile_mode_index = si_tile_mode_index(rtex, level, true);
2603 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2604 }
2605
2606 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2607 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2608 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2609 levelinfo->nblk_y) / 64 - 1);
2610
2611 if (r600_htile_enabled(rtex, level)) {
2612 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2613 S_028040_ALLOW_EXPCLEAR(1);
2614
2615 if (rtex->surface.has_stencil) {
2616 /* Workaround: For a not yet understood reason, the
2617 * combination of MSAA, fast stencil clear and stencil
2618 * decompress messes with subsequent stencil buffer
2619 * uses. Problem was reproduced on Verde, Bonaire,
2620 * Tonga, and Carrizo.
2621 *
2622 * Disabling EXPCLEAR works around the problem.
2623 *
2624 * Check piglit's arb_texture_multisample-stencil-clear
2625 * test if you want to try changing this.
2626 */
2627 if (rtex->resource.b.b.nr_samples <= 1)
2628 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2629 } else if (!rtex->tc_compatible_htile) {
2630 /* Use all of the htile_buffer for depth if there's no stencil.
2631 * This must not be set when TC-compatible HTILE is enabled
2632 * due to a hw bug.
2633 */
2634 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2635 }
2636
2637 surf->db_htile_data_base = (rtex->resource.gpu_address +
2638 rtex->htile_offset) >> 8;
2639 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2640
2641 if (rtex->tc_compatible_htile) {
2642 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2643
2644 if (rtex->resource.b.b.nr_samples <= 1)
2645 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2646 else if (rtex->resource.b.b.nr_samples <= 4)
2647 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2648 else
2649 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2650 }
2651 }
2652 }
2653
2654 surf->db_z_info = z_info;
2655 surf->db_stencil_info = s_info;
2656
2657 surf->depth_initialized = true;
2658 }
2659
2660 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2661 {
2662 if (sctx->decompression_enabled)
2663 return;
2664
2665 if (sctx->framebuffer.state.zsbuf) {
2666 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2667 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
2668
2669 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2670
2671 if (rtex->surface.has_stencil)
2672 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2673 }
2674
2675 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2676 while (compressed_cb_mask) {
2677 unsigned i = u_bit_scan(&compressed_cb_mask);
2678 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2679 struct r600_texture *rtex = (struct r600_texture*)surf->texture;
2680
2681 if (rtex->fmask.size)
2682 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
2683 if (rtex->dcc_gather_statistics)
2684 rtex->separate_dcc_dirty = true;
2685 }
2686 }
2687
2688 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2689 {
2690 for (int i = 0; i < state->nr_cbufs; ++i) {
2691 struct r600_surface *surf = NULL;
2692 struct r600_texture *rtex;
2693
2694 if (!state->cbufs[i])
2695 continue;
2696 surf = (struct r600_surface*)state->cbufs[i];
2697 rtex = (struct r600_texture*)surf->base.texture;
2698
2699 p_atomic_dec(&rtex->framebuffers_bound);
2700 }
2701 }
2702
2703 static void si_set_framebuffer_state(struct pipe_context *ctx,
2704 const struct pipe_framebuffer_state *state)
2705 {
2706 struct si_context *sctx = (struct si_context *)ctx;
2707 struct pipe_constant_buffer constbuf = {0};
2708 struct r600_surface *surf = NULL;
2709 struct r600_texture *rtex;
2710 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2711 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2712 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2713 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2714 bool old_has_stencil =
2715 old_has_zsbuf &&
2716 ((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2717 bool unbound = false;
2718 int i;
2719
2720 si_update_fb_dirtiness_after_rendering(sctx);
2721
2722 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2723 if (!sctx->framebuffer.state.cbufs[i])
2724 continue;
2725
2726 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2727 if (rtex->dcc_gather_statistics)
2728 vi_separate_dcc_stop_query(ctx, rtex);
2729 }
2730
2731 /* Disable DCC if the formats are incompatible. */
2732 for (i = 0; i < state->nr_cbufs; i++) {
2733 if (!state->cbufs[i])
2734 continue;
2735
2736 surf = (struct r600_surface*)state->cbufs[i];
2737 rtex = (struct r600_texture*)surf->base.texture;
2738
2739 if (!surf->dcc_incompatible)
2740 continue;
2741
2742 /* Since the DCC decompression calls back into set_framebuffer-
2743 * _state, we need to unbind the framebuffer, so that
2744 * vi_separate_dcc_stop_query isn't called twice with the same
2745 * color buffer.
2746 */
2747 if (!unbound) {
2748 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2749 unbound = true;
2750 }
2751
2752 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2753 if (!si_texture_disable_dcc(&sctx->b, rtex))
2754 sctx->b.decompress_dcc(ctx, rtex);
2755
2756 surf->dcc_incompatible = false;
2757 }
2758
2759 /* Only flush TC when changing the framebuffer state, because
2760 * the only client not using TC that can change textures is
2761 * the framebuffer.
2762 *
2763 * Wait for compute shaders because of possible transitions:
2764 * - FB write -> shader read
2765 * - shader write -> FB read
2766 *
2767 * DB caches are flushed on demand (using si_decompress_textures).
2768 *
2769 * When MSAA is enabled, CB and TC caches are flushed on demand
2770 * (after FMASK decompression). Shader write -> FB read transitions
2771 * cannot happen for MSAA textures, because MSAA shader images are
2772 * not supported.
2773 *
2774 * Only flush and wait for CB if there is actually a bound color buffer.
2775 */
2776 if (sctx->framebuffer.nr_samples <= 1 &&
2777 sctx->framebuffer.state.nr_cbufs)
2778 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2779 sctx->framebuffer.CB_has_shader_readable_metadata);
2780
2781 sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2782
2783 /* u_blitter doesn't invoke depth decompression when it does multiple
2784 * blits in a row, but the only case when it matters for DB is when
2785 * doing generate_mipmap. So here we flush DB manually between
2786 * individual generate_mipmap blits.
2787 * Note that lower mipmap levels aren't compressed.
2788 */
2789 if (sctx->generate_mipmap_for_depth) {
2790 si_make_DB_shader_coherent(sctx, 1, false,
2791 sctx->framebuffer.DB_has_shader_readable_metadata);
2792 } else if (sctx->b.chip_class == GFX9) {
2793 /* It appears that DB metadata "leaks" in a sequence of:
2794 * - depth clear
2795 * - DCC decompress for shader image writes (with DB disabled)
2796 * - render with DEPTH_BEFORE_SHADER=1
2797 * Flushing DB metadata works around the problem.
2798 */
2799 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2800 }
2801
2802 /* Take the maximum of the old and new count. If the new count is lower,
2803 * dirtying is needed to disable the unbound colorbuffers.
2804 */
2805 sctx->framebuffer.dirty_cbufs |=
2806 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2807 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2808
2809 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2810 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2811
2812 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2813 sctx->framebuffer.spi_shader_col_format = 0;
2814 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2815 sctx->framebuffer.spi_shader_col_format_blend = 0;
2816 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2817 sctx->framebuffer.color_is_int8 = 0;
2818 sctx->framebuffer.color_is_int10 = 0;
2819
2820 sctx->framebuffer.compressed_cb_mask = 0;
2821 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2822 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2823 sctx->framebuffer.any_dst_linear = false;
2824 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2825 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2826
2827 for (i = 0; i < state->nr_cbufs; i++) {
2828 if (!state->cbufs[i])
2829 continue;
2830
2831 surf = (struct r600_surface*)state->cbufs[i];
2832 rtex = (struct r600_texture*)surf->base.texture;
2833
2834 if (!surf->color_initialized) {
2835 si_initialize_color_surface(sctx, surf);
2836 }
2837
2838 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2839 sctx->framebuffer.spi_shader_col_format |=
2840 surf->spi_shader_col_format << (i * 4);
2841 sctx->framebuffer.spi_shader_col_format_alpha |=
2842 surf->spi_shader_col_format_alpha << (i * 4);
2843 sctx->framebuffer.spi_shader_col_format_blend |=
2844 surf->spi_shader_col_format_blend << (i * 4);
2845 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2846 surf->spi_shader_col_format_blend_alpha << (i * 4);
2847
2848 if (surf->color_is_int8)
2849 sctx->framebuffer.color_is_int8 |= 1 << i;
2850 if (surf->color_is_int10)
2851 sctx->framebuffer.color_is_int10 |= 1 << i;
2852
2853 if (rtex->fmask.size) {
2854 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2855 }
2856
2857 if (rtex->surface.is_linear)
2858 sctx->framebuffer.any_dst_linear = true;
2859
2860 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2861 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2862
2863 r600_context_add_resource_size(ctx, surf->base.texture);
2864
2865 p_atomic_inc(&rtex->framebuffers_bound);
2866
2867 if (rtex->dcc_gather_statistics) {
2868 /* Dirty tracking must be enabled for DCC usage analysis. */
2869 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2870 vi_separate_dcc_start_query(ctx, rtex);
2871 }
2872 }
2873
2874 struct r600_texture *zstex = NULL;
2875
2876 if (state->zsbuf) {
2877 surf = (struct r600_surface*)state->zsbuf;
2878 zstex = (struct r600_texture*)surf->base.texture;
2879
2880 if (!surf->depth_initialized) {
2881 si_init_depth_surface(sctx, surf);
2882 }
2883
2884 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2885 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2886
2887 r600_context_add_resource_size(ctx, surf->base.texture);
2888 }
2889
2890 si_update_poly_offset_state(sctx);
2891 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2892 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2893
2894 if (sctx->screen->dpbb_allowed)
2895 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
2896
2897 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2898 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2899
2900 if (sctx->screen->has_out_of_order_rast &&
2901 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2902 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2903 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2904 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2905
2906 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2907 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2908 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2909
2910 /* Set sample locations as fragment shader constants. */
2911 switch (sctx->framebuffer.nr_samples) {
2912 case 1:
2913 constbuf.user_buffer = sctx->sample_locations_1x;
2914 break;
2915 case 2:
2916 constbuf.user_buffer = sctx->sample_locations_2x;
2917 break;
2918 case 4:
2919 constbuf.user_buffer = sctx->sample_locations_4x;
2920 break;
2921 case 8:
2922 constbuf.user_buffer = sctx->sample_locations_8x;
2923 break;
2924 case 16:
2925 constbuf.user_buffer = sctx->sample_locations_16x;
2926 break;
2927 default:
2928 R600_ERR("Requested an invalid number of samples %i.\n",
2929 sctx->framebuffer.nr_samples);
2930 assert(0);
2931 }
2932 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2933 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2934
2935 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2936 }
2937
2938 sctx->do_update_shaders = true;
2939
2940 if (!sctx->decompression_enabled) {
2941 /* Prevent textures decompression when the framebuffer state
2942 * changes come from the decompression passes themselves.
2943 */
2944 sctx->need_check_render_feedback = true;
2945 }
2946 }
2947
2948 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2949 {
2950 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2951 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2952 unsigned i, nr_cbufs = state->nr_cbufs;
2953 struct r600_texture *tex = NULL;
2954 struct r600_surface *cb = NULL;
2955 unsigned cb_color_info = 0;
2956
2957 /* Colorbuffers. */
2958 for (i = 0; i < nr_cbufs; i++) {
2959 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2960 unsigned cb_color_attrib;
2961
2962 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2963 continue;
2964
2965 cb = (struct r600_surface*)state->cbufs[i];
2966 if (!cb) {
2967 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2968 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2969 continue;
2970 }
2971
2972 tex = (struct r600_texture *)cb->base.texture;
2973 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2974 &tex->resource, RADEON_USAGE_READWRITE,
2975 tex->resource.b.b.nr_samples > 1 ?
2976 RADEON_PRIO_COLOR_BUFFER_MSAA :
2977 RADEON_PRIO_COLOR_BUFFER);
2978
2979 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2980 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2981 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2982 RADEON_PRIO_CMASK);
2983 }
2984
2985 if (tex->dcc_separate_buffer)
2986 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2987 tex->dcc_separate_buffer,
2988 RADEON_USAGE_READWRITE,
2989 RADEON_PRIO_DCC);
2990
2991 /* Compute mutable surface parameters. */
2992 cb_color_base = tex->resource.gpu_address >> 8;
2993 cb_color_fmask = 0;
2994 cb_dcc_base = 0;
2995 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2996 cb_color_attrib = cb->cb_color_attrib;
2997
2998 if (tex->fmask.size) {
2999 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
3000 cb_color_fmask |= tex->fmask.tile_swizzle;
3001 }
3002
3003 /* Set up DCC. */
3004 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3005 bool is_msaa_resolve_dst = state->cbufs[0] &&
3006 state->cbufs[0]->texture->nr_samples > 1 &&
3007 state->cbufs[1] == &cb->base &&
3008 state->cbufs[1]->texture->nr_samples <= 1;
3009
3010 if (!is_msaa_resolve_dst)
3011 cb_color_info |= S_028C70_DCC_ENABLE(1);
3012
3013 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
3014 tex->dcc_offset) >> 8;
3015 cb_dcc_base |= tex->surface.tile_swizzle;
3016 }
3017
3018 if (sctx->b.chip_class >= GFX9) {
3019 struct gfx9_surf_meta_flags meta;
3020
3021 if (tex->dcc_offset)
3022 meta = tex->surface.u.gfx9.dcc;
3023 else
3024 meta = tex->surface.u.gfx9.cmask;
3025
3026 /* Set mutable surface parameters. */
3027 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3028 cb_color_base |= tex->surface.tile_swizzle;
3029 if (!tex->fmask.size)
3030 cb_color_fmask = cb_color_base;
3031 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3032 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3033 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3034 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3035
3036 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3037 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3038 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
3039 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3040 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3041 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3042 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3043 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3044 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3045 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
3046 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3047 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
3048 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3049 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3050 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3051 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
3052
3053 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3054 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3055 } else {
3056 /* Compute mutable surface parameters (SI-CI-VI). */
3057 const struct legacy_surf_level *level_info =
3058 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3059 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3060 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3061
3062 cb_color_base += level_info->offset >> 8;
3063 /* Only macrotiled modes can set tile swizzle. */
3064 if (level_info->mode == RADEON_SURF_MODE_2D)
3065 cb_color_base |= tex->surface.tile_swizzle;
3066
3067 if (!tex->fmask.size)
3068 cb_color_fmask = cb_color_base;
3069 if (cb_dcc_base)
3070 cb_dcc_base += level_info->dcc_offset >> 8;
3071
3072 pitch_tile_max = level_info->nblk_x / 8 - 1;
3073 slice_tile_max = level_info->nblk_x *
3074 level_info->nblk_y / 64 - 1;
3075 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3076
3077 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3078 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3079 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3080
3081 if (tex->fmask.size) {
3082 if (sctx->b.chip_class >= CIK)
3083 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
3084 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
3085 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
3086 } else {
3087 /* This must be set for fast clear to work without FMASK. */
3088 if (sctx->b.chip_class >= CIK)
3089 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3090 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3091 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3092 }
3093
3094 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3095 sctx->b.chip_class >= VI ? 14 : 13);
3096 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3097 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3098 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3099 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3100 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3101 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3102 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3103 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
3104 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3105 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3106 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3107 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3108 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3109
3110 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3111 radeon_emit(cs, cb_dcc_base);
3112 }
3113 }
3114 for (; i < 8 ; i++)
3115 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3116 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3117
3118 /* ZS buffer. */
3119 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3120 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
3121 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
3122
3123 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
3124 &rtex->resource, RADEON_USAGE_READWRITE,
3125 zb->base.texture->nr_samples > 1 ?
3126 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3127 RADEON_PRIO_DEPTH_BUFFER);
3128
3129 if (sctx->b.chip_class >= GFX9) {
3130 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3131 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3132 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
3133 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3134
3135 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3136 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3137 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3138 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3139 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3140 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
3141 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3142 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
3143 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3144 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
3145 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3146 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
3147
3148 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3149 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3150 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3151 } else {
3152 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3153
3154 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3155 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3156 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3157 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
3158 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3159 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3160 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3161 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3162 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3163 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3164 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3165 }
3166
3167 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3168 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3169 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3170
3171 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3172 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3173 } else if (sctx->framebuffer.dirty_zsbuf) {
3174 if (sctx->b.chip_class >= GFX9)
3175 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3176 else
3177 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3178
3179 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3180 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3181 }
3182
3183 /* Framebuffer dimensions. */
3184 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3185 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3186 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3187
3188 if (sctx->screen->dfsm_allowed) {
3189 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3190 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3191 }
3192
3193 sctx->framebuffer.dirty_cbufs = 0;
3194 sctx->framebuffer.dirty_zsbuf = false;
3195 }
3196
3197 static void si_emit_msaa_sample_locs(struct si_context *sctx,
3198 struct r600_atom *atom)
3199 {
3200 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3201 unsigned nr_samples = sctx->framebuffer.nr_samples;
3202 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3203
3204 /* Smoothing (only possible with nr_samples == 1) uses the same
3205 * sample locations as the MSAA it simulates.
3206 */
3207 if (nr_samples <= 1 && sctx->smoothing_enabled)
3208 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3209
3210 /* On Polaris, the small primitive filter uses the sample locations
3211 * even when MSAA is off, so we need to make sure they're set to 0.
3212 */
3213 if (has_msaa_sample_loc_bug)
3214 nr_samples = MAX2(nr_samples, 1);
3215
3216 if (nr_samples != sctx->msaa_sample_locs.nr_samples) {
3217 sctx->msaa_sample_locs.nr_samples = nr_samples;
3218 si_emit_sample_locations(cs, nr_samples);
3219 }
3220
3221 if (sctx->b.family >= CHIP_POLARIS10) {
3222 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3223 unsigned small_prim_filter_cntl =
3224 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3225 /* line bug */
3226 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
3227
3228 /* The alternative of setting sample locations to 0 would
3229 * require a DB flush to avoid Z errors, see
3230 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3231 */
3232 if (has_msaa_sample_loc_bug &&
3233 sctx->framebuffer.nr_samples > 1 &&
3234 rs && !rs->multisample_enable)
3235 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3236
3237 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3238 small_prim_filter_cntl);
3239 }
3240 }
3241
3242 static bool si_out_of_order_rasterization(struct si_context *sctx)
3243 {
3244 struct si_state_blend *blend = sctx->queued.named.blend;
3245 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3246
3247 if (!sctx->screen->has_out_of_order_rast)
3248 return false;
3249
3250 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3251
3252 if (blend) {
3253 colormask &= blend->cb_target_enabled_4bit;
3254 } else {
3255 colormask = 0;
3256 }
3257
3258 /* Conservative: No logic op. */
3259 if (colormask && blend->logicop_enable)
3260 return false;
3261
3262 struct si_dsa_order_invariance dsa_order_invariant = {
3263 .zs = true, .pass_set = true, .pass_last = false
3264 };
3265
3266 if (sctx->framebuffer.state.zsbuf) {
3267 struct r600_texture *zstex =
3268 (struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
3269 bool has_stencil = zstex->surface.has_stencil;
3270 dsa_order_invariant = dsa->order_invariance[has_stencil];
3271 if (!dsa_order_invariant.zs)
3272 return false;
3273
3274 /* The set of PS invocations is always order invariant,
3275 * except when early Z/S tests are requested. */
3276 if (sctx->ps_shader.cso &&
3277 sctx->ps_shader.cso->info.writes_memory &&
3278 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3279 !dsa_order_invariant.pass_set)
3280 return false;
3281
3282 if (sctx->b.num_perfect_occlusion_queries != 0 &&
3283 !dsa_order_invariant.pass_set)
3284 return false;
3285 }
3286
3287 if (!colormask)
3288 return true;
3289
3290 unsigned blendmask = colormask & blend->blend_enable_4bit;
3291
3292 if (blendmask) {
3293 /* Only commutative blending. */
3294 if (blendmask & ~blend->commutative_4bit)
3295 return false;
3296
3297 if (!dsa_order_invariant.pass_set)
3298 return false;
3299 }
3300
3301 if (colormask & ~blendmask) {
3302 if (!dsa_order_invariant.pass_last)
3303 return false;
3304 }
3305
3306 return true;
3307 }
3308
3309 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
3310 {
3311 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3312 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
3313 /* 33% faster rendering to linear color buffers */
3314 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3315 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3316 unsigned sc_mode_cntl_1 =
3317 S_028A4C_WALK_SIZE(dst_is_linear) |
3318 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3319 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3320 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3321 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3322 /* always 1: */
3323 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3324 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3325 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3326 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3327 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3328 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3329
3330 int setup_samples = sctx->framebuffer.nr_samples > 1 ? sctx->framebuffer.nr_samples :
3331 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0;
3332
3333 /* Required by OpenGL line rasterization.
3334 *
3335 * TODO: We should also enable perpendicular endcaps for AA lines,
3336 * but that requires implementing line stippling in the pixel
3337 * shader. SC can only do line stippling with axis-aligned
3338 * endcaps.
3339 */
3340 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3341
3342 if (setup_samples > 1) {
3343 /* distance from the pixel center, indexed by log2(nr_samples) */
3344 static unsigned max_dist[] = {
3345 0, /* unused */
3346 4, /* 2x MSAA */
3347 6, /* 4x MSAA */
3348 7, /* 8x MSAA */
3349 8, /* 16x MSAA */
3350 };
3351 unsigned log_samples = util_logbase2(setup_samples);
3352 unsigned log_ps_iter_samples =
3353 util_logbase2(util_next_power_of_two(sctx->ps_iter_samples));
3354
3355 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3356 radeon_emit(cs, sc_line_cntl |
3357 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3358 radeon_emit(cs, S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3359 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3360 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3361
3362 if (sctx->framebuffer.nr_samples > 1) {
3363 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3364 S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
3365 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3366 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3367 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples) |
3368 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3369 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3370 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3371 S_028A4C_PS_ITER_SAMPLE(sctx->ps_iter_samples > 1) |
3372 sc_mode_cntl_1);
3373 } else if (sctx->smoothing_enabled) {
3374 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3375 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3376 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3377 S_028804_OVERRASTERIZATION_AMOUNT(log_samples));
3378 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3379 sc_mode_cntl_1);
3380 }
3381 } else {
3382 radeon_set_context_reg_seq(cs, R_028BDC_PA_SC_LINE_CNTL, 2);
3383 radeon_emit(cs, sc_line_cntl); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3384 radeon_emit(cs, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3385
3386 radeon_set_context_reg(cs, R_028804_DB_EQAA,
3387 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3388 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3389 radeon_set_context_reg(cs, R_028A4C_PA_SC_MODE_CNTL_1,
3390 sc_mode_cntl_1);
3391 }
3392
3393 /* GFX9: Flush DFSM when the AA mode changes. */
3394 if (sctx->screen->dfsm_allowed) {
3395 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3396 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3397 }
3398 }
3399
3400 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3401 {
3402 struct si_context *sctx = (struct si_context *)ctx;
3403
3404 if (sctx->ps_iter_samples == min_samples)
3405 return;
3406
3407 sctx->ps_iter_samples = min_samples;
3408 sctx->do_update_shaders = true;
3409
3410 if (sctx->framebuffer.nr_samples > 1)
3411 si_mark_atom_dirty(sctx, &sctx->msaa_config);
3412 if (sctx->screen->dpbb_allowed)
3413 si_mark_atom_dirty(sctx, &sctx->dpbb_state);
3414 }
3415
3416 /*
3417 * Samplers
3418 */
3419
3420 /**
3421 * Build the sampler view descriptor for a buffer texture.
3422 * @param state 256-bit descriptor; only the high 128 bits are filled in
3423 */
3424 void
3425 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3426 enum pipe_format format,
3427 unsigned offset, unsigned size,
3428 uint32_t *state)
3429 {
3430 const struct util_format_description *desc;
3431 int first_non_void;
3432 unsigned stride;
3433 unsigned num_records;
3434 unsigned num_format, data_format;
3435
3436 desc = util_format_description(format);
3437 first_non_void = util_format_get_first_non_void_channel(format);
3438 stride = desc->block.bits / 8;
3439 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3440 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3441
3442 num_records = size / stride;
3443 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3444
3445 /* The NUM_RECORDS field has a different meaning depending on the chip,
3446 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3447 *
3448 * SI-CIK:
3449 * - If STRIDE == 0, it's in byte units.
3450 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3451 *
3452 * VI:
3453 * - For SMEM and STRIDE == 0, it's in byte units.
3454 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3455 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3456 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3457 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3458 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3459 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3460 * That way the same descriptor can be used by both SMEM and VMEM.
3461 *
3462 * GFX9:
3463 * - For SMEM and STRIDE == 0, it's in byte units.
3464 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3465 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3466 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3467 */
3468 if (screen->b.chip_class >= GFX9)
3469 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3470 * from STRIDE to bytes. This works around it by setting
3471 * NUM_RECORDS to at least the size of one element, so that
3472 * the first element is readable when IDXEN == 0.
3473 *
3474 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3475 * IDXEN is enforced?
3476 */
3477 num_records = num_records ? MAX2(num_records, stride) : 0;
3478 else if (screen->b.chip_class == VI)
3479 num_records *= stride;
3480
3481 state[4] = 0;
3482 state[5] = S_008F04_STRIDE(stride);
3483 state[6] = num_records;
3484 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3485 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3486 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3487 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3488 S_008F0C_NUM_FORMAT(num_format) |
3489 S_008F0C_DATA_FORMAT(data_format);
3490 }
3491
3492 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3493 {
3494 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3495
3496 if (swizzle[3] == PIPE_SWIZZLE_X) {
3497 /* For the pre-defined border color values (white, opaque
3498 * black, transparent black), the only thing that matters is
3499 * that the alpha channel winds up in the correct place
3500 * (because the RGB channels are all the same) so either of
3501 * these enumerations will work.
3502 */
3503 if (swizzle[2] == PIPE_SWIZZLE_Y)
3504 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3505 else
3506 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3507 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3508 if (swizzle[1] == PIPE_SWIZZLE_Y)
3509 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3510 else
3511 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3512 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3513 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3514 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3515 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3516 }
3517
3518 return bc_swizzle;
3519 }
3520
3521 /**
3522 * Build the sampler view descriptor for a texture.
3523 */
3524 void
3525 si_make_texture_descriptor(struct si_screen *screen,
3526 struct r600_texture *tex,
3527 bool sampler,
3528 enum pipe_texture_target target,
3529 enum pipe_format pipe_format,
3530 const unsigned char state_swizzle[4],
3531 unsigned first_level, unsigned last_level,
3532 unsigned first_layer, unsigned last_layer,
3533 unsigned width, unsigned height, unsigned depth,
3534 uint32_t *state,
3535 uint32_t *fmask_state)
3536 {
3537 struct pipe_resource *res = &tex->resource.b.b;
3538 const struct util_format_description *desc;
3539 unsigned char swizzle[4];
3540 int first_non_void;
3541 unsigned num_format, data_format, type;
3542 uint64_t va;
3543
3544 desc = util_format_description(pipe_format);
3545
3546 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3547 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3548 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3549 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3550
3551 switch (pipe_format) {
3552 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3553 case PIPE_FORMAT_X32_S8X24_UINT:
3554 case PIPE_FORMAT_X8Z24_UNORM:
3555 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3556 break;
3557 case PIPE_FORMAT_X24S8_UINT:
3558 /*
3559 * X24S8 is implemented as an 8_8_8_8 data format, to
3560 * fix texture gathers. This affects at least
3561 * GL45-CTS.texture_cube_map_array.sampling on VI.
3562 */
3563 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3564 break;
3565 default:
3566 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3567 }
3568 } else {
3569 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3570 }
3571
3572 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3573
3574 switch (pipe_format) {
3575 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3576 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3577 break;
3578 default:
3579 if (first_non_void < 0) {
3580 if (util_format_is_compressed(pipe_format)) {
3581 switch (pipe_format) {
3582 case PIPE_FORMAT_DXT1_SRGB:
3583 case PIPE_FORMAT_DXT1_SRGBA:
3584 case PIPE_FORMAT_DXT3_SRGBA:
3585 case PIPE_FORMAT_DXT5_SRGBA:
3586 case PIPE_FORMAT_BPTC_SRGBA:
3587 case PIPE_FORMAT_ETC2_SRGB8:
3588 case PIPE_FORMAT_ETC2_SRGB8A1:
3589 case PIPE_FORMAT_ETC2_SRGBA8:
3590 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3591 break;
3592 case PIPE_FORMAT_RGTC1_SNORM:
3593 case PIPE_FORMAT_LATC1_SNORM:
3594 case PIPE_FORMAT_RGTC2_SNORM:
3595 case PIPE_FORMAT_LATC2_SNORM:
3596 case PIPE_FORMAT_ETC2_R11_SNORM:
3597 case PIPE_FORMAT_ETC2_RG11_SNORM:
3598 /* implies float, so use SNORM/UNORM to determine
3599 whether data is signed or not */
3600 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3601 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3602 break;
3603 default:
3604 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3605 break;
3606 }
3607 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3608 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3609 } else {
3610 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3611 }
3612 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3613 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3614 } else {
3615 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3616
3617 switch (desc->channel[first_non_void].type) {
3618 case UTIL_FORMAT_TYPE_FLOAT:
3619 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3620 break;
3621 case UTIL_FORMAT_TYPE_SIGNED:
3622 if (desc->channel[first_non_void].normalized)
3623 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3624 else if (desc->channel[first_non_void].pure_integer)
3625 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3626 else
3627 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3628 break;
3629 case UTIL_FORMAT_TYPE_UNSIGNED:
3630 if (desc->channel[first_non_void].normalized)
3631 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3632 else if (desc->channel[first_non_void].pure_integer)
3633 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3634 else
3635 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3636 }
3637 }
3638 }
3639
3640 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3641 if (data_format == ~0) {
3642 data_format = 0;
3643 }
3644
3645 /* S8 with Z32 HTILE needs a special format. */
3646 if (screen->b.chip_class >= GFX9 &&
3647 pipe_format == PIPE_FORMAT_S8_UINT &&
3648 tex->tc_compatible_htile)
3649 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3650
3651 if (!sampler &&
3652 (res->target == PIPE_TEXTURE_CUBE ||
3653 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3654 (screen->b.chip_class <= VI &&
3655 res->target == PIPE_TEXTURE_3D))) {
3656 /* For the purpose of shader images, treat cube maps and 3D
3657 * textures as 2D arrays. For 3D textures, the address
3658 * calculations for mipmaps are different, so we rely on the
3659 * caller to effectively disable mipmaps.
3660 */
3661 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3662
3663 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3664 } else {
3665 type = si_tex_dim(screen, tex, target, res->nr_samples);
3666 }
3667
3668 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3669 height = 1;
3670 depth = res->array_size;
3671 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3672 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3673 if (sampler || res->target != PIPE_TEXTURE_3D)
3674 depth = res->array_size;
3675 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3676 depth = res->array_size / 6;
3677
3678 state[0] = 0;
3679 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3680 S_008F14_NUM_FORMAT_GFX6(num_format));
3681 state[2] = (S_008F18_WIDTH(width - 1) |
3682 S_008F18_HEIGHT(height - 1) |
3683 S_008F18_PERF_MOD(4));
3684 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3685 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3686 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3687 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3688 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3689 0 : first_level) |
3690 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3691 util_logbase2(res->nr_samples) :
3692 last_level) |
3693 S_008F1C_TYPE(type));
3694 state[4] = 0;
3695 state[5] = S_008F24_BASE_ARRAY(first_layer);
3696 state[6] = 0;
3697 state[7] = 0;
3698
3699 if (screen->b.chip_class >= GFX9) {
3700 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3701
3702 /* Depth is the the last accessible layer on Gfx9.
3703 * The hw doesn't need to know the total number of layers.
3704 */
3705 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3706 state[4] |= S_008F20_DEPTH(depth - 1);
3707 else
3708 state[4] |= S_008F20_DEPTH(last_layer);
3709
3710 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3711 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3712 util_logbase2(res->nr_samples) :
3713 tex->resource.b.b.last_level);
3714 } else {
3715 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3716 state[4] |= S_008F20_DEPTH(depth - 1);
3717 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3718 }
3719
3720 if (tex->dcc_offset) {
3721 unsigned swap = si_translate_colorswap(pipe_format, false);
3722
3723 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3724 } else {
3725 /* The last dword is unused by hw. The shader uses it to clear
3726 * bits in the first dword of sampler state.
3727 */
3728 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3729 if (first_level == last_level)
3730 state[7] = C_008F30_MAX_ANISO_RATIO;
3731 else
3732 state[7] = 0xffffffff;
3733 }
3734 }
3735
3736 /* Initialize the sampler view for FMASK. */
3737 if (tex->fmask.size) {
3738 uint32_t data_format, num_format;
3739
3740 va = tex->resource.gpu_address + tex->fmask.offset;
3741
3742 if (screen->b.chip_class >= GFX9) {
3743 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3744 switch (res->nr_samples) {
3745 case 2:
3746 num_format = V_008F14_IMG_FMASK_8_2_2;
3747 break;
3748 case 4:
3749 num_format = V_008F14_IMG_FMASK_8_4_4;
3750 break;
3751 case 8:
3752 num_format = V_008F14_IMG_FMASK_32_8_8;
3753 break;
3754 default:
3755 unreachable("invalid nr_samples");
3756 }
3757 } else {
3758 switch (res->nr_samples) {
3759 case 2:
3760 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3761 break;
3762 case 4:
3763 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3764 break;
3765 case 8:
3766 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3767 break;
3768 default:
3769 unreachable("invalid nr_samples");
3770 }
3771 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3772 }
3773
3774 fmask_state[0] = (va >> 8) | tex->fmask.tile_swizzle;
3775 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3776 S_008F14_DATA_FORMAT_GFX6(data_format) |
3777 S_008F14_NUM_FORMAT_GFX6(num_format);
3778 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3779 S_008F18_HEIGHT(height - 1);
3780 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3781 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3782 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3783 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3784 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3785 fmask_state[4] = 0;
3786 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3787 fmask_state[6] = 0;
3788 fmask_state[7] = 0;
3789
3790 if (screen->b.chip_class >= GFX9) {
3791 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3792 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3793 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3794 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3795 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3796 } else {
3797 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3798 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3799 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3800 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3801 }
3802 }
3803 }
3804
3805 /**
3806 * Create a sampler view.
3807 *
3808 * @param ctx context
3809 * @param texture texture
3810 * @param state sampler view template
3811 * @param width0 width0 override (for compressed textures as int)
3812 * @param height0 height0 override (for compressed textures as int)
3813 * @param force_level set the base address to the level (for compressed textures)
3814 */
3815 struct pipe_sampler_view *
3816 si_create_sampler_view_custom(struct pipe_context *ctx,
3817 struct pipe_resource *texture,
3818 const struct pipe_sampler_view *state,
3819 unsigned width0, unsigned height0,
3820 unsigned force_level)
3821 {
3822 struct si_context *sctx = (struct si_context*)ctx;
3823 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3824 struct r600_texture *tmp = (struct r600_texture*)texture;
3825 unsigned base_level, first_level, last_level;
3826 unsigned char state_swizzle[4];
3827 unsigned height, depth, width;
3828 unsigned last_layer = state->u.tex.last_layer;
3829 enum pipe_format pipe_format;
3830 const struct legacy_surf_level *surflevel;
3831
3832 if (!view)
3833 return NULL;
3834
3835 /* initialize base object */
3836 view->base = *state;
3837 view->base.texture = NULL;
3838 view->base.reference.count = 1;
3839 view->base.context = ctx;
3840
3841 assert(texture);
3842 pipe_resource_reference(&view->base.texture, texture);
3843
3844 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3845 state->format == PIPE_FORMAT_S8X24_UINT ||
3846 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3847 state->format == PIPE_FORMAT_S8_UINT)
3848 view->is_stencil_sampler = true;
3849
3850 /* Buffer resource. */
3851 if (texture->target == PIPE_BUFFER) {
3852 si_make_buffer_descriptor(sctx->screen,
3853 (struct r600_resource *)texture,
3854 state->format,
3855 state->u.buf.offset,
3856 state->u.buf.size,
3857 view->state);
3858 return &view->base;
3859 }
3860
3861 state_swizzle[0] = state->swizzle_r;
3862 state_swizzle[1] = state->swizzle_g;
3863 state_swizzle[2] = state->swizzle_b;
3864 state_swizzle[3] = state->swizzle_a;
3865
3866 base_level = 0;
3867 first_level = state->u.tex.first_level;
3868 last_level = state->u.tex.last_level;
3869 width = width0;
3870 height = height0;
3871 depth = texture->depth0;
3872
3873 if (sctx->b.chip_class <= VI && force_level) {
3874 assert(force_level == first_level &&
3875 force_level == last_level);
3876 base_level = force_level;
3877 first_level = 0;
3878 last_level = 0;
3879 width = u_minify(width, force_level);
3880 height = u_minify(height, force_level);
3881 depth = u_minify(depth, force_level);
3882 }
3883
3884 /* This is not needed if state trackers set last_layer correctly. */
3885 if (state->target == PIPE_TEXTURE_1D ||
3886 state->target == PIPE_TEXTURE_2D ||
3887 state->target == PIPE_TEXTURE_RECT ||
3888 state->target == PIPE_TEXTURE_CUBE)
3889 last_layer = state->u.tex.first_layer;
3890
3891 /* Texturing with separate depth and stencil. */
3892 pipe_format = state->format;
3893
3894 /* Depth/stencil texturing sometimes needs separate texture. */
3895 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3896 if (!tmp->flushed_depth_texture &&
3897 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
3898 pipe_resource_reference(&view->base.texture, NULL);
3899 FREE(view);
3900 return NULL;
3901 }
3902
3903 assert(tmp->flushed_depth_texture);
3904
3905 /* Override format for the case where the flushed texture
3906 * contains only Z or only S.
3907 */
3908 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3909 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3910
3911 tmp = tmp->flushed_depth_texture;
3912 }
3913
3914 surflevel = tmp->surface.u.legacy.level;
3915
3916 if (tmp->db_compatible) {
3917 if (!view->is_stencil_sampler)
3918 pipe_format = tmp->db_render_format;
3919
3920 switch (pipe_format) {
3921 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3922 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3923 break;
3924 case PIPE_FORMAT_X8Z24_UNORM:
3925 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3926 /* Z24 is always stored like this for DB
3927 * compatibility.
3928 */
3929 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3930 break;
3931 case PIPE_FORMAT_X24S8_UINT:
3932 case PIPE_FORMAT_S8X24_UINT:
3933 case PIPE_FORMAT_X32_S8X24_UINT:
3934 pipe_format = PIPE_FORMAT_S8_UINT;
3935 surflevel = tmp->surface.u.legacy.stencil_level;
3936 break;
3937 default:;
3938 }
3939 }
3940
3941 view->dcc_incompatible =
3942 vi_dcc_formats_are_incompatible(texture,
3943 state->u.tex.first_level,
3944 state->format);
3945
3946 si_make_texture_descriptor(sctx->screen, tmp, true,
3947 state->target, pipe_format, state_swizzle,
3948 first_level, last_level,
3949 state->u.tex.first_layer, last_layer,
3950 width, height, depth,
3951 view->state, view->fmask_state);
3952
3953 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
3954 view->is_integer =
3955 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
3956 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
3957 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
3958 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
3959 view->base_level_info = &surflevel[base_level];
3960 view->base_level = base_level;
3961 view->block_width = util_format_get_blockwidth(pipe_format);
3962 return &view->base;
3963 }
3964
3965 static struct pipe_sampler_view *
3966 si_create_sampler_view(struct pipe_context *ctx,
3967 struct pipe_resource *texture,
3968 const struct pipe_sampler_view *state)
3969 {
3970 return si_create_sampler_view_custom(ctx, texture, state,
3971 texture ? texture->width0 : 0,
3972 texture ? texture->height0 : 0, 0);
3973 }
3974
3975 static void si_sampler_view_destroy(struct pipe_context *ctx,
3976 struct pipe_sampler_view *state)
3977 {
3978 struct si_sampler_view *view = (struct si_sampler_view *)state;
3979
3980 pipe_resource_reference(&state->texture, NULL);
3981 FREE(view);
3982 }
3983
3984 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3985 {
3986 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3987 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3988 (linear_filter &&
3989 (wrap == PIPE_TEX_WRAP_CLAMP ||
3990 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3991 }
3992
3993 static uint32_t si_translate_border_color(struct si_context *sctx,
3994 const struct pipe_sampler_state *state,
3995 const union pipe_color_union *color,
3996 bool is_integer)
3997 {
3998 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3999 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4000
4001 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4002 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4003 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4004 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4005
4006 #define simple_border_types(elt) \
4007 do { \
4008 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4009 color->elt[2] == 0 && color->elt[3] == 0) \
4010 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4011 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4012 color->elt[2] == 0 && color->elt[3] == 1) \
4013 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4014 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4015 color->elt[2] == 1 && color->elt[3] == 1) \
4016 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4017 } while (false)
4018
4019 if (is_integer)
4020 simple_border_types(ui);
4021 else
4022 simple_border_types(f);
4023
4024 #undef simple_border_types
4025
4026 int i;
4027
4028 /* Check if the border has been uploaded already. */
4029 for (i = 0; i < sctx->border_color_count; i++)
4030 if (memcmp(&sctx->border_color_table[i], color,
4031 sizeof(*color)) == 0)
4032 break;
4033
4034 if (i >= SI_MAX_BORDER_COLORS) {
4035 /* Getting 4096 unique border colors is very unlikely. */
4036 fprintf(stderr, "radeonsi: The border color table is full. "
4037 "Any new border colors will be just black. "
4038 "Please file a bug.\n");
4039 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4040 }
4041
4042 if (i == sctx->border_color_count) {
4043 /* Upload a new border color. */
4044 memcpy(&sctx->border_color_table[i], color,
4045 sizeof(*color));
4046 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4047 color, sizeof(*color));
4048 sctx->border_color_count++;
4049 }
4050
4051 return S_008F3C_BORDER_COLOR_PTR(i) |
4052 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4053 }
4054
4055 static void *si_create_sampler_state(struct pipe_context *ctx,
4056 const struct pipe_sampler_state *state)
4057 {
4058 struct si_context *sctx = (struct si_context *)ctx;
4059 struct r600_common_screen *rscreen = sctx->b.screen;
4060 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4061 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
4062 : state->max_anisotropy;
4063 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
4064 union pipe_color_union clamped_border_color;
4065
4066 if (!rstate) {
4067 return NULL;
4068 }
4069
4070 #ifdef DEBUG
4071 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4072 #endif
4073 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4074 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4075 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4076 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4077 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4078 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4079 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4080 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4081 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4082 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
4083 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4084 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4085 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4086 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4087 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
4088 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
4089 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4090 S_008F38_MIP_POINT_PRECLAMP(0) |
4091 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
4092 S_008F38_FILTER_PREC_FIX(1) |
4093 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
4094 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4095
4096 /* Create sampler resource for integer textures. */
4097 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4098 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4099
4100 /* Create sampler resource for upgraded depth textures. */
4101 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4102
4103 for (unsigned i = 0; i < 4; ++i) {
4104 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4105 * when the border color is 1.0. */
4106 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4107 }
4108
4109 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4110 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4111 else
4112 rstate->upgraded_depth_val[3] =
4113 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4114 S_008F3C_UPGRADED_DEPTH(1);
4115
4116 return rstate;
4117 }
4118
4119 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4120 {
4121 struct si_context *sctx = (struct si_context *)ctx;
4122
4123 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
4124 return;
4125
4126 sctx->sample_mask.sample_mask = sample_mask;
4127 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
4128 }
4129
4130 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
4131 {
4132 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
4133 unsigned mask = sctx->sample_mask.sample_mask;
4134
4135 /* Needed for line and polygon smoothing as well as for the Polaris
4136 * small primitive filter. We expect the state tracker to take care of
4137 * this for us.
4138 */
4139 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4140 (mask & 1 && sctx->blitter->running));
4141
4142 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4143 radeon_emit(cs, mask | (mask << 16));
4144 radeon_emit(cs, mask | (mask << 16));
4145 }
4146
4147 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4148 {
4149 #ifdef DEBUG
4150 struct si_sampler_state *s = state;
4151
4152 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4153 s->magic = 0;
4154 #endif
4155 free(state);
4156 }
4157
4158 /*
4159 * Vertex elements & buffers
4160 */
4161
4162 static void *si_create_vertex_elements(struct pipe_context *ctx,
4163 unsigned count,
4164 const struct pipe_vertex_element *elements)
4165 {
4166 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4167 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4168 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4169 int i;
4170
4171 assert(count <= SI_MAX_ATTRIBS);
4172 if (!v)
4173 return NULL;
4174
4175 v->count = count;
4176 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4177
4178 for (i = 0; i < count; ++i) {
4179 const struct util_format_description *desc;
4180 const struct util_format_channel_description *channel;
4181 unsigned data_format, num_format;
4182 int first_non_void;
4183 unsigned vbo_index = elements[i].vertex_buffer_index;
4184 unsigned char swizzle[4];
4185
4186 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4187 FREE(v);
4188 return NULL;
4189 }
4190
4191 if (elements[i].instance_divisor) {
4192 v->uses_instance_divisors = true;
4193 v->instance_divisors[i] = elements[i].instance_divisor;
4194
4195 if (v->instance_divisors[i] == 1)
4196 v->instance_divisor_is_one |= 1u << i;
4197 else
4198 v->instance_divisor_is_fetched |= 1u << i;
4199 }
4200
4201 if (!used[vbo_index]) {
4202 v->first_vb_use_mask |= 1 << i;
4203 used[vbo_index] = true;
4204 }
4205
4206 desc = util_format_description(elements[i].src_format);
4207 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4208 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4209 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4210 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4211 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4212
4213 v->format_size[i] = desc->block.bits / 8;
4214 v->src_offset[i] = elements[i].src_offset;
4215 v->vertex_buffer_index[i] = vbo_index;
4216
4217 /* The hardware always treats the 2-bit alpha channel as
4218 * unsigned, so a shader workaround is needed. The affected
4219 * chips are VI and older except Stoney (GFX8.1).
4220 */
4221 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4222 sscreen->b.chip_class <= VI &&
4223 sscreen->b.family != CHIP_STONEY) {
4224 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4225 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4226 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4227 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4228 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4229 /* This isn't actually used in OpenGL. */
4230 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4231 }
4232 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4233 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4234 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4235 else
4236 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4237 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4238 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4239 if (channel->normalized) {
4240 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4241 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4242 else
4243 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4244 } else {
4245 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4246 }
4247 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4248 if (channel->normalized) {
4249 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4250 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4251 else
4252 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4253 } else {
4254 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4255 }
4256 }
4257 } else if (channel && channel->size == 64 &&
4258 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4259 switch (desc->nr_channels) {
4260 case 1:
4261 case 2:
4262 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4263 swizzle[0] = PIPE_SWIZZLE_X;
4264 swizzle[1] = PIPE_SWIZZLE_Y;
4265 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4266 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4267 break;
4268 case 3:
4269 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4270 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4271 swizzle[1] = PIPE_SWIZZLE_Y;
4272 swizzle[2] = PIPE_SWIZZLE_0;
4273 swizzle[3] = PIPE_SWIZZLE_0;
4274 break;
4275 case 4:
4276 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4277 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4278 swizzle[1] = PIPE_SWIZZLE_Y;
4279 swizzle[2] = PIPE_SWIZZLE_Z;
4280 swizzle[3] = PIPE_SWIZZLE_W;
4281 break;
4282 default:
4283 assert(0);
4284 }
4285 } else if (channel && desc->nr_channels == 3) {
4286 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4287
4288 if (channel->size == 8) {
4289 if (channel->pure_integer)
4290 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4291 else
4292 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4293 } else if (channel->size == 16) {
4294 if (channel->pure_integer)
4295 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4296 else
4297 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4298 }
4299 }
4300
4301 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4302 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4303 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4304 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4305 S_008F0C_NUM_FORMAT(num_format) |
4306 S_008F0C_DATA_FORMAT(data_format);
4307 }
4308 return v;
4309 }
4310
4311 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4312 {
4313 struct si_context *sctx = (struct si_context *)ctx;
4314 struct si_vertex_elements *old = sctx->vertex_elements;
4315 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4316
4317 sctx->vertex_elements = v;
4318 sctx->vertex_buffers_dirty = true;
4319
4320 if (v &&
4321 (!old ||
4322 old->count != v->count ||
4323 old->uses_instance_divisors != v->uses_instance_divisors ||
4324 v->uses_instance_divisors || /* we don't check which divisors changed */
4325 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4326 sctx->do_update_shaders = true;
4327
4328 if (v && v->instance_divisor_is_fetched) {
4329 struct pipe_constant_buffer cb;
4330
4331 cb.buffer = NULL;
4332 cb.user_buffer = v->instance_divisors;
4333 cb.buffer_offset = 0;
4334 cb.buffer_size = sizeof(uint32_t) * v->count;
4335 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4336 }
4337 }
4338
4339 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4340 {
4341 struct si_context *sctx = (struct si_context *)ctx;
4342
4343 if (sctx->vertex_elements == state)
4344 sctx->vertex_elements = NULL;
4345 FREE(state);
4346 }
4347
4348 static void si_set_vertex_buffers(struct pipe_context *ctx,
4349 unsigned start_slot, unsigned count,
4350 const struct pipe_vertex_buffer *buffers)
4351 {
4352 struct si_context *sctx = (struct si_context *)ctx;
4353 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4354 int i;
4355
4356 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4357
4358 if (buffers) {
4359 for (i = 0; i < count; i++) {
4360 const struct pipe_vertex_buffer *src = buffers + i;
4361 struct pipe_vertex_buffer *dsti = dst + i;
4362 struct pipe_resource *buf = src->buffer.resource;
4363
4364 pipe_resource_reference(&dsti->buffer.resource, buf);
4365 dsti->buffer_offset = src->buffer_offset;
4366 dsti->stride = src->stride;
4367 r600_context_add_resource_size(ctx, buf);
4368 if (buf)
4369 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4370 }
4371 } else {
4372 for (i = 0; i < count; i++) {
4373 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4374 }
4375 }
4376 sctx->vertex_buffers_dirty = true;
4377 }
4378
4379 /*
4380 * Misc
4381 */
4382
4383 static void si_set_tess_state(struct pipe_context *ctx,
4384 const float default_outer_level[4],
4385 const float default_inner_level[2])
4386 {
4387 struct si_context *sctx = (struct si_context *)ctx;
4388 struct pipe_constant_buffer cb;
4389 float array[8];
4390
4391 memcpy(array, default_outer_level, sizeof(float) * 4);
4392 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4393
4394 cb.buffer = NULL;
4395 cb.user_buffer = NULL;
4396 cb.buffer_size = sizeof(array);
4397
4398 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4399 (void*)array, sizeof(array),
4400 &cb.buffer_offset);
4401
4402 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4403 pipe_resource_reference(&cb.buffer, NULL);
4404 }
4405
4406 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4407 {
4408 struct si_context *sctx = (struct si_context *)ctx;
4409
4410 si_update_fb_dirtiness_after_rendering(sctx);
4411
4412 /* Multisample surfaces are flushed in si_decompress_textures. */
4413 if (sctx->framebuffer.nr_samples <= 1 &&
4414 sctx->framebuffer.state.nr_cbufs)
4415 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4416 sctx->framebuffer.CB_has_shader_readable_metadata);
4417 }
4418
4419 /* This only ensures coherency for shader image/buffer stores. */
4420 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4421 {
4422 struct si_context *sctx = (struct si_context *)ctx;
4423
4424 /* Subsequent commands must wait for all shader invocations to
4425 * complete. */
4426 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4427 SI_CONTEXT_CS_PARTIAL_FLUSH;
4428
4429 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4430 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
4431 SI_CONTEXT_INV_VMEM_L1;
4432
4433 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4434 PIPE_BARRIER_SHADER_BUFFER |
4435 PIPE_BARRIER_TEXTURE |
4436 PIPE_BARRIER_IMAGE |
4437 PIPE_BARRIER_STREAMOUT_BUFFER |
4438 PIPE_BARRIER_GLOBAL_BUFFER)) {
4439 /* As far as I can tell, L1 contents are written back to L2
4440 * automatically at end of shader, but the contents of other
4441 * L1 caches might still be stale. */
4442 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
4443 }
4444
4445 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4446 /* Indices are read through TC L2 since VI.
4447 * L1 isn't used.
4448 */
4449 if (sctx->screen->b.chip_class <= CIK)
4450 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4451 }
4452
4453 /* MSAA color, any depth and any stencil are flushed in
4454 * si_decompress_textures when needed.
4455 */
4456 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4457 sctx->framebuffer.nr_samples <= 1 &&
4458 sctx->framebuffer.state.nr_cbufs) {
4459 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4460
4461 if (sctx->b.chip_class <= VI)
4462 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4463 }
4464
4465 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4466 if (sctx->screen->b.chip_class <= VI &&
4467 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4468 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4469 }
4470
4471 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4472 {
4473 struct pipe_blend_state blend;
4474
4475 memset(&blend, 0, sizeof(blend));
4476 blend.independent_blend_enable = true;
4477 blend.rt[0].colormask = 0xf;
4478 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
4479 }
4480
4481 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
4482 bool include_draw_vbo)
4483 {
4484 si_need_cs_space((struct si_context*)ctx);
4485 }
4486
4487 static void si_init_config(struct si_context *sctx);
4488
4489 void si_init_state_functions(struct si_context *sctx)
4490 {
4491 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4492 si_init_external_atom(sctx, &sctx->streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4493 si_init_external_atom(sctx, &sctx->streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4494 si_init_external_atom(sctx, &sctx->scissors.atom, &sctx->atoms.s.scissors);
4495 si_init_external_atom(sctx, &sctx->viewports.atom, &sctx->atoms.s.viewports);
4496
4497 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4498 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4499 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4500 si_init_atom(sctx, &sctx->dpbb_state, &sctx->atoms.s.dpbb_state, si_emit_dpbb_state);
4501 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4502 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4503 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4504 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4505 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4506 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4507 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4508
4509 sctx->b.b.create_blend_state = si_create_blend_state;
4510 sctx->b.b.bind_blend_state = si_bind_blend_state;
4511 sctx->b.b.delete_blend_state = si_delete_blend_state;
4512 sctx->b.b.set_blend_color = si_set_blend_color;
4513
4514 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4515 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4516 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4517
4518 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4519 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4520 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4521
4522 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4523 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4524 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4525 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4526 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4527
4528 sctx->b.b.set_clip_state = si_set_clip_state;
4529 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4530
4531 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4532
4533 sctx->b.b.create_sampler_state = si_create_sampler_state;
4534 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4535
4536 sctx->b.b.create_sampler_view = si_create_sampler_view;
4537 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4538
4539 sctx->b.b.set_sample_mask = si_set_sample_mask;
4540
4541 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4542 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4543 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4544 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4545
4546 sctx->b.b.texture_barrier = si_texture_barrier;
4547 sctx->b.b.memory_barrier = si_memory_barrier;
4548 sctx->b.b.set_min_samples = si_set_min_samples;
4549 sctx->b.b.set_tess_state = si_set_tess_state;
4550
4551 sctx->b.b.set_active_query_state = si_set_active_query_state;
4552 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4553 sctx->b.save_qbo_state = si_save_qbo_state;
4554 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4555
4556 sctx->b.b.draw_vbo = si_draw_vbo;
4557
4558 si_init_config(sctx);
4559 }
4560
4561 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4562 {
4563 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4564 }
4565
4566 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4567 struct r600_texture *rtex,
4568 struct radeon_bo_metadata *md)
4569 {
4570 struct si_screen *sscreen = (struct si_screen*)rscreen;
4571 struct pipe_resource *res = &rtex->resource.b.b;
4572 static const unsigned char swizzle[] = {
4573 PIPE_SWIZZLE_X,
4574 PIPE_SWIZZLE_Y,
4575 PIPE_SWIZZLE_Z,
4576 PIPE_SWIZZLE_W
4577 };
4578 uint32_t desc[8], i;
4579 bool is_array = util_resource_is_array_texture(res);
4580
4581 /* DRM 2.x.x doesn't support this. */
4582 if (rscreen->info.drm_major != 3)
4583 return;
4584
4585 assert(rtex->dcc_separate_buffer == NULL);
4586 assert(rtex->fmask.size == 0);
4587
4588 /* Metadata image format format version 1:
4589 * [0] = 1 (metadata format identifier)
4590 * [1] = (VENDOR_ID << 16) | PCI_ID
4591 * [2:9] = image descriptor for the whole resource
4592 * [2] is always 0, because the base address is cleared
4593 * [9] is the DCC offset bits [39:8] from the beginning of
4594 * the buffer
4595 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4596 */
4597
4598 md->metadata[0] = 1; /* metadata image format version 1 */
4599
4600 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4601 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4602
4603 si_make_texture_descriptor(sscreen, rtex, true,
4604 res->target, res->format,
4605 swizzle, 0, res->last_level, 0,
4606 is_array ? res->array_size - 1 : 0,
4607 res->width0, res->height0, res->depth0,
4608 desc, NULL);
4609
4610 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4611 0, 0, rtex->surface.blk_w, false, desc);
4612
4613 /* Clear the base address and set the relative DCC offset. */
4614 desc[0] = 0;
4615 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4616 desc[7] = rtex->dcc_offset >> 8;
4617
4618 /* Dwords [2:9] contain the image descriptor. */
4619 memcpy(&md->metadata[2], desc, sizeof(desc));
4620 md->size_metadata = 10 * 4;
4621
4622 /* Dwords [10:..] contain the mipmap level offsets. */
4623 if (rscreen->chip_class <= VI) {
4624 for (i = 0; i <= res->last_level; i++)
4625 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4626
4627 md->size_metadata += (1 + res->last_level) * 4;
4628 }
4629 }
4630
4631 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4632 struct r600_texture *rtex,
4633 struct radeon_bo_metadata *md)
4634 {
4635 uint32_t *desc = &md->metadata[2];
4636
4637 if (rscreen->chip_class < VI)
4638 return;
4639
4640 /* Return if DCC is enabled. The texture should be set up with it
4641 * already.
4642 */
4643 if (md->size_metadata >= 11 * 4 &&
4644 md->metadata[0] != 0 &&
4645 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4646 G_008F28_COMPRESSION_EN(desc[6])) {
4647 rtex->dcc_offset = (uint64_t)desc[7] << 8;
4648 return;
4649 }
4650
4651 /* Disable DCC. These are always set by texture_from_handle and must
4652 * be cleared here.
4653 */
4654 rtex->dcc_offset = 0;
4655 }
4656
4657 void si_init_screen_state_functions(struct si_screen *sscreen)
4658 {
4659 sscreen->b.b.is_format_supported = si_is_format_supported;
4660 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4661 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4662 }
4663
4664 static void si_set_grbm_gfx_index(struct si_context *sctx,
4665 struct si_pm4_state *pm4, unsigned value)
4666 {
4667 unsigned reg = sctx->b.chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4668 R_00802C_GRBM_GFX_INDEX;
4669 si_pm4_set_reg(pm4, reg, value);
4670 }
4671
4672 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4673 struct si_pm4_state *pm4, unsigned se)
4674 {
4675 assert(se == ~0 || se < sctx->screen->b.info.max_se);
4676 si_set_grbm_gfx_index(sctx, pm4,
4677 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4678 S_030800_SE_INDEX(se)) |
4679 S_030800_SH_BROADCAST_WRITES(1) |
4680 S_030800_INSTANCE_BROADCAST_WRITES(1));
4681 }
4682
4683 static void
4684 si_write_harvested_raster_configs(struct si_context *sctx,
4685 struct si_pm4_state *pm4,
4686 unsigned raster_config,
4687 unsigned raster_config_1)
4688 {
4689 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4690 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4691 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4692 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4693 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4694 unsigned rb_per_se = num_rb / num_se;
4695 unsigned se_mask[4];
4696 unsigned se;
4697
4698 se_mask[0] = ((1 << rb_per_se) - 1);
4699 se_mask[1] = (se_mask[0] << rb_per_se);
4700 se_mask[2] = (se_mask[1] << rb_per_se);
4701 se_mask[3] = (se_mask[2] << rb_per_se);
4702
4703 se_mask[0] &= rb_mask;
4704 se_mask[1] &= rb_mask;
4705 se_mask[2] &= rb_mask;
4706 se_mask[3] &= rb_mask;
4707
4708 assert(num_se == 1 || num_se == 2 || num_se == 4);
4709 assert(sh_per_se == 1 || sh_per_se == 2);
4710 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4711
4712 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4713 * fields are for, so I'm leaving them as their default
4714 * values. */
4715
4716 for (se = 0; se < num_se; se++) {
4717 unsigned raster_config_se = raster_config;
4718 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4719 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4720 int idx = (se / 2) * 2;
4721
4722 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4723 raster_config_se &= C_028350_SE_MAP;
4724
4725 if (!se_mask[idx]) {
4726 raster_config_se |=
4727 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4728 } else {
4729 raster_config_se |=
4730 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4731 }
4732 }
4733
4734 pkr0_mask &= rb_mask;
4735 pkr1_mask &= rb_mask;
4736 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4737 raster_config_se &= C_028350_PKR_MAP;
4738
4739 if (!pkr0_mask) {
4740 raster_config_se |=
4741 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4742 } else {
4743 raster_config_se |=
4744 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4745 }
4746 }
4747
4748 if (rb_per_se >= 2) {
4749 unsigned rb0_mask = 1 << (se * rb_per_se);
4750 unsigned rb1_mask = rb0_mask << 1;
4751
4752 rb0_mask &= rb_mask;
4753 rb1_mask &= rb_mask;
4754 if (!rb0_mask || !rb1_mask) {
4755 raster_config_se &= C_028350_RB_MAP_PKR0;
4756
4757 if (!rb0_mask) {
4758 raster_config_se |=
4759 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4760 } else {
4761 raster_config_se |=
4762 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4763 }
4764 }
4765
4766 if (rb_per_se > 2) {
4767 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4768 rb1_mask = rb0_mask << 1;
4769 rb0_mask &= rb_mask;
4770 rb1_mask &= rb_mask;
4771 if (!rb0_mask || !rb1_mask) {
4772 raster_config_se &= C_028350_RB_MAP_PKR1;
4773
4774 if (!rb0_mask) {
4775 raster_config_se |=
4776 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4777 } else {
4778 raster_config_se |=
4779 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4780 }
4781 }
4782 }
4783 }
4784
4785 si_set_grbm_gfx_index_se(sctx, pm4, se);
4786 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4787 }
4788 si_set_grbm_gfx_index(sctx, pm4, ~0);
4789
4790 if (sctx->b.chip_class >= CIK) {
4791 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4792 (!se_mask[2] && !se_mask[3]))) {
4793 raster_config_1 &= C_028354_SE_PAIR_MAP;
4794
4795 if (!se_mask[0] && !se_mask[1]) {
4796 raster_config_1 |=
4797 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4798 } else {
4799 raster_config_1 |=
4800 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4801 }
4802 }
4803
4804 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4805 }
4806 }
4807
4808 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4809 {
4810 struct si_screen *sscreen = sctx->screen;
4811 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4812 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4813 unsigned raster_config, raster_config_1;
4814
4815 switch (sctx->b.family) {
4816 case CHIP_TAHITI:
4817 case CHIP_PITCAIRN:
4818 raster_config = 0x2a00126a;
4819 raster_config_1 = 0x00000000;
4820 break;
4821 case CHIP_VERDE:
4822 raster_config = 0x0000124a;
4823 raster_config_1 = 0x00000000;
4824 break;
4825 case CHIP_OLAND:
4826 raster_config = 0x00000082;
4827 raster_config_1 = 0x00000000;
4828 break;
4829 case CHIP_HAINAN:
4830 raster_config = 0x00000000;
4831 raster_config_1 = 0x00000000;
4832 break;
4833 case CHIP_BONAIRE:
4834 raster_config = 0x16000012;
4835 raster_config_1 = 0x00000000;
4836 break;
4837 case CHIP_HAWAII:
4838 raster_config = 0x3a00161a;
4839 raster_config_1 = 0x0000002e;
4840 break;
4841 case CHIP_FIJI:
4842 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4843 /* old kernels with old tiling config */
4844 raster_config = 0x16000012;
4845 raster_config_1 = 0x0000002a;
4846 } else {
4847 raster_config = 0x3a00161a;
4848 raster_config_1 = 0x0000002e;
4849 }
4850 break;
4851 case CHIP_POLARIS10:
4852 raster_config = 0x16000012;
4853 raster_config_1 = 0x0000002a;
4854 break;
4855 case CHIP_POLARIS11:
4856 case CHIP_POLARIS12:
4857 raster_config = 0x16000012;
4858 raster_config_1 = 0x00000000;
4859 break;
4860 case CHIP_TONGA:
4861 raster_config = 0x16000012;
4862 raster_config_1 = 0x0000002a;
4863 break;
4864 case CHIP_ICELAND:
4865 if (num_rb == 1)
4866 raster_config = 0x00000000;
4867 else
4868 raster_config = 0x00000002;
4869 raster_config_1 = 0x00000000;
4870 break;
4871 case CHIP_CARRIZO:
4872 raster_config = 0x00000002;
4873 raster_config_1 = 0x00000000;
4874 break;
4875 case CHIP_KAVERI:
4876 /* KV should be 0x00000002, but that causes problems with radeon */
4877 raster_config = 0x00000000; /* 0x00000002 */
4878 raster_config_1 = 0x00000000;
4879 break;
4880 case CHIP_KABINI:
4881 case CHIP_MULLINS:
4882 case CHIP_STONEY:
4883 raster_config = 0x00000000;
4884 raster_config_1 = 0x00000000;
4885 break;
4886 default:
4887 fprintf(stderr,
4888 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4889 raster_config = 0x00000000;
4890 raster_config_1 = 0x00000000;
4891 }
4892
4893 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4894 /* Always use the default config when all backends are enabled
4895 * (or when we failed to determine the enabled backends).
4896 */
4897 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4898 raster_config);
4899 if (sctx->b.chip_class >= CIK)
4900 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4901 raster_config_1);
4902 } else {
4903 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4904 }
4905 }
4906
4907 static void si_init_config(struct si_context *sctx)
4908 {
4909 struct si_screen *sscreen = sctx->screen;
4910 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4911 bool has_clear_state = sscreen->has_clear_state;
4912 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4913
4914 /* Only SI can disable CLEAR_STATE for now. */
4915 assert(has_clear_state || sscreen->b.chip_class == SI);
4916
4917 if (!pm4)
4918 return;
4919
4920 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4921 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4922 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4923 si_pm4_cmd_end(pm4, false);
4924
4925 if (has_clear_state) {
4926 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4927 si_pm4_cmd_add(pm4, 0);
4928 si_pm4_cmd_end(pm4, false);
4929 }
4930
4931 if (sctx->b.chip_class <= VI)
4932 si_set_raster_config(sctx, pm4);
4933
4934 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4935 if (!has_clear_state)
4936 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4937
4938 /* FIXME calculate these values somehow ??? */
4939 if (sctx->b.chip_class <= VI) {
4940 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4941 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4942 }
4943
4944 if (!has_clear_state) {
4945 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4946 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4947 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4948 }
4949
4950 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4951 if (!has_clear_state)
4952 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4953 if (sctx->b.chip_class < CIK)
4954 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4955 S_008A14_CLIP_VTX_REORDER_ENA(1));
4956
4957 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4958 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4959
4960 if (!has_clear_state)
4961 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4962
4963 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4964 * I don't know why. Deduced by trial and error.
4965 */
4966 if (sctx->b.chip_class <= CIK) {
4967 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4968 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4969 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4970 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4971 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4972 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4973 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4974 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4975 }
4976
4977 if (!has_clear_state) {
4978 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4979 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4980 S_028230_ER_TRI(0xA) |
4981 S_028230_ER_POINT(0xA) |
4982 S_028230_ER_RECT(0xA) |
4983 /* Required by DX10_DIAMOND_TEST_ENA: */
4984 S_028230_ER_LINE_LR(0x1A) |
4985 S_028230_ER_LINE_RL(0x26) |
4986 S_028230_ER_LINE_TB(0xA) |
4987 S_028230_ER_LINE_BT(0xA));
4988 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4989 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4990 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4991 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4992 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4993 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4994 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4995 }
4996
4997 if (sctx->b.chip_class >= GFX9) {
4998 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4999 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
5000 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
5001 } else {
5002 /* These registers, when written, also overwrite the CLEAR_STATE
5003 * context, so we can't rely on CLEAR_STATE setting them.
5004 * It would be an issue if there was another UMD changing them.
5005 */
5006 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
5007 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
5008 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
5009 }
5010
5011 if (sctx->b.chip_class >= CIK) {
5012 if (sctx->b.chip_class >= GFX9) {
5013 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5014 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
5015 } else {
5016 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
5017 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
5018 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
5019 S_00B41C_WAVE_LIMIT(0x3F));
5020 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
5021 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5022
5023 /* If this is 0, Bonaire can hang even if GS isn't being used.
5024 * Other chips are unaffected. These are suboptimal values,
5025 * but we don't use on-chip GS.
5026 */
5027 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
5028 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5029 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5030 }
5031 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
5032 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5033
5034 /* Compute LATE_ALLOC_VS.LIMIT. */
5035 unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
5036 (sscreen->b.info.max_se *
5037 sscreen->b.info.max_sh_per_se);
5038 unsigned late_alloc_limit; /* The limit is per SH. */
5039
5040 if (sctx->b.family == CHIP_KABINI) {
5041 late_alloc_limit = 0; /* Potential hang on Kabini. */
5042 } else if (num_cu_per_sh <= 4) {
5043 /* Too few available compute units per SH. Disallowing
5044 * VS to run on one CU could hurt us more than late VS
5045 * allocation would help.
5046 *
5047 * 2 is the highest safe number that allows us to keep
5048 * all CUs enabled.
5049 */
5050 late_alloc_limit = 2;
5051 } else {
5052 /* This is a good initial value, allowing 1 late_alloc
5053 * wave per SIMD on num_cu - 2.
5054 */
5055 late_alloc_limit = (num_cu_per_sh - 2) * 4;
5056
5057 /* The limit is 0-based, so 0 means 1. */
5058 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
5059 late_alloc_limit -= 1;
5060 }
5061
5062 /* VS can't execute on one CU if the limit is > 2. */
5063 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
5064 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
5065 S_00B118_WAVE_LIMIT(0x3F));
5066 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
5067 S_00B11C_LIMIT(late_alloc_limit));
5068 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
5069 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5070 }
5071
5072 if (sctx->b.chip_class >= VI) {
5073 unsigned vgt_tess_distribution;
5074
5075 vgt_tess_distribution =
5076 S_028B50_ACCUM_ISOLINE(32) |
5077 S_028B50_ACCUM_TRI(11) |
5078 S_028B50_ACCUM_QUAD(11) |
5079 S_028B50_DONUT_SPLIT(16);
5080
5081 /* Testing with Unigine Heaven extreme tesselation yielded best results
5082 * with TRAP_SPLIT = 3.
5083 */
5084 if (sctx->b.family == CHIP_FIJI ||
5085 sctx->b.family >= CHIP_POLARIS10)
5086 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
5087
5088 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5089 } else if (!has_clear_state) {
5090 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5091 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5092 }
5093
5094 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5095 if (sctx->b.chip_class >= CIK)
5096 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
5097 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5098 RADEON_PRIO_BORDER_COLORS);
5099
5100 if (sctx->b.chip_class >= GFX9) {
5101 unsigned num_se = sscreen->b.info.max_se;
5102 unsigned pc_lines = 0;
5103
5104 switch (sctx->b.family) {
5105 case CHIP_VEGA10:
5106 pc_lines = 4096;
5107 break;
5108 case CHIP_RAVEN:
5109 pc_lines = 1024;
5110 break;
5111 default:
5112 assert(0);
5113 }
5114
5115 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5116 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5117 S_028C48_MAX_PRIM_PER_BATCH(1023));
5118 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5119 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5120 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5121 }
5122
5123 si_pm4_upload_indirect_buffer(sctx, pm4);
5124 sctx->init_config = pm4;
5125 }