2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
36 static unsigned si_map_swizzle(unsigned swizzle
)
40 return V_008F0C_SQ_SEL_Y
;
42 return V_008F0C_SQ_SEL_Z
;
44 return V_008F0C_SQ_SEL_W
;
46 return V_008F0C_SQ_SEL_0
;
48 return V_008F0C_SQ_SEL_1
;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X
;
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x
)
58 x
>= 4096 ? 0xffff : x
* 16;
62 * Inferred framebuffer and blender state.
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
67 static void si_emit_cb_render_state(struct si_context
*sctx
)
69 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
70 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
77 cb_target_mask
&= blend
->cb_target_mask
;
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
85 if (blend
&& blend
->dual_src_blend
&&
86 sctx
->ps_shader
.cso
&&
87 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
90 radeon_opt_set_context_reg(sctx
, R_028238_CB_TARGET_MASK
,
91 SI_TRACKED_CB_TARGET_MASK
, cb_target_mask
);
93 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
94 * I think we don't have to do anything between IBs.
96 if (sctx
->screen
->dfsm_allowed
&&
97 sctx
->last_cb_target_mask
!= cb_target_mask
) {
98 sctx
->last_cb_target_mask
= cb_target_mask
;
100 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
101 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
104 if (sctx
->chip_class
>= VI
) {
105 /* DCC MSAA workaround for blending.
106 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
107 * COMBINER_DISABLE, but that would be more complicated.
109 bool oc_disable
= (sctx
->chip_class
== VI
||
110 sctx
->chip_class
== GFX9
) &&
112 blend
->blend_enable_4bit
& cb_target_mask
&&
113 sctx
->framebuffer
.nr_samples
>= 2;
115 radeon_opt_set_context_reg(
116 sctx
, R_028424_CB_DCC_CONTROL
,
117 SI_TRACKED_CB_DCC_CONTROL
,
118 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
119 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
120 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable
));
123 /* RB+ register settings. */
124 if (sctx
->screen
->rbplus_allowed
) {
125 unsigned spi_shader_col_format
=
126 sctx
->ps_shader
.cso
?
127 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
128 unsigned sx_ps_downconvert
= 0;
129 unsigned sx_blend_opt_epsilon
= 0;
130 unsigned sx_blend_opt_control
= 0;
132 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
133 struct si_surface
*surf
=
134 (struct si_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
135 unsigned format
, swap
, spi_format
, colormask
;
136 bool has_alpha
, has_rgb
;
141 format
= G_028C70_FORMAT(surf
->cb_color_info
);
142 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
143 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
144 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
146 /* Set if RGB and A are present. */
147 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
149 if (format
== V_028C70_COLOR_8
||
150 format
== V_028C70_COLOR_16
||
151 format
== V_028C70_COLOR_32
)
152 has_rgb
= !has_alpha
;
156 /* Check the colormask and export format. */
157 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
159 if (!(colormask
& PIPE_MASK_A
))
162 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
167 /* Disable value checking for disabled channels. */
169 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
171 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
173 /* Enable down-conversion for 32bpp and smaller formats. */
175 case V_028C70_COLOR_8
:
176 case V_028C70_COLOR_8_8
:
177 case V_028C70_COLOR_8_8_8_8
:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
180 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
181 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
182 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
183 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
187 case V_028C70_COLOR_5_6_5
:
188 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
189 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
190 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
194 case V_028C70_COLOR_1_5_5_5
:
195 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
196 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
197 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
201 case V_028C70_COLOR_4_4_4_4
:
202 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
203 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
204 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
208 case V_028C70_COLOR_32
:
209 if (swap
== V_028C70_SWAP_STD
&&
210 spi_format
== V_028714_SPI_SHADER_32_R
)
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
212 else if (swap
== V_028C70_SWAP_ALT_REV
&&
213 spi_format
== V_028714_SPI_SHADER_32_AR
)
214 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
217 case V_028C70_COLOR_16
:
218 case V_028C70_COLOR_16_16
:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
221 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
222 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
223 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
224 if (swap
== V_028C70_SWAP_STD
||
225 swap
== V_028C70_SWAP_STD_REV
)
226 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
228 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
232 case V_028C70_COLOR_10_11_11
:
233 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
235 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
239 case V_028C70_COLOR_2_10_10_10
:
240 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
241 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
242 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
248 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
249 radeon_opt_set_context_reg3(sctx
, R_028754_SX_PS_DOWNCONVERT
,
250 SI_TRACKED_SX_PS_DOWNCONVERT
,
251 sx_ps_downconvert
, sx_blend_opt_epsilon
,
252 sx_blend_opt_control
);
260 static uint32_t si_translate_blend_function(int blend_func
)
262 switch (blend_func
) {
264 return V_028780_COMB_DST_PLUS_SRC
;
265 case PIPE_BLEND_SUBTRACT
:
266 return V_028780_COMB_SRC_MINUS_DST
;
267 case PIPE_BLEND_REVERSE_SUBTRACT
:
268 return V_028780_COMB_DST_MINUS_SRC
;
270 return V_028780_COMB_MIN_DST_SRC
;
272 return V_028780_COMB_MAX_DST_SRC
;
274 PRINT_ERR("Unknown blend function %d\n", blend_func
);
281 static uint32_t si_translate_blend_factor(int blend_fact
)
283 switch (blend_fact
) {
284 case PIPE_BLENDFACTOR_ONE
:
285 return V_028780_BLEND_ONE
;
286 case PIPE_BLENDFACTOR_SRC_COLOR
:
287 return V_028780_BLEND_SRC_COLOR
;
288 case PIPE_BLENDFACTOR_SRC_ALPHA
:
289 return V_028780_BLEND_SRC_ALPHA
;
290 case PIPE_BLENDFACTOR_DST_ALPHA
:
291 return V_028780_BLEND_DST_ALPHA
;
292 case PIPE_BLENDFACTOR_DST_COLOR
:
293 return V_028780_BLEND_DST_COLOR
;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
296 case PIPE_BLENDFACTOR_CONST_COLOR
:
297 return V_028780_BLEND_CONSTANT_COLOR
;
298 case PIPE_BLENDFACTOR_CONST_ALPHA
:
299 return V_028780_BLEND_CONSTANT_ALPHA
;
300 case PIPE_BLENDFACTOR_ZERO
:
301 return V_028780_BLEND_ZERO
;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
314 case PIPE_BLENDFACTOR_SRC1_COLOR
:
315 return V_028780_BLEND_SRC1_COLOR
;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
317 return V_028780_BLEND_SRC1_ALPHA
;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
319 return V_028780_BLEND_INV_SRC1_COLOR
;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
321 return V_028780_BLEND_INV_SRC1_ALPHA
;
323 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact
);
330 static uint32_t si_translate_blend_opt_function(int blend_func
)
332 switch (blend_func
) {
334 return V_028760_OPT_COMB_ADD
;
335 case PIPE_BLEND_SUBTRACT
:
336 return V_028760_OPT_COMB_SUBTRACT
;
337 case PIPE_BLEND_REVERSE_SUBTRACT
:
338 return V_028760_OPT_COMB_REVSUBTRACT
;
340 return V_028760_OPT_COMB_MIN
;
342 return V_028760_OPT_COMB_MAX
;
344 return V_028760_OPT_COMB_BLEND_DISABLED
;
348 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
350 switch (blend_fact
) {
351 case PIPE_BLENDFACTOR_ZERO
:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
353 case PIPE_BLENDFACTOR_ONE
:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
355 case PIPE_BLENDFACTOR_SRC_COLOR
:
356 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
359 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
361 case PIPE_BLENDFACTOR_SRC_ALPHA
:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
373 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
374 struct si_state_blend
*blend
,
375 enum pipe_blend_func func
,
376 enum pipe_blendfactor src
,
377 enum pipe_blendfactor dst
,
380 /* Src factor is allowed when it does not depend on Dst */
381 static const uint32_t src_allowed
=
382 (1u << PIPE_BLENDFACTOR_ONE
) |
383 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
384 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
386 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
387 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
389 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
390 (1u << PIPE_BLENDFACTOR_ZERO
) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
393 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
398 if (dst
== PIPE_BLENDFACTOR_ONE
&&
399 (src_allowed
& (1u << src
))) {
400 /* Addition is commutative, but floating point addition isn't
401 * associative: subtle changes can be introduced via different
404 * Out-of-order is also non-deterministic, which means that
405 * this breaks OpenGL invariance requirements. So only enable
406 * out-of-order additive blending if explicitly allowed by a
409 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
410 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
411 blend
->commutative_4bit
|= chanmask
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
425 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== PIPE_BLEND_SUBTRACT
)
430 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
431 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
432 *func
= PIPE_BLEND_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
439 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
440 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
441 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
442 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
445 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
446 const struct pipe_blend_state
*state
,
449 struct si_context
*sctx
= (struct si_context
*)ctx
;
450 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
451 struct si_pm4_state
*pm4
= &blend
->pm4
;
452 uint32_t sx_mrt_blend_opt
[8] = {0};
453 uint32_t color_control
= 0;
458 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
459 blend
->alpha_to_one
= state
->alpha_to_one
;
460 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
461 blend
->logicop_enable
= state
->logicop_enable
;
463 if (state
->logicop_enable
) {
464 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
466 color_control
|= S_028808_ROP3(0xcc);
469 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
472 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
476 if (state
->alpha_to_coverage
)
477 blend
->need_src_alpha_4bit
|= 0xf;
479 blend
->cb_target_mask
= 0;
480 blend
->cb_target_enabled_4bit
= 0;
482 for (int i
= 0; i
< 8; i
++) {
483 /* state->rt entries > 0 only written if independent blending */
484 const int j
= state
->independent_blend_enable
? i
: 0;
486 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
487 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
488 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
489 unsigned eqA
= state
->rt
[j
].alpha_func
;
490 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
491 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
493 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
494 unsigned blend_cntl
= 0;
496 sx_mrt_blend_opt
[i
] =
497 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
498 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
500 /* Only set dual source blending for MRT0 to avoid a hang. */
501 if (i
>= 1 && blend
->dual_src_blend
) {
502 /* Vulkan does this for dual source blending. */
504 blend_cntl
|= S_028780_ENABLE(1);
506 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
510 /* Only addition and subtraction equations are supported with
511 * dual source blending.
513 if (blend
->dual_src_blend
&&
514 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
515 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
521 /* cb_render_state will disable unused ones */
522 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
523 if (state
->rt
[j
].colormask
)
524 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
526 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
527 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
531 si_blend_check_commutativity(sctx
->screen
, blend
,
532 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
533 si_blend_check_commutativity(sctx
->screen
, blend
,
534 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
536 /* Blending optimizations for RB+.
537 * These transformations don't change the behavior.
539 * First, get rid of DST in the blend factors:
540 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
542 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
543 PIPE_BLENDFACTOR_DST_COLOR
,
544 PIPE_BLENDFACTOR_SRC_COLOR
);
545 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
546 PIPE_BLENDFACTOR_DST_COLOR
,
547 PIPE_BLENDFACTOR_SRC_COLOR
);
548 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
549 PIPE_BLENDFACTOR_DST_ALPHA
,
550 PIPE_BLENDFACTOR_SRC_ALPHA
);
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
554 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
555 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
556 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
558 /* Handle interdependencies. */
559 if (si_blend_factor_uses_dst(srcRGB
))
560 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
561 if (si_blend_factor_uses_dst(srcA
))
562 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
564 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
565 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
566 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
567 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
568 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
570 /* Set the final value. */
571 sx_mrt_blend_opt
[i
] =
572 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
573 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
574 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
575 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
576 S_028760_ALPHA_DST_OPT(dstA_opt
) |
577 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
579 /* Set blend state. */
580 blend_cntl
|= S_028780_ENABLE(1);
581 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
582 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
583 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
585 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
586 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
587 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
588 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
589 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
591 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
593 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
595 /* This is only important for formats without alpha. */
596 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
597 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
598 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
599 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
600 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
601 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
602 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
605 if (blend
->cb_target_mask
) {
606 color_control
|= S_028808_MODE(mode
);
608 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
611 if (sctx
->screen
->rbplus_allowed
) {
612 /* Disable RB+ blend optimizations for dual source blending.
615 if (blend
->dual_src_blend
) {
616 for (int i
= 0; i
< 8; i
++) {
617 sx_mrt_blend_opt
[i
] =
618 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
623 for (int i
= 0; i
< 8; i
++)
624 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
625 sx_mrt_blend_opt
[i
]);
627 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
628 if (blend
->dual_src_blend
|| state
->logicop_enable
||
629 mode
== V_028808_CB_RESOLVE
)
630 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
633 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
637 static void *si_create_blend_state(struct pipe_context
*ctx
,
638 const struct pipe_blend_state
*state
)
640 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
643 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
645 struct si_context
*sctx
= (struct si_context
*)ctx
;
646 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
647 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
652 si_pm4_bind_state(sctx
, blend
, state
);
655 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
656 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
657 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
&&
658 sctx
->framebuffer
.nr_samples
>= 2 &&
659 sctx
->screen
->dcc_msaa_allowed
))
660 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
663 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
664 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
665 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
666 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
667 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
668 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
669 sctx
->do_update_shaders
= true;
671 if (sctx
->screen
->dpbb_allowed
&&
673 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
674 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
675 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
676 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
678 if (sctx
->screen
->has_out_of_order_rast
&&
680 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
681 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
682 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
683 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
684 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
687 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
689 struct si_context
*sctx
= (struct si_context
*)ctx
;
690 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
693 static void si_set_blend_color(struct pipe_context
*ctx
,
694 const struct pipe_blend_color
*state
)
696 struct si_context
*sctx
= (struct si_context
*)ctx
;
697 static const struct pipe_blend_color zeros
;
699 sctx
->blend_color
.state
= *state
;
700 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
701 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.blend_color
);
704 static void si_emit_blend_color(struct si_context
*sctx
)
706 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
708 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
709 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
716 static void si_set_clip_state(struct pipe_context
*ctx
,
717 const struct pipe_clip_state
*state
)
719 struct si_context
*sctx
= (struct si_context
*)ctx
;
720 struct pipe_constant_buffer cb
;
721 static const struct pipe_clip_state zeros
;
723 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
726 sctx
->clip_state
.state
= *state
;
727 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
728 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_state
);
731 cb
.user_buffer
= state
->ucp
;
732 cb
.buffer_offset
= 0;
733 cb
.buffer_size
= 4*4*8;
734 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
735 pipe_resource_reference(&cb
.buffer
, NULL
);
738 static void si_emit_clip_state(struct si_context
*sctx
)
740 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
742 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
743 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
746 static void si_emit_clip_regs(struct si_context
*sctx
)
748 struct si_shader
*vs
= si_get_vs_state(sctx
);
749 struct si_shader_selector
*vs_sel
= vs
->selector
;
750 struct tgsi_shader_info
*info
= &vs_sel
->info
;
751 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
752 unsigned window_space
=
753 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
754 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
755 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
756 unsigned culldist_mask
= vs_sel
->culldist_mask
;
759 if (vs
->key
.opt
.clip_disable
) {
760 assert(!info
->culldist_writemask
);
764 total_mask
= clipdist_mask
| culldist_mask
;
766 /* Clip distances on points have no effect, so need to be implemented
767 * as cull distances. This applies for the clipvertex case as well.
769 * Setting this for primitives other than points should have no adverse
772 clipdist_mask
&= rs
->clip_plane_enable
;
773 culldist_mask
|= clipdist_mask
;
775 radeon_opt_set_context_reg(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
776 SI_TRACKED_PA_CL_VS_OUT_CNTL
,
777 vs_sel
->pa_cl_vs_out_cntl
|
778 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
779 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
780 clipdist_mask
| (culldist_mask
<< 8));
781 radeon_opt_set_context_reg(sctx
, R_028810_PA_CL_CLIP_CNTL
,
782 SI_TRACKED_PA_CL_CLIP_CNTL
,
783 rs
->pa_cl_clip_cntl
|
785 S_028810_CLIP_DISABLE(window_space
));
789 * inferred state between framebuffer and rasterizer
791 static void si_update_poly_offset_state(struct si_context
*sctx
)
793 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
795 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
796 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
800 /* Use the user format, not db_render_format, so that the polygon
801 * offset behaves as expected by applications.
803 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
804 case PIPE_FORMAT_Z16_UNORM
:
805 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
807 default: /* 24-bit */
808 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
810 case PIPE_FORMAT_Z32_FLOAT
:
811 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
812 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
821 static uint32_t si_translate_fill(uint32_t func
)
824 case PIPE_POLYGON_MODE_FILL
:
825 return V_028814_X_DRAW_TRIANGLES
;
826 case PIPE_POLYGON_MODE_LINE
:
827 return V_028814_X_DRAW_LINES
;
828 case PIPE_POLYGON_MODE_POINT
:
829 return V_028814_X_DRAW_POINTS
;
832 return V_028814_X_DRAW_POINTS
;
836 static void *si_create_rs_state(struct pipe_context
*ctx
,
837 const struct pipe_rasterizer_state
*state
)
839 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
840 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
841 struct si_pm4_state
*pm4
= &rs
->pm4
;
843 float psize_min
, psize_max
;
849 rs
->scissor_enable
= state
->scissor
;
850 rs
->clip_halfz
= state
->clip_halfz
;
851 rs
->two_side
= state
->light_twoside
;
852 rs
->multisample_enable
= state
->multisample
;
853 rs
->force_persample_interp
= state
->force_persample_interp
;
854 rs
->clip_plane_enable
= state
->clip_plane_enable
;
855 rs
->line_stipple_enable
= state
->line_stipple_enable
;
856 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
857 rs
->line_smooth
= state
->line_smooth
;
858 rs
->line_width
= state
->line_width
;
859 rs
->poly_smooth
= state
->poly_smooth
;
860 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
862 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
863 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
864 rs
->flatshade
= state
->flatshade
;
865 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
866 rs
->rasterizer_discard
= state
->rasterizer_discard
;
867 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
868 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
869 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
870 rs
->pa_cl_clip_cntl
=
871 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
872 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip_near
) |
873 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip_far
) |
874 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
875 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
877 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
878 S_0286D4_FLAT_SHADE_ENA(1) |
879 S_0286D4_PNT_SPRITE_ENA(state
->point_quad_rasterization
) |
880 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
883 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
884 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
886 /* point size 12.4 fixed point */
887 tmp
= (unsigned)(state
->point_size
* 8.0);
888 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
890 if (state
->point_size_per_vertex
) {
891 psize_min
= util_get_min_point_size(state
);
894 /* Force the point size to be as if the vertex output was disabled. */
895 psize_min
= state
->point_size
;
896 psize_max
= state
->point_size
;
898 rs
->max_point_size
= psize_max
;
900 /* Divide by two, because 0.5 = 1 pixel. */
901 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
902 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
903 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
905 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
906 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
907 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
908 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
909 S_028A48_MSAA_ENABLE(state
->multisample
||
910 state
->poly_smooth
||
911 state
->line_smooth
) |
912 S_028A48_VPORT_SCISSOR_ENABLE(1) |
913 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->info
.chip_class
>= GFX9
));
915 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
916 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
917 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
919 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
920 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
921 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
922 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
923 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
924 S_028814_FACE(!state
->front_ccw
) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
928 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
929 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
933 if (!rs
->uses_poly_offset
)
936 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
937 if (!rs
->pm4_poly_offset
) {
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i
= 0; i
< 3; i
++) {
944 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
945 float offset_units
= state
->offset_units
;
946 float offset_scale
= state
->offset_scale
* 16.0f
;
947 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
949 if (!state
->offset_units_unscaled
) {
951 case 0: /* 16-bit zbuffer */
952 offset_units
*= 4.0f
;
953 pa_su_poly_offset_db_fmt_cntl
=
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
956 case 1: /* 24-bit zbuffer */
957 offset_units
*= 2.0f
;
958 pa_su_poly_offset_db_fmt_cntl
=
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
961 case 2: /* 32-bit zbuffer */
962 offset_units
*= 1.0f
;
963 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
964 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
969 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
971 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
973 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
975 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
977 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
978 pa_su_poly_offset_db_fmt_cntl
);
984 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
986 struct si_context
*sctx
= (struct si_context
*)ctx
;
987 struct si_state_rasterizer
*old_rs
=
988 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
989 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
994 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
995 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
999 sctx
->framebuffer
.nr_samples
> 1)
1000 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
1003 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1004 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1006 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1007 si_update_poly_offset_state(sctx
);
1010 old_rs
->scissor_enable
!= rs
->scissor_enable
) {
1011 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1012 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scissors
);
1016 old_rs
->line_width
!= rs
->line_width
||
1017 old_rs
->max_point_size
!= rs
->max_point_size
)
1018 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.guardband
);
1021 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1022 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1023 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.viewports
);
1027 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1028 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1029 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
1031 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1032 rs
->line_stipple_enable
;
1035 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1036 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1037 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1038 old_rs
->flatshade
!= rs
->flatshade
||
1039 old_rs
->two_side
!= rs
->two_side
||
1040 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1041 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1042 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1043 old_rs
->line_smooth
!= rs
->line_smooth
||
1044 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1045 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1046 sctx
->do_update_shaders
= true;
1049 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1051 struct si_context
*sctx
= (struct si_context
*)ctx
;
1052 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1054 if (sctx
->queued
.named
.rasterizer
== state
)
1055 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1057 FREE(rs
->pm4_poly_offset
);
1058 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1062 * infeered state between dsa and stencil ref
1064 static void si_emit_stencil_ref(struct si_context
*sctx
)
1066 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
1067 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1068 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1070 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1071 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1072 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1073 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1074 S_028430_STENCILOPVAL(1));
1075 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1076 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1077 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1078 S_028434_STENCILOPVAL_BF(1));
1081 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1082 const struct pipe_stencil_ref
*state
)
1084 struct si_context
*sctx
= (struct si_context
*)ctx
;
1086 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1089 sctx
->stencil_ref
.state
= *state
;
1090 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1098 static uint32_t si_translate_stencil_op(int s_op
)
1101 case PIPE_STENCIL_OP_KEEP
:
1102 return V_02842C_STENCIL_KEEP
;
1103 case PIPE_STENCIL_OP_ZERO
:
1104 return V_02842C_STENCIL_ZERO
;
1105 case PIPE_STENCIL_OP_REPLACE
:
1106 return V_02842C_STENCIL_REPLACE_TEST
;
1107 case PIPE_STENCIL_OP_INCR
:
1108 return V_02842C_STENCIL_ADD_CLAMP
;
1109 case PIPE_STENCIL_OP_DECR
:
1110 return V_02842C_STENCIL_SUB_CLAMP
;
1111 case PIPE_STENCIL_OP_INCR_WRAP
:
1112 return V_02842C_STENCIL_ADD_WRAP
;
1113 case PIPE_STENCIL_OP_DECR_WRAP
:
1114 return V_02842C_STENCIL_SUB_WRAP
;
1115 case PIPE_STENCIL_OP_INVERT
:
1116 return V_02842C_STENCIL_INVERT
;
1118 PRINT_ERR("Unknown stencil op %d", s_op
);
1125 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1127 return s
->enabled
&& s
->writemask
&&
1128 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1129 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1130 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1133 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1135 /* REPLACE is normally order invariant, except when the stencil
1136 * reference value is written by the fragment shader. Tracking this
1137 * interaction does not seem worth the effort, so be conservative. */
1138 return op
!= PIPE_STENCIL_OP_INCR
&&
1139 op
!= PIPE_STENCIL_OP_DECR
&&
1140 op
!= PIPE_STENCIL_OP_REPLACE
;
1143 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1144 * invariant in the sense that the set of passing fragments as well as the
1145 * final stencil buffer result does not depend on the order of fragments. */
1146 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1148 return !state
->enabled
|| !state
->writemask
||
1149 /* The following assumes that Z writes are disabled. */
1150 (state
->func
== PIPE_FUNC_ALWAYS
&&
1151 si_order_invariant_stencil_op(state
->zpass_op
) &&
1152 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1153 (state
->func
== PIPE_FUNC_NEVER
&&
1154 si_order_invariant_stencil_op(state
->fail_op
));
1157 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1158 const struct pipe_depth_stencil_alpha_state
*state
)
1160 struct si_context
*sctx
= (struct si_context
*)ctx
;
1161 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1162 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1163 unsigned db_depth_control
;
1164 uint32_t db_stencil_control
= 0;
1170 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1171 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1172 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1173 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1175 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1176 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1177 S_028800_ZFUNC(state
->depth
.func
) |
1178 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1181 if (state
->stencil
[0].enabled
) {
1182 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1183 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1184 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1185 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1186 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1188 if (state
->stencil
[1].enabled
) {
1189 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1190 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1191 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1192 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1193 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1198 if (state
->alpha
.enabled
) {
1199 dsa
->alpha_func
= state
->alpha
.func
;
1201 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1202 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1204 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1207 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1208 if (state
->stencil
[0].enabled
)
1209 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1210 if (state
->depth
.bounds_test
) {
1211 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1212 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1215 dsa
->depth_enabled
= state
->depth
.enabled
;
1216 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1217 state
->depth
.writemask
;
1218 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1219 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1220 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1221 si_dsa_writes_stencil(&state
->stencil
[1]));
1222 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1223 dsa
->stencil_write_enabled
;
1225 bool zfunc_is_ordered
=
1226 state
->depth
.func
== PIPE_FUNC_NEVER
||
1227 state
->depth
.func
== PIPE_FUNC_LESS
||
1228 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1229 state
->depth
.func
== PIPE_FUNC_GREATER
||
1230 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1232 bool nozwrite_and_order_invariant_stencil
=
1233 !dsa
->db_can_write
||
1234 (!dsa
->depth_write_enabled
&&
1235 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1236 si_order_invariant_stencil_state(&state
->stencil
[1]));
1238 dsa
->order_invariance
[1].zs
=
1239 nozwrite_and_order_invariant_stencil
||
1240 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1241 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1243 dsa
->order_invariance
[1].pass_set
=
1244 nozwrite_and_order_invariant_stencil
||
1245 (!dsa
->stencil_write_enabled
&&
1246 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1247 state
->depth
.func
== PIPE_FUNC_NEVER
));
1248 dsa
->order_invariance
[0].pass_set
=
1249 !dsa
->depth_write_enabled
||
1250 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1251 state
->depth
.func
== PIPE_FUNC_NEVER
);
1253 dsa
->order_invariance
[1].pass_last
=
1254 sctx
->screen
->assume_no_z_fights
&&
1255 !dsa
->stencil_write_enabled
&&
1256 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1257 dsa
->order_invariance
[0].pass_last
=
1258 sctx
->screen
->assume_no_z_fights
&&
1259 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1264 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1266 struct si_context
*sctx
= (struct si_context
*)ctx
;
1267 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1268 struct si_state_dsa
*dsa
= state
;
1273 si_pm4_bind_state(sctx
, dsa
, dsa
);
1275 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1276 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1277 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1278 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.stencil_ref
);
1281 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1282 sctx
->do_update_shaders
= true;
1284 if (sctx
->screen
->dpbb_allowed
&&
1286 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1287 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1288 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1289 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
1291 if (sctx
->screen
->has_out_of_order_rast
&&
1293 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1294 sizeof(old_dsa
->order_invariance
))))
1295 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1298 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1300 struct si_context
*sctx
= (struct si_context
*)ctx
;
1301 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1304 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1306 struct pipe_depth_stencil_alpha_state dsa
= {};
1308 return sctx
->b
.create_depth_stencil_alpha_state(&sctx
->b
, &dsa
);
1311 /* DB RENDER STATE */
1313 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1315 struct si_context
*sctx
= (struct si_context
*)ctx
;
1317 /* Pipeline stat & streamout queries. */
1319 sctx
->flags
&= ~SI_CONTEXT_STOP_PIPELINE_STATS
;
1320 sctx
->flags
|= SI_CONTEXT_START_PIPELINE_STATS
;
1322 sctx
->flags
&= ~SI_CONTEXT_START_PIPELINE_STATS
;
1323 sctx
->flags
|= SI_CONTEXT_STOP_PIPELINE_STATS
;
1326 /* Occlusion queries. */
1327 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1328 sctx
->occlusion_queries_disabled
= !enable
;
1329 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1333 void si_set_occlusion_query_state(struct si_context
*sctx
,
1334 bool old_perfect_enable
)
1336 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
1338 bool perfect_enable
= sctx
->num_perfect_occlusion_queries
!= 0;
1340 if (perfect_enable
!= old_perfect_enable
)
1341 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
1344 void si_save_qbo_state(struct si_context
*sctx
, struct si_qbo_state
*st
)
1346 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1348 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1349 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1352 static void si_emit_db_render_state(struct si_context
*sctx
)
1354 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1355 unsigned db_shader_control
, db_render_control
, db_count_control
;
1357 /* DB_RENDER_CONTROL */
1358 if (sctx
->dbcb_depth_copy_enabled
||
1359 sctx
->dbcb_stencil_copy_enabled
) {
1361 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1362 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1363 S_028000_COPY_CENTROID(1) |
1364 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
);
1365 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1367 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1368 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
);
1371 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1372 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
);
1375 /* DB_COUNT_CONTROL (occlusion queries) */
1376 if (sctx
->num_occlusion_queries
> 0 &&
1377 !sctx
->occlusion_queries_disabled
) {
1378 bool perfect
= sctx
->num_perfect_occlusion_queries
> 0;
1380 if (sctx
->chip_class
>= CIK
) {
1381 unsigned log_sample_rate
= sctx
->framebuffer
.log_samples
;
1383 /* Stoney doesn't increment occlusion query counters
1384 * if the sample rate is 16x. Use 8x sample rate instead.
1386 if (sctx
->family
== CHIP_STONEY
)
1387 log_sample_rate
= MIN2(log_sample_rate
, 3);
1390 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1391 S_028004_SAMPLE_RATE(log_sample_rate
) |
1392 S_028004_ZPASS_ENABLE(1) |
1393 S_028004_SLICE_EVEN_ENABLE(1) |
1394 S_028004_SLICE_ODD_ENABLE(1);
1397 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1398 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
);
1401 /* Disable occlusion queries. */
1402 if (sctx
->chip_class
>= CIK
) {
1403 db_count_control
= 0;
1405 db_count_control
= S_028004_ZPASS_INCREMENT_DISABLE(1);
1409 radeon_opt_set_context_reg2(sctx
, R_028000_DB_RENDER_CONTROL
,
1410 SI_TRACKED_DB_RENDER_CONTROL
, db_render_control
,
1413 /* DB_RENDER_OVERRIDE2 */
1414 radeon_opt_set_context_reg(sctx
, R_028010_DB_RENDER_OVERRIDE2
,
1415 SI_TRACKED_DB_RENDER_OVERRIDE2
,
1416 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1417 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1418 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1420 db_shader_control
= sctx
->ps_db_shader_control
;
1422 /* Bug workaround for smoothing (overrasterization) on SI. */
1423 if (sctx
->chip_class
== SI
&& sctx
->smoothing_enabled
) {
1424 db_shader_control
&= C_02880C_Z_ORDER
;
1425 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1428 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1429 if (!rs
->multisample_enable
)
1430 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1432 if (sctx
->screen
->has_rbplus
&&
1433 !sctx
->screen
->rbplus_allowed
)
1434 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1436 radeon_opt_set_context_reg(sctx
, R_02880C_DB_SHADER_CONTROL
,
1437 SI_TRACKED_DB_SHADER_CONTROL
, db_shader_control
);
1441 * format translation
1443 static uint32_t si_translate_colorformat(enum pipe_format format
)
1445 const struct util_format_description
*desc
= util_format_description(format
);
1447 return V_028C70_COLOR_INVALID
;
1449 #define HAS_SIZE(x,y,z,w) \
1450 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1451 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1453 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1454 return V_028C70_COLOR_10_11_11
;
1456 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1457 return V_028C70_COLOR_INVALID
;
1459 /* hw cannot support mixed formats (except depth/stencil, since
1460 * stencil is not written to). */
1461 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1462 return V_028C70_COLOR_INVALID
;
1464 switch (desc
->nr_channels
) {
1466 switch (desc
->channel
[0].size
) {
1468 return V_028C70_COLOR_8
;
1470 return V_028C70_COLOR_16
;
1472 return V_028C70_COLOR_32
;
1476 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1477 switch (desc
->channel
[0].size
) {
1479 return V_028C70_COLOR_8_8
;
1481 return V_028C70_COLOR_16_16
;
1483 return V_028C70_COLOR_32_32
;
1485 } else if (HAS_SIZE(8,24,0,0)) {
1486 return V_028C70_COLOR_24_8
;
1487 } else if (HAS_SIZE(24,8,0,0)) {
1488 return V_028C70_COLOR_8_24
;
1492 if (HAS_SIZE(5,6,5,0)) {
1493 return V_028C70_COLOR_5_6_5
;
1494 } else if (HAS_SIZE(32,8,24,0)) {
1495 return V_028C70_COLOR_X24_8_32_FLOAT
;
1499 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1500 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1501 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1502 switch (desc
->channel
[0].size
) {
1504 return V_028C70_COLOR_4_4_4_4
;
1506 return V_028C70_COLOR_8_8_8_8
;
1508 return V_028C70_COLOR_16_16_16_16
;
1510 return V_028C70_COLOR_32_32_32_32
;
1512 } else if (HAS_SIZE(5,5,5,1)) {
1513 return V_028C70_COLOR_1_5_5_5
;
1514 } else if (HAS_SIZE(1,5,5,5)) {
1515 return V_028C70_COLOR_5_5_5_1
;
1516 } else if (HAS_SIZE(10,10,10,2)) {
1517 return V_028C70_COLOR_2_10_10_10
;
1521 return V_028C70_COLOR_INVALID
;
1524 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1526 if (SI_BIG_ENDIAN
) {
1527 switch(colorformat
) {
1528 /* 8-bit buffers. */
1529 case V_028C70_COLOR_8
:
1530 return V_028C70_ENDIAN_NONE
;
1532 /* 16-bit buffers. */
1533 case V_028C70_COLOR_5_6_5
:
1534 case V_028C70_COLOR_1_5_5_5
:
1535 case V_028C70_COLOR_4_4_4_4
:
1536 case V_028C70_COLOR_16
:
1537 case V_028C70_COLOR_8_8
:
1538 return V_028C70_ENDIAN_8IN16
;
1540 /* 32-bit buffers. */
1541 case V_028C70_COLOR_8_8_8_8
:
1542 case V_028C70_COLOR_2_10_10_10
:
1543 case V_028C70_COLOR_8_24
:
1544 case V_028C70_COLOR_24_8
:
1545 case V_028C70_COLOR_16_16
:
1546 return V_028C70_ENDIAN_8IN32
;
1548 /* 64-bit buffers. */
1549 case V_028C70_COLOR_16_16_16_16
:
1550 return V_028C70_ENDIAN_8IN16
;
1552 case V_028C70_COLOR_32_32
:
1553 return V_028C70_ENDIAN_8IN32
;
1555 /* 128-bit buffers. */
1556 case V_028C70_COLOR_32_32_32_32
:
1557 return V_028C70_ENDIAN_8IN32
;
1559 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1562 return V_028C70_ENDIAN_NONE
;
1566 static uint32_t si_translate_dbformat(enum pipe_format format
)
1569 case PIPE_FORMAT_Z16_UNORM
:
1570 return V_028040_Z_16
;
1571 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1572 case PIPE_FORMAT_X8Z24_UNORM
:
1573 case PIPE_FORMAT_Z24X8_UNORM
:
1574 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1575 return V_028040_Z_24
; /* deprecated on SI */
1576 case PIPE_FORMAT_Z32_FLOAT
:
1577 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1578 return V_028040_Z_32_FLOAT
;
1580 return V_028040_Z_INVALID
;
1585 * Texture translation
1588 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1589 enum pipe_format format
,
1590 const struct util_format_description
*desc
,
1593 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1594 bool uniform
= true;
1597 /* Colorspace (return non-RGB formats directly). */
1598 switch (desc
->colorspace
) {
1599 /* Depth stencil formats */
1600 case UTIL_FORMAT_COLORSPACE_ZS
:
1602 case PIPE_FORMAT_Z16_UNORM
:
1603 return V_008F14_IMG_DATA_FORMAT_16
;
1604 case PIPE_FORMAT_X24S8_UINT
:
1605 case PIPE_FORMAT_S8X24_UINT
:
1607 * Implemented as an 8_8_8_8 data format to fix texture
1608 * gathers in stencil sampling. This affects at least
1609 * GL45-CTS.texture_cube_map_array.sampling on VI.
1611 if (sscreen
->info
.chip_class
<= VI
)
1612 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1614 if (format
== PIPE_FORMAT_X24S8_UINT
)
1615 return V_008F14_IMG_DATA_FORMAT_8_24
;
1617 return V_008F14_IMG_DATA_FORMAT_24_8
;
1618 case PIPE_FORMAT_Z24X8_UNORM
:
1619 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1620 return V_008F14_IMG_DATA_FORMAT_8_24
;
1621 case PIPE_FORMAT_X8Z24_UNORM
:
1622 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1623 return V_008F14_IMG_DATA_FORMAT_24_8
;
1624 case PIPE_FORMAT_S8_UINT
:
1625 return V_008F14_IMG_DATA_FORMAT_8
;
1626 case PIPE_FORMAT_Z32_FLOAT
:
1627 return V_008F14_IMG_DATA_FORMAT_32
;
1628 case PIPE_FORMAT_X32_S8X24_UINT
:
1629 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1630 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1635 case UTIL_FORMAT_COLORSPACE_YUV
:
1636 goto out_unknown
; /* TODO */
1638 case UTIL_FORMAT_COLORSPACE_SRGB
:
1639 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1647 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1648 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1652 case PIPE_FORMAT_RGTC1_SNORM
:
1653 case PIPE_FORMAT_LATC1_SNORM
:
1654 case PIPE_FORMAT_RGTC1_UNORM
:
1655 case PIPE_FORMAT_LATC1_UNORM
:
1656 return V_008F14_IMG_DATA_FORMAT_BC4
;
1657 case PIPE_FORMAT_RGTC2_SNORM
:
1658 case PIPE_FORMAT_LATC2_SNORM
:
1659 case PIPE_FORMAT_RGTC2_UNORM
:
1660 case PIPE_FORMAT_LATC2_UNORM
:
1661 return V_008F14_IMG_DATA_FORMAT_BC5
;
1667 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1668 (sscreen
->info
.family
== CHIP_STONEY
||
1669 sscreen
->info
.family
== CHIP_VEGA10
||
1670 sscreen
->info
.family
== CHIP_RAVEN
)) {
1672 case PIPE_FORMAT_ETC1_RGB8
:
1673 case PIPE_FORMAT_ETC2_RGB8
:
1674 case PIPE_FORMAT_ETC2_SRGB8
:
1675 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1676 case PIPE_FORMAT_ETC2_RGB8A1
:
1677 case PIPE_FORMAT_ETC2_SRGB8A1
:
1678 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1679 case PIPE_FORMAT_ETC2_RGBA8
:
1680 case PIPE_FORMAT_ETC2_SRGBA8
:
1681 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1682 case PIPE_FORMAT_ETC2_R11_UNORM
:
1683 case PIPE_FORMAT_ETC2_R11_SNORM
:
1684 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1685 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1686 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1687 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1693 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1694 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1698 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1699 case PIPE_FORMAT_BPTC_SRGBA
:
1700 return V_008F14_IMG_DATA_FORMAT_BC7
;
1701 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1702 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1703 return V_008F14_IMG_DATA_FORMAT_BC6
;
1709 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1711 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1712 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1713 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1714 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1715 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1716 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1722 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1723 if (!sscreen
->info
.has_format_bc1_through_bc7
)
1727 case PIPE_FORMAT_DXT1_RGB
:
1728 case PIPE_FORMAT_DXT1_RGBA
:
1729 case PIPE_FORMAT_DXT1_SRGB
:
1730 case PIPE_FORMAT_DXT1_SRGBA
:
1731 return V_008F14_IMG_DATA_FORMAT_BC1
;
1732 case PIPE_FORMAT_DXT3_RGBA
:
1733 case PIPE_FORMAT_DXT3_SRGBA
:
1734 return V_008F14_IMG_DATA_FORMAT_BC2
;
1735 case PIPE_FORMAT_DXT5_RGBA
:
1736 case PIPE_FORMAT_DXT5_SRGBA
:
1737 return V_008F14_IMG_DATA_FORMAT_BC3
;
1743 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1744 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1745 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1746 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1749 /* R8G8Bx_SNORM - TODO CxV8U8 */
1751 /* hw cannot support mixed formats (except depth/stencil, since only
1753 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1756 /* See whether the components are of the same size. */
1757 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1758 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1761 /* Non-uniform formats. */
1763 switch(desc
->nr_channels
) {
1765 if (desc
->channel
[0].size
== 5 &&
1766 desc
->channel
[1].size
== 6 &&
1767 desc
->channel
[2].size
== 5) {
1768 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1772 if (desc
->channel
[0].size
== 5 &&
1773 desc
->channel
[1].size
== 5 &&
1774 desc
->channel
[2].size
== 5 &&
1775 desc
->channel
[3].size
== 1) {
1776 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1778 if (desc
->channel
[0].size
== 1 &&
1779 desc
->channel
[1].size
== 5 &&
1780 desc
->channel
[2].size
== 5 &&
1781 desc
->channel
[3].size
== 5) {
1782 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1784 if (desc
->channel
[0].size
== 10 &&
1785 desc
->channel
[1].size
== 10 &&
1786 desc
->channel
[2].size
== 10 &&
1787 desc
->channel
[3].size
== 2) {
1788 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1795 if (first_non_void
< 0 || first_non_void
> 3)
1798 /* uniform formats */
1799 switch (desc
->channel
[first_non_void
].size
) {
1801 switch (desc
->nr_channels
) {
1802 #if 0 /* Not supported for render targets */
1804 return V_008F14_IMG_DATA_FORMAT_4_4
;
1807 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1811 switch (desc
->nr_channels
) {
1813 return V_008F14_IMG_DATA_FORMAT_8
;
1815 return V_008F14_IMG_DATA_FORMAT_8_8
;
1817 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1821 switch (desc
->nr_channels
) {
1823 return V_008F14_IMG_DATA_FORMAT_16
;
1825 return V_008F14_IMG_DATA_FORMAT_16_16
;
1827 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1831 switch (desc
->nr_channels
) {
1833 return V_008F14_IMG_DATA_FORMAT_32
;
1835 return V_008F14_IMG_DATA_FORMAT_32_32
;
1836 #if 0 /* Not supported for render targets */
1838 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1841 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1849 static unsigned si_tex_wrap(unsigned wrap
)
1853 case PIPE_TEX_WRAP_REPEAT
:
1854 return V_008F30_SQ_TEX_WRAP
;
1855 case PIPE_TEX_WRAP_CLAMP
:
1856 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1857 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1858 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1859 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1860 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1861 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1862 return V_008F30_SQ_TEX_MIRROR
;
1863 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1864 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1865 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1866 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1867 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1868 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1872 static unsigned si_tex_mipfilter(unsigned filter
)
1875 case PIPE_TEX_MIPFILTER_NEAREST
:
1876 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1877 case PIPE_TEX_MIPFILTER_LINEAR
:
1878 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1880 case PIPE_TEX_MIPFILTER_NONE
:
1881 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1885 static unsigned si_tex_compare(unsigned compare
)
1889 case PIPE_FUNC_NEVER
:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1891 case PIPE_FUNC_LESS
:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1893 case PIPE_FUNC_EQUAL
:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1895 case PIPE_FUNC_LEQUAL
:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1897 case PIPE_FUNC_GREATER
:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1899 case PIPE_FUNC_NOTEQUAL
:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1901 case PIPE_FUNC_GEQUAL
:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1903 case PIPE_FUNC_ALWAYS
:
1904 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1908 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct si_texture
*tex
,
1909 unsigned view_target
, unsigned nr_samples
)
1911 unsigned res_target
= tex
->buffer
.b
.b
.target
;
1913 if (view_target
== PIPE_TEXTURE_CUBE
||
1914 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1915 res_target
= view_target
;
1916 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1917 else if (res_target
== PIPE_TEXTURE_CUBE
||
1918 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1919 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1921 /* GFX9 allocates 1D textures as 2D. */
1922 if ((res_target
== PIPE_TEXTURE_1D
||
1923 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1924 sscreen
->info
.chip_class
>= GFX9
&&
1925 tex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1926 if (res_target
== PIPE_TEXTURE_1D
)
1927 res_target
= PIPE_TEXTURE_2D
;
1929 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1932 switch (res_target
) {
1934 case PIPE_TEXTURE_1D
:
1935 return V_008F1C_SQ_RSRC_IMG_1D
;
1936 case PIPE_TEXTURE_1D_ARRAY
:
1937 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1938 case PIPE_TEXTURE_2D
:
1939 case PIPE_TEXTURE_RECT
:
1940 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1941 V_008F1C_SQ_RSRC_IMG_2D
;
1942 case PIPE_TEXTURE_2D_ARRAY
:
1943 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1944 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1945 case PIPE_TEXTURE_3D
:
1946 return V_008F1C_SQ_RSRC_IMG_3D
;
1947 case PIPE_TEXTURE_CUBE
:
1948 case PIPE_TEXTURE_CUBE_ARRAY
:
1949 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1954 * Format support testing
1957 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1959 const struct util_format_description
*desc
= util_format_description(format
);
1963 return si_translate_texformat(screen
, format
, desc
,
1964 util_format_get_first_non_void_channel(format
)) != ~0U;
1967 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1968 const struct util_format_description
*desc
,
1973 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1974 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1976 assert(first_non_void
>= 0);
1978 if (desc
->nr_channels
== 4 &&
1979 desc
->channel
[0].size
== 10 &&
1980 desc
->channel
[1].size
== 10 &&
1981 desc
->channel
[2].size
== 10 &&
1982 desc
->channel
[3].size
== 2)
1983 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1985 /* See whether the components are of the same size. */
1986 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1987 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1988 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1991 switch (desc
->channel
[first_non_void
].size
) {
1993 switch (desc
->nr_channels
) {
1995 case 3: /* 3 loads */
1996 return V_008F0C_BUF_DATA_FORMAT_8
;
1998 return V_008F0C_BUF_DATA_FORMAT_8_8
;
2000 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
2004 switch (desc
->nr_channels
) {
2006 case 3: /* 3 loads */
2007 return V_008F0C_BUF_DATA_FORMAT_16
;
2009 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2011 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2015 switch (desc
->nr_channels
) {
2017 return V_008F0C_BUF_DATA_FORMAT_32
;
2019 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2023 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2027 /* Legacy double formats. */
2028 switch (desc
->nr_channels
) {
2029 case 1: /* 1 load */
2030 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2031 case 2: /* 1 load */
2032 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2033 case 3: /* 3 loads */
2034 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2035 case 4: /* 2 loads */
2036 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2041 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2044 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2045 const struct util_format_description
*desc
,
2048 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2049 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2051 assert(first_non_void
>= 0);
2053 switch (desc
->channel
[first_non_void
].type
) {
2054 case UTIL_FORMAT_TYPE_SIGNED
:
2055 case UTIL_FORMAT_TYPE_FIXED
:
2056 if (desc
->channel
[first_non_void
].size
>= 32 ||
2057 desc
->channel
[first_non_void
].pure_integer
)
2058 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2059 else if (desc
->channel
[first_non_void
].normalized
)
2060 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2062 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2064 case UTIL_FORMAT_TYPE_UNSIGNED
:
2065 if (desc
->channel
[first_non_void
].size
>= 32 ||
2066 desc
->channel
[first_non_void
].pure_integer
)
2067 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2068 else if (desc
->channel
[first_non_void
].normalized
)
2069 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2071 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2073 case UTIL_FORMAT_TYPE_FLOAT
:
2075 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2079 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2080 enum pipe_format format
,
2083 const struct util_format_description
*desc
;
2085 unsigned data_format
;
2087 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2088 PIPE_BIND_SAMPLER_VIEW
|
2089 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2091 desc
= util_format_description(format
);
2095 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2096 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2097 * for read-only access (with caveats surrounding bounds checks), but
2098 * obviously fails for write access which we have to implement for
2099 * shader images. Luckily, OpenGL doesn't expect this to be supported
2100 * anyway, and so the only impact is on PBO uploads / downloads, which
2101 * shouldn't be expected to be fast for GL_RGB anyway.
2103 if (desc
->block
.bits
== 3 * 8 ||
2104 desc
->block
.bits
== 3 * 16) {
2105 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2106 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2112 first_non_void
= util_format_get_first_non_void_channel(format
);
2113 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2114 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2120 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2122 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2123 si_translate_colorswap(format
, false) != ~0U;
2126 static bool si_is_zs_format_supported(enum pipe_format format
)
2128 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2131 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2132 enum pipe_format format
,
2133 enum pipe_texture_target target
,
2134 unsigned sample_count
,
2135 unsigned storage_sample_count
,
2138 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2139 unsigned retval
= 0;
2141 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2142 PRINT_ERR("r600: unsupported texture type %d\n", target
);
2146 if (MAX2(1, sample_count
) < MAX2(1, storage_sample_count
))
2149 if (sample_count
> 1) {
2150 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2153 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2156 /* Only power-of-two sample counts are supported. */
2157 if (!util_is_power_of_two_or_zero(sample_count
) ||
2158 !util_is_power_of_two_or_zero(storage_sample_count
))
2161 /* MSAA support without framebuffer attachments. */
2162 if (format
== PIPE_FORMAT_NONE
&& sample_count
<= 16)
2165 if (!sscreen
->info
.has_eqaa_surface_allocator
||
2166 util_format_is_depth_or_stencil(format
)) {
2167 /* Color without EQAA or depth/stencil. */
2168 if (sample_count
> 8 ||
2169 sample_count
!= storage_sample_count
)
2172 /* Color with EQAA. */
2173 if (sample_count
> 16 ||
2174 storage_sample_count
> 8)
2179 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2180 PIPE_BIND_SHADER_IMAGE
)) {
2181 if (target
== PIPE_BUFFER
) {
2182 retval
|= si_is_vertex_format_supported(
2183 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2184 PIPE_BIND_SHADER_IMAGE
));
2186 if (si_is_sampler_format_supported(screen
, format
))
2187 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2188 PIPE_BIND_SHADER_IMAGE
);
2192 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2193 PIPE_BIND_DISPLAY_TARGET
|
2196 PIPE_BIND_BLENDABLE
)) &&
2197 si_is_colorbuffer_format_supported(format
)) {
2199 (PIPE_BIND_RENDER_TARGET
|
2200 PIPE_BIND_DISPLAY_TARGET
|
2203 if (!util_format_is_pure_integer(format
) &&
2204 !util_format_is_depth_or_stencil(format
))
2205 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2208 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2209 si_is_zs_format_supported(format
)) {
2210 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2213 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2214 retval
|= si_is_vertex_format_supported(screen
, format
,
2215 PIPE_BIND_VERTEX_BUFFER
);
2218 if ((usage
& PIPE_BIND_LINEAR
) &&
2219 !util_format_is_compressed(format
) &&
2220 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2221 retval
|= PIPE_BIND_LINEAR
;
2223 return retval
== usage
;
2227 * framebuffer handling
2230 static void si_choose_spi_color_formats(struct si_surface
*surf
,
2231 unsigned format
, unsigned swap
,
2232 unsigned ntype
, bool is_depth
)
2234 /* Alpha is needed for alpha-to-coverage.
2235 * Blending may be with or without alpha.
2237 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2238 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2239 unsigned blend
= 0; /* supports blending, but may not export alpha */
2240 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2242 /* Choose the SPI color formats. These are required values for RB+.
2243 * Other chips have multiple choices, though they are not necessarily better.
2246 case V_028C70_COLOR_5_6_5
:
2247 case V_028C70_COLOR_1_5_5_5
:
2248 case V_028C70_COLOR_5_5_5_1
:
2249 case V_028C70_COLOR_4_4_4_4
:
2250 case V_028C70_COLOR_10_11_11
:
2251 case V_028C70_COLOR_11_11_10
:
2252 case V_028C70_COLOR_8
:
2253 case V_028C70_COLOR_8_8
:
2254 case V_028C70_COLOR_8_8_8_8
:
2255 case V_028C70_COLOR_10_10_10_2
:
2256 case V_028C70_COLOR_2_10_10_10
:
2257 if (ntype
== V_028C70_NUMBER_UINT
)
2258 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2259 else if (ntype
== V_028C70_NUMBER_SINT
)
2260 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2262 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2265 case V_028C70_COLOR_16
:
2266 case V_028C70_COLOR_16_16
:
2267 case V_028C70_COLOR_16_16_16_16
:
2268 if (ntype
== V_028C70_NUMBER_UNORM
||
2269 ntype
== V_028C70_NUMBER_SNORM
) {
2270 /* UNORM16 and SNORM16 don't support blending */
2271 if (ntype
== V_028C70_NUMBER_UNORM
)
2272 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2274 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2276 /* Use 32 bits per channel for blending. */
2277 if (format
== V_028C70_COLOR_16
) {
2278 if (swap
== V_028C70_SWAP_STD
) { /* R */
2279 blend
= V_028714_SPI_SHADER_32_R
;
2280 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2281 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2282 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2285 } else if (format
== V_028C70_COLOR_16_16
) {
2286 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2287 blend
= V_028714_SPI_SHADER_32_GR
;
2288 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2289 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2290 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2293 } else /* 16_16_16_16 */
2294 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2295 } else if (ntype
== V_028C70_NUMBER_UINT
)
2296 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2297 else if (ntype
== V_028C70_NUMBER_SINT
)
2298 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2299 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2300 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2305 case V_028C70_COLOR_32
:
2306 if (swap
== V_028C70_SWAP_STD
) { /* R */
2307 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2308 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2309 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2310 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2315 case V_028C70_COLOR_32_32
:
2316 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2317 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2318 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2319 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2320 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2325 case V_028C70_COLOR_32_32_32_32
:
2326 case V_028C70_COLOR_8_24
:
2327 case V_028C70_COLOR_24_8
:
2328 case V_028C70_COLOR_X24_8_32_FLOAT
:
2329 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2337 /* The DB->CB copy needs 32_ABGR. */
2339 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2341 surf
->spi_shader_col_format
= normal
;
2342 surf
->spi_shader_col_format_alpha
= alpha
;
2343 surf
->spi_shader_col_format_blend
= blend
;
2344 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2347 static void si_initialize_color_surface(struct si_context
*sctx
,
2348 struct si_surface
*surf
)
2350 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2351 unsigned color_info
, color_attrib
;
2352 unsigned format
, swap
, ntype
, endian
;
2353 const struct util_format_description
*desc
;
2355 unsigned blend_clamp
= 0, blend_bypass
= 0;
2357 desc
= util_format_description(surf
->base
.format
);
2358 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2359 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2363 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2364 ntype
= V_028C70_NUMBER_FLOAT
;
2366 ntype
= V_028C70_NUMBER_UNORM
;
2367 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2368 ntype
= V_028C70_NUMBER_SRGB
;
2369 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2370 if (desc
->channel
[firstchan
].pure_integer
) {
2371 ntype
= V_028C70_NUMBER_SINT
;
2373 assert(desc
->channel
[firstchan
].normalized
);
2374 ntype
= V_028C70_NUMBER_SNORM
;
2376 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2377 if (desc
->channel
[firstchan
].pure_integer
) {
2378 ntype
= V_028C70_NUMBER_UINT
;
2380 assert(desc
->channel
[firstchan
].normalized
);
2381 ntype
= V_028C70_NUMBER_UNORM
;
2386 format
= si_translate_colorformat(surf
->base
.format
);
2387 if (format
== V_028C70_COLOR_INVALID
) {
2388 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2390 assert(format
!= V_028C70_COLOR_INVALID
);
2391 swap
= si_translate_colorswap(surf
->base
.format
, false);
2392 endian
= si_colorformat_endian_swap(format
);
2394 /* blend clamp should be set for all NORM/SRGB types */
2395 if (ntype
== V_028C70_NUMBER_UNORM
||
2396 ntype
== V_028C70_NUMBER_SNORM
||
2397 ntype
== V_028C70_NUMBER_SRGB
)
2400 /* set blend bypass according to docs if SINT/UINT or
2401 8/24 COLOR variants */
2402 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2403 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2404 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2409 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2410 if (format
== V_028C70_COLOR_8
||
2411 format
== V_028C70_COLOR_8_8
||
2412 format
== V_028C70_COLOR_8_8_8_8
)
2413 surf
->color_is_int8
= true;
2414 else if (format
== V_028C70_COLOR_10_10_10_2
||
2415 format
== V_028C70_COLOR_2_10_10_10
)
2416 surf
->color_is_int10
= true;
2419 color_info
= S_028C70_FORMAT(format
) |
2420 S_028C70_COMP_SWAP(swap
) |
2421 S_028C70_BLEND_CLAMP(blend_clamp
) |
2422 S_028C70_BLEND_BYPASS(blend_bypass
) |
2423 S_028C70_SIMPLE_FLOAT(1) |
2424 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2425 ntype
!= V_028C70_NUMBER_SNORM
&&
2426 ntype
!= V_028C70_NUMBER_SRGB
&&
2427 format
!= V_028C70_COLOR_8_24
&&
2428 format
!= V_028C70_COLOR_24_8
) |
2429 S_028C70_NUMBER_TYPE(ntype
) |
2430 S_028C70_ENDIAN(endian
);
2432 /* Intensity is implemented as Red, so treat it that way. */
2433 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2434 util_format_is_intensity(surf
->base
.format
));
2436 if (tex
->buffer
.b
.b
.nr_samples
> 1) {
2437 unsigned log_samples
= util_logbase2(tex
->buffer
.b
.b
.nr_samples
);
2438 unsigned log_fragments
= util_logbase2(tex
->buffer
.b
.b
.nr_storage_samples
);
2440 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2441 S_028C74_NUM_FRAGMENTS(log_fragments
);
2443 if (tex
->surface
.fmask_size
) {
2444 color_info
|= S_028C70_COMPRESSION(1);
2445 unsigned fmask_bankh
= util_logbase2(tex
->surface
.u
.legacy
.fmask
.bankh
);
2447 if (sctx
->chip_class
== SI
) {
2448 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2449 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2454 if (sctx
->chip_class
>= VI
) {
2455 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
2456 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
2458 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2459 64 for APU because all of our APUs to date use DIMMs which have
2460 a request granularity size of 64B while all other chips have a
2462 if (!sctx
->screen
->info
.has_dedicated_vram
)
2463 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
2465 if (tex
->buffer
.b
.b
.nr_storage_samples
> 1) {
2466 if (tex
->surface
.bpe
== 1)
2467 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
2468 else if (tex
->surface
.bpe
== 2)
2469 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
2472 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2473 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
2474 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2477 /* This must be set for fast clear to work without FMASK. */
2478 if (!tex
->surface
.fmask_size
&& sctx
->chip_class
== SI
) {
2479 unsigned bankh
= util_logbase2(tex
->surface
.u
.legacy
.bankh
);
2480 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2483 unsigned color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2484 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2486 if (sctx
->chip_class
>= GFX9
) {
2487 unsigned mip0_depth
= util_max_layer(&tex
->buffer
.b
.b
, 0);
2489 color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2490 color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2491 S_028C74_RESOURCE_TYPE(tex
->surface
.u
.gfx9
.resource_type
);
2492 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2493 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2494 S_028C68_MAX_MIP(tex
->buffer
.b
.b
.last_level
);
2497 surf
->cb_color_view
= color_view
;
2498 surf
->cb_color_info
= color_info
;
2499 surf
->cb_color_attrib
= color_attrib
;
2501 /* Determine pixel shader export format */
2502 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, tex
->is_depth
);
2504 surf
->color_initialized
= true;
2507 static void si_init_depth_surface(struct si_context
*sctx
,
2508 struct si_surface
*surf
)
2510 struct si_texture
*tex
= (struct si_texture
*)surf
->base
.texture
;
2511 unsigned level
= surf
->base
.u
.tex
.level
;
2512 unsigned format
, stencil_format
;
2513 uint32_t z_info
, s_info
;
2515 format
= si_translate_dbformat(tex
->db_render_format
);
2516 stencil_format
= tex
->surface
.has_stencil
?
2517 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2519 assert(format
!= V_028040_Z_INVALID
);
2520 if (format
== V_028040_Z_INVALID
)
2521 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex
->buffer
.b
.b
.format
);
2523 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2524 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2525 surf
->db_htile_data_base
= 0;
2526 surf
->db_htile_surface
= 0;
2528 if (sctx
->chip_class
>= GFX9
) {
2529 assert(tex
->surface
.u
.gfx9
.surf_offset
== 0);
2530 surf
->db_depth_base
= tex
->buffer
.gpu_address
>> 8;
2531 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2532 tex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2533 z_info
= S_028038_FORMAT(format
) |
2534 S_028038_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
)) |
2535 S_028038_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2536 S_028038_MAXMIP(tex
->buffer
.b
.b
.last_level
);
2537 s_info
= S_02803C_FORMAT(stencil_format
) |
2538 S_02803C_SW_MODE(tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2539 surf
->db_z_info2
= S_028068_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
);
2540 surf
->db_stencil_info2
= S_02806C_EPITCH(tex
->surface
.u
.gfx9
.stencil
.epitch
);
2541 surf
->db_depth_view
|= S_028008_MIPID(level
);
2542 surf
->db_depth_size
= S_02801C_X_MAX(tex
->buffer
.b
.b
.width0
- 1) |
2543 S_02801C_Y_MAX(tex
->buffer
.b
.b
.height0
- 1);
2545 if (si_htile_enabled(tex
, level
)) {
2546 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2547 S_028038_ALLOW_EXPCLEAR(1);
2549 if (tex
->tc_compatible_htile
) {
2550 unsigned max_zplanes
= 4;
2552 if (tex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2553 tex
->buffer
.b
.b
.nr_samples
> 1)
2556 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2557 S_028038_ITERATE_FLUSH(1);
2558 s_info
|= S_02803C_ITERATE_FLUSH(1);
2561 if (tex
->surface
.has_stencil
) {
2562 /* Stencil buffer workaround ported from the SI-CI-VI code.
2563 * See that for explanation.
2565 s_info
|= S_02803C_ALLOW_EXPCLEAR(tex
->buffer
.b
.b
.nr_samples
<= 1);
2567 /* Use all HTILE for depth if there's no stencil. */
2568 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2571 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2572 tex
->htile_offset
) >> 8;
2573 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2574 S_028ABC_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2575 S_028ABC_RB_ALIGNED(tex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2579 struct legacy_surf_level
*levelinfo
= &tex
->surface
.u
.legacy
.level
[level
];
2581 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2583 surf
->db_depth_base
= (tex
->buffer
.gpu_address
+
2584 tex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2585 surf
->db_stencil_base
= (tex
->buffer
.gpu_address
+
2586 tex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2588 z_info
= S_028040_FORMAT(format
) |
2589 S_028040_NUM_SAMPLES(util_logbase2(tex
->buffer
.b
.b
.nr_samples
));
2590 s_info
= S_028044_FORMAT(stencil_format
);
2591 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!tex
->tc_compatible_htile
);
2593 if (sctx
->chip_class
>= CIK
) {
2594 struct radeon_info
*info
= &sctx
->screen
->info
;
2595 unsigned index
= tex
->surface
.u
.legacy
.tiling_index
[level
];
2596 unsigned stencil_index
= tex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2597 unsigned macro_index
= tex
->surface
.u
.legacy
.macro_tile_index
;
2598 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2599 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2600 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2602 surf
->db_depth_info
|=
2603 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2604 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2605 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2606 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2607 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2608 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2609 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2610 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2612 unsigned tile_mode_index
= si_tile_mode_index(tex
, level
, false);
2613 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2614 tile_mode_index
= si_tile_mode_index(tex
, level
, true);
2615 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2618 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2619 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2620 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2621 levelinfo
->nblk_y
) / 64 - 1);
2623 if (si_htile_enabled(tex
, level
)) {
2624 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2625 S_028040_ALLOW_EXPCLEAR(1);
2627 if (tex
->surface
.has_stencil
) {
2628 /* Workaround: For a not yet understood reason, the
2629 * combination of MSAA, fast stencil clear and stencil
2630 * decompress messes with subsequent stencil buffer
2631 * uses. Problem was reproduced on Verde, Bonaire,
2632 * Tonga, and Carrizo.
2634 * Disabling EXPCLEAR works around the problem.
2636 * Check piglit's arb_texture_multisample-stencil-clear
2637 * test if you want to try changing this.
2639 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2640 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2641 } else if (!tex
->tc_compatible_htile
) {
2642 /* Use all of the htile_buffer for depth if there's no stencil.
2643 * This must not be set when TC-compatible HTILE is enabled
2646 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2649 surf
->db_htile_data_base
= (tex
->buffer
.gpu_address
+
2650 tex
->htile_offset
) >> 8;
2651 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2653 if (tex
->tc_compatible_htile
) {
2654 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2656 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2657 if (tex
->buffer
.b
.b
.nr_samples
<= 1)
2658 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2659 else if (tex
->buffer
.b
.b
.nr_samples
<= 4)
2660 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2662 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2667 surf
->db_z_info
= z_info
;
2668 surf
->db_stencil_info
= s_info
;
2670 surf
->depth_initialized
= true;
2673 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2675 if (sctx
->decompression_enabled
)
2678 if (sctx
->framebuffer
.state
.zsbuf
) {
2679 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2680 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2682 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2684 if (tex
->surface
.has_stencil
)
2685 tex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2688 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2689 while (compressed_cb_mask
) {
2690 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2691 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2692 struct si_texture
*tex
= (struct si_texture
*)surf
->texture
;
2694 if (tex
->surface
.fmask_size
)
2695 tex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2696 if (tex
->dcc_gather_statistics
)
2697 tex
->separate_dcc_dirty
= true;
2701 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2703 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2704 struct si_surface
*surf
= NULL
;
2705 struct si_texture
*tex
;
2707 if (!state
->cbufs
[i
])
2709 surf
= (struct si_surface
*)state
->cbufs
[i
];
2710 tex
= (struct si_texture
*)surf
->base
.texture
;
2712 p_atomic_dec(&tex
->framebuffers_bound
);
2716 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2717 const struct pipe_framebuffer_state
*state
)
2719 struct si_context
*sctx
= (struct si_context
*)ctx
;
2720 struct si_surface
*surf
= NULL
;
2721 struct si_texture
*tex
;
2722 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2723 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2724 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2725 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2726 bool old_has_stencil
=
2728 ((struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2729 bool unbound
= false;
2732 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2733 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2734 * We could implement the full workaround here, but it's a useless case.
2736 if ((!state
->width
|| !state
->height
) && (state
->nr_cbufs
|| state
->zsbuf
)) {
2737 unreachable("the framebuffer shouldn't have zero area");
2741 si_update_fb_dirtiness_after_rendering(sctx
);
2743 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2744 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2747 tex
= (struct si_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2748 if (tex
->dcc_gather_statistics
)
2749 vi_separate_dcc_stop_query(sctx
, tex
);
2752 /* Disable DCC if the formats are incompatible. */
2753 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2754 if (!state
->cbufs
[i
])
2757 surf
= (struct si_surface
*)state
->cbufs
[i
];
2758 tex
= (struct si_texture
*)surf
->base
.texture
;
2760 if (!surf
->dcc_incompatible
)
2763 /* Since the DCC decompression calls back into set_framebuffer-
2764 * _state, we need to unbind the framebuffer, so that
2765 * vi_separate_dcc_stop_query isn't called twice with the same
2769 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2773 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2774 if (!si_texture_disable_dcc(sctx
, tex
))
2775 si_decompress_dcc(sctx
, tex
);
2777 surf
->dcc_incompatible
= false;
2780 /* Only flush TC when changing the framebuffer state, because
2781 * the only client not using TC that can change textures is
2784 * Wait for compute shaders because of possible transitions:
2785 * - FB write -> shader read
2786 * - shader write -> FB read
2788 * DB caches are flushed on demand (using si_decompress_textures).
2790 * When MSAA is enabled, CB and TC caches are flushed on demand
2791 * (after FMASK decompression). Shader write -> FB read transitions
2792 * cannot happen for MSAA textures, because MSAA shader images are
2795 * Only flush and wait for CB if there is actually a bound color buffer.
2797 if (sctx
->framebuffer
.uncompressed_cb_mask
)
2798 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2799 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2801 sctx
->flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2803 /* u_blitter doesn't invoke depth decompression when it does multiple
2804 * blits in a row, but the only case when it matters for DB is when
2805 * doing generate_mipmap. So here we flush DB manually between
2806 * individual generate_mipmap blits.
2807 * Note that lower mipmap levels aren't compressed.
2809 if (sctx
->generate_mipmap_for_depth
) {
2810 si_make_DB_shader_coherent(sctx
, 1, false,
2811 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2812 } else if (sctx
->chip_class
== GFX9
) {
2813 /* It appears that DB metadata "leaks" in a sequence of:
2815 * - DCC decompress for shader image writes (with DB disabled)
2816 * - render with DEPTH_BEFORE_SHADER=1
2817 * Flushing DB metadata works around the problem.
2819 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2822 /* Take the maximum of the old and new count. If the new count is lower,
2823 * dirtying is needed to disable the unbound colorbuffers.
2825 sctx
->framebuffer
.dirty_cbufs
|=
2826 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2827 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2829 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2830 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2832 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2833 sctx
->framebuffer
.spi_shader_col_format
= 0;
2834 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2835 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2836 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2837 sctx
->framebuffer
.color_is_int8
= 0;
2838 sctx
->framebuffer
.color_is_int10
= 0;
2840 sctx
->framebuffer
.compressed_cb_mask
= 0;
2841 sctx
->framebuffer
.uncompressed_cb_mask
= 0;
2842 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2843 sctx
->framebuffer
.nr_color_samples
= sctx
->framebuffer
.nr_samples
;
2844 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2845 sctx
->framebuffer
.any_dst_linear
= false;
2846 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2847 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2849 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2850 if (!state
->cbufs
[i
])
2853 surf
= (struct si_surface
*)state
->cbufs
[i
];
2854 tex
= (struct si_texture
*)surf
->base
.texture
;
2856 if (!surf
->color_initialized
) {
2857 si_initialize_color_surface(sctx
, surf
);
2860 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2861 sctx
->framebuffer
.spi_shader_col_format
|=
2862 surf
->spi_shader_col_format
<< (i
* 4);
2863 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2864 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2865 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2866 surf
->spi_shader_col_format_blend
<< (i
* 4);
2867 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2868 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2870 if (surf
->color_is_int8
)
2871 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2872 if (surf
->color_is_int10
)
2873 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2875 if (tex
->surface
.fmask_size
)
2876 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2878 sctx
->framebuffer
.uncompressed_cb_mask
|= 1 << i
;
2880 /* Don't update nr_color_samples for non-AA buffers.
2881 * (e.g. destination of MSAA resolve)
2883 if (tex
->buffer
.b
.b
.nr_samples
>= 2 &&
2884 tex
->buffer
.b
.b
.nr_storage_samples
< tex
->buffer
.b
.b
.nr_samples
) {
2885 sctx
->framebuffer
.nr_color_samples
=
2886 MIN2(sctx
->framebuffer
.nr_color_samples
,
2887 tex
->buffer
.b
.b
.nr_storage_samples
);
2888 sctx
->framebuffer
.nr_color_samples
=
2889 MAX2(1, sctx
->framebuffer
.nr_color_samples
);
2892 if (tex
->surface
.is_linear
)
2893 sctx
->framebuffer
.any_dst_linear
= true;
2895 if (vi_dcc_enabled(tex
, surf
->base
.u
.tex
.level
))
2896 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2898 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2900 p_atomic_inc(&tex
->framebuffers_bound
);
2902 if (tex
->dcc_gather_statistics
) {
2903 /* Dirty tracking must be enabled for DCC usage analysis. */
2904 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2905 vi_separate_dcc_start_query(sctx
, tex
);
2909 struct si_texture
*zstex
= NULL
;
2912 surf
= (struct si_surface
*)state
->zsbuf
;
2913 zstex
= (struct si_texture
*)surf
->base
.texture
;
2915 if (!surf
->depth_initialized
) {
2916 si_init_depth_surface(sctx
, surf
);
2919 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2920 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2922 si_context_add_resource_size(sctx
, surf
->base
.texture
);
2925 si_update_ps_colorbuf0_slot(sctx
);
2926 si_update_poly_offset_state(sctx
);
2927 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
2928 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.framebuffer
);
2930 if (sctx
->screen
->dpbb_allowed
)
2931 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
2933 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2934 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2936 if (sctx
->screen
->has_out_of_order_rast
&&
2937 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2938 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2939 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2940 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2942 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2943 struct pipe_constant_buffer constbuf
= {0};
2945 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
2946 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
2948 constbuf
.buffer
= sctx
->sample_pos_buffer
;
2950 /* Set sample locations as fragment shader constants. */
2951 switch (sctx
->framebuffer
.nr_samples
) {
2953 constbuf
.buffer_offset
= 0;
2956 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x2
-
2957 (ubyte
*)sctx
->sample_positions
.x1
;
2960 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x4
-
2961 (ubyte
*)sctx
->sample_positions
.x1
;
2964 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x8
-
2965 (ubyte
*)sctx
->sample_positions
.x1
;
2968 constbuf
.buffer_offset
= (ubyte
*)sctx
->sample_positions
.x16
-
2969 (ubyte
*)sctx
->sample_positions
.x1
;
2972 PRINT_ERR("Requested an invalid number of samples %i.\n",
2973 sctx
->framebuffer
.nr_samples
);
2976 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2977 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2979 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
2982 sctx
->do_update_shaders
= true;
2984 if (!sctx
->decompression_enabled
) {
2985 /* Prevent textures decompression when the framebuffer state
2986 * changes come from the decompression passes themselves.
2988 sctx
->need_check_render_feedback
= true;
2992 static void si_emit_framebuffer_state(struct si_context
*sctx
)
2994 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
2995 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2996 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2997 struct si_texture
*tex
= NULL
;
2998 struct si_surface
*cb
= NULL
;
2999 unsigned cb_color_info
= 0;
3002 for (i
= 0; i
< nr_cbufs
; i
++) {
3003 uint64_t cb_color_base
, cb_color_fmask
, cb_color_cmask
, cb_dcc_base
;
3004 unsigned cb_color_attrib
;
3006 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
3009 cb
= (struct si_surface
*)state
->cbufs
[i
];
3011 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
3012 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
3016 tex
= (struct si_texture
*)cb
->base
.texture
;
3017 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3018 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3019 tex
->buffer
.b
.b
.nr_samples
> 1 ?
3020 RADEON_PRIO_COLOR_BUFFER_MSAA
:
3021 RADEON_PRIO_COLOR_BUFFER
);
3023 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->buffer
) {
3024 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3025 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
3026 RADEON_PRIO_SEPARATE_META
);
3029 if (tex
->dcc_separate_buffer
)
3030 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3031 tex
->dcc_separate_buffer
,
3032 RADEON_USAGE_READWRITE
,
3033 RADEON_PRIO_SEPARATE_META
);
3035 /* Compute mutable surface parameters. */
3036 cb_color_base
= tex
->buffer
.gpu_address
>> 8;
3038 cb_color_cmask
= tex
->cmask_base_address_reg
;
3040 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
3041 cb_color_attrib
= cb
->cb_color_attrib
;
3043 if (cb
->base
.u
.tex
.level
> 0)
3044 cb_color_info
&= C_028C70_FAST_CLEAR
;
3046 if (tex
->surface
.fmask_size
) {
3047 cb_color_fmask
= (tex
->buffer
.gpu_address
+ tex
->fmask_offset
) >> 8;
3048 cb_color_fmask
|= tex
->surface
.fmask_tile_swizzle
;
3052 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
3053 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
3054 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
3055 state
->cbufs
[1] == &cb
->base
&&
3056 state
->cbufs
[1]->texture
->nr_samples
<= 1;
3058 if (!is_msaa_resolve_dst
)
3059 cb_color_info
|= S_028C70_DCC_ENABLE(1);
3061 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->buffer
.gpu_address
: 0) +
3062 tex
->dcc_offset
) >> 8;
3063 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
3066 if (sctx
->chip_class
>= GFX9
) {
3067 struct gfx9_surf_meta_flags meta
;
3069 if (tex
->dcc_offset
)
3070 meta
= tex
->surface
.u
.gfx9
.dcc
;
3072 meta
= tex
->surface
.u
.gfx9
.cmask
;
3074 /* Set mutable surface parameters. */
3075 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3076 cb_color_base
|= tex
->surface
.tile_swizzle
;
3077 if (!tex
->surface
.fmask_size
)
3078 cb_color_fmask
= cb_color_base
;
3079 if (cb
->base
.u
.tex
.level
> 0)
3080 cb_color_cmask
= cb_color_base
;
3081 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3082 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3083 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3084 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3086 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3087 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3088 radeon_emit(cs
, S_028C64_BASE_256B(cb_color_base
>> 32)); /* CB_COLOR0_BASE_EXT */
3089 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3090 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3091 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3092 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3093 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3094 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3095 radeon_emit(cs
, S_028C80_BASE_256B(cb_color_cmask
>> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3096 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3097 radeon_emit(cs
, S_028C88_BASE_256B(cb_color_fmask
>> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3098 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3099 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3100 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3101 radeon_emit(cs
, S_028C98_BASE_256B(cb_dcc_base
>> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3103 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3104 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3106 /* Compute mutable surface parameters (SI-CI-VI). */
3107 const struct legacy_surf_level
*level_info
=
3108 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3109 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3110 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3112 cb_color_base
+= level_info
->offset
>> 8;
3113 /* Only macrotiled modes can set tile swizzle. */
3114 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3115 cb_color_base
|= tex
->surface
.tile_swizzle
;
3117 if (!tex
->surface
.fmask_size
)
3118 cb_color_fmask
= cb_color_base
;
3119 if (cb
->base
.u
.tex
.level
> 0)
3120 cb_color_cmask
= cb_color_base
;
3122 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3124 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3125 slice_tile_max
= level_info
->nblk_x
*
3126 level_info
->nblk_y
/ 64 - 1;
3127 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3129 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3130 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3131 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3133 if (tex
->surface
.fmask_size
) {
3134 if (sctx
->chip_class
>= CIK
)
3135 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
3136 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3137 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->surface
.u
.legacy
.fmask
.slice_tile_max
);
3139 /* This must be set for fast clear to work without FMASK. */
3140 if (sctx
->chip_class
>= CIK
)
3141 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3142 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3143 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3146 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3147 sctx
->chip_class
>= VI
? 14 : 13);
3148 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3149 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3150 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3151 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3152 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3153 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3154 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3155 radeon_emit(cs
, cb_color_cmask
); /* CB_COLOR0_CMASK */
3156 radeon_emit(cs
, tex
->surface
.u
.legacy
.cmask_slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3157 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3158 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3159 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3160 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3162 if (sctx
->chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3163 radeon_emit(cs
, cb_dcc_base
);
3167 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3168 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3171 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3172 struct si_surface
*zb
= (struct si_surface
*)state
->zsbuf
;
3173 struct si_texture
*tex
= (struct si_texture
*)zb
->base
.texture
;
3175 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
3176 &tex
->buffer
, RADEON_USAGE_READWRITE
,
3177 zb
->base
.texture
->nr_samples
> 1 ?
3178 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3179 RADEON_PRIO_DEPTH_BUFFER
);
3181 if (sctx
->chip_class
>= GFX9
) {
3182 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3183 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3184 radeon_emit(cs
, S_028018_BASE_HI(zb
->db_htile_data_base
>> 32)); /* DB_HTILE_DATA_BASE_HI */
3185 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3187 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3188 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3189 S_028038_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3190 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3191 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3192 radeon_emit(cs
, S_028044_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_READ_BASE_HI */
3193 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3194 radeon_emit(cs
, S_02804C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_READ_BASE_HI */
3195 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3196 radeon_emit(cs
, S_028054_BASE_HI(zb
->db_depth_base
>> 32)); /* DB_Z_WRITE_BASE_HI */
3197 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3198 radeon_emit(cs
, S_02805C_BASE_HI(zb
->db_stencil_base
>> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3200 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3201 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3202 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3204 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3206 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3207 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3208 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3209 S_028040_ZRANGE_PRECISION(tex
->depth_clear_value
!= 0));
3210 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3211 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3212 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3213 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3214 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3215 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3216 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3219 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3220 radeon_emit(cs
, tex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3221 radeon_emit(cs
, fui(tex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3223 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3224 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3225 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3226 if (sctx
->chip_class
>= GFX9
)
3227 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3229 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3231 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3232 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3235 /* Framebuffer dimensions. */
3236 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3237 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3238 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3240 if (sctx
->screen
->dfsm_allowed
) {
3241 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3242 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3245 sctx
->framebuffer
.dirty_cbufs
= 0;
3246 sctx
->framebuffer
.dirty_zsbuf
= false;
3249 static void si_emit_msaa_sample_locs(struct si_context
*sctx
)
3251 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3252 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3253 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3254 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3256 /* Smoothing (only possible with nr_samples == 1) uses the same
3257 * sample locations as the MSAA it simulates.
3259 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3260 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3262 /* On Polaris, the small primitive filter uses the sample locations
3263 * even when MSAA is off, so we need to make sure they're set to 0.
3265 if (has_msaa_sample_loc_bug
)
3266 nr_samples
= MAX2(nr_samples
, 1);
3268 if (nr_samples
!= sctx
->sample_locs_num_samples
) {
3269 sctx
->sample_locs_num_samples
= nr_samples
;
3270 si_emit_sample_locations(cs
, nr_samples
);
3273 if (sctx
->family
>= CHIP_POLARIS10
) {
3274 unsigned small_prim_filter_cntl
=
3275 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3277 S_028830_LINE_FILTER_DISABLE(sctx
->family
<= CHIP_POLARIS12
);
3279 /* The alternative of setting sample locations to 0 would
3280 * require a DB flush to avoid Z errors, see
3281 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3283 if (has_msaa_sample_loc_bug
&&
3284 sctx
->framebuffer
.nr_samples
> 1 &&
3285 !rs
->multisample_enable
)
3286 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3288 radeon_opt_set_context_reg(sctx
,
3289 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3290 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3291 small_prim_filter_cntl
);
3294 /* The exclusion bits can be set to improve rasterization efficiency
3295 * if no sample lies on the pixel boundary (-8 sample offset).
3297 bool exclusion
= sctx
->chip_class
>= CIK
&&
3298 (!rs
->multisample_enable
|| nr_samples
!= 16);
3299 radeon_opt_set_context_reg(sctx
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3300 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL
,
3301 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3302 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3305 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3307 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3308 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3310 if (!sctx
->screen
->has_out_of_order_rast
)
3313 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3316 colormask
&= blend
->cb_target_enabled_4bit
;
3321 /* Conservative: No logic op. */
3322 if (colormask
&& blend
->logicop_enable
)
3325 struct si_dsa_order_invariance dsa_order_invariant
= {
3326 .zs
= true, .pass_set
= true, .pass_last
= false
3329 if (sctx
->framebuffer
.state
.zsbuf
) {
3330 struct si_texture
*zstex
=
3331 (struct si_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3332 bool has_stencil
= zstex
->surface
.has_stencil
;
3333 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3334 if (!dsa_order_invariant
.zs
)
3337 /* The set of PS invocations is always order invariant,
3338 * except when early Z/S tests are requested. */
3339 if (sctx
->ps_shader
.cso
&&
3340 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3341 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3342 !dsa_order_invariant
.pass_set
)
3345 if (sctx
->num_perfect_occlusion_queries
!= 0 &&
3346 !dsa_order_invariant
.pass_set
)
3353 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3356 /* Only commutative blending. */
3357 if (blendmask
& ~blend
->commutative_4bit
)
3360 if (!dsa_order_invariant
.pass_set
)
3364 if (colormask
& ~blendmask
) {
3365 if (!dsa_order_invariant
.pass_last
)
3372 static void si_emit_msaa_config(struct si_context
*sctx
)
3374 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3375 unsigned num_tile_pipes
= sctx
->screen
->info
.num_tile_pipes
;
3376 /* 33% faster rendering to linear color buffers */
3377 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3378 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3379 unsigned sc_mode_cntl_1
=
3380 S_028A4C_WALK_SIZE(dst_is_linear
) |
3381 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3382 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3383 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3384 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3386 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3387 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3388 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3389 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3390 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3391 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3392 unsigned db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3393 S_028804_INCOHERENT_EQAA_READS(1) |
3394 S_028804_INTERPOLATE_COMP_Z(1) |
3395 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3396 unsigned coverage_samples
, color_samples
, z_samples
;
3398 /* S: Coverage samples (up to 16x):
3399 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3400 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3402 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3403 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3404 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3405 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3406 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3409 * F: Color samples (up to 8x, must be <= coverage samples):
3410 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3411 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3413 * Can be anything between coverage and color samples:
3414 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3415 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3416 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3417 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3418 * # All are currently set the same as coverage samples.
3420 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3421 * flag for undefined color samples. A shader-based resolve must handle unknowns
3422 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3423 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3424 * useful. The CB resolve always drops unknowns.
3426 * Sensible AA configurations:
3427 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3428 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3429 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3430 * EQAA 8s 8z 8f = 8x MSAA
3431 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3432 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3433 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3434 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3435 * EQAA 4s 4z 4f = 4x MSAA
3436 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3437 * EQAA 2s 2z 2f = 2x MSAA
3439 if (sctx
->framebuffer
.nr_samples
> 1) {
3440 coverage_samples
= sctx
->framebuffer
.nr_samples
;
3441 color_samples
= sctx
->framebuffer
.nr_color_samples
;
3443 if (sctx
->framebuffer
.state
.zsbuf
) {
3444 z_samples
= sctx
->framebuffer
.state
.zsbuf
->texture
->nr_samples
;
3445 z_samples
= MAX2(1, z_samples
);
3447 z_samples
= coverage_samples
;
3449 } else if (sctx
->smoothing_enabled
) {
3450 coverage_samples
= color_samples
= z_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3452 coverage_samples
= color_samples
= z_samples
= 1;
3455 /* Required by OpenGL line rasterization.
3457 * TODO: We should also enable perpendicular endcaps for AA lines,
3458 * but that requires implementing line stippling in the pixel
3459 * shader. SC can only do line stippling with axis-aligned
3462 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3463 unsigned sc_aa_config
= 0;
3465 if (coverage_samples
> 1) {
3466 /* distance from the pixel center, indexed by log2(nr_samples) */
3467 static unsigned max_dist
[] = {
3474 unsigned log_samples
= util_logbase2(coverage_samples
);
3475 unsigned log_z_samples
= util_logbase2(z_samples
);
3476 unsigned ps_iter_samples
= si_get_ps_iter_samples(sctx
);
3477 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
3479 sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1);
3480 sc_aa_config
= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3481 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3482 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
);
3484 if (sctx
->framebuffer
.nr_samples
> 1) {
3485 db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
3486 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3487 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3488 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
3489 sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
3490 } else if (sctx
->smoothing_enabled
) {
3491 db_eqaa
|= S_028804_OVERRASTERIZATION_AMOUNT(log_samples
);
3495 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3496 radeon_opt_set_context_reg2(sctx
, R_028BDC_PA_SC_LINE_CNTL
,
3497 SI_TRACKED_PA_SC_LINE_CNTL
, sc_line_cntl
,
3499 /* R_028804_DB_EQAA */
3500 radeon_opt_set_context_reg(sctx
, R_028804_DB_EQAA
, SI_TRACKED_DB_EQAA
,
3502 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3503 radeon_opt_set_context_reg(sctx
, R_028A4C_PA_SC_MODE_CNTL_1
,
3504 SI_TRACKED_PA_SC_MODE_CNTL_1
, sc_mode_cntl_1
);
3506 /* GFX9: Flush DFSM when the AA mode changes. */
3507 if (sctx
->screen
->dfsm_allowed
) {
3508 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3509 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3513 void si_update_ps_iter_samples(struct si_context
*sctx
)
3515 if (sctx
->framebuffer
.nr_samples
> 1)
3516 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3517 if (sctx
->screen
->dpbb_allowed
)
3518 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3521 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3523 struct si_context
*sctx
= (struct si_context
*)ctx
;
3525 /* The hardware can only do sample shading with 2^n samples. */
3526 min_samples
= util_next_power_of_two(min_samples
);
3528 if (sctx
->ps_iter_samples
== min_samples
)
3531 sctx
->ps_iter_samples
= min_samples
;
3532 sctx
->do_update_shaders
= true;
3534 si_update_ps_iter_samples(sctx
);
3542 * Build the sampler view descriptor for a buffer texture.
3543 * @param state 256-bit descriptor; only the high 128 bits are filled in
3546 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3547 enum pipe_format format
,
3548 unsigned offset
, unsigned size
,
3551 const struct util_format_description
*desc
;
3554 unsigned num_records
;
3555 unsigned num_format
, data_format
;
3557 desc
= util_format_description(format
);
3558 first_non_void
= util_format_get_first_non_void_channel(format
);
3559 stride
= desc
->block
.bits
/ 8;
3560 num_format
= si_translate_buffer_numformat(&screen
->b
, desc
, first_non_void
);
3561 data_format
= si_translate_buffer_dataformat(&screen
->b
, desc
, first_non_void
);
3563 num_records
= size
/ stride
;
3564 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3566 /* The NUM_RECORDS field has a different meaning depending on the chip,
3567 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3570 * - If STRIDE == 0, it's in byte units.
3571 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3574 * - For SMEM and STRIDE == 0, it's in byte units.
3575 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3576 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3577 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3578 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3579 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3580 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3581 * That way the same descriptor can be used by both SMEM and VMEM.
3584 * - For SMEM and STRIDE == 0, it's in byte units.
3585 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3586 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3587 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3589 if (screen
->info
.chip_class
>= GFX9
)
3590 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3591 * from STRIDE to bytes. This works around it by setting
3592 * NUM_RECORDS to at least the size of one element, so that
3593 * the first element is readable when IDXEN == 0.
3595 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3596 * IDXEN is enforced?
3598 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3599 else if (screen
->info
.chip_class
== VI
)
3600 num_records
*= stride
;
3603 state
[5] = S_008F04_STRIDE(stride
);
3604 state
[6] = num_records
;
3605 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3606 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3607 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3608 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3609 S_008F0C_NUM_FORMAT(num_format
) |
3610 S_008F0C_DATA_FORMAT(data_format
);
3613 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3615 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3617 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3618 /* For the pre-defined border color values (white, opaque
3619 * black, transparent black), the only thing that matters is
3620 * that the alpha channel winds up in the correct place
3621 * (because the RGB channels are all the same) so either of
3622 * these enumerations will work.
3624 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3625 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3627 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3628 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3629 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3630 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3632 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3633 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3634 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3635 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3636 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3643 * Build the sampler view descriptor for a texture.
3646 si_make_texture_descriptor(struct si_screen
*screen
,
3647 struct si_texture
*tex
,
3649 enum pipe_texture_target target
,
3650 enum pipe_format pipe_format
,
3651 const unsigned char state_swizzle
[4],
3652 unsigned first_level
, unsigned last_level
,
3653 unsigned first_layer
, unsigned last_layer
,
3654 unsigned width
, unsigned height
, unsigned depth
,
3656 uint32_t *fmask_state
)
3658 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
3659 const struct util_format_description
*desc
;
3660 unsigned char swizzle
[4];
3662 unsigned num_format
, data_format
, type
, num_samples
;
3665 desc
= util_format_description(pipe_format
);
3667 num_samples
= desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
?
3668 MAX2(1, res
->nr_samples
) :
3669 MAX2(1, res
->nr_storage_samples
);
3671 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3672 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3673 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3674 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3676 switch (pipe_format
) {
3677 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3678 case PIPE_FORMAT_X32_S8X24_UINT
:
3679 case PIPE_FORMAT_X8Z24_UNORM
:
3680 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3682 case PIPE_FORMAT_X24S8_UINT
:
3684 * X24S8 is implemented as an 8_8_8_8 data format, to
3685 * fix texture gathers. This affects at least
3686 * GL45-CTS.texture_cube_map_array.sampling on VI.
3688 if (screen
->info
.chip_class
<= VI
)
3689 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3691 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3694 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3697 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3700 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3702 switch (pipe_format
) {
3703 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3704 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3707 if (first_non_void
< 0) {
3708 if (util_format_is_compressed(pipe_format
)) {
3709 switch (pipe_format
) {
3710 case PIPE_FORMAT_DXT1_SRGB
:
3711 case PIPE_FORMAT_DXT1_SRGBA
:
3712 case PIPE_FORMAT_DXT3_SRGBA
:
3713 case PIPE_FORMAT_DXT5_SRGBA
:
3714 case PIPE_FORMAT_BPTC_SRGBA
:
3715 case PIPE_FORMAT_ETC2_SRGB8
:
3716 case PIPE_FORMAT_ETC2_SRGB8A1
:
3717 case PIPE_FORMAT_ETC2_SRGBA8
:
3718 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3720 case PIPE_FORMAT_RGTC1_SNORM
:
3721 case PIPE_FORMAT_LATC1_SNORM
:
3722 case PIPE_FORMAT_RGTC2_SNORM
:
3723 case PIPE_FORMAT_LATC2_SNORM
:
3724 case PIPE_FORMAT_ETC2_R11_SNORM
:
3725 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3726 /* implies float, so use SNORM/UNORM to determine
3727 whether data is signed or not */
3728 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3729 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3732 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3735 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3736 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3738 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3740 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3741 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3743 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3745 switch (desc
->channel
[first_non_void
].type
) {
3746 case UTIL_FORMAT_TYPE_FLOAT
:
3747 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3749 case UTIL_FORMAT_TYPE_SIGNED
:
3750 if (desc
->channel
[first_non_void
].normalized
)
3751 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3752 else if (desc
->channel
[first_non_void
].pure_integer
)
3753 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3755 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3757 case UTIL_FORMAT_TYPE_UNSIGNED
:
3758 if (desc
->channel
[first_non_void
].normalized
)
3759 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3760 else if (desc
->channel
[first_non_void
].pure_integer
)
3761 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3763 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3768 data_format
= si_translate_texformat(&screen
->b
, pipe_format
, desc
, first_non_void
);
3769 if (data_format
== ~0) {
3773 /* S8 with Z32 HTILE needs a special format. */
3774 if (screen
->info
.chip_class
>= GFX9
&&
3775 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3776 tex
->tc_compatible_htile
)
3777 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3780 (res
->target
== PIPE_TEXTURE_CUBE
||
3781 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3782 (screen
->info
.chip_class
<= VI
&&
3783 res
->target
== PIPE_TEXTURE_3D
))) {
3784 /* For the purpose of shader images, treat cube maps and 3D
3785 * textures as 2D arrays. For 3D textures, the address
3786 * calculations for mipmaps are different, so we rely on the
3787 * caller to effectively disable mipmaps.
3789 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3791 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3793 type
= si_tex_dim(screen
, tex
, target
, num_samples
);
3796 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3798 depth
= res
->array_size
;
3799 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3800 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3801 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3802 depth
= res
->array_size
;
3803 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3804 depth
= res
->array_size
/ 6;
3807 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3808 S_008F14_NUM_FORMAT_GFX6(num_format
));
3809 state
[2] = (S_008F18_WIDTH(width
- 1) |
3810 S_008F18_HEIGHT(height
- 1) |
3811 S_008F18_PERF_MOD(4));
3812 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3813 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3814 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3815 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3816 S_008F1C_BASE_LEVEL(num_samples
> 1 ? 0 : first_level
) |
3817 S_008F1C_LAST_LEVEL(num_samples
> 1 ?
3818 util_logbase2(num_samples
) :
3820 S_008F1C_TYPE(type
));
3822 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3826 if (screen
->info
.chip_class
>= GFX9
) {
3827 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3829 /* Depth is the the last accessible layer on Gfx9.
3830 * The hw doesn't need to know the total number of layers.
3832 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3833 state
[4] |= S_008F20_DEPTH(depth
- 1);
3835 state
[4] |= S_008F20_DEPTH(last_layer
);
3837 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3838 state
[5] |= S_008F24_MAX_MIP(num_samples
> 1 ?
3839 util_logbase2(num_samples
) :
3840 tex
->buffer
.b
.b
.last_level
);
3842 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3843 state
[4] |= S_008F20_DEPTH(depth
- 1);
3844 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3847 if (tex
->dcc_offset
) {
3848 state
[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format
));
3850 /* The last dword is unused by hw. The shader uses it to clear
3851 * bits in the first dword of sampler state.
3853 if (screen
->info
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3854 if (first_level
== last_level
)
3855 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3857 state
[7] = 0xffffffff;
3861 /* Initialize the sampler view for FMASK. */
3862 if (tex
->surface
.fmask_size
) {
3863 uint32_t data_format
, num_format
;
3865 va
= tex
->buffer
.gpu_address
+ tex
->fmask_offset
;
3867 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3868 if (screen
->info
.chip_class
>= GFX9
) {
3869 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3870 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3872 num_format
= V_008F14_IMG_FMASK_8_2_1
;
3875 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3878 num_format
= V_008F14_IMG_FMASK_8_4_1
;
3881 num_format
= V_008F14_IMG_FMASK_8_4_2
;
3884 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3887 num_format
= V_008F14_IMG_FMASK_8_8_1
;
3890 num_format
= V_008F14_IMG_FMASK_16_8_2
;
3893 num_format
= V_008F14_IMG_FMASK_32_8_4
;
3896 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3899 num_format
= V_008F14_IMG_FMASK_16_16_1
;
3902 num_format
= V_008F14_IMG_FMASK_32_16_2
;
3905 num_format
= V_008F14_IMG_FMASK_64_16_4
;
3908 num_format
= V_008F14_IMG_FMASK_64_16_8
;
3911 unreachable("invalid nr_samples");
3914 switch (FMASK(res
->nr_samples
, res
->nr_storage_samples
)) {
3916 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1
;
3919 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3922 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1
;
3925 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2
;
3928 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3931 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1
;
3934 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2
;
3937 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4
;
3940 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3943 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1
;
3946 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2
;
3949 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4
;
3952 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8
;
3955 unreachable("invalid nr_samples");
3957 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3961 fmask_state
[0] = (va
>> 8) | tex
->surface
.fmask_tile_swizzle
;
3962 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3963 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3964 S_008F14_NUM_FORMAT_GFX6(num_format
);
3965 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3966 S_008F18_HEIGHT(height
- 1);
3967 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3968 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3969 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3970 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3971 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3973 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3977 if (screen
->info
.chip_class
>= GFX9
) {
3978 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3979 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3980 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3981 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3982 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3984 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->surface
.u
.legacy
.fmask
.tiling_index
);
3985 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3986 S_008F20_PITCH_GFX6(tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
- 1);
3987 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3993 * Create a sampler view.
3995 * @param ctx context
3996 * @param texture texture
3997 * @param state sampler view template
3998 * @param width0 width0 override (for compressed textures as int)
3999 * @param height0 height0 override (for compressed textures as int)
4000 * @param force_level set the base address to the level (for compressed textures)
4002 struct pipe_sampler_view
*
4003 si_create_sampler_view_custom(struct pipe_context
*ctx
,
4004 struct pipe_resource
*texture
,
4005 const struct pipe_sampler_view
*state
,
4006 unsigned width0
, unsigned height0
,
4007 unsigned force_level
)
4009 struct si_context
*sctx
= (struct si_context
*)ctx
;
4010 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
4011 struct si_texture
*tex
= (struct si_texture
*)texture
;
4012 unsigned base_level
, first_level
, last_level
;
4013 unsigned char state_swizzle
[4];
4014 unsigned height
, depth
, width
;
4015 unsigned last_layer
= state
->u
.tex
.last_layer
;
4016 enum pipe_format pipe_format
;
4017 const struct legacy_surf_level
*surflevel
;
4022 /* initialize base object */
4023 view
->base
= *state
;
4024 view
->base
.texture
= NULL
;
4025 view
->base
.reference
.count
= 1;
4026 view
->base
.context
= ctx
;
4029 pipe_resource_reference(&view
->base
.texture
, texture
);
4031 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
4032 state
->format
== PIPE_FORMAT_S8X24_UINT
||
4033 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
4034 state
->format
== PIPE_FORMAT_S8_UINT
)
4035 view
->is_stencil_sampler
= true;
4037 /* Buffer resource. */
4038 if (texture
->target
== PIPE_BUFFER
) {
4039 si_make_buffer_descriptor(sctx
->screen
,
4040 r600_resource(texture
),
4042 state
->u
.buf
.offset
,
4048 state_swizzle
[0] = state
->swizzle_r
;
4049 state_swizzle
[1] = state
->swizzle_g
;
4050 state_swizzle
[2] = state
->swizzle_b
;
4051 state_swizzle
[3] = state
->swizzle_a
;
4054 first_level
= state
->u
.tex
.first_level
;
4055 last_level
= state
->u
.tex
.last_level
;
4058 depth
= texture
->depth0
;
4060 if (sctx
->chip_class
<= VI
&& force_level
) {
4061 assert(force_level
== first_level
&&
4062 force_level
== last_level
);
4063 base_level
= force_level
;
4066 width
= u_minify(width
, force_level
);
4067 height
= u_minify(height
, force_level
);
4068 depth
= u_minify(depth
, force_level
);
4071 /* This is not needed if state trackers set last_layer correctly. */
4072 if (state
->target
== PIPE_TEXTURE_1D
||
4073 state
->target
== PIPE_TEXTURE_2D
||
4074 state
->target
== PIPE_TEXTURE_RECT
||
4075 state
->target
== PIPE_TEXTURE_CUBE
)
4076 last_layer
= state
->u
.tex
.first_layer
;
4078 /* Texturing with separate depth and stencil. */
4079 pipe_format
= state
->format
;
4081 /* Depth/stencil texturing sometimes needs separate texture. */
4082 if (tex
->is_depth
&& !si_can_sample_zs(tex
, view
->is_stencil_sampler
)) {
4083 if (!tex
->flushed_depth_texture
&&
4084 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
4085 pipe_resource_reference(&view
->base
.texture
, NULL
);
4090 assert(tex
->flushed_depth_texture
);
4092 /* Override format for the case where the flushed texture
4093 * contains only Z or only S.
4095 if (tex
->flushed_depth_texture
->buffer
.b
.b
.format
!= tex
->buffer
.b
.b
.format
)
4096 pipe_format
= tex
->flushed_depth_texture
->buffer
.b
.b
.format
;
4098 tex
= tex
->flushed_depth_texture
;
4101 surflevel
= tex
->surface
.u
.legacy
.level
;
4103 if (tex
->db_compatible
) {
4104 if (!view
->is_stencil_sampler
)
4105 pipe_format
= tex
->db_render_format
;
4107 switch (pipe_format
) {
4108 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
4109 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
4111 case PIPE_FORMAT_X8Z24_UNORM
:
4112 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
4113 /* Z24 is always stored like this for DB
4116 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
4118 case PIPE_FORMAT_X24S8_UINT
:
4119 case PIPE_FORMAT_S8X24_UINT
:
4120 case PIPE_FORMAT_X32_S8X24_UINT
:
4121 pipe_format
= PIPE_FORMAT_S8_UINT
;
4122 surflevel
= tex
->surface
.u
.legacy
.stencil_level
;
4128 view
->dcc_incompatible
=
4129 vi_dcc_formats_are_incompatible(texture
,
4130 state
->u
.tex
.first_level
,
4133 si_make_texture_descriptor(sctx
->screen
, tex
, true,
4134 state
->target
, pipe_format
, state_swizzle
,
4135 first_level
, last_level
,
4136 state
->u
.tex
.first_layer
, last_layer
,
4137 width
, height
, depth
,
4138 view
->state
, view
->fmask_state
);
4140 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
4142 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
4143 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
4144 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
4145 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
4146 view
->base_level_info
= &surflevel
[base_level
];
4147 view
->base_level
= base_level
;
4148 view
->block_width
= util_format_get_blockwidth(pipe_format
);
4152 static struct pipe_sampler_view
*
4153 si_create_sampler_view(struct pipe_context
*ctx
,
4154 struct pipe_resource
*texture
,
4155 const struct pipe_sampler_view
*state
)
4157 return si_create_sampler_view_custom(ctx
, texture
, state
,
4158 texture
? texture
->width0
: 0,
4159 texture
? texture
->height0
: 0, 0);
4162 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
4163 struct pipe_sampler_view
*state
)
4165 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
4167 pipe_resource_reference(&state
->texture
, NULL
);
4171 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
4173 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
4174 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
4176 (wrap
== PIPE_TEX_WRAP_CLAMP
||
4177 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
4180 static uint32_t si_translate_border_color(struct si_context
*sctx
,
4181 const struct pipe_sampler_state
*state
,
4182 const union pipe_color_union
*color
,
4185 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
4186 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
4188 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
4189 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
4190 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
4191 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4193 #define simple_border_types(elt) \
4195 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4196 color->elt[2] == 0 && color->elt[3] == 0) \
4197 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4198 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4199 color->elt[2] == 0 && color->elt[3] == 1) \
4200 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4201 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4202 color->elt[2] == 1 && color->elt[3] == 1) \
4203 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4207 simple_border_types(ui
);
4209 simple_border_types(f
);
4211 #undef simple_border_types
4215 /* Check if the border has been uploaded already. */
4216 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4217 if (memcmp(&sctx
->border_color_table
[i
], color
,
4218 sizeof(*color
)) == 0)
4221 if (i
>= SI_MAX_BORDER_COLORS
) {
4222 /* Getting 4096 unique border colors is very unlikely. */
4223 fprintf(stderr
, "radeonsi: The border color table is full. "
4224 "Any new border colors will be just black. "
4225 "Please file a bug.\n");
4226 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4229 if (i
== sctx
->border_color_count
) {
4230 /* Upload a new border color. */
4231 memcpy(&sctx
->border_color_table
[i
], color
,
4233 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4234 color
, sizeof(*color
));
4235 sctx
->border_color_count
++;
4238 return S_008F3C_BORDER_COLOR_PTR(i
) |
4239 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4242 static inline int S_FIXED(float value
, unsigned frac_bits
)
4244 return value
* (1 << frac_bits
);
4247 static inline unsigned si_tex_filter(unsigned filter
, unsigned max_aniso
)
4249 if (filter
== PIPE_TEX_FILTER_LINEAR
)
4250 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4251 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR
;
4253 return max_aniso
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4254 : V_008F38_SQ_TEX_XY_FILTER_POINT
;
4257 static inline unsigned si_tex_aniso_filter(unsigned filter
)
4270 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4271 const struct pipe_sampler_state
*state
)
4273 struct si_context
*sctx
= (struct si_context
*)ctx
;
4274 struct si_screen
*sscreen
= sctx
->screen
;
4275 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4276 unsigned max_aniso
= sscreen
->force_aniso
>= 0 ? sscreen
->force_aniso
4277 : state
->max_anisotropy
;
4278 unsigned max_aniso_ratio
= si_tex_aniso_filter(max_aniso
);
4279 union pipe_color_union clamped_border_color
;
4286 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4288 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4289 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4290 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4291 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4292 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4293 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4294 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4295 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4296 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4297 S_008F30_COMPAT_MODE(sctx
->chip_class
>= VI
));
4298 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4299 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4300 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4301 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4302 S_008F38_XY_MAG_FILTER(si_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4303 S_008F38_XY_MIN_FILTER(si_tex_filter(state
->min_img_filter
, max_aniso
)) |
4304 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4305 S_008F38_MIP_POINT_PRECLAMP(0) |
4306 S_008F38_DISABLE_LSB_CEIL(sctx
->chip_class
<= VI
) |
4307 S_008F38_FILTER_PREC_FIX(1) |
4308 S_008F38_ANISO_OVERRIDE(sctx
->chip_class
>= VI
));
4309 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4311 /* Create sampler resource for integer textures. */
4312 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4313 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4315 /* Create sampler resource for upgraded depth textures. */
4316 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4318 for (unsigned i
= 0; i
< 4; ++i
) {
4319 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4320 * when the border color is 1.0. */
4321 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4324 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4325 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4327 rstate
->upgraded_depth_val
[3] =
4328 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4329 S_008F3C_UPGRADED_DEPTH(1);
4334 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4336 struct si_context
*sctx
= (struct si_context
*)ctx
;
4338 if (sctx
->sample_mask
== (uint16_t)sample_mask
)
4341 sctx
->sample_mask
= sample_mask
;
4342 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.sample_mask
);
4345 static void si_emit_sample_mask(struct si_context
*sctx
)
4347 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4348 unsigned mask
= sctx
->sample_mask
;
4350 /* Needed for line and polygon smoothing as well as for the Polaris
4351 * small primitive filter. We expect the state tracker to take care of
4354 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4355 (mask
& 1 && sctx
->blitter
->running
));
4357 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4358 radeon_emit(cs
, mask
| (mask
<< 16));
4359 radeon_emit(cs
, mask
| (mask
<< 16));
4362 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4365 struct si_sampler_state
*s
= state
;
4367 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4374 * Vertex elements & buffers
4377 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4379 const struct pipe_vertex_element
*elements
)
4381 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4382 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4383 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4386 assert(count
<= SI_MAX_ATTRIBS
);
4391 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4393 for (i
= 0; i
< count
; ++i
) {
4394 const struct util_format_description
*desc
;
4395 const struct util_format_channel_description
*channel
;
4396 unsigned data_format
, num_format
;
4398 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4399 unsigned char swizzle
[4];
4401 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4406 if (elements
[i
].instance_divisor
) {
4407 v
->uses_instance_divisors
= true;
4408 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4410 if (v
->instance_divisors
[i
] == 1)
4411 v
->instance_divisor_is_one
|= 1u << i
;
4413 v
->instance_divisor_is_fetched
|= 1u << i
;
4416 if (!used
[vbo_index
]) {
4417 v
->first_vb_use_mask
|= 1 << i
;
4418 used
[vbo_index
] = true;
4421 desc
= util_format_description(elements
[i
].src_format
);
4422 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4423 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4424 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4425 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4426 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4428 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4429 v
->src_offset
[i
] = elements
[i
].src_offset
;
4430 v
->vertex_buffer_index
[i
] = vbo_index
;
4432 /* The hardware always treats the 2-bit alpha channel as
4433 * unsigned, so a shader workaround is needed. The affected
4434 * chips are VI and older except Stoney (GFX8.1).
4436 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4437 sscreen
->info
.chip_class
<= VI
&&
4438 sscreen
->info
.family
!= CHIP_STONEY
) {
4439 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4440 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4441 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4442 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4443 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4444 /* This isn't actually used in OpenGL. */
4445 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4447 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4448 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4449 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4451 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4452 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4453 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4454 if (channel
->normalized
) {
4455 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4456 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4458 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4460 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4462 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4463 if (channel
->normalized
) {
4464 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4465 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4467 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4469 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4472 } else if (channel
&& channel
->size
== 64 &&
4473 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4474 switch (desc
->nr_channels
) {
4477 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4478 swizzle
[0] = PIPE_SWIZZLE_X
;
4479 swizzle
[1] = PIPE_SWIZZLE_Y
;
4480 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4481 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4484 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4485 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4486 swizzle
[1] = PIPE_SWIZZLE_Y
;
4487 swizzle
[2] = PIPE_SWIZZLE_0
;
4488 swizzle
[3] = PIPE_SWIZZLE_0
;
4491 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4492 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4493 swizzle
[1] = PIPE_SWIZZLE_Y
;
4494 swizzle
[2] = PIPE_SWIZZLE_Z
;
4495 swizzle
[3] = PIPE_SWIZZLE_W
;
4500 } else if (channel
&& desc
->nr_channels
== 3) {
4501 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4503 if (channel
->size
== 8) {
4504 if (channel
->pure_integer
)
4505 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4507 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4508 } else if (channel
->size
== 16) {
4509 if (channel
->pure_integer
)
4510 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4512 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4516 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4517 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4518 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4519 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4520 S_008F0C_NUM_FORMAT(num_format
) |
4521 S_008F0C_DATA_FORMAT(data_format
);
4526 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4528 struct si_context
*sctx
= (struct si_context
*)ctx
;
4529 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4530 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4532 sctx
->vertex_elements
= v
;
4533 sctx
->vertex_buffers_dirty
= true;
4537 old
->count
!= v
->count
||
4538 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4539 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4540 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4541 sctx
->do_update_shaders
= true;
4543 if (v
&& v
->instance_divisor_is_fetched
) {
4544 struct pipe_constant_buffer cb
;
4547 cb
.user_buffer
= v
->instance_divisors
;
4548 cb
.buffer_offset
= 0;
4549 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4550 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4554 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4556 struct si_context
*sctx
= (struct si_context
*)ctx
;
4558 if (sctx
->vertex_elements
== state
)
4559 sctx
->vertex_elements
= NULL
;
4563 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4564 unsigned start_slot
, unsigned count
,
4565 const struct pipe_vertex_buffer
*buffers
)
4567 struct si_context
*sctx
= (struct si_context
*)ctx
;
4568 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4571 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4574 for (i
= 0; i
< count
; i
++) {
4575 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4576 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4577 struct pipe_resource
*buf
= src
->buffer
.resource
;
4579 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4580 dsti
->buffer_offset
= src
->buffer_offset
;
4581 dsti
->stride
= src
->stride
;
4582 si_context_add_resource_size(sctx
, buf
);
4584 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4587 for (i
= 0; i
< count
; i
++) {
4588 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4591 sctx
->vertex_buffers_dirty
= true;
4598 static void si_set_tess_state(struct pipe_context
*ctx
,
4599 const float default_outer_level
[4],
4600 const float default_inner_level
[2])
4602 struct si_context
*sctx
= (struct si_context
*)ctx
;
4603 struct pipe_constant_buffer cb
;
4606 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4607 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4610 cb
.user_buffer
= NULL
;
4611 cb
.buffer_size
= sizeof(array
);
4613 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4614 (void*)array
, sizeof(array
),
4617 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4618 pipe_resource_reference(&cb
.buffer
, NULL
);
4621 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4623 struct si_context
*sctx
= (struct si_context
*)ctx
;
4625 si_update_fb_dirtiness_after_rendering(sctx
);
4627 /* Multisample surfaces are flushed in si_decompress_textures. */
4628 if (sctx
->framebuffer
.uncompressed_cb_mask
)
4629 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4630 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4633 /* This only ensures coherency for shader image/buffer stores. */
4634 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4636 struct si_context
*sctx
= (struct si_context
*)ctx
;
4638 /* Subsequent commands must wait for all shader invocations to
4640 sctx
->flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4641 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4643 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4644 sctx
->flags
|= SI_CONTEXT_INV_SMEM_L1
|
4645 SI_CONTEXT_INV_VMEM_L1
;
4647 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4648 PIPE_BARRIER_SHADER_BUFFER
|
4649 PIPE_BARRIER_TEXTURE
|
4650 PIPE_BARRIER_IMAGE
|
4651 PIPE_BARRIER_STREAMOUT_BUFFER
|
4652 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4653 /* As far as I can tell, L1 contents are written back to L2
4654 * automatically at end of shader, but the contents of other
4655 * L1 caches might still be stale. */
4656 sctx
->flags
|= SI_CONTEXT_INV_VMEM_L1
;
4659 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4660 /* Indices are read through TC L2 since VI.
4663 if (sctx
->screen
->info
.chip_class
<= CIK
)
4664 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4667 /* MSAA color, any depth and any stencil are flushed in
4668 * si_decompress_textures when needed.
4670 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4671 sctx
->framebuffer
.uncompressed_cb_mask
) {
4672 sctx
->flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4674 if (sctx
->chip_class
<= VI
)
4675 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4678 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4679 if (sctx
->screen
->info
.chip_class
<= VI
&&
4680 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4681 sctx
->flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4684 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4686 struct pipe_blend_state blend
;
4688 memset(&blend
, 0, sizeof(blend
));
4689 blend
.independent_blend_enable
= true;
4690 blend
.rt
[0].colormask
= 0xf;
4691 return si_create_blend_state_mode(&sctx
->b
, &blend
, mode
);
4694 static void si_init_config(struct si_context
*sctx
);
4696 void si_init_state_functions(struct si_context
*sctx
)
4698 sctx
->atoms
.s
.framebuffer
.emit
= si_emit_framebuffer_state
;
4699 sctx
->atoms
.s
.msaa_sample_locs
.emit
= si_emit_msaa_sample_locs
;
4700 sctx
->atoms
.s
.db_render_state
.emit
= si_emit_db_render_state
;
4701 sctx
->atoms
.s
.dpbb_state
.emit
= si_emit_dpbb_state
;
4702 sctx
->atoms
.s
.msaa_config
.emit
= si_emit_msaa_config
;
4703 sctx
->atoms
.s
.sample_mask
.emit
= si_emit_sample_mask
;
4704 sctx
->atoms
.s
.cb_render_state
.emit
= si_emit_cb_render_state
;
4705 sctx
->atoms
.s
.blend_color
.emit
= si_emit_blend_color
;
4706 sctx
->atoms
.s
.clip_regs
.emit
= si_emit_clip_regs
;
4707 sctx
->atoms
.s
.clip_state
.emit
= si_emit_clip_state
;
4708 sctx
->atoms
.s
.stencil_ref
.emit
= si_emit_stencil_ref
;
4710 sctx
->b
.create_blend_state
= si_create_blend_state
;
4711 sctx
->b
.bind_blend_state
= si_bind_blend_state
;
4712 sctx
->b
.delete_blend_state
= si_delete_blend_state
;
4713 sctx
->b
.set_blend_color
= si_set_blend_color
;
4715 sctx
->b
.create_rasterizer_state
= si_create_rs_state
;
4716 sctx
->b
.bind_rasterizer_state
= si_bind_rs_state
;
4717 sctx
->b
.delete_rasterizer_state
= si_delete_rs_state
;
4719 sctx
->b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4720 sctx
->b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4721 sctx
->b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4723 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4724 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4725 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4726 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4727 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4729 sctx
->b
.set_clip_state
= si_set_clip_state
;
4730 sctx
->b
.set_stencil_ref
= si_set_stencil_ref
;
4732 sctx
->b
.set_framebuffer_state
= si_set_framebuffer_state
;
4734 sctx
->b
.create_sampler_state
= si_create_sampler_state
;
4735 sctx
->b
.delete_sampler_state
= si_delete_sampler_state
;
4737 sctx
->b
.create_sampler_view
= si_create_sampler_view
;
4738 sctx
->b
.sampler_view_destroy
= si_sampler_view_destroy
;
4740 sctx
->b
.set_sample_mask
= si_set_sample_mask
;
4742 sctx
->b
.create_vertex_elements_state
= si_create_vertex_elements
;
4743 sctx
->b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4744 sctx
->b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4745 sctx
->b
.set_vertex_buffers
= si_set_vertex_buffers
;
4747 sctx
->b
.texture_barrier
= si_texture_barrier
;
4748 sctx
->b
.memory_barrier
= si_memory_barrier
;
4749 sctx
->b
.set_min_samples
= si_set_min_samples
;
4750 sctx
->b
.set_tess_state
= si_set_tess_state
;
4752 sctx
->b
.set_active_query_state
= si_set_active_query_state
;
4754 sctx
->b
.draw_vbo
= si_draw_vbo
;
4756 si_init_config(sctx
);
4759 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4761 sscreen
->b
.is_format_supported
= si_is_format_supported
;
4764 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4765 struct si_pm4_state
*pm4
, unsigned value
)
4767 unsigned reg
= sctx
->chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4768 R_00802C_GRBM_GFX_INDEX
;
4769 si_pm4_set_reg(pm4
, reg
, value
);
4772 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4773 struct si_pm4_state
*pm4
, unsigned se
)
4775 assert(se
== ~0 || se
< sctx
->screen
->info
.max_se
);
4776 si_set_grbm_gfx_index(sctx
, pm4
,
4777 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4778 S_030800_SE_INDEX(se
)) |
4779 S_030800_SH_BROADCAST_WRITES(1) |
4780 S_030800_INSTANCE_BROADCAST_WRITES(1));
4784 si_write_harvested_raster_configs(struct si_context
*sctx
,
4785 struct si_pm4_state
*pm4
,
4786 unsigned raster_config
,
4787 unsigned raster_config_1
)
4789 unsigned num_se
= MAX2(sctx
->screen
->info
.max_se
, 1);
4790 unsigned raster_config_se
[4];
4793 ac_get_harvested_configs(&sctx
->screen
->info
,
4798 for (se
= 0; se
< num_se
; se
++) {
4799 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4800 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
[se
]);
4802 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4804 if (sctx
->chip_class
>= CIK
) {
4805 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4809 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4811 struct si_screen
*sscreen
= sctx
->screen
;
4812 unsigned num_rb
= MIN2(sscreen
->info
.num_render_backends
, 16);
4813 unsigned rb_mask
= sscreen
->info
.enabled_rb_mask
;
4814 unsigned raster_config
= sscreen
->pa_sc_raster_config
;
4815 unsigned raster_config_1
= sscreen
->pa_sc_raster_config_1
;
4817 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4818 /* Always use the default config when all backends are enabled
4819 * (or when we failed to determine the enabled backends).
4821 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4823 if (sctx
->chip_class
>= CIK
)
4824 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4827 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4831 static void si_init_config(struct si_context
*sctx
)
4833 struct si_screen
*sscreen
= sctx
->screen
;
4834 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4835 bool has_clear_state
= sscreen
->has_clear_state
;
4836 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4838 /* Only SI can disable CLEAR_STATE for now. */
4839 assert(has_clear_state
|| sscreen
->info
.chip_class
== SI
);
4844 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4845 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4846 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4847 si_pm4_cmd_end(pm4
, false);
4849 if (has_clear_state
) {
4850 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4851 si_pm4_cmd_add(pm4
, 0);
4852 si_pm4_cmd_end(pm4
, false);
4855 if (sctx
->chip_class
<= VI
)
4856 si_set_raster_config(sctx
, pm4
);
4858 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4859 if (!has_clear_state
)
4860 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4862 /* FIXME calculate these values somehow ??? */
4863 if (sctx
->chip_class
<= VI
) {
4864 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4865 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4868 if (!has_clear_state
) {
4869 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4870 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4871 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4874 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4875 if (!has_clear_state
)
4876 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4877 if (sctx
->chip_class
< CIK
)
4878 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4879 S_008A14_CLIP_VTX_REORDER_ENA(1));
4881 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4882 * I don't know why. Deduced by trial and error.
4884 if (sctx
->chip_class
<= CIK
) {
4885 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4886 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4887 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4888 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4889 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4890 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4891 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4892 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4895 if (!has_clear_state
) {
4896 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4897 S_028230_ER_TRI(0xA) |
4898 S_028230_ER_POINT(0xA) |
4899 S_028230_ER_RECT(0xA) |
4900 /* Required by DX10_DIAMOND_TEST_ENA: */
4901 S_028230_ER_LINE_LR(0x1A) |
4902 S_028230_ER_LINE_RL(0x26) |
4903 S_028230_ER_LINE_TB(0xA) |
4904 S_028230_ER_LINE_BT(0xA));
4905 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4906 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4907 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4908 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4909 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4912 if (sctx
->chip_class
>= GFX9
) {
4913 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4914 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4915 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4917 /* These registers, when written, also overwrite the CLEAR_STATE
4918 * context, so we can't rely on CLEAR_STATE setting them.
4919 * It would be an issue if there was another UMD changing them.
4921 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4922 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4923 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4926 if (sctx
->chip_class
>= CIK
) {
4927 if (sctx
->chip_class
>= GFX9
) {
4928 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4929 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4931 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4932 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4933 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4934 S_00B41C_WAVE_LIMIT(0x3F));
4935 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
4936 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4938 /* If this is 0, Bonaire can hang even if GS isn't being used.
4939 * Other chips are unaffected. These are suboptimal values,
4940 * but we don't use on-chip GS.
4942 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4943 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4944 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4946 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
4947 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4949 /* Compute LATE_ALLOC_VS.LIMIT. */
4950 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
4951 unsigned late_alloc_limit
; /* The limit is per SH. */
4953 if (sctx
->family
== CHIP_KABINI
) {
4954 late_alloc_limit
= 0; /* Potential hang on Kabini. */
4955 } else if (num_cu_per_sh
<= 4) {
4956 /* Too few available compute units per SH. Disallowing
4957 * VS to run on one CU could hurt us more than late VS
4958 * allocation would help.
4960 * 2 is the highest safe number that allows us to keep
4963 late_alloc_limit
= 2;
4965 /* This is a good initial value, allowing 1 late_alloc
4966 * wave per SIMD on num_cu - 2.
4968 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
4970 /* The limit is 0-based, so 0 means 1. */
4971 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
4972 late_alloc_limit
-= 1;
4975 /* VS can't execute on one CU if the limit is > 2. */
4976 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
4977 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
4978 S_00B118_WAVE_LIMIT(0x3F));
4979 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
4980 S_00B11C_LIMIT(late_alloc_limit
));
4981 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
4982 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4985 if (sctx
->chip_class
>= VI
) {
4986 unsigned vgt_tess_distribution
;
4988 vgt_tess_distribution
=
4989 S_028B50_ACCUM_ISOLINE(32) |
4990 S_028B50_ACCUM_TRI(11) |
4991 S_028B50_ACCUM_QUAD(11) |
4992 S_028B50_DONUT_SPLIT(16);
4994 /* Testing with Unigine Heaven extreme tesselation yielded best results
4995 * with TRAP_SPLIT = 3.
4997 if (sctx
->family
== CHIP_FIJI
||
4998 sctx
->family
>= CHIP_POLARIS10
)
4999 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5001 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5002 } else if (!has_clear_state
) {
5003 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5004 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5007 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5008 if (sctx
->chip_class
>= CIK
) {
5009 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
,
5010 S_028084_ADDRESS(border_color_va
>> 40));
5012 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5013 RADEON_PRIO_BORDER_COLORS
);
5015 if (sctx
->chip_class
>= GFX9
) {
5016 unsigned num_se
= sscreen
->info
.max_se
;
5017 unsigned pc_lines
= 0;
5019 switch (sctx
->family
) {
5032 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5033 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5034 S_028C48_MAX_PRIM_PER_BATCH(1023));
5035 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5036 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5037 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5040 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5041 sctx
->init_config
= pm4
;