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radeonsi: don't change pipe_resource in resource_copy_region
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "sid.h"
30 #include "radeon/r600_cs.h"
31
32 #include "util/u_format.h"
33 #include "util/u_format_s3tc.h"
34 #include "util/u_memory.h"
35 #include "util/u_pstipple.h"
36
37 static void si_init_atom(struct r600_atom *atom, struct r600_atom **list_elem,
38 void (*emit)(struct si_context *ctx, struct r600_atom *state),
39 unsigned num_dw)
40 {
41 atom->emit = (void*)emit;
42 atom->num_dw = num_dw;
43 atom->dirty = false;
44 *list_elem = atom;
45 }
46
47 unsigned si_array_mode(unsigned mode)
48 {
49 switch (mode) {
50 case RADEON_SURF_MODE_LINEAR_ALIGNED:
51 return V_009910_ARRAY_LINEAR_ALIGNED;
52 case RADEON_SURF_MODE_1D:
53 return V_009910_ARRAY_1D_TILED_THIN1;
54 case RADEON_SURF_MODE_2D:
55 return V_009910_ARRAY_2D_TILED_THIN1;
56 default:
57 case RADEON_SURF_MODE_LINEAR:
58 return V_009910_ARRAY_LINEAR_GENERAL;
59 }
60 }
61
62 uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
63 {
64 if (sscreen->b.chip_class == CIK &&
65 sscreen->b.info.cik_macrotile_mode_array_valid) {
66 unsigned index, tileb;
67
68 tileb = 8 * 8 * tex->surface.bpe;
69 tileb = MIN2(tex->surface.tile_split, tileb);
70
71 for (index = 0; tileb > 64; index++) {
72 tileb >>= 1;
73 }
74 assert(index < 16);
75
76 return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) & 0x3;
77 }
78
79 if (sscreen->b.chip_class == SI &&
80 sscreen->b.info.si_tile_mode_array_valid) {
81 /* Don't use stencil_tiling_index, because num_banks is always
82 * read from the depth mode. */
83 unsigned tile_mode_index = tex->surface.tiling_index[0];
84 assert(tile_mode_index < 32);
85
86 return G_009910_NUM_BANKS(sscreen->b.info.si_tile_mode_array[tile_mode_index]);
87 }
88
89 /* The old way. */
90 switch (sscreen->b.tiling_info.num_banks) {
91 case 2:
92 return V_02803C_ADDR_SURF_2_BANK;
93 case 4:
94 return V_02803C_ADDR_SURF_4_BANK;
95 case 8:
96 default:
97 return V_02803C_ADDR_SURF_8_BANK;
98 case 16:
99 return V_02803C_ADDR_SURF_16_BANK;
100 }
101 }
102
103 unsigned cik_tile_split(unsigned tile_split)
104 {
105 switch (tile_split) {
106 case 64:
107 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
108 break;
109 case 128:
110 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
111 break;
112 case 256:
113 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
114 break;
115 case 512:
116 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
117 break;
118 default:
119 case 1024:
120 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
121 break;
122 case 2048:
123 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
124 break;
125 case 4096:
126 tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
127 break;
128 }
129 return tile_split;
130 }
131
132 unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
133 {
134 switch (macro_tile_aspect) {
135 default:
136 case 1:
137 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
138 break;
139 case 2:
140 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
141 break;
142 case 4:
143 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
144 break;
145 case 8:
146 macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
147 break;
148 }
149 return macro_tile_aspect;
150 }
151
152 unsigned cik_bank_wh(unsigned bankwh)
153 {
154 switch (bankwh) {
155 default:
156 case 1:
157 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
158 break;
159 case 2:
160 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
161 break;
162 case 4:
163 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
164 break;
165 case 8:
166 bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
167 break;
168 }
169 return bankwh;
170 }
171
172 unsigned cik_db_pipe_config(struct si_screen *sscreen, unsigned tile_mode)
173 {
174 if (sscreen->b.info.si_tile_mode_array_valid) {
175 uint32_t gb_tile_mode = sscreen->b.info.si_tile_mode_array[tile_mode];
176
177 return G_009910_PIPE_CONFIG(gb_tile_mode);
178 }
179
180 /* This is probably broken for a lot of chips, but it's only used
181 * if the kernel cannot return the tile mode array for CIK. */
182 switch (sscreen->b.info.r600_num_tile_pipes) {
183 case 16:
184 return V_02803C_X_ADDR_SURF_P16_32X32_16X16;
185 case 8:
186 return V_02803C_X_ADDR_SURF_P8_32X32_16X16;
187 case 4:
188 default:
189 if (sscreen->b.info.r600_num_backends == 4)
190 return V_02803C_X_ADDR_SURF_P4_16X16;
191 else
192 return V_02803C_X_ADDR_SURF_P4_8X16;
193 case 2:
194 return V_02803C_ADDR_SURF_P2;
195 }
196 }
197
198 static unsigned si_map_swizzle(unsigned swizzle)
199 {
200 switch (swizzle) {
201 case UTIL_FORMAT_SWIZZLE_Y:
202 return V_008F0C_SQ_SEL_Y;
203 case UTIL_FORMAT_SWIZZLE_Z:
204 return V_008F0C_SQ_SEL_Z;
205 case UTIL_FORMAT_SWIZZLE_W:
206 return V_008F0C_SQ_SEL_W;
207 case UTIL_FORMAT_SWIZZLE_0:
208 return V_008F0C_SQ_SEL_0;
209 case UTIL_FORMAT_SWIZZLE_1:
210 return V_008F0C_SQ_SEL_1;
211 default: /* UTIL_FORMAT_SWIZZLE_X */
212 return V_008F0C_SQ_SEL_X;
213 }
214 }
215
216 static uint32_t S_FIXED(float value, uint32_t frac_bits)
217 {
218 return value * (1 << frac_bits);
219 }
220
221 /* 12.4 fixed-point */
222 static unsigned si_pack_float_12p4(float x)
223 {
224 return x <= 0 ? 0 :
225 x >= 4096 ? 0xffff : x * 16;
226 }
227
228 /*
229 * Inferred framebuffer and blender state.
230 *
231 * One of the reasons this must be derived from the framebuffer state is that:
232 * - The blend state mask is 0xf most of the time.
233 * - The COLOR1 format isn't INVALID because of possible dual-source blending,
234 * so COLOR1 is enabled pretty much all the time.
235 * So CB_TARGET_MASK is the only register that can disable COLOR1.
236 */
237 static void si_update_fb_blend_state(struct si_context *sctx)
238 {
239 struct si_pm4_state *pm4;
240 struct si_state_blend *blend = sctx->queued.named.blend;
241 uint32_t mask = 0, i;
242
243 if (blend == NULL)
244 return;
245
246 pm4 = CALLOC_STRUCT(si_pm4_state);
247 if (pm4 == NULL)
248 return;
249
250 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++)
251 if (sctx->framebuffer.state.cbufs[i])
252 mask |= 0xf << (4*i);
253 mask &= blend->cb_target_mask;
254
255 si_pm4_set_reg(pm4, R_028238_CB_TARGET_MASK, mask);
256 si_pm4_set_state(sctx, fb_blend, pm4);
257 }
258
259 /*
260 * Blender functions
261 */
262
263 static uint32_t si_translate_blend_function(int blend_func)
264 {
265 switch (blend_func) {
266 case PIPE_BLEND_ADD:
267 return V_028780_COMB_DST_PLUS_SRC;
268 case PIPE_BLEND_SUBTRACT:
269 return V_028780_COMB_SRC_MINUS_DST;
270 case PIPE_BLEND_REVERSE_SUBTRACT:
271 return V_028780_COMB_DST_MINUS_SRC;
272 case PIPE_BLEND_MIN:
273 return V_028780_COMB_MIN_DST_SRC;
274 case PIPE_BLEND_MAX:
275 return V_028780_COMB_MAX_DST_SRC;
276 default:
277 R600_ERR("Unknown blend function %d\n", blend_func);
278 assert(0);
279 break;
280 }
281 return 0;
282 }
283
284 static uint32_t si_translate_blend_factor(int blend_fact)
285 {
286 switch (blend_fact) {
287 case PIPE_BLENDFACTOR_ONE:
288 return V_028780_BLEND_ONE;
289 case PIPE_BLENDFACTOR_SRC_COLOR:
290 return V_028780_BLEND_SRC_COLOR;
291 case PIPE_BLENDFACTOR_SRC_ALPHA:
292 return V_028780_BLEND_SRC_ALPHA;
293 case PIPE_BLENDFACTOR_DST_ALPHA:
294 return V_028780_BLEND_DST_ALPHA;
295 case PIPE_BLENDFACTOR_DST_COLOR:
296 return V_028780_BLEND_DST_COLOR;
297 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
298 return V_028780_BLEND_SRC_ALPHA_SATURATE;
299 case PIPE_BLENDFACTOR_CONST_COLOR:
300 return V_028780_BLEND_CONSTANT_COLOR;
301 case PIPE_BLENDFACTOR_CONST_ALPHA:
302 return V_028780_BLEND_CONSTANT_ALPHA;
303 case PIPE_BLENDFACTOR_ZERO:
304 return V_028780_BLEND_ZERO;
305 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
306 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
307 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
308 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
309 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
310 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
311 case PIPE_BLENDFACTOR_INV_DST_COLOR:
312 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
313 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
314 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
315 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
316 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
317 case PIPE_BLENDFACTOR_SRC1_COLOR:
318 return V_028780_BLEND_SRC1_COLOR;
319 case PIPE_BLENDFACTOR_SRC1_ALPHA:
320 return V_028780_BLEND_SRC1_ALPHA;
321 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
322 return V_028780_BLEND_INV_SRC1_COLOR;
323 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
324 return V_028780_BLEND_INV_SRC1_ALPHA;
325 default:
326 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
327 assert(0);
328 break;
329 }
330 return 0;
331 }
332
333 static void *si_create_blend_state_mode(struct pipe_context *ctx,
334 const struct pipe_blend_state *state,
335 unsigned mode)
336 {
337 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
338 struct si_pm4_state *pm4 = &blend->pm4;
339
340 uint32_t color_control = 0;
341
342 if (blend == NULL)
343 return NULL;
344
345 blend->alpha_to_one = state->alpha_to_one;
346
347 if (state->logicop_enable) {
348 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
349 } else {
350 color_control |= S_028808_ROP3(0xcc);
351 }
352
353 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
354 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
355 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
356 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
357 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
358 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
359
360 blend->cb_target_mask = 0;
361 for (int i = 0; i < 8; i++) {
362 /* state->rt entries > 0 only written if independent blending */
363 const int j = state->independent_blend_enable ? i : 0;
364
365 unsigned eqRGB = state->rt[j].rgb_func;
366 unsigned srcRGB = state->rt[j].rgb_src_factor;
367 unsigned dstRGB = state->rt[j].rgb_dst_factor;
368 unsigned eqA = state->rt[j].alpha_func;
369 unsigned srcA = state->rt[j].alpha_src_factor;
370 unsigned dstA = state->rt[j].alpha_dst_factor;
371
372 unsigned blend_cntl = 0;
373
374 /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
375 blend->cb_target_mask |= state->rt[j].colormask << (4 * i);
376
377 if (!state->rt[j].blend_enable) {
378 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
379 continue;
380 }
381
382 blend_cntl |= S_028780_ENABLE(1);
383 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
384 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
385 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
386
387 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
388 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
389 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
390 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
391 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
392 }
393 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
394 }
395
396 if (blend->cb_target_mask) {
397 color_control |= S_028808_MODE(mode);
398 } else {
399 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
400 }
401 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
402
403 return blend;
404 }
405
406 static void *si_create_blend_state(struct pipe_context *ctx,
407 const struct pipe_blend_state *state)
408 {
409 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
410 }
411
412 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
413 {
414 struct si_context *sctx = (struct si_context *)ctx;
415 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
416 si_update_fb_blend_state(sctx);
417 }
418
419 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
420 {
421 struct si_context *sctx = (struct si_context *)ctx;
422 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
423 }
424
425 static void si_set_blend_color(struct pipe_context *ctx,
426 const struct pipe_blend_color *state)
427 {
428 struct si_context *sctx = (struct si_context *)ctx;
429 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
430
431 if (pm4 == NULL)
432 return;
433
434 si_pm4_set_reg(pm4, R_028414_CB_BLEND_RED, fui(state->color[0]));
435 si_pm4_set_reg(pm4, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
436 si_pm4_set_reg(pm4, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
437 si_pm4_set_reg(pm4, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
438
439 si_pm4_set_state(sctx, blend_color, pm4);
440 }
441
442 /*
443 * Clipping, scissors and viewport
444 */
445
446 static void si_set_clip_state(struct pipe_context *ctx,
447 const struct pipe_clip_state *state)
448 {
449 struct si_context *sctx = (struct si_context *)ctx;
450 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
451 struct pipe_constant_buffer cb;
452
453 if (pm4 == NULL)
454 return;
455
456 for (int i = 0; i < 6; i++) {
457 si_pm4_set_reg(pm4, R_0285BC_PA_CL_UCP_0_X + i * 16,
458 fui(state->ucp[i][0]));
459 si_pm4_set_reg(pm4, R_0285C0_PA_CL_UCP_0_Y + i * 16,
460 fui(state->ucp[i][1]));
461 si_pm4_set_reg(pm4, R_0285C4_PA_CL_UCP_0_Z + i * 16,
462 fui(state->ucp[i][2]));
463 si_pm4_set_reg(pm4, R_0285C8_PA_CL_UCP_0_W + i * 16,
464 fui(state->ucp[i][3]));
465 }
466
467 cb.buffer = NULL;
468 cb.user_buffer = state->ucp;
469 cb.buffer_offset = 0;
470 cb.buffer_size = 4*4*8;
471 ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, SI_DRIVER_STATE_CONST_BUF, &cb);
472 pipe_resource_reference(&cb.buffer, NULL);
473
474 si_pm4_set_state(sctx, clip, pm4);
475 }
476
477 #define SIX_BITS 0x3F
478
479 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
480 {
481 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
482 struct tgsi_shader_info *info = si_get_vs_info(sctx);
483 unsigned window_space =
484 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
485 unsigned clipdist_mask =
486 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
487
488 r600_write_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
489 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
490 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
491 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
492 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
493 S_02881C_VS_OUT_CCDIST0_VEC_ENA((clipdist_mask & 0x0F) != 0) |
494 S_02881C_VS_OUT_CCDIST1_VEC_ENA((clipdist_mask & 0xF0) != 0) |
495 S_02881C_VS_OUT_MISC_VEC_ENA(info->writes_psize ||
496 info->writes_edgeflag ||
497 info->writes_layer ||
498 info->writes_viewport_index) |
499 (sctx->queued.named.rasterizer->clip_plane_enable &
500 clipdist_mask));
501 r600_write_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
502 sctx->queued.named.rasterizer->pa_cl_clip_cntl |
503 (clipdist_mask ? 0 :
504 sctx->queued.named.rasterizer->clip_plane_enable & SIX_BITS) |
505 S_028810_CLIP_DISABLE(window_space));
506 }
507
508 static void si_set_scissor_states(struct pipe_context *ctx,
509 unsigned start_slot,
510 unsigned num_scissors,
511 const struct pipe_scissor_state *state)
512 {
513 struct si_context *sctx = (struct si_context *)ctx;
514 struct si_state_scissor *scissor;
515 struct si_pm4_state *pm4;
516 int i;
517
518 for (i = start_slot; i < start_slot + num_scissors; i++) {
519 int idx = i - start_slot;
520 int offset = i * 4 * 2;
521
522 scissor = CALLOC_STRUCT(si_state_scissor);
523 if (scissor == NULL)
524 return;
525 pm4 = &scissor->pm4;
526 scissor->scissor = state[idx];
527 si_pm4_set_reg(pm4, R_028250_PA_SC_VPORT_SCISSOR_0_TL + offset,
528 S_028250_TL_X(state[idx].minx) | S_028250_TL_Y(state[idx].miny) |
529 S_028250_WINDOW_OFFSET_DISABLE(1));
530 si_pm4_set_reg(pm4, R_028254_PA_SC_VPORT_SCISSOR_0_BR + offset,
531 S_028254_BR_X(state[idx].maxx) | S_028254_BR_Y(state[idx].maxy));
532 si_pm4_set_state(sctx, scissor[i], scissor);
533 }
534 }
535
536 static void si_set_viewport_states(struct pipe_context *ctx,
537 unsigned start_slot,
538 unsigned num_viewports,
539 const struct pipe_viewport_state *state)
540 {
541 struct si_context *sctx = (struct si_context *)ctx;
542 struct si_state_viewport *viewport;
543 struct si_pm4_state *pm4;
544 int i;
545
546 for (i = start_slot; i < start_slot + num_viewports; i++) {
547 int idx = i - start_slot;
548 int offset = i * 4 * 6;
549
550 viewport = CALLOC_STRUCT(si_state_viewport);
551 if (!viewport)
552 return;
553 pm4 = &viewport->pm4;
554
555 viewport->viewport = state[idx];
556 si_pm4_set_reg(pm4, R_02843C_PA_CL_VPORT_XSCALE_0 + offset, fui(state[idx].scale[0]));
557 si_pm4_set_reg(pm4, R_028440_PA_CL_VPORT_XOFFSET_0 + offset, fui(state[idx].translate[0]));
558 si_pm4_set_reg(pm4, R_028444_PA_CL_VPORT_YSCALE_0 + offset, fui(state[idx].scale[1]));
559 si_pm4_set_reg(pm4, R_028448_PA_CL_VPORT_YOFFSET_0 + offset, fui(state[idx].translate[1]));
560 si_pm4_set_reg(pm4, R_02844C_PA_CL_VPORT_ZSCALE_0 + offset, fui(state[idx].scale[2]));
561 si_pm4_set_reg(pm4, R_028450_PA_CL_VPORT_ZOFFSET_0 + offset, fui(state[idx].translate[2]));
562
563 si_pm4_set_state(sctx, viewport[i], viewport);
564 }
565 }
566
567 /*
568 * inferred state between framebuffer and rasterizer
569 */
570 static void si_update_fb_rs_state(struct si_context *sctx)
571 {
572 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
573 struct si_pm4_state *pm4;
574 float offset_units;
575
576 if (!rs || !sctx->framebuffer.state.zsbuf)
577 return;
578
579 offset_units = sctx->queued.named.rasterizer->offset_units;
580 switch (sctx->framebuffer.state.zsbuf->texture->format) {
581 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
582 case PIPE_FORMAT_X8Z24_UNORM:
583 case PIPE_FORMAT_Z24X8_UNORM:
584 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
585 offset_units *= 2.0f;
586 break;
587 case PIPE_FORMAT_Z32_FLOAT:
588 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
589 offset_units *= 1.0f;
590 break;
591 case PIPE_FORMAT_Z16_UNORM:
592 offset_units *= 4.0f;
593 break;
594 default:
595 return;
596 }
597
598 pm4 = CALLOC_STRUCT(si_pm4_state);
599
600 if (pm4 == NULL)
601 return;
602
603 /* FIXME some of those reg can be computed with cso */
604 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
605 fui(sctx->queued.named.rasterizer->offset_scale));
606 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET, fui(offset_units));
607 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
608 fui(sctx->queued.named.rasterizer->offset_scale));
609 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET, fui(offset_units));
610
611 si_pm4_set_state(sctx, fb_rs, pm4);
612 }
613
614 /*
615 * Rasterizer
616 */
617
618 static uint32_t si_translate_fill(uint32_t func)
619 {
620 switch(func) {
621 case PIPE_POLYGON_MODE_FILL:
622 return V_028814_X_DRAW_TRIANGLES;
623 case PIPE_POLYGON_MODE_LINE:
624 return V_028814_X_DRAW_LINES;
625 case PIPE_POLYGON_MODE_POINT:
626 return V_028814_X_DRAW_POINTS;
627 default:
628 assert(0);
629 return V_028814_X_DRAW_POINTS;
630 }
631 }
632
633 static void *si_create_rs_state(struct pipe_context *ctx,
634 const struct pipe_rasterizer_state *state)
635 {
636 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
637 struct si_pm4_state *pm4 = &rs->pm4;
638 unsigned tmp;
639 float psize_min, psize_max;
640
641 if (rs == NULL) {
642 return NULL;
643 }
644
645 rs->two_side = state->light_twoside;
646 rs->multisample_enable = state->multisample;
647 rs->clip_plane_enable = state->clip_plane_enable;
648 rs->line_stipple_enable = state->line_stipple_enable;
649 rs->poly_stipple_enable = state->poly_stipple_enable;
650 rs->line_smooth = state->line_smooth;
651 rs->poly_smooth = state->poly_smooth;
652
653 rs->flatshade = state->flatshade;
654 rs->sprite_coord_enable = state->sprite_coord_enable;
655 rs->pa_sc_line_stipple = state->line_stipple_enable ?
656 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
657 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
658 rs->pa_cl_clip_cntl =
659 S_028810_PS_UCP_MODE(3) |
660 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
661 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
662 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
663 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
664 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
665
666 /* offset */
667 rs->offset_units = state->offset_units;
668 rs->offset_scale = state->offset_scale * 12.0f;
669
670 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
671 S_0286D4_FLAT_SHADE_ENA(1) |
672 S_0286D4_PNT_SPRITE_ENA(1) |
673 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
674 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
675 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
676 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
677 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
678
679 /* point size 12.4 fixed point */
680 tmp = (unsigned)(state->point_size * 8.0);
681 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
682
683 if (state->point_size_per_vertex) {
684 psize_min = util_get_min_point_size(state);
685 psize_max = 8192;
686 } else {
687 /* Force the point size to be as if the vertex output was disabled. */
688 psize_min = state->point_size;
689 psize_max = state->point_size;
690 }
691 /* Divide by two, because 0.5 = 1 pixel. */
692 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
693 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
694 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
695
696 tmp = (unsigned)state->line_width * 8;
697 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
698 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
699 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
700 S_028A48_MSAA_ENABLE(state->multisample ||
701 state->poly_smooth ||
702 state->line_smooth) |
703 S_028A48_VPORT_SCISSOR_ENABLE(state->scissor));
704
705 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
706 S_028BE4_PIX_CENTER(state->half_pixel_center) |
707 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
708
709 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
710 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
711 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
712 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
713 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
714 S_028814_FACE(!state->front_ccw) |
715 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
716 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
717 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
718 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
719 state->fill_back != PIPE_POLYGON_MODE_FILL) |
720 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
721 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
722 return rs;
723 }
724
725 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
726 {
727 struct si_context *sctx = (struct si_context *)ctx;
728 struct si_state_rasterizer *old_rs =
729 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
730 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
731
732 if (state == NULL)
733 return;
734
735 if (sctx->framebuffer.nr_samples > 1 &&
736 (!old_rs || old_rs->multisample_enable != rs->multisample_enable))
737 sctx->db_render_state.dirty = true;
738
739 si_pm4_bind_state(sctx, rasterizer, rs);
740 si_update_fb_rs_state(sctx);
741
742 sctx->clip_regs.dirty = true;
743 }
744
745 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
746 {
747 struct si_context *sctx = (struct si_context *)ctx;
748 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
749 }
750
751 /*
752 * infeered state between dsa and stencil ref
753 */
754 static void si_update_dsa_stencil_ref(struct si_context *sctx)
755 {
756 struct si_pm4_state *pm4;
757 struct pipe_stencil_ref *ref = &sctx->stencil_ref;
758 struct si_state_dsa *dsa = sctx->queued.named.dsa;
759
760 if (!dsa)
761 return;
762
763 pm4 = CALLOC_STRUCT(si_pm4_state);
764 if (pm4 == NULL)
765 return;
766
767 si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
768 S_028430_STENCILTESTVAL(ref->ref_value[0]) |
769 S_028430_STENCILMASK(dsa->valuemask[0]) |
770 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
771 S_028430_STENCILOPVAL(1));
772 si_pm4_set_reg(pm4, R_028434_DB_STENCILREFMASK_BF,
773 S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
774 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
775 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
776 S_028434_STENCILOPVAL_BF(1));
777
778 si_pm4_set_state(sctx, dsa_stencil_ref, pm4);
779 }
780
781 static void si_set_pipe_stencil_ref(struct pipe_context *ctx,
782 const struct pipe_stencil_ref *state)
783 {
784 struct si_context *sctx = (struct si_context *)ctx;
785 sctx->stencil_ref = *state;
786 si_update_dsa_stencil_ref(sctx);
787 }
788
789
790 /*
791 * DSA
792 */
793
794 static uint32_t si_translate_stencil_op(int s_op)
795 {
796 switch (s_op) {
797 case PIPE_STENCIL_OP_KEEP:
798 return V_02842C_STENCIL_KEEP;
799 case PIPE_STENCIL_OP_ZERO:
800 return V_02842C_STENCIL_ZERO;
801 case PIPE_STENCIL_OP_REPLACE:
802 return V_02842C_STENCIL_REPLACE_TEST;
803 case PIPE_STENCIL_OP_INCR:
804 return V_02842C_STENCIL_ADD_CLAMP;
805 case PIPE_STENCIL_OP_DECR:
806 return V_02842C_STENCIL_SUB_CLAMP;
807 case PIPE_STENCIL_OP_INCR_WRAP:
808 return V_02842C_STENCIL_ADD_WRAP;
809 case PIPE_STENCIL_OP_DECR_WRAP:
810 return V_02842C_STENCIL_SUB_WRAP;
811 case PIPE_STENCIL_OP_INVERT:
812 return V_02842C_STENCIL_INVERT;
813 default:
814 R600_ERR("Unknown stencil op %d", s_op);
815 assert(0);
816 break;
817 }
818 return 0;
819 }
820
821 static void *si_create_dsa_state(struct pipe_context *ctx,
822 const struct pipe_depth_stencil_alpha_state *state)
823 {
824 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
825 struct si_pm4_state *pm4 = &dsa->pm4;
826 unsigned db_depth_control;
827 uint32_t db_stencil_control = 0;
828
829 if (dsa == NULL) {
830 return NULL;
831 }
832
833 dsa->valuemask[0] = state->stencil[0].valuemask;
834 dsa->valuemask[1] = state->stencil[1].valuemask;
835 dsa->writemask[0] = state->stencil[0].writemask;
836 dsa->writemask[1] = state->stencil[1].writemask;
837
838 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
839 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
840 S_028800_ZFUNC(state->depth.func);
841
842 /* stencil */
843 if (state->stencil[0].enabled) {
844 db_depth_control |= S_028800_STENCIL_ENABLE(1);
845 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
846 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
847 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
848 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
849
850 if (state->stencil[1].enabled) {
851 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
852 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
853 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
854 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
855 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
856 }
857 }
858
859 /* alpha */
860 if (state->alpha.enabled) {
861 dsa->alpha_func = state->alpha.func;
862
863 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
864 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
865 } else {
866 dsa->alpha_func = PIPE_FUNC_ALWAYS;
867 }
868
869 /* misc */
870 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
871 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
872
873 return dsa;
874 }
875
876 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
877 {
878 struct si_context *sctx = (struct si_context *)ctx;
879 struct si_state_dsa *dsa = state;
880
881 if (state == NULL)
882 return;
883
884 si_pm4_bind_state(sctx, dsa, dsa);
885 si_update_dsa_stencil_ref(sctx);
886 }
887
888 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
889 {
890 struct si_context *sctx = (struct si_context *)ctx;
891 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
892 }
893
894 static void *si_create_db_flush_dsa(struct si_context *sctx)
895 {
896 struct pipe_depth_stencil_alpha_state dsa = {};
897
898 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
899 }
900
901 /* DB RENDER STATE */
902
903 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
904 {
905 struct si_context *sctx = (struct si_context*)ctx;
906
907 sctx->db_render_state.dirty = true;
908 }
909
910 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
911 {
912 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
913 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
914 unsigned db_shader_control;
915
916 r600_write_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
917
918 /* DB_RENDER_CONTROL */
919 if (sctx->dbcb_depth_copy_enabled ||
920 sctx->dbcb_stencil_copy_enabled) {
921 radeon_emit(cs,
922 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
923 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
924 S_028000_COPY_CENTROID(1) |
925 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
926 } else if (sctx->db_inplace_flush_enabled) {
927 radeon_emit(cs,
928 S_028000_DEPTH_COMPRESS_DISABLE(1) |
929 S_028000_STENCIL_COMPRESS_DISABLE(1));
930 } else if (sctx->db_depth_clear) {
931 radeon_emit(cs, S_028000_DEPTH_CLEAR_ENABLE(1));
932 } else {
933 radeon_emit(cs, 0);
934 }
935
936 /* DB_COUNT_CONTROL (occlusion queries) */
937 if (sctx->b.num_occlusion_queries > 0) {
938 if (sctx->b.chip_class >= CIK) {
939 radeon_emit(cs,
940 S_028004_PERFECT_ZPASS_COUNTS(1) |
941 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
942 S_028004_ZPASS_ENABLE(1) |
943 S_028004_SLICE_EVEN_ENABLE(1) |
944 S_028004_SLICE_ODD_ENABLE(1));
945 } else {
946 radeon_emit(cs,
947 S_028004_PERFECT_ZPASS_COUNTS(1) |
948 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
949 }
950 } else {
951 /* Disable occlusion queries. */
952 if (sctx->b.chip_class >= CIK) {
953 radeon_emit(cs, 0);
954 } else {
955 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
956 }
957 }
958
959 /* DB_RENDER_OVERRIDE2 */
960 if (sctx->db_depth_disable_expclear) {
961 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
962 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(1));
963 } else {
964 r600_write_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2, 0);
965 }
966
967 db_shader_control = S_02880C_ALPHA_TO_MASK_DISABLE(sctx->framebuffer.cb0_is_integer) |
968 sctx->ps_db_shader_control;
969
970 /* Bug workaround for smoothing (overrasterization) on SI. */
971 if (sctx->b.chip_class == SI && sctx->smoothing_enabled)
972 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
973 else
974 db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
975
976 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
977 if (sctx->framebuffer.nr_samples <= 1 || (rs && !rs->multisample_enable))
978 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
979
980 r600_write_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
981 db_shader_control);
982 }
983
984 /*
985 * format translation
986 */
987 static uint32_t si_translate_colorformat(enum pipe_format format)
988 {
989 const struct util_format_description *desc = util_format_description(format);
990
991 #define HAS_SIZE(x,y,z,w) \
992 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
993 desc->channel[2].size == (z) && desc->channel[3].size == (w))
994
995 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
996 return V_028C70_COLOR_10_11_11;
997
998 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
999 return V_028C70_COLOR_INVALID;
1000
1001 switch (desc->nr_channels) {
1002 case 1:
1003 switch (desc->channel[0].size) {
1004 case 8:
1005 return V_028C70_COLOR_8;
1006 case 16:
1007 return V_028C70_COLOR_16;
1008 case 32:
1009 return V_028C70_COLOR_32;
1010 }
1011 break;
1012 case 2:
1013 if (desc->channel[0].size == desc->channel[1].size) {
1014 switch (desc->channel[0].size) {
1015 case 8:
1016 return V_028C70_COLOR_8_8;
1017 case 16:
1018 return V_028C70_COLOR_16_16;
1019 case 32:
1020 return V_028C70_COLOR_32_32;
1021 }
1022 } else if (HAS_SIZE(8,24,0,0)) {
1023 return V_028C70_COLOR_24_8;
1024 } else if (HAS_SIZE(24,8,0,0)) {
1025 return V_028C70_COLOR_8_24;
1026 }
1027 break;
1028 case 3:
1029 if (HAS_SIZE(5,6,5,0)) {
1030 return V_028C70_COLOR_5_6_5;
1031 } else if (HAS_SIZE(32,8,24,0)) {
1032 return V_028C70_COLOR_X24_8_32_FLOAT;
1033 }
1034 break;
1035 case 4:
1036 if (desc->channel[0].size == desc->channel[1].size &&
1037 desc->channel[0].size == desc->channel[2].size &&
1038 desc->channel[0].size == desc->channel[3].size) {
1039 switch (desc->channel[0].size) {
1040 case 4:
1041 return V_028C70_COLOR_4_4_4_4;
1042 case 8:
1043 return V_028C70_COLOR_8_8_8_8;
1044 case 16:
1045 return V_028C70_COLOR_16_16_16_16;
1046 case 32:
1047 return V_028C70_COLOR_32_32_32_32;
1048 }
1049 } else if (HAS_SIZE(5,5,5,1)) {
1050 return V_028C70_COLOR_1_5_5_5;
1051 } else if (HAS_SIZE(10,10,10,2)) {
1052 return V_028C70_COLOR_2_10_10_10;
1053 }
1054 break;
1055 }
1056 return V_028C70_COLOR_INVALID;
1057 }
1058
1059 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1060 {
1061 if (SI_BIG_ENDIAN) {
1062 switch(colorformat) {
1063 /* 8-bit buffers. */
1064 case V_028C70_COLOR_8:
1065 return V_028C70_ENDIAN_NONE;
1066
1067 /* 16-bit buffers. */
1068 case V_028C70_COLOR_5_6_5:
1069 case V_028C70_COLOR_1_5_5_5:
1070 case V_028C70_COLOR_4_4_4_4:
1071 case V_028C70_COLOR_16:
1072 case V_028C70_COLOR_8_8:
1073 return V_028C70_ENDIAN_8IN16;
1074
1075 /* 32-bit buffers. */
1076 case V_028C70_COLOR_8_8_8_8:
1077 case V_028C70_COLOR_2_10_10_10:
1078 case V_028C70_COLOR_8_24:
1079 case V_028C70_COLOR_24_8:
1080 case V_028C70_COLOR_16_16:
1081 return V_028C70_ENDIAN_8IN32;
1082
1083 /* 64-bit buffers. */
1084 case V_028C70_COLOR_16_16_16_16:
1085 return V_028C70_ENDIAN_8IN16;
1086
1087 case V_028C70_COLOR_32_32:
1088 return V_028C70_ENDIAN_8IN32;
1089
1090 /* 128-bit buffers. */
1091 case V_028C70_COLOR_32_32_32_32:
1092 return V_028C70_ENDIAN_8IN32;
1093 default:
1094 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1095 }
1096 } else {
1097 return V_028C70_ENDIAN_NONE;
1098 }
1099 }
1100
1101 /* Returns the size in bits of the widest component of a CB format */
1102 static unsigned si_colorformat_max_comp_size(uint32_t colorformat)
1103 {
1104 switch(colorformat) {
1105 case V_028C70_COLOR_4_4_4_4:
1106 return 4;
1107
1108 case V_028C70_COLOR_1_5_5_5:
1109 case V_028C70_COLOR_5_5_5_1:
1110 return 5;
1111
1112 case V_028C70_COLOR_5_6_5:
1113 return 6;
1114
1115 case V_028C70_COLOR_8:
1116 case V_028C70_COLOR_8_8:
1117 case V_028C70_COLOR_8_8_8_8:
1118 return 8;
1119
1120 case V_028C70_COLOR_10_10_10_2:
1121 case V_028C70_COLOR_2_10_10_10:
1122 return 10;
1123
1124 case V_028C70_COLOR_10_11_11:
1125 case V_028C70_COLOR_11_11_10:
1126 return 11;
1127
1128 case V_028C70_COLOR_16:
1129 case V_028C70_COLOR_16_16:
1130 case V_028C70_COLOR_16_16_16_16:
1131 return 16;
1132
1133 case V_028C70_COLOR_8_24:
1134 case V_028C70_COLOR_24_8:
1135 return 24;
1136
1137 case V_028C70_COLOR_32:
1138 case V_028C70_COLOR_32_32:
1139 case V_028C70_COLOR_32_32_32_32:
1140 case V_028C70_COLOR_X24_8_32_FLOAT:
1141 return 32;
1142 }
1143
1144 assert(!"Unknown maximum component size");
1145 return 0;
1146 }
1147
1148 static uint32_t si_translate_dbformat(enum pipe_format format)
1149 {
1150 switch (format) {
1151 case PIPE_FORMAT_Z16_UNORM:
1152 return V_028040_Z_16;
1153 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1154 case PIPE_FORMAT_X8Z24_UNORM:
1155 case PIPE_FORMAT_Z24X8_UNORM:
1156 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1157 return V_028040_Z_24; /* deprecated on SI */
1158 case PIPE_FORMAT_Z32_FLOAT:
1159 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1160 return V_028040_Z_32_FLOAT;
1161 default:
1162 return V_028040_Z_INVALID;
1163 }
1164 }
1165
1166 /*
1167 * Texture translation
1168 */
1169
1170 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1171 enum pipe_format format,
1172 const struct util_format_description *desc,
1173 int first_non_void)
1174 {
1175 struct si_screen *sscreen = (struct si_screen*)screen;
1176 bool enable_s3tc = sscreen->b.info.drm_minor >= 31;
1177 boolean uniform = TRUE;
1178 int i;
1179
1180 /* Colorspace (return non-RGB formats directly). */
1181 switch (desc->colorspace) {
1182 /* Depth stencil formats */
1183 case UTIL_FORMAT_COLORSPACE_ZS:
1184 switch (format) {
1185 case PIPE_FORMAT_Z16_UNORM:
1186 return V_008F14_IMG_DATA_FORMAT_16;
1187 case PIPE_FORMAT_X24S8_UINT:
1188 case PIPE_FORMAT_Z24X8_UNORM:
1189 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1190 return V_008F14_IMG_DATA_FORMAT_8_24;
1191 case PIPE_FORMAT_X8Z24_UNORM:
1192 case PIPE_FORMAT_S8X24_UINT:
1193 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1194 return V_008F14_IMG_DATA_FORMAT_24_8;
1195 case PIPE_FORMAT_S8_UINT:
1196 return V_008F14_IMG_DATA_FORMAT_8;
1197 case PIPE_FORMAT_Z32_FLOAT:
1198 return V_008F14_IMG_DATA_FORMAT_32;
1199 case PIPE_FORMAT_X32_S8X24_UINT:
1200 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1201 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1202 default:
1203 goto out_unknown;
1204 }
1205
1206 case UTIL_FORMAT_COLORSPACE_YUV:
1207 goto out_unknown; /* TODO */
1208
1209 case UTIL_FORMAT_COLORSPACE_SRGB:
1210 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1211 goto out_unknown;
1212 break;
1213
1214 default:
1215 break;
1216 }
1217
1218 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1219 if (!enable_s3tc)
1220 goto out_unknown;
1221
1222 switch (format) {
1223 case PIPE_FORMAT_RGTC1_SNORM:
1224 case PIPE_FORMAT_LATC1_SNORM:
1225 case PIPE_FORMAT_RGTC1_UNORM:
1226 case PIPE_FORMAT_LATC1_UNORM:
1227 return V_008F14_IMG_DATA_FORMAT_BC4;
1228 case PIPE_FORMAT_RGTC2_SNORM:
1229 case PIPE_FORMAT_LATC2_SNORM:
1230 case PIPE_FORMAT_RGTC2_UNORM:
1231 case PIPE_FORMAT_LATC2_UNORM:
1232 return V_008F14_IMG_DATA_FORMAT_BC5;
1233 default:
1234 goto out_unknown;
1235 }
1236 }
1237
1238 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1239 if (!enable_s3tc)
1240 goto out_unknown;
1241
1242 switch (format) {
1243 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1244 case PIPE_FORMAT_BPTC_SRGBA:
1245 return V_008F14_IMG_DATA_FORMAT_BC7;
1246 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1247 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1248 return V_008F14_IMG_DATA_FORMAT_BC6;
1249 default:
1250 goto out_unknown;
1251 }
1252 }
1253
1254 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1255 switch (format) {
1256 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1257 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1258 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1259 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1260 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1261 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1262 default:
1263 goto out_unknown;
1264 }
1265 }
1266
1267 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1268
1269 if (!enable_s3tc)
1270 goto out_unknown;
1271
1272 if (!util_format_s3tc_enabled) {
1273 goto out_unknown;
1274 }
1275
1276 switch (format) {
1277 case PIPE_FORMAT_DXT1_RGB:
1278 case PIPE_FORMAT_DXT1_RGBA:
1279 case PIPE_FORMAT_DXT1_SRGB:
1280 case PIPE_FORMAT_DXT1_SRGBA:
1281 return V_008F14_IMG_DATA_FORMAT_BC1;
1282 case PIPE_FORMAT_DXT3_RGBA:
1283 case PIPE_FORMAT_DXT3_SRGBA:
1284 return V_008F14_IMG_DATA_FORMAT_BC2;
1285 case PIPE_FORMAT_DXT5_RGBA:
1286 case PIPE_FORMAT_DXT5_SRGBA:
1287 return V_008F14_IMG_DATA_FORMAT_BC3;
1288 default:
1289 goto out_unknown;
1290 }
1291 }
1292
1293 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1294 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1295 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1296 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1297 }
1298
1299 /* R8G8Bx_SNORM - TODO CxV8U8 */
1300
1301 /* See whether the components are of the same size. */
1302 for (i = 1; i < desc->nr_channels; i++) {
1303 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1304 }
1305
1306 /* Non-uniform formats. */
1307 if (!uniform) {
1308 switch(desc->nr_channels) {
1309 case 3:
1310 if (desc->channel[0].size == 5 &&
1311 desc->channel[1].size == 6 &&
1312 desc->channel[2].size == 5) {
1313 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1314 }
1315 goto out_unknown;
1316 case 4:
1317 if (desc->channel[0].size == 5 &&
1318 desc->channel[1].size == 5 &&
1319 desc->channel[2].size == 5 &&
1320 desc->channel[3].size == 1) {
1321 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1322 }
1323 if (desc->channel[0].size == 10 &&
1324 desc->channel[1].size == 10 &&
1325 desc->channel[2].size == 10 &&
1326 desc->channel[3].size == 2) {
1327 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1328 }
1329 goto out_unknown;
1330 }
1331 goto out_unknown;
1332 }
1333
1334 if (first_non_void < 0 || first_non_void > 3)
1335 goto out_unknown;
1336
1337 /* uniform formats */
1338 switch (desc->channel[first_non_void].size) {
1339 case 4:
1340 switch (desc->nr_channels) {
1341 #if 0 /* Not supported for render targets */
1342 case 2:
1343 return V_008F14_IMG_DATA_FORMAT_4_4;
1344 #endif
1345 case 4:
1346 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1347 }
1348 break;
1349 case 8:
1350 switch (desc->nr_channels) {
1351 case 1:
1352 return V_008F14_IMG_DATA_FORMAT_8;
1353 case 2:
1354 return V_008F14_IMG_DATA_FORMAT_8_8;
1355 case 4:
1356 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1357 }
1358 break;
1359 case 16:
1360 switch (desc->nr_channels) {
1361 case 1:
1362 return V_008F14_IMG_DATA_FORMAT_16;
1363 case 2:
1364 return V_008F14_IMG_DATA_FORMAT_16_16;
1365 case 4:
1366 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1367 }
1368 break;
1369 case 32:
1370 switch (desc->nr_channels) {
1371 case 1:
1372 return V_008F14_IMG_DATA_FORMAT_32;
1373 case 2:
1374 return V_008F14_IMG_DATA_FORMAT_32_32;
1375 #if 0 /* Not supported for render targets */
1376 case 3:
1377 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1378 #endif
1379 case 4:
1380 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1381 }
1382 }
1383
1384 out_unknown:
1385 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1386 return ~0;
1387 }
1388
1389 static unsigned si_tex_wrap(unsigned wrap)
1390 {
1391 switch (wrap) {
1392 default:
1393 case PIPE_TEX_WRAP_REPEAT:
1394 return V_008F30_SQ_TEX_WRAP;
1395 case PIPE_TEX_WRAP_CLAMP:
1396 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1397 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1398 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1399 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1400 return V_008F30_SQ_TEX_CLAMP_BORDER;
1401 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1402 return V_008F30_SQ_TEX_MIRROR;
1403 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1404 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1405 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1406 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1407 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1408 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1409 }
1410 }
1411
1412 static unsigned si_tex_filter(unsigned filter)
1413 {
1414 switch (filter) {
1415 default:
1416 case PIPE_TEX_FILTER_NEAREST:
1417 return V_008F38_SQ_TEX_XY_FILTER_POINT;
1418 case PIPE_TEX_FILTER_LINEAR:
1419 return V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
1420 }
1421 }
1422
1423 static unsigned si_tex_mipfilter(unsigned filter)
1424 {
1425 switch (filter) {
1426 case PIPE_TEX_MIPFILTER_NEAREST:
1427 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1428 case PIPE_TEX_MIPFILTER_LINEAR:
1429 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1430 default:
1431 case PIPE_TEX_MIPFILTER_NONE:
1432 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1433 }
1434 }
1435
1436 static unsigned si_tex_compare(unsigned compare)
1437 {
1438 switch (compare) {
1439 default:
1440 case PIPE_FUNC_NEVER:
1441 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1442 case PIPE_FUNC_LESS:
1443 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1444 case PIPE_FUNC_EQUAL:
1445 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1446 case PIPE_FUNC_LEQUAL:
1447 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1448 case PIPE_FUNC_GREATER:
1449 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1450 case PIPE_FUNC_NOTEQUAL:
1451 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1452 case PIPE_FUNC_GEQUAL:
1453 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1454 case PIPE_FUNC_ALWAYS:
1455 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1456 }
1457 }
1458
1459 static unsigned si_tex_dim(unsigned dim, unsigned nr_samples)
1460 {
1461 switch (dim) {
1462 default:
1463 case PIPE_TEXTURE_1D:
1464 return V_008F1C_SQ_RSRC_IMG_1D;
1465 case PIPE_TEXTURE_1D_ARRAY:
1466 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1467 case PIPE_TEXTURE_2D:
1468 case PIPE_TEXTURE_RECT:
1469 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1470 V_008F1C_SQ_RSRC_IMG_2D;
1471 case PIPE_TEXTURE_2D_ARRAY:
1472 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1473 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1474 case PIPE_TEXTURE_3D:
1475 return V_008F1C_SQ_RSRC_IMG_3D;
1476 case PIPE_TEXTURE_CUBE:
1477 case PIPE_TEXTURE_CUBE_ARRAY:
1478 return V_008F1C_SQ_RSRC_IMG_CUBE;
1479 }
1480 }
1481
1482 /*
1483 * Format support testing
1484 */
1485
1486 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1487 {
1488 return si_translate_texformat(screen, format, util_format_description(format),
1489 util_format_get_first_non_void_channel(format)) != ~0U;
1490 }
1491
1492 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1493 const struct util_format_description *desc,
1494 int first_non_void)
1495 {
1496 unsigned type = desc->channel[first_non_void].type;
1497 int i;
1498
1499 if (type == UTIL_FORMAT_TYPE_FIXED)
1500 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1501
1502 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1503 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1504
1505 if (desc->nr_channels == 4 &&
1506 desc->channel[0].size == 10 &&
1507 desc->channel[1].size == 10 &&
1508 desc->channel[2].size == 10 &&
1509 desc->channel[3].size == 2)
1510 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1511
1512 /* See whether the components are of the same size. */
1513 for (i = 0; i < desc->nr_channels; i++) {
1514 if (desc->channel[first_non_void].size != desc->channel[i].size)
1515 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1516 }
1517
1518 switch (desc->channel[first_non_void].size) {
1519 case 8:
1520 switch (desc->nr_channels) {
1521 case 1:
1522 return V_008F0C_BUF_DATA_FORMAT_8;
1523 case 2:
1524 return V_008F0C_BUF_DATA_FORMAT_8_8;
1525 case 3:
1526 case 4:
1527 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1528 }
1529 break;
1530 case 16:
1531 switch (desc->nr_channels) {
1532 case 1:
1533 return V_008F0C_BUF_DATA_FORMAT_16;
1534 case 2:
1535 return V_008F0C_BUF_DATA_FORMAT_16_16;
1536 case 3:
1537 case 4:
1538 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1539 }
1540 break;
1541 case 32:
1542 /* From the Southern Islands ISA documentation about MTBUF:
1543 * 'Memory reads of data in memory that is 32 or 64 bits do not
1544 * undergo any format conversion.'
1545 */
1546 if (type != UTIL_FORMAT_TYPE_FLOAT &&
1547 !desc->channel[first_non_void].pure_integer)
1548 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1549
1550 switch (desc->nr_channels) {
1551 case 1:
1552 return V_008F0C_BUF_DATA_FORMAT_32;
1553 case 2:
1554 return V_008F0C_BUF_DATA_FORMAT_32_32;
1555 case 3:
1556 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1557 case 4:
1558 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1559 }
1560 break;
1561 }
1562
1563 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1564 }
1565
1566 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1567 const struct util_format_description *desc,
1568 int first_non_void)
1569 {
1570 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1571 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1572
1573 switch (desc->channel[first_non_void].type) {
1574 case UTIL_FORMAT_TYPE_SIGNED:
1575 if (desc->channel[first_non_void].normalized)
1576 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1577 else if (desc->channel[first_non_void].pure_integer)
1578 return V_008F0C_BUF_NUM_FORMAT_SINT;
1579 else
1580 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1581 break;
1582 case UTIL_FORMAT_TYPE_UNSIGNED:
1583 if (desc->channel[first_non_void].normalized)
1584 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1585 else if (desc->channel[first_non_void].pure_integer)
1586 return V_008F0C_BUF_NUM_FORMAT_UINT;
1587 else
1588 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1589 break;
1590 case UTIL_FORMAT_TYPE_FLOAT:
1591 default:
1592 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1593 }
1594 }
1595
1596 static bool si_is_vertex_format_supported(struct pipe_screen *screen, enum pipe_format format)
1597 {
1598 const struct util_format_description *desc;
1599 int first_non_void;
1600 unsigned data_format;
1601
1602 desc = util_format_description(format);
1603 first_non_void = util_format_get_first_non_void_channel(format);
1604 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1605 return data_format != V_008F0C_BUF_DATA_FORMAT_INVALID;
1606 }
1607
1608 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1609 {
1610 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1611 r600_translate_colorswap(format) != ~0U;
1612 }
1613
1614 static bool si_is_zs_format_supported(enum pipe_format format)
1615 {
1616 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1617 }
1618
1619 boolean si_is_format_supported(struct pipe_screen *screen,
1620 enum pipe_format format,
1621 enum pipe_texture_target target,
1622 unsigned sample_count,
1623 unsigned usage)
1624 {
1625 struct si_screen *sscreen = (struct si_screen *)screen;
1626 unsigned retval = 0;
1627
1628 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1629 R600_ERR("r600: unsupported texture type %d\n", target);
1630 return FALSE;
1631 }
1632
1633 if (!util_format_is_supported(format, usage))
1634 return FALSE;
1635
1636 if (sample_count > 1) {
1637 /* 2D tiling on CIK is supported since DRM 2.35.0 */
1638 if (sscreen->b.chip_class >= CIK && sscreen->b.info.drm_minor < 35)
1639 return FALSE;
1640
1641 switch (sample_count) {
1642 case 2:
1643 case 4:
1644 case 8:
1645 break;
1646 default:
1647 return FALSE;
1648 }
1649 }
1650
1651 if (usage & PIPE_BIND_SAMPLER_VIEW) {
1652 if (target == PIPE_BUFFER) {
1653 if (si_is_vertex_format_supported(screen, format))
1654 retval |= PIPE_BIND_SAMPLER_VIEW;
1655 } else {
1656 if (si_is_sampler_format_supported(screen, format))
1657 retval |= PIPE_BIND_SAMPLER_VIEW;
1658 }
1659 }
1660
1661 if ((usage & (PIPE_BIND_RENDER_TARGET |
1662 PIPE_BIND_DISPLAY_TARGET |
1663 PIPE_BIND_SCANOUT |
1664 PIPE_BIND_SHARED |
1665 PIPE_BIND_BLENDABLE)) &&
1666 si_is_colorbuffer_format_supported(format)) {
1667 retval |= usage &
1668 (PIPE_BIND_RENDER_TARGET |
1669 PIPE_BIND_DISPLAY_TARGET |
1670 PIPE_BIND_SCANOUT |
1671 PIPE_BIND_SHARED);
1672 if (!util_format_is_pure_integer(format) &&
1673 !util_format_is_depth_or_stencil(format))
1674 retval |= usage & PIPE_BIND_BLENDABLE;
1675 }
1676
1677 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1678 si_is_zs_format_supported(format)) {
1679 retval |= PIPE_BIND_DEPTH_STENCIL;
1680 }
1681
1682 if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
1683 si_is_vertex_format_supported(screen, format)) {
1684 retval |= PIPE_BIND_VERTEX_BUFFER;
1685 }
1686
1687 if (usage & PIPE_BIND_TRANSFER_READ)
1688 retval |= PIPE_BIND_TRANSFER_READ;
1689 if (usage & PIPE_BIND_TRANSFER_WRITE)
1690 retval |= PIPE_BIND_TRANSFER_WRITE;
1691
1692 return retval == usage;
1693 }
1694
1695 unsigned si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
1696 {
1697 unsigned tile_mode_index = 0;
1698
1699 if (stencil) {
1700 tile_mode_index = rtex->surface.stencil_tiling_index[level];
1701 } else {
1702 tile_mode_index = rtex->surface.tiling_index[level];
1703 }
1704 return tile_mode_index;
1705 }
1706
1707 /*
1708 * framebuffer handling
1709 */
1710
1711 static void si_initialize_color_surface(struct si_context *sctx,
1712 struct r600_surface *surf)
1713 {
1714 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1715 unsigned level = surf->base.u.tex.level;
1716 uint64_t offset = rtex->surface.level[level].offset;
1717 unsigned pitch, slice;
1718 unsigned color_info, color_attrib, color_pitch, color_view;
1719 unsigned tile_mode_index;
1720 unsigned format, swap, ntype, endian;
1721 const struct util_format_description *desc;
1722 int i;
1723 unsigned blend_clamp = 0, blend_bypass = 0;
1724 unsigned max_comp_size;
1725
1726 /* Layered rendering doesn't work with LINEAR_GENERAL.
1727 * (LINEAR_ALIGNED and others work) */
1728 if (rtex->surface.level[level].mode == RADEON_SURF_MODE_LINEAR) {
1729 assert(surf->base.u.tex.first_layer == surf->base.u.tex.last_layer);
1730 offset += rtex->surface.level[level].slice_size *
1731 surf->base.u.tex.first_layer;
1732 color_view = 0;
1733 } else {
1734 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
1735 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
1736 }
1737
1738 pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
1739 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1740 if (slice) {
1741 slice = slice - 1;
1742 }
1743
1744 tile_mode_index = si_tile_mode_index(rtex, level, false);
1745
1746 desc = util_format_description(surf->base.format);
1747 for (i = 0; i < 4; i++) {
1748 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1749 break;
1750 }
1751 }
1752 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
1753 ntype = V_028C70_NUMBER_FLOAT;
1754 } else {
1755 ntype = V_028C70_NUMBER_UNORM;
1756 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1757 ntype = V_028C70_NUMBER_SRGB;
1758 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1759 if (desc->channel[i].pure_integer) {
1760 ntype = V_028C70_NUMBER_SINT;
1761 } else {
1762 assert(desc->channel[i].normalized);
1763 ntype = V_028C70_NUMBER_SNORM;
1764 }
1765 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1766 if (desc->channel[i].pure_integer) {
1767 ntype = V_028C70_NUMBER_UINT;
1768 } else {
1769 assert(desc->channel[i].normalized);
1770 ntype = V_028C70_NUMBER_UNORM;
1771 }
1772 }
1773 }
1774
1775 format = si_translate_colorformat(surf->base.format);
1776 if (format == V_028C70_COLOR_INVALID) {
1777 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
1778 }
1779 assert(format != V_028C70_COLOR_INVALID);
1780 swap = r600_translate_colorswap(surf->base.format);
1781 if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1782 endian = V_028C70_ENDIAN_NONE;
1783 } else {
1784 endian = si_colorformat_endian_swap(format);
1785 }
1786
1787 /* blend clamp should be set for all NORM/SRGB types */
1788 if (ntype == V_028C70_NUMBER_UNORM ||
1789 ntype == V_028C70_NUMBER_SNORM ||
1790 ntype == V_028C70_NUMBER_SRGB)
1791 blend_clamp = 1;
1792
1793 /* set blend bypass according to docs if SINT/UINT or
1794 8/24 COLOR variants */
1795 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1796 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1797 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1798 blend_clamp = 0;
1799 blend_bypass = 1;
1800 }
1801
1802 color_info = S_028C70_FORMAT(format) |
1803 S_028C70_COMP_SWAP(swap) |
1804 S_028C70_BLEND_CLAMP(blend_clamp) |
1805 S_028C70_BLEND_BYPASS(blend_bypass) |
1806 S_028C70_NUMBER_TYPE(ntype) |
1807 S_028C70_ENDIAN(endian);
1808
1809 color_pitch = S_028C64_TILE_MAX(pitch);
1810
1811 color_attrib = S_028C74_TILE_MODE_INDEX(tile_mode_index) |
1812 S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == UTIL_FORMAT_SWIZZLE_1);
1813
1814 if (rtex->resource.b.b.nr_samples > 1) {
1815 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
1816
1817 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1818 S_028C74_NUM_FRAGMENTS(log_samples);
1819
1820 if (rtex->fmask.size) {
1821 color_info |= S_028C70_COMPRESSION(1);
1822 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
1823
1824 color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(rtex->fmask.tile_mode_index);
1825
1826 if (sctx->b.chip_class == SI) {
1827 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
1828 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
1829 }
1830 if (sctx->b.chip_class >= CIK) {
1831 color_pitch |= S_028C64_FMASK_TILE_MAX(rtex->fmask.pitch / 8 - 1);
1832 }
1833 }
1834 }
1835
1836 offset += rtex->resource.gpu_address;
1837
1838 surf->cb_color_base = offset >> 8;
1839 surf->cb_color_pitch = color_pitch;
1840 surf->cb_color_slice = S_028C68_TILE_MAX(slice);
1841 surf->cb_color_view = color_view;
1842 surf->cb_color_info = color_info;
1843 surf->cb_color_attrib = color_attrib;
1844
1845 if (rtex->fmask.size) {
1846 surf->cb_color_fmask = (offset + rtex->fmask.offset) >> 8;
1847 surf->cb_color_fmask_slice = S_028C88_TILE_MAX(rtex->fmask.slice_tile_max);
1848 } else {
1849 /* This must be set for fast clear to work without FMASK. */
1850 surf->cb_color_fmask = surf->cb_color_base;
1851 surf->cb_color_fmask_slice = surf->cb_color_slice;
1852 surf->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1853
1854 if (sctx->b.chip_class == SI) {
1855 unsigned bankh = util_logbase2(rtex->surface.bankh);
1856 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1857 }
1858
1859 if (sctx->b.chip_class >= CIK) {
1860 surf->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch);
1861 }
1862 }
1863
1864 /* Determine pixel shader export format */
1865 max_comp_size = si_colorformat_max_comp_size(format);
1866 if (ntype == V_028C70_NUMBER_SRGB ||
1867 ((ntype == V_028C70_NUMBER_UNORM || ntype == V_028C70_NUMBER_SNORM) &&
1868 max_comp_size <= 10) ||
1869 (ntype == V_028C70_NUMBER_FLOAT && max_comp_size <= 16)) {
1870 surf->export_16bpc = true;
1871 }
1872
1873 surf->color_initialized = true;
1874 }
1875
1876 static void si_init_depth_surface(struct si_context *sctx,
1877 struct r600_surface *surf)
1878 {
1879 struct si_screen *sscreen = sctx->screen;
1880 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1881 unsigned level = surf->base.u.tex.level;
1882 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
1883 unsigned format, tile_mode_index, array_mode;
1884 unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks, pipe_config;
1885 uint32_t z_info, s_info, db_depth_info;
1886 uint64_t z_offs, s_offs;
1887 uint32_t db_htile_data_base, db_htile_surface, pa_su_poly_offset_db_fmt_cntl = 0;
1888
1889 switch (sctx->framebuffer.state.zsbuf->texture->format) {
1890 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1891 case PIPE_FORMAT_X8Z24_UNORM:
1892 case PIPE_FORMAT_Z24X8_UNORM:
1893 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1894 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1895 break;
1896 case PIPE_FORMAT_Z32_FLOAT:
1897 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1898 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1899 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1900 break;
1901 case PIPE_FORMAT_Z16_UNORM:
1902 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1903 break;
1904 default:
1905 assert(0);
1906 }
1907
1908 format = si_translate_dbformat(rtex->resource.b.b.format);
1909
1910 if (format == V_028040_Z_INVALID) {
1911 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
1912 }
1913 assert(format != V_028040_Z_INVALID);
1914
1915 s_offs = z_offs = rtex->resource.gpu_address;
1916 z_offs += rtex->surface.level[level].offset;
1917 s_offs += rtex->surface.stencil_level[level].offset;
1918
1919 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1920
1921 z_info = S_028040_FORMAT(format);
1922 if (rtex->resource.b.b.nr_samples > 1) {
1923 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
1924 }
1925
1926 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1927 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
1928 else
1929 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1930
1931 if (sctx->b.chip_class >= CIK) {
1932 switch (rtex->surface.level[level].mode) {
1933 case RADEON_SURF_MODE_2D:
1934 array_mode = V_02803C_ARRAY_2D_TILED_THIN1;
1935 break;
1936 case RADEON_SURF_MODE_1D:
1937 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1938 case RADEON_SURF_MODE_LINEAR:
1939 default:
1940 array_mode = V_02803C_ARRAY_1D_TILED_THIN1;
1941 break;
1942 }
1943 tile_split = rtex->surface.tile_split;
1944 stile_split = rtex->surface.stencil_tile_split;
1945 macro_aspect = rtex->surface.mtilea;
1946 bankw = rtex->surface.bankw;
1947 bankh = rtex->surface.bankh;
1948 tile_split = cik_tile_split(tile_split);
1949 stile_split = cik_tile_split(stile_split);
1950 macro_aspect = cik_macro_tile_aspect(macro_aspect);
1951 bankw = cik_bank_wh(bankw);
1952 bankh = cik_bank_wh(bankh);
1953 nbanks = si_num_banks(sscreen, rtex);
1954 tile_mode_index = si_tile_mode_index(rtex, level, false);
1955 pipe_config = cik_db_pipe_config(sscreen, tile_mode_index);
1956
1957 db_depth_info |= S_02803C_ARRAY_MODE(array_mode) |
1958 S_02803C_PIPE_CONFIG(pipe_config) |
1959 S_02803C_BANK_WIDTH(bankw) |
1960 S_02803C_BANK_HEIGHT(bankh) |
1961 S_02803C_MACRO_TILE_ASPECT(macro_aspect) |
1962 S_02803C_NUM_BANKS(nbanks);
1963 z_info |= S_028040_TILE_SPLIT(tile_split);
1964 s_info |= S_028044_TILE_SPLIT(stile_split);
1965 } else {
1966 tile_mode_index = si_tile_mode_index(rtex, level, false);
1967 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1968 tile_mode_index = si_tile_mode_index(rtex, level, true);
1969 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1970 }
1971
1972 /* HiZ aka depth buffer htile */
1973 /* use htile only for first level */
1974 if (rtex->htile_buffer && !level) {
1975 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1976 S_028040_ALLOW_EXPCLEAR(1);
1977
1978 /* Use all of the htile_buffer for depth, because we don't
1979 * use HTILE for stencil because of FAST_STENCIL_DISABLE. */
1980 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
1981
1982 uint64_t va = rtex->htile_buffer->gpu_address;
1983 db_htile_data_base = va >> 8;
1984 db_htile_surface = S_028ABC_FULL_CACHE(1);
1985 } else {
1986 db_htile_data_base = 0;
1987 db_htile_surface = 0;
1988 }
1989
1990 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
1991
1992 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
1993 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
1994 surf->db_htile_data_base = db_htile_data_base;
1995 surf->db_depth_info = db_depth_info;
1996 surf->db_z_info = z_info;
1997 surf->db_stencil_info = s_info;
1998 surf->db_depth_base = z_offs >> 8;
1999 surf->db_stencil_base = s_offs >> 8;
2000 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2001 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2002 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2003 levelinfo->nblk_y) / 64 - 1);
2004 surf->db_htile_surface = db_htile_surface;
2005 surf->pa_su_poly_offset_db_fmt_cntl = pa_su_poly_offset_db_fmt_cntl;
2006
2007 surf->depth_initialized = true;
2008 }
2009
2010 static void si_set_framebuffer_state(struct pipe_context *ctx,
2011 const struct pipe_framebuffer_state *state)
2012 {
2013 struct si_context *sctx = (struct si_context *)ctx;
2014 struct pipe_constant_buffer constbuf = {0};
2015 struct r600_surface *surf = NULL;
2016 struct r600_texture *rtex;
2017 bool old_cb0_is_integer = sctx->framebuffer.cb0_is_integer;
2018 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2019 int i;
2020
2021 /* Only flush TC when changing the framebuffer state, because
2022 * the only client not using TC that can change textures is
2023 * the framebuffer.
2024 *
2025 * Flush all CB and DB caches here because all buffers can be used
2026 * for write by both TC (with shader image stores) and CB/DB.
2027 */
2028 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2029 SI_CONTEXT_INV_TC_L2 |
2030 SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER;
2031
2032 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2033
2034 sctx->framebuffer.export_16bpc = 0;
2035 sctx->framebuffer.compressed_cb_mask = 0;
2036 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2037 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2038 sctx->framebuffer.cb0_is_integer = state->nr_cbufs && state->cbufs[0] &&
2039 util_format_is_pure_integer(state->cbufs[0]->format);
2040
2041 if (sctx->framebuffer.cb0_is_integer != old_cb0_is_integer)
2042 sctx->db_render_state.dirty = true;
2043
2044 for (i = 0; i < state->nr_cbufs; i++) {
2045 if (!state->cbufs[i])
2046 continue;
2047
2048 surf = (struct r600_surface*)state->cbufs[i];
2049 rtex = (struct r600_texture*)surf->base.texture;
2050
2051 if (!surf->color_initialized) {
2052 si_initialize_color_surface(sctx, surf);
2053 }
2054
2055 if (surf->export_16bpc) {
2056 sctx->framebuffer.export_16bpc |= 1 << i;
2057 }
2058
2059 if (rtex->fmask.size && rtex->cmask.size) {
2060 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2061 }
2062 }
2063 /* Set the 16BPC export for possible dual-src blending. */
2064 if (i == 1 && surf && surf->export_16bpc) {
2065 sctx->framebuffer.export_16bpc |= 1 << 1;
2066 }
2067
2068 assert(!(sctx->framebuffer.export_16bpc & ~0xff));
2069
2070 if (state->zsbuf) {
2071 surf = (struct r600_surface*)state->zsbuf;
2072
2073 if (!surf->depth_initialized) {
2074 si_init_depth_surface(sctx, surf);
2075 }
2076 }
2077
2078 si_update_fb_rs_state(sctx);
2079 si_update_fb_blend_state(sctx);
2080
2081 sctx->framebuffer.atom.num_dw = state->nr_cbufs*15 + (8 - state->nr_cbufs)*3;
2082 sctx->framebuffer.atom.num_dw += state->zsbuf ? 26 : 4;
2083 sctx->framebuffer.atom.num_dw += 3; /* WINDOW_SCISSOR_BR */
2084 sctx->framebuffer.atom.num_dw += 18; /* MSAA sample locations */
2085 sctx->framebuffer.atom.dirty = true;
2086
2087 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2088 sctx->msaa_config.dirty = true;
2089 sctx->db_render_state.dirty = true;
2090
2091 /* Set sample locations as fragment shader constants. */
2092 switch (sctx->framebuffer.nr_samples) {
2093 case 1:
2094 constbuf.user_buffer = sctx->b.sample_locations_1x;
2095 break;
2096 case 2:
2097 constbuf.user_buffer = sctx->b.sample_locations_2x;
2098 break;
2099 case 4:
2100 constbuf.user_buffer = sctx->b.sample_locations_4x;
2101 break;
2102 case 8:
2103 constbuf.user_buffer = sctx->b.sample_locations_8x;
2104 break;
2105 case 16:
2106 constbuf.user_buffer = sctx->b.sample_locations_16x;
2107 break;
2108 default:
2109 assert(0);
2110 }
2111 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2112 ctx->set_constant_buffer(ctx, PIPE_SHADER_FRAGMENT,
2113 SI_DRIVER_STATE_CONST_BUF, &constbuf);
2114
2115 /* Smoothing (only possible with nr_samples == 1) uses the same
2116 * sample locations as the MSAA it simulates.
2117 *
2118 * Therefore, don't update the sample locations when
2119 * transitioning from no AA to smoothing-equivalent AA, and
2120 * vice versa.
2121 */
2122 if ((sctx->framebuffer.nr_samples != 1 ||
2123 old_nr_samples != SI_NUM_SMOOTH_AA_SAMPLES) &&
2124 (sctx->framebuffer.nr_samples != SI_NUM_SMOOTH_AA_SAMPLES ||
2125 old_nr_samples != 1))
2126 sctx->msaa_sample_locs.dirty = true;
2127 }
2128 }
2129
2130 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2131 {
2132 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2133 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2134 unsigned i, nr_cbufs = state->nr_cbufs;
2135 struct r600_texture *tex = NULL;
2136 struct r600_surface *cb = NULL;
2137
2138 /* Colorbuffers. */
2139 for (i = 0; i < nr_cbufs; i++) {
2140 cb = (struct r600_surface*)state->cbufs[i];
2141 if (!cb) {
2142 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2143 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2144 continue;
2145 }
2146
2147 tex = (struct r600_texture *)cb->base.texture;
2148 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2149 &tex->resource, RADEON_USAGE_READWRITE,
2150 tex->surface.nsamples > 1 ?
2151 RADEON_PRIO_COLOR_BUFFER_MSAA :
2152 RADEON_PRIO_COLOR_BUFFER);
2153
2154 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2155 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2156 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2157 RADEON_PRIO_COLOR_META);
2158 }
2159
2160 r600_write_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 13);
2161 radeon_emit(cs, cb->cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2162 radeon_emit(cs, cb->cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2163 radeon_emit(cs, cb->cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2164 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2165 radeon_emit(cs, cb->cb_color_info | tex->cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2166 radeon_emit(cs, cb->cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2167 radeon_emit(cs, 0); /* R_028C78 unused */
2168 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2169 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2170 radeon_emit(cs, cb->cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2171 radeon_emit(cs, cb->cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2172 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2173 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2174 }
2175 /* set CB_COLOR1_INFO for possible dual-src blending */
2176 if (i == 1 && state->cbufs[0]) {
2177 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + 1 * 0x3C,
2178 cb->cb_color_info | tex->cb_color_info);
2179 i++;
2180 }
2181 for (; i < 8 ; i++) {
2182 r600_write_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2183 }
2184
2185 /* ZS buffer. */
2186 if (state->zsbuf) {
2187 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2188 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2189
2190 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2191 &rtex->resource, RADEON_USAGE_READWRITE,
2192 zb->base.texture->nr_samples > 1 ?
2193 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2194 RADEON_PRIO_DEPTH_BUFFER);
2195
2196 if (zb->db_htile_data_base) {
2197 r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
2198 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2199 RADEON_PRIO_DEPTH_META);
2200 }
2201
2202 r600_write_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2203 r600_write_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2204
2205 r600_write_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2206 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2207 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2208 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2209 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2210 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2211 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2212 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2213 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2214 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2215 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2216
2217 r600_write_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2218 r600_write_context_reg(cs, R_02802C_DB_DEPTH_CLEAR, fui(rtex->depth_clear_value));
2219 r600_write_context_reg(cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
2220 zb->pa_su_poly_offset_db_fmt_cntl);
2221 } else {
2222 r600_write_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2223 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2224 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2225 }
2226
2227 /* Framebuffer dimensions. */
2228 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2229 r600_write_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2230 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2231 }
2232
2233 static void si_emit_msaa_sample_locs(struct r600_common_context *rctx,
2234 struct r600_atom *atom)
2235 {
2236 struct si_context *sctx = (struct si_context *)rctx;
2237 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2238 unsigned nr_samples = sctx->framebuffer.nr_samples;
2239
2240 cayman_emit_msaa_sample_locs(cs, nr_samples > 1 ? nr_samples :
2241 SI_NUM_SMOOTH_AA_SAMPLES);
2242 }
2243
2244 const struct r600_atom si_atom_msaa_sample_locs = { si_emit_msaa_sample_locs, 18 }; /* number of CS dwords */
2245
2246 static void si_emit_msaa_config(struct r600_common_context *rctx, struct r600_atom *atom)
2247 {
2248 struct si_context *sctx = (struct si_context *)rctx;
2249 struct radeon_winsys_cs *cs = sctx->b.rings.gfx.cs;
2250
2251 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2252 sctx->ps_iter_samples,
2253 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0);
2254 }
2255
2256 const struct r600_atom si_atom_msaa_config = { si_emit_msaa_config, 10 }; /* number of CS dwords */
2257
2258 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2259 {
2260 struct si_context *sctx = (struct si_context *)ctx;
2261
2262 if (sctx->ps_iter_samples == min_samples)
2263 return;
2264
2265 sctx->ps_iter_samples = min_samples;
2266
2267 if (sctx->framebuffer.nr_samples > 1)
2268 sctx->msaa_config.dirty = true;
2269 }
2270
2271 /*
2272 * Samplers
2273 */
2274
2275 /**
2276 * Create a sampler view.
2277 *
2278 * @param ctx context
2279 * @param texture texture
2280 * @param state sampler view template
2281 * @param width0 width0 override (for compressed textures as int)
2282 * @param height0 height0 override (for compressed textures as int)
2283 * @param force_level set the base address to the level (for compressed textures)
2284 */
2285 struct pipe_sampler_view *
2286 si_create_sampler_view_custom(struct pipe_context *ctx,
2287 struct pipe_resource *texture,
2288 const struct pipe_sampler_view *state,
2289 unsigned width0, unsigned height0,
2290 unsigned force_level)
2291 {
2292 struct si_context *sctx = (struct si_context*)ctx;
2293 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
2294 struct r600_texture *tmp = (struct r600_texture*)texture;
2295 const struct util_format_description *desc;
2296 unsigned format, num_format, base_level, first_level, last_level;
2297 uint32_t pitch = 0;
2298 unsigned char state_swizzle[4], swizzle[4];
2299 unsigned height, depth, width;
2300 enum pipe_format pipe_format = state->format;
2301 struct radeon_surf_level *surflevel;
2302 int first_non_void;
2303 uint64_t va;
2304
2305 if (view == NULL)
2306 return NULL;
2307
2308 /* initialize base object */
2309 view->base = *state;
2310 view->base.texture = NULL;
2311 view->base.reference.count = 1;
2312 view->base.context = ctx;
2313
2314 /* NULL resource, obey swizzle (only ZERO and ONE make sense). */
2315 if (!texture) {
2316 view->state[3] = S_008F1C_DST_SEL_X(si_map_swizzle(state->swizzle_r)) |
2317 S_008F1C_DST_SEL_Y(si_map_swizzle(state->swizzle_g)) |
2318 S_008F1C_DST_SEL_Z(si_map_swizzle(state->swizzle_b)) |
2319 S_008F1C_DST_SEL_W(si_map_swizzle(state->swizzle_a)) |
2320 S_008F1C_TYPE(V_008F1C_SQ_RSRC_IMG_1D);
2321 return &view->base;
2322 }
2323
2324 pipe_resource_reference(&view->base.texture, texture);
2325 view->resource = &tmp->resource;
2326
2327 /* Buffer resource. */
2328 if (texture->target == PIPE_BUFFER) {
2329 unsigned stride;
2330
2331 desc = util_format_description(state->format);
2332 first_non_void = util_format_get_first_non_void_channel(state->format);
2333 stride = desc->block.bits / 8;
2334 va = tmp->resource.gpu_address + state->u.buf.first_element*stride;
2335 format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2336 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2337
2338 view->state[4] = va;
2339 view->state[5] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
2340 S_008F04_STRIDE(stride);
2341 view->state[6] = state->u.buf.last_element + 1 - state->u.buf.first_element;
2342 view->state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2343 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2344 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2345 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2346 S_008F0C_NUM_FORMAT(num_format) |
2347 S_008F0C_DATA_FORMAT(format);
2348
2349 LIST_ADDTAIL(&view->list, &sctx->b.texture_buffers);
2350 return &view->base;
2351 }
2352
2353 state_swizzle[0] = state->swizzle_r;
2354 state_swizzle[1] = state->swizzle_g;
2355 state_swizzle[2] = state->swizzle_b;
2356 state_swizzle[3] = state->swizzle_a;
2357
2358 surflevel = tmp->surface.level;
2359
2360 /* Texturing with separate depth and stencil. */
2361 if (tmp->is_depth && !tmp->is_flushing_texture) {
2362 switch (pipe_format) {
2363 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
2364 pipe_format = PIPE_FORMAT_Z32_FLOAT;
2365 break;
2366 case PIPE_FORMAT_X8Z24_UNORM:
2367 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2368 /* Z24 is always stored like this. */
2369 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
2370 break;
2371 case PIPE_FORMAT_X24S8_UINT:
2372 case PIPE_FORMAT_S8X24_UINT:
2373 case PIPE_FORMAT_X32_S8X24_UINT:
2374 pipe_format = PIPE_FORMAT_S8_UINT;
2375 surflevel = tmp->surface.stencil_level;
2376 break;
2377 default:;
2378 }
2379 }
2380
2381 desc = util_format_description(pipe_format);
2382
2383 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2384 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2385 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2386
2387 switch (pipe_format) {
2388 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2389 case PIPE_FORMAT_X24S8_UINT:
2390 case PIPE_FORMAT_X32_S8X24_UINT:
2391 case PIPE_FORMAT_X8Z24_UNORM:
2392 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2393 break;
2394 default:
2395 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2396 }
2397 } else {
2398 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2399 }
2400
2401 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2402
2403 switch (pipe_format) {
2404 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2405 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2406 break;
2407 default:
2408 if (first_non_void < 0) {
2409 if (util_format_is_compressed(pipe_format)) {
2410 switch (pipe_format) {
2411 case PIPE_FORMAT_DXT1_SRGB:
2412 case PIPE_FORMAT_DXT1_SRGBA:
2413 case PIPE_FORMAT_DXT3_SRGBA:
2414 case PIPE_FORMAT_DXT5_SRGBA:
2415 case PIPE_FORMAT_BPTC_SRGBA:
2416 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2417 break;
2418 case PIPE_FORMAT_RGTC1_SNORM:
2419 case PIPE_FORMAT_LATC1_SNORM:
2420 case PIPE_FORMAT_RGTC2_SNORM:
2421 case PIPE_FORMAT_LATC2_SNORM:
2422 /* implies float, so use SNORM/UNORM to determine
2423 whether data is signed or not */
2424 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2425 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2426 break;
2427 default:
2428 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2429 break;
2430 }
2431 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2432 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2433 } else {
2434 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2435 }
2436 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2437 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2438 } else {
2439 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2440
2441 switch (desc->channel[first_non_void].type) {
2442 case UTIL_FORMAT_TYPE_FLOAT:
2443 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2444 break;
2445 case UTIL_FORMAT_TYPE_SIGNED:
2446 if (desc->channel[first_non_void].normalized)
2447 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2448 else if (desc->channel[first_non_void].pure_integer)
2449 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2450 else
2451 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2452 break;
2453 case UTIL_FORMAT_TYPE_UNSIGNED:
2454 if (desc->channel[first_non_void].normalized)
2455 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2456 else if (desc->channel[first_non_void].pure_integer)
2457 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2458 else
2459 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2460 }
2461 }
2462 }
2463
2464 format = si_translate_texformat(ctx->screen, pipe_format, desc, first_non_void);
2465 if (format == ~0) {
2466 format = 0;
2467 }
2468
2469 base_level = 0;
2470 first_level = state->u.tex.first_level;
2471 last_level = state->u.tex.last_level;
2472 width = width0;
2473 height = height0;
2474 depth = texture->depth0;
2475
2476 if (force_level) {
2477 assert(force_level == first_level &&
2478 force_level == last_level);
2479 base_level = force_level;
2480 first_level = 0;
2481 last_level = 0;
2482 width = u_minify(width, force_level);
2483 height = u_minify(height, force_level);
2484 depth = u_minify(depth, force_level);
2485 }
2486
2487 pitch = surflevel[base_level].nblk_x * util_format_get_blockwidth(pipe_format);
2488
2489 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
2490 height = 1;
2491 depth = texture->array_size;
2492 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
2493 depth = texture->array_size;
2494 } else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
2495 depth = texture->array_size / 6;
2496
2497 va = tmp->resource.gpu_address + surflevel[base_level].offset;
2498
2499 view->state[0] = va >> 8;
2500 view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
2501 S_008F14_DATA_FORMAT(format) |
2502 S_008F14_NUM_FORMAT(num_format));
2503 view->state[2] = (S_008F18_WIDTH(width - 1) |
2504 S_008F18_HEIGHT(height - 1));
2505 view->state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2506 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2507 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2508 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2509 S_008F1C_BASE_LEVEL(texture->nr_samples > 1 ?
2510 0 : first_level) |
2511 S_008F1C_LAST_LEVEL(texture->nr_samples > 1 ?
2512 util_logbase2(texture->nr_samples) :
2513 last_level) |
2514 S_008F1C_TILING_INDEX(si_tile_mode_index(tmp, 0, false)) |
2515 S_008F1C_POW2_PAD(texture->last_level > 0) |
2516 S_008F1C_TYPE(si_tex_dim(texture->target, texture->nr_samples)));
2517 view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
2518 view->state[5] = (S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2519 S_008F24_LAST_ARRAY(state->u.tex.last_layer));
2520 view->state[6] = 0;
2521 view->state[7] = 0;
2522
2523 /* Initialize the sampler view for FMASK. */
2524 if (tmp->fmask.size) {
2525 uint64_t va = tmp->resource.gpu_address + tmp->fmask.offset;
2526 uint32_t fmask_format;
2527
2528 switch (texture->nr_samples) {
2529 case 2:
2530 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2531 break;
2532 case 4:
2533 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2534 break;
2535 case 8:
2536 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2537 break;
2538 default:
2539 assert(0);
2540 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2541 }
2542
2543 view->fmask_state[0] = va >> 8;
2544 view->fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2545 S_008F14_DATA_FORMAT(fmask_format) |
2546 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2547 view->fmask_state[2] = S_008F18_WIDTH(width - 1) |
2548 S_008F18_HEIGHT(height - 1);
2549 view->fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2550 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2551 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
2552 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
2553 S_008F1C_TILING_INDEX(tmp->fmask.tile_mode_index) |
2554 S_008F1C_TYPE(si_tex_dim(texture->target, 0));
2555 view->fmask_state[4] = S_008F20_DEPTH(depth - 1) |
2556 S_008F20_PITCH(tmp->fmask.pitch - 1);
2557 view->fmask_state[5] = S_008F24_BASE_ARRAY(state->u.tex.first_layer) |
2558 S_008F24_LAST_ARRAY(state->u.tex.last_layer);
2559 view->fmask_state[6] = 0;
2560 view->fmask_state[7] = 0;
2561 }
2562
2563 return &view->base;
2564 }
2565
2566 static struct pipe_sampler_view *
2567 si_create_sampler_view(struct pipe_context *ctx,
2568 struct pipe_resource *texture,
2569 const struct pipe_sampler_view *state)
2570 {
2571 return si_create_sampler_view_custom(ctx, texture, state,
2572 texture ? texture->width0 : 0,
2573 texture ? texture->height0 : 0, 0);
2574 }
2575
2576 static void si_sampler_view_destroy(struct pipe_context *ctx,
2577 struct pipe_sampler_view *state)
2578 {
2579 struct si_sampler_view *view = (struct si_sampler_view *)state;
2580
2581 if (view->resource && view->resource->b.b.target == PIPE_BUFFER)
2582 LIST_DELINIT(&view->list);
2583
2584 pipe_resource_reference(&state->texture, NULL);
2585 FREE(view);
2586 }
2587
2588 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
2589 {
2590 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
2591 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
2592 (linear_filter &&
2593 (wrap == PIPE_TEX_WRAP_CLAMP ||
2594 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
2595 }
2596
2597 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
2598 {
2599 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
2600 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
2601
2602 return (state->border_color.ui[0] || state->border_color.ui[1] ||
2603 state->border_color.ui[2] || state->border_color.ui[3]) &&
2604 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
2605 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
2606 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
2607 }
2608
2609 static void *si_create_sampler_state(struct pipe_context *ctx,
2610 const struct pipe_sampler_state *state)
2611 {
2612 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
2613 unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 2 : 0;
2614 unsigned border_color_type;
2615
2616 if (rstate == NULL) {
2617 return NULL;
2618 }
2619
2620 if (sampler_state_needs_border_color(state))
2621 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
2622 else
2623 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2624
2625 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
2626 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
2627 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
2628 r600_tex_aniso_filter(state->max_anisotropy) << 9 |
2629 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
2630 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
2631 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map));
2632 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
2633 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)));
2634 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
2635 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
2636 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter) | aniso_flag_offset) |
2637 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)));
2638 rstate->val[3] = S_008F3C_BORDER_COLOR_TYPE(border_color_type);
2639
2640 if (border_color_type == V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2641 memcpy(rstate->border_color, state->border_color.ui,
2642 sizeof(rstate->border_color));
2643 }
2644
2645 return rstate;
2646 }
2647
2648 /* Upload border colors and update the pointers in resource descriptors.
2649 * There can only be 4096 border colors per context.
2650 *
2651 * XXX: This is broken if the buffer gets reallocated.
2652 */
2653 static void si_set_border_colors(struct si_context *sctx, unsigned count,
2654 void **states)
2655 {
2656 struct si_sampler_state **rstates = (struct si_sampler_state **)states;
2657 uint32_t *border_color_table = NULL;
2658 int i, j;
2659
2660 for (i = 0; i < count; i++) {
2661 if (rstates[i] &&
2662 G_008F3C_BORDER_COLOR_TYPE(rstates[i]->val[3]) ==
2663 V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER) {
2664 if (!sctx->border_color_table ||
2665 ((sctx->border_color_offset + count - i) &
2666 C_008F3C_BORDER_COLOR_PTR)) {
2667 r600_resource_reference(&sctx->border_color_table, NULL);
2668 sctx->border_color_offset = 0;
2669
2670 sctx->border_color_table =
2671 si_resource_create_custom(&sctx->screen->b.b,
2672 PIPE_USAGE_DYNAMIC,
2673 4096 * 4 * 4);
2674 }
2675
2676 if (!border_color_table) {
2677 border_color_table =
2678 sctx->b.ws->buffer_map(sctx->border_color_table->cs_buf,
2679 sctx->b.rings.gfx.cs,
2680 PIPE_TRANSFER_WRITE |
2681 PIPE_TRANSFER_UNSYNCHRONIZED);
2682 }
2683
2684 for (j = 0; j < 4; j++) {
2685 border_color_table[4 * sctx->border_color_offset + j] =
2686 util_le32_to_cpu(rstates[i]->border_color[j]);
2687 }
2688
2689 rstates[i]->val[3] &= C_008F3C_BORDER_COLOR_PTR;
2690 rstates[i]->val[3] |= S_008F3C_BORDER_COLOR_PTR(sctx->border_color_offset++);
2691 }
2692 }
2693
2694 if (border_color_table) {
2695 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
2696
2697 uint64_t va_offset = sctx->border_color_table->gpu_address;
2698
2699 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8);
2700 if (sctx->b.chip_class >= CIK)
2701 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40);
2702 si_pm4_add_bo(pm4, sctx->border_color_table, RADEON_USAGE_READ,
2703 RADEON_PRIO_SHADER_DATA);
2704 si_pm4_set_state(sctx, ta_bordercolor_base, pm4);
2705 }
2706 }
2707
2708 static void si_bind_sampler_states(struct pipe_context *ctx, unsigned shader,
2709 unsigned start, unsigned count,
2710 void **states)
2711 {
2712 struct si_context *sctx = (struct si_context *)ctx;
2713
2714 if (!count || shader >= SI_NUM_SHADERS)
2715 return;
2716
2717 si_set_border_colors(sctx, count, states);
2718 si_set_sampler_descriptors(sctx, shader, start, count, states);
2719 }
2720
2721 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
2722 {
2723 struct si_context *sctx = (struct si_context *)ctx;
2724 struct si_state_sample_mask *state = CALLOC_STRUCT(si_state_sample_mask);
2725 struct si_pm4_state *pm4 = &state->pm4;
2726 uint16_t mask = sample_mask;
2727
2728 if (state == NULL)
2729 return;
2730
2731 state->sample_mask = mask;
2732 si_pm4_set_reg(pm4, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, mask | (mask << 16));
2733 si_pm4_set_reg(pm4, R_028C3C_PA_SC_AA_MASK_X0Y1_X1Y1, mask | (mask << 16));
2734
2735 si_pm4_set_state(sctx, sample_mask, state);
2736 }
2737
2738 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
2739 {
2740 free(state);
2741 }
2742
2743 /*
2744 * Vertex elements & buffers
2745 */
2746
2747 static void *si_create_vertex_elements(struct pipe_context *ctx,
2748 unsigned count,
2749 const struct pipe_vertex_element *elements)
2750 {
2751 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
2752 int i;
2753
2754 assert(count < PIPE_MAX_ATTRIBS);
2755 if (!v)
2756 return NULL;
2757
2758 v->count = count;
2759 for (i = 0; i < count; ++i) {
2760 const struct util_format_description *desc;
2761 unsigned data_format, num_format;
2762 int first_non_void;
2763
2764 desc = util_format_description(elements[i].src_format);
2765 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
2766 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
2767 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
2768
2769 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2770 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2771 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2772 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2773 S_008F0C_NUM_FORMAT(num_format) |
2774 S_008F0C_DATA_FORMAT(data_format);
2775 v->format_size[i] = desc->block.bits / 8;
2776 }
2777 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
2778
2779 return v;
2780 }
2781
2782 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
2783 {
2784 struct si_context *sctx = (struct si_context *)ctx;
2785 struct si_vertex_element *v = (struct si_vertex_element*)state;
2786
2787 sctx->vertex_elements = v;
2788 sctx->vertex_buffers_dirty = true;
2789 }
2790
2791 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
2792 {
2793 struct si_context *sctx = (struct si_context *)ctx;
2794
2795 if (sctx->vertex_elements == state)
2796 sctx->vertex_elements = NULL;
2797 FREE(state);
2798 }
2799
2800 static void si_set_vertex_buffers(struct pipe_context *ctx,
2801 unsigned start_slot, unsigned count,
2802 const struct pipe_vertex_buffer *buffers)
2803 {
2804 struct si_context *sctx = (struct si_context *)ctx;
2805 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
2806 int i;
2807
2808 assert(start_slot + count <= Elements(sctx->vertex_buffer));
2809
2810 if (buffers) {
2811 for (i = 0; i < count; i++) {
2812 const struct pipe_vertex_buffer *src = buffers + i;
2813 struct pipe_vertex_buffer *dsti = dst + i;
2814
2815 pipe_resource_reference(&dsti->buffer, src->buffer);
2816 dsti->buffer_offset = src->buffer_offset;
2817 dsti->stride = src->stride;
2818 }
2819 } else {
2820 for (i = 0; i < count; i++) {
2821 pipe_resource_reference(&dst[i].buffer, NULL);
2822 }
2823 }
2824 sctx->vertex_buffers_dirty = true;
2825 }
2826
2827 static void si_set_index_buffer(struct pipe_context *ctx,
2828 const struct pipe_index_buffer *ib)
2829 {
2830 struct si_context *sctx = (struct si_context *)ctx;
2831
2832 if (ib) {
2833 pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer);
2834 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
2835 } else {
2836 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
2837 }
2838 }
2839
2840 /*
2841 * Misc
2842 */
2843 static void si_set_polygon_stipple(struct pipe_context *ctx,
2844 const struct pipe_poly_stipple *state)
2845 {
2846 struct si_context *sctx = (struct si_context *)ctx;
2847 struct pipe_resource *tex;
2848 struct pipe_sampler_view *view;
2849 bool is_zero = true;
2850 bool is_one = true;
2851 int i;
2852
2853 /* The hardware obeys 0 and 1 swizzles in the descriptor even if
2854 * the resource is NULL/invalid. Take advantage of this fact and skip
2855 * texture allocation if the stipple pattern is constant.
2856 *
2857 * This is an optimization for the common case when stippling isn't
2858 * used but set_polygon_stipple is still called by st/mesa.
2859 */
2860 for (i = 0; i < Elements(state->stipple); i++) {
2861 is_zero = is_zero && state->stipple[i] == 0;
2862 is_one = is_one && state->stipple[i] == 0xffffffff;
2863 }
2864
2865 if (is_zero || is_one) {
2866 struct pipe_sampler_view templ = {{0}};
2867
2868 templ.swizzle_r = PIPE_SWIZZLE_ZERO;
2869 templ.swizzle_g = PIPE_SWIZZLE_ZERO;
2870 templ.swizzle_b = PIPE_SWIZZLE_ZERO;
2871 /* The pattern should be inverted in the texture. */
2872 templ.swizzle_a = is_zero ? PIPE_SWIZZLE_ONE : PIPE_SWIZZLE_ZERO;
2873
2874 view = ctx->create_sampler_view(ctx, NULL, &templ);
2875 } else {
2876 /* Create a new texture. */
2877 tex = util_pstipple_create_stipple_texture(ctx, state->stipple);
2878 if (!tex)
2879 return;
2880
2881 view = util_pstipple_create_sampler_view(ctx, tex);
2882 pipe_resource_reference(&tex, NULL);
2883 }
2884
2885 ctx->set_sampler_views(ctx, PIPE_SHADER_FRAGMENT,
2886 SI_POLY_STIPPLE_SAMPLER, 1, &view);
2887 pipe_sampler_view_reference(&view, NULL);
2888
2889 /* Bind the sampler state if needed. */
2890 if (!sctx->pstipple_sampler_state) {
2891 sctx->pstipple_sampler_state = util_pstipple_create_sampler(ctx);
2892 ctx->bind_sampler_states(ctx, PIPE_SHADER_FRAGMENT,
2893 SI_POLY_STIPPLE_SAMPLER, 1,
2894 &sctx->pstipple_sampler_state);
2895 }
2896 }
2897
2898 static void si_texture_barrier(struct pipe_context *ctx)
2899 {
2900 struct si_context *sctx = (struct si_context *)ctx;
2901
2902 sctx->b.flags |= SI_CONTEXT_INV_TC_L1 |
2903 SI_CONTEXT_INV_TC_L2 |
2904 SI_CONTEXT_FLUSH_AND_INV_CB;
2905 }
2906
2907 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
2908 {
2909 struct pipe_blend_state blend;
2910
2911 memset(&blend, 0, sizeof(blend));
2912 blend.independent_blend_enable = true;
2913 blend.rt[0].colormask = 0xf;
2914 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
2915 }
2916
2917 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
2918 bool include_draw_vbo)
2919 {
2920 si_need_cs_space((struct si_context*)ctx, num_dw, include_draw_vbo);
2921 }
2922
2923 void si_init_state_functions(struct si_context *sctx)
2924 {
2925 si_init_atom(&sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state, 0);
2926 si_init_atom(&sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state, 10);
2927 si_init_atom(&sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs, 6);
2928
2929 sctx->b.b.create_blend_state = si_create_blend_state;
2930 sctx->b.b.bind_blend_state = si_bind_blend_state;
2931 sctx->b.b.delete_blend_state = si_delete_blend_state;
2932 sctx->b.b.set_blend_color = si_set_blend_color;
2933
2934 sctx->b.b.create_rasterizer_state = si_create_rs_state;
2935 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
2936 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
2937
2938 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
2939 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
2940 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
2941
2942 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
2943 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
2944 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
2945 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
2946
2947 sctx->b.b.set_clip_state = si_set_clip_state;
2948 sctx->b.b.set_scissor_states = si_set_scissor_states;
2949 sctx->b.b.set_viewport_states = si_set_viewport_states;
2950 sctx->b.b.set_stencil_ref = si_set_pipe_stencil_ref;
2951
2952 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
2953 sctx->b.b.get_sample_position = cayman_get_sample_position;
2954
2955 sctx->b.b.create_sampler_state = si_create_sampler_state;
2956 sctx->b.b.bind_sampler_states = si_bind_sampler_states;
2957 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
2958
2959 sctx->b.b.create_sampler_view = si_create_sampler_view;
2960 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
2961
2962 sctx->b.b.set_sample_mask = si_set_sample_mask;
2963
2964 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
2965 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
2966 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
2967 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
2968 sctx->b.b.set_index_buffer = si_set_index_buffer;
2969
2970 sctx->b.b.texture_barrier = si_texture_barrier;
2971 sctx->b.b.set_polygon_stipple = si_set_polygon_stipple;
2972 sctx->b.b.set_min_samples = si_set_min_samples;
2973
2974 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
2975 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
2976
2977 sctx->b.b.draw_vbo = si_draw_vbo;
2978
2979 if (sctx->b.chip_class >= CIK) {
2980 sctx->b.dma_copy = cik_sdma_copy;
2981 } else {
2982 sctx->b.dma_copy = si_dma_copy;
2983 }
2984 }
2985
2986 static void
2987 si_write_harvested_raster_configs(struct si_context *sctx,
2988 struct si_pm4_state *pm4,
2989 unsigned raster_config)
2990 {
2991 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
2992 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
2993 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
2994 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
2995 unsigned rb_per_pkr = num_rb / num_se / sh_per_se;
2996 unsigned rb_per_se = num_rb / num_se;
2997 unsigned se0_mask = (1 << rb_per_se) - 1;
2998 unsigned se1_mask = se0_mask << rb_per_se;
2999 unsigned se;
3000
3001 assert(num_se == 1 || num_se == 2);
3002 assert(sh_per_se == 1 || sh_per_se == 2);
3003 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3004
3005 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3006 * fields are for, so I'm leaving them as their default
3007 * values. */
3008
3009 se0_mask &= rb_mask;
3010 se1_mask &= rb_mask;
3011 if (num_se == 2 && (!se0_mask || !se1_mask)) {
3012 raster_config &= C_028350_SE_MAP;
3013
3014 if (!se0_mask) {
3015 raster_config |=
3016 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3017 } else {
3018 raster_config |=
3019 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3020 }
3021 }
3022
3023 for (se = 0; se < num_se; se++) {
3024 unsigned raster_config_se = raster_config;
3025 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3026 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3027
3028 pkr0_mask &= rb_mask;
3029 pkr1_mask &= rb_mask;
3030 if (sh_per_se == 2 && (!pkr0_mask || !pkr1_mask)) {
3031 raster_config_se &= C_028350_PKR_MAP;
3032
3033 if (!pkr0_mask) {
3034 raster_config_se |=
3035 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3036 } else {
3037 raster_config_se |=
3038 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3039 }
3040 }
3041
3042 if (rb_per_pkr == 2) {
3043 unsigned rb0_mask = 1 << (se * rb_per_se);
3044 unsigned rb1_mask = rb0_mask << 1;
3045
3046 rb0_mask &= rb_mask;
3047 rb1_mask &= rb_mask;
3048 if (!rb0_mask || !rb1_mask) {
3049 raster_config_se &= C_028350_RB_MAP_PKR0;
3050
3051 if (!rb0_mask) {
3052 raster_config_se |=
3053 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3054 } else {
3055 raster_config_se |=
3056 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3057 }
3058 }
3059
3060 if (sh_per_se == 2) {
3061 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3062 rb1_mask = rb0_mask << 1;
3063 rb0_mask &= rb_mask;
3064 rb1_mask &= rb_mask;
3065 if (!rb0_mask || !rb1_mask) {
3066 raster_config_se &= C_028350_RB_MAP_PKR1;
3067
3068 if (!rb0_mask) {
3069 raster_config_se |=
3070 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3071 } else {
3072 raster_config_se |=
3073 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3074 }
3075 }
3076 }
3077 }
3078
3079 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3080 SE_INDEX(se) | SH_BROADCAST_WRITES |
3081 INSTANCE_BROADCAST_WRITES);
3082 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3083 }
3084
3085 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3086 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3087 INSTANCE_BROADCAST_WRITES);
3088 }
3089
3090 void si_init_config(struct si_context *sctx)
3091 {
3092 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3093
3094 if (pm4 == NULL)
3095 return;
3096
3097 si_cmd_context_control(pm4);
3098
3099 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x0);
3100 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x0);
3101
3102 /* FIXME calculate these values somehow ??? */
3103 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, 0x80);
3104 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3105 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3106
3107 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0x0);
3108 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3109 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0);
3110 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3111
3112 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, 0);
3113 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, 0);
3114 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, 0);
3115
3116 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3117 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
3118 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3119 if (sctx->b.chip_class < CIK)
3120 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3121 S_008A14_CLIP_VTX_REORDER_ENA(1));
3122
3123 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3124 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3125
3126 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3127
3128 if (sctx->b.chip_class >= CIK) {
3129 switch (sctx->screen->b.family) {
3130 case CHIP_BONAIRE:
3131 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x16000012);
3132 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3133 break;
3134 case CHIP_HAWAII:
3135 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a);
3136 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x0000002e);
3137 break;
3138 case CHIP_KAVERI:
3139 /* XXX todo */
3140 case CHIP_KABINI:
3141 /* XXX todo */
3142 case CHIP_MULLINS:
3143 /* XXX todo */
3144 default:
3145 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
3146 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
3147 break;
3148 }
3149 } else {
3150 unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
3151 unsigned num_rb = sctx->screen->b.info.r600_num_backends;
3152 unsigned raster_config;
3153
3154 switch (sctx->screen->b.family) {
3155 case CHIP_TAHITI:
3156 case CHIP_PITCAIRN:
3157 raster_config = 0x2a00126a;
3158 break;
3159 case CHIP_VERDE:
3160 raster_config = 0x0000124a;
3161 break;
3162 case CHIP_OLAND:
3163 raster_config = 0x00000082;
3164 break;
3165 case CHIP_HAINAN:
3166 raster_config = 0;
3167 break;
3168 default:
3169 fprintf(stderr,
3170 "radeonsi: Unknown GPU, using 0 for raster_config\n");
3171 raster_config = 0;
3172 break;
3173 }
3174
3175 /* Always use the default config when all backends are enabled
3176 * (or when we failed to determine the enabled backends).
3177 */
3178 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
3179 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
3180 raster_config);
3181 } else {
3182 si_write_harvested_raster_configs(sctx, pm4, raster_config);
3183 }
3184 }
3185
3186 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
3187 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
3188 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
3189 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
3190 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
3191 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
3192 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
3193
3194 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
3195 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
3196 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
3197 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
3198 si_pm4_set_reg(pm4, R_0282D0_PA_SC_VPORT_ZMIN_0, 0);
3199 si_pm4_set_reg(pm4, R_0282D4_PA_SC_VPORT_ZMAX_0, fui(1.0));
3200 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
3201 si_pm4_set_reg(pm4, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, fui(1.0));
3202 si_pm4_set_reg(pm4, R_028BEC_PA_CL_GB_VERT_DISC_ADJ, fui(1.0));
3203 si_pm4_set_reg(pm4, R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, fui(1.0));
3204 si_pm4_set_reg(pm4, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ, fui(1.0));
3205 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, 0);
3206 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, 0);
3207 si_pm4_set_reg(pm4, R_028028_DB_STENCIL_CLEAR, 0);
3208 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
3209 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
3210 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
3211
3212 /* There is a hang if stencil is used and fast stencil is enabled
3213 * regardless of whether HTILE is depth-only or not.
3214 */
3215 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE,
3216 S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3217 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE) |
3218 S_02800C_FAST_STENCIL_DISABLE(1));
3219
3220 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
3221 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
3222 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
3223
3224 if (sctx->b.chip_class >= CIK) {
3225 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
3226 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(0));
3227 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
3228 }
3229
3230 sctx->init_config = pm4;
3231 }