projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi: don't update dependent states if it has no effect (v2)
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "gfx9d.h"
30 #include "radeon/r600_cs.h"
31 #include "radeon/r600_query.h"
32
33 #include "util/u_dual_blend.h"
34 #include "util/u_format.h"
35 #include "util/u_format_s3tc.h"
36 #include "util/u_memory.h"
37 #include "util/u_resource.h"
38 #include "util/u_upload_mgr.h"
39
40 /* Initialize an external atom (owned by ../radeon). */
41 static void
42 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
43 struct r600_atom **list_elem)
44 {
45 atom->id = list_elem - sctx->atoms.array;
46 *list_elem = atom;
47 }
48
49 /* Initialize an atom owned by radeonsi. */
50 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
51 struct r600_atom **list_elem,
52 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
53 {
54 atom->emit = (void*)emit_func;
55 atom->id = list_elem - sctx->atoms.array;
56 *list_elem = atom;
57 }
58
59 static unsigned si_map_swizzle(unsigned swizzle)
60 {
61 switch (swizzle) {
62 case PIPE_SWIZZLE_Y:
63 return V_008F0C_SQ_SEL_Y;
64 case PIPE_SWIZZLE_Z:
65 return V_008F0C_SQ_SEL_Z;
66 case PIPE_SWIZZLE_W:
67 return V_008F0C_SQ_SEL_W;
68 case PIPE_SWIZZLE_0:
69 return V_008F0C_SQ_SEL_0;
70 case PIPE_SWIZZLE_1:
71 return V_008F0C_SQ_SEL_1;
72 default: /* PIPE_SWIZZLE_X */
73 return V_008F0C_SQ_SEL_X;
74 }
75 }
76
77 static uint32_t S_FIXED(float value, uint32_t frac_bits)
78 {
79 return value * (1 << frac_bits);
80 }
81
82 /* 12.4 fixed-point */
83 static unsigned si_pack_float_12p4(float x)
84 {
85 return x <= 0 ? 0 :
86 x >= 4096 ? 0xffff : x * 16;
87 }
88
89 /*
90 * Inferred framebuffer and blender state.
91 *
92 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
93 * if there is not enough PS outputs.
94 */
95 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_state_blend *blend = sctx->queued.named.blend;
99 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
100 * but you never know. */
101 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
102 unsigned i;
103
104 if (blend)
105 cb_target_mask &= blend->cb_target_mask;
106
107 /* Avoid a hang that happens when dual source blending is enabled
108 * but there is not enough color outputs. This is undefined behavior,
109 * so disable color writes completely.
110 *
111 * Reproducible with Unigine Heaven 4.0 and drirc missing.
112 */
113 if (blend && blend->dual_src_blend &&
114 sctx->ps_shader.cso &&
115 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
116 cb_target_mask = 0;
117
118 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
119
120 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
121 * I think we don't have to do anything between IBs.
122 */
123 if (sctx->b.chip_class >= GFX9 &&
124 sctx->last_cb_target_mask != cb_target_mask) {
125 sctx->last_cb_target_mask = cb_target_mask;
126
127 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
128 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
129 }
130
131 /* RB+ register settings. */
132 if (sctx->screen->b.rbplus_allowed) {
133 unsigned spi_shader_col_format =
134 sctx->ps_shader.cso ?
135 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
136 unsigned sx_ps_downconvert = 0;
137 unsigned sx_blend_opt_epsilon = 0;
138 unsigned sx_blend_opt_control = 0;
139
140 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
141 struct r600_surface *surf =
142 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
143 unsigned format, swap, spi_format, colormask;
144 bool has_alpha, has_rgb;
145
146 if (!surf)
147 continue;
148
149 format = G_028C70_FORMAT(surf->cb_color_info);
150 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
151 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
152 colormask = (cb_target_mask >> (i * 4)) & 0xf;
153
154 /* Set if RGB and A are present. */
155 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
156
157 if (format == V_028C70_COLOR_8 ||
158 format == V_028C70_COLOR_16 ||
159 format == V_028C70_COLOR_32)
160 has_rgb = !has_alpha;
161 else
162 has_rgb = true;
163
164 /* Check the colormask and export format. */
165 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
166 has_rgb = false;
167 if (!(colormask & PIPE_MASK_A))
168 has_alpha = false;
169
170 if (spi_format == V_028714_SPI_SHADER_ZERO) {
171 has_rgb = false;
172 has_alpha = false;
173 }
174
175 /* Disable value checking for disabled channels. */
176 if (!has_rgb)
177 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
178 if (!has_alpha)
179 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
180
181 /* Enable down-conversion for 32bpp and smaller formats. */
182 switch (format) {
183 case V_028C70_COLOR_8:
184 case V_028C70_COLOR_8_8:
185 case V_028C70_COLOR_8_8_8_8:
186 /* For 1 and 2-channel formats, use the superset thereof. */
187 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
188 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
189 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
190 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
191 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
192 }
193 break;
194
195 case V_028C70_COLOR_5_6_5:
196 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
197 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
198 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
199 }
200 break;
201
202 case V_028C70_COLOR_1_5_5_5:
203 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
204 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
205 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
206 }
207 break;
208
209 case V_028C70_COLOR_4_4_4_4:
210 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
212 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
213 }
214 break;
215
216 case V_028C70_COLOR_32:
217 if (swap == V_0280A0_SWAP_STD &&
218 spi_format == V_028714_SPI_SHADER_32_R)
219 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
220 else if (swap == V_0280A0_SWAP_ALT_REV &&
221 spi_format == V_028714_SPI_SHADER_32_AR)
222 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
223 break;
224
225 case V_028C70_COLOR_16:
226 case V_028C70_COLOR_16_16:
227 /* For 1-channel formats, use the superset thereof. */
228 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
229 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
230 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
231 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
232 if (swap == V_0280A0_SWAP_STD ||
233 swap == V_0280A0_SWAP_STD_REV)
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
235 else
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
237 }
238 break;
239
240 case V_028C70_COLOR_10_11_11:
241 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
242 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
243 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
244 }
245 break;
246
247 case V_028C70_COLOR_2_10_10_10:
248 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
249 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
250 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
251 }
252 break;
253 }
254 }
255
256 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
257 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
258 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
259 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 } else if (sctx->screen->b.has_rbplus) {
261 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
262 radeon_emit(cs, 0); /* R_028754_SX_PS_DOWNCONVERT */
263 radeon_emit(cs, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
264 radeon_emit(cs, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
265 }
266 }
267
268 /*
269 * Blender functions
270 */
271
272 static uint32_t si_translate_blend_function(int blend_func)
273 {
274 switch (blend_func) {
275 case PIPE_BLEND_ADD:
276 return V_028780_COMB_DST_PLUS_SRC;
277 case PIPE_BLEND_SUBTRACT:
278 return V_028780_COMB_SRC_MINUS_DST;
279 case PIPE_BLEND_REVERSE_SUBTRACT:
280 return V_028780_COMB_DST_MINUS_SRC;
281 case PIPE_BLEND_MIN:
282 return V_028780_COMB_MIN_DST_SRC;
283 case PIPE_BLEND_MAX:
284 return V_028780_COMB_MAX_DST_SRC;
285 default:
286 R600_ERR("Unknown blend function %d\n", blend_func);
287 assert(0);
288 break;
289 }
290 return 0;
291 }
292
293 static uint32_t si_translate_blend_factor(int blend_fact)
294 {
295 switch (blend_fact) {
296 case PIPE_BLENDFACTOR_ONE:
297 return V_028780_BLEND_ONE;
298 case PIPE_BLENDFACTOR_SRC_COLOR:
299 return V_028780_BLEND_SRC_COLOR;
300 case PIPE_BLENDFACTOR_SRC_ALPHA:
301 return V_028780_BLEND_SRC_ALPHA;
302 case PIPE_BLENDFACTOR_DST_ALPHA:
303 return V_028780_BLEND_DST_ALPHA;
304 case PIPE_BLENDFACTOR_DST_COLOR:
305 return V_028780_BLEND_DST_COLOR;
306 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
307 return V_028780_BLEND_SRC_ALPHA_SATURATE;
308 case PIPE_BLENDFACTOR_CONST_COLOR:
309 return V_028780_BLEND_CONSTANT_COLOR;
310 case PIPE_BLENDFACTOR_CONST_ALPHA:
311 return V_028780_BLEND_CONSTANT_ALPHA;
312 case PIPE_BLENDFACTOR_ZERO:
313 return V_028780_BLEND_ZERO;
314 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
315 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
316 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
317 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
318 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
319 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
320 case PIPE_BLENDFACTOR_INV_DST_COLOR:
321 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
322 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
323 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
324 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
325 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
326 case PIPE_BLENDFACTOR_SRC1_COLOR:
327 return V_028780_BLEND_SRC1_COLOR;
328 case PIPE_BLENDFACTOR_SRC1_ALPHA:
329 return V_028780_BLEND_SRC1_ALPHA;
330 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
331 return V_028780_BLEND_INV_SRC1_COLOR;
332 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
333 return V_028780_BLEND_INV_SRC1_ALPHA;
334 default:
335 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
336 assert(0);
337 break;
338 }
339 return 0;
340 }
341
342 static uint32_t si_translate_blend_opt_function(int blend_func)
343 {
344 switch (blend_func) {
345 case PIPE_BLEND_ADD:
346 return V_028760_OPT_COMB_ADD;
347 case PIPE_BLEND_SUBTRACT:
348 return V_028760_OPT_COMB_SUBTRACT;
349 case PIPE_BLEND_REVERSE_SUBTRACT:
350 return V_028760_OPT_COMB_REVSUBTRACT;
351 case PIPE_BLEND_MIN:
352 return V_028760_OPT_COMB_MIN;
353 case PIPE_BLEND_MAX:
354 return V_028760_OPT_COMB_MAX;
355 default:
356 return V_028760_OPT_COMB_BLEND_DISABLED;
357 }
358 }
359
360 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
361 {
362 switch (blend_fact) {
363 case PIPE_BLENDFACTOR_ZERO:
364 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
365 case PIPE_BLENDFACTOR_ONE:
366 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
367 case PIPE_BLENDFACTOR_SRC_COLOR:
368 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
369 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
370 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
371 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
372 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
373 case PIPE_BLENDFACTOR_SRC_ALPHA:
374 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
375 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
376 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
377 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
378 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
379 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
380 default:
381 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
382 }
383 }
384
385 /**
386 * Get rid of DST in the blend factors by commuting the operands:
387 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
388 */
389 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
390 unsigned *dst_factor, unsigned expected_dst,
391 unsigned replacement_src)
392 {
393 if (*src_factor == expected_dst &&
394 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
395 *src_factor = PIPE_BLENDFACTOR_ZERO;
396 *dst_factor = replacement_src;
397
398 /* Commuting the operands requires reversing subtractions. */
399 if (*func == PIPE_BLEND_SUBTRACT)
400 *func = PIPE_BLEND_REVERSE_SUBTRACT;
401 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
402 *func = PIPE_BLEND_SUBTRACT;
403 }
404 }
405
406 static bool si_blend_factor_uses_dst(unsigned factor)
407 {
408 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
409 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
410 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
411 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
412 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
413 }
414
415 static void *si_create_blend_state_mode(struct pipe_context *ctx,
416 const struct pipe_blend_state *state,
417 unsigned mode)
418 {
419 struct si_context *sctx = (struct si_context*)ctx;
420 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
421 struct si_pm4_state *pm4 = &blend->pm4;
422 uint32_t sx_mrt_blend_opt[8] = {0};
423 uint32_t color_control = 0;
424
425 if (!blend)
426 return NULL;
427
428 blend->alpha_to_coverage = state->alpha_to_coverage;
429 blend->alpha_to_one = state->alpha_to_one;
430 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
431
432 if (state->logicop_enable) {
433 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
434 } else {
435 color_control |= S_028808_ROP3(0xcc);
436 }
437
438 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
439 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
440 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
441 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
442 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
443 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
444
445 if (state->alpha_to_coverage)
446 blend->need_src_alpha_4bit |= 0xf;
447
448 blend->cb_target_mask = 0;
449 for (int i = 0; i < 8; i++) {
450 /* state->rt entries > 0 only written if independent blending */
451 const int j = state->independent_blend_enable ? i : 0;
452
453 unsigned eqRGB = state->rt[j].rgb_func;
454 unsigned srcRGB = state->rt[j].rgb_src_factor;
455 unsigned dstRGB = state->rt[j].rgb_dst_factor;
456 unsigned eqA = state->rt[j].alpha_func;
457 unsigned srcA = state->rt[j].alpha_src_factor;
458 unsigned dstA = state->rt[j].alpha_dst_factor;
459
460 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
461 unsigned blend_cntl = 0;
462
463 sx_mrt_blend_opt[i] =
464 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
465 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
466
467 /* Only set dual source blending for MRT0 to avoid a hang. */
468 if (i >= 1 && blend->dual_src_blend) {
469 /* Vulkan does this for dual source blending. */
470 if (i == 1)
471 blend_cntl |= S_028780_ENABLE(1);
472
473 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
474 continue;
475 }
476
477 /* Only addition and subtraction equations are supported with
478 * dual source blending.
479 */
480 if (blend->dual_src_blend &&
481 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
482 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
483 assert(!"Unsupported equation for dual source blending");
484 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
485 continue;
486 }
487
488 /* cb_render_state will disable unused ones */
489 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
490
491 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
492 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
493 continue;
494 }
495
496 /* Blending optimizations for RB+.
497 * These transformations don't change the behavior.
498 *
499 * First, get rid of DST in the blend factors:
500 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
501 */
502 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
503 PIPE_BLENDFACTOR_DST_COLOR,
504 PIPE_BLENDFACTOR_SRC_COLOR);
505 si_blend_remove_dst(&eqA, &srcA, &dstA,
506 PIPE_BLENDFACTOR_DST_COLOR,
507 PIPE_BLENDFACTOR_SRC_COLOR);
508 si_blend_remove_dst(&eqA, &srcA, &dstA,
509 PIPE_BLENDFACTOR_DST_ALPHA,
510 PIPE_BLENDFACTOR_SRC_ALPHA);
511
512 /* Look up the ideal settings from tables. */
513 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
514 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
515 srcA_opt = si_translate_blend_opt_factor(srcA, true);
516 dstA_opt = si_translate_blend_opt_factor(dstA, true);
517
518 /* Handle interdependencies. */
519 if (si_blend_factor_uses_dst(srcRGB))
520 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
521 if (si_blend_factor_uses_dst(srcA))
522 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
523
524 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
525 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
526 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
527 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
528 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
529
530 /* Set the final value. */
531 sx_mrt_blend_opt[i] =
532 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
533 S_028760_COLOR_DST_OPT(dstRGB_opt) |
534 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
535 S_028760_ALPHA_SRC_OPT(srcA_opt) |
536 S_028760_ALPHA_DST_OPT(dstA_opt) |
537 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
538
539 /* Set blend state. */
540 blend_cntl |= S_028780_ENABLE(1);
541 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
542 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
543 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
544
545 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
546 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
547 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
548 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
549 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
550 }
551 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
552
553 blend->blend_enable_4bit |= 0xfu << (i * 4);
554
555 /* This is only important for formats without alpha. */
556 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
557 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
558 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
559 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
560 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
561 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
562 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
563 }
564
565 if (blend->cb_target_mask) {
566 color_control |= S_028808_MODE(mode);
567 } else {
568 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
569 }
570
571 if (sctx->screen->b.has_rbplus) {
572 /* Disable RB+ blend optimizations for dual source blending.
573 * Vulkan does this.
574 */
575 if (blend->dual_src_blend) {
576 for (int i = 0; i < 8; i++) {
577 sx_mrt_blend_opt[i] =
578 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
579 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
580 }
581 }
582
583 for (int i = 0; i < 8; i++)
584 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
585 sx_mrt_blend_opt[i]);
586
587 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
588 if (blend->dual_src_blend || state->logicop_enable ||
589 mode == V_028808_CB_RESOLVE)
590 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
591 }
592
593 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
594 return blend;
595 }
596
597 static void *si_create_blend_state(struct pipe_context *ctx,
598 const struct pipe_blend_state *state)
599 {
600 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
601 }
602
603 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
604 {
605 struct si_context *sctx = (struct si_context *)ctx;
606 struct si_state_blend *old_blend = sctx->queued.named.blend;
607 struct si_state_blend *blend = (struct si_state_blend *)state;
608
609 if (!state)
610 return;
611
612 if (!old_blend ||
613 old_blend->cb_target_mask != blend->cb_target_mask ||
614 old_blend->dual_src_blend != blend->dual_src_blend)
615 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
616
617 si_pm4_bind_state(sctx, blend, state);
618
619 if (!old_blend ||
620 old_blend->cb_target_mask != blend->cb_target_mask ||
621 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
622 old_blend->alpha_to_one != blend->alpha_to_one ||
623 old_blend->dual_src_blend != blend->dual_src_blend ||
624 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
625 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
626 sctx->do_update_shaders = true;
627 }
628
629 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
630 {
631 struct si_context *sctx = (struct si_context *)ctx;
632 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
633 }
634
635 static void si_set_blend_color(struct pipe_context *ctx,
636 const struct pipe_blend_color *state)
637 {
638 struct si_context *sctx = (struct si_context *)ctx;
639
640 sctx->blend_color.state = *state;
641 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
642 }
643
644 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
645 {
646 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
647
648 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
649 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
650 }
651
652 /*
653 * Clipping
654 */
655
656 static void si_set_clip_state(struct pipe_context *ctx,
657 const struct pipe_clip_state *state)
658 {
659 struct si_context *sctx = (struct si_context *)ctx;
660 struct pipe_constant_buffer cb;
661
662 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
663 return;
664
665 sctx->clip_state.state = *state;
666 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
667
668 cb.buffer = NULL;
669 cb.user_buffer = state->ucp;
670 cb.buffer_offset = 0;
671 cb.buffer_size = 4*4*8;
672 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
673 pipe_resource_reference(&cb.buffer, NULL);
674 }
675
676 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
677 {
678 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
679
680 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
681 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
682 }
683
684 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
685 {
686 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
687 struct si_shader *vs = si_get_vs_state(sctx);
688 struct si_shader_selector *vs_sel = vs->selector;
689 struct tgsi_shader_info *info = &vs_sel->info;
690 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
691 unsigned window_space =
692 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
693 unsigned clipdist_mask = vs_sel->clipdist_mask;
694 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
695 unsigned culldist_mask = vs_sel->culldist_mask;
696 unsigned total_mask;
697
698 if (vs->key.opt.hw_vs.clip_disable) {
699 assert(!info->culldist_writemask);
700 clipdist_mask = 0;
701 culldist_mask = 0;
702 }
703 total_mask = clipdist_mask | culldist_mask;
704
705 /* Clip distances on points have no effect, so need to be implemented
706 * as cull distances. This applies for the clipvertex case as well.
707 *
708 * Setting this for primitives other than points should have no adverse
709 * effects.
710 */
711 clipdist_mask &= rs->clip_plane_enable;
712 culldist_mask |= clipdist_mask;
713
714 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
715 vs_sel->pa_cl_vs_out_cntl |
716 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
717 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
718 clipdist_mask | (culldist_mask << 8));
719 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
720 rs->pa_cl_clip_cntl |
721 ucp_mask |
722 S_028810_CLIP_DISABLE(window_space));
723
724 if (sctx->b.chip_class <= VI) {
725 /* reuse needs to be set off if we write oViewport */
726 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
727 S_028AB4_REUSE_OFF(info->writes_viewport_index));
728 }
729 }
730
731 /*
732 * inferred state between framebuffer and rasterizer
733 */
734 static void si_update_poly_offset_state(struct si_context *sctx)
735 {
736 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
737
738 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
739 si_pm4_bind_state(sctx, poly_offset, NULL);
740 return;
741 }
742
743 /* Use the user format, not db_render_format, so that the polygon
744 * offset behaves as expected by applications.
745 */
746 switch (sctx->framebuffer.state.zsbuf->texture->format) {
747 case PIPE_FORMAT_Z16_UNORM:
748 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
749 break;
750 default: /* 24-bit */
751 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
752 break;
753 case PIPE_FORMAT_Z32_FLOAT:
754 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
755 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
756 break;
757 }
758 }
759
760 /*
761 * Rasterizer
762 */
763
764 static uint32_t si_translate_fill(uint32_t func)
765 {
766 switch(func) {
767 case PIPE_POLYGON_MODE_FILL:
768 return V_028814_X_DRAW_TRIANGLES;
769 case PIPE_POLYGON_MODE_LINE:
770 return V_028814_X_DRAW_LINES;
771 case PIPE_POLYGON_MODE_POINT:
772 return V_028814_X_DRAW_POINTS;
773 default:
774 assert(0);
775 return V_028814_X_DRAW_POINTS;
776 }
777 }
778
779 static void *si_create_rs_state(struct pipe_context *ctx,
780 const struct pipe_rasterizer_state *state)
781 {
782 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
783 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
784 struct si_pm4_state *pm4 = &rs->pm4;
785 unsigned tmp, i;
786 float psize_min, psize_max;
787
788 if (!rs) {
789 return NULL;
790 }
791
792 rs->scissor_enable = state->scissor;
793 rs->clip_halfz = state->clip_halfz;
794 rs->two_side = state->light_twoside;
795 rs->multisample_enable = state->multisample;
796 rs->force_persample_interp = state->force_persample_interp;
797 rs->clip_plane_enable = state->clip_plane_enable;
798 rs->line_stipple_enable = state->line_stipple_enable;
799 rs->poly_stipple_enable = state->poly_stipple_enable;
800 rs->line_smooth = state->line_smooth;
801 rs->poly_smooth = state->poly_smooth;
802 rs->uses_poly_offset = state->offset_point || state->offset_line ||
803 state->offset_tri;
804 rs->clamp_fragment_color = state->clamp_fragment_color;
805 rs->clamp_vertex_color = state->clamp_vertex_color;
806 rs->flatshade = state->flatshade;
807 rs->sprite_coord_enable = state->sprite_coord_enable;
808 rs->rasterizer_discard = state->rasterizer_discard;
809 rs->pa_sc_line_stipple = state->line_stipple_enable ?
810 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
811 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
812 rs->pa_cl_clip_cntl =
813 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
814 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
815 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
816 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
817 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
818
819 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
820 S_0286D4_FLAT_SHADE_ENA(1) |
821 S_0286D4_PNT_SPRITE_ENA(1) |
822 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
823 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
824 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
825 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
826 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
827
828 /* point size 12.4 fixed point */
829 tmp = (unsigned)(state->point_size * 8.0);
830 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
831
832 if (state->point_size_per_vertex) {
833 psize_min = util_get_min_point_size(state);
834 psize_max = 8192;
835 } else {
836 /* Force the point size to be as if the vertex output was disabled. */
837 psize_min = state->point_size;
838 psize_max = state->point_size;
839 }
840 /* Divide by two, because 0.5 = 1 pixel. */
841 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
842 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
843 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
844
845 tmp = (unsigned)state->line_width * 8;
846 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
847 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
848 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
849 S_028A48_MSAA_ENABLE(state->multisample ||
850 state->poly_smooth ||
851 state->line_smooth) |
852 S_028A48_VPORT_SCISSOR_ENABLE(1) |
853 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->b.chip_class >= GFX9));
854
855 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
856 S_028BE4_PIX_CENTER(state->half_pixel_center) |
857 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
858
859 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
860 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
861 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
862 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
863 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
864 S_028814_FACE(!state->front_ccw) |
865 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
866 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
867 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
868 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
869 state->fill_back != PIPE_POLYGON_MODE_FILL) |
870 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
871 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
872
873 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
874 for (i = 0; i < 3; i++) {
875 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
876 float offset_units = state->offset_units;
877 float offset_scale = state->offset_scale * 16.0f;
878 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
879
880 if (!state->offset_units_unscaled) {
881 switch (i) {
882 case 0: /* 16-bit zbuffer */
883 offset_units *= 4.0f;
884 pa_su_poly_offset_db_fmt_cntl =
885 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
886 break;
887 case 1: /* 24-bit zbuffer */
888 offset_units *= 2.0f;
889 pa_su_poly_offset_db_fmt_cntl =
890 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
891 break;
892 case 2: /* 32-bit zbuffer */
893 offset_units *= 1.0f;
894 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
895 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
896 break;
897 }
898 }
899
900 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
901 fui(offset_scale));
902 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
903 fui(offset_units));
904 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
905 fui(offset_scale));
906 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
907 fui(offset_units));
908 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
909 pa_su_poly_offset_db_fmt_cntl);
910 }
911
912 return rs;
913 }
914
915 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
916 {
917 struct si_context *sctx = (struct si_context *)ctx;
918 struct si_state_rasterizer *old_rs =
919 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
920 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
921
922 if (!state)
923 return;
924
925 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
926 si_mark_atom_dirty(sctx, &sctx->db_render_state);
927
928 /* Update the small primitive filter workaround if necessary. */
929 if (sctx->screen->has_msaa_sample_loc_bug &&
930 sctx->framebuffer.nr_samples > 1)
931 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
932 }
933
934 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
935 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
936
937 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
938
939 si_pm4_bind_state(sctx, rasterizer, rs);
940 si_update_poly_offset_state(sctx);
941
942 if (!old_rs ||
943 old_rs->clip_plane_enable != rs->clip_plane_enable ||
944 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
945 si_mark_atom_dirty(sctx, &sctx->clip_regs);
946
947 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
948 rs->line_stipple_enable;
949
950 if (!old_rs ||
951 old_rs->clip_plane_enable != rs->clip_plane_enable ||
952 old_rs->rasterizer_discard != rs->rasterizer_discard ||
953 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
954 old_rs->flatshade != rs->flatshade ||
955 old_rs->two_side != rs->two_side ||
956 old_rs->multisample_enable != rs->multisample_enable ||
957 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
958 old_rs->poly_smooth != rs->poly_smooth ||
959 old_rs->line_smooth != rs->line_smooth ||
960 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
961 old_rs->force_persample_interp != rs->force_persample_interp)
962 sctx->do_update_shaders = true;
963 }
964
965 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
966 {
967 struct si_context *sctx = (struct si_context *)ctx;
968
969 if (sctx->queued.named.rasterizer == state)
970 si_pm4_bind_state(sctx, poly_offset, NULL);
971 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
972 }
973
974 /*
975 * infeered state between dsa and stencil ref
976 */
977 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
978 {
979 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
980 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
981 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
982
983 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
984 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
985 S_028430_STENCILMASK(dsa->valuemask[0]) |
986 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
987 S_028430_STENCILOPVAL(1));
988 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
989 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
990 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
991 S_028434_STENCILOPVAL_BF(1));
992 }
993
994 static void si_set_stencil_ref(struct pipe_context *ctx,
995 const struct pipe_stencil_ref *state)
996 {
997 struct si_context *sctx = (struct si_context *)ctx;
998
999 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1000 return;
1001
1002 sctx->stencil_ref.state = *state;
1003 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1004 }
1005
1006
1007 /*
1008 * DSA
1009 */
1010
1011 static uint32_t si_translate_stencil_op(int s_op)
1012 {
1013 switch (s_op) {
1014 case PIPE_STENCIL_OP_KEEP:
1015 return V_02842C_STENCIL_KEEP;
1016 case PIPE_STENCIL_OP_ZERO:
1017 return V_02842C_STENCIL_ZERO;
1018 case PIPE_STENCIL_OP_REPLACE:
1019 return V_02842C_STENCIL_REPLACE_TEST;
1020 case PIPE_STENCIL_OP_INCR:
1021 return V_02842C_STENCIL_ADD_CLAMP;
1022 case PIPE_STENCIL_OP_DECR:
1023 return V_02842C_STENCIL_SUB_CLAMP;
1024 case PIPE_STENCIL_OP_INCR_WRAP:
1025 return V_02842C_STENCIL_ADD_WRAP;
1026 case PIPE_STENCIL_OP_DECR_WRAP:
1027 return V_02842C_STENCIL_SUB_WRAP;
1028 case PIPE_STENCIL_OP_INVERT:
1029 return V_02842C_STENCIL_INVERT;
1030 default:
1031 R600_ERR("Unknown stencil op %d", s_op);
1032 assert(0);
1033 break;
1034 }
1035 return 0;
1036 }
1037
1038 static void *si_create_dsa_state(struct pipe_context *ctx,
1039 const struct pipe_depth_stencil_alpha_state *state)
1040 {
1041 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1042 struct si_pm4_state *pm4 = &dsa->pm4;
1043 unsigned db_depth_control;
1044 uint32_t db_stencil_control = 0;
1045
1046 if (!dsa) {
1047 return NULL;
1048 }
1049
1050 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1051 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1052 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1053 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1054
1055 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1056 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1057 S_028800_ZFUNC(state->depth.func) |
1058 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1059
1060 /* stencil */
1061 if (state->stencil[0].enabled) {
1062 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1063 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1064 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1065 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1066 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1067
1068 if (state->stencil[1].enabled) {
1069 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1070 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1071 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1072 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1073 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1074 }
1075 }
1076
1077 /* alpha */
1078 if (state->alpha.enabled) {
1079 dsa->alpha_func = state->alpha.func;
1080
1081 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1082 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1083 } else {
1084 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1085 }
1086
1087 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1088 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1089 if (state->depth.bounds_test) {
1090 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1091 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1092 }
1093
1094 return dsa;
1095 }
1096
1097 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1098 {
1099 struct si_context *sctx = (struct si_context *)ctx;
1100 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1101 struct si_state_dsa *dsa = state;
1102
1103 if (!state)
1104 return;
1105
1106 si_pm4_bind_state(sctx, dsa, dsa);
1107
1108 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1109 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1110 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1111 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1112 }
1113
1114 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1115 sctx->do_update_shaders = true;
1116 }
1117
1118 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1119 {
1120 struct si_context *sctx = (struct si_context *)ctx;
1121 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1122 }
1123
1124 static void *si_create_db_flush_dsa(struct si_context *sctx)
1125 {
1126 struct pipe_depth_stencil_alpha_state dsa = {};
1127
1128 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1129 }
1130
1131 /* DB RENDER STATE */
1132
1133 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1134 {
1135 struct si_context *sctx = (struct si_context*)ctx;
1136
1137 /* Pipeline stat & streamout queries. */
1138 if (enable) {
1139 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1140 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1141 } else {
1142 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1143 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1144 }
1145
1146 /* Occlusion queries. */
1147 if (sctx->occlusion_queries_disabled != !enable) {
1148 sctx->occlusion_queries_disabled = !enable;
1149 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1150 }
1151 }
1152
1153 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1154 {
1155 struct si_context *sctx = (struct si_context*)ctx;
1156
1157 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1158 }
1159
1160 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1161 {
1162 struct si_context *sctx = (struct si_context*)ctx;
1163
1164 st->saved_compute = sctx->cs_shader_state.program;
1165
1166 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1167 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1168 }
1169
1170 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1171 {
1172 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1173 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1174 unsigned db_shader_control;
1175
1176 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1177
1178 /* DB_RENDER_CONTROL */
1179 if (sctx->dbcb_depth_copy_enabled ||
1180 sctx->dbcb_stencil_copy_enabled) {
1181 radeon_emit(cs,
1182 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1183 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1184 S_028000_COPY_CENTROID(1) |
1185 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1186 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1187 radeon_emit(cs,
1188 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1189 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1190 } else {
1191 radeon_emit(cs,
1192 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1193 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1194 }
1195
1196 /* DB_COUNT_CONTROL (occlusion queries) */
1197 if (sctx->b.num_occlusion_queries > 0 &&
1198 !sctx->occlusion_queries_disabled) {
1199 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1200
1201 if (sctx->b.chip_class >= CIK) {
1202 radeon_emit(cs,
1203 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1204 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1205 S_028004_ZPASS_ENABLE(1) |
1206 S_028004_SLICE_EVEN_ENABLE(1) |
1207 S_028004_SLICE_ODD_ENABLE(1));
1208 } else {
1209 radeon_emit(cs,
1210 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1211 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1212 }
1213 } else {
1214 /* Disable occlusion queries. */
1215 if (sctx->b.chip_class >= CIK) {
1216 radeon_emit(cs, 0);
1217 } else {
1218 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1219 }
1220 }
1221
1222 /* DB_RENDER_OVERRIDE2 */
1223 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1224 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1225 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1226 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1227
1228 db_shader_control = sctx->ps_db_shader_control;
1229
1230 /* Bug workaround for smoothing (overrasterization) on SI. */
1231 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1232 db_shader_control &= C_02880C_Z_ORDER;
1233 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1234 }
1235
1236 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1237 if (!rs || !rs->multisample_enable)
1238 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1239
1240 if (sctx->screen->b.has_rbplus &&
1241 !sctx->screen->b.rbplus_allowed)
1242 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1243
1244 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1245 db_shader_control);
1246 }
1247
1248 /*
1249 * format translation
1250 */
1251 static uint32_t si_translate_colorformat(enum pipe_format format)
1252 {
1253 const struct util_format_description *desc = util_format_description(format);
1254
1255 #define HAS_SIZE(x,y,z,w) \
1256 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1257 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1258
1259 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1260 return V_028C70_COLOR_10_11_11;
1261
1262 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1263 return V_028C70_COLOR_INVALID;
1264
1265 /* hw cannot support mixed formats (except depth/stencil, since
1266 * stencil is not written to). */
1267 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1268 return V_028C70_COLOR_INVALID;
1269
1270 switch (desc->nr_channels) {
1271 case 1:
1272 switch (desc->channel[0].size) {
1273 case 8:
1274 return V_028C70_COLOR_8;
1275 case 16:
1276 return V_028C70_COLOR_16;
1277 case 32:
1278 return V_028C70_COLOR_32;
1279 }
1280 break;
1281 case 2:
1282 if (desc->channel[0].size == desc->channel[1].size) {
1283 switch (desc->channel[0].size) {
1284 case 8:
1285 return V_028C70_COLOR_8_8;
1286 case 16:
1287 return V_028C70_COLOR_16_16;
1288 case 32:
1289 return V_028C70_COLOR_32_32;
1290 }
1291 } else if (HAS_SIZE(8,24,0,0)) {
1292 return V_028C70_COLOR_24_8;
1293 } else if (HAS_SIZE(24,8,0,0)) {
1294 return V_028C70_COLOR_8_24;
1295 }
1296 break;
1297 case 3:
1298 if (HAS_SIZE(5,6,5,0)) {
1299 return V_028C70_COLOR_5_6_5;
1300 } else if (HAS_SIZE(32,8,24,0)) {
1301 return V_028C70_COLOR_X24_8_32_FLOAT;
1302 }
1303 break;
1304 case 4:
1305 if (desc->channel[0].size == desc->channel[1].size &&
1306 desc->channel[0].size == desc->channel[2].size &&
1307 desc->channel[0].size == desc->channel[3].size) {
1308 switch (desc->channel[0].size) {
1309 case 4:
1310 return V_028C70_COLOR_4_4_4_4;
1311 case 8:
1312 return V_028C70_COLOR_8_8_8_8;
1313 case 16:
1314 return V_028C70_COLOR_16_16_16_16;
1315 case 32:
1316 return V_028C70_COLOR_32_32_32_32;
1317 }
1318 } else if (HAS_SIZE(5,5,5,1)) {
1319 return V_028C70_COLOR_1_5_5_5;
1320 } else if (HAS_SIZE(10,10,10,2)) {
1321 return V_028C70_COLOR_2_10_10_10;
1322 }
1323 break;
1324 }
1325 return V_028C70_COLOR_INVALID;
1326 }
1327
1328 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1329 {
1330 if (SI_BIG_ENDIAN) {
1331 switch(colorformat) {
1332 /* 8-bit buffers. */
1333 case V_028C70_COLOR_8:
1334 return V_028C70_ENDIAN_NONE;
1335
1336 /* 16-bit buffers. */
1337 case V_028C70_COLOR_5_6_5:
1338 case V_028C70_COLOR_1_5_5_5:
1339 case V_028C70_COLOR_4_4_4_4:
1340 case V_028C70_COLOR_16:
1341 case V_028C70_COLOR_8_8:
1342 return V_028C70_ENDIAN_8IN16;
1343
1344 /* 32-bit buffers. */
1345 case V_028C70_COLOR_8_8_8_8:
1346 case V_028C70_COLOR_2_10_10_10:
1347 case V_028C70_COLOR_8_24:
1348 case V_028C70_COLOR_24_8:
1349 case V_028C70_COLOR_16_16:
1350 return V_028C70_ENDIAN_8IN32;
1351
1352 /* 64-bit buffers. */
1353 case V_028C70_COLOR_16_16_16_16:
1354 return V_028C70_ENDIAN_8IN16;
1355
1356 case V_028C70_COLOR_32_32:
1357 return V_028C70_ENDIAN_8IN32;
1358
1359 /* 128-bit buffers. */
1360 case V_028C70_COLOR_32_32_32_32:
1361 return V_028C70_ENDIAN_8IN32;
1362 default:
1363 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1364 }
1365 } else {
1366 return V_028C70_ENDIAN_NONE;
1367 }
1368 }
1369
1370 static uint32_t si_translate_dbformat(enum pipe_format format)
1371 {
1372 switch (format) {
1373 case PIPE_FORMAT_Z16_UNORM:
1374 return V_028040_Z_16;
1375 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1376 case PIPE_FORMAT_X8Z24_UNORM:
1377 case PIPE_FORMAT_Z24X8_UNORM:
1378 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1379 return V_028040_Z_24; /* deprecated on SI */
1380 case PIPE_FORMAT_Z32_FLOAT:
1381 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1382 return V_028040_Z_32_FLOAT;
1383 default:
1384 return V_028040_Z_INVALID;
1385 }
1386 }
1387
1388 /*
1389 * Texture translation
1390 */
1391
1392 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1393 enum pipe_format format,
1394 const struct util_format_description *desc,
1395 int first_non_void)
1396 {
1397 struct si_screen *sscreen = (struct si_screen*)screen;
1398 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1399 sscreen->b.info.drm_minor >= 31) ||
1400 sscreen->b.info.drm_major == 3;
1401 bool uniform = true;
1402 int i;
1403
1404 /* Colorspace (return non-RGB formats directly). */
1405 switch (desc->colorspace) {
1406 /* Depth stencil formats */
1407 case UTIL_FORMAT_COLORSPACE_ZS:
1408 switch (format) {
1409 case PIPE_FORMAT_Z16_UNORM:
1410 return V_008F14_IMG_DATA_FORMAT_16;
1411 case PIPE_FORMAT_X24S8_UINT:
1412 case PIPE_FORMAT_S8X24_UINT:
1413 /*
1414 * Implemented as an 8_8_8_8 data format to fix texture
1415 * gathers in stencil sampling. This affects at least
1416 * GL45-CTS.texture_cube_map_array.sampling on VI.
1417 */
1418 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1419 case PIPE_FORMAT_Z24X8_UNORM:
1420 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1421 return V_008F14_IMG_DATA_FORMAT_8_24;
1422 case PIPE_FORMAT_X8Z24_UNORM:
1423 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1424 return V_008F14_IMG_DATA_FORMAT_24_8;
1425 case PIPE_FORMAT_S8_UINT:
1426 return V_008F14_IMG_DATA_FORMAT_8;
1427 case PIPE_FORMAT_Z32_FLOAT:
1428 return V_008F14_IMG_DATA_FORMAT_32;
1429 case PIPE_FORMAT_X32_S8X24_UINT:
1430 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1431 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1432 default:
1433 goto out_unknown;
1434 }
1435
1436 case UTIL_FORMAT_COLORSPACE_YUV:
1437 goto out_unknown; /* TODO */
1438
1439 case UTIL_FORMAT_COLORSPACE_SRGB:
1440 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1441 goto out_unknown;
1442 break;
1443
1444 default:
1445 break;
1446 }
1447
1448 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1449 if (!enable_compressed_formats)
1450 goto out_unknown;
1451
1452 switch (format) {
1453 case PIPE_FORMAT_RGTC1_SNORM:
1454 case PIPE_FORMAT_LATC1_SNORM:
1455 case PIPE_FORMAT_RGTC1_UNORM:
1456 case PIPE_FORMAT_LATC1_UNORM:
1457 return V_008F14_IMG_DATA_FORMAT_BC4;
1458 case PIPE_FORMAT_RGTC2_SNORM:
1459 case PIPE_FORMAT_LATC2_SNORM:
1460 case PIPE_FORMAT_RGTC2_UNORM:
1461 case PIPE_FORMAT_LATC2_UNORM:
1462 return V_008F14_IMG_DATA_FORMAT_BC5;
1463 default:
1464 goto out_unknown;
1465 }
1466 }
1467
1468 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1469 (sscreen->b.family == CHIP_STONEY ||
1470 sscreen->b.chip_class >= GFX9)) {
1471 switch (format) {
1472 case PIPE_FORMAT_ETC1_RGB8:
1473 case PIPE_FORMAT_ETC2_RGB8:
1474 case PIPE_FORMAT_ETC2_SRGB8:
1475 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1476 case PIPE_FORMAT_ETC2_RGB8A1:
1477 case PIPE_FORMAT_ETC2_SRGB8A1:
1478 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1479 case PIPE_FORMAT_ETC2_RGBA8:
1480 case PIPE_FORMAT_ETC2_SRGBA8:
1481 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1482 case PIPE_FORMAT_ETC2_R11_UNORM:
1483 case PIPE_FORMAT_ETC2_R11_SNORM:
1484 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1485 case PIPE_FORMAT_ETC2_RG11_UNORM:
1486 case PIPE_FORMAT_ETC2_RG11_SNORM:
1487 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1488 default:
1489 goto out_unknown;
1490 }
1491 }
1492
1493 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1494 if (!enable_compressed_formats)
1495 goto out_unknown;
1496
1497 switch (format) {
1498 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1499 case PIPE_FORMAT_BPTC_SRGBA:
1500 return V_008F14_IMG_DATA_FORMAT_BC7;
1501 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1502 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1503 return V_008F14_IMG_DATA_FORMAT_BC6;
1504 default:
1505 goto out_unknown;
1506 }
1507 }
1508
1509 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1510 switch (format) {
1511 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1512 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1513 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1514 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1515 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1516 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1517 default:
1518 goto out_unknown;
1519 }
1520 }
1521
1522 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1523 if (!enable_compressed_formats)
1524 goto out_unknown;
1525
1526 if (!util_format_s3tc_enabled) {
1527 goto out_unknown;
1528 }
1529
1530 switch (format) {
1531 case PIPE_FORMAT_DXT1_RGB:
1532 case PIPE_FORMAT_DXT1_RGBA:
1533 case PIPE_FORMAT_DXT1_SRGB:
1534 case PIPE_FORMAT_DXT1_SRGBA:
1535 return V_008F14_IMG_DATA_FORMAT_BC1;
1536 case PIPE_FORMAT_DXT3_RGBA:
1537 case PIPE_FORMAT_DXT3_SRGBA:
1538 return V_008F14_IMG_DATA_FORMAT_BC2;
1539 case PIPE_FORMAT_DXT5_RGBA:
1540 case PIPE_FORMAT_DXT5_SRGBA:
1541 return V_008F14_IMG_DATA_FORMAT_BC3;
1542 default:
1543 goto out_unknown;
1544 }
1545 }
1546
1547 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1548 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1549 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1550 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1551 }
1552
1553 /* R8G8Bx_SNORM - TODO CxV8U8 */
1554
1555 /* hw cannot support mixed formats (except depth/stencil, since only
1556 * depth is read).*/
1557 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1558 goto out_unknown;
1559
1560 /* See whether the components are of the same size. */
1561 for (i = 1; i < desc->nr_channels; i++) {
1562 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1563 }
1564
1565 /* Non-uniform formats. */
1566 if (!uniform) {
1567 switch(desc->nr_channels) {
1568 case 3:
1569 if (desc->channel[0].size == 5 &&
1570 desc->channel[1].size == 6 &&
1571 desc->channel[2].size == 5) {
1572 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1573 }
1574 goto out_unknown;
1575 case 4:
1576 if (desc->channel[0].size == 5 &&
1577 desc->channel[1].size == 5 &&
1578 desc->channel[2].size == 5 &&
1579 desc->channel[3].size == 1) {
1580 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1581 }
1582 if (desc->channel[0].size == 10 &&
1583 desc->channel[1].size == 10 &&
1584 desc->channel[2].size == 10 &&
1585 desc->channel[3].size == 2) {
1586 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1587 }
1588 goto out_unknown;
1589 }
1590 goto out_unknown;
1591 }
1592
1593 if (first_non_void < 0 || first_non_void > 3)
1594 goto out_unknown;
1595
1596 /* uniform formats */
1597 switch (desc->channel[first_non_void].size) {
1598 case 4:
1599 switch (desc->nr_channels) {
1600 #if 0 /* Not supported for render targets */
1601 case 2:
1602 return V_008F14_IMG_DATA_FORMAT_4_4;
1603 #endif
1604 case 4:
1605 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1606 }
1607 break;
1608 case 8:
1609 switch (desc->nr_channels) {
1610 case 1:
1611 return V_008F14_IMG_DATA_FORMAT_8;
1612 case 2:
1613 return V_008F14_IMG_DATA_FORMAT_8_8;
1614 case 4:
1615 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1616 }
1617 break;
1618 case 16:
1619 switch (desc->nr_channels) {
1620 case 1:
1621 return V_008F14_IMG_DATA_FORMAT_16;
1622 case 2:
1623 return V_008F14_IMG_DATA_FORMAT_16_16;
1624 case 4:
1625 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1626 }
1627 break;
1628 case 32:
1629 switch (desc->nr_channels) {
1630 case 1:
1631 return V_008F14_IMG_DATA_FORMAT_32;
1632 case 2:
1633 return V_008F14_IMG_DATA_FORMAT_32_32;
1634 #if 0 /* Not supported for render targets */
1635 case 3:
1636 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1637 #endif
1638 case 4:
1639 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1640 }
1641 }
1642
1643 out_unknown:
1644 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1645 return ~0;
1646 }
1647
1648 static unsigned si_tex_wrap(unsigned wrap)
1649 {
1650 switch (wrap) {
1651 default:
1652 case PIPE_TEX_WRAP_REPEAT:
1653 return V_008F30_SQ_TEX_WRAP;
1654 case PIPE_TEX_WRAP_CLAMP:
1655 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1656 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1657 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1658 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1659 return V_008F30_SQ_TEX_CLAMP_BORDER;
1660 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1661 return V_008F30_SQ_TEX_MIRROR;
1662 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1663 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1664 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1665 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1666 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1667 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1668 }
1669 }
1670
1671 static unsigned si_tex_mipfilter(unsigned filter)
1672 {
1673 switch (filter) {
1674 case PIPE_TEX_MIPFILTER_NEAREST:
1675 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1676 case PIPE_TEX_MIPFILTER_LINEAR:
1677 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1678 default:
1679 case PIPE_TEX_MIPFILTER_NONE:
1680 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1681 }
1682 }
1683
1684 static unsigned si_tex_compare(unsigned compare)
1685 {
1686 switch (compare) {
1687 default:
1688 case PIPE_FUNC_NEVER:
1689 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1690 case PIPE_FUNC_LESS:
1691 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1692 case PIPE_FUNC_EQUAL:
1693 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1694 case PIPE_FUNC_LEQUAL:
1695 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1696 case PIPE_FUNC_GREATER:
1697 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1698 case PIPE_FUNC_NOTEQUAL:
1699 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1700 case PIPE_FUNC_GEQUAL:
1701 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1702 case PIPE_FUNC_ALWAYS:
1703 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1704 }
1705 }
1706
1707 static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
1708 unsigned view_target, unsigned nr_samples)
1709 {
1710 unsigned res_target = rtex->resource.b.b.target;
1711
1712 if (view_target == PIPE_TEXTURE_CUBE ||
1713 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1714 res_target = view_target;
1715 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1716 else if (res_target == PIPE_TEXTURE_CUBE ||
1717 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1718 res_target = PIPE_TEXTURE_2D_ARRAY;
1719
1720 /* GFX9 allocates 1D textures as 2D. */
1721 if ((res_target == PIPE_TEXTURE_1D ||
1722 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1723 sscreen->b.chip_class >= GFX9 &&
1724 rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1725 if (res_target == PIPE_TEXTURE_1D)
1726 res_target = PIPE_TEXTURE_2D;
1727 else
1728 res_target = PIPE_TEXTURE_2D_ARRAY;
1729 }
1730
1731 switch (res_target) {
1732 default:
1733 case PIPE_TEXTURE_1D:
1734 return V_008F1C_SQ_RSRC_IMG_1D;
1735 case PIPE_TEXTURE_1D_ARRAY:
1736 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1737 case PIPE_TEXTURE_2D:
1738 case PIPE_TEXTURE_RECT:
1739 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1740 V_008F1C_SQ_RSRC_IMG_2D;
1741 case PIPE_TEXTURE_2D_ARRAY:
1742 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1743 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1744 case PIPE_TEXTURE_3D:
1745 return V_008F1C_SQ_RSRC_IMG_3D;
1746 case PIPE_TEXTURE_CUBE:
1747 case PIPE_TEXTURE_CUBE_ARRAY:
1748 return V_008F1C_SQ_RSRC_IMG_CUBE;
1749 }
1750 }
1751
1752 /*
1753 * Format support testing
1754 */
1755
1756 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1757 {
1758 return si_translate_texformat(screen, format, util_format_description(format),
1759 util_format_get_first_non_void_channel(format)) != ~0U;
1760 }
1761
1762 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1763 const struct util_format_description *desc,
1764 int first_non_void)
1765 {
1766 int i;
1767
1768 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1769 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1770
1771 assert(first_non_void >= 0);
1772
1773 if (desc->nr_channels == 4 &&
1774 desc->channel[0].size == 10 &&
1775 desc->channel[1].size == 10 &&
1776 desc->channel[2].size == 10 &&
1777 desc->channel[3].size == 2)
1778 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1779
1780 /* See whether the components are of the same size. */
1781 for (i = 0; i < desc->nr_channels; i++) {
1782 if (desc->channel[first_non_void].size != desc->channel[i].size)
1783 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1784 }
1785
1786 switch (desc->channel[first_non_void].size) {
1787 case 8:
1788 switch (desc->nr_channels) {
1789 case 1:
1790 case 3: /* 3 loads */
1791 return V_008F0C_BUF_DATA_FORMAT_8;
1792 case 2:
1793 return V_008F0C_BUF_DATA_FORMAT_8_8;
1794 case 4:
1795 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1796 }
1797 break;
1798 case 16:
1799 switch (desc->nr_channels) {
1800 case 1:
1801 case 3: /* 3 loads */
1802 return V_008F0C_BUF_DATA_FORMAT_16;
1803 case 2:
1804 return V_008F0C_BUF_DATA_FORMAT_16_16;
1805 case 4:
1806 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1807 }
1808 break;
1809 case 32:
1810 switch (desc->nr_channels) {
1811 case 1:
1812 return V_008F0C_BUF_DATA_FORMAT_32;
1813 case 2:
1814 return V_008F0C_BUF_DATA_FORMAT_32_32;
1815 case 3:
1816 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1817 case 4:
1818 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1819 }
1820 break;
1821 case 64:
1822 /* Legacy double formats. */
1823 switch (desc->nr_channels) {
1824 case 1: /* 1 load */
1825 return V_008F0C_BUF_DATA_FORMAT_32_32;
1826 case 2: /* 1 load */
1827 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1828 case 3: /* 3 loads */
1829 return V_008F0C_BUF_DATA_FORMAT_32_32;
1830 case 4: /* 2 loads */
1831 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1832 }
1833 break;
1834 }
1835
1836 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1837 }
1838
1839 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1840 const struct util_format_description *desc,
1841 int first_non_void)
1842 {
1843 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1844 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1845
1846 assert(first_non_void >= 0);
1847
1848 switch (desc->channel[first_non_void].type) {
1849 case UTIL_FORMAT_TYPE_SIGNED:
1850 case UTIL_FORMAT_TYPE_FIXED:
1851 if (desc->channel[first_non_void].size >= 32 ||
1852 desc->channel[first_non_void].pure_integer)
1853 return V_008F0C_BUF_NUM_FORMAT_SINT;
1854 else if (desc->channel[first_non_void].normalized)
1855 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1856 else
1857 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1858 break;
1859 case UTIL_FORMAT_TYPE_UNSIGNED:
1860 if (desc->channel[first_non_void].size >= 32 ||
1861 desc->channel[first_non_void].pure_integer)
1862 return V_008F0C_BUF_NUM_FORMAT_UINT;
1863 else if (desc->channel[first_non_void].normalized)
1864 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1865 else
1866 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1867 break;
1868 case UTIL_FORMAT_TYPE_FLOAT:
1869 default:
1870 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1871 }
1872 }
1873
1874 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1875 enum pipe_format format,
1876 unsigned usage)
1877 {
1878 const struct util_format_description *desc;
1879 int first_non_void;
1880 unsigned data_format;
1881
1882 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1883 PIPE_BIND_SAMPLER_VIEW |
1884 PIPE_BIND_VERTEX_BUFFER)) == 0);
1885
1886 desc = util_format_description(format);
1887
1888 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1889 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1890 * for read-only access (with caveats surrounding bounds checks), but
1891 * obviously fails for write access which we have to implement for
1892 * shader images. Luckily, OpenGL doesn't expect this to be supported
1893 * anyway, and so the only impact is on PBO uploads / downloads, which
1894 * shouldn't be expected to be fast for GL_RGB anyway.
1895 */
1896 if (desc->block.bits == 3 * 8 ||
1897 desc->block.bits == 3 * 16) {
1898 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1899 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1900 if (!usage)
1901 return 0;
1902 }
1903 }
1904
1905 first_non_void = util_format_get_first_non_void_channel(format);
1906 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1907 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1908 return 0;
1909
1910 return usage;
1911 }
1912
1913 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1914 {
1915 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1916 r600_translate_colorswap(format, false) != ~0U;
1917 }
1918
1919 static bool si_is_zs_format_supported(enum pipe_format format)
1920 {
1921 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1922 }
1923
1924 static boolean si_is_format_supported(struct pipe_screen *screen,
1925 enum pipe_format format,
1926 enum pipe_texture_target target,
1927 unsigned sample_count,
1928 unsigned usage)
1929 {
1930 unsigned retval = 0;
1931
1932 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1933 R600_ERR("r600: unsupported texture type %d\n", target);
1934 return false;
1935 }
1936
1937 if (!util_format_is_supported(format, usage))
1938 return false;
1939
1940 if (sample_count > 1) {
1941 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1942 return false;
1943
1944 if (usage & PIPE_BIND_SHADER_IMAGE)
1945 return false;
1946
1947 switch (sample_count) {
1948 case 2:
1949 case 4:
1950 case 8:
1951 break;
1952 case 16:
1953 if (format == PIPE_FORMAT_NONE)
1954 return true;
1955 else
1956 return false;
1957 default:
1958 return false;
1959 }
1960 }
1961
1962 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1963 PIPE_BIND_SHADER_IMAGE)) {
1964 if (target == PIPE_BUFFER) {
1965 retval |= si_is_vertex_format_supported(
1966 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1967 PIPE_BIND_SHADER_IMAGE));
1968 } else {
1969 if (si_is_sampler_format_supported(screen, format))
1970 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1971 PIPE_BIND_SHADER_IMAGE);
1972 }
1973 }
1974
1975 if ((usage & (PIPE_BIND_RENDER_TARGET |
1976 PIPE_BIND_DISPLAY_TARGET |
1977 PIPE_BIND_SCANOUT |
1978 PIPE_BIND_SHARED |
1979 PIPE_BIND_BLENDABLE)) &&
1980 si_is_colorbuffer_format_supported(format)) {
1981 retval |= usage &
1982 (PIPE_BIND_RENDER_TARGET |
1983 PIPE_BIND_DISPLAY_TARGET |
1984 PIPE_BIND_SCANOUT |
1985 PIPE_BIND_SHARED);
1986 if (!util_format_is_pure_integer(format) &&
1987 !util_format_is_depth_or_stencil(format))
1988 retval |= usage & PIPE_BIND_BLENDABLE;
1989 }
1990
1991 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1992 si_is_zs_format_supported(format)) {
1993 retval |= PIPE_BIND_DEPTH_STENCIL;
1994 }
1995
1996 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1997 retval |= si_is_vertex_format_supported(screen, format,
1998 PIPE_BIND_VERTEX_BUFFER);
1999 }
2000
2001 if ((usage & PIPE_BIND_LINEAR) &&
2002 !util_format_is_compressed(format) &&
2003 !(usage & PIPE_BIND_DEPTH_STENCIL))
2004 retval |= PIPE_BIND_LINEAR;
2005
2006 return retval == usage;
2007 }
2008
2009 /*
2010 * framebuffer handling
2011 */
2012
2013 static void si_choose_spi_color_formats(struct r600_surface *surf,
2014 unsigned format, unsigned swap,
2015 unsigned ntype, bool is_depth)
2016 {
2017 /* Alpha is needed for alpha-to-coverage.
2018 * Blending may be with or without alpha.
2019 */
2020 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2021 unsigned alpha = 0; /* exports alpha, but may not support blending */
2022 unsigned blend = 0; /* supports blending, but may not export alpha */
2023 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2024
2025 /* Choose the SPI color formats. These are required values for RB+.
2026 * Other chips have multiple choices, though they are not necessarily better.
2027 */
2028 switch (format) {
2029 case V_028C70_COLOR_5_6_5:
2030 case V_028C70_COLOR_1_5_5_5:
2031 case V_028C70_COLOR_5_5_5_1:
2032 case V_028C70_COLOR_4_4_4_4:
2033 case V_028C70_COLOR_10_11_11:
2034 case V_028C70_COLOR_11_11_10:
2035 case V_028C70_COLOR_8:
2036 case V_028C70_COLOR_8_8:
2037 case V_028C70_COLOR_8_8_8_8:
2038 case V_028C70_COLOR_10_10_10_2:
2039 case V_028C70_COLOR_2_10_10_10:
2040 if (ntype == V_028C70_NUMBER_UINT)
2041 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2042 else if (ntype == V_028C70_NUMBER_SINT)
2043 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2044 else
2045 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2046 break;
2047
2048 case V_028C70_COLOR_16:
2049 case V_028C70_COLOR_16_16:
2050 case V_028C70_COLOR_16_16_16_16:
2051 if (ntype == V_028C70_NUMBER_UNORM ||
2052 ntype == V_028C70_NUMBER_SNORM) {
2053 /* UNORM16 and SNORM16 don't support blending */
2054 if (ntype == V_028C70_NUMBER_UNORM)
2055 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2056 else
2057 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2058
2059 /* Use 32 bits per channel for blending. */
2060 if (format == V_028C70_COLOR_16) {
2061 if (swap == V_028C70_SWAP_STD) { /* R */
2062 blend = V_028714_SPI_SHADER_32_R;
2063 blend_alpha = V_028714_SPI_SHADER_32_AR;
2064 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2065 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2066 else
2067 assert(0);
2068 } else if (format == V_028C70_COLOR_16_16) {
2069 if (swap == V_028C70_SWAP_STD) { /* RG */
2070 blend = V_028714_SPI_SHADER_32_GR;
2071 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2072 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2073 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2074 else
2075 assert(0);
2076 } else /* 16_16_16_16 */
2077 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2078 } else if (ntype == V_028C70_NUMBER_UINT)
2079 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2080 else if (ntype == V_028C70_NUMBER_SINT)
2081 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2082 else if (ntype == V_028C70_NUMBER_FLOAT)
2083 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2084 else
2085 assert(0);
2086 break;
2087
2088 case V_028C70_COLOR_32:
2089 if (swap == V_028C70_SWAP_STD) { /* R */
2090 blend = normal = V_028714_SPI_SHADER_32_R;
2091 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2092 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2093 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2094 else
2095 assert(0);
2096 break;
2097
2098 case V_028C70_COLOR_32_32:
2099 if (swap == V_028C70_SWAP_STD) { /* RG */
2100 blend = normal = V_028714_SPI_SHADER_32_GR;
2101 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2102 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2103 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2104 else
2105 assert(0);
2106 break;
2107
2108 case V_028C70_COLOR_32_32_32_32:
2109 case V_028C70_COLOR_8_24:
2110 case V_028C70_COLOR_24_8:
2111 case V_028C70_COLOR_X24_8_32_FLOAT:
2112 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2113 break;
2114
2115 default:
2116 assert(0);
2117 return;
2118 }
2119
2120 /* The DB->CB copy needs 32_ABGR. */
2121 if (is_depth)
2122 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2123
2124 surf->spi_shader_col_format = normal;
2125 surf->spi_shader_col_format_alpha = alpha;
2126 surf->spi_shader_col_format_blend = blend;
2127 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2128 }
2129
2130 static void si_initialize_color_surface(struct si_context *sctx,
2131 struct r600_surface *surf)
2132 {
2133 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2134 unsigned color_info, color_attrib, color_view;
2135 unsigned format, swap, ntype, endian;
2136 const struct util_format_description *desc;
2137 int i;
2138 unsigned blend_clamp = 0, blend_bypass = 0;
2139
2140 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2141 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2142
2143 desc = util_format_description(surf->base.format);
2144 for (i = 0; i < 4; i++) {
2145 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2146 break;
2147 }
2148 }
2149 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2150 ntype = V_028C70_NUMBER_FLOAT;
2151 } else {
2152 ntype = V_028C70_NUMBER_UNORM;
2153 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2154 ntype = V_028C70_NUMBER_SRGB;
2155 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2156 if (desc->channel[i].pure_integer) {
2157 ntype = V_028C70_NUMBER_SINT;
2158 } else {
2159 assert(desc->channel[i].normalized);
2160 ntype = V_028C70_NUMBER_SNORM;
2161 }
2162 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2163 if (desc->channel[i].pure_integer) {
2164 ntype = V_028C70_NUMBER_UINT;
2165 } else {
2166 assert(desc->channel[i].normalized);
2167 ntype = V_028C70_NUMBER_UNORM;
2168 }
2169 }
2170 }
2171
2172 format = si_translate_colorformat(surf->base.format);
2173 if (format == V_028C70_COLOR_INVALID) {
2174 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2175 }
2176 assert(format != V_028C70_COLOR_INVALID);
2177 swap = r600_translate_colorswap(surf->base.format, false);
2178 endian = si_colorformat_endian_swap(format);
2179
2180 /* blend clamp should be set for all NORM/SRGB types */
2181 if (ntype == V_028C70_NUMBER_UNORM ||
2182 ntype == V_028C70_NUMBER_SNORM ||
2183 ntype == V_028C70_NUMBER_SRGB)
2184 blend_clamp = 1;
2185
2186 /* set blend bypass according to docs if SINT/UINT or
2187 8/24 COLOR variants */
2188 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2189 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2190 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2191 blend_clamp = 0;
2192 blend_bypass = 1;
2193 }
2194
2195 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2196 if (format == V_028C70_COLOR_8 ||
2197 format == V_028C70_COLOR_8_8 ||
2198 format == V_028C70_COLOR_8_8_8_8)
2199 surf->color_is_int8 = true;
2200 else if (format == V_028C70_COLOR_10_10_10_2 ||
2201 format == V_028C70_COLOR_2_10_10_10)
2202 surf->color_is_int10 = true;
2203 }
2204
2205 color_info = S_028C70_FORMAT(format) |
2206 S_028C70_COMP_SWAP(swap) |
2207 S_028C70_BLEND_CLAMP(blend_clamp) |
2208 S_028C70_BLEND_BYPASS(blend_bypass) |
2209 S_028C70_SIMPLE_FLOAT(1) |
2210 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2211 ntype != V_028C70_NUMBER_SNORM &&
2212 ntype != V_028C70_NUMBER_SRGB &&
2213 format != V_028C70_COLOR_8_24 &&
2214 format != V_028C70_COLOR_24_8) |
2215 S_028C70_NUMBER_TYPE(ntype) |
2216 S_028C70_ENDIAN(endian);
2217
2218 /* Intensity is implemented as Red, so treat it that way. */
2219 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2220 util_format_is_intensity(surf->base.format));
2221
2222 if (rtex->resource.b.b.nr_samples > 1) {
2223 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2224
2225 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2226 S_028C74_NUM_FRAGMENTS(log_samples);
2227
2228 if (rtex->fmask.size) {
2229 color_info |= S_028C70_COMPRESSION(1);
2230 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2231
2232 if (sctx->b.chip_class == SI) {
2233 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2234 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2235 }
2236 }
2237 }
2238
2239 surf->cb_color_view = color_view;
2240 surf->cb_color_info = color_info;
2241 surf->cb_color_attrib = color_attrib;
2242
2243 if (sctx->b.chip_class >= VI) {
2244 unsigned max_uncompressed_block_size = 2;
2245
2246 if (rtex->resource.b.b.nr_samples > 1) {
2247 if (rtex->surface.bpe == 1)
2248 max_uncompressed_block_size = 0;
2249 else if (rtex->surface.bpe == 2)
2250 max_uncompressed_block_size = 1;
2251 }
2252
2253 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2254 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2255 }
2256
2257 /* This must be set for fast clear to work without FMASK. */
2258 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2259 unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
2260 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2261 }
2262
2263 if (sctx->b.chip_class >= GFX9) {
2264 unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
2265
2266 surf->cb_color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2267 surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2268 S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
2269 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2270 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2271 S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
2272 }
2273
2274 /* Determine pixel shader export format */
2275 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2276
2277 surf->color_initialized = true;
2278 }
2279
2280 static void si_init_depth_surface(struct si_context *sctx,
2281 struct r600_surface *surf)
2282 {
2283 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2284 unsigned level = surf->base.u.tex.level;
2285 unsigned format, stencil_format;
2286 uint32_t z_info, s_info;
2287
2288 format = si_translate_dbformat(rtex->db_render_format);
2289 stencil_format = rtex->surface.flags & RADEON_SURF_SBUFFER ?
2290 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2291
2292 assert(format != V_028040_Z_INVALID);
2293 if (format == V_028040_Z_INVALID)
2294 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2295
2296 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2297 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2298 surf->db_htile_data_base = 0;
2299 surf->db_htile_surface = 0;
2300
2301 if (sctx->b.chip_class >= GFX9) {
2302 assert(rtex->surface.u.gfx9.surf_offset == 0);
2303 surf->db_depth_base = rtex->resource.gpu_address >> 8;
2304 surf->db_stencil_base = (rtex->resource.gpu_address +
2305 rtex->surface.u.gfx9.stencil_offset) >> 8;
2306 z_info = S_028038_FORMAT(format) |
2307 S_028038_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples)) |
2308 S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
2309 S_028038_MAXMIP(rtex->resource.b.b.last_level);
2310 s_info = S_02803C_FORMAT(stencil_format) |
2311 S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
2312 surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
2313 surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
2314 surf->db_depth_view |= S_028008_MIPID(level);
2315 surf->db_depth_size = S_02801C_X_MAX(rtex->resource.b.b.width0 - 1) |
2316 S_02801C_Y_MAX(rtex->resource.b.b.height0 - 1);
2317
2318 /* Only use HTILE for the first level. */
2319 if (rtex->htile_buffer && !level) {
2320 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2321 S_028038_ALLOW_EXPCLEAR(1);
2322
2323 if (rtex->tc_compatible_htile) {
2324 unsigned max_zplanes = 4;
2325
2326 if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2327 rtex->resource.b.b.nr_samples > 1)
2328 max_zplanes = 2;
2329
2330 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2331 S_028038_ITERATE_FLUSH(1);
2332 s_info |= S_02803C_ITERATE_FLUSH(1);
2333 }
2334
2335 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2336 /* Stencil buffer workaround ported from the SI-CI-VI code.
2337 * See that for explanation.
2338 */
2339 s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->resource.b.b.nr_samples <= 1);
2340 } else {
2341 /* Use all HTILE for depth if there's no stencil. */
2342 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2343 }
2344
2345 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2346 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2347 S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
2348 S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
2349 }
2350 } else {
2351 /* SI-CI-VI */
2352 struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
2353
2354 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2355
2356 surf->db_depth_base = (rtex->resource.gpu_address +
2357 rtex->surface.u.legacy.level[level].offset) >> 8;
2358 surf->db_stencil_base = (rtex->resource.gpu_address +
2359 rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
2360
2361 z_info = S_028040_FORMAT(format) |
2362 S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2363 s_info = S_028044_FORMAT(stencil_format);
2364 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2365
2366 if (sctx->b.chip_class >= CIK) {
2367 struct radeon_info *info = &sctx->screen->b.info;
2368 unsigned index = rtex->surface.u.legacy.tiling_index[level];
2369 unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
2370 unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
2371 unsigned tile_mode = info->si_tile_mode_array[index];
2372 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2373 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2374
2375 surf->db_depth_info |=
2376 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2377 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2378 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2379 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2380 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2381 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2382 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2383 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2384 } else {
2385 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2386 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2387 tile_mode_index = si_tile_mode_index(rtex, level, true);
2388 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2389 }
2390
2391 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2392 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2393 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2394 levelinfo->nblk_y) / 64 - 1);
2395
2396 /* Only use HTILE for the first level. */
2397 if (rtex->htile_buffer && !level) {
2398 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2399 S_028040_ALLOW_EXPCLEAR(1);
2400
2401 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2402 /* Workaround: For a not yet understood reason, the
2403 * combination of MSAA, fast stencil clear and stencil
2404 * decompress messes with subsequent stencil buffer
2405 * uses. Problem was reproduced on Verde, Bonaire,
2406 * Tonga, and Carrizo.
2407 *
2408 * Disabling EXPCLEAR works around the problem.
2409 *
2410 * Check piglit's arb_texture_multisample-stencil-clear
2411 * test if you want to try changing this.
2412 */
2413 if (rtex->resource.b.b.nr_samples <= 1)
2414 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2415 } else if (!rtex->tc_compatible_htile) {
2416 /* Use all of the htile_buffer for depth if there's no stencil.
2417 * This must not be set when TC-compatible HTILE is enabled
2418 * due to a hw bug.
2419 */
2420 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2421 }
2422
2423 surf->db_htile_data_base = rtex->htile_buffer->gpu_address >> 8;
2424 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2425
2426 if (rtex->tc_compatible_htile) {
2427 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2428
2429 if (rtex->resource.b.b.nr_samples <= 1)
2430 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2431 else if (rtex->resource.b.b.nr_samples <= 4)
2432 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2433 else
2434 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2435 }
2436 }
2437 }
2438
2439 surf->db_z_info = z_info;
2440 surf->db_stencil_info = s_info;
2441
2442 surf->depth_initialized = true;
2443 }
2444
2445 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2446 {
2447 for (int i = 0; i < state->nr_cbufs; ++i) {
2448 struct r600_surface *surf = NULL;
2449 struct r600_texture *rtex;
2450
2451 if (!state->cbufs[i])
2452 continue;
2453 surf = (struct r600_surface*)state->cbufs[i];
2454 rtex = (struct r600_texture*)surf->base.texture;
2455
2456 p_atomic_dec(&rtex->framebuffers_bound);
2457 }
2458 }
2459
2460 static void si_set_framebuffer_state(struct pipe_context *ctx,
2461 const struct pipe_framebuffer_state *state)
2462 {
2463 struct si_context *sctx = (struct si_context *)ctx;
2464 struct pipe_constant_buffer constbuf = {0};
2465 struct r600_surface *surf = NULL;
2466 struct r600_texture *rtex;
2467 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2468 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2469 bool unbound = false;
2470 int i;
2471
2472 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2473 if (!sctx->framebuffer.state.cbufs[i])
2474 continue;
2475
2476 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2477 if (rtex->dcc_gather_statistics)
2478 vi_separate_dcc_stop_query(ctx, rtex);
2479 }
2480
2481 /* Disable DCC if the formats are incompatible. */
2482 for (i = 0; i < state->nr_cbufs; i++) {
2483 if (!state->cbufs[i])
2484 continue;
2485
2486 surf = (struct r600_surface*)state->cbufs[i];
2487 rtex = (struct r600_texture*)surf->base.texture;
2488
2489 if (!surf->dcc_incompatible)
2490 continue;
2491
2492 /* Since the DCC decompression calls back into set_framebuffer-
2493 * _state, we need to unbind the framebuffer, so that
2494 * vi_separate_dcc_stop_query isn't called twice with the same
2495 * color buffer.
2496 */
2497 if (!unbound) {
2498 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2499 unbound = true;
2500 }
2501
2502 if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
2503 if (!r600_texture_disable_dcc(&sctx->b, rtex))
2504 sctx->b.decompress_dcc(ctx, rtex);
2505
2506 surf->dcc_incompatible = false;
2507 }
2508
2509 /* Only flush TC when changing the framebuffer state, because
2510 * the only client not using TC that can change textures is
2511 * the framebuffer.
2512 *
2513 * Flush all CB and DB caches here because all buffers can be used
2514 * for write by both TC (with shader image stores) and CB/DB.
2515 */
2516 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2517 SI_CONTEXT_INV_GLOBAL_L2 |
2518 SI_CONTEXT_FLUSH_AND_INV_CB |
2519 SI_CONTEXT_FLUSH_AND_INV_DB |
2520 SI_CONTEXT_CS_PARTIAL_FLUSH;
2521
2522 /* Take the maximum of the old and new count. If the new count is lower,
2523 * dirtying is needed to disable the unbound colorbuffers.
2524 */
2525 sctx->framebuffer.dirty_cbufs |=
2526 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2527 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2528
2529 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2530 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2531
2532 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2533 sctx->framebuffer.spi_shader_col_format = 0;
2534 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2535 sctx->framebuffer.spi_shader_col_format_blend = 0;
2536 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2537 sctx->framebuffer.color_is_int8 = 0;
2538 sctx->framebuffer.color_is_int10 = 0;
2539
2540 sctx->framebuffer.compressed_cb_mask = 0;
2541 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2542 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2543 sctx->framebuffer.any_dst_linear = false;
2544
2545 for (i = 0; i < state->nr_cbufs; i++) {
2546 if (!state->cbufs[i])
2547 continue;
2548
2549 surf = (struct r600_surface*)state->cbufs[i];
2550 rtex = (struct r600_texture*)surf->base.texture;
2551
2552 if (!surf->color_initialized) {
2553 si_initialize_color_surface(sctx, surf);
2554 }
2555
2556 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2557 sctx->framebuffer.spi_shader_col_format |=
2558 surf->spi_shader_col_format << (i * 4);
2559 sctx->framebuffer.spi_shader_col_format_alpha |=
2560 surf->spi_shader_col_format_alpha << (i * 4);
2561 sctx->framebuffer.spi_shader_col_format_blend |=
2562 surf->spi_shader_col_format_blend << (i * 4);
2563 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2564 surf->spi_shader_col_format_blend_alpha << (i * 4);
2565
2566 if (surf->color_is_int8)
2567 sctx->framebuffer.color_is_int8 |= 1 << i;
2568 if (surf->color_is_int10)
2569 sctx->framebuffer.color_is_int10 |= 1 << i;
2570
2571 if (rtex->fmask.size) {
2572 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2573 }
2574
2575 if (rtex->surface.is_linear)
2576 sctx->framebuffer.any_dst_linear = true;
2577
2578 r600_context_add_resource_size(ctx, surf->base.texture);
2579
2580 p_atomic_inc(&rtex->framebuffers_bound);
2581
2582 if (rtex->dcc_gather_statistics) {
2583 /* Dirty tracking must be enabled for DCC usage analysis. */
2584 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2585 vi_separate_dcc_start_query(ctx, rtex);
2586 }
2587 }
2588
2589 if (state->zsbuf) {
2590 surf = (struct r600_surface*)state->zsbuf;
2591 rtex = (struct r600_texture*)surf->base.texture;
2592
2593 if (!surf->depth_initialized) {
2594 si_init_depth_surface(sctx, surf);
2595 }
2596 r600_context_add_resource_size(ctx, surf->base.texture);
2597 }
2598
2599 si_update_poly_offset_state(sctx);
2600 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2601 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2602
2603 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2604 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2605
2606 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2607 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2608 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2609
2610 /* Set sample locations as fragment shader constants. */
2611 switch (sctx->framebuffer.nr_samples) {
2612 case 1:
2613 constbuf.user_buffer = sctx->b.sample_locations_1x;
2614 break;
2615 case 2:
2616 constbuf.user_buffer = sctx->b.sample_locations_2x;
2617 break;
2618 case 4:
2619 constbuf.user_buffer = sctx->b.sample_locations_4x;
2620 break;
2621 case 8:
2622 constbuf.user_buffer = sctx->b.sample_locations_8x;
2623 break;
2624 case 16:
2625 constbuf.user_buffer = sctx->b.sample_locations_16x;
2626 break;
2627 default:
2628 R600_ERR("Requested an invalid number of samples %i.\n",
2629 sctx->framebuffer.nr_samples);
2630 assert(0);
2631 }
2632 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2633 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2634
2635 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2636 }
2637
2638 sctx->do_update_shaders = true;
2639
2640 if (!sctx->decompression_enabled) {
2641 /* Prevent textures decompression when the framebuffer state
2642 * changes come from the decompression passes themselves.
2643 */
2644 sctx->need_check_render_feedback = true;
2645 sctx->framebuffer.do_update_surf_dirtiness = true;
2646 }
2647 }
2648
2649 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2650 {
2651 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2652 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2653 unsigned i, nr_cbufs = state->nr_cbufs;
2654 struct r600_texture *tex = NULL;
2655 struct r600_surface *cb = NULL;
2656 unsigned cb_color_info = 0;
2657
2658 /* Colorbuffers. */
2659 for (i = 0; i < nr_cbufs; i++) {
2660 uint64_t cb_color_base, cb_color_fmask, cb_dcc_base;
2661 unsigned cb_color_attrib;
2662
2663 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2664 continue;
2665
2666 cb = (struct r600_surface*)state->cbufs[i];
2667 if (!cb) {
2668 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2669 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2670 continue;
2671 }
2672
2673 tex = (struct r600_texture *)cb->base.texture;
2674 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2675 &tex->resource, RADEON_USAGE_READWRITE,
2676 tex->resource.b.b.nr_samples > 1 ?
2677 RADEON_PRIO_COLOR_BUFFER_MSAA :
2678 RADEON_PRIO_COLOR_BUFFER);
2679
2680 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2681 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2682 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2683 RADEON_PRIO_CMASK);
2684 }
2685
2686 if (tex->dcc_separate_buffer)
2687 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2688 tex->dcc_separate_buffer,
2689 RADEON_USAGE_READWRITE,
2690 RADEON_PRIO_DCC);
2691
2692 /* Compute mutable surface parameters. */
2693 cb_color_base = tex->resource.gpu_address >> 8;
2694 cb_color_fmask = cb_color_base;
2695 cb_dcc_base = 0;
2696 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2697 cb_color_attrib = cb->cb_color_attrib;
2698
2699 if (tex->fmask.size)
2700 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2701
2702 /* Set up DCC. */
2703 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
2704 bool is_msaa_resolve_dst = state->cbufs[0] &&
2705 state->cbufs[0]->texture->nr_samples > 1 &&
2706 state->cbufs[1] == &cb->base &&
2707 state->cbufs[1]->texture->nr_samples <= 1;
2708
2709 if (!is_msaa_resolve_dst)
2710 cb_color_info |= S_028C70_DCC_ENABLE(1);
2711
2712 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2713 tex->dcc_offset) >> 8;
2714 }
2715
2716 if (sctx->b.chip_class >= GFX9) {
2717 struct gfx9_surf_meta_flags meta;
2718
2719 if (tex->dcc_offset)
2720 meta = tex->surface.u.gfx9.dcc;
2721 else
2722 meta = tex->surface.u.gfx9.cmask;
2723
2724 /* Set mutable surface parameters. */
2725 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
2726 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2727 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
2728 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2729 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2730
2731 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
2732 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2733 radeon_emit(cs, cb_color_base >> 32); /* CB_COLOR0_BASE_EXT */
2734 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
2735 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2736 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2737 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2738 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2739 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2740 radeon_emit(cs, tex->cmask.base_address_reg >> 32); /* CB_COLOR0_CMASK_BASE_EXT */
2741 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2742 radeon_emit(cs, cb_color_fmask >> 32); /* CB_COLOR0_FMASK_BASE_EXT */
2743 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2744 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2745 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
2746 radeon_emit(cs, cb_dcc_base >> 32); /* CB_COLOR0_DCC_BASE_EXT */
2747
2748 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
2749 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
2750 } else {
2751 /* Compute mutable surface parameters (SI-CI-VI). */
2752 const struct legacy_surf_level *level_info =
2753 &tex->surface.u.legacy.level[cb->base.u.tex.level];
2754 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2755 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2756
2757 cb_color_base += level_info->offset >> 8;
2758 if (cb_dcc_base)
2759 cb_dcc_base += level_info->dcc_offset >> 8;
2760
2761 pitch_tile_max = level_info->nblk_x / 8 - 1;
2762 slice_tile_max = level_info->nblk_x *
2763 level_info->nblk_y / 64 - 1;
2764 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2765
2766 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2767 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2768 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2769
2770 if (tex->fmask.size) {
2771 if (sctx->b.chip_class >= CIK)
2772 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2773 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2774 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2775 } else {
2776 /* This must be set for fast clear to work without FMASK. */
2777 if (sctx->b.chip_class >= CIK)
2778 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2779 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2780 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2781 }
2782
2783 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2784 sctx->b.chip_class >= VI ? 14 : 13);
2785 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
2786 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
2787 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
2788 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
2789 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
2790 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
2791 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
2792 radeon_emit(cs, tex->cmask.base_address_reg); /* CB_COLOR0_CMASK */
2793 radeon_emit(cs, tex->cmask.slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
2794 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
2795 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
2796 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
2797 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
2798
2799 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2800 radeon_emit(cs, cb_dcc_base);
2801 }
2802 }
2803 for (; i < 8 ; i++)
2804 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2805 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2806
2807 /* ZS buffer. */
2808 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2809 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2810 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2811
2812 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2813 &rtex->resource, RADEON_USAGE_READWRITE,
2814 zb->base.texture->nr_samples > 1 ?
2815 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2816 RADEON_PRIO_DEPTH_BUFFER);
2817
2818 if (zb->db_htile_data_base) {
2819 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2820 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2821 RADEON_PRIO_HTILE);
2822 }
2823
2824 if (sctx->b.chip_class >= GFX9) {
2825 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
2826 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
2827 radeon_emit(cs, zb->db_htile_data_base >> 32); /* DB_HTILE_DATA_BASE_HI */
2828 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2829
2830 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
2831 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2832 S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2833 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2834 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2835 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_READ_BASE_HI */
2836 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2837 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_READ_BASE_HI */
2838 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2839 radeon_emit(cs, zb->db_depth_base >> 32); /* DB_Z_WRITE_BASE_HI */
2840 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2841 radeon_emit(cs, zb->db_stencil_base >> 32); /* DB_STENCIL_WRITE_BASE_HI */
2842
2843 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
2844 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
2845 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
2846 } else {
2847 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2848
2849 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2850 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
2851 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
2852 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2853 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
2854 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
2855 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
2856 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
2857 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
2858 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
2859 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
2860 }
2861
2862 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2863 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2864 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2865
2866 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2867 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2868 } else if (sctx->framebuffer.dirty_zsbuf) {
2869 if (sctx->b.chip_class >= GFX9)
2870 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
2871 else
2872 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2873
2874 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
2875 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
2876 }
2877
2878 /* Framebuffer dimensions. */
2879 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2880 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2881 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2882
2883 if (sctx->b.chip_class >= GFX9) {
2884 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2885 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
2886 }
2887
2888 sctx->framebuffer.dirty_cbufs = 0;
2889 sctx->framebuffer.dirty_zsbuf = false;
2890 }
2891
2892 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2893 struct r600_atom *atom)
2894 {
2895 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2896 unsigned nr_samples = sctx->framebuffer.nr_samples;
2897 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
2898
2899 /* Smoothing (only possible with nr_samples == 1) uses the same
2900 * sample locations as the MSAA it simulates.
2901 */
2902 if (nr_samples <= 1 && sctx->smoothing_enabled)
2903 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2904
2905 /* On Polaris, the small primitive filter uses the sample locations
2906 * even when MSAA is off, so we need to make sure they're set to 0.
2907 */
2908 if (has_msaa_sample_loc_bug)
2909 nr_samples = MAX2(nr_samples, 1);
2910
2911 if (nr_samples >= 1 &&
2912 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2913 sctx->msaa_sample_locs.nr_samples = nr_samples;
2914 cayman_emit_msaa_sample_locs(cs, nr_samples);
2915 }
2916
2917 if (sctx->b.family >= CHIP_POLARIS10) {
2918 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2919 unsigned small_prim_filter_cntl =
2920 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2921 /* line bug */
2922 S_028830_LINE_FILTER_DISABLE(sctx->b.family <= CHIP_POLARIS12);
2923
2924 /* The alternative of setting sample locations to 0 would
2925 * require a DB flush to avoid Z errors, see
2926 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2927 */
2928 if (has_msaa_sample_loc_bug &&
2929 sctx->framebuffer.nr_samples > 1 &&
2930 rs && !rs->multisample_enable)
2931 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2932
2933 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2934 small_prim_filter_cntl);
2935 }
2936 }
2937
2938 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2939 {
2940 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2941 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2942 /* 33% faster rendering to linear color buffers */
2943 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2944 unsigned sc_mode_cntl_1 =
2945 S_028A4C_WALK_SIZE(dst_is_linear) |
2946 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2947 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2948 /* always 1: */
2949 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2950 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2951 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2952 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2953 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2954 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2955
2956 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2957 sctx->ps_iter_samples,
2958 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2959 sc_mode_cntl_1);
2960
2961 /* GFX9: Flush DFSM when the AA mode changes. */
2962 if (sctx->b.chip_class >= GFX9) {
2963 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2964 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
2965 }
2966 }
2967
2968 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2969 {
2970 struct si_context *sctx = (struct si_context *)ctx;
2971
2972 if (sctx->ps_iter_samples == min_samples)
2973 return;
2974
2975 sctx->ps_iter_samples = min_samples;
2976 sctx->do_update_shaders = true;
2977
2978 if (sctx->framebuffer.nr_samples > 1)
2979 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2980 }
2981
2982 /*
2983 * Samplers
2984 */
2985
2986 /**
2987 * Build the sampler view descriptor for a buffer texture.
2988 * @param state 256-bit descriptor; only the high 128 bits are filled in
2989 */
2990 void
2991 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2992 enum pipe_format format,
2993 unsigned offset, unsigned size,
2994 uint32_t *state)
2995 {
2996 const struct util_format_description *desc;
2997 int first_non_void;
2998 unsigned stride;
2999 unsigned num_records;
3000 unsigned num_format, data_format;
3001
3002 desc = util_format_description(format);
3003 first_non_void = util_format_get_first_non_void_channel(format);
3004 stride = desc->block.bits / 8;
3005 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
3006 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
3007
3008 num_records = size / stride;
3009 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3010
3011 /* The NUM_RECORDS field has a different meaning depending on the chip,
3012 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3013 *
3014 * SI-CIK:
3015 * - If STRIDE == 0, it's in byte units.
3016 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3017 *
3018 * VI:
3019 * - For SMEM and STRIDE == 0, it's in byte units.
3020 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3021 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3022 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3023 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3024 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3025 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3026 * That way the same descriptor can be used by both SMEM and VMEM.
3027 *
3028 * GFX9:
3029 * - For SMEM and STRIDE == 0, it's in byte units.
3030 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3031 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3032 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3033 */
3034 if (screen->b.chip_class >= GFX9)
3035 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3036 * from STRIDE to bytes. This works around it by setting
3037 * NUM_RECORDS to at least the size of one element, so that
3038 * the first element is readable when IDXEN == 0.
3039 *
3040 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3041 * IDXEN is enforced?
3042 */
3043 num_records = num_records ? MAX2(num_records, stride) : 0;
3044 else if (screen->b.chip_class == VI)
3045 num_records *= stride;
3046
3047 state[4] = 0;
3048 state[5] = S_008F04_STRIDE(stride);
3049 state[6] = num_records;
3050 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3051 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3052 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3053 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3054 S_008F0C_NUM_FORMAT(num_format) |
3055 S_008F0C_DATA_FORMAT(data_format);
3056 }
3057
3058 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3059 {
3060 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3061
3062 if (swizzle[3] == PIPE_SWIZZLE_X) {
3063 /* For the pre-defined border color values (white, opaque
3064 * black, transparent black), the only thing that matters is
3065 * that the alpha channel winds up in the correct place
3066 * (because the RGB channels are all the same) so either of
3067 * these enumerations will work.
3068 */
3069 if (swizzle[2] == PIPE_SWIZZLE_Y)
3070 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3071 else
3072 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3073 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3074 if (swizzle[1] == PIPE_SWIZZLE_Y)
3075 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3076 else
3077 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3078 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3079 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3080 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3081 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3082 }
3083
3084 return bc_swizzle;
3085 }
3086
3087 /**
3088 * Build the sampler view descriptor for a texture.
3089 */
3090 void
3091 si_make_texture_descriptor(struct si_screen *screen,
3092 struct r600_texture *tex,
3093 bool sampler,
3094 enum pipe_texture_target target,
3095 enum pipe_format pipe_format,
3096 const unsigned char state_swizzle[4],
3097 unsigned first_level, unsigned last_level,
3098 unsigned first_layer, unsigned last_layer,
3099 unsigned width, unsigned height, unsigned depth,
3100 uint32_t *state,
3101 uint32_t *fmask_state)
3102 {
3103 struct pipe_resource *res = &tex->resource.b.b;
3104 const struct util_format_description *base_desc, *desc;
3105 unsigned char swizzle[4];
3106 int first_non_void;
3107 unsigned num_format, data_format, type;
3108 uint64_t va;
3109
3110 desc = util_format_description(pipe_format);
3111 base_desc = util_format_description(res->format);
3112
3113 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3114 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3115 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3116 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3117
3118 switch (pipe_format) {
3119 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3120 case PIPE_FORMAT_X32_S8X24_UINT:
3121 case PIPE_FORMAT_X8Z24_UNORM:
3122 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3123 break;
3124 case PIPE_FORMAT_X24S8_UINT:
3125 /*
3126 * X24S8 is implemented as an 8_8_8_8 data format, to
3127 * fix texture gathers. This affects at least
3128 * GL45-CTS.texture_cube_map_array.sampling on VI.
3129 */
3130 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3131 break;
3132 default:
3133 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3134 }
3135 } else {
3136 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3137 }
3138
3139 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3140
3141 switch (pipe_format) {
3142 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3143 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3144 break;
3145 default:
3146 if (first_non_void < 0) {
3147 if (util_format_is_compressed(pipe_format)) {
3148 switch (pipe_format) {
3149 case PIPE_FORMAT_DXT1_SRGB:
3150 case PIPE_FORMAT_DXT1_SRGBA:
3151 case PIPE_FORMAT_DXT3_SRGBA:
3152 case PIPE_FORMAT_DXT5_SRGBA:
3153 case PIPE_FORMAT_BPTC_SRGBA:
3154 case PIPE_FORMAT_ETC2_SRGB8:
3155 case PIPE_FORMAT_ETC2_SRGB8A1:
3156 case PIPE_FORMAT_ETC2_SRGBA8:
3157 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3158 break;
3159 case PIPE_FORMAT_RGTC1_SNORM:
3160 case PIPE_FORMAT_LATC1_SNORM:
3161 case PIPE_FORMAT_RGTC2_SNORM:
3162 case PIPE_FORMAT_LATC2_SNORM:
3163 case PIPE_FORMAT_ETC2_R11_SNORM:
3164 case PIPE_FORMAT_ETC2_RG11_SNORM:
3165 /* implies float, so use SNORM/UNORM to determine
3166 whether data is signed or not */
3167 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3168 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3169 break;
3170 default:
3171 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3172 break;
3173 }
3174 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3175 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3176 } else {
3177 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3178 }
3179 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3180 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3181 } else {
3182 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3183
3184 switch (desc->channel[first_non_void].type) {
3185 case UTIL_FORMAT_TYPE_FLOAT:
3186 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3187 break;
3188 case UTIL_FORMAT_TYPE_SIGNED:
3189 if (desc->channel[first_non_void].normalized)
3190 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3191 else if (desc->channel[first_non_void].pure_integer)
3192 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3193 else
3194 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3195 break;
3196 case UTIL_FORMAT_TYPE_UNSIGNED:
3197 if (desc->channel[first_non_void].normalized)
3198 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3199 else if (desc->channel[first_non_void].pure_integer)
3200 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3201 else
3202 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3203 }
3204 }
3205 }
3206
3207 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
3208 if (data_format == ~0) {
3209 data_format = 0;
3210 }
3211
3212 /* Enable clamping for UNORM depth formats promoted to Z32F. */
3213 if (screen->b.chip_class >= GFX9 &&
3214 util_format_has_depth(desc) &&
3215 num_format == V_008F14_IMG_NUM_FORMAT_FLOAT &&
3216 util_get_depth_format_type(base_desc) != UTIL_FORMAT_TYPE_FLOAT) {
3217 /* NUM_FORMAT=FLOAT and DATA_FORMAT=24_8 means "clamp to [0,1]". */
3218 data_format = V_008F14_IMG_DATA_FORMAT_24_8;
3219 }
3220
3221 if (!sampler &&
3222 (res->target == PIPE_TEXTURE_CUBE ||
3223 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3224 (screen->b.chip_class <= VI &&
3225 res->target == PIPE_TEXTURE_3D))) {
3226 /* For the purpose of shader images, treat cube maps and 3D
3227 * textures as 2D arrays. For 3D textures, the address
3228 * calculations for mipmaps are different, so we rely on the
3229 * caller to effectively disable mipmaps.
3230 */
3231 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3232
3233 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3234 } else {
3235 type = si_tex_dim(screen, tex, target, res->nr_samples);
3236 }
3237
3238 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3239 height = 1;
3240 depth = res->array_size;
3241 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3242 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3243 if (sampler || res->target != PIPE_TEXTURE_3D)
3244 depth = res->array_size;
3245 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3246 depth = res->array_size / 6;
3247
3248 state[0] = 0;
3249 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3250 S_008F14_NUM_FORMAT_GFX6(num_format));
3251 state[2] = (S_008F18_WIDTH(width - 1) |
3252 S_008F18_HEIGHT(height - 1) |
3253 S_008F18_PERF_MOD(4));
3254 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3255 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3256 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3257 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3258 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
3259 0 : first_level) |
3260 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
3261 util_logbase2(res->nr_samples) :
3262 last_level) |
3263 S_008F1C_TYPE(type));
3264 state[4] = 0;
3265 state[5] = S_008F24_BASE_ARRAY(first_layer);
3266 state[6] = 0;
3267 state[7] = 0;
3268
3269 if (screen->b.chip_class >= GFX9) {
3270 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3271
3272 /* Depth is the the last accessible layer on Gfx9.
3273 * The hw doesn't need to know the total number of layers.
3274 */
3275 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3276 state[4] |= S_008F20_DEPTH(depth - 1);
3277 else
3278 state[4] |= S_008F20_DEPTH(last_layer);
3279
3280 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3281 state[5] |= S_008F24_MAX_MIP(res->nr_samples > 1 ?
3282 util_logbase2(res->nr_samples) :
3283 tex->resource.b.b.last_level);
3284 } else {
3285 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3286 state[4] |= S_008F20_DEPTH(depth - 1);
3287 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3288 }
3289
3290 if (tex->dcc_offset) {
3291 unsigned swap = r600_translate_colorswap(pipe_format, false);
3292
3293 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
3294 } else {
3295 /* The last dword is unused by hw. The shader uses it to clear
3296 * bits in the first dword of sampler state.
3297 */
3298 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
3299 if (first_level == last_level)
3300 state[7] = C_008F30_MAX_ANISO_RATIO;
3301 else
3302 state[7] = 0xffffffff;
3303 }
3304 }
3305
3306 /* Initialize the sampler view for FMASK. */
3307 if (tex->fmask.size) {
3308 uint32_t data_format, num_format;
3309
3310 va = tex->resource.gpu_address + tex->fmask.offset;
3311
3312 if (screen->b.chip_class >= GFX9) {
3313 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3314 switch (res->nr_samples) {
3315 case 2:
3316 num_format = V_008F14_IMG_FMASK_8_2_2;
3317 break;
3318 case 4:
3319 num_format = V_008F14_IMG_FMASK_8_4_4;
3320 break;
3321 case 8:
3322 num_format = V_008F14_IMG_FMASK_32_8_8;
3323 break;
3324 default:
3325 unreachable("invalid nr_samples");
3326 }
3327 } else {
3328 switch (res->nr_samples) {
3329 case 2:
3330 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3331 break;
3332 case 4:
3333 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3334 break;
3335 case 8:
3336 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3337 break;
3338 default:
3339 unreachable("invalid nr_samples");
3340 }
3341 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3342 }
3343
3344 fmask_state[0] = va >> 8;
3345 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3346 S_008F14_DATA_FORMAT_GFX6(data_format) |
3347 S_008F14_NUM_FORMAT_GFX6(num_format);
3348 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3349 S_008F18_HEIGHT(height - 1);
3350 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3351 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3352 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3353 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3354 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3355 fmask_state[4] = 0;
3356 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3357 fmask_state[6] = 0;
3358 fmask_state[7] = 0;
3359
3360 if (screen->b.chip_class >= GFX9) {
3361 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3362 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3363 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3364 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3365 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3366 } else {
3367 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index);
3368 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3369 S_008F20_PITCH_GFX6(tex->fmask.pitch_in_pixels - 1);
3370 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3371 }
3372 }
3373 }
3374
3375 /**
3376 * Create a sampler view.
3377 *
3378 * @param ctx context
3379 * @param texture texture
3380 * @param state sampler view template
3381 * @param width0 width0 override (for compressed textures as int)
3382 * @param height0 height0 override (for compressed textures as int)
3383 * @param force_level set the base address to the level (for compressed textures)
3384 */
3385 struct pipe_sampler_view *
3386 si_create_sampler_view_custom(struct pipe_context *ctx,
3387 struct pipe_resource *texture,
3388 const struct pipe_sampler_view *state,
3389 unsigned width0, unsigned height0,
3390 unsigned force_level)
3391 {
3392 struct si_context *sctx = (struct si_context*)ctx;
3393 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3394 struct r600_texture *tmp = (struct r600_texture*)texture;
3395 unsigned base_level, first_level, last_level;
3396 unsigned char state_swizzle[4];
3397 unsigned height, depth, width;
3398 unsigned last_layer = state->u.tex.last_layer;
3399 enum pipe_format pipe_format;
3400 const struct legacy_surf_level *surflevel;
3401
3402 if (!view)
3403 return NULL;
3404
3405 /* initialize base object */
3406 view->base = *state;
3407 view->base.texture = NULL;
3408 view->base.reference.count = 1;
3409 view->base.context = ctx;
3410
3411 assert(texture);
3412 pipe_resource_reference(&view->base.texture, texture);
3413
3414 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3415 state->format == PIPE_FORMAT_S8X24_UINT ||
3416 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3417 state->format == PIPE_FORMAT_S8_UINT)
3418 view->is_stencil_sampler = true;
3419
3420 /* Buffer resource. */
3421 if (texture->target == PIPE_BUFFER) {
3422 si_make_buffer_descriptor(sctx->screen,
3423 (struct r600_resource *)texture,
3424 state->format,
3425 state->u.buf.offset,
3426 state->u.buf.size,
3427 view->state);
3428 return &view->base;
3429 }
3430
3431 state_swizzle[0] = state->swizzle_r;
3432 state_swizzle[1] = state->swizzle_g;
3433 state_swizzle[2] = state->swizzle_b;
3434 state_swizzle[3] = state->swizzle_a;
3435
3436 base_level = 0;
3437 first_level = state->u.tex.first_level;
3438 last_level = state->u.tex.last_level;
3439 width = width0;
3440 height = height0;
3441 depth = texture->depth0;
3442
3443 if (sctx->b.chip_class <= VI && force_level) {
3444 assert(force_level == first_level &&
3445 force_level == last_level);
3446 base_level = force_level;
3447 first_level = 0;
3448 last_level = 0;
3449 width = u_minify(width, force_level);
3450 height = u_minify(height, force_level);
3451 depth = u_minify(depth, force_level);
3452 }
3453
3454 /* This is not needed if state trackers set last_layer correctly. */
3455 if (state->target == PIPE_TEXTURE_1D ||
3456 state->target == PIPE_TEXTURE_2D ||
3457 state->target == PIPE_TEXTURE_RECT ||
3458 state->target == PIPE_TEXTURE_CUBE)
3459 last_layer = state->u.tex.first_layer;
3460
3461 /* Texturing with separate depth and stencil. */
3462 pipe_format = state->format;
3463
3464 /* Depth/stencil texturing sometimes needs separate texture. */
3465 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3466 if (!tmp->flushed_depth_texture &&
3467 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3468 pipe_resource_reference(&view->base.texture, NULL);
3469 FREE(view);
3470 return NULL;
3471 }
3472
3473 assert(tmp->flushed_depth_texture);
3474
3475 /* Override format for the case where the flushed texture
3476 * contains only Z or only S.
3477 */
3478 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3479 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3480
3481 tmp = tmp->flushed_depth_texture;
3482 }
3483
3484 surflevel = tmp->surface.u.legacy.level;
3485
3486 if (tmp->db_compatible) {
3487 if (!view->is_stencil_sampler)
3488 pipe_format = tmp->db_render_format;
3489
3490 switch (pipe_format) {
3491 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3492 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3493 break;
3494 case PIPE_FORMAT_X8Z24_UNORM:
3495 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3496 /* Z24 is always stored like this for DB
3497 * compatibility.
3498 */
3499 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3500 break;
3501 case PIPE_FORMAT_X24S8_UINT:
3502 case PIPE_FORMAT_S8X24_UINT:
3503 case PIPE_FORMAT_X32_S8X24_UINT:
3504 pipe_format = PIPE_FORMAT_S8_UINT;
3505 surflevel = tmp->surface.u.legacy.stencil_level;
3506 break;
3507 default:;
3508 }
3509 }
3510
3511 view->dcc_incompatible =
3512 vi_dcc_formats_are_incompatible(texture,
3513 state->u.tex.first_level,
3514 state->format);
3515
3516 si_make_texture_descriptor(sctx->screen, tmp, true,
3517 state->target, pipe_format, state_swizzle,
3518 first_level, last_level,
3519 state->u.tex.first_layer, last_layer,
3520 width, height, depth,
3521 view->state, view->fmask_state);
3522
3523 view->base_level_info = &surflevel[base_level];
3524 view->base_level = base_level;
3525 view->block_width = util_format_get_blockwidth(pipe_format);
3526 return &view->base;
3527 }
3528
3529 static struct pipe_sampler_view *
3530 si_create_sampler_view(struct pipe_context *ctx,
3531 struct pipe_resource *texture,
3532 const struct pipe_sampler_view *state)
3533 {
3534 return si_create_sampler_view_custom(ctx, texture, state,
3535 texture ? texture->width0 : 0,
3536 texture ? texture->height0 : 0, 0);
3537 }
3538
3539 static void si_sampler_view_destroy(struct pipe_context *ctx,
3540 struct pipe_sampler_view *state)
3541 {
3542 struct si_sampler_view *view = (struct si_sampler_view *)state;
3543
3544 pipe_resource_reference(&state->texture, NULL);
3545 FREE(view);
3546 }
3547
3548 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3549 {
3550 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3551 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3552 (linear_filter &&
3553 (wrap == PIPE_TEX_WRAP_CLAMP ||
3554 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3555 }
3556
3557 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3558 {
3559 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3560 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3561
3562 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3563 state->border_color.ui[2] || state->border_color.ui[3]) &&
3564 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3565 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3566 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3567 }
3568
3569 static void *si_create_sampler_state(struct pipe_context *ctx,
3570 const struct pipe_sampler_state *state)
3571 {
3572 struct si_context *sctx = (struct si_context *)ctx;
3573 struct r600_common_screen *rscreen = sctx->b.screen;
3574 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3575 unsigned border_color_type, border_color_index = 0;
3576 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3577 : state->max_anisotropy;
3578 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3579
3580 if (!rstate) {
3581 return NULL;
3582 }
3583
3584 if (!sampler_state_needs_border_color(state))
3585 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3586 else if (state->border_color.f[0] == 0 &&
3587 state->border_color.f[1] == 0 &&
3588 state->border_color.f[2] == 0 &&
3589 state->border_color.f[3] == 0)
3590 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3591 else if (state->border_color.f[0] == 0 &&
3592 state->border_color.f[1] == 0 &&
3593 state->border_color.f[2] == 0 &&
3594 state->border_color.f[3] == 1)
3595 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3596 else if (state->border_color.f[0] == 1 &&
3597 state->border_color.f[1] == 1 &&
3598 state->border_color.f[2] == 1 &&
3599 state->border_color.f[3] == 1)
3600 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3601 else {
3602 int i;
3603
3604 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3605
3606 /* Check if the border has been uploaded already. */
3607 for (i = 0; i < sctx->border_color_count; i++)
3608 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3609 sizeof(state->border_color)) == 0)
3610 break;
3611
3612 if (i >= SI_MAX_BORDER_COLORS) {
3613 /* Getting 4096 unique border colors is very unlikely. */
3614 fprintf(stderr, "radeonsi: The border color table is full. "
3615 "Any new border colors will be just black. "
3616 "Please file a bug.\n");
3617 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3618 } else {
3619 if (i == sctx->border_color_count) {
3620 /* Upload a new border color. */
3621 memcpy(&sctx->border_color_table[i], &state->border_color,
3622 sizeof(state->border_color));
3623 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3624 &state->border_color,
3625 sizeof(state->border_color));
3626 sctx->border_color_count++;
3627 }
3628
3629 border_color_index = i;
3630 }
3631 }
3632
3633 #ifdef DEBUG
3634 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3635 #endif
3636 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3637 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3638 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3639 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3640 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3641 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3642 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3643 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3644 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3645 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3646 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3647 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3648 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3649 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3650 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3651 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3652 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3653 S_008F38_MIP_POINT_PRECLAMP(1) |
3654 S_008F38_DISABLE_LSB_CEIL(sctx->b.chip_class <= VI) |
3655 S_008F38_FILTER_PREC_FIX(1) |
3656 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3657 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3658 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3659 return rstate;
3660 }
3661
3662 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3663 {
3664 struct si_context *sctx = (struct si_context *)ctx;
3665
3666 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3667 return;
3668
3669 sctx->sample_mask.sample_mask = sample_mask;
3670 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3671 }
3672
3673 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3674 {
3675 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3676 unsigned mask = sctx->sample_mask.sample_mask;
3677
3678 /* Needed for line and polygon smoothing as well as for the Polaris
3679 * small primitive filter. We expect the state tracker to take care of
3680 * this for us.
3681 */
3682 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3683 (mask & 1 && sctx->blitter->running));
3684
3685 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3686 radeon_emit(cs, mask | (mask << 16));
3687 radeon_emit(cs, mask | (mask << 16));
3688 }
3689
3690 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3691 {
3692 #ifdef DEBUG
3693 struct si_sampler_state *s = state;
3694
3695 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3696 s->magic = 0;
3697 #endif
3698 free(state);
3699 }
3700
3701 /*
3702 * Vertex elements & buffers
3703 */
3704
3705 static void *si_create_vertex_elements(struct pipe_context *ctx,
3706 unsigned count,
3707 const struct pipe_vertex_element *elements)
3708 {
3709 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
3710 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3711 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3712 int i;
3713
3714 assert(count <= SI_MAX_ATTRIBS);
3715 if (!v)
3716 return NULL;
3717
3718 v->count = count;
3719 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
3720
3721 for (i = 0; i < count; ++i) {
3722 const struct util_format_description *desc;
3723 const struct util_format_channel_description *channel;
3724 unsigned data_format, num_format;
3725 int first_non_void;
3726 unsigned vbo_index = elements[i].vertex_buffer_index;
3727 unsigned char swizzle[4];
3728
3729 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3730 FREE(v);
3731 return NULL;
3732 }
3733
3734 if (elements[i].instance_divisor)
3735 v->uses_instance_divisors = true;
3736
3737 if (!used[vbo_index]) {
3738 v->first_vb_use_mask |= 1 << i;
3739 used[vbo_index] = true;
3740 }
3741
3742 desc = util_format_description(elements[i].src_format);
3743 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3744 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3745 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3746 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3747 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
3748
3749 v->format_size[i] = desc->block.bits / 8;
3750
3751 /* The hardware always treats the 2-bit alpha channel as
3752 * unsigned, so a shader workaround is needed. The affected
3753 * chips are VI and older except Stoney (GFX8.1).
3754 */
3755 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
3756 sscreen->b.chip_class <= VI &&
3757 sscreen->b.family != CHIP_STONEY) {
3758 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3759 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
3760 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3761 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
3762 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3763 /* This isn't actually used in OpenGL. */
3764 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
3765 }
3766 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3767 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3768 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
3769 else
3770 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
3771 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3772 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3773 if (channel->normalized) {
3774 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3775 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
3776 else
3777 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
3778 } else {
3779 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
3780 }
3781 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3782 if (channel->normalized) {
3783 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3784 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
3785 else
3786 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
3787 } else {
3788 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
3789 }
3790 }
3791 } else if (channel && channel->size == 64 &&
3792 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
3793 switch (desc->nr_channels) {
3794 case 1:
3795 case 2:
3796 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
3797 swizzle[0] = PIPE_SWIZZLE_X;
3798 swizzle[1] = PIPE_SWIZZLE_Y;
3799 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
3800 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
3801 break;
3802 case 3:
3803 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
3804 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
3805 swizzle[1] = PIPE_SWIZZLE_Y;
3806 swizzle[2] = PIPE_SWIZZLE_0;
3807 swizzle[3] = PIPE_SWIZZLE_0;
3808 break;
3809 case 4:
3810 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
3811 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
3812 swizzle[1] = PIPE_SWIZZLE_Y;
3813 swizzle[2] = PIPE_SWIZZLE_Z;
3814 swizzle[3] = PIPE_SWIZZLE_W;
3815 break;
3816 default:
3817 assert(0);
3818 }
3819 } else if (channel && desc->nr_channels == 3) {
3820 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
3821
3822 if (channel->size == 8) {
3823 if (channel->pure_integer)
3824 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
3825 else
3826 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
3827 } else if (channel->size == 16) {
3828 if (channel->pure_integer)
3829 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
3830 else
3831 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
3832 }
3833 }
3834
3835 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3836 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3837 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3838 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3839 S_008F0C_NUM_FORMAT(num_format) |
3840 S_008F0C_DATA_FORMAT(data_format);
3841 }
3842 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3843
3844 return v;
3845 }
3846
3847 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3848 {
3849 struct si_context *sctx = (struct si_context *)ctx;
3850 struct si_vertex_element *old = sctx->vertex_elements;
3851 struct si_vertex_element *v = (struct si_vertex_element*)state;
3852
3853 sctx->vertex_elements = v;
3854 sctx->vertex_buffers_dirty = true;
3855
3856 if (v &&
3857 (!old ||
3858 old->count != v->count ||
3859 old->uses_instance_divisors != v->uses_instance_divisors ||
3860 v->uses_instance_divisors || /* we don't check which divisors changed */
3861 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
3862 sctx->do_update_shaders = true;
3863 }
3864
3865 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3866 {
3867 struct si_context *sctx = (struct si_context *)ctx;
3868
3869 if (sctx->vertex_elements == state)
3870 sctx->vertex_elements = NULL;
3871 FREE(state);
3872 }
3873
3874 static void si_set_vertex_buffers(struct pipe_context *ctx,
3875 unsigned start_slot, unsigned count,
3876 const struct pipe_vertex_buffer *buffers)
3877 {
3878 struct si_context *sctx = (struct si_context *)ctx;
3879 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3880 int i;
3881
3882 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3883
3884 if (buffers) {
3885 for (i = 0; i < count; i++) {
3886 const struct pipe_vertex_buffer *src = buffers + i;
3887 struct pipe_vertex_buffer *dsti = dst + i;
3888 struct pipe_resource *buf = src->buffer.resource;
3889
3890 pipe_resource_reference(&dsti->buffer.resource, buf);
3891 dsti->buffer_offset = src->buffer_offset;
3892 dsti->stride = src->stride;
3893 r600_context_add_resource_size(ctx, buf);
3894 if (buf)
3895 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3896 }
3897 } else {
3898 for (i = 0; i < count; i++) {
3899 pipe_resource_reference(&dst[i].buffer.resource, NULL);
3900 }
3901 }
3902 sctx->vertex_buffers_dirty = true;
3903 }
3904
3905 /*
3906 * Misc
3907 */
3908
3909 static void si_set_tess_state(struct pipe_context *ctx,
3910 const float default_outer_level[4],
3911 const float default_inner_level[2])
3912 {
3913 struct si_context *sctx = (struct si_context *)ctx;
3914 struct pipe_constant_buffer cb;
3915 float array[8];
3916
3917 memcpy(array, default_outer_level, sizeof(float) * 4);
3918 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3919
3920 cb.buffer = NULL;
3921 cb.user_buffer = NULL;
3922 cb.buffer_size = sizeof(array);
3923
3924 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3925 (void*)array, sizeof(array),
3926 &cb.buffer_offset);
3927
3928 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3929 pipe_resource_reference(&cb.buffer, NULL);
3930 }
3931
3932 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3933 {
3934 struct si_context *sctx = (struct si_context *)ctx;
3935
3936 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3937 SI_CONTEXT_INV_GLOBAL_L2 |
3938 SI_CONTEXT_FLUSH_AND_INV_CB;
3939 sctx->framebuffer.do_update_surf_dirtiness = true;
3940 }
3941
3942 /* This only ensures coherency for shader image/buffer stores. */
3943 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3944 {
3945 struct si_context *sctx = (struct si_context *)ctx;
3946
3947 /* Subsequent commands must wait for all shader invocations to
3948 * complete. */
3949 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3950 SI_CONTEXT_CS_PARTIAL_FLUSH;
3951
3952 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3953 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3954 SI_CONTEXT_INV_VMEM_L1;
3955
3956 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3957 PIPE_BARRIER_SHADER_BUFFER |
3958 PIPE_BARRIER_TEXTURE |
3959 PIPE_BARRIER_IMAGE |
3960 PIPE_BARRIER_STREAMOUT_BUFFER |
3961 PIPE_BARRIER_GLOBAL_BUFFER)) {
3962 /* As far as I can tell, L1 contents are written back to L2
3963 * automatically at end of shader, but the contents of other
3964 * L1 caches might still be stale. */
3965 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3966 }
3967
3968 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3969 /* Indices are read through TC L2 since VI.
3970 * L1 isn't used.
3971 */
3972 if (sctx->screen->b.chip_class <= CIK)
3973 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3974 }
3975
3976 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3977 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3978 SI_CONTEXT_FLUSH_AND_INV_DB;
3979
3980 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3981 PIPE_BARRIER_INDIRECT_BUFFER))
3982 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3983 }
3984
3985 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3986 {
3987 struct pipe_blend_state blend;
3988
3989 memset(&blend, 0, sizeof(blend));
3990 blend.independent_blend_enable = true;
3991 blend.rt[0].colormask = 0xf;
3992 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3993 }
3994
3995 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3996 bool include_draw_vbo)
3997 {
3998 si_need_cs_space((struct si_context*)ctx);
3999 }
4000
4001 static void si_init_config(struct si_context *sctx);
4002
4003 void si_init_state_functions(struct si_context *sctx)
4004 {
4005 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
4006 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
4007 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
4008 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
4009 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
4010
4011 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
4012 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
4013 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
4014 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
4015 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
4016 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
4017 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
4018 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
4019 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
4020 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
4021
4022 sctx->b.b.create_blend_state = si_create_blend_state;
4023 sctx->b.b.bind_blend_state = si_bind_blend_state;
4024 sctx->b.b.delete_blend_state = si_delete_blend_state;
4025 sctx->b.b.set_blend_color = si_set_blend_color;
4026
4027 sctx->b.b.create_rasterizer_state = si_create_rs_state;
4028 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
4029 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
4030
4031 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
4032 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4033 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4034
4035 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4036 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4037 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4038 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4039 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4040
4041 sctx->b.b.set_clip_state = si_set_clip_state;
4042 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
4043
4044 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
4045 sctx->b.b.get_sample_position = cayman_get_sample_position;
4046
4047 sctx->b.b.create_sampler_state = si_create_sampler_state;
4048 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
4049
4050 sctx->b.b.create_sampler_view = si_create_sampler_view;
4051 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
4052
4053 sctx->b.b.set_sample_mask = si_set_sample_mask;
4054
4055 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
4056 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
4057 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
4058 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
4059
4060 sctx->b.b.texture_barrier = si_texture_barrier;
4061 sctx->b.b.memory_barrier = si_memory_barrier;
4062 sctx->b.b.set_min_samples = si_set_min_samples;
4063 sctx->b.b.set_tess_state = si_set_tess_state;
4064
4065 sctx->b.b.set_active_query_state = si_set_active_query_state;
4066 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
4067 sctx->b.save_qbo_state = si_save_qbo_state;
4068 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
4069
4070 sctx->b.b.draw_vbo = si_draw_vbo;
4071
4072 si_init_config(sctx);
4073 }
4074
4075 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
4076 {
4077 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
4078 }
4079
4080 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
4081 struct r600_texture *rtex,
4082 struct radeon_bo_metadata *md)
4083 {
4084 struct si_screen *sscreen = (struct si_screen*)rscreen;
4085 struct pipe_resource *res = &rtex->resource.b.b;
4086 static const unsigned char swizzle[] = {
4087 PIPE_SWIZZLE_X,
4088 PIPE_SWIZZLE_Y,
4089 PIPE_SWIZZLE_Z,
4090 PIPE_SWIZZLE_W
4091 };
4092 uint32_t desc[8], i;
4093 bool is_array = util_resource_is_array_texture(res);
4094
4095 /* DRM 2.x.x doesn't support this. */
4096 if (rscreen->info.drm_major != 3)
4097 return;
4098
4099 assert(rtex->dcc_separate_buffer == NULL);
4100 assert(rtex->fmask.size == 0);
4101
4102 /* Metadata image format format version 1:
4103 * [0] = 1 (metadata format identifier)
4104 * [1] = (VENDOR_ID << 16) | PCI_ID
4105 * [2:9] = image descriptor for the whole resource
4106 * [2] is always 0, because the base address is cleared
4107 * [9] is the DCC offset bits [39:8] from the beginning of
4108 * the buffer
4109 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4110 */
4111
4112 md->metadata[0] = 1; /* metadata image format version 1 */
4113
4114 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4115 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
4116
4117 si_make_texture_descriptor(sscreen, rtex, true,
4118 res->target, res->format,
4119 swizzle, 0, res->last_level, 0,
4120 is_array ? res->array_size - 1 : 0,
4121 res->width0, res->height0, res->depth0,
4122 desc, NULL);
4123
4124 si_set_mutable_tex_desc_fields(sscreen, rtex, &rtex->surface.u.legacy.level[0],
4125 0, 0, rtex->surface.blk_w, false, desc);
4126
4127 /* Clear the base address and set the relative DCC offset. */
4128 desc[0] = 0;
4129 desc[1] &= C_008F14_BASE_ADDRESS_HI;
4130 desc[7] = rtex->dcc_offset >> 8;
4131
4132 /* Dwords [2:9] contain the image descriptor. */
4133 memcpy(&md->metadata[2], desc, sizeof(desc));
4134 md->size_metadata = 10 * 4;
4135
4136 /* Dwords [10:..] contain the mipmap level offsets. */
4137 if (rscreen->chip_class <= VI) {
4138 for (i = 0; i <= res->last_level; i++)
4139 md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
4140
4141 md->size_metadata += (1 + res->last_level) * 4;
4142 }
4143 }
4144
4145 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
4146 struct r600_texture *rtex,
4147 struct radeon_bo_metadata *md)
4148 {
4149 uint32_t *desc = &md->metadata[2];
4150
4151 if (rscreen->chip_class < VI)
4152 return;
4153
4154 /* Return if DCC is enabled. The texture should be set up with it
4155 * already.
4156 */
4157 if (md->size_metadata >= 11 * 4 &&
4158 md->metadata[0] != 0 &&
4159 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
4160 G_008F28_COMPRESSION_EN(desc[6])) {
4161 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
4162 return;
4163 }
4164
4165 /* Disable DCC. These are always set by texture_from_handle and must
4166 * be cleared here.
4167 */
4168 rtex->dcc_offset = 0;
4169 }
4170
4171 void si_init_screen_state_functions(struct si_screen *sscreen)
4172 {
4173 sscreen->b.b.is_format_supported = si_is_format_supported;
4174 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
4175 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
4176 }
4177
4178 static void
4179 si_write_harvested_raster_configs(struct si_context *sctx,
4180 struct si_pm4_state *pm4,
4181 unsigned raster_config,
4182 unsigned raster_config_1)
4183 {
4184 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
4185 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
4186 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4187 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4188 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
4189 unsigned rb_per_se = num_rb / num_se;
4190 unsigned se_mask[4];
4191 unsigned se;
4192
4193 se_mask[0] = ((1 << rb_per_se) - 1);
4194 se_mask[1] = (se_mask[0] << rb_per_se);
4195 se_mask[2] = (se_mask[1] << rb_per_se);
4196 se_mask[3] = (se_mask[2] << rb_per_se);
4197
4198 se_mask[0] &= rb_mask;
4199 se_mask[1] &= rb_mask;
4200 se_mask[2] &= rb_mask;
4201 se_mask[3] &= rb_mask;
4202
4203 assert(num_se == 1 || num_se == 2 || num_se == 4);
4204 assert(sh_per_se == 1 || sh_per_se == 2);
4205 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
4206
4207 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4208 * fields are for, so I'm leaving them as their default
4209 * values. */
4210
4211 for (se = 0; se < num_se; se++) {
4212 unsigned raster_config_se = raster_config;
4213 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
4214 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
4215 int idx = (se / 2) * 2;
4216
4217 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
4218 raster_config_se &= C_028350_SE_MAP;
4219
4220 if (!se_mask[idx]) {
4221 raster_config_se |=
4222 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
4223 } else {
4224 raster_config_se |=
4225 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
4226 }
4227 }
4228
4229 pkr0_mask &= rb_mask;
4230 pkr1_mask &= rb_mask;
4231 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
4232 raster_config_se &= C_028350_PKR_MAP;
4233
4234 if (!pkr0_mask) {
4235 raster_config_se |=
4236 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
4237 } else {
4238 raster_config_se |=
4239 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
4240 }
4241 }
4242
4243 if (rb_per_se >= 2) {
4244 unsigned rb0_mask = 1 << (se * rb_per_se);
4245 unsigned rb1_mask = rb0_mask << 1;
4246
4247 rb0_mask &= rb_mask;
4248 rb1_mask &= rb_mask;
4249 if (!rb0_mask || !rb1_mask) {
4250 raster_config_se &= C_028350_RB_MAP_PKR0;
4251
4252 if (!rb0_mask) {
4253 raster_config_se |=
4254 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
4255 } else {
4256 raster_config_se |=
4257 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
4258 }
4259 }
4260
4261 if (rb_per_se > 2) {
4262 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
4263 rb1_mask = rb0_mask << 1;
4264 rb0_mask &= rb_mask;
4265 rb1_mask &= rb_mask;
4266 if (!rb0_mask || !rb1_mask) {
4267 raster_config_se &= C_028350_RB_MAP_PKR1;
4268
4269 if (!rb0_mask) {
4270 raster_config_se |=
4271 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
4272 } else {
4273 raster_config_se |=
4274 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
4275 }
4276 }
4277 }
4278 }
4279
4280 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4281 if (sctx->b.chip_class < CIK)
4282 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4283 SE_INDEX(se) | SH_BROADCAST_WRITES |
4284 INSTANCE_BROADCAST_WRITES);
4285 else
4286 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4287 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
4288 S_030800_INSTANCE_BROADCAST_WRITES(1));
4289 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
4290 }
4291
4292 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
4293 if (sctx->b.chip_class < CIK)
4294 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
4295 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
4296 INSTANCE_BROADCAST_WRITES);
4297 else {
4298 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
4299 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
4300 S_030800_INSTANCE_BROADCAST_WRITES(1));
4301
4302 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
4303 (!se_mask[2] && !se_mask[3]))) {
4304 raster_config_1 &= C_028354_SE_PAIR_MAP;
4305
4306 if (!se_mask[0] && !se_mask[1]) {
4307 raster_config_1 |=
4308 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
4309 } else {
4310 raster_config_1 |=
4311 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
4312 }
4313 }
4314
4315 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4316 }
4317 }
4318
4319 static void si_init_config(struct si_context *sctx)
4320 {
4321 struct si_screen *sscreen = sctx->screen;
4322 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
4323 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
4324 unsigned raster_config, raster_config_1;
4325 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4326 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4327
4328 if (!pm4)
4329 return;
4330
4331 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4332 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4333 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4334 si_pm4_cmd_end(pm4, false);
4335
4336 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4337 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4338
4339 /* FIXME calculate these values somehow ??? */
4340 if (sctx->b.chip_class <= VI) {
4341 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4342 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4343 }
4344 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4345
4346 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4347 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4348
4349 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4350 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4351 if (sctx->b.chip_class >= GFX9)
4352 si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0);
4353 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4354 if (sctx->b.chip_class < CIK)
4355 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4356 S_008A14_CLIP_VTX_REORDER_ENA(1));
4357
4358 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
4359 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
4360
4361 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
4362
4363 switch (sctx->screen->b.family) {
4364 case CHIP_TAHITI:
4365 case CHIP_PITCAIRN:
4366 raster_config = 0x2a00126a;
4367 raster_config_1 = 0x00000000;
4368 break;
4369 case CHIP_VERDE:
4370 raster_config = 0x0000124a;
4371 raster_config_1 = 0x00000000;
4372 break;
4373 case CHIP_OLAND:
4374 raster_config = 0x00000082;
4375 raster_config_1 = 0x00000000;
4376 break;
4377 case CHIP_HAINAN:
4378 raster_config = 0x00000000;
4379 raster_config_1 = 0x00000000;
4380 break;
4381 case CHIP_BONAIRE:
4382 raster_config = 0x16000012;
4383 raster_config_1 = 0x00000000;
4384 break;
4385 case CHIP_HAWAII:
4386 raster_config = 0x3a00161a;
4387 raster_config_1 = 0x0000002e;
4388 break;
4389 case CHIP_FIJI:
4390 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
4391 /* old kernels with old tiling config */
4392 raster_config = 0x16000012;
4393 raster_config_1 = 0x0000002a;
4394 } else {
4395 raster_config = 0x3a00161a;
4396 raster_config_1 = 0x0000002e;
4397 }
4398 break;
4399 case CHIP_POLARIS10:
4400 raster_config = 0x16000012;
4401 raster_config_1 = 0x0000002a;
4402 break;
4403 case CHIP_POLARIS11:
4404 case CHIP_POLARIS12:
4405 raster_config = 0x16000012;
4406 raster_config_1 = 0x00000000;
4407 break;
4408 case CHIP_TONGA:
4409 raster_config = 0x16000012;
4410 raster_config_1 = 0x0000002a;
4411 break;
4412 case CHIP_ICELAND:
4413 if (num_rb == 1)
4414 raster_config = 0x00000000;
4415 else
4416 raster_config = 0x00000002;
4417 raster_config_1 = 0x00000000;
4418 break;
4419 case CHIP_CARRIZO:
4420 raster_config = 0x00000002;
4421 raster_config_1 = 0x00000000;
4422 break;
4423 case CHIP_KAVERI:
4424 /* KV should be 0x00000002, but that causes problems with radeon */
4425 raster_config = 0x00000000; /* 0x00000002 */
4426 raster_config_1 = 0x00000000;
4427 break;
4428 case CHIP_KABINI:
4429 case CHIP_MULLINS:
4430 case CHIP_STONEY:
4431 raster_config = 0x00000000;
4432 raster_config_1 = 0x00000000;
4433 break;
4434 default:
4435 if (sctx->b.chip_class <= VI) {
4436 fprintf(stderr,
4437 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4438 raster_config = 0x00000000;
4439 raster_config_1 = 0x00000000;
4440 }
4441 break;
4442 }
4443
4444 if (sctx->b.chip_class <= VI) {
4445 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4446 /* Always use the default config when all backends are enabled
4447 * (or when we failed to determine the enabled backends).
4448 */
4449 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4450 raster_config);
4451 if (sctx->b.chip_class >= CIK)
4452 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4453 raster_config_1);
4454 } else {
4455 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4456 }
4457 }
4458
4459 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4460 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4461 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4462 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4463 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4464 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4465 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4466
4467 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4468 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4469 S_028230_ER_TRI(0xA) |
4470 S_028230_ER_POINT(0xA) |
4471 S_028230_ER_RECT(0xA) |
4472 /* Required by DX10_DIAMOND_TEST_ENA: */
4473 S_028230_ER_LINE_LR(0x1A) |
4474 S_028230_ER_LINE_RL(0x26) |
4475 S_028230_ER_LINE_TB(0xA) |
4476 S_028230_ER_LINE_BT(0xA));
4477 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4478 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4479 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4480 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4481 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4482 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4483 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4484
4485 if (sctx->b.chip_class >= GFX9) {
4486 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4487 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4488 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4489 } else {
4490 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4491 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4492 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4493 }
4494
4495 if (sctx->b.chip_class >= CIK) {
4496 if (sctx->b.chip_class >= GFX9) {
4497 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
4498 } else {
4499 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4500 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4501 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4502
4503 /* If this is 0, Bonaire can hang even if GS isn't being used.
4504 * Other chips are unaffected. These are suboptimal values,
4505 * but we don't use on-chip GS.
4506 */
4507 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4508 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4509 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4510 }
4511 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4512
4513 if (sscreen->b.info.num_good_compute_units /
4514 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4515 /* Too few available compute units per SH. Disallowing
4516 * VS to run on CU0 could hurt us more than late VS
4517 * allocation would help.
4518 *
4519 * LATE_ALLOC_VS = 2 is the highest safe number.
4520 */
4521 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4522 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4523 } else {
4524 /* Set LATE_ALLOC_VS == 31. It should be less than
4525 * the number of scratch waves. Limitations:
4526 * - VS can't execute on CU0.
4527 * - If HS writes outputs to LDS, LS can't execute on CU0.
4528 */
4529 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4530 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4531 }
4532
4533 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4534 }
4535
4536 if (sctx->b.chip_class >= VI) {
4537 unsigned vgt_tess_distribution;
4538
4539 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4540 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4541 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4542 if (sctx->b.family < CHIP_POLARIS10)
4543 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4544 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4545
4546 vgt_tess_distribution =
4547 S_028B50_ACCUM_ISOLINE(32) |
4548 S_028B50_ACCUM_TRI(11) |
4549 S_028B50_ACCUM_QUAD(11) |
4550 S_028B50_DONUT_SPLIT(16);
4551
4552 /* Testing with Unigine Heaven extreme tesselation yielded best results
4553 * with TRAP_SPLIT = 3.
4554 */
4555 if (sctx->b.family == CHIP_FIJI ||
4556 sctx->b.family >= CHIP_POLARIS10)
4557 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4558
4559 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4560 } else {
4561 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4562 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4563 }
4564
4565 if (sctx->screen->b.has_rbplus)
4566 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4567
4568 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4569 if (sctx->b.chip_class >= CIK)
4570 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4571 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4572 RADEON_PRIO_BORDER_COLORS);
4573
4574 if (sctx->b.chip_class >= GFX9) {
4575 unsigned num_se = sscreen->b.info.max_se;
4576 unsigned pc_lines = 0;
4577
4578 switch (sctx->b.family) {
4579 case CHIP_VEGA10:
4580 pc_lines = 4096;
4581 break;
4582 case CHIP_RAVEN:
4583 pc_lines = 1024;
4584 break;
4585 default:
4586 assert(0);
4587 }
4588
4589 si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
4590 S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
4591 si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
4592 /* TODO: We can use this to disable RBs for rendering to GART: */
4593 si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
4594 si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
4595 /* TODO: Enable the binner: */
4596 si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
4597 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
4598 S_028C44_DISABLE_START_OF_PRIM(1));
4599 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
4600 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
4601 S_028C48_MAX_PRIM_PER_BATCH(1023));
4602 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
4603 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
4604 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
4605 }
4606
4607 si_pm4_upload_indirect_buffer(sctx, pm4);
4608 sctx->init_config = pm4;
4609 }