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radeonsi: remove SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "sid.h"
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
31
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
37
38 /* Initialize an external atom (owned by ../radeon). */
39 static void
40 si_init_external_atom(struct si_context *sctx, struct r600_atom *atom,
41 struct r600_atom **list_elem)
42 {
43 atom->id = list_elem - sctx->atoms.array;
44 *list_elem = atom;
45 }
46
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context *sctx, struct r600_atom *atom,
49 struct r600_atom **list_elem,
50 void (*emit_func)(struct si_context *ctx, struct r600_atom *state))
51 {
52 atom->emit = (void*)emit_func;
53 atom->id = list_elem - sctx->atoms.array;
54 *list_elem = atom;
55 }
56
57 static unsigned si_map_swizzle(unsigned swizzle)
58 {
59 switch (swizzle) {
60 case PIPE_SWIZZLE_Y:
61 return V_008F0C_SQ_SEL_Y;
62 case PIPE_SWIZZLE_Z:
63 return V_008F0C_SQ_SEL_Z;
64 case PIPE_SWIZZLE_W:
65 return V_008F0C_SQ_SEL_W;
66 case PIPE_SWIZZLE_0:
67 return V_008F0C_SQ_SEL_0;
68 case PIPE_SWIZZLE_1:
69 return V_008F0C_SQ_SEL_1;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X;
72 }
73 }
74
75 static uint32_t S_FIXED(float value, uint32_t frac_bits)
76 {
77 return value * (1 << frac_bits);
78 }
79
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x)
82 {
83 return x <= 0 ? 0 :
84 x >= 4096 ? 0xffff : x * 16;
85 }
86
87 /*
88 * Inferred framebuffer and blender state.
89 *
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
92 */
93 static void si_emit_cb_render_state(struct si_context *sctx, struct r600_atom *atom)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_state_blend *blend = sctx->queued.named.blend;
97 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
98 * but you never know. */
99 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
100 unsigned i;
101
102 if (blend)
103 cb_target_mask &= blend->cb_target_mask;
104
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
108 *
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
110 */
111 if (blend && blend->dual_src_blend &&
112 sctx->ps_shader.cso &&
113 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
114 cb_target_mask = 0;
115
116 radeon_set_context_reg(cs, R_028238_CB_TARGET_MASK, cb_target_mask);
117
118 /* STONEY-specific register settings. */
119 if (sctx->b.family == CHIP_STONEY) {
120 unsigned spi_shader_col_format =
121 sctx->ps_shader.cso ?
122 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
123 unsigned sx_ps_downconvert = 0;
124 unsigned sx_blend_opt_epsilon = 0;
125 unsigned sx_blend_opt_control = 0;
126
127 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
128 struct r600_surface *surf =
129 (struct r600_surface*)sctx->framebuffer.state.cbufs[i];
130 unsigned format, swap, spi_format, colormask;
131 bool has_alpha, has_rgb;
132
133 if (!surf)
134 continue;
135
136 format = G_028C70_FORMAT(surf->cb_color_info);
137 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
138 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
139 colormask = (cb_target_mask >> (i * 4)) & 0xf;
140
141 /* Set if RGB and A are present. */
142 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
143
144 if (format == V_028C70_COLOR_8 ||
145 format == V_028C70_COLOR_16 ||
146 format == V_028C70_COLOR_32)
147 has_rgb = !has_alpha;
148 else
149 has_rgb = true;
150
151 /* Check the colormask and export format. */
152 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
153 has_rgb = false;
154 if (!(colormask & PIPE_MASK_A))
155 has_alpha = false;
156
157 if (spi_format == V_028714_SPI_SHADER_ZERO) {
158 has_rgb = false;
159 has_alpha = false;
160 }
161
162 /* Disable value checking for disabled channels. */
163 if (!has_rgb)
164 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
165 if (!has_alpha)
166 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
167
168 /* Enable down-conversion for 32bpp and smaller formats. */
169 switch (format) {
170 case V_028C70_COLOR_8:
171 case V_028C70_COLOR_8_8:
172 case V_028C70_COLOR_8_8_8_8:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
175 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
176 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
177 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
178 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
179 }
180 break;
181
182 case V_028C70_COLOR_5_6_5:
183 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
184 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
185 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
186 }
187 break;
188
189 case V_028C70_COLOR_1_5_5_5:
190 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
191 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
192 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
193 }
194 break;
195
196 case V_028C70_COLOR_4_4_4_4:
197 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
198 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
199 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
200 }
201 break;
202
203 case V_028C70_COLOR_32:
204 if (swap == V_0280A0_SWAP_STD &&
205 spi_format == V_028714_SPI_SHADER_32_R)
206 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
207 else if (swap == V_0280A0_SWAP_ALT_REV &&
208 spi_format == V_028714_SPI_SHADER_32_AR)
209 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
210 break;
211
212 case V_028C70_COLOR_16:
213 case V_028C70_COLOR_16_16:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
216 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
217 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
218 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
219 if (swap == V_0280A0_SWAP_STD ||
220 swap == V_0280A0_SWAP_STD_REV)
221 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
222 else
223 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
224 }
225 break;
226
227 case V_028C70_COLOR_10_11_11:
228 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
229 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
230 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
231 }
232 break;
233
234 case V_028C70_COLOR_2_10_10_10:
235 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
236 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
237 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
238 }
239 break;
240 }
241 }
242
243 if (sctx->screen->b.debug_flags & DBG_NO_RB_PLUS) {
244 sx_ps_downconvert = 0;
245 sx_blend_opt_epsilon = 0;
246 sx_blend_opt_control = 0;
247 }
248
249 radeon_set_context_reg_seq(cs, R_028754_SX_PS_DOWNCONVERT, 3);
250 radeon_emit(cs, sx_ps_downconvert); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs, sx_blend_opt_epsilon); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs, sx_blend_opt_control); /* R_02875C_SX_BLEND_OPT_CONTROL */
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 R600_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 /**
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
376 */
377 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
378 unsigned *dst_factor, unsigned expected_dst,
379 unsigned replacement_src)
380 {
381 if (*src_factor == expected_dst &&
382 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
383 *src_factor = PIPE_BLENDFACTOR_ZERO;
384 *dst_factor = replacement_src;
385
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func == PIPE_BLEND_SUBTRACT)
388 *func = PIPE_BLEND_REVERSE_SUBTRACT;
389 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
390 *func = PIPE_BLEND_SUBTRACT;
391 }
392 }
393
394 static bool si_blend_factor_uses_dst(unsigned factor)
395 {
396 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
397 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
398 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
399 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
400 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
401 }
402
403 static void *si_create_blend_state_mode(struct pipe_context *ctx,
404 const struct pipe_blend_state *state,
405 unsigned mode)
406 {
407 struct si_context *sctx = (struct si_context*)ctx;
408 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
409 struct si_pm4_state *pm4 = &blend->pm4;
410 uint32_t sx_mrt_blend_opt[8] = {0};
411 uint32_t color_control = 0;
412
413 if (!blend)
414 return NULL;
415
416 blend->alpha_to_coverage = state->alpha_to_coverage;
417 blend->alpha_to_one = state->alpha_to_one;
418 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
419
420 if (state->logicop_enable) {
421 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
422 } else {
423 color_control |= S_028808_ROP3(0xcc);
424 }
425
426 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
432
433 if (state->alpha_to_coverage)
434 blend->need_src_alpha_4bit |= 0xf;
435
436 blend->cb_target_mask = 0;
437 for (int i = 0; i < 8; i++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j = state->independent_blend_enable ? i : 0;
440
441 unsigned eqRGB = state->rt[j].rgb_func;
442 unsigned srcRGB = state->rt[j].rgb_src_factor;
443 unsigned dstRGB = state->rt[j].rgb_dst_factor;
444 unsigned eqA = state->rt[j].alpha_func;
445 unsigned srcA = state->rt[j].alpha_src_factor;
446 unsigned dstA = state->rt[j].alpha_dst_factor;
447
448 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
449 unsigned blend_cntl = 0;
450
451 sx_mrt_blend_opt[i] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
454
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i >= 1 && blend->dual_src_blend) {
457 /* Vulkan does this for dual source blending. */
458 if (i == 1)
459 blend_cntl |= S_028780_ENABLE(1);
460
461 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
462 continue;
463 }
464
465 /* Only addition and subtraction equations are supported with
466 * dual source blending.
467 */
468 if (blend->dual_src_blend &&
469 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
470 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
471 assert(!"Unsupported equation for dual source blending");
472 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
473 continue;
474 }
475
476 /* cb_render_state will disable unused ones */
477 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
478
479 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
480 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
481 continue;
482 }
483
484 /* Blending optimizations for Stoney.
485 * These transformations don't change the behavior.
486 *
487 * First, get rid of DST in the blend factors:
488 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
489 */
490 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
491 PIPE_BLENDFACTOR_DST_COLOR,
492 PIPE_BLENDFACTOR_SRC_COLOR);
493 si_blend_remove_dst(&eqA, &srcA, &dstA,
494 PIPE_BLENDFACTOR_DST_COLOR,
495 PIPE_BLENDFACTOR_SRC_COLOR);
496 si_blend_remove_dst(&eqA, &srcA, &dstA,
497 PIPE_BLENDFACTOR_DST_ALPHA,
498 PIPE_BLENDFACTOR_SRC_ALPHA);
499
500 /* Look up the ideal settings from tables. */
501 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
502 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
503 srcA_opt = si_translate_blend_opt_factor(srcA, true);
504 dstA_opt = si_translate_blend_opt_factor(dstA, true);
505
506 /* Handle interdependencies. */
507 if (si_blend_factor_uses_dst(srcRGB))
508 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
509 if (si_blend_factor_uses_dst(srcA))
510 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
511
512 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
513 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
514 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
515 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
516 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
517
518 /* Set the final value. */
519 sx_mrt_blend_opt[i] =
520 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
521 S_028760_COLOR_DST_OPT(dstRGB_opt) |
522 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
523 S_028760_ALPHA_SRC_OPT(srcA_opt) |
524 S_028760_ALPHA_DST_OPT(dstA_opt) |
525 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
526
527 /* Set blend state. */
528 blend_cntl |= S_028780_ENABLE(1);
529 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
530 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
531 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
532
533 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
534 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
535 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
536 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
537 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
538 }
539 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
540
541 blend->blend_enable_4bit |= 0xfu << (i * 4);
542
543 /* This is only important for formats without alpha. */
544 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
545 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
546 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
547 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
548 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
549 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
550 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
551 }
552
553 if (blend->cb_target_mask) {
554 color_control |= S_028808_MODE(mode);
555 } else {
556 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
557 }
558
559 if (sctx->b.family == CHIP_STONEY) {
560 /* Disable RB+ blend optimizations for dual source blending.
561 * Vulkan does this.
562 */
563 if (blend->dual_src_blend) {
564 for (int i = 0; i < 8; i++) {
565 sx_mrt_blend_opt[i] =
566 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
567 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
568 }
569 }
570
571 for (int i = 0; i < 8; i++)
572 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
573 sx_mrt_blend_opt[i]);
574
575 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
576 if (blend->dual_src_blend || state->logicop_enable ||
577 mode == V_028808_CB_RESOLVE)
578 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
579 }
580
581 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
582 return blend;
583 }
584
585 static void *si_create_blend_state(struct pipe_context *ctx,
586 const struct pipe_blend_state *state)
587 {
588 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
589 }
590
591 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
592 {
593 struct si_context *sctx = (struct si_context *)ctx;
594 si_pm4_bind_state(sctx, blend, (struct si_state_blend *)state);
595 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
596 sctx->do_update_shaders = true;
597 }
598
599 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
600 {
601 struct si_context *sctx = (struct si_context *)ctx;
602 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
603 }
604
605 static void si_set_blend_color(struct pipe_context *ctx,
606 const struct pipe_blend_color *state)
607 {
608 struct si_context *sctx = (struct si_context *)ctx;
609
610 if (memcmp(&sctx->blend_color.state, state, sizeof(*state)) == 0)
611 return;
612
613 sctx->blend_color.state = *state;
614 si_mark_atom_dirty(sctx, &sctx->blend_color.atom);
615 }
616
617 static void si_emit_blend_color(struct si_context *sctx, struct r600_atom *atom)
618 {
619 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
620
621 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
622 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
623 }
624
625 /*
626 * Clipping
627 */
628
629 static void si_set_clip_state(struct pipe_context *ctx,
630 const struct pipe_clip_state *state)
631 {
632 struct si_context *sctx = (struct si_context *)ctx;
633 struct pipe_constant_buffer cb;
634
635 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
636 return;
637
638 sctx->clip_state.state = *state;
639 si_mark_atom_dirty(sctx, &sctx->clip_state.atom);
640
641 cb.buffer = NULL;
642 cb.user_buffer = state->ucp;
643 cb.buffer_offset = 0;
644 cb.buffer_size = 4*4*8;
645 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
646 pipe_resource_reference(&cb.buffer, NULL);
647 }
648
649 static void si_emit_clip_state(struct si_context *sctx, struct r600_atom *atom)
650 {
651 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
652
653 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
654 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
655 }
656
657 #define SIX_BITS 0x3F
658
659 static void si_emit_clip_regs(struct si_context *sctx, struct r600_atom *atom)
660 {
661 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
662 struct si_shader *vs = si_get_vs_state(sctx);
663 struct tgsi_shader_info *info = si_get_vs_info(sctx);
664 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
665 unsigned window_space =
666 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
667 unsigned clipdist_mask =
668 info->writes_clipvertex ? SIX_BITS : info->clipdist_writemask;
669 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
670 unsigned culldist_mask = info->culldist_writemask << info->num_written_clipdistance;
671 unsigned total_mask;
672 bool misc_vec_ena;
673
674 if (vs->key.opt.hw_vs.clip_disable) {
675 assert(!info->culldist_writemask);
676 clipdist_mask = 0;
677 culldist_mask = 0;
678 }
679 total_mask = clipdist_mask | culldist_mask;
680
681 /* Clip distances on points have no effect, so need to be implemented
682 * as cull distances. This applies for the clipvertex case as well.
683 *
684 * Setting this for primitives other than points should have no adverse
685 * effects.
686 */
687 clipdist_mask &= rs->clip_plane_enable;
688 culldist_mask |= clipdist_mask;
689
690 misc_vec_ena = info->writes_psize || info->writes_edgeflag ||
691 info->writes_layer || info->writes_viewport_index;
692
693 radeon_set_context_reg(cs, R_02881C_PA_CL_VS_OUT_CNTL,
694 S_02881C_USE_VTX_POINT_SIZE(info->writes_psize) |
695 S_02881C_USE_VTX_EDGE_FLAG(info->writes_edgeflag) |
696 S_02881C_USE_VTX_RENDER_TARGET_INDX(info->writes_layer) |
697 S_02881C_USE_VTX_VIEWPORT_INDX(info->writes_viewport_index) |
698 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
699 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
700 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
701 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
702 clipdist_mask | (culldist_mask << 8));
703 radeon_set_context_reg(cs, R_028810_PA_CL_CLIP_CNTL,
704 rs->pa_cl_clip_cntl |
705 ucp_mask |
706 S_028810_CLIP_DISABLE(window_space));
707
708 /* reuse needs to be set off if we write oViewport */
709 radeon_set_context_reg(cs, R_028AB4_VGT_REUSE_OFF,
710 S_028AB4_REUSE_OFF(info->writes_viewport_index));
711 }
712
713 /*
714 * inferred state between framebuffer and rasterizer
715 */
716 static void si_update_poly_offset_state(struct si_context *sctx)
717 {
718 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
719
720 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
721 si_pm4_bind_state(sctx, poly_offset, NULL);
722 return;
723 }
724
725 /* Use the user format, not db_render_format, so that the polygon
726 * offset behaves as expected by applications.
727 */
728 switch (sctx->framebuffer.state.zsbuf->texture->format) {
729 case PIPE_FORMAT_Z16_UNORM:
730 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
731 break;
732 default: /* 24-bit */
733 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
734 break;
735 case PIPE_FORMAT_Z32_FLOAT:
736 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
737 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
738 break;
739 }
740 }
741
742 /*
743 * Rasterizer
744 */
745
746 static uint32_t si_translate_fill(uint32_t func)
747 {
748 switch(func) {
749 case PIPE_POLYGON_MODE_FILL:
750 return V_028814_X_DRAW_TRIANGLES;
751 case PIPE_POLYGON_MODE_LINE:
752 return V_028814_X_DRAW_LINES;
753 case PIPE_POLYGON_MODE_POINT:
754 return V_028814_X_DRAW_POINTS;
755 default:
756 assert(0);
757 return V_028814_X_DRAW_POINTS;
758 }
759 }
760
761 static void *si_create_rs_state(struct pipe_context *ctx,
762 const struct pipe_rasterizer_state *state)
763 {
764 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
765 struct si_pm4_state *pm4 = &rs->pm4;
766 unsigned tmp, i;
767 float psize_min, psize_max;
768
769 if (!rs) {
770 return NULL;
771 }
772
773 rs->scissor_enable = state->scissor;
774 rs->clip_halfz = state->clip_halfz;
775 rs->two_side = state->light_twoside;
776 rs->multisample_enable = state->multisample;
777 rs->force_persample_interp = state->force_persample_interp;
778 rs->clip_plane_enable = state->clip_plane_enable;
779 rs->line_stipple_enable = state->line_stipple_enable;
780 rs->poly_stipple_enable = state->poly_stipple_enable;
781 rs->line_smooth = state->line_smooth;
782 rs->poly_smooth = state->poly_smooth;
783 rs->uses_poly_offset = state->offset_point || state->offset_line ||
784 state->offset_tri;
785 rs->clamp_fragment_color = state->clamp_fragment_color;
786 rs->flatshade = state->flatshade;
787 rs->sprite_coord_enable = state->sprite_coord_enable;
788 rs->rasterizer_discard = state->rasterizer_discard;
789 rs->pa_sc_line_stipple = state->line_stipple_enable ?
790 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
791 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
792 rs->pa_cl_clip_cntl =
793 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
794 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
795 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
796 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
797 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
798
799 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
800 S_0286D4_FLAT_SHADE_ENA(1) |
801 S_0286D4_PNT_SPRITE_ENA(1) |
802 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
803 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
804 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
805 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
806 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
807
808 /* point size 12.4 fixed point */
809 tmp = (unsigned)(state->point_size * 8.0);
810 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
811
812 if (state->point_size_per_vertex) {
813 psize_min = util_get_min_point_size(state);
814 psize_max = 8192;
815 } else {
816 /* Force the point size to be as if the vertex output was disabled. */
817 psize_min = state->point_size;
818 psize_max = state->point_size;
819 }
820 /* Divide by two, because 0.5 = 1 pixel. */
821 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
822 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
823 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
824
825 tmp = (unsigned)state->line_width * 8;
826 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
827 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
828 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
829 S_028A48_MSAA_ENABLE(state->multisample ||
830 state->poly_smooth ||
831 state->line_smooth) |
832 S_028A48_VPORT_SCISSOR_ENABLE(1));
833
834 si_pm4_set_reg(pm4, R_028BE4_PA_SU_VTX_CNTL,
835 S_028BE4_PIX_CENTER(state->half_pixel_center) |
836 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
837
838 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
839 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
840 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
841 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
842 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
843 S_028814_FACE(!state->front_ccw) |
844 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
845 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
846 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
847 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
848 state->fill_back != PIPE_POLYGON_MODE_FILL) |
849 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
850 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
851 si_pm4_set_reg(pm4, R_00B130_SPI_SHADER_USER_DATA_VS_0 +
852 SI_SGPR_VS_STATE_BITS * 4, state->clamp_vertex_color);
853
854 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
855 for (i = 0; i < 3; i++) {
856 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
857 float offset_units = state->offset_units;
858 float offset_scale = state->offset_scale * 16.0f;
859 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
860
861 if (!state->offset_units_unscaled) {
862 switch (i) {
863 case 0: /* 16-bit zbuffer */
864 offset_units *= 4.0f;
865 pa_su_poly_offset_db_fmt_cntl =
866 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
867 break;
868 case 1: /* 24-bit zbuffer */
869 offset_units *= 2.0f;
870 pa_su_poly_offset_db_fmt_cntl =
871 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
872 break;
873 case 2: /* 32-bit zbuffer */
874 offset_units *= 1.0f;
875 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
876 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
877 break;
878 }
879 }
880
881 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
882 fui(offset_scale));
883 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
884 fui(offset_units));
885 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
886 fui(offset_scale));
887 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
888 fui(offset_units));
889 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
890 pa_su_poly_offset_db_fmt_cntl);
891 }
892
893 return rs;
894 }
895
896 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
897 {
898 struct si_context *sctx = (struct si_context *)ctx;
899 struct si_state_rasterizer *old_rs =
900 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
901 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
902
903 if (!state)
904 return;
905
906 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
907 si_mark_atom_dirty(sctx, &sctx->db_render_state);
908
909 /* Update the small primitive filter workaround if necessary. */
910 if (sctx->b.family >= CHIP_POLARIS10 &&
911 sctx->framebuffer.nr_samples > 1)
912 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
913 }
914
915 r600_viewport_set_rast_deps(&sctx->b, rs->scissor_enable, rs->clip_halfz);
916
917 si_pm4_bind_state(sctx, rasterizer, rs);
918 si_update_poly_offset_state(sctx);
919
920 si_mark_atom_dirty(sctx, &sctx->clip_regs);
921 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
922 rs->line_stipple_enable;
923 sctx->do_update_shaders = true;
924 }
925
926 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
927 {
928 struct si_context *sctx = (struct si_context *)ctx;
929
930 if (sctx->queued.named.rasterizer == state)
931 si_pm4_bind_state(sctx, poly_offset, NULL);
932 si_pm4_delete_state(sctx, rasterizer, (struct si_state_rasterizer *)state);
933 }
934
935 /*
936 * infeered state between dsa and stencil ref
937 */
938 static void si_emit_stencil_ref(struct si_context *sctx, struct r600_atom *atom)
939 {
940 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
941 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
942 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
943
944 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
945 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
946 S_028430_STENCILMASK(dsa->valuemask[0]) |
947 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
948 S_028430_STENCILOPVAL(1));
949 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
950 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
951 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
952 S_028434_STENCILOPVAL_BF(1));
953 }
954
955 static void si_set_stencil_ref(struct pipe_context *ctx,
956 const struct pipe_stencil_ref *state)
957 {
958 struct si_context *sctx = (struct si_context *)ctx;
959
960 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
961 return;
962
963 sctx->stencil_ref.state = *state;
964 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
965 }
966
967
968 /*
969 * DSA
970 */
971
972 static uint32_t si_translate_stencil_op(int s_op)
973 {
974 switch (s_op) {
975 case PIPE_STENCIL_OP_KEEP:
976 return V_02842C_STENCIL_KEEP;
977 case PIPE_STENCIL_OP_ZERO:
978 return V_02842C_STENCIL_ZERO;
979 case PIPE_STENCIL_OP_REPLACE:
980 return V_02842C_STENCIL_REPLACE_TEST;
981 case PIPE_STENCIL_OP_INCR:
982 return V_02842C_STENCIL_ADD_CLAMP;
983 case PIPE_STENCIL_OP_DECR:
984 return V_02842C_STENCIL_SUB_CLAMP;
985 case PIPE_STENCIL_OP_INCR_WRAP:
986 return V_02842C_STENCIL_ADD_WRAP;
987 case PIPE_STENCIL_OP_DECR_WRAP:
988 return V_02842C_STENCIL_SUB_WRAP;
989 case PIPE_STENCIL_OP_INVERT:
990 return V_02842C_STENCIL_INVERT;
991 default:
992 R600_ERR("Unknown stencil op %d", s_op);
993 assert(0);
994 break;
995 }
996 return 0;
997 }
998
999 static void *si_create_dsa_state(struct pipe_context *ctx,
1000 const struct pipe_depth_stencil_alpha_state *state)
1001 {
1002 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1003 struct si_pm4_state *pm4 = &dsa->pm4;
1004 unsigned db_depth_control;
1005 uint32_t db_stencil_control = 0;
1006
1007 if (!dsa) {
1008 return NULL;
1009 }
1010
1011 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1012 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1013 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1014 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1015
1016 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1017 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1018 S_028800_ZFUNC(state->depth.func) |
1019 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1020
1021 /* stencil */
1022 if (state->stencil[0].enabled) {
1023 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1024 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1025 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1026 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1027 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1028
1029 if (state->stencil[1].enabled) {
1030 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1031 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1032 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1033 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1034 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1035 }
1036 }
1037
1038 /* alpha */
1039 if (state->alpha.enabled) {
1040 dsa->alpha_func = state->alpha.func;
1041
1042 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1043 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1044 } else {
1045 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1046 }
1047
1048 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1049 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1050 if (state->depth.bounds_test) {
1051 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1052 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1053 }
1054
1055 return dsa;
1056 }
1057
1058 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1059 {
1060 struct si_context *sctx = (struct si_context *)ctx;
1061 struct si_state_dsa *dsa = state;
1062
1063 if (!state)
1064 return;
1065
1066 si_pm4_bind_state(sctx, dsa, dsa);
1067
1068 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1069 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1070 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1071 si_mark_atom_dirty(sctx, &sctx->stencil_ref.atom);
1072 }
1073 sctx->do_update_shaders = true;
1074 }
1075
1076 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1077 {
1078 struct si_context *sctx = (struct si_context *)ctx;
1079 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1080 }
1081
1082 static void *si_create_db_flush_dsa(struct si_context *sctx)
1083 {
1084 struct pipe_depth_stencil_alpha_state dsa = {};
1085
1086 return sctx->b.b.create_depth_stencil_alpha_state(&sctx->b.b, &dsa);
1087 }
1088
1089 /* DB RENDER STATE */
1090
1091 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1092 {
1093 struct si_context *sctx = (struct si_context*)ctx;
1094
1095 /* Pipeline stat & streamout queries. */
1096 if (enable) {
1097 sctx->b.flags &= ~R600_CONTEXT_STOP_PIPELINE_STATS;
1098 sctx->b.flags |= R600_CONTEXT_START_PIPELINE_STATS;
1099 } else {
1100 sctx->b.flags &= ~R600_CONTEXT_START_PIPELINE_STATS;
1101 sctx->b.flags |= R600_CONTEXT_STOP_PIPELINE_STATS;
1102 }
1103
1104 /* Occlusion queries. */
1105 if (sctx->occlusion_queries_disabled != !enable) {
1106 sctx->occlusion_queries_disabled = !enable;
1107 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1108 }
1109 }
1110
1111 static void si_set_occlusion_query_state(struct pipe_context *ctx, bool enable)
1112 {
1113 struct si_context *sctx = (struct si_context*)ctx;
1114
1115 si_mark_atom_dirty(sctx, &sctx->db_render_state);
1116 }
1117
1118 static void si_save_qbo_state(struct pipe_context *ctx, struct r600_qbo_state *st)
1119 {
1120 struct si_context *sctx = (struct si_context*)ctx;
1121
1122 st->saved_compute = sctx->cs_shader_state.program;
1123
1124 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1125 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1126 }
1127
1128 static void si_emit_db_render_state(struct si_context *sctx, struct r600_atom *state)
1129 {
1130 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1131 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1132 unsigned db_shader_control;
1133
1134 radeon_set_context_reg_seq(cs, R_028000_DB_RENDER_CONTROL, 2);
1135
1136 /* DB_RENDER_CONTROL */
1137 if (sctx->dbcb_depth_copy_enabled ||
1138 sctx->dbcb_stencil_copy_enabled) {
1139 radeon_emit(cs,
1140 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1141 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1142 S_028000_COPY_CENTROID(1) |
1143 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample));
1144 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1145 radeon_emit(cs,
1146 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1147 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace));
1148 } else {
1149 radeon_emit(cs,
1150 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1151 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear));
1152 }
1153
1154 /* DB_COUNT_CONTROL (occlusion queries) */
1155 if (sctx->b.num_occlusion_queries > 0 &&
1156 !sctx->occlusion_queries_disabled) {
1157 bool perfect = sctx->b.num_perfect_occlusion_queries > 0;
1158
1159 if (sctx->b.chip_class >= CIK) {
1160 radeon_emit(cs,
1161 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1162 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples) |
1163 S_028004_ZPASS_ENABLE(1) |
1164 S_028004_SLICE_EVEN_ENABLE(1) |
1165 S_028004_SLICE_ODD_ENABLE(1));
1166 } else {
1167 radeon_emit(cs,
1168 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1169 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples));
1170 }
1171 } else {
1172 /* Disable occlusion queries. */
1173 if (sctx->b.chip_class >= CIK) {
1174 radeon_emit(cs, 0);
1175 } else {
1176 radeon_emit(cs, S_028004_ZPASS_INCREMENT_DISABLE(1));
1177 }
1178 }
1179
1180 /* DB_RENDER_OVERRIDE2 */
1181 radeon_set_context_reg(cs, R_028010_DB_RENDER_OVERRIDE2,
1182 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1183 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1184 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1185
1186 db_shader_control = sctx->ps_db_shader_control;
1187
1188 /* Bug workaround for smoothing (overrasterization) on SI. */
1189 if (sctx->b.chip_class == SI && sctx->smoothing_enabled) {
1190 db_shader_control &= C_02880C_Z_ORDER;
1191 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1192 }
1193
1194 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1195 if (!rs || !rs->multisample_enable)
1196 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1197
1198 if (sctx->b.family == CHIP_STONEY &&
1199 sctx->screen->b.debug_flags & DBG_NO_RB_PLUS)
1200 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1201
1202 radeon_set_context_reg(cs, R_02880C_DB_SHADER_CONTROL,
1203 db_shader_control);
1204 }
1205
1206 /*
1207 * format translation
1208 */
1209 static uint32_t si_translate_colorformat(enum pipe_format format)
1210 {
1211 const struct util_format_description *desc = util_format_description(format);
1212
1213 #define HAS_SIZE(x,y,z,w) \
1214 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1215 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1216
1217 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1218 return V_028C70_COLOR_10_11_11;
1219
1220 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1221 return V_028C70_COLOR_INVALID;
1222
1223 /* hw cannot support mixed formats (except depth/stencil, since
1224 * stencil is not written to). */
1225 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1226 return V_028C70_COLOR_INVALID;
1227
1228 switch (desc->nr_channels) {
1229 case 1:
1230 switch (desc->channel[0].size) {
1231 case 8:
1232 return V_028C70_COLOR_8;
1233 case 16:
1234 return V_028C70_COLOR_16;
1235 case 32:
1236 return V_028C70_COLOR_32;
1237 }
1238 break;
1239 case 2:
1240 if (desc->channel[0].size == desc->channel[1].size) {
1241 switch (desc->channel[0].size) {
1242 case 8:
1243 return V_028C70_COLOR_8_8;
1244 case 16:
1245 return V_028C70_COLOR_16_16;
1246 case 32:
1247 return V_028C70_COLOR_32_32;
1248 }
1249 } else if (HAS_SIZE(8,24,0,0)) {
1250 return V_028C70_COLOR_24_8;
1251 } else if (HAS_SIZE(24,8,0,0)) {
1252 return V_028C70_COLOR_8_24;
1253 }
1254 break;
1255 case 3:
1256 if (HAS_SIZE(5,6,5,0)) {
1257 return V_028C70_COLOR_5_6_5;
1258 } else if (HAS_SIZE(32,8,24,0)) {
1259 return V_028C70_COLOR_X24_8_32_FLOAT;
1260 }
1261 break;
1262 case 4:
1263 if (desc->channel[0].size == desc->channel[1].size &&
1264 desc->channel[0].size == desc->channel[2].size &&
1265 desc->channel[0].size == desc->channel[3].size) {
1266 switch (desc->channel[0].size) {
1267 case 4:
1268 return V_028C70_COLOR_4_4_4_4;
1269 case 8:
1270 return V_028C70_COLOR_8_8_8_8;
1271 case 16:
1272 return V_028C70_COLOR_16_16_16_16;
1273 case 32:
1274 return V_028C70_COLOR_32_32_32_32;
1275 }
1276 } else if (HAS_SIZE(5,5,5,1)) {
1277 return V_028C70_COLOR_1_5_5_5;
1278 } else if (HAS_SIZE(10,10,10,2)) {
1279 return V_028C70_COLOR_2_10_10_10;
1280 }
1281 break;
1282 }
1283 return V_028C70_COLOR_INVALID;
1284 }
1285
1286 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1287 {
1288 if (SI_BIG_ENDIAN) {
1289 switch(colorformat) {
1290 /* 8-bit buffers. */
1291 case V_028C70_COLOR_8:
1292 return V_028C70_ENDIAN_NONE;
1293
1294 /* 16-bit buffers. */
1295 case V_028C70_COLOR_5_6_5:
1296 case V_028C70_COLOR_1_5_5_5:
1297 case V_028C70_COLOR_4_4_4_4:
1298 case V_028C70_COLOR_16:
1299 case V_028C70_COLOR_8_8:
1300 return V_028C70_ENDIAN_8IN16;
1301
1302 /* 32-bit buffers. */
1303 case V_028C70_COLOR_8_8_8_8:
1304 case V_028C70_COLOR_2_10_10_10:
1305 case V_028C70_COLOR_8_24:
1306 case V_028C70_COLOR_24_8:
1307 case V_028C70_COLOR_16_16:
1308 return V_028C70_ENDIAN_8IN32;
1309
1310 /* 64-bit buffers. */
1311 case V_028C70_COLOR_16_16_16_16:
1312 return V_028C70_ENDIAN_8IN16;
1313
1314 case V_028C70_COLOR_32_32:
1315 return V_028C70_ENDIAN_8IN32;
1316
1317 /* 128-bit buffers. */
1318 case V_028C70_COLOR_32_32_32_32:
1319 return V_028C70_ENDIAN_8IN32;
1320 default:
1321 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1322 }
1323 } else {
1324 return V_028C70_ENDIAN_NONE;
1325 }
1326 }
1327
1328 static uint32_t si_translate_dbformat(enum pipe_format format)
1329 {
1330 switch (format) {
1331 case PIPE_FORMAT_Z16_UNORM:
1332 return V_028040_Z_16;
1333 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1334 case PIPE_FORMAT_X8Z24_UNORM:
1335 case PIPE_FORMAT_Z24X8_UNORM:
1336 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1337 return V_028040_Z_24; /* deprecated on SI */
1338 case PIPE_FORMAT_Z32_FLOAT:
1339 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1340 return V_028040_Z_32_FLOAT;
1341 default:
1342 return V_028040_Z_INVALID;
1343 }
1344 }
1345
1346 /*
1347 * Texture translation
1348 */
1349
1350 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1351 enum pipe_format format,
1352 const struct util_format_description *desc,
1353 int first_non_void)
1354 {
1355 struct si_screen *sscreen = (struct si_screen*)screen;
1356 bool enable_compressed_formats = (sscreen->b.info.drm_major == 2 &&
1357 sscreen->b.info.drm_minor >= 31) ||
1358 sscreen->b.info.drm_major == 3;
1359 bool uniform = true;
1360 int i;
1361
1362 /* Colorspace (return non-RGB formats directly). */
1363 switch (desc->colorspace) {
1364 /* Depth stencil formats */
1365 case UTIL_FORMAT_COLORSPACE_ZS:
1366 switch (format) {
1367 case PIPE_FORMAT_Z16_UNORM:
1368 return V_008F14_IMG_DATA_FORMAT_16;
1369 case PIPE_FORMAT_X24S8_UINT:
1370 case PIPE_FORMAT_S8X24_UINT:
1371 /*
1372 * Implemented as an 8_8_8_8 data format to fix texture
1373 * gathers in stencil sampling. This affects at least
1374 * GL45-CTS.texture_cube_map_array.sampling on VI.
1375 */
1376 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1377 case PIPE_FORMAT_Z24X8_UNORM:
1378 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1379 return V_008F14_IMG_DATA_FORMAT_8_24;
1380 case PIPE_FORMAT_X8Z24_UNORM:
1381 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1382 return V_008F14_IMG_DATA_FORMAT_24_8;
1383 case PIPE_FORMAT_S8_UINT:
1384 return V_008F14_IMG_DATA_FORMAT_8;
1385 case PIPE_FORMAT_Z32_FLOAT:
1386 return V_008F14_IMG_DATA_FORMAT_32;
1387 case PIPE_FORMAT_X32_S8X24_UINT:
1388 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1389 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1390 default:
1391 goto out_unknown;
1392 }
1393
1394 case UTIL_FORMAT_COLORSPACE_YUV:
1395 goto out_unknown; /* TODO */
1396
1397 case UTIL_FORMAT_COLORSPACE_SRGB:
1398 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1399 goto out_unknown;
1400 break;
1401
1402 default:
1403 break;
1404 }
1405
1406 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1407 if (!enable_compressed_formats)
1408 goto out_unknown;
1409
1410 switch (format) {
1411 case PIPE_FORMAT_RGTC1_SNORM:
1412 case PIPE_FORMAT_LATC1_SNORM:
1413 case PIPE_FORMAT_RGTC1_UNORM:
1414 case PIPE_FORMAT_LATC1_UNORM:
1415 return V_008F14_IMG_DATA_FORMAT_BC4;
1416 case PIPE_FORMAT_RGTC2_SNORM:
1417 case PIPE_FORMAT_LATC2_SNORM:
1418 case PIPE_FORMAT_RGTC2_UNORM:
1419 case PIPE_FORMAT_LATC2_UNORM:
1420 return V_008F14_IMG_DATA_FORMAT_BC5;
1421 default:
1422 goto out_unknown;
1423 }
1424 }
1425
1426 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1427 sscreen->b.family == CHIP_STONEY) {
1428 switch (format) {
1429 case PIPE_FORMAT_ETC1_RGB8:
1430 case PIPE_FORMAT_ETC2_RGB8:
1431 case PIPE_FORMAT_ETC2_SRGB8:
1432 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1433 case PIPE_FORMAT_ETC2_RGB8A1:
1434 case PIPE_FORMAT_ETC2_SRGB8A1:
1435 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1436 case PIPE_FORMAT_ETC2_RGBA8:
1437 case PIPE_FORMAT_ETC2_SRGBA8:
1438 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1439 case PIPE_FORMAT_ETC2_R11_UNORM:
1440 case PIPE_FORMAT_ETC2_R11_SNORM:
1441 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1442 case PIPE_FORMAT_ETC2_RG11_UNORM:
1443 case PIPE_FORMAT_ETC2_RG11_SNORM:
1444 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1445 default:
1446 goto out_unknown;
1447 }
1448 }
1449
1450 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1451 if (!enable_compressed_formats)
1452 goto out_unknown;
1453
1454 switch (format) {
1455 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1456 case PIPE_FORMAT_BPTC_SRGBA:
1457 return V_008F14_IMG_DATA_FORMAT_BC7;
1458 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1459 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1460 return V_008F14_IMG_DATA_FORMAT_BC6;
1461 default:
1462 goto out_unknown;
1463 }
1464 }
1465
1466 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1467 switch (format) {
1468 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1469 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1470 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1471 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1472 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1473 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1474 default:
1475 goto out_unknown;
1476 }
1477 }
1478
1479 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1480 if (!enable_compressed_formats)
1481 goto out_unknown;
1482
1483 if (!util_format_s3tc_enabled) {
1484 goto out_unknown;
1485 }
1486
1487 switch (format) {
1488 case PIPE_FORMAT_DXT1_RGB:
1489 case PIPE_FORMAT_DXT1_RGBA:
1490 case PIPE_FORMAT_DXT1_SRGB:
1491 case PIPE_FORMAT_DXT1_SRGBA:
1492 return V_008F14_IMG_DATA_FORMAT_BC1;
1493 case PIPE_FORMAT_DXT3_RGBA:
1494 case PIPE_FORMAT_DXT3_SRGBA:
1495 return V_008F14_IMG_DATA_FORMAT_BC2;
1496 case PIPE_FORMAT_DXT5_RGBA:
1497 case PIPE_FORMAT_DXT5_SRGBA:
1498 return V_008F14_IMG_DATA_FORMAT_BC3;
1499 default:
1500 goto out_unknown;
1501 }
1502 }
1503
1504 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1505 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1506 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1507 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1508 }
1509
1510 /* R8G8Bx_SNORM - TODO CxV8U8 */
1511
1512 /* hw cannot support mixed formats (except depth/stencil, since only
1513 * depth is read).*/
1514 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1515 goto out_unknown;
1516
1517 /* See whether the components are of the same size. */
1518 for (i = 1; i < desc->nr_channels; i++) {
1519 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1520 }
1521
1522 /* Non-uniform formats. */
1523 if (!uniform) {
1524 switch(desc->nr_channels) {
1525 case 3:
1526 if (desc->channel[0].size == 5 &&
1527 desc->channel[1].size == 6 &&
1528 desc->channel[2].size == 5) {
1529 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1530 }
1531 goto out_unknown;
1532 case 4:
1533 if (desc->channel[0].size == 5 &&
1534 desc->channel[1].size == 5 &&
1535 desc->channel[2].size == 5 &&
1536 desc->channel[3].size == 1) {
1537 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1538 }
1539 if (desc->channel[0].size == 10 &&
1540 desc->channel[1].size == 10 &&
1541 desc->channel[2].size == 10 &&
1542 desc->channel[3].size == 2) {
1543 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1544 }
1545 goto out_unknown;
1546 }
1547 goto out_unknown;
1548 }
1549
1550 if (first_non_void < 0 || first_non_void > 3)
1551 goto out_unknown;
1552
1553 /* uniform formats */
1554 switch (desc->channel[first_non_void].size) {
1555 case 4:
1556 switch (desc->nr_channels) {
1557 #if 0 /* Not supported for render targets */
1558 case 2:
1559 return V_008F14_IMG_DATA_FORMAT_4_4;
1560 #endif
1561 case 4:
1562 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1563 }
1564 break;
1565 case 8:
1566 switch (desc->nr_channels) {
1567 case 1:
1568 return V_008F14_IMG_DATA_FORMAT_8;
1569 case 2:
1570 return V_008F14_IMG_DATA_FORMAT_8_8;
1571 case 4:
1572 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1573 }
1574 break;
1575 case 16:
1576 switch (desc->nr_channels) {
1577 case 1:
1578 return V_008F14_IMG_DATA_FORMAT_16;
1579 case 2:
1580 return V_008F14_IMG_DATA_FORMAT_16_16;
1581 case 4:
1582 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1583 }
1584 break;
1585 case 32:
1586 switch (desc->nr_channels) {
1587 case 1:
1588 return V_008F14_IMG_DATA_FORMAT_32;
1589 case 2:
1590 return V_008F14_IMG_DATA_FORMAT_32_32;
1591 #if 0 /* Not supported for render targets */
1592 case 3:
1593 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1594 #endif
1595 case 4:
1596 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1597 }
1598 }
1599
1600 out_unknown:
1601 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1602 return ~0;
1603 }
1604
1605 static unsigned si_tex_wrap(unsigned wrap)
1606 {
1607 switch (wrap) {
1608 default:
1609 case PIPE_TEX_WRAP_REPEAT:
1610 return V_008F30_SQ_TEX_WRAP;
1611 case PIPE_TEX_WRAP_CLAMP:
1612 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1613 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1614 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1615 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1616 return V_008F30_SQ_TEX_CLAMP_BORDER;
1617 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1618 return V_008F30_SQ_TEX_MIRROR;
1619 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1620 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1621 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1622 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1623 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1624 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1625 }
1626 }
1627
1628 static unsigned si_tex_mipfilter(unsigned filter)
1629 {
1630 switch (filter) {
1631 case PIPE_TEX_MIPFILTER_NEAREST:
1632 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1633 case PIPE_TEX_MIPFILTER_LINEAR:
1634 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1635 default:
1636 case PIPE_TEX_MIPFILTER_NONE:
1637 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1638 }
1639 }
1640
1641 static unsigned si_tex_compare(unsigned compare)
1642 {
1643 switch (compare) {
1644 default:
1645 case PIPE_FUNC_NEVER:
1646 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1647 case PIPE_FUNC_LESS:
1648 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1649 case PIPE_FUNC_EQUAL:
1650 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1651 case PIPE_FUNC_LEQUAL:
1652 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1653 case PIPE_FUNC_GREATER:
1654 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1655 case PIPE_FUNC_NOTEQUAL:
1656 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1657 case PIPE_FUNC_GEQUAL:
1658 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1659 case PIPE_FUNC_ALWAYS:
1660 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1661 }
1662 }
1663
1664 static unsigned si_tex_dim(unsigned res_target, unsigned view_target,
1665 unsigned nr_samples)
1666 {
1667 if (view_target == PIPE_TEXTURE_CUBE ||
1668 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1669 res_target = view_target;
1670 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1671 else if (res_target == PIPE_TEXTURE_CUBE ||
1672 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1673 res_target = PIPE_TEXTURE_2D_ARRAY;
1674
1675 switch (res_target) {
1676 default:
1677 case PIPE_TEXTURE_1D:
1678 return V_008F1C_SQ_RSRC_IMG_1D;
1679 case PIPE_TEXTURE_1D_ARRAY:
1680 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1681 case PIPE_TEXTURE_2D:
1682 case PIPE_TEXTURE_RECT:
1683 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1684 V_008F1C_SQ_RSRC_IMG_2D;
1685 case PIPE_TEXTURE_2D_ARRAY:
1686 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1687 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1688 case PIPE_TEXTURE_3D:
1689 return V_008F1C_SQ_RSRC_IMG_3D;
1690 case PIPE_TEXTURE_CUBE:
1691 case PIPE_TEXTURE_CUBE_ARRAY:
1692 return V_008F1C_SQ_RSRC_IMG_CUBE;
1693 }
1694 }
1695
1696 /*
1697 * Format support testing
1698 */
1699
1700 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1701 {
1702 return si_translate_texformat(screen, format, util_format_description(format),
1703 util_format_get_first_non_void_channel(format)) != ~0U;
1704 }
1705
1706 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1707 const struct util_format_description *desc,
1708 int first_non_void)
1709 {
1710 int i;
1711
1712 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1713 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1714
1715 assert(first_non_void >= 0);
1716
1717 if (desc->nr_channels == 4 &&
1718 desc->channel[0].size == 10 &&
1719 desc->channel[1].size == 10 &&
1720 desc->channel[2].size == 10 &&
1721 desc->channel[3].size == 2)
1722 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1723
1724 /* See whether the components are of the same size. */
1725 for (i = 0; i < desc->nr_channels; i++) {
1726 if (desc->channel[first_non_void].size != desc->channel[i].size)
1727 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1728 }
1729
1730 switch (desc->channel[first_non_void].size) {
1731 case 8:
1732 switch (desc->nr_channels) {
1733 case 1:
1734 return V_008F0C_BUF_DATA_FORMAT_8;
1735 case 2:
1736 return V_008F0C_BUF_DATA_FORMAT_8_8;
1737 case 3:
1738 case 4:
1739 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1740 }
1741 break;
1742 case 16:
1743 switch (desc->nr_channels) {
1744 case 1:
1745 return V_008F0C_BUF_DATA_FORMAT_16;
1746 case 2:
1747 return V_008F0C_BUF_DATA_FORMAT_16_16;
1748 case 3:
1749 case 4:
1750 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
1751 }
1752 break;
1753 case 32:
1754 switch (desc->nr_channels) {
1755 case 1:
1756 return V_008F0C_BUF_DATA_FORMAT_32;
1757 case 2:
1758 return V_008F0C_BUF_DATA_FORMAT_32_32;
1759 case 3:
1760 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
1761 case 4:
1762 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
1763 }
1764 break;
1765 }
1766
1767 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1768 }
1769
1770 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
1771 const struct util_format_description *desc,
1772 int first_non_void)
1773 {
1774 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1775 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1776
1777 assert(first_non_void >= 0);
1778
1779 switch (desc->channel[first_non_void].type) {
1780 case UTIL_FORMAT_TYPE_SIGNED:
1781 case UTIL_FORMAT_TYPE_FIXED:
1782 if (desc->channel[first_non_void].size >= 32 ||
1783 desc->channel[first_non_void].pure_integer)
1784 return V_008F0C_BUF_NUM_FORMAT_SINT;
1785 else if (desc->channel[first_non_void].normalized)
1786 return V_008F0C_BUF_NUM_FORMAT_SNORM;
1787 else
1788 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
1789 break;
1790 case UTIL_FORMAT_TYPE_UNSIGNED:
1791 if (desc->channel[first_non_void].size >= 32 ||
1792 desc->channel[first_non_void].pure_integer)
1793 return V_008F0C_BUF_NUM_FORMAT_UINT;
1794 else if (desc->channel[first_non_void].normalized)
1795 return V_008F0C_BUF_NUM_FORMAT_UNORM;
1796 else
1797 return V_008F0C_BUF_NUM_FORMAT_USCALED;
1798 break;
1799 case UTIL_FORMAT_TYPE_FLOAT:
1800 default:
1801 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
1802 }
1803 }
1804
1805 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
1806 enum pipe_format format,
1807 unsigned usage)
1808 {
1809 const struct util_format_description *desc;
1810 int first_non_void;
1811 unsigned data_format;
1812
1813 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
1814 PIPE_BIND_SAMPLER_VIEW |
1815 PIPE_BIND_VERTEX_BUFFER)) == 0);
1816
1817 desc = util_format_description(format);
1818
1819 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1820 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1821 * for read-only access (with caveats surrounding bounds checks), but
1822 * obviously fails for write access which we have to implement for
1823 * shader images. Luckily, OpenGL doesn't expect this to be supported
1824 * anyway, and so the only impact is on PBO uploads / downloads, which
1825 * shouldn't be expected to be fast for GL_RGB anyway.
1826 */
1827 if (desc->block.bits == 3 * 8 ||
1828 desc->block.bits == 3 * 16) {
1829 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
1830 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
1831 if (!usage)
1832 return 0;
1833 }
1834 }
1835
1836 first_non_void = util_format_get_first_non_void_channel(format);
1837 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
1838 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
1839 return 0;
1840
1841 return usage;
1842 }
1843
1844 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
1845 {
1846 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
1847 r600_translate_colorswap(format, false) != ~0U;
1848 }
1849
1850 static bool si_is_zs_format_supported(enum pipe_format format)
1851 {
1852 return si_translate_dbformat(format) != V_028040_Z_INVALID;
1853 }
1854
1855 static boolean si_is_format_supported(struct pipe_screen *screen,
1856 enum pipe_format format,
1857 enum pipe_texture_target target,
1858 unsigned sample_count,
1859 unsigned usage)
1860 {
1861 unsigned retval = 0;
1862
1863 if (target >= PIPE_MAX_TEXTURE_TYPES) {
1864 R600_ERR("r600: unsupported texture type %d\n", target);
1865 return false;
1866 }
1867
1868 if (!util_format_is_supported(format, usage))
1869 return false;
1870
1871 if (sample_count > 1) {
1872 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
1873 return false;
1874
1875 if (usage & PIPE_BIND_SHADER_IMAGE)
1876 return false;
1877
1878 switch (sample_count) {
1879 case 2:
1880 case 4:
1881 case 8:
1882 break;
1883 case 16:
1884 if (format == PIPE_FORMAT_NONE)
1885 return true;
1886 else
1887 return false;
1888 default:
1889 return false;
1890 }
1891 }
1892
1893 if (usage & (PIPE_BIND_SAMPLER_VIEW |
1894 PIPE_BIND_SHADER_IMAGE)) {
1895 if (target == PIPE_BUFFER) {
1896 retval |= si_is_vertex_format_supported(
1897 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
1898 PIPE_BIND_SHADER_IMAGE));
1899 } else {
1900 if (si_is_sampler_format_supported(screen, format))
1901 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
1902 PIPE_BIND_SHADER_IMAGE);
1903 }
1904 }
1905
1906 if ((usage & (PIPE_BIND_RENDER_TARGET |
1907 PIPE_BIND_DISPLAY_TARGET |
1908 PIPE_BIND_SCANOUT |
1909 PIPE_BIND_SHARED |
1910 PIPE_BIND_BLENDABLE)) &&
1911 si_is_colorbuffer_format_supported(format)) {
1912 retval |= usage &
1913 (PIPE_BIND_RENDER_TARGET |
1914 PIPE_BIND_DISPLAY_TARGET |
1915 PIPE_BIND_SCANOUT |
1916 PIPE_BIND_SHARED);
1917 if (!util_format_is_pure_integer(format) &&
1918 !util_format_is_depth_or_stencil(format))
1919 retval |= usage & PIPE_BIND_BLENDABLE;
1920 }
1921
1922 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
1923 si_is_zs_format_supported(format)) {
1924 retval |= PIPE_BIND_DEPTH_STENCIL;
1925 }
1926
1927 if (usage & PIPE_BIND_VERTEX_BUFFER) {
1928 retval |= si_is_vertex_format_supported(screen, format,
1929 PIPE_BIND_VERTEX_BUFFER);
1930 }
1931
1932 if ((usage & PIPE_BIND_LINEAR) &&
1933 !util_format_is_compressed(format) &&
1934 !(usage & PIPE_BIND_DEPTH_STENCIL))
1935 retval |= PIPE_BIND_LINEAR;
1936
1937 return retval == usage;
1938 }
1939
1940 /*
1941 * framebuffer handling
1942 */
1943
1944 static void si_choose_spi_color_formats(struct r600_surface *surf,
1945 unsigned format, unsigned swap,
1946 unsigned ntype, bool is_depth)
1947 {
1948 /* Alpha is needed for alpha-to-coverage.
1949 * Blending may be with or without alpha.
1950 */
1951 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
1952 unsigned alpha = 0; /* exports alpha, but may not support blending */
1953 unsigned blend = 0; /* supports blending, but may not export alpha */
1954 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
1955
1956 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1957 * Other chips have multiple choices, though they are not necessarily better.
1958 */
1959 switch (format) {
1960 case V_028C70_COLOR_5_6_5:
1961 case V_028C70_COLOR_1_5_5_5:
1962 case V_028C70_COLOR_5_5_5_1:
1963 case V_028C70_COLOR_4_4_4_4:
1964 case V_028C70_COLOR_10_11_11:
1965 case V_028C70_COLOR_11_11_10:
1966 case V_028C70_COLOR_8:
1967 case V_028C70_COLOR_8_8:
1968 case V_028C70_COLOR_8_8_8_8:
1969 case V_028C70_COLOR_10_10_10_2:
1970 case V_028C70_COLOR_2_10_10_10:
1971 if (ntype == V_028C70_NUMBER_UINT)
1972 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
1973 else if (ntype == V_028C70_NUMBER_SINT)
1974 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
1975 else
1976 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
1977 break;
1978
1979 case V_028C70_COLOR_16:
1980 case V_028C70_COLOR_16_16:
1981 case V_028C70_COLOR_16_16_16_16:
1982 if (ntype == V_028C70_NUMBER_UNORM ||
1983 ntype == V_028C70_NUMBER_SNORM) {
1984 /* UNORM16 and SNORM16 don't support blending */
1985 if (ntype == V_028C70_NUMBER_UNORM)
1986 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
1987 else
1988 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
1989
1990 /* Use 32 bits per channel for blending. */
1991 if (format == V_028C70_COLOR_16) {
1992 if (swap == V_028C70_SWAP_STD) { /* R */
1993 blend = V_028714_SPI_SHADER_32_R;
1994 blend_alpha = V_028714_SPI_SHADER_32_AR;
1995 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
1996 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
1997 else
1998 assert(0);
1999 } else if (format == V_028C70_COLOR_16_16) {
2000 if (swap == V_028C70_SWAP_STD) { /* RG */
2001 blend = V_028714_SPI_SHADER_32_GR;
2002 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2003 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2004 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2005 else
2006 assert(0);
2007 } else /* 16_16_16_16 */
2008 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2009 } else if (ntype == V_028C70_NUMBER_UINT)
2010 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2011 else if (ntype == V_028C70_NUMBER_SINT)
2012 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2013 else if (ntype == V_028C70_NUMBER_FLOAT)
2014 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2015 else
2016 assert(0);
2017 break;
2018
2019 case V_028C70_COLOR_32:
2020 if (swap == V_028C70_SWAP_STD) { /* R */
2021 blend = normal = V_028714_SPI_SHADER_32_R;
2022 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2023 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2024 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2025 else
2026 assert(0);
2027 break;
2028
2029 case V_028C70_COLOR_32_32:
2030 if (swap == V_028C70_SWAP_STD) { /* RG */
2031 blend = normal = V_028714_SPI_SHADER_32_GR;
2032 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2033 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2034 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2035 else
2036 assert(0);
2037 break;
2038
2039 case V_028C70_COLOR_32_32_32_32:
2040 case V_028C70_COLOR_8_24:
2041 case V_028C70_COLOR_24_8:
2042 case V_028C70_COLOR_X24_8_32_FLOAT:
2043 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2044 break;
2045
2046 default:
2047 assert(0);
2048 return;
2049 }
2050
2051 /* The DB->CB copy needs 32_ABGR. */
2052 if (is_depth)
2053 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2054
2055 surf->spi_shader_col_format = normal;
2056 surf->spi_shader_col_format_alpha = alpha;
2057 surf->spi_shader_col_format_blend = blend;
2058 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2059 }
2060
2061 static void si_initialize_color_surface(struct si_context *sctx,
2062 struct r600_surface *surf)
2063 {
2064 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2065 unsigned color_info, color_attrib, color_view;
2066 unsigned format, swap, ntype, endian;
2067 const struct util_format_description *desc;
2068 int i;
2069 unsigned blend_clamp = 0, blend_bypass = 0;
2070
2071 color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2072 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2073
2074 desc = util_format_description(surf->base.format);
2075 for (i = 0; i < 4; i++) {
2076 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
2077 break;
2078 }
2079 }
2080 if (i == 4 || desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT) {
2081 ntype = V_028C70_NUMBER_FLOAT;
2082 } else {
2083 ntype = V_028C70_NUMBER_UNORM;
2084 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2085 ntype = V_028C70_NUMBER_SRGB;
2086 else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
2087 if (desc->channel[i].pure_integer) {
2088 ntype = V_028C70_NUMBER_SINT;
2089 } else {
2090 assert(desc->channel[i].normalized);
2091 ntype = V_028C70_NUMBER_SNORM;
2092 }
2093 } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2094 if (desc->channel[i].pure_integer) {
2095 ntype = V_028C70_NUMBER_UINT;
2096 } else {
2097 assert(desc->channel[i].normalized);
2098 ntype = V_028C70_NUMBER_UNORM;
2099 }
2100 }
2101 }
2102
2103 format = si_translate_colorformat(surf->base.format);
2104 if (format == V_028C70_COLOR_INVALID) {
2105 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2106 }
2107 assert(format != V_028C70_COLOR_INVALID);
2108 swap = r600_translate_colorswap(surf->base.format, false);
2109 endian = si_colorformat_endian_swap(format);
2110
2111 /* blend clamp should be set for all NORM/SRGB types */
2112 if (ntype == V_028C70_NUMBER_UNORM ||
2113 ntype == V_028C70_NUMBER_SNORM ||
2114 ntype == V_028C70_NUMBER_SRGB)
2115 blend_clamp = 1;
2116
2117 /* set blend bypass according to docs if SINT/UINT or
2118 8/24 COLOR variants */
2119 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2120 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2121 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2122 blend_clamp = 0;
2123 blend_bypass = 1;
2124 }
2125
2126 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2127 (format == V_028C70_COLOR_8 ||
2128 format == V_028C70_COLOR_8_8 ||
2129 format == V_028C70_COLOR_8_8_8_8))
2130 surf->color_is_int8 = true;
2131
2132 color_info = S_028C70_FORMAT(format) |
2133 S_028C70_COMP_SWAP(swap) |
2134 S_028C70_BLEND_CLAMP(blend_clamp) |
2135 S_028C70_BLEND_BYPASS(blend_bypass) |
2136 S_028C70_SIMPLE_FLOAT(1) |
2137 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2138 ntype != V_028C70_NUMBER_SNORM &&
2139 ntype != V_028C70_NUMBER_SRGB &&
2140 format != V_028C70_COLOR_8_24 &&
2141 format != V_028C70_COLOR_24_8) |
2142 S_028C70_NUMBER_TYPE(ntype) |
2143 S_028C70_ENDIAN(endian);
2144
2145 /* Intensity is implemented as Red, so treat it that way. */
2146 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2147 util_format_is_intensity(surf->base.format));
2148
2149 if (rtex->resource.b.b.nr_samples > 1) {
2150 unsigned log_samples = util_logbase2(rtex->resource.b.b.nr_samples);
2151
2152 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2153 S_028C74_NUM_FRAGMENTS(log_samples);
2154
2155 if (rtex->fmask.size) {
2156 color_info |= S_028C70_COMPRESSION(1);
2157 unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
2158
2159 if (sctx->b.chip_class == SI) {
2160 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2161 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2162 }
2163 }
2164 }
2165
2166 surf->cb_color_view = color_view;
2167 surf->cb_color_info = color_info;
2168 surf->cb_color_attrib = color_attrib;
2169
2170 if (sctx->b.chip_class >= VI) {
2171 unsigned max_uncompressed_block_size = 2;
2172
2173 if (rtex->resource.b.b.nr_samples > 1) {
2174 if (rtex->surface.bpe == 1)
2175 max_uncompressed_block_size = 0;
2176 else if (rtex->surface.bpe == 2)
2177 max_uncompressed_block_size = 1;
2178 }
2179
2180 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2181 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2182 }
2183
2184 /* This must be set for fast clear to work without FMASK. */
2185 if (!rtex->fmask.size && sctx->b.chip_class == SI) {
2186 unsigned bankh = util_logbase2(rtex->surface.bankh);
2187 surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2188 }
2189
2190 /* Determine pixel shader export format */
2191 si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
2192
2193 surf->color_initialized = true;
2194 }
2195
2196 static void si_init_depth_surface(struct si_context *sctx,
2197 struct r600_surface *surf)
2198 {
2199 struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
2200 unsigned level = surf->base.u.tex.level;
2201 struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
2202 unsigned format;
2203 uint32_t z_info, s_info, db_depth_info;
2204 uint64_t z_offs, s_offs;
2205 uint32_t db_htile_data_base, db_htile_surface;
2206
2207 format = si_translate_dbformat(rtex->db_render_format);
2208
2209 if (format == V_028040_Z_INVALID) {
2210 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex->resource.b.b.format);
2211 }
2212 assert(format != V_028040_Z_INVALID);
2213
2214 s_offs = z_offs = rtex->resource.gpu_address;
2215 z_offs += rtex->surface.level[level].offset;
2216 s_offs += rtex->surface.stencil_level[level].offset;
2217
2218 db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
2219
2220 z_info = S_028040_FORMAT(format);
2221 if (rtex->resource.b.b.nr_samples > 1) {
2222 z_info |= S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
2223 }
2224
2225 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
2226 s_info = S_028044_FORMAT(V_028044_STENCIL_8);
2227 else
2228 s_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2229
2230 if (sctx->b.chip_class >= CIK) {
2231 struct radeon_info *info = &sctx->screen->b.info;
2232 unsigned index = rtex->surface.tiling_index[level];
2233 unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
2234 unsigned macro_index = rtex->surface.macro_tile_index;
2235 unsigned tile_mode = info->si_tile_mode_array[index];
2236 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2237 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2238
2239 db_depth_info |=
2240 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2241 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2242 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2243 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2244 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2245 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2246 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2247 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2248 } else {
2249 unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
2250 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2251 tile_mode_index = si_tile_mode_index(rtex, level, true);
2252 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2253 }
2254
2255 /* HiZ aka depth buffer htile */
2256 /* use htile only for first level */
2257 if (rtex->htile_buffer && !level) {
2258 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2259 S_028040_ALLOW_EXPCLEAR(1);
2260
2261 if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
2262 /* Workaround: For a not yet understood reason, the
2263 * combination of MSAA, fast stencil clear and stencil
2264 * decompress messes with subsequent stencil buffer
2265 * uses. Problem was reproduced on Verde, Bonaire,
2266 * Tonga, and Carrizo.
2267 *
2268 * Disabling EXPCLEAR works around the problem.
2269 *
2270 * Check piglit's arb_texture_multisample-stencil-clear
2271 * test if you want to try changing this.
2272 */
2273 if (rtex->resource.b.b.nr_samples <= 1)
2274 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2275 } else if (!rtex->tc_compatible_htile) {
2276 /* Use all of the htile_buffer for depth if there's no stencil.
2277 * This must not be set when TC-compatible HTILE is enabled
2278 * due to a hw bug.
2279 */
2280 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2281 }
2282
2283 uint64_t va = rtex->htile_buffer->gpu_address;
2284 db_htile_data_base = va >> 8;
2285 db_htile_surface = S_028ABC_FULL_CACHE(1);
2286
2287 if (rtex->tc_compatible_htile) {
2288 db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2289
2290 switch (rtex->resource.b.b.nr_samples) {
2291 case 0:
2292 case 1:
2293 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2294 break;
2295 case 2:
2296 case 4:
2297 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2298 break;
2299 case 8:
2300 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2301 break;
2302 default:
2303 assert(0);
2304 }
2305 }
2306 } else {
2307 db_htile_data_base = 0;
2308 db_htile_surface = 0;
2309 }
2310
2311 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2312
2313 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2314 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2315 surf->db_htile_data_base = db_htile_data_base;
2316 surf->db_depth_info = db_depth_info;
2317 surf->db_z_info = z_info;
2318 surf->db_stencil_info = s_info;
2319 surf->db_depth_base = z_offs >> 8;
2320 surf->db_stencil_base = s_offs >> 8;
2321 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2322 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2323 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2324 levelinfo->nblk_y) / 64 - 1);
2325 surf->db_htile_surface = db_htile_surface;
2326
2327 surf->depth_initialized = true;
2328 }
2329
2330 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2331 {
2332 for (int i = 0; i < state->nr_cbufs; ++i) {
2333 struct r600_surface *surf = NULL;
2334 struct r600_texture *rtex;
2335
2336 if (!state->cbufs[i])
2337 continue;
2338 surf = (struct r600_surface*)state->cbufs[i];
2339 rtex = (struct r600_texture*)surf->base.texture;
2340
2341 p_atomic_dec(&rtex->framebuffers_bound);
2342 }
2343 }
2344
2345 static void si_set_framebuffer_state(struct pipe_context *ctx,
2346 const struct pipe_framebuffer_state *state)
2347 {
2348 struct si_context *sctx = (struct si_context *)ctx;
2349 struct pipe_constant_buffer constbuf = {0};
2350 struct r600_surface *surf = NULL;
2351 struct r600_texture *rtex;
2352 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2353 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2354 int i;
2355
2356 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2357 if (!sctx->framebuffer.state.cbufs[i])
2358 continue;
2359
2360 rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2361 if (rtex->dcc_gather_statistics)
2362 vi_separate_dcc_stop_query(ctx, rtex);
2363 }
2364
2365 /* Only flush TC when changing the framebuffer state, because
2366 * the only client not using TC that can change textures is
2367 * the framebuffer.
2368 *
2369 * Flush all CB and DB caches here because all buffers can be used
2370 * for write by both TC (with shader image stores) and CB/DB.
2371 */
2372 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
2373 SI_CONTEXT_INV_GLOBAL_L2 |
2374 SI_CONTEXT_FLUSH_AND_INV_CB |
2375 SI_CONTEXT_FLUSH_AND_INV_DB |
2376 SI_CONTEXT_CS_PARTIAL_FLUSH;
2377
2378 /* Take the maximum of the old and new count. If the new count is lower,
2379 * dirtying is needed to disable the unbound colorbuffers.
2380 */
2381 sctx->framebuffer.dirty_cbufs |=
2382 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2383 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2384
2385 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2386 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2387
2388 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2389 sctx->framebuffer.spi_shader_col_format = 0;
2390 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2391 sctx->framebuffer.spi_shader_col_format_blend = 0;
2392 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2393 sctx->framebuffer.color_is_int8 = 0;
2394
2395 sctx->framebuffer.compressed_cb_mask = 0;
2396 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2397 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2398 sctx->framebuffer.any_dst_linear = false;
2399
2400 for (i = 0; i < state->nr_cbufs; i++) {
2401 if (!state->cbufs[i])
2402 continue;
2403
2404 surf = (struct r600_surface*)state->cbufs[i];
2405 rtex = (struct r600_texture*)surf->base.texture;
2406
2407 if (!surf->color_initialized) {
2408 si_initialize_color_surface(sctx, surf);
2409 }
2410
2411 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2412 sctx->framebuffer.spi_shader_col_format |=
2413 surf->spi_shader_col_format << (i * 4);
2414 sctx->framebuffer.spi_shader_col_format_alpha |=
2415 surf->spi_shader_col_format_alpha << (i * 4);
2416 sctx->framebuffer.spi_shader_col_format_blend |=
2417 surf->spi_shader_col_format_blend << (i * 4);
2418 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2419 surf->spi_shader_col_format_blend_alpha << (i * 4);
2420
2421 if (surf->color_is_int8)
2422 sctx->framebuffer.color_is_int8 |= 1 << i;
2423
2424 if (rtex->fmask.size) {
2425 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2426 }
2427
2428 if (rtex->surface.is_linear)
2429 sctx->framebuffer.any_dst_linear = true;
2430
2431 r600_context_add_resource_size(ctx, surf->base.texture);
2432
2433 p_atomic_inc(&rtex->framebuffers_bound);
2434
2435 if (rtex->dcc_gather_statistics) {
2436 /* Dirty tracking must be enabled for DCC usage analysis. */
2437 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2438 vi_separate_dcc_start_query(ctx, rtex);
2439 }
2440 }
2441
2442 if (state->zsbuf) {
2443 surf = (struct r600_surface*)state->zsbuf;
2444 rtex = (struct r600_texture*)surf->base.texture;
2445
2446 if (!surf->depth_initialized) {
2447 si_init_depth_surface(sctx, surf);
2448 }
2449 r600_context_add_resource_size(ctx, surf->base.texture);
2450 }
2451
2452 si_update_poly_offset_state(sctx);
2453 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2454 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
2455
2456 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2457 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2458
2459 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2460 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2461 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2462
2463 /* Set sample locations as fragment shader constants. */
2464 switch (sctx->framebuffer.nr_samples) {
2465 case 1:
2466 constbuf.user_buffer = sctx->b.sample_locations_1x;
2467 break;
2468 case 2:
2469 constbuf.user_buffer = sctx->b.sample_locations_2x;
2470 break;
2471 case 4:
2472 constbuf.user_buffer = sctx->b.sample_locations_4x;
2473 break;
2474 case 8:
2475 constbuf.user_buffer = sctx->b.sample_locations_8x;
2476 break;
2477 case 16:
2478 constbuf.user_buffer = sctx->b.sample_locations_16x;
2479 break;
2480 default:
2481 R600_ERR("Requested an invalid number of samples %i.\n",
2482 sctx->framebuffer.nr_samples);
2483 assert(0);
2484 }
2485 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2486 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2487
2488 si_mark_atom_dirty(sctx, &sctx->msaa_sample_locs.atom);
2489 }
2490
2491 sctx->need_check_render_feedback = true;
2492 sctx->do_update_shaders = true;
2493 sctx->framebuffer.do_update_surf_dirtiness = true;
2494 }
2495
2496 static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom *atom)
2497 {
2498 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2499 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2500 unsigned i, nr_cbufs = state->nr_cbufs;
2501 struct r600_texture *tex = NULL;
2502 struct r600_surface *cb = NULL;
2503 unsigned cb_color_info = 0;
2504
2505 /* Colorbuffers. */
2506 for (i = 0; i < nr_cbufs; i++) {
2507 const struct radeon_surf_level *level_info;
2508 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2509 unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
2510 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
2511
2512 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
2513 continue;
2514
2515 cb = (struct r600_surface*)state->cbufs[i];
2516 if (!cb) {
2517 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
2518 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
2519 continue;
2520 }
2521
2522 tex = (struct r600_texture *)cb->base.texture;
2523 level_info = &tex->surface.level[cb->base.u.tex.level];
2524 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2525 &tex->resource, RADEON_USAGE_READWRITE,
2526 tex->resource.b.b.nr_samples > 1 ?
2527 RADEON_PRIO_COLOR_BUFFER_MSAA :
2528 RADEON_PRIO_COLOR_BUFFER);
2529
2530 if (tex->cmask_buffer && tex->cmask_buffer != &tex->resource) {
2531 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2532 tex->cmask_buffer, RADEON_USAGE_READWRITE,
2533 RADEON_PRIO_CMASK);
2534 }
2535
2536 if (tex->dcc_separate_buffer)
2537 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2538 tex->dcc_separate_buffer,
2539 RADEON_USAGE_READWRITE,
2540 RADEON_PRIO_DCC);
2541
2542 /* Compute mutable surface parameters. */
2543 pitch_tile_max = level_info->nblk_x / 8 - 1;
2544 slice_tile_max = level_info->nblk_x *
2545 level_info->nblk_y / 64 - 1;
2546 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
2547
2548 cb_color_base = (tex->resource.gpu_address + level_info->offset) >> 8;
2549 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2550 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2551 cb_color_attrib = cb->cb_color_attrib |
2552 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2553
2554 if (tex->fmask.size) {
2555 if (sctx->b.chip_class >= CIK)
2556 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->fmask.pitch_in_pixels / 8 - 1);
2557 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->fmask.tile_mode_index);
2558 cb_color_fmask = (tex->resource.gpu_address + tex->fmask.offset) >> 8;
2559 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->fmask.slice_tile_max);
2560 } else {
2561 /* This must be set for fast clear to work without FMASK. */
2562 if (sctx->b.chip_class >= CIK)
2563 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2564 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2565 cb_color_fmask = cb_color_base;
2566 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2567 }
2568
2569 cb_color_info = cb->cb_color_info | tex->cb_color_info;
2570
2571 if (tex->dcc_offset && cb->base.u.tex.level < tex->surface.num_dcc_levels) {
2572 bool is_msaa_resolve_dst = state->cbufs[0] &&
2573 state->cbufs[0]->texture->nr_samples > 1 &&
2574 state->cbufs[1] == &cb->base &&
2575 state->cbufs[1]->texture->nr_samples <= 1;
2576
2577 if (!is_msaa_resolve_dst)
2578 cb_color_info |= S_028C70_DCC_ENABLE(1);
2579 }
2580
2581 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
2582 sctx->b.chip_class >= VI ? 14 : 13);
2583 radeon_emit(cs, cb_color_base); /* R_028C60_CB_COLOR0_BASE */
2584 radeon_emit(cs, cb_color_pitch); /* R_028C64_CB_COLOR0_PITCH */
2585 radeon_emit(cs, cb_color_slice); /* R_028C68_CB_COLOR0_SLICE */
2586 radeon_emit(cs, cb->cb_color_view); /* R_028C6C_CB_COLOR0_VIEW */
2587 radeon_emit(cs, cb_color_info); /* R_028C70_CB_COLOR0_INFO */
2588 radeon_emit(cs, cb_color_attrib); /* R_028C74_CB_COLOR0_ATTRIB */
2589 radeon_emit(cs, cb->cb_dcc_control); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2590 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */
2591 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2592 radeon_emit(cs, cb_color_fmask); /* R_028C84_CB_COLOR0_FMASK */
2593 radeon_emit(cs, cb_color_fmask_slice); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2594 radeon_emit(cs, tex->color_clear_value[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2595 radeon_emit(cs, tex->color_clear_value[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2596
2597 if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
2598 radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
2599 tex->dcc_offset +
2600 tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
2601 }
2602 for (; i < 8 ; i++)
2603 if (sctx->framebuffer.dirty_cbufs & (1 << i))
2604 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
2605
2606 /* ZS buffer. */
2607 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
2608 struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
2609 struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
2610
2611 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2612 &rtex->resource, RADEON_USAGE_READWRITE,
2613 zb->base.texture->nr_samples > 1 ?
2614 RADEON_PRIO_DEPTH_BUFFER_MSAA :
2615 RADEON_PRIO_DEPTH_BUFFER);
2616
2617 if (zb->db_htile_data_base) {
2618 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
2619 rtex->htile_buffer, RADEON_USAGE_READWRITE,
2620 RADEON_PRIO_HTILE);
2621 }
2622
2623 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
2624 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
2625
2626 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
2627 radeon_emit(cs, zb->db_depth_info); /* R_02803C_DB_DEPTH_INFO */
2628 radeon_emit(cs, zb->db_z_info | /* R_028040_DB_Z_INFO */
2629 S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
2630 radeon_emit(cs, zb->db_stencil_info); /* R_028044_DB_STENCIL_INFO */
2631 radeon_emit(cs, zb->db_depth_base); /* R_028048_DB_Z_READ_BASE */
2632 radeon_emit(cs, zb->db_stencil_base); /* R_02804C_DB_STENCIL_READ_BASE */
2633 radeon_emit(cs, zb->db_depth_base); /* R_028050_DB_Z_WRITE_BASE */
2634 radeon_emit(cs, zb->db_stencil_base); /* R_028054_DB_STENCIL_WRITE_BASE */
2635 radeon_emit(cs, zb->db_depth_size); /* R_028058_DB_DEPTH_SIZE */
2636 radeon_emit(cs, zb->db_depth_slice); /* R_02805C_DB_DEPTH_SLICE */
2637
2638 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
2639 radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
2640 radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
2641
2642 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
2643 } else if (sctx->framebuffer.dirty_zsbuf) {
2644 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
2645 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* R_028040_DB_Z_INFO */
2646 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* R_028044_DB_STENCIL_INFO */
2647 }
2648
2649 /* Framebuffer dimensions. */
2650 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2651 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
2652 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
2653
2654 sctx->framebuffer.dirty_cbufs = 0;
2655 sctx->framebuffer.dirty_zsbuf = false;
2656 }
2657
2658 static void si_emit_msaa_sample_locs(struct si_context *sctx,
2659 struct r600_atom *atom)
2660 {
2661 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2662 unsigned nr_samples = sctx->framebuffer.nr_samples;
2663
2664 /* Smoothing (only possible with nr_samples == 1) uses the same
2665 * sample locations as the MSAA it simulates.
2666 */
2667 if (nr_samples <= 1 && sctx->smoothing_enabled)
2668 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
2669
2670 /* On Polaris, the small primitive filter uses the sample locations
2671 * even when MSAA is off, so we need to make sure they're set to 0.
2672 */
2673 if (sctx->b.family >= CHIP_POLARIS10)
2674 nr_samples = MAX2(nr_samples, 1);
2675
2676 if (nr_samples >= 1 &&
2677 (nr_samples != sctx->msaa_sample_locs.nr_samples)) {
2678 sctx->msaa_sample_locs.nr_samples = nr_samples;
2679 cayman_emit_msaa_sample_locs(cs, nr_samples);
2680 }
2681
2682 if (sctx->b.family >= CHIP_POLARIS10) {
2683 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2684 unsigned small_prim_filter_cntl =
2685 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2686 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2687
2688 /* The alternative of setting sample locations to 0 would
2689 * require a DB flush to avoid Z errors, see
2690 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2691 */
2692 if (sctx->framebuffer.nr_samples > 1 && rs && !rs->multisample_enable)
2693 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
2694
2695 radeon_set_context_reg(cs, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
2696 small_prim_filter_cntl);
2697 }
2698 }
2699
2700 static void si_emit_msaa_config(struct si_context *sctx, struct r600_atom *atom)
2701 {
2702 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
2703 unsigned num_tile_pipes = sctx->screen->b.info.num_tile_pipes;
2704 /* 33% faster rendering to linear color buffers */
2705 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
2706 unsigned sc_mode_cntl_1 =
2707 S_028A4C_WALK_SIZE(dst_is_linear) |
2708 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
2709 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
2710 /* always 1: */
2711 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2712 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2713 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2714 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2715 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2716 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2717
2718 cayman_emit_msaa_config(cs, sctx->framebuffer.nr_samples,
2719 sctx->ps_iter_samples,
2720 sctx->smoothing_enabled ? SI_NUM_SMOOTH_AA_SAMPLES : 0,
2721 sc_mode_cntl_1);
2722 }
2723
2724 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
2725 {
2726 struct si_context *sctx = (struct si_context *)ctx;
2727
2728 if (sctx->ps_iter_samples == min_samples)
2729 return;
2730
2731 sctx->ps_iter_samples = min_samples;
2732 sctx->do_update_shaders = true;
2733
2734 if (sctx->framebuffer.nr_samples > 1)
2735 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2736 }
2737
2738 /*
2739 * Samplers
2740 */
2741
2742 /**
2743 * Build the sampler view descriptor for a buffer texture.
2744 * @param state 256-bit descriptor; only the high 128 bits are filled in
2745 */
2746 void
2747 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
2748 enum pipe_format format,
2749 unsigned offset, unsigned size,
2750 uint32_t *state)
2751 {
2752 const struct util_format_description *desc;
2753 int first_non_void;
2754 unsigned stride;
2755 unsigned num_records;
2756 unsigned num_format, data_format;
2757
2758 desc = util_format_description(format);
2759 first_non_void = util_format_get_first_non_void_channel(format);
2760 stride = desc->block.bits / 8;
2761 num_format = si_translate_buffer_numformat(&screen->b.b, desc, first_non_void);
2762 data_format = si_translate_buffer_dataformat(&screen->b.b, desc, first_non_void);
2763
2764 num_records = size / stride;
2765 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
2766
2767 if (screen->b.chip_class >= VI)
2768 num_records *= stride;
2769
2770 state[4] = 0;
2771 state[5] = S_008F04_STRIDE(stride);
2772 state[6] = num_records;
2773 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
2774 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
2775 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
2776 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
2777 S_008F0C_NUM_FORMAT(num_format) |
2778 S_008F0C_DATA_FORMAT(data_format);
2779 }
2780
2781 /**
2782 * Build the sampler view descriptor for a texture.
2783 */
2784 void
2785 si_make_texture_descriptor(struct si_screen *screen,
2786 struct r600_texture *tex,
2787 bool sampler,
2788 enum pipe_texture_target target,
2789 enum pipe_format pipe_format,
2790 const unsigned char state_swizzle[4],
2791 unsigned first_level, unsigned last_level,
2792 unsigned first_layer, unsigned last_layer,
2793 unsigned width, unsigned height, unsigned depth,
2794 uint32_t *state,
2795 uint32_t *fmask_state)
2796 {
2797 struct pipe_resource *res = &tex->resource.b.b;
2798 const struct util_format_description *desc;
2799 unsigned char swizzle[4];
2800 int first_non_void;
2801 unsigned num_format, data_format, type;
2802 uint64_t va;
2803
2804 desc = util_format_description(pipe_format);
2805
2806 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
2807 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
2808 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
2809 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
2810
2811 switch (pipe_format) {
2812 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2813 case PIPE_FORMAT_X32_S8X24_UINT:
2814 case PIPE_FORMAT_X8Z24_UNORM:
2815 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
2816 break;
2817 case PIPE_FORMAT_X24S8_UINT:
2818 /*
2819 * X24S8 is implemented as an 8_8_8_8 data format, to
2820 * fix texture gathers. This affects at least
2821 * GL45-CTS.texture_cube_map_array.sampling on VI.
2822 */
2823 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
2824 break;
2825 default:
2826 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
2827 }
2828 } else {
2829 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
2830 }
2831
2832 first_non_void = util_format_get_first_non_void_channel(pipe_format);
2833
2834 switch (pipe_format) {
2835 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
2836 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2837 break;
2838 default:
2839 if (first_non_void < 0) {
2840 if (util_format_is_compressed(pipe_format)) {
2841 switch (pipe_format) {
2842 case PIPE_FORMAT_DXT1_SRGB:
2843 case PIPE_FORMAT_DXT1_SRGBA:
2844 case PIPE_FORMAT_DXT3_SRGBA:
2845 case PIPE_FORMAT_DXT5_SRGBA:
2846 case PIPE_FORMAT_BPTC_SRGBA:
2847 case PIPE_FORMAT_ETC2_SRGB8:
2848 case PIPE_FORMAT_ETC2_SRGB8A1:
2849 case PIPE_FORMAT_ETC2_SRGBA8:
2850 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2851 break;
2852 case PIPE_FORMAT_RGTC1_SNORM:
2853 case PIPE_FORMAT_LATC1_SNORM:
2854 case PIPE_FORMAT_RGTC2_SNORM:
2855 case PIPE_FORMAT_LATC2_SNORM:
2856 case PIPE_FORMAT_ETC2_R11_SNORM:
2857 case PIPE_FORMAT_ETC2_RG11_SNORM:
2858 /* implies float, so use SNORM/UNORM to determine
2859 whether data is signed or not */
2860 case PIPE_FORMAT_BPTC_RGB_FLOAT:
2861 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2862 break;
2863 default:
2864 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2865 break;
2866 }
2867 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
2868 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2869 } else {
2870 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2871 }
2872 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
2873 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
2874 } else {
2875 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2876
2877 switch (desc->channel[first_non_void].type) {
2878 case UTIL_FORMAT_TYPE_FLOAT:
2879 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
2880 break;
2881 case UTIL_FORMAT_TYPE_SIGNED:
2882 if (desc->channel[first_non_void].normalized)
2883 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
2884 else if (desc->channel[first_non_void].pure_integer)
2885 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
2886 else
2887 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
2888 break;
2889 case UTIL_FORMAT_TYPE_UNSIGNED:
2890 if (desc->channel[first_non_void].normalized)
2891 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
2892 else if (desc->channel[first_non_void].pure_integer)
2893 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
2894 else
2895 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
2896 }
2897 }
2898 }
2899
2900 data_format = si_translate_texformat(&screen->b.b, pipe_format, desc, first_non_void);
2901 if (data_format == ~0) {
2902 data_format = 0;
2903 }
2904
2905 if (!sampler &&
2906 (res->target == PIPE_TEXTURE_CUBE ||
2907 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
2908 res->target == PIPE_TEXTURE_3D)) {
2909 /* For the purpose of shader images, treat cube maps and 3D
2910 * textures as 2D arrays. For 3D textures, the address
2911 * calculations for mipmaps are different, so we rely on the
2912 * caller to effectively disable mipmaps.
2913 */
2914 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
2915
2916 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
2917 } else {
2918 type = si_tex_dim(res->target, target, res->nr_samples);
2919 }
2920
2921 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
2922 height = 1;
2923 depth = res->array_size;
2924 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
2925 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
2926 if (sampler || res->target != PIPE_TEXTURE_3D)
2927 depth = res->array_size;
2928 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
2929 depth = res->array_size / 6;
2930
2931 state[0] = 0;
2932 state[1] = (S_008F14_DATA_FORMAT(data_format) |
2933 S_008F14_NUM_FORMAT(num_format));
2934 state[2] = (S_008F18_WIDTH(width - 1) |
2935 S_008F18_HEIGHT(height - 1) |
2936 S_008F18_PERF_MOD(4));
2937 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
2938 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
2939 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
2940 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
2941 S_008F1C_BASE_LEVEL(res->nr_samples > 1 ?
2942 0 : first_level) |
2943 S_008F1C_LAST_LEVEL(res->nr_samples > 1 ?
2944 util_logbase2(res->nr_samples) :
2945 last_level) |
2946 S_008F1C_POW2_PAD(res->last_level > 0) |
2947 S_008F1C_TYPE(type));
2948 state[4] = S_008F20_DEPTH(depth - 1);
2949 state[5] = (S_008F24_BASE_ARRAY(first_layer) |
2950 S_008F24_LAST_ARRAY(last_layer));
2951 state[6] = 0;
2952 state[7] = 0;
2953
2954 if (tex->dcc_offset) {
2955 unsigned swap = r600_translate_colorswap(pipe_format, false);
2956
2957 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
2958 } else {
2959 /* The last dword is unused by hw. The shader uses it to clear
2960 * bits in the first dword of sampler state.
2961 */
2962 if (screen->b.chip_class <= CIK && res->nr_samples <= 1) {
2963 if (first_level == last_level)
2964 state[7] = C_008F30_MAX_ANISO_RATIO;
2965 else
2966 state[7] = 0xffffffff;
2967 }
2968 }
2969
2970 /* Initialize the sampler view for FMASK. */
2971 if (tex->fmask.size) {
2972 uint32_t fmask_format;
2973
2974 va = tex->resource.gpu_address + tex->fmask.offset;
2975
2976 switch (res->nr_samples) {
2977 case 2:
2978 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
2979 break;
2980 case 4:
2981 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
2982 break;
2983 case 8:
2984 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
2985 break;
2986 default:
2987 assert(0);
2988 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
2989 }
2990
2991 fmask_state[0] = va >> 8;
2992 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
2993 S_008F14_DATA_FORMAT(fmask_format) |
2994 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT);
2995 fmask_state[2] = S_008F18_WIDTH(width - 1) |
2996 S_008F18_HEIGHT(height - 1);
2997 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
2998 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
2999 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3000 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3001 S_008F1C_TILING_INDEX(tex->fmask.tile_mode_index) |
3002 S_008F1C_TYPE(si_tex_dim(res->target, target, 0));
3003 fmask_state[4] = S_008F20_DEPTH(depth - 1) |
3004 S_008F20_PITCH(tex->fmask.pitch_in_pixels - 1);
3005 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer) |
3006 S_008F24_LAST_ARRAY(last_layer);
3007 fmask_state[6] = 0;
3008 fmask_state[7] = 0;
3009 }
3010 }
3011
3012 /**
3013 * Create a sampler view.
3014 *
3015 * @param ctx context
3016 * @param texture texture
3017 * @param state sampler view template
3018 * @param width0 width0 override (for compressed textures as int)
3019 * @param height0 height0 override (for compressed textures as int)
3020 * @param force_level set the base address to the level (for compressed textures)
3021 */
3022 struct pipe_sampler_view *
3023 si_create_sampler_view_custom(struct pipe_context *ctx,
3024 struct pipe_resource *texture,
3025 const struct pipe_sampler_view *state,
3026 unsigned width0, unsigned height0,
3027 unsigned force_level)
3028 {
3029 struct si_context *sctx = (struct si_context*)ctx;
3030 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
3031 struct r600_texture *tmp = (struct r600_texture*)texture;
3032 unsigned base_level, first_level, last_level;
3033 unsigned char state_swizzle[4];
3034 unsigned height, depth, width;
3035 unsigned last_layer = state->u.tex.last_layer;
3036 enum pipe_format pipe_format;
3037 const struct radeon_surf_level *surflevel;
3038
3039 if (!view)
3040 return NULL;
3041
3042 /* initialize base object */
3043 view->base = *state;
3044 view->base.texture = NULL;
3045 view->base.reference.count = 1;
3046 view->base.context = ctx;
3047
3048 assert(texture);
3049 pipe_resource_reference(&view->base.texture, texture);
3050
3051 if (state->format == PIPE_FORMAT_X24S8_UINT ||
3052 state->format == PIPE_FORMAT_S8X24_UINT ||
3053 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
3054 state->format == PIPE_FORMAT_S8_UINT)
3055 view->is_stencil_sampler = true;
3056
3057 /* Buffer resource. */
3058 if (texture->target == PIPE_BUFFER) {
3059 si_make_buffer_descriptor(sctx->screen,
3060 (struct r600_resource *)texture,
3061 state->format,
3062 state->u.buf.offset,
3063 state->u.buf.size,
3064 view->state);
3065 return &view->base;
3066 }
3067
3068 state_swizzle[0] = state->swizzle_r;
3069 state_swizzle[1] = state->swizzle_g;
3070 state_swizzle[2] = state->swizzle_b;
3071 state_swizzle[3] = state->swizzle_a;
3072
3073 base_level = 0;
3074 first_level = state->u.tex.first_level;
3075 last_level = state->u.tex.last_level;
3076 width = width0;
3077 height = height0;
3078 depth = texture->depth0;
3079
3080 if (force_level) {
3081 assert(force_level == first_level &&
3082 force_level == last_level);
3083 base_level = force_level;
3084 first_level = 0;
3085 last_level = 0;
3086 width = u_minify(width, force_level);
3087 height = u_minify(height, force_level);
3088 depth = u_minify(depth, force_level);
3089 }
3090
3091 /* This is not needed if state trackers set last_layer correctly. */
3092 if (state->target == PIPE_TEXTURE_1D ||
3093 state->target == PIPE_TEXTURE_2D ||
3094 state->target == PIPE_TEXTURE_RECT ||
3095 state->target == PIPE_TEXTURE_CUBE)
3096 last_layer = state->u.tex.first_layer;
3097
3098 /* Texturing with separate depth and stencil. */
3099 pipe_format = state->format;
3100
3101 /* Depth/stencil texturing sometimes needs separate texture. */
3102 if (tmp->is_depth && !r600_can_sample_zs(tmp, view->is_stencil_sampler)) {
3103 if (!tmp->flushed_depth_texture &&
3104 !r600_init_flushed_depth_texture(ctx, texture, NULL)) {
3105 pipe_resource_reference(&view->base.texture, NULL);
3106 FREE(view);
3107 return NULL;
3108 }
3109
3110 assert(tmp->flushed_depth_texture);
3111
3112 /* Override format for the case where the flushed texture
3113 * contains only Z or only S.
3114 */
3115 if (tmp->flushed_depth_texture->resource.b.b.format != tmp->resource.b.b.format)
3116 pipe_format = tmp->flushed_depth_texture->resource.b.b.format;
3117
3118 tmp = tmp->flushed_depth_texture;
3119 }
3120
3121 surflevel = tmp->surface.level;
3122
3123 if (tmp->db_compatible) {
3124 if (!view->is_stencil_sampler)
3125 pipe_format = tmp->db_render_format;
3126
3127 switch (pipe_format) {
3128 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
3129 pipe_format = PIPE_FORMAT_Z32_FLOAT;
3130 break;
3131 case PIPE_FORMAT_X8Z24_UNORM:
3132 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3133 /* Z24 is always stored like this for DB
3134 * compatibility.
3135 */
3136 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
3137 break;
3138 case PIPE_FORMAT_X24S8_UINT:
3139 case PIPE_FORMAT_S8X24_UINT:
3140 case PIPE_FORMAT_X32_S8X24_UINT:
3141 pipe_format = PIPE_FORMAT_S8_UINT;
3142 surflevel = tmp->surface.stencil_level;
3143 break;
3144 default:;
3145 }
3146 }
3147
3148 vi_dcc_disable_if_incompatible_format(&sctx->b, texture,
3149 state->u.tex.first_level,
3150 state->format);
3151
3152 si_make_texture_descriptor(sctx->screen, tmp, true,
3153 state->target, pipe_format, state_swizzle,
3154 first_level, last_level,
3155 state->u.tex.first_layer, last_layer,
3156 width, height, depth,
3157 view->state, view->fmask_state);
3158
3159 view->base_level_info = &surflevel[base_level];
3160 view->base_level = base_level;
3161 view->block_width = util_format_get_blockwidth(pipe_format);
3162 return &view->base;
3163 }
3164
3165 static struct pipe_sampler_view *
3166 si_create_sampler_view(struct pipe_context *ctx,
3167 struct pipe_resource *texture,
3168 const struct pipe_sampler_view *state)
3169 {
3170 return si_create_sampler_view_custom(ctx, texture, state,
3171 texture ? texture->width0 : 0,
3172 texture ? texture->height0 : 0, 0);
3173 }
3174
3175 static void si_sampler_view_destroy(struct pipe_context *ctx,
3176 struct pipe_sampler_view *state)
3177 {
3178 struct si_sampler_view *view = (struct si_sampler_view *)state;
3179
3180 pipe_resource_reference(&state->texture, NULL);
3181 FREE(view);
3182 }
3183
3184 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
3185 {
3186 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
3187 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
3188 (linear_filter &&
3189 (wrap == PIPE_TEX_WRAP_CLAMP ||
3190 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
3191 }
3192
3193 static bool sampler_state_needs_border_color(const struct pipe_sampler_state *state)
3194 {
3195 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
3196 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
3197
3198 return (state->border_color.ui[0] || state->border_color.ui[1] ||
3199 state->border_color.ui[2] || state->border_color.ui[3]) &&
3200 (wrap_mode_uses_border_color(state->wrap_s, linear_filter) ||
3201 wrap_mode_uses_border_color(state->wrap_t, linear_filter) ||
3202 wrap_mode_uses_border_color(state->wrap_r, linear_filter));
3203 }
3204
3205 static void *si_create_sampler_state(struct pipe_context *ctx,
3206 const struct pipe_sampler_state *state)
3207 {
3208 struct si_context *sctx = (struct si_context *)ctx;
3209 struct r600_common_screen *rscreen = sctx->b.screen;
3210 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
3211 unsigned border_color_type, border_color_index = 0;
3212 unsigned max_aniso = rscreen->force_aniso >= 0 ? rscreen->force_aniso
3213 : state->max_anisotropy;
3214 unsigned max_aniso_ratio = r600_tex_aniso_filter(max_aniso);
3215
3216 if (!rstate) {
3217 return NULL;
3218 }
3219
3220 if (!sampler_state_needs_border_color(state))
3221 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3222 else if (state->border_color.f[0] == 0 &&
3223 state->border_color.f[1] == 0 &&
3224 state->border_color.f[2] == 0 &&
3225 state->border_color.f[3] == 0)
3226 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3227 else if (state->border_color.f[0] == 0 &&
3228 state->border_color.f[1] == 0 &&
3229 state->border_color.f[2] == 0 &&
3230 state->border_color.f[3] == 1)
3231 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3232 else if (state->border_color.f[0] == 1 &&
3233 state->border_color.f[1] == 1 &&
3234 state->border_color.f[2] == 1 &&
3235 state->border_color.f[3] == 1)
3236 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3237 else {
3238 int i;
3239
3240 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
3241
3242 /* Check if the border has been uploaded already. */
3243 for (i = 0; i < sctx->border_color_count; i++)
3244 if (memcmp(&sctx->border_color_table[i], &state->border_color,
3245 sizeof(state->border_color)) == 0)
3246 break;
3247
3248 if (i >= SI_MAX_BORDER_COLORS) {
3249 /* Getting 4096 unique border colors is very unlikely. */
3250 fprintf(stderr, "radeonsi: The border color table is full. "
3251 "Any new border colors will be just black. "
3252 "Please file a bug.\n");
3253 border_color_type = V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3254 } else {
3255 if (i == sctx->border_color_count) {
3256 /* Upload a new border color. */
3257 memcpy(&sctx->border_color_table[i], &state->border_color,
3258 sizeof(state->border_color));
3259 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
3260 &state->border_color,
3261 sizeof(state->border_color));
3262 sctx->border_color_count++;
3263 }
3264
3265 border_color_index = i;
3266 }
3267 }
3268
3269 #ifdef DEBUG
3270 rstate->magic = SI_SAMPLER_STATE_MAGIC;
3271 #endif
3272 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
3273 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
3274 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
3275 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3276 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
3277 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
3278 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3279 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3280 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
3281 S_008F30_COMPAT_MODE(sctx->b.chip_class >= VI));
3282 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
3283 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
3284 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3285 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
3286 S_008F38_XY_MAG_FILTER(eg_tex_filter(state->mag_img_filter, max_aniso)) |
3287 S_008F38_XY_MIN_FILTER(eg_tex_filter(state->min_img_filter, max_aniso)) |
3288 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
3289 S_008F38_MIP_POINT_PRECLAMP(1) |
3290 S_008F38_DISABLE_LSB_CEIL(1) |
3291 S_008F38_FILTER_PREC_FIX(1) |
3292 S_008F38_ANISO_OVERRIDE(sctx->b.chip_class >= VI));
3293 rstate->val[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index) |
3294 S_008F3C_BORDER_COLOR_TYPE(border_color_type);
3295 return rstate;
3296 }
3297
3298 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
3299 {
3300 struct si_context *sctx = (struct si_context *)ctx;
3301
3302 if (sctx->sample_mask.sample_mask == (uint16_t)sample_mask)
3303 return;
3304
3305 sctx->sample_mask.sample_mask = sample_mask;
3306 si_mark_atom_dirty(sctx, &sctx->sample_mask.atom);
3307 }
3308
3309 static void si_emit_sample_mask(struct si_context *sctx, struct r600_atom *atom)
3310 {
3311 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
3312 unsigned mask = sctx->sample_mask.sample_mask;
3313
3314 /* Needed for line and polygon smoothing as well as for the Polaris
3315 * small primitive filter. We expect the state tracker to take care of
3316 * this for us.
3317 */
3318 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
3319 (mask & 1 && sctx->blitter->running));
3320
3321 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3322 radeon_emit(cs, mask | (mask << 16));
3323 radeon_emit(cs, mask | (mask << 16));
3324 }
3325
3326 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
3327 {
3328 #ifdef DEBUG
3329 struct si_sampler_state *s = state;
3330
3331 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
3332 s->magic = 0;
3333 #endif
3334 free(state);
3335 }
3336
3337 /*
3338 * Vertex elements & buffers
3339 */
3340
3341 static void *si_create_vertex_elements(struct pipe_context *ctx,
3342 unsigned count,
3343 const struct pipe_vertex_element *elements)
3344 {
3345 struct si_vertex_element *v = CALLOC_STRUCT(si_vertex_element);
3346 bool used[SI_NUM_VERTEX_BUFFERS] = {};
3347 int i;
3348
3349 assert(count <= SI_MAX_ATTRIBS);
3350 if (!v)
3351 return NULL;
3352
3353 v->count = count;
3354 for (i = 0; i < count; ++i) {
3355 const struct util_format_description *desc;
3356 const struct util_format_channel_description *channel;
3357 unsigned data_format, num_format;
3358 int first_non_void;
3359 unsigned vbo_index = elements[i].vertex_buffer_index;
3360
3361 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
3362 FREE(v);
3363 return NULL;
3364 }
3365
3366 if (!used[vbo_index]) {
3367 v->first_vb_use_mask |= 1 << i;
3368 used[vbo_index] = true;
3369 }
3370
3371 desc = util_format_description(elements[i].src_format);
3372 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
3373 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
3374 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
3375 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
3376
3377 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3378 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3379 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3380 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3381 S_008F0C_NUM_FORMAT(num_format) |
3382 S_008F0C_DATA_FORMAT(data_format);
3383 v->format_size[i] = desc->block.bits / 8;
3384
3385 /* The hardware always treats the 2-bit alpha channel as
3386 * unsigned, so a shader workaround is needed.
3387 */
3388 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10) {
3389 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
3390 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_A2_SNORM << (4 * i);
3391 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
3392 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_A2_SSCALED << (4 * i);
3393 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
3394 /* This isn't actually used in OpenGL. */
3395 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_A2_SINT << (4 * i);
3396 }
3397 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
3398 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3399 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBX_32_FIXED << (4 * i);
3400 else
3401 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBA_32_FIXED << (4 * i);
3402 } else if (channel && channel->size == 32 && !channel->pure_integer) {
3403 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
3404 if (channel->normalized) {
3405 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3406 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBX_32_SNORM << (4 * i);
3407 else
3408 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBA_32_SNORM << (4 * i);
3409 } else {
3410 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBA_32_SSCALED << (4 * i);
3411 }
3412 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
3413 if (channel->normalized) {
3414 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
3415 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBX_32_UNORM << (4 * i);
3416 else
3417 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBA_32_UNORM << (4 * i);
3418 } else {
3419 v->fix_fetch |= (uint64_t)SI_FIX_FETCH_RGBA_32_USCALED << (4 * i);
3420 }
3421 }
3422 }
3423
3424 /* We work around the fact that 8_8_8 and 16_16_16 data formats
3425 * do not exist by using the corresponding 4-component formats.
3426 * This requires a fixup of the descriptor for bounds checks.
3427 */
3428 if (desc->block.bits == 3 * 8 ||
3429 desc->block.bits == 3 * 16) {
3430 v->fix_size3 |= (desc->block.bits / 24) << (2 * i);
3431 }
3432 }
3433 memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
3434
3435 return v;
3436 }
3437
3438 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
3439 {
3440 struct si_context *sctx = (struct si_context *)ctx;
3441 struct si_vertex_element *v = (struct si_vertex_element*)state;
3442
3443 sctx->vertex_elements = v;
3444 sctx->vertex_buffers_dirty = true;
3445 sctx->do_update_shaders = true;
3446 }
3447
3448 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
3449 {
3450 struct si_context *sctx = (struct si_context *)ctx;
3451
3452 if (sctx->vertex_elements == state)
3453 sctx->vertex_elements = NULL;
3454 FREE(state);
3455 }
3456
3457 static void si_set_vertex_buffers(struct pipe_context *ctx,
3458 unsigned start_slot, unsigned count,
3459 const struct pipe_vertex_buffer *buffers)
3460 {
3461 struct si_context *sctx = (struct si_context *)ctx;
3462 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
3463 int i;
3464
3465 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
3466
3467 if (buffers) {
3468 for (i = 0; i < count; i++) {
3469 const struct pipe_vertex_buffer *src = buffers + i;
3470 struct pipe_vertex_buffer *dsti = dst + i;
3471 struct pipe_resource *buf = src->buffer;
3472
3473 pipe_resource_reference(&dsti->buffer, buf);
3474 dsti->buffer_offset = src->buffer_offset;
3475 dsti->stride = src->stride;
3476 r600_context_add_resource_size(ctx, buf);
3477 if (buf)
3478 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
3479 }
3480 } else {
3481 for (i = 0; i < count; i++) {
3482 pipe_resource_reference(&dst[i].buffer, NULL);
3483 }
3484 }
3485 sctx->vertex_buffers_dirty = true;
3486 }
3487
3488 static void si_set_index_buffer(struct pipe_context *ctx,
3489 const struct pipe_index_buffer *ib)
3490 {
3491 struct si_context *sctx = (struct si_context *)ctx;
3492
3493 if (ib) {
3494 struct pipe_resource *buf = ib->buffer;
3495
3496 pipe_resource_reference(&sctx->index_buffer.buffer, buf);
3497 memcpy(&sctx->index_buffer, ib, sizeof(*ib));
3498 r600_context_add_resource_size(ctx, buf);
3499 if (buf)
3500 r600_resource(buf)->bind_history |= PIPE_BIND_INDEX_BUFFER;
3501 } else {
3502 pipe_resource_reference(&sctx->index_buffer.buffer, NULL);
3503 }
3504 }
3505
3506 /*
3507 * Misc
3508 */
3509
3510 static void si_set_tess_state(struct pipe_context *ctx,
3511 const float default_outer_level[4],
3512 const float default_inner_level[2])
3513 {
3514 struct si_context *sctx = (struct si_context *)ctx;
3515 struct pipe_constant_buffer cb;
3516 float array[8];
3517
3518 memcpy(array, default_outer_level, sizeof(float) * 4);
3519 memcpy(array+4, default_inner_level, sizeof(float) * 2);
3520
3521 cb.buffer = NULL;
3522 cb.user_buffer = NULL;
3523 cb.buffer_size = sizeof(array);
3524
3525 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
3526 (void*)array, sizeof(array),
3527 &cb.buffer_offset);
3528
3529 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
3530 pipe_resource_reference(&cb.buffer, NULL);
3531 }
3532
3533 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
3534 {
3535 struct si_context *sctx = (struct si_context *)ctx;
3536
3537 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1 |
3538 SI_CONTEXT_INV_GLOBAL_L2 |
3539 SI_CONTEXT_FLUSH_AND_INV_CB;
3540 sctx->framebuffer.do_update_surf_dirtiness = true;
3541 }
3542
3543 /* This only ensures coherency for shader image/buffer stores. */
3544 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
3545 {
3546 struct si_context *sctx = (struct si_context *)ctx;
3547
3548 /* Subsequent commands must wait for all shader invocations to
3549 * complete. */
3550 sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
3551 SI_CONTEXT_CS_PARTIAL_FLUSH;
3552
3553 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
3554 sctx->b.flags |= SI_CONTEXT_INV_SMEM_L1 |
3555 SI_CONTEXT_INV_VMEM_L1;
3556
3557 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
3558 PIPE_BARRIER_SHADER_BUFFER |
3559 PIPE_BARRIER_TEXTURE |
3560 PIPE_BARRIER_IMAGE |
3561 PIPE_BARRIER_STREAMOUT_BUFFER |
3562 PIPE_BARRIER_GLOBAL_BUFFER)) {
3563 /* As far as I can tell, L1 contents are written back to L2
3564 * automatically at end of shader, but the contents of other
3565 * L1 caches might still be stale. */
3566 sctx->b.flags |= SI_CONTEXT_INV_VMEM_L1;
3567 }
3568
3569 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
3570 /* Indices are read through TC L2 since VI.
3571 * L1 isn't used.
3572 */
3573 if (sctx->screen->b.chip_class <= CIK)
3574 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3575 }
3576
3577 if (flags & PIPE_BARRIER_FRAMEBUFFER)
3578 sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_CB |
3579 SI_CONTEXT_FLUSH_AND_INV_DB;
3580
3581 if (flags & (PIPE_BARRIER_FRAMEBUFFER |
3582 PIPE_BARRIER_INDIRECT_BUFFER))
3583 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
3584 }
3585
3586 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
3587 {
3588 struct pipe_blend_state blend;
3589
3590 memset(&blend, 0, sizeof(blend));
3591 blend.independent_blend_enable = true;
3592 blend.rt[0].colormask = 0xf;
3593 return si_create_blend_state_mode(&sctx->b.b, &blend, mode);
3594 }
3595
3596 static void si_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
3597 bool include_draw_vbo)
3598 {
3599 si_need_cs_space((struct si_context*)ctx);
3600 }
3601
3602 static void si_init_config(struct si_context *sctx);
3603
3604 void si_init_state_functions(struct si_context *sctx)
3605 {
3606 si_init_external_atom(sctx, &sctx->b.render_cond_atom, &sctx->atoms.s.render_cond);
3607 si_init_external_atom(sctx, &sctx->b.streamout.begin_atom, &sctx->atoms.s.streamout_begin);
3608 si_init_external_atom(sctx, &sctx->b.streamout.enable_atom, &sctx->atoms.s.streamout_enable);
3609 si_init_external_atom(sctx, &sctx->b.scissors.atom, &sctx->atoms.s.scissors);
3610 si_init_external_atom(sctx, &sctx->b.viewports.atom, &sctx->atoms.s.viewports);
3611
3612 si_init_atom(sctx, &sctx->framebuffer.atom, &sctx->atoms.s.framebuffer, si_emit_framebuffer_state);
3613 si_init_atom(sctx, &sctx->msaa_sample_locs.atom, &sctx->atoms.s.msaa_sample_locs, si_emit_msaa_sample_locs);
3614 si_init_atom(sctx, &sctx->db_render_state, &sctx->atoms.s.db_render_state, si_emit_db_render_state);
3615 si_init_atom(sctx, &sctx->msaa_config, &sctx->atoms.s.msaa_config, si_emit_msaa_config);
3616 si_init_atom(sctx, &sctx->sample_mask.atom, &sctx->atoms.s.sample_mask, si_emit_sample_mask);
3617 si_init_atom(sctx, &sctx->cb_render_state, &sctx->atoms.s.cb_render_state, si_emit_cb_render_state);
3618 si_init_atom(sctx, &sctx->blend_color.atom, &sctx->atoms.s.blend_color, si_emit_blend_color);
3619 si_init_atom(sctx, &sctx->clip_regs, &sctx->atoms.s.clip_regs, si_emit_clip_regs);
3620 si_init_atom(sctx, &sctx->clip_state.atom, &sctx->atoms.s.clip_state, si_emit_clip_state);
3621 si_init_atom(sctx, &sctx->stencil_ref.atom, &sctx->atoms.s.stencil_ref, si_emit_stencil_ref);
3622
3623 sctx->b.b.create_blend_state = si_create_blend_state;
3624 sctx->b.b.bind_blend_state = si_bind_blend_state;
3625 sctx->b.b.delete_blend_state = si_delete_blend_state;
3626 sctx->b.b.set_blend_color = si_set_blend_color;
3627
3628 sctx->b.b.create_rasterizer_state = si_create_rs_state;
3629 sctx->b.b.bind_rasterizer_state = si_bind_rs_state;
3630 sctx->b.b.delete_rasterizer_state = si_delete_rs_state;
3631
3632 sctx->b.b.create_depth_stencil_alpha_state = si_create_dsa_state;
3633 sctx->b.b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
3634 sctx->b.b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
3635
3636 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
3637 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
3638 sctx->custom_blend_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
3639 sctx->custom_blend_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
3640 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
3641
3642 sctx->b.b.set_clip_state = si_set_clip_state;
3643 sctx->b.b.set_stencil_ref = si_set_stencil_ref;
3644
3645 sctx->b.b.set_framebuffer_state = si_set_framebuffer_state;
3646 sctx->b.b.get_sample_position = cayman_get_sample_position;
3647
3648 sctx->b.b.create_sampler_state = si_create_sampler_state;
3649 sctx->b.b.delete_sampler_state = si_delete_sampler_state;
3650
3651 sctx->b.b.create_sampler_view = si_create_sampler_view;
3652 sctx->b.b.sampler_view_destroy = si_sampler_view_destroy;
3653
3654 sctx->b.b.set_sample_mask = si_set_sample_mask;
3655
3656 sctx->b.b.create_vertex_elements_state = si_create_vertex_elements;
3657 sctx->b.b.bind_vertex_elements_state = si_bind_vertex_elements;
3658 sctx->b.b.delete_vertex_elements_state = si_delete_vertex_element;
3659 sctx->b.b.set_vertex_buffers = si_set_vertex_buffers;
3660 sctx->b.b.set_index_buffer = si_set_index_buffer;
3661
3662 sctx->b.b.texture_barrier = si_texture_barrier;
3663 sctx->b.b.memory_barrier = si_memory_barrier;
3664 sctx->b.b.set_min_samples = si_set_min_samples;
3665 sctx->b.b.set_tess_state = si_set_tess_state;
3666
3667 sctx->b.b.set_active_query_state = si_set_active_query_state;
3668 sctx->b.set_occlusion_query_state = si_set_occlusion_query_state;
3669 sctx->b.save_qbo_state = si_save_qbo_state;
3670 sctx->b.need_gfx_cs_space = si_need_gfx_cs_space;
3671
3672 sctx->b.b.draw_vbo = si_draw_vbo;
3673
3674 si_init_config(sctx);
3675 }
3676
3677 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen *rscreen)
3678 {
3679 return (ATI_VENDOR_ID << 16) | rscreen->info.pci_id;
3680 }
3681
3682 static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
3683 struct r600_texture *rtex,
3684 struct radeon_bo_metadata *md)
3685 {
3686 struct si_screen *sscreen = (struct si_screen*)rscreen;
3687 struct pipe_resource *res = &rtex->resource.b.b;
3688 static const unsigned char swizzle[] = {
3689 PIPE_SWIZZLE_X,
3690 PIPE_SWIZZLE_Y,
3691 PIPE_SWIZZLE_Z,
3692 PIPE_SWIZZLE_W
3693 };
3694 uint32_t desc[8], i;
3695 bool is_array = util_resource_is_array_texture(res);
3696
3697 /* DRM 2.x.x doesn't support this. */
3698 if (rscreen->info.drm_major != 3)
3699 return;
3700
3701 assert(rtex->dcc_separate_buffer == NULL);
3702 assert(rtex->fmask.size == 0);
3703
3704 /* Metadata image format format version 1:
3705 * [0] = 1 (metadata format identifier)
3706 * [1] = (VENDOR_ID << 16) | PCI_ID
3707 * [2:9] = image descriptor for the whole resource
3708 * [2] is always 0, because the base address is cleared
3709 * [9] is the DCC offset bits [39:8] from the beginning of
3710 * the buffer
3711 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3712 */
3713
3714 md->metadata[0] = 1; /* metadata image format version 1 */
3715
3716 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3717 md->metadata[1] = si_get_bo_metadata_word1(rscreen);
3718
3719 si_make_texture_descriptor(sscreen, rtex, true,
3720 res->target, res->format,
3721 swizzle, 0, res->last_level, 0,
3722 is_array ? res->array_size - 1 : 0,
3723 res->width0, res->height0, res->depth0,
3724 desc, NULL);
3725
3726 si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
3727 rtex->surface.blk_w, false, desc);
3728
3729 /* Clear the base address and set the relative DCC offset. */
3730 desc[0] = 0;
3731 desc[1] &= C_008F14_BASE_ADDRESS_HI;
3732 desc[7] = rtex->dcc_offset >> 8;
3733
3734 /* Dwords [2:9] contain the image descriptor. */
3735 memcpy(&md->metadata[2], desc, sizeof(desc));
3736
3737 /* Dwords [10:..] contain the mipmap level offsets. */
3738 for (i = 0; i <= res->last_level; i++)
3739 md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
3740
3741 md->size_metadata = (11 + res->last_level) * 4;
3742 }
3743
3744 static void si_apply_opaque_metadata(struct r600_common_screen *rscreen,
3745 struct r600_texture *rtex,
3746 struct radeon_bo_metadata *md)
3747 {
3748 uint32_t *desc = &md->metadata[2];
3749
3750 if (rscreen->chip_class < VI)
3751 return;
3752
3753 /* Return if DCC is enabled. The texture should be set up with it
3754 * already.
3755 */
3756 if (md->size_metadata >= 11 * 4 &&
3757 md->metadata[0] != 0 &&
3758 md->metadata[1] == si_get_bo_metadata_word1(rscreen) &&
3759 G_008F28_COMPRESSION_EN(desc[6])) {
3760 assert(rtex->dcc_offset == ((uint64_t)desc[7] << 8));
3761 return;
3762 }
3763
3764 /* Disable DCC. These are always set by texture_from_handle and must
3765 * be cleared here.
3766 */
3767 rtex->dcc_offset = 0;
3768 }
3769
3770 void si_init_screen_state_functions(struct si_screen *sscreen)
3771 {
3772 sscreen->b.b.is_format_supported = si_is_format_supported;
3773 sscreen->b.query_opaque_metadata = si_query_opaque_metadata;
3774 sscreen->b.apply_opaque_metadata = si_apply_opaque_metadata;
3775 }
3776
3777 static void
3778 si_write_harvested_raster_configs(struct si_context *sctx,
3779 struct si_pm4_state *pm4,
3780 unsigned raster_config,
3781 unsigned raster_config_1)
3782 {
3783 unsigned sh_per_se = MAX2(sctx->screen->b.info.max_sh_per_se, 1);
3784 unsigned num_se = MAX2(sctx->screen->b.info.max_se, 1);
3785 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3786 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3787 unsigned rb_per_pkr = MIN2(num_rb / num_se / sh_per_se, 2);
3788 unsigned rb_per_se = num_rb / num_se;
3789 unsigned se_mask[4];
3790 unsigned se;
3791
3792 se_mask[0] = ((1 << rb_per_se) - 1);
3793 se_mask[1] = (se_mask[0] << rb_per_se);
3794 se_mask[2] = (se_mask[1] << rb_per_se);
3795 se_mask[3] = (se_mask[2] << rb_per_se);
3796
3797 se_mask[0] &= rb_mask;
3798 se_mask[1] &= rb_mask;
3799 se_mask[2] &= rb_mask;
3800 se_mask[3] &= rb_mask;
3801
3802 assert(num_se == 1 || num_se == 2 || num_se == 4);
3803 assert(sh_per_se == 1 || sh_per_se == 2);
3804 assert(rb_per_pkr == 1 || rb_per_pkr == 2);
3805
3806 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3807 * fields are for, so I'm leaving them as their default
3808 * values. */
3809
3810 for (se = 0; se < num_se; se++) {
3811 unsigned raster_config_se = raster_config;
3812 unsigned pkr0_mask = ((1 << rb_per_pkr) - 1) << (se * rb_per_se);
3813 unsigned pkr1_mask = pkr0_mask << rb_per_pkr;
3814 int idx = (se / 2) * 2;
3815
3816 if ((num_se > 1) && (!se_mask[idx] || !se_mask[idx + 1])) {
3817 raster_config_se &= C_028350_SE_MAP;
3818
3819 if (!se_mask[idx]) {
3820 raster_config_se |=
3821 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3);
3822 } else {
3823 raster_config_se |=
3824 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0);
3825 }
3826 }
3827
3828 pkr0_mask &= rb_mask;
3829 pkr1_mask &= rb_mask;
3830 if (rb_per_se > 2 && (!pkr0_mask || !pkr1_mask)) {
3831 raster_config_se &= C_028350_PKR_MAP;
3832
3833 if (!pkr0_mask) {
3834 raster_config_se |=
3835 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3);
3836 } else {
3837 raster_config_se |=
3838 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0);
3839 }
3840 }
3841
3842 if (rb_per_se >= 2) {
3843 unsigned rb0_mask = 1 << (se * rb_per_se);
3844 unsigned rb1_mask = rb0_mask << 1;
3845
3846 rb0_mask &= rb_mask;
3847 rb1_mask &= rb_mask;
3848 if (!rb0_mask || !rb1_mask) {
3849 raster_config_se &= C_028350_RB_MAP_PKR0;
3850
3851 if (!rb0_mask) {
3852 raster_config_se |=
3853 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3);
3854 } else {
3855 raster_config_se |=
3856 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0);
3857 }
3858 }
3859
3860 if (rb_per_se > 2) {
3861 rb0_mask = 1 << (se * rb_per_se + rb_per_pkr);
3862 rb1_mask = rb0_mask << 1;
3863 rb0_mask &= rb_mask;
3864 rb1_mask &= rb_mask;
3865 if (!rb0_mask || !rb1_mask) {
3866 raster_config_se &= C_028350_RB_MAP_PKR1;
3867
3868 if (!rb0_mask) {
3869 raster_config_se |=
3870 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3);
3871 } else {
3872 raster_config_se |=
3873 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0);
3874 }
3875 }
3876 }
3877 }
3878
3879 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3880 if (sctx->b.chip_class < CIK)
3881 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3882 SE_INDEX(se) | SH_BROADCAST_WRITES |
3883 INSTANCE_BROADCAST_WRITES);
3884 else
3885 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3886 S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) |
3887 S_030800_INSTANCE_BROADCAST_WRITES(1));
3888 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se);
3889 }
3890
3891 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3892 if (sctx->b.chip_class < CIK)
3893 si_pm4_set_reg(pm4, GRBM_GFX_INDEX,
3894 SE_BROADCAST_WRITES | SH_BROADCAST_WRITES |
3895 INSTANCE_BROADCAST_WRITES);
3896 else {
3897 si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX,
3898 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3899 S_030800_INSTANCE_BROADCAST_WRITES(1));
3900
3901 if ((num_se > 2) && ((!se_mask[0] && !se_mask[1]) ||
3902 (!se_mask[2] && !se_mask[3]))) {
3903 raster_config_1 &= C_028354_SE_PAIR_MAP;
3904
3905 if (!se_mask[0] && !se_mask[1]) {
3906 raster_config_1 |=
3907 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3);
3908 } else {
3909 raster_config_1 |=
3910 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0);
3911 }
3912 }
3913
3914 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
3915 }
3916 }
3917
3918 static void si_init_config(struct si_context *sctx)
3919 {
3920 struct si_screen *sscreen = sctx->screen;
3921 unsigned num_rb = MIN2(sctx->screen->b.info.num_render_backends, 16);
3922 unsigned rb_mask = sctx->screen->b.info.enabled_rb_mask;
3923 unsigned raster_config, raster_config_1;
3924 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
3925 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3926
3927 if (!pm4)
3928 return;
3929
3930 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
3931 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
3932 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3933 si_pm4_cmd_end(pm4, false);
3934
3935 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
3936 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
3937
3938 /* FIXME calculate these values somehow ??? */
3939 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
3940 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
3941 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
3942
3943 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
3944 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
3945
3946 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
3947 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
3948 if (sctx->b.chip_class < CIK)
3949 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
3950 S_008A14_CLIP_VTX_REORDER_ENA(1));
3951
3952 si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210);
3953 si_pm4_set_reg(pm4, R_028BD8_PA_SC_CENTROID_PRIORITY_1, 0xfedcba98);
3954
3955 si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
3956
3957 switch (sctx->screen->b.family) {
3958 case CHIP_TAHITI:
3959 case CHIP_PITCAIRN:
3960 raster_config = 0x2a00126a;
3961 raster_config_1 = 0x00000000;
3962 break;
3963 case CHIP_VERDE:
3964 raster_config = 0x0000124a;
3965 raster_config_1 = 0x00000000;
3966 break;
3967 case CHIP_OLAND:
3968 raster_config = 0x00000082;
3969 raster_config_1 = 0x00000000;
3970 break;
3971 case CHIP_HAINAN:
3972 raster_config = 0x00000000;
3973 raster_config_1 = 0x00000000;
3974 break;
3975 case CHIP_BONAIRE:
3976 raster_config = 0x16000012;
3977 raster_config_1 = 0x00000000;
3978 break;
3979 case CHIP_HAWAII:
3980 raster_config = 0x3a00161a;
3981 raster_config_1 = 0x0000002e;
3982 break;
3983 case CHIP_FIJI:
3984 if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x000000e8) {
3985 /* old kernels with old tiling config */
3986 raster_config = 0x16000012;
3987 raster_config_1 = 0x0000002a;
3988 } else {
3989 raster_config = 0x3a00161a;
3990 raster_config_1 = 0x0000002e;
3991 }
3992 break;
3993 case CHIP_POLARIS10:
3994 raster_config = 0x16000012;
3995 raster_config_1 = 0x0000002a;
3996 break;
3997 case CHIP_POLARIS11:
3998 case CHIP_POLARIS12:
3999 raster_config = 0x16000012;
4000 raster_config_1 = 0x00000000;
4001 break;
4002 case CHIP_TONGA:
4003 raster_config = 0x16000012;
4004 raster_config_1 = 0x0000002a;
4005 break;
4006 case CHIP_ICELAND:
4007 if (num_rb == 1)
4008 raster_config = 0x00000000;
4009 else
4010 raster_config = 0x00000002;
4011 raster_config_1 = 0x00000000;
4012 break;
4013 case CHIP_CARRIZO:
4014 raster_config = 0x00000002;
4015 raster_config_1 = 0x00000000;
4016 break;
4017 case CHIP_KAVERI:
4018 /* KV should be 0x00000002, but that causes problems with radeon */
4019 raster_config = 0x00000000; /* 0x00000002 */
4020 raster_config_1 = 0x00000000;
4021 break;
4022 case CHIP_KABINI:
4023 case CHIP_MULLINS:
4024 case CHIP_STONEY:
4025 raster_config = 0x00000000;
4026 raster_config_1 = 0x00000000;
4027 break;
4028 default:
4029 fprintf(stderr,
4030 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4031 raster_config = 0x00000000;
4032 raster_config_1 = 0x00000000;
4033 break;
4034 }
4035
4036 /* Always use the default config when all backends are enabled
4037 * (or when we failed to determine the enabled backends).
4038 */
4039 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4040 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4041 raster_config);
4042 if (sctx->b.chip_class >= CIK)
4043 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4044 raster_config_1);
4045 } else {
4046 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4047 }
4048
4049 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4050 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4051 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4052 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4053 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4054 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4055 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4056
4057 si_pm4_set_reg(pm4, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
4058 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4059 S_028230_ER_TRI(0xA) |
4060 S_028230_ER_POINT(0xA) |
4061 S_028230_ER_RECT(0xA) |
4062 /* Required by DX10_DIAMOND_TEST_ENA: */
4063 S_028230_ER_LINE_LR(0x1A) |
4064 S_028230_ER_LINE_RL(0x26) |
4065 S_028230_ER_LINE_TB(0xA) |
4066 S_028230_ER_LINE_BT(0xA));
4067 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4068 si_pm4_set_reg(pm4, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
4069 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4070 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4071 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4072 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4073 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4074
4075 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4076 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4077 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4078
4079 if (sctx->b.chip_class >= CIK) {
4080 /* If this is 0, Bonaire can hang even if GS isn't being used.
4081 * Other chips are unaffected. These are suboptimal values,
4082 * but we don't use on-chip GS.
4083 */
4084 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4085 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4086 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4087
4088 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
4089 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
4090 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
4091 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
4092
4093 if (sscreen->b.info.num_good_compute_units /
4094 (sscreen->b.info.max_se * sscreen->b.info.max_sh_per_se) <= 4) {
4095 /* Too few available compute units per SH. Disallowing
4096 * VS to run on CU0 could hurt us more than late VS
4097 * allocation would help.
4098 *
4099 * LATE_ALLOC_VS = 2 is the highest safe number.
4100 */
4101 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xffff));
4102 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(2));
4103 } else {
4104 /* Set LATE_ALLOC_VS == 31. It should be less than
4105 * the number of scratch waves. Limitations:
4106 * - VS can't execute on CU0.
4107 * - If HS writes outputs to LDS, LS can't execute on CU0.
4108 */
4109 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS, S_00B118_CU_EN(0xfffe));
4110 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS, S_00B11C_LIMIT(31));
4111 }
4112
4113 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
4114 }
4115
4116 if (sctx->b.chip_class >= VI) {
4117 unsigned vgt_tess_distribution;
4118
4119 si_pm4_set_reg(pm4, R_028424_CB_DCC_CONTROL,
4120 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4121 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4122 if (sctx->b.family < CHIP_POLARIS10)
4123 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 30);
4124 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 32);
4125
4126 vgt_tess_distribution =
4127 S_028B50_ACCUM_ISOLINE(32) |
4128 S_028B50_ACCUM_TRI(11) |
4129 S_028B50_ACCUM_QUAD(11) |
4130 S_028B50_DONUT_SPLIT(16);
4131
4132 /* Testing with Unigine Heaven extreme tesselation yielded best results
4133 * with TRAP_SPLIT = 3.
4134 */
4135 if (sctx->b.family == CHIP_FIJI ||
4136 sctx->b.family >= CHIP_POLARIS10)
4137 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4138
4139 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
4140 } else {
4141 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
4142 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
4143 }
4144
4145 if (sctx->b.family == CHIP_STONEY)
4146 si_pm4_set_reg(pm4, R_028C40_PA_SC_SHADER_CONTROL, 0);
4147
4148 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
4149 if (sctx->b.chip_class >= CIK)
4150 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, border_color_va >> 40);
4151 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
4152 RADEON_PRIO_BORDER_COLORS);
4153
4154 si_pm4_upload_indirect_buffer(sctx, pm4);
4155 sctx->init_config = pm4;
4156 }