2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Christian König <christian.koenig@amd.com>
29 #include "radeon/r600_cs.h"
30 #include "radeon/r600_query.h"
32 #include "util/u_dual_blend.h"
33 #include "util/u_format.h"
34 #include "util/u_format_s3tc.h"
35 #include "util/u_memory.h"
36 #include "util/u_resource.h"
38 /* Initialize an external atom (owned by ../radeon). */
40 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
41 struct r600_atom
**list_elem
)
43 atom
->id
= list_elem
- sctx
->atoms
.array
;
47 /* Initialize an atom owned by radeonsi. */
48 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
49 struct r600_atom
**list_elem
,
50 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
52 atom
->emit
= (void*)emit_func
;
53 atom
->id
= list_elem
- sctx
->atoms
.array
;
57 static unsigned si_map_swizzle(unsigned swizzle
)
61 return V_008F0C_SQ_SEL_Y
;
63 return V_008F0C_SQ_SEL_Z
;
65 return V_008F0C_SQ_SEL_W
;
67 return V_008F0C_SQ_SEL_0
;
69 return V_008F0C_SQ_SEL_1
;
70 default: /* PIPE_SWIZZLE_X */
71 return V_008F0C_SQ_SEL_X
;
75 static uint32_t S_FIXED(float value
, uint32_t frac_bits
)
77 return value
* (1 << frac_bits
);
80 /* 12.4 fixed-point */
81 static unsigned si_pack_float_12p4(float x
)
84 x
>= 4096 ? 0xffff : x
* 16;
88 * Inferred framebuffer and blender state.
90 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
91 * if there is not enough PS outputs.
93 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
95 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
96 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
97 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
98 * but you never know. */
99 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
103 cb_target_mask
&= blend
->cb_target_mask
;
105 /* Avoid a hang that happens when dual source blending is enabled
106 * but there is not enough color outputs. This is undefined behavior,
107 * so disable color writes completely.
109 * Reproducible with Unigine Heaven 4.0 and drirc missing.
111 if (blend
&& blend
->dual_src_blend
&&
112 sctx
->ps_shader
.cso
&&
113 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
116 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
118 /* STONEY-specific register settings. */
119 if (sctx
->b
.family
== CHIP_STONEY
) {
120 unsigned spi_shader_col_format
=
121 sctx
->ps_shader
.cso
?
122 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
123 unsigned sx_ps_downconvert
= 0;
124 unsigned sx_blend_opt_epsilon
= 0;
125 unsigned sx_blend_opt_control
= 0;
127 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
128 struct r600_surface
*surf
=
129 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
130 unsigned format
, swap
, spi_format
, colormask
;
131 bool has_alpha
, has_rgb
;
136 format
= G_028C70_FORMAT(surf
->cb_color_info
);
137 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
138 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
139 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
141 /* Set if RGB and A are present. */
142 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
144 if (format
== V_028C70_COLOR_8
||
145 format
== V_028C70_COLOR_16
||
146 format
== V_028C70_COLOR_32
)
147 has_rgb
= !has_alpha
;
151 /* Check the colormask and export format. */
152 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
154 if (!(colormask
& PIPE_MASK_A
))
157 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
162 /* Disable value checking for disabled channels. */
164 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
166 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
168 /* Enable down-conversion for 32bpp and smaller formats. */
170 case V_028C70_COLOR_8
:
171 case V_028C70_COLOR_8_8
:
172 case V_028C70_COLOR_8_8_8_8
:
173 /* For 1 and 2-channel formats, use the superset thereof. */
174 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
175 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
176 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
177 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
178 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
182 case V_028C70_COLOR_5_6_5
:
183 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
184 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
185 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
189 case V_028C70_COLOR_1_5_5_5
:
190 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
191 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
192 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
196 case V_028C70_COLOR_4_4_4_4
:
197 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
198 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
199 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
203 case V_028C70_COLOR_32
:
204 if (swap
== V_0280A0_SWAP_STD
&&
205 spi_format
== V_028714_SPI_SHADER_32_R
)
206 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
207 else if (swap
== V_0280A0_SWAP_ALT_REV
&&
208 spi_format
== V_028714_SPI_SHADER_32_AR
)
209 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
212 case V_028C70_COLOR_16
:
213 case V_028C70_COLOR_16_16
:
214 /* For 1-channel formats, use the superset thereof. */
215 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
216 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
217 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
218 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
219 if (swap
== V_0280A0_SWAP_STD
||
220 swap
== V_0280A0_SWAP_STD_REV
)
221 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
223 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
227 case V_028C70_COLOR_10_11_11
:
228 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
229 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
230 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
234 case V_028C70_COLOR_2_10_10_10
:
235 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
236 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
237 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
243 if (sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
) {
244 sx_ps_downconvert
= 0;
245 sx_blend_opt_epsilon
= 0;
246 sx_blend_opt_control
= 0;
249 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
250 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
251 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
252 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
260 static uint32_t si_translate_blend_function(int blend_func
)
262 switch (blend_func
) {
264 return V_028780_COMB_DST_PLUS_SRC
;
265 case PIPE_BLEND_SUBTRACT
:
266 return V_028780_COMB_SRC_MINUS_DST
;
267 case PIPE_BLEND_REVERSE_SUBTRACT
:
268 return V_028780_COMB_DST_MINUS_SRC
;
270 return V_028780_COMB_MIN_DST_SRC
;
272 return V_028780_COMB_MAX_DST_SRC
;
274 R600_ERR("Unknown blend function %d\n", blend_func
);
281 static uint32_t si_translate_blend_factor(int blend_fact
)
283 switch (blend_fact
) {
284 case PIPE_BLENDFACTOR_ONE
:
285 return V_028780_BLEND_ONE
;
286 case PIPE_BLENDFACTOR_SRC_COLOR
:
287 return V_028780_BLEND_SRC_COLOR
;
288 case PIPE_BLENDFACTOR_SRC_ALPHA
:
289 return V_028780_BLEND_SRC_ALPHA
;
290 case PIPE_BLENDFACTOR_DST_ALPHA
:
291 return V_028780_BLEND_DST_ALPHA
;
292 case PIPE_BLENDFACTOR_DST_COLOR
:
293 return V_028780_BLEND_DST_COLOR
;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
296 case PIPE_BLENDFACTOR_CONST_COLOR
:
297 return V_028780_BLEND_CONSTANT_COLOR
;
298 case PIPE_BLENDFACTOR_CONST_ALPHA
:
299 return V_028780_BLEND_CONSTANT_ALPHA
;
300 case PIPE_BLENDFACTOR_ZERO
:
301 return V_028780_BLEND_ZERO
;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
314 case PIPE_BLENDFACTOR_SRC1_COLOR
:
315 return V_028780_BLEND_SRC1_COLOR
;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
317 return V_028780_BLEND_SRC1_ALPHA
;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
319 return V_028780_BLEND_INV_SRC1_COLOR
;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
321 return V_028780_BLEND_INV_SRC1_ALPHA
;
323 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
330 static uint32_t si_translate_blend_opt_function(int blend_func
)
332 switch (blend_func
) {
334 return V_028760_OPT_COMB_ADD
;
335 case PIPE_BLEND_SUBTRACT
:
336 return V_028760_OPT_COMB_SUBTRACT
;
337 case PIPE_BLEND_REVERSE_SUBTRACT
:
338 return V_028760_OPT_COMB_REVSUBTRACT
;
340 return V_028760_OPT_COMB_MIN
;
342 return V_028760_OPT_COMB_MAX
;
344 return V_028760_OPT_COMB_BLEND_DISABLED
;
348 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
350 switch (blend_fact
) {
351 case PIPE_BLENDFACTOR_ZERO
:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
353 case PIPE_BLENDFACTOR_ONE
:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
355 case PIPE_BLENDFACTOR_SRC_COLOR
:
356 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
359 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
361 case PIPE_BLENDFACTOR_SRC_ALPHA
:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
366 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
374 * Get rid of DST in the blend factors by commuting the operands:
375 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
377 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
378 unsigned *dst_factor
, unsigned expected_dst
,
379 unsigned replacement_src
)
381 if (*src_factor
== expected_dst
&&
382 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
383 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
384 *dst_factor
= replacement_src
;
386 /* Commuting the operands requires reversing subtractions. */
387 if (*func
== PIPE_BLEND_SUBTRACT
)
388 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
389 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
390 *func
= PIPE_BLEND_SUBTRACT
;
394 static bool si_blend_factor_uses_dst(unsigned factor
)
396 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
397 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
398 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
399 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
400 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
403 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
404 const struct pipe_blend_state
*state
,
407 struct si_context
*sctx
= (struct si_context
*)ctx
;
408 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
409 struct si_pm4_state
*pm4
= &blend
->pm4
;
410 uint32_t sx_mrt_blend_opt
[8] = {0};
411 uint32_t color_control
= 0;
416 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
417 blend
->alpha_to_one
= state
->alpha_to_one
;
418 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
420 if (state
->logicop_enable
) {
421 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
423 color_control
|= S_028808_ROP3(0xcc);
426 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
427 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
428 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
429 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
430 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
431 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
433 if (state
->alpha_to_coverage
)
434 blend
->need_src_alpha_4bit
|= 0xf;
436 blend
->cb_target_mask
= 0;
437 for (int i
= 0; i
< 8; i
++) {
438 /* state->rt entries > 0 only written if independent blending */
439 const int j
= state
->independent_blend_enable
? i
: 0;
441 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
442 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
443 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
444 unsigned eqA
= state
->rt
[j
].alpha_func
;
445 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
446 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
448 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
449 unsigned blend_cntl
= 0;
451 sx_mrt_blend_opt
[i
] =
452 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
453 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
455 /* Only set dual source blending for MRT0 to avoid a hang. */
456 if (i
>= 1 && blend
->dual_src_blend
) {
457 /* Vulkan does this for dual source blending. */
459 blend_cntl
|= S_028780_ENABLE(1);
461 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
465 /* Only addition and subtraction equations are supported with
466 * dual source blending.
468 if (blend
->dual_src_blend
&&
469 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
470 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
471 assert(!"Unsupported equation for dual source blending");
472 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
476 /* cb_render_state will disable unused ones */
477 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
479 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
480 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
484 /* Blending optimizations for Stoney.
485 * These transformations don't change the behavior.
487 * First, get rid of DST in the blend factors:
488 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
490 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
491 PIPE_BLENDFACTOR_DST_COLOR
,
492 PIPE_BLENDFACTOR_SRC_COLOR
);
493 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
494 PIPE_BLENDFACTOR_DST_COLOR
,
495 PIPE_BLENDFACTOR_SRC_COLOR
);
496 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
497 PIPE_BLENDFACTOR_DST_ALPHA
,
498 PIPE_BLENDFACTOR_SRC_ALPHA
);
500 /* Look up the ideal settings from tables. */
501 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
502 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
503 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
504 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
506 /* Handle interdependencies. */
507 if (si_blend_factor_uses_dst(srcRGB
))
508 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
509 if (si_blend_factor_uses_dst(srcA
))
510 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
512 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
513 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
514 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
515 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
516 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
518 /* Set the final value. */
519 sx_mrt_blend_opt
[i
] =
520 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
521 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
522 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
523 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
524 S_028760_ALPHA_DST_OPT(dstA_opt
) |
525 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
527 /* Set blend state. */
528 blend_cntl
|= S_028780_ENABLE(1);
529 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
530 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
531 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
533 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
534 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
535 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
536 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
537 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
539 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
541 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
543 /* This is only important for formats without alpha. */
544 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
545 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
546 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
547 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
548 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
549 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
550 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
553 if (blend
->cb_target_mask
) {
554 color_control
|= S_028808_MODE(mode
);
556 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
559 if (sctx
->b
.family
== CHIP_STONEY
) {
560 /* Disable RB+ blend optimizations for dual source blending.
563 if (blend
->dual_src_blend
) {
564 for (int i
= 0; i
< 8; i
++) {
565 sx_mrt_blend_opt
[i
] =
566 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
567 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
571 for (int i
= 0; i
< 8; i
++)
572 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
573 sx_mrt_blend_opt
[i
]);
575 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
576 if (blend
->dual_src_blend
|| state
->logicop_enable
||
577 mode
== V_028808_CB_RESOLVE
)
578 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
581 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
585 static void *si_create_blend_state(struct pipe_context
*ctx
,
586 const struct pipe_blend_state
*state
)
588 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
591 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
593 struct si_context
*sctx
= (struct si_context
*)ctx
;
594 si_pm4_bind_state(sctx
, blend
, (struct si_state_blend
*)state
);
595 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
596 sctx
->do_update_shaders
= true;
599 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
601 struct si_context
*sctx
= (struct si_context
*)ctx
;
602 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
605 static void si_set_blend_color(struct pipe_context
*ctx
,
606 const struct pipe_blend_color
*state
)
608 struct si_context
*sctx
= (struct si_context
*)ctx
;
610 if (memcmp(&sctx
->blend_color
.state
, state
, sizeof(*state
)) == 0)
613 sctx
->blend_color
.state
= *state
;
614 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
617 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
619 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
621 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
622 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
629 static void si_set_clip_state(struct pipe_context
*ctx
,
630 const struct pipe_clip_state
*state
)
632 struct si_context
*sctx
= (struct si_context
*)ctx
;
633 struct pipe_constant_buffer cb
;
635 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
638 sctx
->clip_state
.state
= *state
;
639 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
642 cb
.user_buffer
= state
->ucp
;
643 cb
.buffer_offset
= 0;
644 cb
.buffer_size
= 4*4*8;
645 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
646 pipe_resource_reference(&cb
.buffer
, NULL
);
649 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
651 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
653 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
654 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
657 #define SIX_BITS 0x3F
659 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
661 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
662 struct si_shader
*vs
= si_get_vs_state(sctx
);
663 struct tgsi_shader_info
*info
= si_get_vs_info(sctx
);
664 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
665 unsigned window_space
=
666 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
667 unsigned clipdist_mask
=
668 info
->writes_clipvertex
? SIX_BITS
: info
->clipdist_writemask
;
669 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
670 unsigned culldist_mask
= info
->culldist_writemask
<< info
->num_written_clipdistance
;
674 if (vs
->key
.opt
.hw_vs
.clip_disable
) {
675 assert(!info
->culldist_writemask
);
679 total_mask
= clipdist_mask
| culldist_mask
;
681 /* Clip distances on points have no effect, so need to be implemented
682 * as cull distances. This applies for the clipvertex case as well.
684 * Setting this for primitives other than points should have no adverse
687 clipdist_mask
&= rs
->clip_plane_enable
;
688 culldist_mask
|= clipdist_mask
;
690 misc_vec_ena
= info
->writes_psize
|| info
->writes_edgeflag
||
691 info
->writes_layer
|| info
->writes_viewport_index
;
693 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
694 S_02881C_USE_VTX_POINT_SIZE(info
->writes_psize
) |
695 S_02881C_USE_VTX_EDGE_FLAG(info
->writes_edgeflag
) |
696 S_02881C_USE_VTX_RENDER_TARGET_INDX(info
->writes_layer
) |
697 S_02881C_USE_VTX_VIEWPORT_INDX(info
->writes_viewport_index
) |
698 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
699 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
700 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
701 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
702 clipdist_mask
| (culldist_mask
<< 8));
703 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
704 rs
->pa_cl_clip_cntl
|
706 S_028810_CLIP_DISABLE(window_space
));
708 /* reuse needs to be set off if we write oViewport */
709 radeon_set_context_reg(cs
, R_028AB4_VGT_REUSE_OFF
,
710 S_028AB4_REUSE_OFF(info
->writes_viewport_index
));
714 * inferred state between framebuffer and rasterizer
716 static void si_update_poly_offset_state(struct si_context
*sctx
)
718 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
720 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
721 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
725 /* Use the user format, not db_render_format, so that the polygon
726 * offset behaves as expected by applications.
728 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
729 case PIPE_FORMAT_Z16_UNORM
:
730 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
732 default: /* 24-bit */
733 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
735 case PIPE_FORMAT_Z32_FLOAT
:
736 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
737 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
746 static uint32_t si_translate_fill(uint32_t func
)
749 case PIPE_POLYGON_MODE_FILL
:
750 return V_028814_X_DRAW_TRIANGLES
;
751 case PIPE_POLYGON_MODE_LINE
:
752 return V_028814_X_DRAW_LINES
;
753 case PIPE_POLYGON_MODE_POINT
:
754 return V_028814_X_DRAW_POINTS
;
757 return V_028814_X_DRAW_POINTS
;
761 static void *si_create_rs_state(struct pipe_context
*ctx
,
762 const struct pipe_rasterizer_state
*state
)
764 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
765 struct si_pm4_state
*pm4
= &rs
->pm4
;
767 float psize_min
, psize_max
;
773 rs
->scissor_enable
= state
->scissor
;
774 rs
->clip_halfz
= state
->clip_halfz
;
775 rs
->two_side
= state
->light_twoside
;
776 rs
->multisample_enable
= state
->multisample
;
777 rs
->force_persample_interp
= state
->force_persample_interp
;
778 rs
->clip_plane_enable
= state
->clip_plane_enable
;
779 rs
->line_stipple_enable
= state
->line_stipple_enable
;
780 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
781 rs
->line_smooth
= state
->line_smooth
;
782 rs
->poly_smooth
= state
->poly_smooth
;
783 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
785 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
786 rs
->flatshade
= state
->flatshade
;
787 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
788 rs
->rasterizer_discard
= state
->rasterizer_discard
;
789 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
790 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
791 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
792 rs
->pa_cl_clip_cntl
=
793 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
794 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
795 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
796 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
797 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
799 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
800 S_0286D4_FLAT_SHADE_ENA(1) |
801 S_0286D4_PNT_SPRITE_ENA(1) |
802 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
803 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
804 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
805 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
806 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
808 /* point size 12.4 fixed point */
809 tmp
= (unsigned)(state
->point_size
* 8.0);
810 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
812 if (state
->point_size_per_vertex
) {
813 psize_min
= util_get_min_point_size(state
);
816 /* Force the point size to be as if the vertex output was disabled. */
817 psize_min
= state
->point_size
;
818 psize_max
= state
->point_size
;
820 /* Divide by two, because 0.5 = 1 pixel. */
821 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
822 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
823 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
825 tmp
= (unsigned)state
->line_width
* 8;
826 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
, S_028A08_WIDTH(tmp
));
827 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
828 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
829 S_028A48_MSAA_ENABLE(state
->multisample
||
830 state
->poly_smooth
||
831 state
->line_smooth
) |
832 S_028A48_VPORT_SCISSOR_ENABLE(1));
834 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
835 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
836 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
838 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
839 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
840 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
841 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
842 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
843 S_028814_FACE(!state
->front_ccw
) |
844 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
845 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
846 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
847 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
848 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
849 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
850 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
851 si_pm4_set_reg(pm4
, R_00B130_SPI_SHADER_USER_DATA_VS_0
+
852 SI_SGPR_VS_STATE_BITS
* 4, state
->clamp_vertex_color
);
854 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
855 for (i
= 0; i
< 3; i
++) {
856 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
857 float offset_units
= state
->offset_units
;
858 float offset_scale
= state
->offset_scale
* 16.0f
;
859 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
861 if (!state
->offset_units_unscaled
) {
863 case 0: /* 16-bit zbuffer */
864 offset_units
*= 4.0f
;
865 pa_su_poly_offset_db_fmt_cntl
=
866 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
868 case 1: /* 24-bit zbuffer */
869 offset_units
*= 2.0f
;
870 pa_su_poly_offset_db_fmt_cntl
=
871 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
873 case 2: /* 32-bit zbuffer */
874 offset_units
*= 1.0f
;
875 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
876 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
881 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
883 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
885 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
887 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
889 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
890 pa_su_poly_offset_db_fmt_cntl
);
896 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
898 struct si_context
*sctx
= (struct si_context
*)ctx
;
899 struct si_state_rasterizer
*old_rs
=
900 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
901 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
906 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
907 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
909 /* Update the small primitive filter workaround if necessary. */
910 if (sctx
->b
.family
>= CHIP_POLARIS10
&&
911 sctx
->framebuffer
.nr_samples
> 1)
912 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
915 r600_viewport_set_rast_deps(&sctx
->b
, rs
->scissor_enable
, rs
->clip_halfz
);
917 si_pm4_bind_state(sctx
, rasterizer
, rs
);
918 si_update_poly_offset_state(sctx
);
920 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
921 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
922 rs
->line_stipple_enable
;
923 sctx
->do_update_shaders
= true;
926 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
928 struct si_context
*sctx
= (struct si_context
*)ctx
;
930 if (sctx
->queued
.named
.rasterizer
== state
)
931 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
932 si_pm4_delete_state(sctx
, rasterizer
, (struct si_state_rasterizer
*)state
);
936 * infeered state between dsa and stencil ref
938 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
940 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
941 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
942 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
944 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
945 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
946 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
947 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
948 S_028430_STENCILOPVAL(1));
949 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
950 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
951 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
952 S_028434_STENCILOPVAL_BF(1));
955 static void si_set_stencil_ref(struct pipe_context
*ctx
,
956 const struct pipe_stencil_ref
*state
)
958 struct si_context
*sctx
= (struct si_context
*)ctx
;
960 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
963 sctx
->stencil_ref
.state
= *state
;
964 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
972 static uint32_t si_translate_stencil_op(int s_op
)
975 case PIPE_STENCIL_OP_KEEP
:
976 return V_02842C_STENCIL_KEEP
;
977 case PIPE_STENCIL_OP_ZERO
:
978 return V_02842C_STENCIL_ZERO
;
979 case PIPE_STENCIL_OP_REPLACE
:
980 return V_02842C_STENCIL_REPLACE_TEST
;
981 case PIPE_STENCIL_OP_INCR
:
982 return V_02842C_STENCIL_ADD_CLAMP
;
983 case PIPE_STENCIL_OP_DECR
:
984 return V_02842C_STENCIL_SUB_CLAMP
;
985 case PIPE_STENCIL_OP_INCR_WRAP
:
986 return V_02842C_STENCIL_ADD_WRAP
;
987 case PIPE_STENCIL_OP_DECR_WRAP
:
988 return V_02842C_STENCIL_SUB_WRAP
;
989 case PIPE_STENCIL_OP_INVERT
:
990 return V_02842C_STENCIL_INVERT
;
992 R600_ERR("Unknown stencil op %d", s_op
);
999 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1000 const struct pipe_depth_stencil_alpha_state
*state
)
1002 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1003 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1004 unsigned db_depth_control
;
1005 uint32_t db_stencil_control
= 0;
1011 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1012 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1013 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1014 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1016 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1017 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1018 S_028800_ZFUNC(state
->depth
.func
) |
1019 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1022 if (state
->stencil
[0].enabled
) {
1023 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1024 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1025 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1026 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1027 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1029 if (state
->stencil
[1].enabled
) {
1030 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1031 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1032 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1033 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1034 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1039 if (state
->alpha
.enabled
) {
1040 dsa
->alpha_func
= state
->alpha
.func
;
1042 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1043 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1045 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1048 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1049 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1050 if (state
->depth
.bounds_test
) {
1051 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1052 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1058 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1060 struct si_context
*sctx
= (struct si_context
*)ctx
;
1061 struct si_state_dsa
*dsa
= state
;
1066 si_pm4_bind_state(sctx
, dsa
, dsa
);
1068 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1069 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1070 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1071 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1073 sctx
->do_update_shaders
= true;
1076 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1078 struct si_context
*sctx
= (struct si_context
*)ctx
;
1079 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1082 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1084 struct pipe_depth_stencil_alpha_state dsa
= {};
1086 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1089 /* DB RENDER STATE */
1091 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1093 struct si_context
*sctx
= (struct si_context
*)ctx
;
1095 /* Pipeline stat & streamout queries. */
1097 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1098 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1100 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1101 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1104 /* Occlusion queries. */
1105 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1106 sctx
->occlusion_queries_disabled
= !enable
;
1107 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1111 static void si_set_occlusion_query_state(struct pipe_context
*ctx
, bool enable
)
1113 struct si_context
*sctx
= (struct si_context
*)ctx
;
1115 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1118 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1120 struct si_context
*sctx
= (struct si_context
*)ctx
;
1122 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1124 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1125 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1128 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1130 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1131 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1132 unsigned db_shader_control
;
1134 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1136 /* DB_RENDER_CONTROL */
1137 if (sctx
->dbcb_depth_copy_enabled
||
1138 sctx
->dbcb_stencil_copy_enabled
) {
1140 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1141 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1142 S_028000_COPY_CENTROID(1) |
1143 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1144 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1146 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1147 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1150 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1151 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1154 /* DB_COUNT_CONTROL (occlusion queries) */
1155 if (sctx
->b
.num_occlusion_queries
> 0 &&
1156 !sctx
->occlusion_queries_disabled
) {
1157 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1159 if (sctx
->b
.chip_class
>= CIK
) {
1161 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1162 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1163 S_028004_ZPASS_ENABLE(1) |
1164 S_028004_SLICE_EVEN_ENABLE(1) |
1165 S_028004_SLICE_ODD_ENABLE(1));
1168 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1169 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1172 /* Disable occlusion queries. */
1173 if (sctx
->b
.chip_class
>= CIK
) {
1176 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1180 /* DB_RENDER_OVERRIDE2 */
1181 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1182 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1183 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1184 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1186 db_shader_control
= sctx
->ps_db_shader_control
;
1188 /* Bug workaround for smoothing (overrasterization) on SI. */
1189 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1190 db_shader_control
&= C_02880C_Z_ORDER
;
1191 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1194 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1195 if (!rs
|| !rs
->multisample_enable
)
1196 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1198 if (sctx
->b
.family
== CHIP_STONEY
&&
1199 sctx
->screen
->b
.debug_flags
& DBG_NO_RB_PLUS
)
1200 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1202 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1207 * format translation
1209 static uint32_t si_translate_colorformat(enum pipe_format format
)
1211 const struct util_format_description
*desc
= util_format_description(format
);
1213 #define HAS_SIZE(x,y,z,w) \
1214 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1215 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1217 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1218 return V_028C70_COLOR_10_11_11
;
1220 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1221 return V_028C70_COLOR_INVALID
;
1223 /* hw cannot support mixed formats (except depth/stencil, since
1224 * stencil is not written to). */
1225 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1226 return V_028C70_COLOR_INVALID
;
1228 switch (desc
->nr_channels
) {
1230 switch (desc
->channel
[0].size
) {
1232 return V_028C70_COLOR_8
;
1234 return V_028C70_COLOR_16
;
1236 return V_028C70_COLOR_32
;
1240 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1241 switch (desc
->channel
[0].size
) {
1243 return V_028C70_COLOR_8_8
;
1245 return V_028C70_COLOR_16_16
;
1247 return V_028C70_COLOR_32_32
;
1249 } else if (HAS_SIZE(8,24,0,0)) {
1250 return V_028C70_COLOR_24_8
;
1251 } else if (HAS_SIZE(24,8,0,0)) {
1252 return V_028C70_COLOR_8_24
;
1256 if (HAS_SIZE(5,6,5,0)) {
1257 return V_028C70_COLOR_5_6_5
;
1258 } else if (HAS_SIZE(32,8,24,0)) {
1259 return V_028C70_COLOR_X24_8_32_FLOAT
;
1263 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1264 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1265 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1266 switch (desc
->channel
[0].size
) {
1268 return V_028C70_COLOR_4_4_4_4
;
1270 return V_028C70_COLOR_8_8_8_8
;
1272 return V_028C70_COLOR_16_16_16_16
;
1274 return V_028C70_COLOR_32_32_32_32
;
1276 } else if (HAS_SIZE(5,5,5,1)) {
1277 return V_028C70_COLOR_1_5_5_5
;
1278 } else if (HAS_SIZE(10,10,10,2)) {
1279 return V_028C70_COLOR_2_10_10_10
;
1283 return V_028C70_COLOR_INVALID
;
1286 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1288 if (SI_BIG_ENDIAN
) {
1289 switch(colorformat
) {
1290 /* 8-bit buffers. */
1291 case V_028C70_COLOR_8
:
1292 return V_028C70_ENDIAN_NONE
;
1294 /* 16-bit buffers. */
1295 case V_028C70_COLOR_5_6_5
:
1296 case V_028C70_COLOR_1_5_5_5
:
1297 case V_028C70_COLOR_4_4_4_4
:
1298 case V_028C70_COLOR_16
:
1299 case V_028C70_COLOR_8_8
:
1300 return V_028C70_ENDIAN_8IN16
;
1302 /* 32-bit buffers. */
1303 case V_028C70_COLOR_8_8_8_8
:
1304 case V_028C70_COLOR_2_10_10_10
:
1305 case V_028C70_COLOR_8_24
:
1306 case V_028C70_COLOR_24_8
:
1307 case V_028C70_COLOR_16_16
:
1308 return V_028C70_ENDIAN_8IN32
;
1310 /* 64-bit buffers. */
1311 case V_028C70_COLOR_16_16_16_16
:
1312 return V_028C70_ENDIAN_8IN16
;
1314 case V_028C70_COLOR_32_32
:
1315 return V_028C70_ENDIAN_8IN32
;
1317 /* 128-bit buffers. */
1318 case V_028C70_COLOR_32_32_32_32
:
1319 return V_028C70_ENDIAN_8IN32
;
1321 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1324 return V_028C70_ENDIAN_NONE
;
1328 static uint32_t si_translate_dbformat(enum pipe_format format
)
1331 case PIPE_FORMAT_Z16_UNORM
:
1332 return V_028040_Z_16
;
1333 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1334 case PIPE_FORMAT_X8Z24_UNORM
:
1335 case PIPE_FORMAT_Z24X8_UNORM
:
1336 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1337 return V_028040_Z_24
; /* deprecated on SI */
1338 case PIPE_FORMAT_Z32_FLOAT
:
1339 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1340 return V_028040_Z_32_FLOAT
;
1342 return V_028040_Z_INVALID
;
1347 * Texture translation
1350 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1351 enum pipe_format format
,
1352 const struct util_format_description
*desc
,
1355 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1356 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1357 sscreen
->b
.info
.drm_minor
>= 31) ||
1358 sscreen
->b
.info
.drm_major
== 3;
1359 bool uniform
= true;
1362 /* Colorspace (return non-RGB formats directly). */
1363 switch (desc
->colorspace
) {
1364 /* Depth stencil formats */
1365 case UTIL_FORMAT_COLORSPACE_ZS
:
1367 case PIPE_FORMAT_Z16_UNORM
:
1368 return V_008F14_IMG_DATA_FORMAT_16
;
1369 case PIPE_FORMAT_X24S8_UINT
:
1370 case PIPE_FORMAT_S8X24_UINT
:
1372 * Implemented as an 8_8_8_8 data format to fix texture
1373 * gathers in stencil sampling. This affects at least
1374 * GL45-CTS.texture_cube_map_array.sampling on VI.
1376 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1377 case PIPE_FORMAT_Z24X8_UNORM
:
1378 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1379 return V_008F14_IMG_DATA_FORMAT_8_24
;
1380 case PIPE_FORMAT_X8Z24_UNORM
:
1381 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1382 return V_008F14_IMG_DATA_FORMAT_24_8
;
1383 case PIPE_FORMAT_S8_UINT
:
1384 return V_008F14_IMG_DATA_FORMAT_8
;
1385 case PIPE_FORMAT_Z32_FLOAT
:
1386 return V_008F14_IMG_DATA_FORMAT_32
;
1387 case PIPE_FORMAT_X32_S8X24_UINT
:
1388 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1389 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1394 case UTIL_FORMAT_COLORSPACE_YUV
:
1395 goto out_unknown
; /* TODO */
1397 case UTIL_FORMAT_COLORSPACE_SRGB
:
1398 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1406 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1407 if (!enable_compressed_formats
)
1411 case PIPE_FORMAT_RGTC1_SNORM
:
1412 case PIPE_FORMAT_LATC1_SNORM
:
1413 case PIPE_FORMAT_RGTC1_UNORM
:
1414 case PIPE_FORMAT_LATC1_UNORM
:
1415 return V_008F14_IMG_DATA_FORMAT_BC4
;
1416 case PIPE_FORMAT_RGTC2_SNORM
:
1417 case PIPE_FORMAT_LATC2_SNORM
:
1418 case PIPE_FORMAT_RGTC2_UNORM
:
1419 case PIPE_FORMAT_LATC2_UNORM
:
1420 return V_008F14_IMG_DATA_FORMAT_BC5
;
1426 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1427 sscreen
->b
.family
== CHIP_STONEY
) {
1429 case PIPE_FORMAT_ETC1_RGB8
:
1430 case PIPE_FORMAT_ETC2_RGB8
:
1431 case PIPE_FORMAT_ETC2_SRGB8
:
1432 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1433 case PIPE_FORMAT_ETC2_RGB8A1
:
1434 case PIPE_FORMAT_ETC2_SRGB8A1
:
1435 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1436 case PIPE_FORMAT_ETC2_RGBA8
:
1437 case PIPE_FORMAT_ETC2_SRGBA8
:
1438 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1439 case PIPE_FORMAT_ETC2_R11_UNORM
:
1440 case PIPE_FORMAT_ETC2_R11_SNORM
:
1441 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1442 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1443 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1444 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1450 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1451 if (!enable_compressed_formats
)
1455 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1456 case PIPE_FORMAT_BPTC_SRGBA
:
1457 return V_008F14_IMG_DATA_FORMAT_BC7
;
1458 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1459 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1460 return V_008F14_IMG_DATA_FORMAT_BC6
;
1466 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1468 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1469 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1470 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1471 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1472 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1473 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1479 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1480 if (!enable_compressed_formats
)
1483 if (!util_format_s3tc_enabled
) {
1488 case PIPE_FORMAT_DXT1_RGB
:
1489 case PIPE_FORMAT_DXT1_RGBA
:
1490 case PIPE_FORMAT_DXT1_SRGB
:
1491 case PIPE_FORMAT_DXT1_SRGBA
:
1492 return V_008F14_IMG_DATA_FORMAT_BC1
;
1493 case PIPE_FORMAT_DXT3_RGBA
:
1494 case PIPE_FORMAT_DXT3_SRGBA
:
1495 return V_008F14_IMG_DATA_FORMAT_BC2
;
1496 case PIPE_FORMAT_DXT5_RGBA
:
1497 case PIPE_FORMAT_DXT5_SRGBA
:
1498 return V_008F14_IMG_DATA_FORMAT_BC3
;
1504 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1505 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1506 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1507 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1510 /* R8G8Bx_SNORM - TODO CxV8U8 */
1512 /* hw cannot support mixed formats (except depth/stencil, since only
1514 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1517 /* See whether the components are of the same size. */
1518 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1519 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1522 /* Non-uniform formats. */
1524 switch(desc
->nr_channels
) {
1526 if (desc
->channel
[0].size
== 5 &&
1527 desc
->channel
[1].size
== 6 &&
1528 desc
->channel
[2].size
== 5) {
1529 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1533 if (desc
->channel
[0].size
== 5 &&
1534 desc
->channel
[1].size
== 5 &&
1535 desc
->channel
[2].size
== 5 &&
1536 desc
->channel
[3].size
== 1) {
1537 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1539 if (desc
->channel
[0].size
== 10 &&
1540 desc
->channel
[1].size
== 10 &&
1541 desc
->channel
[2].size
== 10 &&
1542 desc
->channel
[3].size
== 2) {
1543 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1550 if (first_non_void
< 0 || first_non_void
> 3)
1553 /* uniform formats */
1554 switch (desc
->channel
[first_non_void
].size
) {
1556 switch (desc
->nr_channels
) {
1557 #if 0 /* Not supported for render targets */
1559 return V_008F14_IMG_DATA_FORMAT_4_4
;
1562 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1566 switch (desc
->nr_channels
) {
1568 return V_008F14_IMG_DATA_FORMAT_8
;
1570 return V_008F14_IMG_DATA_FORMAT_8_8
;
1572 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1576 switch (desc
->nr_channels
) {
1578 return V_008F14_IMG_DATA_FORMAT_16
;
1580 return V_008F14_IMG_DATA_FORMAT_16_16
;
1582 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1586 switch (desc
->nr_channels
) {
1588 return V_008F14_IMG_DATA_FORMAT_32
;
1590 return V_008F14_IMG_DATA_FORMAT_32_32
;
1591 #if 0 /* Not supported for render targets */
1593 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1596 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1601 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1605 static unsigned si_tex_wrap(unsigned wrap
)
1609 case PIPE_TEX_WRAP_REPEAT
:
1610 return V_008F30_SQ_TEX_WRAP
;
1611 case PIPE_TEX_WRAP_CLAMP
:
1612 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1613 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1614 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1615 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1616 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1617 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1618 return V_008F30_SQ_TEX_MIRROR
;
1619 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1620 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1621 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1622 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1623 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1624 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1628 static unsigned si_tex_mipfilter(unsigned filter
)
1631 case PIPE_TEX_MIPFILTER_NEAREST
:
1632 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1633 case PIPE_TEX_MIPFILTER_LINEAR
:
1634 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1636 case PIPE_TEX_MIPFILTER_NONE
:
1637 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1641 static unsigned si_tex_compare(unsigned compare
)
1645 case PIPE_FUNC_NEVER
:
1646 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1647 case PIPE_FUNC_LESS
:
1648 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1649 case PIPE_FUNC_EQUAL
:
1650 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1651 case PIPE_FUNC_LEQUAL
:
1652 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1653 case PIPE_FUNC_GREATER
:
1654 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1655 case PIPE_FUNC_NOTEQUAL
:
1656 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1657 case PIPE_FUNC_GEQUAL
:
1658 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1659 case PIPE_FUNC_ALWAYS
:
1660 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1664 static unsigned si_tex_dim(unsigned res_target
, unsigned view_target
,
1665 unsigned nr_samples
)
1667 if (view_target
== PIPE_TEXTURE_CUBE
||
1668 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1669 res_target
= view_target
;
1670 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1671 else if (res_target
== PIPE_TEXTURE_CUBE
||
1672 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1673 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1675 switch (res_target
) {
1677 case PIPE_TEXTURE_1D
:
1678 return V_008F1C_SQ_RSRC_IMG_1D
;
1679 case PIPE_TEXTURE_1D_ARRAY
:
1680 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1681 case PIPE_TEXTURE_2D
:
1682 case PIPE_TEXTURE_RECT
:
1683 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1684 V_008F1C_SQ_RSRC_IMG_2D
;
1685 case PIPE_TEXTURE_2D_ARRAY
:
1686 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1687 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1688 case PIPE_TEXTURE_3D
:
1689 return V_008F1C_SQ_RSRC_IMG_3D
;
1690 case PIPE_TEXTURE_CUBE
:
1691 case PIPE_TEXTURE_CUBE_ARRAY
:
1692 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1697 * Format support testing
1700 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1702 return si_translate_texformat(screen
, format
, util_format_description(format
),
1703 util_format_get_first_non_void_channel(format
)) != ~0U;
1706 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1707 const struct util_format_description
*desc
,
1712 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1713 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1715 assert(first_non_void
>= 0);
1717 if (desc
->nr_channels
== 4 &&
1718 desc
->channel
[0].size
== 10 &&
1719 desc
->channel
[1].size
== 10 &&
1720 desc
->channel
[2].size
== 10 &&
1721 desc
->channel
[3].size
== 2)
1722 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1724 /* See whether the components are of the same size. */
1725 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1726 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1727 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1730 switch (desc
->channel
[first_non_void
].size
) {
1732 switch (desc
->nr_channels
) {
1734 return V_008F0C_BUF_DATA_FORMAT_8
;
1736 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1739 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1743 switch (desc
->nr_channels
) {
1745 return V_008F0C_BUF_DATA_FORMAT_16
;
1747 return V_008F0C_BUF_DATA_FORMAT_16_16
;
1750 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
1754 switch (desc
->nr_channels
) {
1756 return V_008F0C_BUF_DATA_FORMAT_32
;
1758 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1760 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
1762 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1766 /* Legacy double formats. */
1767 switch (desc
->nr_channels
) {
1768 case 1: /* 1 load */
1769 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1770 case 2: /* 1 load */
1771 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1772 case 3: /* 3 loads */
1773 return V_008F0C_BUF_DATA_FORMAT_32_32
;
1774 case 4: /* 2 loads */
1775 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
1780 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1783 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
1784 const struct util_format_description
*desc
,
1787 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1788 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1790 assert(first_non_void
>= 0);
1792 switch (desc
->channel
[first_non_void
].type
) {
1793 case UTIL_FORMAT_TYPE_SIGNED
:
1794 case UTIL_FORMAT_TYPE_FIXED
:
1795 if (desc
->channel
[first_non_void
].size
>= 32 ||
1796 desc
->channel
[first_non_void
].pure_integer
)
1797 return V_008F0C_BUF_NUM_FORMAT_SINT
;
1798 else if (desc
->channel
[first_non_void
].normalized
)
1799 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
1801 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
1803 case UTIL_FORMAT_TYPE_UNSIGNED
:
1804 if (desc
->channel
[first_non_void
].size
>= 32 ||
1805 desc
->channel
[first_non_void
].pure_integer
)
1806 return V_008F0C_BUF_NUM_FORMAT_UINT
;
1807 else if (desc
->channel
[first_non_void
].normalized
)
1808 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
1810 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
1812 case UTIL_FORMAT_TYPE_FLOAT
:
1814 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
1818 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
1819 enum pipe_format format
,
1822 const struct util_format_description
*desc
;
1824 unsigned data_format
;
1826 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
1827 PIPE_BIND_SAMPLER_VIEW
|
1828 PIPE_BIND_VERTEX_BUFFER
)) == 0);
1830 desc
= util_format_description(format
);
1832 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
1833 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
1834 * for read-only access (with caveats surrounding bounds checks), but
1835 * obviously fails for write access which we have to implement for
1836 * shader images. Luckily, OpenGL doesn't expect this to be supported
1837 * anyway, and so the only impact is on PBO uploads / downloads, which
1838 * shouldn't be expected to be fast for GL_RGB anyway.
1840 if (desc
->block
.bits
== 3 * 8 ||
1841 desc
->block
.bits
== 3 * 16) {
1842 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
1843 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
1849 first_non_void
= util_format_get_first_non_void_channel(format
);
1850 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
1851 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
1857 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
1859 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
1860 r600_translate_colorswap(format
, false) != ~0U;
1863 static bool si_is_zs_format_supported(enum pipe_format format
)
1865 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
1868 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
1869 enum pipe_format format
,
1870 enum pipe_texture_target target
,
1871 unsigned sample_count
,
1874 unsigned retval
= 0;
1876 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
1877 R600_ERR("r600: unsupported texture type %d\n", target
);
1881 if (!util_format_is_supported(format
, usage
))
1884 if (sample_count
> 1) {
1885 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
1888 if (usage
& PIPE_BIND_SHADER_IMAGE
)
1891 switch (sample_count
) {
1897 if (format
== PIPE_FORMAT_NONE
)
1906 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
1907 PIPE_BIND_SHADER_IMAGE
)) {
1908 if (target
== PIPE_BUFFER
) {
1909 retval
|= si_is_vertex_format_supported(
1910 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
1911 PIPE_BIND_SHADER_IMAGE
));
1913 if (si_is_sampler_format_supported(screen
, format
))
1914 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
1915 PIPE_BIND_SHADER_IMAGE
);
1919 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
1920 PIPE_BIND_DISPLAY_TARGET
|
1923 PIPE_BIND_BLENDABLE
)) &&
1924 si_is_colorbuffer_format_supported(format
)) {
1926 (PIPE_BIND_RENDER_TARGET
|
1927 PIPE_BIND_DISPLAY_TARGET
|
1930 if (!util_format_is_pure_integer(format
) &&
1931 !util_format_is_depth_or_stencil(format
))
1932 retval
|= usage
& PIPE_BIND_BLENDABLE
;
1935 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
1936 si_is_zs_format_supported(format
)) {
1937 retval
|= PIPE_BIND_DEPTH_STENCIL
;
1940 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
1941 retval
|= si_is_vertex_format_supported(screen
, format
,
1942 PIPE_BIND_VERTEX_BUFFER
);
1945 if ((usage
& PIPE_BIND_LINEAR
) &&
1946 !util_format_is_compressed(format
) &&
1947 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
1948 retval
|= PIPE_BIND_LINEAR
;
1950 return retval
== usage
;
1954 * framebuffer handling
1957 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
1958 unsigned format
, unsigned swap
,
1959 unsigned ntype
, bool is_depth
)
1961 /* Alpha is needed for alpha-to-coverage.
1962 * Blending may be with or without alpha.
1964 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
1965 unsigned alpha
= 0; /* exports alpha, but may not support blending */
1966 unsigned blend
= 0; /* supports blending, but may not export alpha */
1967 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
1969 /* Choose the SPI color formats. These are required values for Stoney/RB+.
1970 * Other chips have multiple choices, though they are not necessarily better.
1973 case V_028C70_COLOR_5_6_5
:
1974 case V_028C70_COLOR_1_5_5_5
:
1975 case V_028C70_COLOR_5_5_5_1
:
1976 case V_028C70_COLOR_4_4_4_4
:
1977 case V_028C70_COLOR_10_11_11
:
1978 case V_028C70_COLOR_11_11_10
:
1979 case V_028C70_COLOR_8
:
1980 case V_028C70_COLOR_8_8
:
1981 case V_028C70_COLOR_8_8_8_8
:
1982 case V_028C70_COLOR_10_10_10_2
:
1983 case V_028C70_COLOR_2_10_10_10
:
1984 if (ntype
== V_028C70_NUMBER_UINT
)
1985 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
1986 else if (ntype
== V_028C70_NUMBER_SINT
)
1987 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
1989 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
1992 case V_028C70_COLOR_16
:
1993 case V_028C70_COLOR_16_16
:
1994 case V_028C70_COLOR_16_16_16_16
:
1995 if (ntype
== V_028C70_NUMBER_UNORM
||
1996 ntype
== V_028C70_NUMBER_SNORM
) {
1997 /* UNORM16 and SNORM16 don't support blending */
1998 if (ntype
== V_028C70_NUMBER_UNORM
)
1999 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2001 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2003 /* Use 32 bits per channel for blending. */
2004 if (format
== V_028C70_COLOR_16
) {
2005 if (swap
== V_028C70_SWAP_STD
) { /* R */
2006 blend
= V_028714_SPI_SHADER_32_R
;
2007 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2008 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2009 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2012 } else if (format
== V_028C70_COLOR_16_16
) {
2013 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2014 blend
= V_028714_SPI_SHADER_32_GR
;
2015 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2016 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2017 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2020 } else /* 16_16_16_16 */
2021 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2022 } else if (ntype
== V_028C70_NUMBER_UINT
)
2023 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2024 else if (ntype
== V_028C70_NUMBER_SINT
)
2025 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2026 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2027 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2032 case V_028C70_COLOR_32
:
2033 if (swap
== V_028C70_SWAP_STD
) { /* R */
2034 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2035 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2036 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2037 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2042 case V_028C70_COLOR_32_32
:
2043 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2044 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2045 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2046 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2047 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2052 case V_028C70_COLOR_32_32_32_32
:
2053 case V_028C70_COLOR_8_24
:
2054 case V_028C70_COLOR_24_8
:
2055 case V_028C70_COLOR_X24_8_32_FLOAT
:
2056 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2064 /* The DB->CB copy needs 32_ABGR. */
2066 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2068 surf
->spi_shader_col_format
= normal
;
2069 surf
->spi_shader_col_format_alpha
= alpha
;
2070 surf
->spi_shader_col_format_blend
= blend
;
2071 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2074 static void si_initialize_color_surface(struct si_context
*sctx
,
2075 struct r600_surface
*surf
)
2077 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2078 unsigned color_info
, color_attrib
, color_view
;
2079 unsigned format
, swap
, ntype
, endian
;
2080 const struct util_format_description
*desc
;
2082 unsigned blend_clamp
= 0, blend_bypass
= 0;
2084 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2085 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2087 desc
= util_format_description(surf
->base
.format
);
2088 for (i
= 0; i
< 4; i
++) {
2089 if (desc
->channel
[i
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2093 if (i
== 4 || desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2094 ntype
= V_028C70_NUMBER_FLOAT
;
2096 ntype
= V_028C70_NUMBER_UNORM
;
2097 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2098 ntype
= V_028C70_NUMBER_SRGB
;
2099 else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2100 if (desc
->channel
[i
].pure_integer
) {
2101 ntype
= V_028C70_NUMBER_SINT
;
2103 assert(desc
->channel
[i
].normalized
);
2104 ntype
= V_028C70_NUMBER_SNORM
;
2106 } else if (desc
->channel
[i
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2107 if (desc
->channel
[i
].pure_integer
) {
2108 ntype
= V_028C70_NUMBER_UINT
;
2110 assert(desc
->channel
[i
].normalized
);
2111 ntype
= V_028C70_NUMBER_UNORM
;
2116 format
= si_translate_colorformat(surf
->base
.format
);
2117 if (format
== V_028C70_COLOR_INVALID
) {
2118 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2120 assert(format
!= V_028C70_COLOR_INVALID
);
2121 swap
= r600_translate_colorswap(surf
->base
.format
, false);
2122 endian
= si_colorformat_endian_swap(format
);
2124 /* blend clamp should be set for all NORM/SRGB types */
2125 if (ntype
== V_028C70_NUMBER_UNORM
||
2126 ntype
== V_028C70_NUMBER_SNORM
||
2127 ntype
== V_028C70_NUMBER_SRGB
)
2130 /* set blend bypass according to docs if SINT/UINT or
2131 8/24 COLOR variants */
2132 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2133 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2134 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2139 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2140 (format
== V_028C70_COLOR_8
||
2141 format
== V_028C70_COLOR_8_8
||
2142 format
== V_028C70_COLOR_8_8_8_8
))
2143 surf
->color_is_int8
= true;
2145 color_info
= S_028C70_FORMAT(format
) |
2146 S_028C70_COMP_SWAP(swap
) |
2147 S_028C70_BLEND_CLAMP(blend_clamp
) |
2148 S_028C70_BLEND_BYPASS(blend_bypass
) |
2149 S_028C70_SIMPLE_FLOAT(1) |
2150 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2151 ntype
!= V_028C70_NUMBER_SNORM
&&
2152 ntype
!= V_028C70_NUMBER_SRGB
&&
2153 format
!= V_028C70_COLOR_8_24
&&
2154 format
!= V_028C70_COLOR_24_8
) |
2155 S_028C70_NUMBER_TYPE(ntype
) |
2156 S_028C70_ENDIAN(endian
);
2158 /* Intensity is implemented as Red, so treat it that way. */
2159 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2160 util_format_is_intensity(surf
->base
.format
));
2162 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2163 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2165 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2166 S_028C74_NUM_FRAGMENTS(log_samples
);
2168 if (rtex
->fmask
.size
) {
2169 color_info
|= S_028C70_COMPRESSION(1);
2170 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2172 if (sctx
->b
.chip_class
== SI
) {
2173 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2174 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2179 surf
->cb_color_view
= color_view
;
2180 surf
->cb_color_info
= color_info
;
2181 surf
->cb_color_attrib
= color_attrib
;
2183 if (sctx
->b
.chip_class
>= VI
) {
2184 unsigned max_uncompressed_block_size
= 2;
2186 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2187 if (rtex
->surface
.bpe
== 1)
2188 max_uncompressed_block_size
= 0;
2189 else if (rtex
->surface
.bpe
== 2)
2190 max_uncompressed_block_size
= 1;
2193 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2194 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2197 /* This must be set for fast clear to work without FMASK. */
2198 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2199 unsigned bankh
= util_logbase2(rtex
->surface
.bankh
);
2200 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2203 /* Determine pixel shader export format */
2204 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2206 surf
->color_initialized
= true;
2209 static void si_init_depth_surface(struct si_context
*sctx
,
2210 struct r600_surface
*surf
)
2212 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2213 unsigned level
= surf
->base
.u
.tex
.level
;
2214 struct radeon_surf_level
*levelinfo
= &rtex
->surface
.level
[level
];
2216 uint32_t z_info
, s_info
, db_depth_info
;
2217 uint64_t z_offs
, s_offs
;
2218 uint32_t db_htile_data_base
, db_htile_surface
;
2220 format
= si_translate_dbformat(rtex
->db_render_format
);
2222 if (format
== V_028040_Z_INVALID
) {
2223 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2225 assert(format
!= V_028040_Z_INVALID
);
2227 s_offs
= z_offs
= rtex
->resource
.gpu_address
;
2228 z_offs
+= rtex
->surface
.level
[level
].offset
;
2229 s_offs
+= rtex
->surface
.stencil_level
[level
].offset
;
2231 db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2233 z_info
= S_028040_FORMAT(format
);
2234 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2235 z_info
|= S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2238 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
)
2239 s_info
= S_028044_FORMAT(V_028044_STENCIL_8
);
2241 s_info
= S_028044_FORMAT(V_028044_STENCIL_INVALID
);
2243 if (sctx
->b
.chip_class
>= CIK
) {
2244 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
2245 unsigned index
= rtex
->surface
.tiling_index
[level
];
2246 unsigned stencil_index
= rtex
->surface
.stencil_tiling_index
[level
];
2247 unsigned macro_index
= rtex
->surface
.macro_tile_index
;
2248 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2249 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2250 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2253 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2254 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2255 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2256 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2257 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2258 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2259 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2260 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2262 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2263 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2264 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2265 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2268 /* HiZ aka depth buffer htile */
2269 /* use htile only for first level */
2270 if (rtex
->htile_buffer
&& !level
) {
2271 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2272 S_028040_ALLOW_EXPCLEAR(1);
2274 if (rtex
->surface
.flags
& RADEON_SURF_SBUFFER
) {
2275 /* Workaround: For a not yet understood reason, the
2276 * combination of MSAA, fast stencil clear and stencil
2277 * decompress messes with subsequent stencil buffer
2278 * uses. Problem was reproduced on Verde, Bonaire,
2279 * Tonga, and Carrizo.
2281 * Disabling EXPCLEAR works around the problem.
2283 * Check piglit's arb_texture_multisample-stencil-clear
2284 * test if you want to try changing this.
2286 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2287 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2288 } else if (!rtex
->tc_compatible_htile
) {
2289 /* Use all of the htile_buffer for depth if there's no stencil.
2290 * This must not be set when TC-compatible HTILE is enabled
2293 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2296 uint64_t va
= rtex
->htile_buffer
->gpu_address
;
2297 db_htile_data_base
= va
>> 8;
2298 db_htile_surface
= S_028ABC_FULL_CACHE(1);
2300 if (rtex
->tc_compatible_htile
) {
2301 db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2303 switch (rtex
->resource
.b
.b
.nr_samples
) {
2306 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2310 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2313 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2320 db_htile_data_base
= 0;
2321 db_htile_surface
= 0;
2324 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2326 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2327 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2328 surf
->db_htile_data_base
= db_htile_data_base
;
2329 surf
->db_depth_info
= db_depth_info
;
2330 surf
->db_z_info
= z_info
;
2331 surf
->db_stencil_info
= s_info
;
2332 surf
->db_depth_base
= z_offs
>> 8;
2333 surf
->db_stencil_base
= s_offs
>> 8;
2334 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2335 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2336 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2337 levelinfo
->nblk_y
) / 64 - 1);
2338 surf
->db_htile_surface
= db_htile_surface
;
2340 surf
->depth_initialized
= true;
2343 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2345 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2346 struct r600_surface
*surf
= NULL
;
2347 struct r600_texture
*rtex
;
2349 if (!state
->cbufs
[i
])
2351 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2352 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2354 p_atomic_dec(&rtex
->framebuffers_bound
);
2358 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2359 const struct pipe_framebuffer_state
*state
)
2361 struct si_context
*sctx
= (struct si_context
*)ctx
;
2362 struct pipe_constant_buffer constbuf
= {0};
2363 struct r600_surface
*surf
= NULL
;
2364 struct r600_texture
*rtex
;
2365 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2366 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2369 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2370 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2373 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2374 if (rtex
->dcc_gather_statistics
)
2375 vi_separate_dcc_stop_query(ctx
, rtex
);
2378 /* Only flush TC when changing the framebuffer state, because
2379 * the only client not using TC that can change textures is
2382 * Flush all CB and DB caches here because all buffers can be used
2383 * for write by both TC (with shader image stores) and CB/DB.
2385 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
2386 SI_CONTEXT_INV_GLOBAL_L2
|
2387 SI_CONTEXT_FLUSH_AND_INV_CB
|
2388 SI_CONTEXT_FLUSH_AND_INV_DB
|
2389 SI_CONTEXT_CS_PARTIAL_FLUSH
;
2391 /* Take the maximum of the old and new count. If the new count is lower,
2392 * dirtying is needed to disable the unbound colorbuffers.
2394 sctx
->framebuffer
.dirty_cbufs
|=
2395 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2396 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2398 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2399 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2401 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2402 sctx
->framebuffer
.spi_shader_col_format
= 0;
2403 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2404 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2405 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2406 sctx
->framebuffer
.color_is_int8
= 0;
2408 sctx
->framebuffer
.compressed_cb_mask
= 0;
2409 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2410 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2411 sctx
->framebuffer
.any_dst_linear
= false;
2413 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2414 if (!state
->cbufs
[i
])
2417 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2418 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2420 if (!surf
->color_initialized
) {
2421 si_initialize_color_surface(sctx
, surf
);
2424 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2425 sctx
->framebuffer
.spi_shader_col_format
|=
2426 surf
->spi_shader_col_format
<< (i
* 4);
2427 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2428 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2429 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2430 surf
->spi_shader_col_format_blend
<< (i
* 4);
2431 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2432 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2434 if (surf
->color_is_int8
)
2435 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2437 if (rtex
->fmask
.size
) {
2438 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2441 if (rtex
->surface
.is_linear
)
2442 sctx
->framebuffer
.any_dst_linear
= true;
2444 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2446 p_atomic_inc(&rtex
->framebuffers_bound
);
2448 if (rtex
->dcc_gather_statistics
) {
2449 /* Dirty tracking must be enabled for DCC usage analysis. */
2450 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2451 vi_separate_dcc_start_query(ctx
, rtex
);
2456 surf
= (struct r600_surface
*)state
->zsbuf
;
2457 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2459 if (!surf
->depth_initialized
) {
2460 si_init_depth_surface(sctx
, surf
);
2462 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2465 si_update_poly_offset_state(sctx
);
2466 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2467 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2469 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2470 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2472 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2473 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2474 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2476 /* Set sample locations as fragment shader constants. */
2477 switch (sctx
->framebuffer
.nr_samples
) {
2479 constbuf
.user_buffer
= sctx
->b
.sample_locations_1x
;
2482 constbuf
.user_buffer
= sctx
->b
.sample_locations_2x
;
2485 constbuf
.user_buffer
= sctx
->b
.sample_locations_4x
;
2488 constbuf
.user_buffer
= sctx
->b
.sample_locations_8x
;
2491 constbuf
.user_buffer
= sctx
->b
.sample_locations_16x
;
2494 R600_ERR("Requested an invalid number of samples %i.\n",
2495 sctx
->framebuffer
.nr_samples
);
2498 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2499 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2501 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2504 sctx
->need_check_render_feedback
= true;
2505 sctx
->do_update_shaders
= true;
2506 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
2509 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2511 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2512 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2513 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2514 struct r600_texture
*tex
= NULL
;
2515 struct r600_surface
*cb
= NULL
;
2516 unsigned cb_color_info
= 0;
2519 for (i
= 0; i
< nr_cbufs
; i
++) {
2520 const struct radeon_surf_level
*level_info
;
2521 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2522 unsigned cb_color_base
, cb_color_fmask
, cb_color_attrib
;
2523 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
2525 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2528 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2530 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2531 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2535 tex
= (struct r600_texture
*)cb
->base
.texture
;
2536 level_info
= &tex
->surface
.level
[cb
->base
.u
.tex
.level
];
2537 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2538 &tex
->resource
, RADEON_USAGE_READWRITE
,
2539 tex
->resource
.b
.b
.nr_samples
> 1 ?
2540 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2541 RADEON_PRIO_COLOR_BUFFER
);
2543 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2544 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2545 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2549 if (tex
->dcc_separate_buffer
)
2550 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2551 tex
->dcc_separate_buffer
,
2552 RADEON_USAGE_READWRITE
,
2555 /* Compute mutable surface parameters. */
2556 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2557 slice_tile_max
= level_info
->nblk_x
*
2558 level_info
->nblk_y
/ 64 - 1;
2559 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
2561 cb_color_base
= (tex
->resource
.gpu_address
+ level_info
->offset
) >> 8;
2562 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2563 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2564 cb_color_attrib
= cb
->cb_color_attrib
|
2565 S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2567 if (tex
->fmask
.size
) {
2568 if (sctx
->b
.chip_class
>= CIK
)
2569 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
2570 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
2571 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
2572 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
2574 /* This must be set for fast clear to work without FMASK. */
2575 if (sctx
->b
.chip_class
>= CIK
)
2576 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2577 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2578 cb_color_fmask
= cb_color_base
;
2579 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2582 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2584 if (tex
->dcc_offset
&& cb
->base
.u
.tex
.level
< tex
->surface
.num_dcc_levels
) {
2585 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
2586 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2587 state
->cbufs
[1] == &cb
->base
&&
2588 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2590 if (!is_msaa_resolve_dst
)
2591 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2594 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
2595 sctx
->b
.chip_class
>= VI
? 14 : 13);
2596 radeon_emit(cs
, cb_color_base
); /* R_028C60_CB_COLOR0_BASE */
2597 radeon_emit(cs
, cb_color_pitch
); /* R_028C64_CB_COLOR0_PITCH */
2598 radeon_emit(cs
, cb_color_slice
); /* R_028C68_CB_COLOR0_SLICE */
2599 radeon_emit(cs
, cb
->cb_color_view
); /* R_028C6C_CB_COLOR0_VIEW */
2600 radeon_emit(cs
, cb_color_info
); /* R_028C70_CB_COLOR0_INFO */
2601 radeon_emit(cs
, cb_color_attrib
); /* R_028C74_CB_COLOR0_ATTRIB */
2602 radeon_emit(cs
, cb
->cb_dcc_control
); /* R_028C78_CB_COLOR0_DCC_CONTROL */
2603 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* R_028C7C_CB_COLOR0_CMASK */
2604 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* R_028C80_CB_COLOR0_CMASK_SLICE */
2605 radeon_emit(cs
, cb_color_fmask
); /* R_028C84_CB_COLOR0_FMASK */
2606 radeon_emit(cs
, cb_color_fmask_slice
); /* R_028C88_CB_COLOR0_FMASK_SLICE */
2607 radeon_emit(cs
, tex
->color_clear_value
[0]); /* R_028C8C_CB_COLOR0_CLEAR_WORD0 */
2608 radeon_emit(cs
, tex
->color_clear_value
[1]); /* R_028C90_CB_COLOR0_CLEAR_WORD1 */
2610 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
2611 radeon_emit(cs
, ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
2613 tex
->surface
.level
[cb
->base
.u
.tex
.level
].dcc_offset
) >> 8);
2616 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
2617 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
2620 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
2621 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
2622 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
2624 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2625 &rtex
->resource
, RADEON_USAGE_READWRITE
,
2626 zb
->base
.texture
->nr_samples
> 1 ?
2627 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
2628 RADEON_PRIO_DEPTH_BUFFER
);
2630 if (zb
->db_htile_data_base
) {
2631 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2632 rtex
->htile_buffer
, RADEON_USAGE_READWRITE
,
2636 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
2637 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
2639 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
2640 radeon_emit(cs
, zb
->db_depth_info
); /* R_02803C_DB_DEPTH_INFO */
2641 radeon_emit(cs
, zb
->db_z_info
| /* R_028040_DB_Z_INFO */
2642 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
2643 radeon_emit(cs
, zb
->db_stencil_info
); /* R_028044_DB_STENCIL_INFO */
2644 radeon_emit(cs
, zb
->db_depth_base
); /* R_028048_DB_Z_READ_BASE */
2645 radeon_emit(cs
, zb
->db_stencil_base
); /* R_02804C_DB_STENCIL_READ_BASE */
2646 radeon_emit(cs
, zb
->db_depth_base
); /* R_028050_DB_Z_WRITE_BASE */
2647 radeon_emit(cs
, zb
->db_stencil_base
); /* R_028054_DB_STENCIL_WRITE_BASE */
2648 radeon_emit(cs
, zb
->db_depth_size
); /* R_028058_DB_DEPTH_SIZE */
2649 radeon_emit(cs
, zb
->db_depth_slice
); /* R_02805C_DB_DEPTH_SLICE */
2651 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
2652 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
2653 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
2655 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
2656 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
2657 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
2658 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* R_028040_DB_Z_INFO */
2659 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* R_028044_DB_STENCIL_INFO */
2662 /* Framebuffer dimensions. */
2663 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
2664 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
2665 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
2667 sctx
->framebuffer
.dirty_cbufs
= 0;
2668 sctx
->framebuffer
.dirty_zsbuf
= false;
2671 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
2672 struct r600_atom
*atom
)
2674 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2675 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
2677 /* Smoothing (only possible with nr_samples == 1) uses the same
2678 * sample locations as the MSAA it simulates.
2680 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
2681 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
2683 /* On Polaris, the small primitive filter uses the sample locations
2684 * even when MSAA is off, so we need to make sure they're set to 0.
2686 if (sctx
->b
.family
>= CHIP_POLARIS10
)
2687 nr_samples
= MAX2(nr_samples
, 1);
2689 if (nr_samples
>= 1 &&
2690 (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
)) {
2691 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
2692 cayman_emit_msaa_sample_locs(cs
, nr_samples
);
2695 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
2696 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2697 unsigned small_prim_filter_cntl
=
2698 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
2699 S_028830_LINE_FILTER_DISABLE(1); /* line bug */
2701 /* The alternative of setting sample locations to 0 would
2702 * require a DB flush to avoid Z errors, see
2703 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
2705 if (sctx
->framebuffer
.nr_samples
> 1 && rs
&& !rs
->multisample_enable
)
2706 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
2708 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
2709 small_prim_filter_cntl
);
2713 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
2715 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2716 unsigned num_tile_pipes
= sctx
->screen
->b
.info
.num_tile_pipes
;
2717 /* 33% faster rendering to linear color buffers */
2718 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
2719 unsigned sc_mode_cntl_1
=
2720 S_028A4C_WALK_SIZE(dst_is_linear
) |
2721 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
2722 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
2724 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
2725 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
2726 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
2727 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
2728 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
2729 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
2731 cayman_emit_msaa_config(cs
, sctx
->framebuffer
.nr_samples
,
2732 sctx
->ps_iter_samples
,
2733 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0,
2737 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
2739 struct si_context
*sctx
= (struct si_context
*)ctx
;
2741 if (sctx
->ps_iter_samples
== min_samples
)
2744 sctx
->ps_iter_samples
= min_samples
;
2745 sctx
->do_update_shaders
= true;
2747 if (sctx
->framebuffer
.nr_samples
> 1)
2748 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2756 * Build the sampler view descriptor for a buffer texture.
2757 * @param state 256-bit descriptor; only the high 128 bits are filled in
2760 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
2761 enum pipe_format format
,
2762 unsigned offset
, unsigned size
,
2765 const struct util_format_description
*desc
;
2768 unsigned num_records
;
2769 unsigned num_format
, data_format
;
2771 desc
= util_format_description(format
);
2772 first_non_void
= util_format_get_first_non_void_channel(format
);
2773 stride
= desc
->block
.bits
/ 8;
2774 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
2775 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
2777 num_records
= size
/ stride
;
2778 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
2780 if (screen
->b
.chip_class
>= VI
)
2781 num_records
*= stride
;
2784 state
[5] = S_008F04_STRIDE(stride
);
2785 state
[6] = num_records
;
2786 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
2787 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
2788 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
2789 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
2790 S_008F0C_NUM_FORMAT(num_format
) |
2791 S_008F0C_DATA_FORMAT(data_format
);
2795 * Build the sampler view descriptor for a texture.
2798 si_make_texture_descriptor(struct si_screen
*screen
,
2799 struct r600_texture
*tex
,
2801 enum pipe_texture_target target
,
2802 enum pipe_format pipe_format
,
2803 const unsigned char state_swizzle
[4],
2804 unsigned first_level
, unsigned last_level
,
2805 unsigned first_layer
, unsigned last_layer
,
2806 unsigned width
, unsigned height
, unsigned depth
,
2808 uint32_t *fmask_state
)
2810 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
2811 const struct util_format_description
*desc
;
2812 unsigned char swizzle
[4];
2814 unsigned num_format
, data_format
, type
;
2817 desc
= util_format_description(pipe_format
);
2819 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
2820 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
2821 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
2822 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
2824 switch (pipe_format
) {
2825 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2826 case PIPE_FORMAT_X32_S8X24_UINT
:
2827 case PIPE_FORMAT_X8Z24_UNORM
:
2828 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
2830 case PIPE_FORMAT_X24S8_UINT
:
2832 * X24S8 is implemented as an 8_8_8_8 data format, to
2833 * fix texture gathers. This affects at least
2834 * GL45-CTS.texture_cube_map_array.sampling on VI.
2836 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
2839 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
2842 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
2845 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
2847 switch (pipe_format
) {
2848 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
2849 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2852 if (first_non_void
< 0) {
2853 if (util_format_is_compressed(pipe_format
)) {
2854 switch (pipe_format
) {
2855 case PIPE_FORMAT_DXT1_SRGB
:
2856 case PIPE_FORMAT_DXT1_SRGBA
:
2857 case PIPE_FORMAT_DXT3_SRGBA
:
2858 case PIPE_FORMAT_DXT5_SRGBA
:
2859 case PIPE_FORMAT_BPTC_SRGBA
:
2860 case PIPE_FORMAT_ETC2_SRGB8
:
2861 case PIPE_FORMAT_ETC2_SRGB8A1
:
2862 case PIPE_FORMAT_ETC2_SRGBA8
:
2863 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2865 case PIPE_FORMAT_RGTC1_SNORM
:
2866 case PIPE_FORMAT_LATC1_SNORM
:
2867 case PIPE_FORMAT_RGTC2_SNORM
:
2868 case PIPE_FORMAT_LATC2_SNORM
:
2869 case PIPE_FORMAT_ETC2_R11_SNORM
:
2870 case PIPE_FORMAT_ETC2_RG11_SNORM
:
2871 /* implies float, so use SNORM/UNORM to determine
2872 whether data is signed or not */
2873 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
2874 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2877 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2880 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
2881 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2883 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2885 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
2886 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
2888 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2890 switch (desc
->channel
[first_non_void
].type
) {
2891 case UTIL_FORMAT_TYPE_FLOAT
:
2892 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
2894 case UTIL_FORMAT_TYPE_SIGNED
:
2895 if (desc
->channel
[first_non_void
].normalized
)
2896 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
2897 else if (desc
->channel
[first_non_void
].pure_integer
)
2898 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
2900 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
2902 case UTIL_FORMAT_TYPE_UNSIGNED
:
2903 if (desc
->channel
[first_non_void
].normalized
)
2904 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
2905 else if (desc
->channel
[first_non_void
].pure_integer
)
2906 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
2908 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
2913 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
2914 if (data_format
== ~0) {
2919 (res
->target
== PIPE_TEXTURE_CUBE
||
2920 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2921 res
->target
== PIPE_TEXTURE_3D
)) {
2922 /* For the purpose of shader images, treat cube maps and 3D
2923 * textures as 2D arrays. For 3D textures, the address
2924 * calculations for mipmaps are different, so we rely on the
2925 * caller to effectively disable mipmaps.
2927 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
2929 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
2931 type
= si_tex_dim(res
->target
, target
, res
->nr_samples
);
2934 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
2936 depth
= res
->array_size
;
2937 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
2938 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
2939 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
2940 depth
= res
->array_size
;
2941 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
2942 depth
= res
->array_size
/ 6;
2945 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
2946 S_008F14_NUM_FORMAT(num_format
));
2947 state
[2] = (S_008F18_WIDTH(width
- 1) |
2948 S_008F18_HEIGHT(height
- 1) |
2949 S_008F18_PERF_MOD(4));
2950 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
2951 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
2952 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
2953 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
2954 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
2956 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
2957 util_logbase2(res
->nr_samples
) :
2959 S_008F1C_POW2_PAD(res
->last_level
> 0) |
2960 S_008F1C_TYPE(type
));
2961 state
[4] = S_008F20_DEPTH(depth
- 1);
2962 state
[5] = (S_008F24_BASE_ARRAY(first_layer
) |
2963 S_008F24_LAST_ARRAY(last_layer
));
2967 if (tex
->dcc_offset
) {
2968 unsigned swap
= r600_translate_colorswap(pipe_format
, false);
2970 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
2972 /* The last dword is unused by hw. The shader uses it to clear
2973 * bits in the first dword of sampler state.
2975 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
2976 if (first_level
== last_level
)
2977 state
[7] = C_008F30_MAX_ANISO_RATIO
;
2979 state
[7] = 0xffffffff;
2983 /* Initialize the sampler view for FMASK. */
2984 if (tex
->fmask
.size
) {
2985 uint32_t fmask_format
;
2987 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
2989 switch (res
->nr_samples
) {
2991 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
2994 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
2997 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3001 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
3004 fmask_state
[0] = va
>> 8;
3005 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3006 S_008F14_DATA_FORMAT(fmask_format
) |
3007 S_008F14_NUM_FORMAT(V_008F14_IMG_NUM_FORMAT_UINT
);
3008 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3009 S_008F18_HEIGHT(height
- 1);
3010 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3011 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3012 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3013 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3014 S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
) |
3015 S_008F1C_TYPE(si_tex_dim(res
->target
, target
, 0));
3016 fmask_state
[4] = S_008F20_DEPTH(depth
- 1) |
3017 S_008F20_PITCH(tex
->fmask
.pitch_in_pixels
- 1);
3018 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
) |
3019 S_008F24_LAST_ARRAY(last_layer
);
3026 * Create a sampler view.
3028 * @param ctx context
3029 * @param texture texture
3030 * @param state sampler view template
3031 * @param width0 width0 override (for compressed textures as int)
3032 * @param height0 height0 override (for compressed textures as int)
3033 * @param force_level set the base address to the level (for compressed textures)
3035 struct pipe_sampler_view
*
3036 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3037 struct pipe_resource
*texture
,
3038 const struct pipe_sampler_view
*state
,
3039 unsigned width0
, unsigned height0
,
3040 unsigned force_level
)
3042 struct si_context
*sctx
= (struct si_context
*)ctx
;
3043 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3044 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3045 unsigned base_level
, first_level
, last_level
;
3046 unsigned char state_swizzle
[4];
3047 unsigned height
, depth
, width
;
3048 unsigned last_layer
= state
->u
.tex
.last_layer
;
3049 enum pipe_format pipe_format
;
3050 const struct radeon_surf_level
*surflevel
;
3055 /* initialize base object */
3056 view
->base
= *state
;
3057 view
->base
.texture
= NULL
;
3058 view
->base
.reference
.count
= 1;
3059 view
->base
.context
= ctx
;
3062 pipe_resource_reference(&view
->base
.texture
, texture
);
3064 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3065 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3066 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3067 state
->format
== PIPE_FORMAT_S8_UINT
)
3068 view
->is_stencil_sampler
= true;
3070 /* Buffer resource. */
3071 if (texture
->target
== PIPE_BUFFER
) {
3072 si_make_buffer_descriptor(sctx
->screen
,
3073 (struct r600_resource
*)texture
,
3075 state
->u
.buf
.offset
,
3081 state_swizzle
[0] = state
->swizzle_r
;
3082 state_swizzle
[1] = state
->swizzle_g
;
3083 state_swizzle
[2] = state
->swizzle_b
;
3084 state_swizzle
[3] = state
->swizzle_a
;
3087 first_level
= state
->u
.tex
.first_level
;
3088 last_level
= state
->u
.tex
.last_level
;
3091 depth
= texture
->depth0
;
3094 assert(force_level
== first_level
&&
3095 force_level
== last_level
);
3096 base_level
= force_level
;
3099 width
= u_minify(width
, force_level
);
3100 height
= u_minify(height
, force_level
);
3101 depth
= u_minify(depth
, force_level
);
3104 /* This is not needed if state trackers set last_layer correctly. */
3105 if (state
->target
== PIPE_TEXTURE_1D
||
3106 state
->target
== PIPE_TEXTURE_2D
||
3107 state
->target
== PIPE_TEXTURE_RECT
||
3108 state
->target
== PIPE_TEXTURE_CUBE
)
3109 last_layer
= state
->u
.tex
.first_layer
;
3111 /* Texturing with separate depth and stencil. */
3112 pipe_format
= state
->format
;
3114 /* Depth/stencil texturing sometimes needs separate texture. */
3115 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3116 if (!tmp
->flushed_depth_texture
&&
3117 !r600_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3118 pipe_resource_reference(&view
->base
.texture
, NULL
);
3123 assert(tmp
->flushed_depth_texture
);
3125 /* Override format for the case where the flushed texture
3126 * contains only Z or only S.
3128 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3129 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3131 tmp
= tmp
->flushed_depth_texture
;
3134 surflevel
= tmp
->surface
.level
;
3136 if (tmp
->db_compatible
) {
3137 if (!view
->is_stencil_sampler
)
3138 pipe_format
= tmp
->db_render_format
;
3140 switch (pipe_format
) {
3141 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3142 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3144 case PIPE_FORMAT_X8Z24_UNORM
:
3145 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3146 /* Z24 is always stored like this for DB
3149 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3151 case PIPE_FORMAT_X24S8_UINT
:
3152 case PIPE_FORMAT_S8X24_UINT
:
3153 case PIPE_FORMAT_X32_S8X24_UINT
:
3154 pipe_format
= PIPE_FORMAT_S8_UINT
;
3155 surflevel
= tmp
->surface
.stencil_level
;
3161 vi_dcc_disable_if_incompatible_format(&sctx
->b
, texture
,
3162 state
->u
.tex
.first_level
,
3165 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3166 state
->target
, pipe_format
, state_swizzle
,
3167 first_level
, last_level
,
3168 state
->u
.tex
.first_layer
, last_layer
,
3169 width
, height
, depth
,
3170 view
->state
, view
->fmask_state
);
3172 view
->base_level_info
= &surflevel
[base_level
];
3173 view
->base_level
= base_level
;
3174 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3178 static struct pipe_sampler_view
*
3179 si_create_sampler_view(struct pipe_context
*ctx
,
3180 struct pipe_resource
*texture
,
3181 const struct pipe_sampler_view
*state
)
3183 return si_create_sampler_view_custom(ctx
, texture
, state
,
3184 texture
? texture
->width0
: 0,
3185 texture
? texture
->height0
: 0, 0);
3188 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3189 struct pipe_sampler_view
*state
)
3191 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3193 pipe_resource_reference(&state
->texture
, NULL
);
3197 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3199 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3200 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3202 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3203 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3206 static bool sampler_state_needs_border_color(const struct pipe_sampler_state
*state
)
3208 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3209 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3211 return (state
->border_color
.ui
[0] || state
->border_color
.ui
[1] ||
3212 state
->border_color
.ui
[2] || state
->border_color
.ui
[3]) &&
3213 (wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) ||
3214 wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) ||
3215 wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
));
3218 static void *si_create_sampler_state(struct pipe_context
*ctx
,
3219 const struct pipe_sampler_state
*state
)
3221 struct si_context
*sctx
= (struct si_context
*)ctx
;
3222 struct r600_common_screen
*rscreen
= sctx
->b
.screen
;
3223 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
3224 unsigned border_color_type
, border_color_index
= 0;
3225 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
3226 : state
->max_anisotropy
;
3227 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
3233 if (!sampler_state_needs_border_color(state
))
3234 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3235 else if (state
->border_color
.f
[0] == 0 &&
3236 state
->border_color
.f
[1] == 0 &&
3237 state
->border_color
.f
[2] == 0 &&
3238 state
->border_color
.f
[3] == 0)
3239 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3240 else if (state
->border_color
.f
[0] == 0 &&
3241 state
->border_color
.f
[1] == 0 &&
3242 state
->border_color
.f
[2] == 0 &&
3243 state
->border_color
.f
[3] == 1)
3244 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3245 else if (state
->border_color
.f
[0] == 1 &&
3246 state
->border_color
.f
[1] == 1 &&
3247 state
->border_color
.f
[2] == 1 &&
3248 state
->border_color
.f
[3] == 1)
3249 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3253 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
3255 /* Check if the border has been uploaded already. */
3256 for (i
= 0; i
< sctx
->border_color_count
; i
++)
3257 if (memcmp(&sctx
->border_color_table
[i
], &state
->border_color
,
3258 sizeof(state
->border_color
)) == 0)
3261 if (i
>= SI_MAX_BORDER_COLORS
) {
3262 /* Getting 4096 unique border colors is very unlikely. */
3263 fprintf(stderr
, "radeonsi: The border color table is full. "
3264 "Any new border colors will be just black. "
3265 "Please file a bug.\n");
3266 border_color_type
= V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3268 if (i
== sctx
->border_color_count
) {
3269 /* Upload a new border color. */
3270 memcpy(&sctx
->border_color_table
[i
], &state
->border_color
,
3271 sizeof(state
->border_color
));
3272 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
3273 &state
->border_color
,
3274 sizeof(state
->border_color
));
3275 sctx
->border_color_count
++;
3278 border_color_index
= i
;
3283 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
3285 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
3286 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
3287 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
3288 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3289 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
3290 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
3291 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3292 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3293 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
3294 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
3295 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
3296 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
3297 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3298 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
3299 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
3300 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
3301 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
3302 S_008F38_MIP_POINT_PRECLAMP(1) |
3303 S_008F38_DISABLE_LSB_CEIL(1) |
3304 S_008F38_FILTER_PREC_FIX(1) |
3305 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
3306 rstate
->val
[3] = S_008F3C_BORDER_COLOR_PTR(border_color_index
) |
3307 S_008F3C_BORDER_COLOR_TYPE(border_color_type
);
3311 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
3313 struct si_context
*sctx
= (struct si_context
*)ctx
;
3315 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
3318 sctx
->sample_mask
.sample_mask
= sample_mask
;
3319 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
3322 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
3324 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3325 unsigned mask
= sctx
->sample_mask
.sample_mask
;
3327 /* Needed for line and polygon smoothing as well as for the Polaris
3328 * small primitive filter. We expect the state tracker to take care of
3331 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
3332 (mask
& 1 && sctx
->blitter
->running
));
3334 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3335 radeon_emit(cs
, mask
| (mask
<< 16));
3336 radeon_emit(cs
, mask
| (mask
<< 16));
3339 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
3342 struct si_sampler_state
*s
= state
;
3344 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
3351 * Vertex elements & buffers
3354 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
3356 const struct pipe_vertex_element
*elements
)
3358 struct si_vertex_element
*v
= CALLOC_STRUCT(si_vertex_element
);
3359 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
3362 assert(count
<= SI_MAX_ATTRIBS
);
3367 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
3369 for (i
= 0; i
< count
; ++i
) {
3370 const struct util_format_description
*desc
;
3371 const struct util_format_channel_description
*channel
;
3372 unsigned data_format
, num_format
;
3374 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
3375 unsigned char swizzle
[4];
3377 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
3382 if (!used
[vbo_index
]) {
3383 v
->first_vb_use_mask
|= 1 << i
;
3384 used
[vbo_index
] = true;
3387 desc
= util_format_description(elements
[i
].src_format
);
3388 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
3389 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
3390 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
3391 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
3392 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
3394 v
->format_size
[i
] = desc
->block
.bits
/ 8;
3396 /* The hardware always treats the 2-bit alpha channel as
3397 * unsigned, so a shader workaround is needed.
3399 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
) {
3400 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
3401 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_A2_SNORM
<< (4 * i
);
3402 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
3403 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_A2_SSCALED
<< (4 * i
);
3404 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
3405 /* This isn't actually used in OpenGL. */
3406 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_A2_SINT
<< (4 * i
);
3408 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
3409 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3410 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBX_32_FIXED
<< (4 * i
);
3412 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBA_32_FIXED
<< (4 * i
);
3413 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
3414 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
3415 if (channel
->normalized
) {
3416 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3417 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBX_32_SNORM
<< (4 * i
);
3419 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBA_32_SNORM
<< (4 * i
);
3421 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBA_32_SSCALED
<< (4 * i
);
3423 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
3424 if (channel
->normalized
) {
3425 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
3426 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBX_32_UNORM
<< (4 * i
);
3428 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBA_32_UNORM
<< (4 * i
);
3430 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBA_32_USCALED
<< (4 * i
);
3433 } else if (channel
&& channel
->size
== 64 &&
3434 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
3435 switch (desc
->nr_channels
) {
3438 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RG_64_FLOAT
<< (4 * i
);
3439 swizzle
[0] = PIPE_SWIZZLE_X
;
3440 swizzle
[1] = PIPE_SWIZZLE_Y
;
3441 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
3442 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
3445 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGB_64_FLOAT
<< (4 * i
);
3446 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
3447 swizzle
[1] = PIPE_SWIZZLE_Y
;
3448 swizzle
[2] = PIPE_SWIZZLE_0
;
3449 swizzle
[3] = PIPE_SWIZZLE_0
;
3452 v
->fix_fetch
|= (uint64_t)SI_FIX_FETCH_RGBA_64_FLOAT
<< (4 * i
);
3453 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
3454 swizzle
[1] = PIPE_SWIZZLE_Y
;
3455 swizzle
[2] = PIPE_SWIZZLE_Z
;
3456 swizzle
[3] = PIPE_SWIZZLE_W
;
3463 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3464 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3465 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3466 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3467 S_008F0C_NUM_FORMAT(num_format
) |
3468 S_008F0C_DATA_FORMAT(data_format
);
3470 /* We work around the fact that 8_8_8 and 16_16_16 data formats
3471 * do not exist by using the corresponding 4-component formats.
3472 * This requires a fixup of the descriptor for bounds checks.
3474 if (desc
->block
.bits
== 3 * 8 ||
3475 desc
->block
.bits
== 3 * 16) {
3476 v
->fix_size3
|= (desc
->block
.bits
/ 24) << (2 * i
);
3479 memcpy(v
->elements
, elements
, sizeof(struct pipe_vertex_element
) * count
);
3484 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
3486 struct si_context
*sctx
= (struct si_context
*)ctx
;
3487 struct si_vertex_element
*v
= (struct si_vertex_element
*)state
;
3489 sctx
->vertex_elements
= v
;
3490 sctx
->vertex_buffers_dirty
= true;
3491 sctx
->do_update_shaders
= true;
3494 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
3496 struct si_context
*sctx
= (struct si_context
*)ctx
;
3498 if (sctx
->vertex_elements
== state
)
3499 sctx
->vertex_elements
= NULL
;
3503 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
3504 unsigned start_slot
, unsigned count
,
3505 const struct pipe_vertex_buffer
*buffers
)
3507 struct si_context
*sctx
= (struct si_context
*)ctx
;
3508 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
3511 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
3514 for (i
= 0; i
< count
; i
++) {
3515 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
3516 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
3517 struct pipe_resource
*buf
= src
->buffer
;
3519 pipe_resource_reference(&dsti
->buffer
, buf
);
3520 dsti
->buffer_offset
= src
->buffer_offset
;
3521 dsti
->stride
= src
->stride
;
3522 r600_context_add_resource_size(ctx
, buf
);
3524 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
3527 for (i
= 0; i
< count
; i
++) {
3528 pipe_resource_reference(&dst
[i
].buffer
, NULL
);
3531 sctx
->vertex_buffers_dirty
= true;
3534 static void si_set_index_buffer(struct pipe_context
*ctx
,
3535 const struct pipe_index_buffer
*ib
)
3537 struct si_context
*sctx
= (struct si_context
*)ctx
;
3540 struct pipe_resource
*buf
= ib
->buffer
;
3542 pipe_resource_reference(&sctx
->index_buffer
.buffer
, buf
);
3543 memcpy(&sctx
->index_buffer
, ib
, sizeof(*ib
));
3544 r600_context_add_resource_size(ctx
, buf
);
3546 r600_resource(buf
)->bind_history
|= PIPE_BIND_INDEX_BUFFER
;
3548 pipe_resource_reference(&sctx
->index_buffer
.buffer
, NULL
);
3556 static void si_set_tess_state(struct pipe_context
*ctx
,
3557 const float default_outer_level
[4],
3558 const float default_inner_level
[2])
3560 struct si_context
*sctx
= (struct si_context
*)ctx
;
3561 struct pipe_constant_buffer cb
;
3564 memcpy(array
, default_outer_level
, sizeof(float) * 4);
3565 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
3568 cb
.user_buffer
= NULL
;
3569 cb
.buffer_size
= sizeof(array
);
3571 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
3572 (void*)array
, sizeof(array
),
3575 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
3576 pipe_resource_reference(&cb
.buffer
, NULL
);
3579 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
3581 struct si_context
*sctx
= (struct si_context
*)ctx
;
3583 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
|
3584 SI_CONTEXT_INV_GLOBAL_L2
|
3585 SI_CONTEXT_FLUSH_AND_INV_CB
;
3586 sctx
->framebuffer
.do_update_surf_dirtiness
= true;
3589 /* This only ensures coherency for shader image/buffer stores. */
3590 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
3592 struct si_context
*sctx
= (struct si_context
*)ctx
;
3594 /* Subsequent commands must wait for all shader invocations to
3596 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
3597 SI_CONTEXT_CS_PARTIAL_FLUSH
;
3599 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
3600 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
3601 SI_CONTEXT_INV_VMEM_L1
;
3603 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
3604 PIPE_BARRIER_SHADER_BUFFER
|
3605 PIPE_BARRIER_TEXTURE
|
3606 PIPE_BARRIER_IMAGE
|
3607 PIPE_BARRIER_STREAMOUT_BUFFER
|
3608 PIPE_BARRIER_GLOBAL_BUFFER
)) {
3609 /* As far as I can tell, L1 contents are written back to L2
3610 * automatically at end of shader, but the contents of other
3611 * L1 caches might still be stale. */
3612 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
3615 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
3616 /* Indices are read through TC L2 since VI.
3619 if (sctx
->screen
->b
.chip_class
<= CIK
)
3620 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
3623 if (flags
& PIPE_BARRIER_FRAMEBUFFER
)
3624 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
|
3625 SI_CONTEXT_FLUSH_AND_INV_DB
;
3627 if (flags
& (PIPE_BARRIER_FRAMEBUFFER
|
3628 PIPE_BARRIER_INDIRECT_BUFFER
))
3629 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
3632 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
3634 struct pipe_blend_state blend
;
3636 memset(&blend
, 0, sizeof(blend
));
3637 blend
.independent_blend_enable
= true;
3638 blend
.rt
[0].colormask
= 0xf;
3639 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
3642 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
3643 bool include_draw_vbo
)
3645 si_need_cs_space((struct si_context
*)ctx
);
3648 static void si_init_config(struct si_context
*sctx
);
3650 void si_init_state_functions(struct si_context
*sctx
)
3652 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
3653 si_init_external_atom(sctx
, &sctx
->b
.streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
3654 si_init_external_atom(sctx
, &sctx
->b
.streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
3655 si_init_external_atom(sctx
, &sctx
->b
.scissors
.atom
, &sctx
->atoms
.s
.scissors
);
3656 si_init_external_atom(sctx
, &sctx
->b
.viewports
.atom
, &sctx
->atoms
.s
.viewports
);
3658 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
3659 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
3660 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
3661 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
3662 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
3663 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
3664 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
3665 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
3666 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
3667 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
3669 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
3670 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
3671 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
3672 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
3674 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
3675 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
3676 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
3678 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
3679 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
3680 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
3682 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
3683 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
3684 sctx
->custom_blend_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
3685 sctx
->custom_blend_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
3686 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
3688 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
3689 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
3691 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
3692 sctx
->b
.b
.get_sample_position
= cayman_get_sample_position
;
3694 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
3695 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
3697 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
3698 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
3700 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
3702 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
3703 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
3704 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
3705 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
3706 sctx
->b
.b
.set_index_buffer
= si_set_index_buffer
;
3708 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
3709 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
3710 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
3711 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
3713 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
3714 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
3715 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
3716 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
3718 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
3720 si_init_config(sctx
);
3723 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen
*rscreen
)
3725 return (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
3728 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
3729 struct r600_texture
*rtex
,
3730 struct radeon_bo_metadata
*md
)
3732 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
3733 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
3734 static const unsigned char swizzle
[] = {
3740 uint32_t desc
[8], i
;
3741 bool is_array
= util_resource_is_array_texture(res
);
3743 /* DRM 2.x.x doesn't support this. */
3744 if (rscreen
->info
.drm_major
!= 3)
3747 assert(rtex
->dcc_separate_buffer
== NULL
);
3748 assert(rtex
->fmask
.size
== 0);
3750 /* Metadata image format format version 1:
3751 * [0] = 1 (metadata format identifier)
3752 * [1] = (VENDOR_ID << 16) | PCI_ID
3753 * [2:9] = image descriptor for the whole resource
3754 * [2] is always 0, because the base address is cleared
3755 * [9] is the DCC offset bits [39:8] from the beginning of
3757 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
3760 md
->metadata
[0] = 1; /* metadata image format version 1 */
3762 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
3763 md
->metadata
[1] = si_get_bo_metadata_word1(rscreen
);
3765 si_make_texture_descriptor(sscreen
, rtex
, true,
3766 res
->target
, res
->format
,
3767 swizzle
, 0, res
->last_level
, 0,
3768 is_array
? res
->array_size
- 1 : 0,
3769 res
->width0
, res
->height0
, res
->depth0
,
3772 si_set_mutable_tex_desc_fields(rtex
, &rtex
->surface
.level
[0], 0, 0,
3773 rtex
->surface
.blk_w
, false, desc
);
3775 /* Clear the base address and set the relative DCC offset. */
3777 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
3778 desc
[7] = rtex
->dcc_offset
>> 8;
3780 /* Dwords [2:9] contain the image descriptor. */
3781 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
3783 /* Dwords [10:..] contain the mipmap level offsets. */
3784 for (i
= 0; i
<= res
->last_level
; i
++)
3785 md
->metadata
[10+i
] = rtex
->surface
.level
[i
].offset
>> 8;
3787 md
->size_metadata
= (11 + res
->last_level
) * 4;
3790 static void si_apply_opaque_metadata(struct r600_common_screen
*rscreen
,
3791 struct r600_texture
*rtex
,
3792 struct radeon_bo_metadata
*md
)
3794 uint32_t *desc
= &md
->metadata
[2];
3796 if (rscreen
->chip_class
< VI
)
3799 /* Return if DCC is enabled. The texture should be set up with it
3802 if (md
->size_metadata
>= 11 * 4 &&
3803 md
->metadata
[0] != 0 &&
3804 md
->metadata
[1] == si_get_bo_metadata_word1(rscreen
) &&
3805 G_008F28_COMPRESSION_EN(desc
[6])) {
3806 assert(rtex
->dcc_offset
== ((uint64_t)desc
[7] << 8));
3810 /* Disable DCC. These are always set by texture_from_handle and must
3813 rtex
->dcc_offset
= 0;
3816 void si_init_screen_state_functions(struct si_screen
*sscreen
)
3818 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
3819 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
3820 sscreen
->b
.apply_opaque_metadata
= si_apply_opaque_metadata
;
3824 si_write_harvested_raster_configs(struct si_context
*sctx
,
3825 struct si_pm4_state
*pm4
,
3826 unsigned raster_config
,
3827 unsigned raster_config_1
)
3829 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
3830 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
3831 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
3832 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
3833 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
3834 unsigned rb_per_se
= num_rb
/ num_se
;
3835 unsigned se_mask
[4];
3838 se_mask
[0] = ((1 << rb_per_se
) - 1);
3839 se_mask
[1] = (se_mask
[0] << rb_per_se
);
3840 se_mask
[2] = (se_mask
[1] << rb_per_se
);
3841 se_mask
[3] = (se_mask
[2] << rb_per_se
);
3843 se_mask
[0] &= rb_mask
;
3844 se_mask
[1] &= rb_mask
;
3845 se_mask
[2] &= rb_mask
;
3846 se_mask
[3] &= rb_mask
;
3848 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
3849 assert(sh_per_se
== 1 || sh_per_se
== 2);
3850 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
3852 /* XXX: I can't figure out what the *_XSEL and *_YSEL
3853 * fields are for, so I'm leaving them as their default
3856 for (se
= 0; se
< num_se
; se
++) {
3857 unsigned raster_config_se
= raster_config
;
3858 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
3859 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
3860 int idx
= (se
/ 2) * 2;
3862 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
3863 raster_config_se
&= C_028350_SE_MAP
;
3865 if (!se_mask
[idx
]) {
3867 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
3870 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
3874 pkr0_mask
&= rb_mask
;
3875 pkr1_mask
&= rb_mask
;
3876 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
3877 raster_config_se
&= C_028350_PKR_MAP
;
3881 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
3884 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
3888 if (rb_per_se
>= 2) {
3889 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
3890 unsigned rb1_mask
= rb0_mask
<< 1;
3892 rb0_mask
&= rb_mask
;
3893 rb1_mask
&= rb_mask
;
3894 if (!rb0_mask
|| !rb1_mask
) {
3895 raster_config_se
&= C_028350_RB_MAP_PKR0
;
3899 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
3902 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
3906 if (rb_per_se
> 2) {
3907 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
3908 rb1_mask
= rb0_mask
<< 1;
3909 rb0_mask
&= rb_mask
;
3910 rb1_mask
&= rb_mask
;
3911 if (!rb0_mask
|| !rb1_mask
) {
3912 raster_config_se
&= C_028350_RB_MAP_PKR1
;
3916 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
3919 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
3925 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3926 if (sctx
->b
.chip_class
< CIK
)
3927 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3928 SE_INDEX(se
) | SH_BROADCAST_WRITES
|
3929 INSTANCE_BROADCAST_WRITES
);
3931 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3932 S_030800_SE_INDEX(se
) | S_030800_SH_BROADCAST_WRITES(1) |
3933 S_030800_INSTANCE_BROADCAST_WRITES(1));
3934 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
3937 /* GRBM_GFX_INDEX has a different offset on SI and CI+ */
3938 if (sctx
->b
.chip_class
< CIK
)
3939 si_pm4_set_reg(pm4
, GRBM_GFX_INDEX
,
3940 SE_BROADCAST_WRITES
| SH_BROADCAST_WRITES
|
3941 INSTANCE_BROADCAST_WRITES
);
3943 si_pm4_set_reg(pm4
, R_030800_GRBM_GFX_INDEX
,
3944 S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) |
3945 S_030800_INSTANCE_BROADCAST_WRITES(1));
3947 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
3948 (!se_mask
[2] && !se_mask
[3]))) {
3949 raster_config_1
&= C_028354_SE_PAIR_MAP
;
3951 if (!se_mask
[0] && !se_mask
[1]) {
3953 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
3956 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
3960 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
3964 static void si_init_config(struct si_context
*sctx
)
3966 struct si_screen
*sscreen
= sctx
->screen
;
3967 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
3968 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
3969 unsigned raster_config
, raster_config_1
;
3970 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
3971 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3976 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
3977 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
3978 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
3979 si_pm4_cmd_end(pm4
, false);
3981 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
3982 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
3984 /* FIXME calculate these values somehow ??? */
3985 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
3986 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
3987 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
3989 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
3990 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
3992 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
3993 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
3994 if (sctx
->b
.chip_class
< CIK
)
3995 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
3996 S_008A14_CLIP_VTX_REORDER_ENA(1));
3998 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
3999 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4001 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4003 switch (sctx
->screen
->b
.family
) {
4006 raster_config
= 0x2a00126a;
4007 raster_config_1
= 0x00000000;
4010 raster_config
= 0x0000124a;
4011 raster_config_1
= 0x00000000;
4014 raster_config
= 0x00000082;
4015 raster_config_1
= 0x00000000;
4018 raster_config
= 0x00000000;
4019 raster_config_1
= 0x00000000;
4022 raster_config
= 0x16000012;
4023 raster_config_1
= 0x00000000;
4026 raster_config
= 0x3a00161a;
4027 raster_config_1
= 0x0000002e;
4030 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4031 /* old kernels with old tiling config */
4032 raster_config
= 0x16000012;
4033 raster_config_1
= 0x0000002a;
4035 raster_config
= 0x3a00161a;
4036 raster_config_1
= 0x0000002e;
4039 case CHIP_POLARIS10
:
4040 raster_config
= 0x16000012;
4041 raster_config_1
= 0x0000002a;
4043 case CHIP_POLARIS11
:
4044 case CHIP_POLARIS12
:
4045 raster_config
= 0x16000012;
4046 raster_config_1
= 0x00000000;
4049 raster_config
= 0x16000012;
4050 raster_config_1
= 0x0000002a;
4054 raster_config
= 0x00000000;
4056 raster_config
= 0x00000002;
4057 raster_config_1
= 0x00000000;
4060 raster_config
= 0x00000002;
4061 raster_config_1
= 0x00000000;
4064 /* KV should be 0x00000002, but that causes problems with radeon */
4065 raster_config
= 0x00000000; /* 0x00000002 */
4066 raster_config_1
= 0x00000000;
4071 raster_config
= 0x00000000;
4072 raster_config_1
= 0x00000000;
4076 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4077 raster_config
= 0x00000000;
4078 raster_config_1
= 0x00000000;
4082 /* Always use the default config when all backends are enabled
4083 * (or when we failed to determine the enabled backends).
4085 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4086 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4088 if (sctx
->b
.chip_class
>= CIK
)
4089 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4092 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4095 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4096 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4097 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4098 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4099 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4100 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4101 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4103 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4104 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4105 S_028230_ER_TRI(0xA) |
4106 S_028230_ER_POINT(0xA) |
4107 S_028230_ER_RECT(0xA) |
4108 /* Required by DX10_DIAMOND_TEST_ENA: */
4109 S_028230_ER_LINE_LR(0x1A) |
4110 S_028230_ER_LINE_RL(0x26) |
4111 S_028230_ER_LINE_TB(0xA) |
4112 S_028230_ER_LINE_BT(0xA));
4113 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4114 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4115 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4116 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4117 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4118 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4119 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4121 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4122 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4123 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4125 if (sctx
->b
.chip_class
>= CIK
) {
4126 /* If this is 0, Bonaire can hang even if GS isn't being used.
4127 * Other chips are unaffected. These are suboptimal values,
4128 * but we don't use on-chip GS.
4130 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4131 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4132 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4134 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
, S_00B51C_CU_EN(0xffff));
4135 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
, 0);
4136 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
, S_00B31C_CU_EN(0xffff));
4137 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
, S_00B21C_CU_EN(0xffff));
4139 if (sscreen
->b
.info
.num_good_compute_units
/
4140 (sscreen
->b
.info
.max_se
* sscreen
->b
.info
.max_sh_per_se
) <= 4) {
4141 /* Too few available compute units per SH. Disallowing
4142 * VS to run on CU0 could hurt us more than late VS
4143 * allocation would help.
4145 * LATE_ALLOC_VS = 2 is the highest safe number.
4147 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xffff));
4148 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(2));
4150 /* Set LATE_ALLOC_VS == 31. It should be less than
4151 * the number of scratch waves. Limitations:
4152 * - VS can't execute on CU0.
4153 * - If HS writes outputs to LDS, LS can't execute on CU0.
4155 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
, S_00B118_CU_EN(0xfffe));
4156 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
, S_00B11C_LIMIT(31));
4159 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
, S_00B01C_CU_EN(0xffff));
4162 if (sctx
->b
.chip_class
>= VI
) {
4163 unsigned vgt_tess_distribution
;
4165 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
4166 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
4167 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
4168 if (sctx
->b
.family
< CHIP_POLARIS10
)
4169 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 30);
4170 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 32);
4172 vgt_tess_distribution
=
4173 S_028B50_ACCUM_ISOLINE(32) |
4174 S_028B50_ACCUM_TRI(11) |
4175 S_028B50_ACCUM_QUAD(11) |
4176 S_028B50_DONUT_SPLIT(16);
4178 /* Testing with Unigine Heaven extreme tesselation yielded best results
4179 * with TRAP_SPLIT = 3.
4181 if (sctx
->b
.family
== CHIP_FIJI
||
4182 sctx
->b
.family
>= CHIP_POLARIS10
)
4183 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
4185 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
4187 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
4188 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
4191 if (sctx
->b
.family
== CHIP_STONEY
)
4192 si_pm4_set_reg(pm4
, R_028C40_PA_SC_SHADER_CONTROL
, 0);
4194 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
4195 if (sctx
->b
.chip_class
>= CIK
)
4196 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
4197 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
4198 RADEON_PRIO_BORDER_COLORS
);
4200 si_pm4_upload_indirect_buffer(sctx
, pm4
);
4201 sctx
->init_config
= pm4
;