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radeonsi: move emission of PA_SU_VTX_CNTL into emit_guardband
[mesa.git] / src / gallium / drivers / radeonsi / si_state.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "gfx9d.h"
27 #include "si_query.h"
28
29 #include "util/u_dual_blend.h"
30 #include "util/u_format.h"
31 #include "util/u_format_s3tc.h"
32 #include "util/u_memory.h"
33 #include "util/u_resource.h"
34 #include "util/u_upload_mgr.h"
35
36 static unsigned si_map_swizzle(unsigned swizzle)
37 {
38 switch (swizzle) {
39 case PIPE_SWIZZLE_Y:
40 return V_008F0C_SQ_SEL_Y;
41 case PIPE_SWIZZLE_Z:
42 return V_008F0C_SQ_SEL_Z;
43 case PIPE_SWIZZLE_W:
44 return V_008F0C_SQ_SEL_W;
45 case PIPE_SWIZZLE_0:
46 return V_008F0C_SQ_SEL_0;
47 case PIPE_SWIZZLE_1:
48 return V_008F0C_SQ_SEL_1;
49 default: /* PIPE_SWIZZLE_X */
50 return V_008F0C_SQ_SEL_X;
51 }
52 }
53
54 /* 12.4 fixed-point */
55 static unsigned si_pack_float_12p4(float x)
56 {
57 return x <= 0 ? 0 :
58 x >= 4096 ? 0xffff : x * 16;
59 }
60
61 /*
62 * Inferred framebuffer and blender state.
63 *
64 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
65 * if there is not enough PS outputs.
66 */
67 static void si_emit_cb_render_state(struct si_context *sctx)
68 {
69 struct radeon_cmdbuf *cs = sctx->gfx_cs;
70 struct si_state_blend *blend = sctx->queued.named.blend;
71 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
72 * but you never know. */
73 uint32_t cb_target_mask = sctx->framebuffer.colorbuf_enabled_4bit;
74 unsigned i;
75
76 if (blend)
77 cb_target_mask &= blend->cb_target_mask;
78
79 /* Avoid a hang that happens when dual source blending is enabled
80 * but there is not enough color outputs. This is undefined behavior,
81 * so disable color writes completely.
82 *
83 * Reproducible with Unigine Heaven 4.0 and drirc missing.
84 */
85 if (blend && blend->dual_src_blend &&
86 sctx->ps_shader.cso &&
87 (sctx->ps_shader.cso->info.colors_written & 0x3) != 0x3)
88 cb_target_mask = 0;
89
90 radeon_opt_set_context_reg(sctx, R_028238_CB_TARGET_MASK,
91 SI_TRACKED_CB_TARGET_MASK, cb_target_mask);
92
93 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
94 * I think we don't have to do anything between IBs.
95 */
96 if (sctx->screen->dfsm_allowed &&
97 sctx->last_cb_target_mask != cb_target_mask) {
98 sctx->last_cb_target_mask = cb_target_mask;
99
100 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
101 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
102 }
103
104 if (sctx->chip_class >= VI) {
105 /* DCC MSAA workaround for blending.
106 * Alternatively, we can set CB_COLORi_DCC_CONTROL.OVERWRITE_-
107 * COMBINER_DISABLE, but that would be more complicated.
108 */
109 bool oc_disable = (sctx->chip_class == VI ||
110 sctx->chip_class == GFX9) &&
111 blend &&
112 blend->blend_enable_4bit & cb_target_mask &&
113 sctx->framebuffer.nr_samples >= 2;
114
115 radeon_opt_set_context_reg(
116 sctx, R_028424_CB_DCC_CONTROL,
117 SI_TRACKED_CB_DCC_CONTROL,
118 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
119 S_028424_OVERWRITE_COMBINER_WATERMARK(4) |
120 S_028424_OVERWRITE_COMBINER_DISABLE(oc_disable));
121 }
122
123 /* RB+ register settings. */
124 if (sctx->screen->rbplus_allowed) {
125 unsigned spi_shader_col_format =
126 sctx->ps_shader.cso ?
127 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format : 0;
128 unsigned sx_ps_downconvert = 0;
129 unsigned sx_blend_opt_epsilon = 0;
130 unsigned sx_blend_opt_control = 0;
131
132 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
133 struct si_surface *surf =
134 (struct si_surface*)sctx->framebuffer.state.cbufs[i];
135 unsigned format, swap, spi_format, colormask;
136 bool has_alpha, has_rgb;
137
138 if (!surf)
139 continue;
140
141 format = G_028C70_FORMAT(surf->cb_color_info);
142 swap = G_028C70_COMP_SWAP(surf->cb_color_info);
143 spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
144 colormask = (cb_target_mask >> (i * 4)) & 0xf;
145
146 /* Set if RGB and A are present. */
147 has_alpha = !G_028C74_FORCE_DST_ALPHA_1(surf->cb_color_attrib);
148
149 if (format == V_028C70_COLOR_8 ||
150 format == V_028C70_COLOR_16 ||
151 format == V_028C70_COLOR_32)
152 has_rgb = !has_alpha;
153 else
154 has_rgb = true;
155
156 /* Check the colormask and export format. */
157 if (!(colormask & (PIPE_MASK_RGBA & ~PIPE_MASK_A)))
158 has_rgb = false;
159 if (!(colormask & PIPE_MASK_A))
160 has_alpha = false;
161
162 if (spi_format == V_028714_SPI_SHADER_ZERO) {
163 has_rgb = false;
164 has_alpha = false;
165 }
166
167 /* Disable value checking for disabled channels. */
168 if (!has_rgb)
169 sx_blend_opt_control |= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
170 if (!has_alpha)
171 sx_blend_opt_control |= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
172
173 /* Enable down-conversion for 32bpp and smaller formats. */
174 switch (format) {
175 case V_028C70_COLOR_8:
176 case V_028C70_COLOR_8_8:
177 case V_028C70_COLOR_8_8_8_8:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
180 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
181 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
182 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
183 sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << (i * 4);
184 }
185 break;
186
187 case V_028C70_COLOR_5_6_5:
188 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
189 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
190 sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << (i * 4);
191 }
192 break;
193
194 case V_028C70_COLOR_1_5_5_5:
195 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
196 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_1_5_5_5 << (i * 4);
197 sx_blend_opt_epsilon |= V_028758_5BIT_FORMAT << (i * 4);
198 }
199 break;
200
201 case V_028C70_COLOR_4_4_4_4:
202 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
203 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_4_4_4_4 << (i * 4);
204 sx_blend_opt_epsilon |= V_028758_4BIT_FORMAT << (i * 4);
205 }
206 break;
207
208 case V_028C70_COLOR_32:
209 if (swap == V_028C70_SWAP_STD &&
210 spi_format == V_028714_SPI_SHADER_32_R)
211 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_R << (i * 4);
212 else if (swap == V_028C70_SWAP_ALT_REV &&
213 spi_format == V_028714_SPI_SHADER_32_AR)
214 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_32_A << (i * 4);
215 break;
216
217 case V_028C70_COLOR_16:
218 case V_028C70_COLOR_16_16:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format == V_028714_SPI_SHADER_UNORM16_ABGR ||
221 spi_format == V_028714_SPI_SHADER_SNORM16_ABGR ||
222 spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
223 spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
224 if (swap == V_028C70_SWAP_STD ||
225 swap == V_028C70_SWAP_STD_REV)
226 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_GR << (i * 4);
227 else
228 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_16_16_AR << (i * 4);
229 }
230 break;
231
232 case V_028C70_COLOR_10_11_11:
233 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
234 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_10_11_11 << (i * 4);
235 sx_blend_opt_epsilon |= V_028758_11BIT_FORMAT << (i * 4);
236 }
237 break;
238
239 case V_028C70_COLOR_2_10_10_10:
240 if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
241 sx_ps_downconvert |= V_028754_SX_RT_EXPORT_2_10_10_10 << (i * 4);
242 sx_blend_opt_epsilon |= V_028758_10BIT_FORMAT << (i * 4);
243 }
244 break;
245 }
246 }
247
248 /* SX_PS_DOWNCONVERT, SX_BLEND_OPT_EPSILON, SX_BLEND_OPT_CONTROL */
249 radeon_opt_set_context_reg3(sctx, R_028754_SX_PS_DOWNCONVERT,
250 SI_TRACKED_SX_PS_DOWNCONVERT,
251 sx_ps_downconvert, sx_blend_opt_epsilon,
252 sx_blend_opt_control);
253 }
254 }
255
256 /*
257 * Blender functions
258 */
259
260 static uint32_t si_translate_blend_function(int blend_func)
261 {
262 switch (blend_func) {
263 case PIPE_BLEND_ADD:
264 return V_028780_COMB_DST_PLUS_SRC;
265 case PIPE_BLEND_SUBTRACT:
266 return V_028780_COMB_SRC_MINUS_DST;
267 case PIPE_BLEND_REVERSE_SUBTRACT:
268 return V_028780_COMB_DST_MINUS_SRC;
269 case PIPE_BLEND_MIN:
270 return V_028780_COMB_MIN_DST_SRC;
271 case PIPE_BLEND_MAX:
272 return V_028780_COMB_MAX_DST_SRC;
273 default:
274 PRINT_ERR("Unknown blend function %d\n", blend_func);
275 assert(0);
276 break;
277 }
278 return 0;
279 }
280
281 static uint32_t si_translate_blend_factor(int blend_fact)
282 {
283 switch (blend_fact) {
284 case PIPE_BLENDFACTOR_ONE:
285 return V_028780_BLEND_ONE;
286 case PIPE_BLENDFACTOR_SRC_COLOR:
287 return V_028780_BLEND_SRC_COLOR;
288 case PIPE_BLENDFACTOR_SRC_ALPHA:
289 return V_028780_BLEND_SRC_ALPHA;
290 case PIPE_BLENDFACTOR_DST_ALPHA:
291 return V_028780_BLEND_DST_ALPHA;
292 case PIPE_BLENDFACTOR_DST_COLOR:
293 return V_028780_BLEND_DST_COLOR;
294 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
295 return V_028780_BLEND_SRC_ALPHA_SATURATE;
296 case PIPE_BLENDFACTOR_CONST_COLOR:
297 return V_028780_BLEND_CONSTANT_COLOR;
298 case PIPE_BLENDFACTOR_CONST_ALPHA:
299 return V_028780_BLEND_CONSTANT_ALPHA;
300 case PIPE_BLENDFACTOR_ZERO:
301 return V_028780_BLEND_ZERO;
302 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
303 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
304 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
305 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
306 case PIPE_BLENDFACTOR_INV_DST_ALPHA:
307 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
308 case PIPE_BLENDFACTOR_INV_DST_COLOR:
309 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
310 case PIPE_BLENDFACTOR_INV_CONST_COLOR:
311 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
312 case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
313 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
314 case PIPE_BLENDFACTOR_SRC1_COLOR:
315 return V_028780_BLEND_SRC1_COLOR;
316 case PIPE_BLENDFACTOR_SRC1_ALPHA:
317 return V_028780_BLEND_SRC1_ALPHA;
318 case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
319 return V_028780_BLEND_INV_SRC1_COLOR;
320 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
321 return V_028780_BLEND_INV_SRC1_ALPHA;
322 default:
323 PRINT_ERR("Bad blend factor %d not supported!\n", blend_fact);
324 assert(0);
325 break;
326 }
327 return 0;
328 }
329
330 static uint32_t si_translate_blend_opt_function(int blend_func)
331 {
332 switch (blend_func) {
333 case PIPE_BLEND_ADD:
334 return V_028760_OPT_COMB_ADD;
335 case PIPE_BLEND_SUBTRACT:
336 return V_028760_OPT_COMB_SUBTRACT;
337 case PIPE_BLEND_REVERSE_SUBTRACT:
338 return V_028760_OPT_COMB_REVSUBTRACT;
339 case PIPE_BLEND_MIN:
340 return V_028760_OPT_COMB_MIN;
341 case PIPE_BLEND_MAX:
342 return V_028760_OPT_COMB_MAX;
343 default:
344 return V_028760_OPT_COMB_BLEND_DISABLED;
345 }
346 }
347
348 static uint32_t si_translate_blend_opt_factor(int blend_fact, bool is_alpha)
349 {
350 switch (blend_fact) {
351 case PIPE_BLENDFACTOR_ZERO:
352 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
353 case PIPE_BLENDFACTOR_ONE:
354 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
355 case PIPE_BLENDFACTOR_SRC_COLOR:
356 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
357 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
358 case PIPE_BLENDFACTOR_INV_SRC_COLOR:
359 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
360 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
361 case PIPE_BLENDFACTOR_SRC_ALPHA:
362 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
363 case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
364 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
365 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
366 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
367 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
368 default:
369 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
370 }
371 }
372
373 static void si_blend_check_commutativity(struct si_screen *sscreen,
374 struct si_state_blend *blend,
375 enum pipe_blend_func func,
376 enum pipe_blendfactor src,
377 enum pipe_blendfactor dst,
378 unsigned chanmask)
379 {
380 /* Src factor is allowed when it does not depend on Dst */
381 static const uint32_t src_allowed =
382 (1u << PIPE_BLENDFACTOR_ONE) |
383 (1u << PIPE_BLENDFACTOR_SRC_COLOR) |
384 (1u << PIPE_BLENDFACTOR_SRC_ALPHA) |
385 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE) |
386 (1u << PIPE_BLENDFACTOR_CONST_COLOR) |
387 (1u << PIPE_BLENDFACTOR_CONST_ALPHA) |
388 (1u << PIPE_BLENDFACTOR_SRC1_COLOR) |
389 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA) |
390 (1u << PIPE_BLENDFACTOR_ZERO) |
391 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR) |
392 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA) |
393 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR) |
394 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA);
397
398 if (dst == PIPE_BLENDFACTOR_ONE &&
399 (src_allowed & (1u << src))) {
400 /* Addition is commutative, but floating point addition isn't
401 * associative: subtle changes can be introduced via different
402 * rounding.
403 *
404 * Out-of-order is also non-deterministic, which means that
405 * this breaks OpenGL invariance requirements. So only enable
406 * out-of-order additive blending if explicitly allowed by a
407 * setting.
408 */
409 if (func == PIPE_BLEND_MAX || func == PIPE_BLEND_MIN ||
410 (func == PIPE_BLEND_ADD && sscreen->commutative_blend_add))
411 blend->commutative_4bit |= chanmask;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == PIPE_BLENDFACTOR_ZERO) {
425 *src_factor = PIPE_BLENDFACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == PIPE_BLEND_SUBTRACT)
430 *func = PIPE_BLEND_REVERSE_SUBTRACT;
431 else if (*func == PIPE_BLEND_REVERSE_SUBTRACT)
432 *func = PIPE_BLEND_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == PIPE_BLENDFACTOR_DST_COLOR ||
439 factor == PIPE_BLENDFACTOR_DST_ALPHA ||
440 factor == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
441 factor == PIPE_BLENDFACTOR_INV_DST_ALPHA ||
442 factor == PIPE_BLENDFACTOR_INV_DST_COLOR;
443 }
444
445 static void *si_create_blend_state_mode(struct pipe_context *ctx,
446 const struct pipe_blend_state *state,
447 unsigned mode)
448 {
449 struct si_context *sctx = (struct si_context*)ctx;
450 struct si_state_blend *blend = CALLOC_STRUCT(si_state_blend);
451 struct si_pm4_state *pm4 = &blend->pm4;
452 uint32_t sx_mrt_blend_opt[8] = {0};
453 uint32_t color_control = 0;
454
455 if (!blend)
456 return NULL;
457
458 blend->alpha_to_coverage = state->alpha_to_coverage;
459 blend->alpha_to_one = state->alpha_to_one;
460 blend->dual_src_blend = util_blend_state_is_dual(state, 0);
461 blend->logicop_enable = state->logicop_enable;
462
463 if (state->logicop_enable) {
464 color_control |= S_028808_ROP3(state->logicop_func | (state->logicop_func << 4));
465 } else {
466 color_control |= S_028808_ROP3(0xcc);
467 }
468
469 si_pm4_set_reg(pm4, R_028B70_DB_ALPHA_TO_MASK,
470 S_028B70_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
471 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
472 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
473 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
474 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
475
476 if (state->alpha_to_coverage)
477 blend->need_src_alpha_4bit |= 0xf;
478
479 blend->cb_target_mask = 0;
480 blend->cb_target_enabled_4bit = 0;
481
482 for (int i = 0; i < 8; i++) {
483 /* state->rt entries > 0 only written if independent blending */
484 const int j = state->independent_blend_enable ? i : 0;
485
486 unsigned eqRGB = state->rt[j].rgb_func;
487 unsigned srcRGB = state->rt[j].rgb_src_factor;
488 unsigned dstRGB = state->rt[j].rgb_dst_factor;
489 unsigned eqA = state->rt[j].alpha_func;
490 unsigned srcA = state->rt[j].alpha_src_factor;
491 unsigned dstA = state->rt[j].alpha_dst_factor;
492
493 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
494 unsigned blend_cntl = 0;
495
496 sx_mrt_blend_opt[i] =
497 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) |
498 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
499
500 /* Only set dual source blending for MRT0 to avoid a hang. */
501 if (i >= 1 && blend->dual_src_blend) {
502 /* Vulkan does this for dual source blending. */
503 if (i == 1)
504 blend_cntl |= S_028780_ENABLE(1);
505
506 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
507 continue;
508 }
509
510 /* Only addition and subtraction equations are supported with
511 * dual source blending.
512 */
513 if (blend->dual_src_blend &&
514 (eqRGB == PIPE_BLEND_MIN || eqRGB == PIPE_BLEND_MAX ||
515 eqA == PIPE_BLEND_MIN || eqA == PIPE_BLEND_MAX)) {
516 assert(!"Unsupported equation for dual source blending");
517 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
518 continue;
519 }
520
521 /* cb_render_state will disable unused ones */
522 blend->cb_target_mask |= (unsigned)state->rt[j].colormask << (4 * i);
523 if (state->rt[j].colormask)
524 blend->cb_target_enabled_4bit |= 0xf << (4 * i);
525
526 if (!state->rt[j].colormask || !state->rt[j].blend_enable) {
527 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
528 continue;
529 }
530
531 si_blend_check_commutativity(sctx->screen, blend,
532 eqRGB, srcRGB, dstRGB, 0x7 << (4 * i));
533 si_blend_check_commutativity(sctx->screen, blend,
534 eqA, srcA, dstA, 0x8 << (4 * i));
535
536 /* Blending optimizations for RB+.
537 * These transformations don't change the behavior.
538 *
539 * First, get rid of DST in the blend factors:
540 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
541 */
542 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
543 PIPE_BLENDFACTOR_DST_COLOR,
544 PIPE_BLENDFACTOR_SRC_COLOR);
545 si_blend_remove_dst(&eqA, &srcA, &dstA,
546 PIPE_BLENDFACTOR_DST_COLOR,
547 PIPE_BLENDFACTOR_SRC_COLOR);
548 si_blend_remove_dst(&eqA, &srcA, &dstA,
549 PIPE_BLENDFACTOR_DST_ALPHA,
550 PIPE_BLENDFACTOR_SRC_ALPHA);
551
552 /* Look up the ideal settings from tables. */
553 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
554 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
555 srcA_opt = si_translate_blend_opt_factor(srcA, true);
556 dstA_opt = si_translate_blend_opt_factor(dstA, true);
557
558 /* Handle interdependencies. */
559 if (si_blend_factor_uses_dst(srcRGB))
560 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
561 if (si_blend_factor_uses_dst(srcA))
562 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
563
564 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE &&
565 (dstRGB == PIPE_BLENDFACTOR_ZERO ||
566 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
567 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE))
568 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
569
570 /* Set the final value. */
571 sx_mrt_blend_opt[i] =
572 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
573 S_028760_COLOR_DST_OPT(dstRGB_opt) |
574 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
575 S_028760_ALPHA_SRC_OPT(srcA_opt) |
576 S_028760_ALPHA_DST_OPT(dstA_opt) |
577 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
578
579 /* Set blend state. */
580 blend_cntl |= S_028780_ENABLE(1);
581 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
582 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
583 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
584
585 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
586 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
587 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
588 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
589 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
590 }
591 si_pm4_set_reg(pm4, R_028780_CB_BLEND0_CONTROL + i * 4, blend_cntl);
592
593 blend->blend_enable_4bit |= 0xfu << (i * 4);
594
595 /* This is only important for formats without alpha. */
596 if (srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
597 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA ||
598 srcRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
599 dstRGB == PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE ||
600 srcRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA ||
601 dstRGB == PIPE_BLENDFACTOR_INV_SRC_ALPHA)
602 blend->need_src_alpha_4bit |= 0xfu << (i * 4);
603 }
604
605 if (blend->cb_target_mask) {
606 color_control |= S_028808_MODE(mode);
607 } else {
608 color_control |= S_028808_MODE(V_028808_CB_DISABLE);
609 }
610
611 if (sctx->screen->rbplus_allowed) {
612 /* Disable RB+ blend optimizations for dual source blending.
613 * Vulkan does this.
614 */
615 if (blend->dual_src_blend) {
616 for (int i = 0; i < 8; i++) {
617 sx_mrt_blend_opt[i] =
618 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
619 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
620 }
621 }
622
623 for (int i = 0; i < 8; i++)
624 si_pm4_set_reg(pm4, R_028760_SX_MRT0_BLEND_OPT + i * 4,
625 sx_mrt_blend_opt[i]);
626
627 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
628 if (blend->dual_src_blend || state->logicop_enable ||
629 mode == V_028808_CB_RESOLVE)
630 color_control |= S_028808_DISABLE_DUAL_QUAD(1);
631 }
632
633 si_pm4_set_reg(pm4, R_028808_CB_COLOR_CONTROL, color_control);
634 return blend;
635 }
636
637 static void *si_create_blend_state(struct pipe_context *ctx,
638 const struct pipe_blend_state *state)
639 {
640 return si_create_blend_state_mode(ctx, state, V_028808_CB_NORMAL);
641 }
642
643 static void si_bind_blend_state(struct pipe_context *ctx, void *state)
644 {
645 struct si_context *sctx = (struct si_context *)ctx;
646 struct si_state_blend *old_blend = sctx->queued.named.blend;
647 struct si_state_blend *blend = (struct si_state_blend *)state;
648
649 if (!state)
650 return;
651
652 si_pm4_bind_state(sctx, blend, state);
653
654 if (!old_blend ||
655 old_blend->cb_target_mask != blend->cb_target_mask ||
656 old_blend->dual_src_blend != blend->dual_src_blend ||
657 (old_blend->blend_enable_4bit != blend->blend_enable_4bit &&
658 sctx->framebuffer.nr_samples >= 2 &&
659 sctx->screen->dcc_msaa_allowed))
660 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
661
662 if (!old_blend ||
663 old_blend->cb_target_mask != blend->cb_target_mask ||
664 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
665 old_blend->alpha_to_one != blend->alpha_to_one ||
666 old_blend->dual_src_blend != blend->dual_src_blend ||
667 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
668 old_blend->need_src_alpha_4bit != blend->need_src_alpha_4bit)
669 sctx->do_update_shaders = true;
670
671 if (sctx->screen->dpbb_allowed &&
672 (!old_blend ||
673 old_blend->alpha_to_coverage != blend->alpha_to_coverage ||
674 old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
675 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit))
676 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
677
678 if (sctx->screen->has_out_of_order_rast &&
679 (!old_blend ||
680 (old_blend->blend_enable_4bit != blend->blend_enable_4bit ||
681 old_blend->cb_target_enabled_4bit != blend->cb_target_enabled_4bit ||
682 old_blend->commutative_4bit != blend->commutative_4bit ||
683 old_blend->logicop_enable != blend->logicop_enable)))
684 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
685 }
686
687 static void si_delete_blend_state(struct pipe_context *ctx, void *state)
688 {
689 struct si_context *sctx = (struct si_context *)ctx;
690 si_pm4_delete_state(sctx, blend, (struct si_state_blend *)state);
691 }
692
693 static void si_set_blend_color(struct pipe_context *ctx,
694 const struct pipe_blend_color *state)
695 {
696 struct si_context *sctx = (struct si_context *)ctx;
697 static const struct pipe_blend_color zeros;
698
699 sctx->blend_color.state = *state;
700 sctx->blend_color.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
701 si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
702 }
703
704 static void si_emit_blend_color(struct si_context *sctx)
705 {
706 struct radeon_cmdbuf *cs = sctx->gfx_cs;
707
708 radeon_set_context_reg_seq(cs, R_028414_CB_BLEND_RED, 4);
709 radeon_emit_array(cs, (uint32_t*)sctx->blend_color.state.color, 4);
710 }
711
712 /*
713 * Clipping
714 */
715
716 static void si_set_clip_state(struct pipe_context *ctx,
717 const struct pipe_clip_state *state)
718 {
719 struct si_context *sctx = (struct si_context *)ctx;
720 struct pipe_constant_buffer cb;
721 static const struct pipe_clip_state zeros;
722
723 if (memcmp(&sctx->clip_state.state, state, sizeof(*state)) == 0)
724 return;
725
726 sctx->clip_state.state = *state;
727 sctx->clip_state.any_nonzeros = memcmp(state, &zeros, sizeof(*state)) != 0;
728 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_state);
729
730 cb.buffer = NULL;
731 cb.user_buffer = state->ucp;
732 cb.buffer_offset = 0;
733 cb.buffer_size = 4*4*8;
734 si_set_rw_buffer(sctx, SI_VS_CONST_CLIP_PLANES, &cb);
735 pipe_resource_reference(&cb.buffer, NULL);
736 }
737
738 static void si_emit_clip_state(struct si_context *sctx)
739 {
740 struct radeon_cmdbuf *cs = sctx->gfx_cs;
741
742 radeon_set_context_reg_seq(cs, R_0285BC_PA_CL_UCP_0_X, 6*4);
743 radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
744 }
745
746 static void si_emit_clip_regs(struct si_context *sctx)
747 {
748 struct si_shader *vs = si_get_vs_state(sctx);
749 struct si_shader_selector *vs_sel = vs->selector;
750 struct tgsi_shader_info *info = &vs_sel->info;
751 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
752 unsigned window_space =
753 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
754 unsigned clipdist_mask = vs_sel->clipdist_mask;
755 unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SIX_BITS;
756 unsigned culldist_mask = vs_sel->culldist_mask;
757 unsigned total_mask;
758
759 if (vs->key.opt.clip_disable) {
760 assert(!info->culldist_writemask);
761 clipdist_mask = 0;
762 culldist_mask = 0;
763 }
764 total_mask = clipdist_mask | culldist_mask;
765
766 /* Clip distances on points have no effect, so need to be implemented
767 * as cull distances. This applies for the clipvertex case as well.
768 *
769 * Setting this for primitives other than points should have no adverse
770 * effects.
771 */
772 clipdist_mask &= rs->clip_plane_enable;
773 culldist_mask |= clipdist_mask;
774
775 radeon_opt_set_context_reg(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
776 SI_TRACKED_PA_CL_VS_OUT_CNTL,
777 vs_sel->pa_cl_vs_out_cntl |
778 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0F) != 0) |
779 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xF0) != 0) |
780 clipdist_mask | (culldist_mask << 8));
781 radeon_opt_set_context_reg(sctx, R_028810_PA_CL_CLIP_CNTL,
782 SI_TRACKED_PA_CL_CLIP_CNTL,
783 rs->pa_cl_clip_cntl |
784 ucp_mask |
785 S_028810_CLIP_DISABLE(window_space));
786 }
787
788 /*
789 * inferred state between framebuffer and rasterizer
790 */
791 static void si_update_poly_offset_state(struct si_context *sctx)
792 {
793 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
794
795 if (!rs || !rs->uses_poly_offset || !sctx->framebuffer.state.zsbuf) {
796 si_pm4_bind_state(sctx, poly_offset, NULL);
797 return;
798 }
799
800 /* Use the user format, not db_render_format, so that the polygon
801 * offset behaves as expected by applications.
802 */
803 switch (sctx->framebuffer.state.zsbuf->texture->format) {
804 case PIPE_FORMAT_Z16_UNORM:
805 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[0]);
806 break;
807 default: /* 24-bit */
808 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[1]);
809 break;
810 case PIPE_FORMAT_Z32_FLOAT:
811 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
812 si_pm4_bind_state(sctx, poly_offset, &rs->pm4_poly_offset[2]);
813 break;
814 }
815 }
816
817 /*
818 * Rasterizer
819 */
820
821 static uint32_t si_translate_fill(uint32_t func)
822 {
823 switch(func) {
824 case PIPE_POLYGON_MODE_FILL:
825 return V_028814_X_DRAW_TRIANGLES;
826 case PIPE_POLYGON_MODE_LINE:
827 return V_028814_X_DRAW_LINES;
828 case PIPE_POLYGON_MODE_POINT:
829 return V_028814_X_DRAW_POINTS;
830 default:
831 assert(0);
832 return V_028814_X_DRAW_POINTS;
833 }
834 }
835
836 static void *si_create_rs_state(struct pipe_context *ctx,
837 const struct pipe_rasterizer_state *state)
838 {
839 struct si_screen *sscreen = ((struct si_context *)ctx)->screen;
840 struct si_state_rasterizer *rs = CALLOC_STRUCT(si_state_rasterizer);
841 struct si_pm4_state *pm4 = &rs->pm4;
842 unsigned tmp, i;
843 float psize_min, psize_max;
844
845 if (!rs) {
846 return NULL;
847 }
848
849 rs->scissor_enable = state->scissor;
850 rs->clip_halfz = state->clip_halfz;
851 rs->two_side = state->light_twoside;
852 rs->multisample_enable = state->multisample;
853 rs->force_persample_interp = state->force_persample_interp;
854 rs->clip_plane_enable = state->clip_plane_enable;
855 rs->half_pixel_center = state->half_pixel_center;
856 rs->line_stipple_enable = state->line_stipple_enable;
857 rs->poly_stipple_enable = state->poly_stipple_enable;
858 rs->line_smooth = state->line_smooth;
859 rs->line_width = state->line_width;
860 rs->poly_smooth = state->poly_smooth;
861 rs->uses_poly_offset = state->offset_point || state->offset_line ||
862 state->offset_tri;
863 rs->clamp_fragment_color = state->clamp_fragment_color;
864 rs->clamp_vertex_color = state->clamp_vertex_color;
865 rs->flatshade = state->flatshade;
866 rs->sprite_coord_enable = state->sprite_coord_enable;
867 rs->rasterizer_discard = state->rasterizer_discard;
868 rs->pa_sc_line_stipple = state->line_stipple_enable ?
869 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
870 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
871 rs->pa_cl_clip_cntl =
872 S_028810_DX_CLIP_SPACE_DEF(state->clip_halfz) |
873 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip_near) |
874 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip_far) |
875 S_028810_DX_RASTERIZATION_KILL(state->rasterizer_discard) |
876 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
877
878 si_pm4_set_reg(pm4, R_0286D4_SPI_INTERP_CONTROL_0,
879 S_0286D4_FLAT_SHADE_ENA(1) |
880 S_0286D4_PNT_SPRITE_ENA(state->point_quad_rasterization) |
881 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
882 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
883 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
884 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
885 S_0286D4_PNT_SPRITE_TOP_1(state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT));
886
887 /* point size 12.4 fixed point */
888 tmp = (unsigned)(state->point_size * 8.0);
889 si_pm4_set_reg(pm4, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
890
891 if (state->point_size_per_vertex) {
892 psize_min = util_get_min_point_size(state);
893 psize_max = 8192;
894 } else {
895 /* Force the point size to be as if the vertex output was disabled. */
896 psize_min = state->point_size;
897 psize_max = state->point_size;
898 }
899 rs->max_point_size = psize_max;
900
901 /* Divide by two, because 0.5 = 1 pixel. */
902 si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
903 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
904 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
905
906 si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
907 S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
908 si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
909 S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable) |
910 S_028A48_MSAA_ENABLE(state->multisample ||
911 state->poly_smooth ||
912 state->line_smooth) |
913 S_028A48_VPORT_SCISSOR_ENABLE(1) |
914 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen->info.chip_class >= GFX9));
915
916 si_pm4_set_reg(pm4, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
917 si_pm4_set_reg(pm4, R_028814_PA_SU_SC_MODE_CNTL,
918 S_028814_PROVOKING_VTX_LAST(!state->flatshade_first) |
919 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
920 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
921 S_028814_FACE(!state->front_ccw) |
922 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state, state->fill_front)) |
923 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state, state->fill_back)) |
924 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_point || state->offset_line) |
925 S_028814_POLY_MODE(state->fill_front != PIPE_POLYGON_MODE_FILL ||
926 state->fill_back != PIPE_POLYGON_MODE_FILL) |
927 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state->fill_front)) |
928 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state->fill_back)));
929
930 if (!rs->uses_poly_offset)
931 return rs;
932
933 rs->pm4_poly_offset = CALLOC(3, sizeof(struct si_pm4_state));
934 if (!rs->pm4_poly_offset) {
935 FREE(rs);
936 return NULL;
937 }
938
939 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
940 for (i = 0; i < 3; i++) {
941 struct si_pm4_state *pm4 = &rs->pm4_poly_offset[i];
942 float offset_units = state->offset_units;
943 float offset_scale = state->offset_scale * 16.0f;
944 uint32_t pa_su_poly_offset_db_fmt_cntl = 0;
945
946 if (!state->offset_units_unscaled) {
947 switch (i) {
948 case 0: /* 16-bit zbuffer */
949 offset_units *= 4.0f;
950 pa_su_poly_offset_db_fmt_cntl =
951 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
952 break;
953 case 1: /* 24-bit zbuffer */
954 offset_units *= 2.0f;
955 pa_su_poly_offset_db_fmt_cntl =
956 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
957 break;
958 case 2: /* 32-bit zbuffer */
959 offset_units *= 1.0f;
960 pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
961 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
962 break;
963 }
964 }
965
966 si_pm4_set_reg(pm4, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
967 fui(offset_scale));
968 si_pm4_set_reg(pm4, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
969 fui(offset_units));
970 si_pm4_set_reg(pm4, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
971 fui(offset_scale));
972 si_pm4_set_reg(pm4, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
973 fui(offset_units));
974 si_pm4_set_reg(pm4, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
975 pa_su_poly_offset_db_fmt_cntl);
976 }
977
978 return rs;
979 }
980
981 static void si_bind_rs_state(struct pipe_context *ctx, void *state)
982 {
983 struct si_context *sctx = (struct si_context *)ctx;
984 struct si_state_rasterizer *old_rs =
985 (struct si_state_rasterizer*)sctx->queued.named.rasterizer;
986 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
987
988 if (!state)
989 return;
990
991 if (!old_rs || old_rs->multisample_enable != rs->multisample_enable) {
992 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
993
994 /* Update the small primitive filter workaround if necessary. */
995 if (sctx->screen->has_msaa_sample_loc_bug &&
996 sctx->framebuffer.nr_samples > 1)
997 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
998 }
999
1000 sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
1001 sctx->current_vs_state |= S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
1002
1003 si_pm4_bind_state(sctx, rasterizer, rs);
1004 si_update_poly_offset_state(sctx);
1005
1006 if (!old_rs ||
1007 old_rs->scissor_enable != rs->scissor_enable) {
1008 sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1009 si_mark_atom_dirty(sctx, &sctx->atoms.s.scissors);
1010 }
1011
1012 if (!old_rs ||
1013 old_rs->line_width != rs->line_width ||
1014 old_rs->max_point_size != rs->max_point_size ||
1015 old_rs->half_pixel_center != rs->half_pixel_center)
1016 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1017
1018 if (!old_rs ||
1019 old_rs->clip_halfz != rs->clip_halfz) {
1020 sctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
1021 si_mark_atom_dirty(sctx, &sctx->atoms.s.viewports);
1022 }
1023
1024 if (!old_rs ||
1025 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1026 old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
1027 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
1028
1029 sctx->ia_multi_vgt_param_key.u.line_stipple_enabled =
1030 rs->line_stipple_enable;
1031
1032 if (!old_rs ||
1033 old_rs->clip_plane_enable != rs->clip_plane_enable ||
1034 old_rs->rasterizer_discard != rs->rasterizer_discard ||
1035 old_rs->sprite_coord_enable != rs->sprite_coord_enable ||
1036 old_rs->flatshade != rs->flatshade ||
1037 old_rs->two_side != rs->two_side ||
1038 old_rs->multisample_enable != rs->multisample_enable ||
1039 old_rs->poly_stipple_enable != rs->poly_stipple_enable ||
1040 old_rs->poly_smooth != rs->poly_smooth ||
1041 old_rs->line_smooth != rs->line_smooth ||
1042 old_rs->clamp_fragment_color != rs->clamp_fragment_color ||
1043 old_rs->force_persample_interp != rs->force_persample_interp)
1044 sctx->do_update_shaders = true;
1045 }
1046
1047 static void si_delete_rs_state(struct pipe_context *ctx, void *state)
1048 {
1049 struct si_context *sctx = (struct si_context *)ctx;
1050 struct si_state_rasterizer *rs = (struct si_state_rasterizer *)state;
1051
1052 if (sctx->queued.named.rasterizer == state)
1053 si_pm4_bind_state(sctx, poly_offset, NULL);
1054
1055 FREE(rs->pm4_poly_offset);
1056 si_pm4_delete_state(sctx, rasterizer, rs);
1057 }
1058
1059 /*
1060 * infeered state between dsa and stencil ref
1061 */
1062 static void si_emit_stencil_ref(struct si_context *sctx)
1063 {
1064 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1065 struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
1066 struct si_dsa_stencil_ref_part *dsa = &sctx->stencil_ref.dsa_part;
1067
1068 radeon_set_context_reg_seq(cs, R_028430_DB_STENCILREFMASK, 2);
1069 radeon_emit(cs, S_028430_STENCILTESTVAL(ref->ref_value[0]) |
1070 S_028430_STENCILMASK(dsa->valuemask[0]) |
1071 S_028430_STENCILWRITEMASK(dsa->writemask[0]) |
1072 S_028430_STENCILOPVAL(1));
1073 radeon_emit(cs, S_028434_STENCILTESTVAL_BF(ref->ref_value[1]) |
1074 S_028434_STENCILMASK_BF(dsa->valuemask[1]) |
1075 S_028434_STENCILWRITEMASK_BF(dsa->writemask[1]) |
1076 S_028434_STENCILOPVAL_BF(1));
1077 }
1078
1079 static void si_set_stencil_ref(struct pipe_context *ctx,
1080 const struct pipe_stencil_ref *state)
1081 {
1082 struct si_context *sctx = (struct si_context *)ctx;
1083
1084 if (memcmp(&sctx->stencil_ref.state, state, sizeof(*state)) == 0)
1085 return;
1086
1087 sctx->stencil_ref.state = *state;
1088 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1089 }
1090
1091
1092 /*
1093 * DSA
1094 */
1095
1096 static uint32_t si_translate_stencil_op(int s_op)
1097 {
1098 switch (s_op) {
1099 case PIPE_STENCIL_OP_KEEP:
1100 return V_02842C_STENCIL_KEEP;
1101 case PIPE_STENCIL_OP_ZERO:
1102 return V_02842C_STENCIL_ZERO;
1103 case PIPE_STENCIL_OP_REPLACE:
1104 return V_02842C_STENCIL_REPLACE_TEST;
1105 case PIPE_STENCIL_OP_INCR:
1106 return V_02842C_STENCIL_ADD_CLAMP;
1107 case PIPE_STENCIL_OP_DECR:
1108 return V_02842C_STENCIL_SUB_CLAMP;
1109 case PIPE_STENCIL_OP_INCR_WRAP:
1110 return V_02842C_STENCIL_ADD_WRAP;
1111 case PIPE_STENCIL_OP_DECR_WRAP:
1112 return V_02842C_STENCIL_SUB_WRAP;
1113 case PIPE_STENCIL_OP_INVERT:
1114 return V_02842C_STENCIL_INVERT;
1115 default:
1116 PRINT_ERR("Unknown stencil op %d", s_op);
1117 assert(0);
1118 break;
1119 }
1120 return 0;
1121 }
1122
1123 static bool si_dsa_writes_stencil(const struct pipe_stencil_state *s)
1124 {
1125 return s->enabled && s->writemask &&
1126 (s->fail_op != PIPE_STENCIL_OP_KEEP ||
1127 s->zfail_op != PIPE_STENCIL_OP_KEEP ||
1128 s->zpass_op != PIPE_STENCIL_OP_KEEP);
1129 }
1130
1131 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op)
1132 {
1133 /* REPLACE is normally order invariant, except when the stencil
1134 * reference value is written by the fragment shader. Tracking this
1135 * interaction does not seem worth the effort, so be conservative. */
1136 return op != PIPE_STENCIL_OP_INCR &&
1137 op != PIPE_STENCIL_OP_DECR &&
1138 op != PIPE_STENCIL_OP_REPLACE;
1139 }
1140
1141 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1142 * invariant in the sense that the set of passing fragments as well as the
1143 * final stencil buffer result does not depend on the order of fragments. */
1144 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state *state)
1145 {
1146 return !state->enabled || !state->writemask ||
1147 /* The following assumes that Z writes are disabled. */
1148 (state->func == PIPE_FUNC_ALWAYS &&
1149 si_order_invariant_stencil_op(state->zpass_op) &&
1150 si_order_invariant_stencil_op(state->zfail_op)) ||
1151 (state->func == PIPE_FUNC_NEVER &&
1152 si_order_invariant_stencil_op(state->fail_op));
1153 }
1154
1155 static void *si_create_dsa_state(struct pipe_context *ctx,
1156 const struct pipe_depth_stencil_alpha_state *state)
1157 {
1158 struct si_context *sctx = (struct si_context *)ctx;
1159 struct si_state_dsa *dsa = CALLOC_STRUCT(si_state_dsa);
1160 struct si_pm4_state *pm4 = &dsa->pm4;
1161 unsigned db_depth_control;
1162 uint32_t db_stencil_control = 0;
1163
1164 if (!dsa) {
1165 return NULL;
1166 }
1167
1168 dsa->stencil_ref.valuemask[0] = state->stencil[0].valuemask;
1169 dsa->stencil_ref.valuemask[1] = state->stencil[1].valuemask;
1170 dsa->stencil_ref.writemask[0] = state->stencil[0].writemask;
1171 dsa->stencil_ref.writemask[1] = state->stencil[1].writemask;
1172
1173 db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
1174 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
1175 S_028800_ZFUNC(state->depth.func) |
1176 S_028800_DEPTH_BOUNDS_ENABLE(state->depth.bounds_test);
1177
1178 /* stencil */
1179 if (state->stencil[0].enabled) {
1180 db_depth_control |= S_028800_STENCIL_ENABLE(1);
1181 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func);
1182 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(state->stencil[0].fail_op));
1183 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(state->stencil[0].zpass_op));
1184 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(state->stencil[0].zfail_op));
1185
1186 if (state->stencil[1].enabled) {
1187 db_depth_control |= S_028800_BACKFACE_ENABLE(1);
1188 db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func);
1189 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state->stencil[1].fail_op));
1190 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state->stencil[1].zpass_op));
1191 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state->stencil[1].zfail_op));
1192 }
1193 }
1194
1195 /* alpha */
1196 if (state->alpha.enabled) {
1197 dsa->alpha_func = state->alpha.func;
1198
1199 si_pm4_set_reg(pm4, R_00B030_SPI_SHADER_USER_DATA_PS_0 +
1200 SI_SGPR_ALPHA_REF * 4, fui(state->alpha.ref_value));
1201 } else {
1202 dsa->alpha_func = PIPE_FUNC_ALWAYS;
1203 }
1204
1205 si_pm4_set_reg(pm4, R_028800_DB_DEPTH_CONTROL, db_depth_control);
1206 if (state->stencil[0].enabled)
1207 si_pm4_set_reg(pm4, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
1208 if (state->depth.bounds_test) {
1209 si_pm4_set_reg(pm4, R_028020_DB_DEPTH_BOUNDS_MIN, fui(state->depth.bounds_min));
1210 si_pm4_set_reg(pm4, R_028024_DB_DEPTH_BOUNDS_MAX, fui(state->depth.bounds_max));
1211 }
1212
1213 dsa->depth_enabled = state->depth.enabled;
1214 dsa->depth_write_enabled = state->depth.enabled &&
1215 state->depth.writemask;
1216 dsa->stencil_enabled = state->stencil[0].enabled;
1217 dsa->stencil_write_enabled = state->stencil[0].enabled &&
1218 (si_dsa_writes_stencil(&state->stencil[0]) ||
1219 si_dsa_writes_stencil(&state->stencil[1]));
1220 dsa->db_can_write = dsa->depth_write_enabled ||
1221 dsa->stencil_write_enabled;
1222
1223 bool zfunc_is_ordered =
1224 state->depth.func == PIPE_FUNC_NEVER ||
1225 state->depth.func == PIPE_FUNC_LESS ||
1226 state->depth.func == PIPE_FUNC_LEQUAL ||
1227 state->depth.func == PIPE_FUNC_GREATER ||
1228 state->depth.func == PIPE_FUNC_GEQUAL;
1229
1230 bool nozwrite_and_order_invariant_stencil =
1231 !dsa->db_can_write ||
1232 (!dsa->depth_write_enabled &&
1233 si_order_invariant_stencil_state(&state->stencil[0]) &&
1234 si_order_invariant_stencil_state(&state->stencil[1]));
1235
1236 dsa->order_invariance[1].zs =
1237 nozwrite_and_order_invariant_stencil ||
1238 (!dsa->stencil_write_enabled && zfunc_is_ordered);
1239 dsa->order_invariance[0].zs = !dsa->depth_write_enabled || zfunc_is_ordered;
1240
1241 dsa->order_invariance[1].pass_set =
1242 nozwrite_and_order_invariant_stencil ||
1243 (!dsa->stencil_write_enabled &&
1244 (state->depth.func == PIPE_FUNC_ALWAYS ||
1245 state->depth.func == PIPE_FUNC_NEVER));
1246 dsa->order_invariance[0].pass_set =
1247 !dsa->depth_write_enabled ||
1248 (state->depth.func == PIPE_FUNC_ALWAYS ||
1249 state->depth.func == PIPE_FUNC_NEVER);
1250
1251 dsa->order_invariance[1].pass_last =
1252 sctx->screen->assume_no_z_fights &&
1253 !dsa->stencil_write_enabled &&
1254 dsa->depth_write_enabled && zfunc_is_ordered;
1255 dsa->order_invariance[0].pass_last =
1256 sctx->screen->assume_no_z_fights &&
1257 dsa->depth_write_enabled && zfunc_is_ordered;
1258
1259 return dsa;
1260 }
1261
1262 static void si_bind_dsa_state(struct pipe_context *ctx, void *state)
1263 {
1264 struct si_context *sctx = (struct si_context *)ctx;
1265 struct si_state_dsa *old_dsa = sctx->queued.named.dsa;
1266 struct si_state_dsa *dsa = state;
1267
1268 if (!state)
1269 return;
1270
1271 si_pm4_bind_state(sctx, dsa, dsa);
1272
1273 if (memcmp(&dsa->stencil_ref, &sctx->stencil_ref.dsa_part,
1274 sizeof(struct si_dsa_stencil_ref_part)) != 0) {
1275 sctx->stencil_ref.dsa_part = dsa->stencil_ref;
1276 si_mark_atom_dirty(sctx, &sctx->atoms.s.stencil_ref);
1277 }
1278
1279 if (!old_dsa || old_dsa->alpha_func != dsa->alpha_func)
1280 sctx->do_update_shaders = true;
1281
1282 if (sctx->screen->dpbb_allowed &&
1283 (!old_dsa ||
1284 (old_dsa->depth_enabled != dsa->depth_enabled ||
1285 old_dsa->stencil_enabled != dsa->stencil_enabled ||
1286 old_dsa->db_can_write != dsa->db_can_write)))
1287 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
1288
1289 if (sctx->screen->has_out_of_order_rast &&
1290 (!old_dsa ||
1291 memcmp(old_dsa->order_invariance, dsa->order_invariance,
1292 sizeof(old_dsa->order_invariance))))
1293 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1294 }
1295
1296 static void si_delete_dsa_state(struct pipe_context *ctx, void *state)
1297 {
1298 struct si_context *sctx = (struct si_context *)ctx;
1299 si_pm4_delete_state(sctx, dsa, (struct si_state_dsa *)state);
1300 }
1301
1302 static void *si_create_db_flush_dsa(struct si_context *sctx)
1303 {
1304 struct pipe_depth_stencil_alpha_state dsa = {};
1305
1306 return sctx->b.create_depth_stencil_alpha_state(&sctx->b, &dsa);
1307 }
1308
1309 /* DB RENDER STATE */
1310
1311 static void si_set_active_query_state(struct pipe_context *ctx, boolean enable)
1312 {
1313 struct si_context *sctx = (struct si_context*)ctx;
1314
1315 /* Pipeline stat & streamout queries. */
1316 if (enable) {
1317 sctx->flags &= ~SI_CONTEXT_STOP_PIPELINE_STATS;
1318 sctx->flags |= SI_CONTEXT_START_PIPELINE_STATS;
1319 } else {
1320 sctx->flags &= ~SI_CONTEXT_START_PIPELINE_STATS;
1321 sctx->flags |= SI_CONTEXT_STOP_PIPELINE_STATS;
1322 }
1323
1324 /* Occlusion queries. */
1325 if (sctx->occlusion_queries_disabled != !enable) {
1326 sctx->occlusion_queries_disabled = !enable;
1327 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1328 }
1329 }
1330
1331 void si_set_occlusion_query_state(struct si_context *sctx,
1332 bool old_perfect_enable)
1333 {
1334 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
1335
1336 bool perfect_enable = sctx->num_perfect_occlusion_queries != 0;
1337
1338 if (perfect_enable != old_perfect_enable)
1339 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
1340 }
1341
1342 void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
1343 {
1344 st->saved_compute = sctx->cs_shader_state.program;
1345
1346 si_get_pipe_constant_buffer(sctx, PIPE_SHADER_COMPUTE, 0, &st->saved_const0);
1347 si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
1348 }
1349
1350 static void si_emit_db_render_state(struct si_context *sctx)
1351 {
1352 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1353 unsigned db_shader_control, db_render_control, db_count_control;
1354
1355 /* DB_RENDER_CONTROL */
1356 if (sctx->dbcb_depth_copy_enabled ||
1357 sctx->dbcb_stencil_copy_enabled) {
1358 db_render_control =
1359 S_028000_DEPTH_COPY(sctx->dbcb_depth_copy_enabled) |
1360 S_028000_STENCIL_COPY(sctx->dbcb_stencil_copy_enabled) |
1361 S_028000_COPY_CENTROID(1) |
1362 S_028000_COPY_SAMPLE(sctx->dbcb_copy_sample);
1363 } else if (sctx->db_flush_depth_inplace || sctx->db_flush_stencil_inplace) {
1364 db_render_control =
1365 S_028000_DEPTH_COMPRESS_DISABLE(sctx->db_flush_depth_inplace) |
1366 S_028000_STENCIL_COMPRESS_DISABLE(sctx->db_flush_stencil_inplace);
1367 } else {
1368 db_render_control =
1369 S_028000_DEPTH_CLEAR_ENABLE(sctx->db_depth_clear) |
1370 S_028000_STENCIL_CLEAR_ENABLE(sctx->db_stencil_clear);
1371 }
1372
1373 /* DB_COUNT_CONTROL (occlusion queries) */
1374 if (sctx->num_occlusion_queries > 0 &&
1375 !sctx->occlusion_queries_disabled) {
1376 bool perfect = sctx->num_perfect_occlusion_queries > 0;
1377
1378 if (sctx->chip_class >= CIK) {
1379 unsigned log_sample_rate = sctx->framebuffer.log_samples;
1380
1381 /* Stoney doesn't increment occlusion query counters
1382 * if the sample rate is 16x. Use 8x sample rate instead.
1383 */
1384 if (sctx->family == CHIP_STONEY)
1385 log_sample_rate = MIN2(log_sample_rate, 3);
1386
1387 db_count_control =
1388 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1389 S_028004_SAMPLE_RATE(log_sample_rate) |
1390 S_028004_ZPASS_ENABLE(1) |
1391 S_028004_SLICE_EVEN_ENABLE(1) |
1392 S_028004_SLICE_ODD_ENABLE(1);
1393 } else {
1394 db_count_control =
1395 S_028004_PERFECT_ZPASS_COUNTS(perfect) |
1396 S_028004_SAMPLE_RATE(sctx->framebuffer.log_samples);
1397 }
1398 } else {
1399 /* Disable occlusion queries. */
1400 if (sctx->chip_class >= CIK) {
1401 db_count_control = 0;
1402 } else {
1403 db_count_control = S_028004_ZPASS_INCREMENT_DISABLE(1);
1404 }
1405 }
1406
1407 radeon_opt_set_context_reg2(sctx, R_028000_DB_RENDER_CONTROL,
1408 SI_TRACKED_DB_RENDER_CONTROL, db_render_control,
1409 db_count_control);
1410
1411 /* DB_RENDER_OVERRIDE2 */
1412 radeon_opt_set_context_reg(sctx, R_028010_DB_RENDER_OVERRIDE2,
1413 SI_TRACKED_DB_RENDER_OVERRIDE2,
1414 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx->db_depth_disable_expclear) |
1415 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx->db_stencil_disable_expclear) |
1416 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx->framebuffer.nr_samples >= 4));
1417
1418 db_shader_control = sctx->ps_db_shader_control;
1419
1420 /* Bug workaround for smoothing (overrasterization) on SI. */
1421 if (sctx->chip_class == SI && sctx->smoothing_enabled) {
1422 db_shader_control &= C_02880C_Z_ORDER;
1423 db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z);
1424 }
1425
1426 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1427 if (!rs->multisample_enable)
1428 db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
1429
1430 if (sctx->screen->has_rbplus &&
1431 !sctx->screen->rbplus_allowed)
1432 db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);
1433
1434 radeon_opt_set_context_reg(sctx, R_02880C_DB_SHADER_CONTROL,
1435 SI_TRACKED_DB_SHADER_CONTROL, db_shader_control);
1436 }
1437
1438 /*
1439 * format translation
1440 */
1441 static uint32_t si_translate_colorformat(enum pipe_format format)
1442 {
1443 const struct util_format_description *desc = util_format_description(format);
1444 if (!desc)
1445 return V_028C70_COLOR_INVALID;
1446
1447 #define HAS_SIZE(x,y,z,w) \
1448 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1449 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1450
1451 if (format == PIPE_FORMAT_R11G11B10_FLOAT) /* isn't plain */
1452 return V_028C70_COLOR_10_11_11;
1453
1454 if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN)
1455 return V_028C70_COLOR_INVALID;
1456
1457 /* hw cannot support mixed formats (except depth/stencil, since
1458 * stencil is not written to). */
1459 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1460 return V_028C70_COLOR_INVALID;
1461
1462 switch (desc->nr_channels) {
1463 case 1:
1464 switch (desc->channel[0].size) {
1465 case 8:
1466 return V_028C70_COLOR_8;
1467 case 16:
1468 return V_028C70_COLOR_16;
1469 case 32:
1470 return V_028C70_COLOR_32;
1471 }
1472 break;
1473 case 2:
1474 if (desc->channel[0].size == desc->channel[1].size) {
1475 switch (desc->channel[0].size) {
1476 case 8:
1477 return V_028C70_COLOR_8_8;
1478 case 16:
1479 return V_028C70_COLOR_16_16;
1480 case 32:
1481 return V_028C70_COLOR_32_32;
1482 }
1483 } else if (HAS_SIZE(8,24,0,0)) {
1484 return V_028C70_COLOR_24_8;
1485 } else if (HAS_SIZE(24,8,0,0)) {
1486 return V_028C70_COLOR_8_24;
1487 }
1488 break;
1489 case 3:
1490 if (HAS_SIZE(5,6,5,0)) {
1491 return V_028C70_COLOR_5_6_5;
1492 } else if (HAS_SIZE(32,8,24,0)) {
1493 return V_028C70_COLOR_X24_8_32_FLOAT;
1494 }
1495 break;
1496 case 4:
1497 if (desc->channel[0].size == desc->channel[1].size &&
1498 desc->channel[0].size == desc->channel[2].size &&
1499 desc->channel[0].size == desc->channel[3].size) {
1500 switch (desc->channel[0].size) {
1501 case 4:
1502 return V_028C70_COLOR_4_4_4_4;
1503 case 8:
1504 return V_028C70_COLOR_8_8_8_8;
1505 case 16:
1506 return V_028C70_COLOR_16_16_16_16;
1507 case 32:
1508 return V_028C70_COLOR_32_32_32_32;
1509 }
1510 } else if (HAS_SIZE(5,5,5,1)) {
1511 return V_028C70_COLOR_1_5_5_5;
1512 } else if (HAS_SIZE(1,5,5,5)) {
1513 return V_028C70_COLOR_5_5_5_1;
1514 } else if (HAS_SIZE(10,10,10,2)) {
1515 return V_028C70_COLOR_2_10_10_10;
1516 }
1517 break;
1518 }
1519 return V_028C70_COLOR_INVALID;
1520 }
1521
1522 static uint32_t si_colorformat_endian_swap(uint32_t colorformat)
1523 {
1524 if (SI_BIG_ENDIAN) {
1525 switch(colorformat) {
1526 /* 8-bit buffers. */
1527 case V_028C70_COLOR_8:
1528 return V_028C70_ENDIAN_NONE;
1529
1530 /* 16-bit buffers. */
1531 case V_028C70_COLOR_5_6_5:
1532 case V_028C70_COLOR_1_5_5_5:
1533 case V_028C70_COLOR_4_4_4_4:
1534 case V_028C70_COLOR_16:
1535 case V_028C70_COLOR_8_8:
1536 return V_028C70_ENDIAN_8IN16;
1537
1538 /* 32-bit buffers. */
1539 case V_028C70_COLOR_8_8_8_8:
1540 case V_028C70_COLOR_2_10_10_10:
1541 case V_028C70_COLOR_8_24:
1542 case V_028C70_COLOR_24_8:
1543 case V_028C70_COLOR_16_16:
1544 return V_028C70_ENDIAN_8IN32;
1545
1546 /* 64-bit buffers. */
1547 case V_028C70_COLOR_16_16_16_16:
1548 return V_028C70_ENDIAN_8IN16;
1549
1550 case V_028C70_COLOR_32_32:
1551 return V_028C70_ENDIAN_8IN32;
1552
1553 /* 128-bit buffers. */
1554 case V_028C70_COLOR_32_32_32_32:
1555 return V_028C70_ENDIAN_8IN32;
1556 default:
1557 return V_028C70_ENDIAN_NONE; /* Unsupported. */
1558 }
1559 } else {
1560 return V_028C70_ENDIAN_NONE;
1561 }
1562 }
1563
1564 static uint32_t si_translate_dbformat(enum pipe_format format)
1565 {
1566 switch (format) {
1567 case PIPE_FORMAT_Z16_UNORM:
1568 return V_028040_Z_16;
1569 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1570 case PIPE_FORMAT_X8Z24_UNORM:
1571 case PIPE_FORMAT_Z24X8_UNORM:
1572 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1573 return V_028040_Z_24; /* deprecated on SI */
1574 case PIPE_FORMAT_Z32_FLOAT:
1575 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1576 return V_028040_Z_32_FLOAT;
1577 default:
1578 return V_028040_Z_INVALID;
1579 }
1580 }
1581
1582 /*
1583 * Texture translation
1584 */
1585
1586 static uint32_t si_translate_texformat(struct pipe_screen *screen,
1587 enum pipe_format format,
1588 const struct util_format_description *desc,
1589 int first_non_void)
1590 {
1591 struct si_screen *sscreen = (struct si_screen*)screen;
1592 bool uniform = true;
1593 int i;
1594
1595 /* Colorspace (return non-RGB formats directly). */
1596 switch (desc->colorspace) {
1597 /* Depth stencil formats */
1598 case UTIL_FORMAT_COLORSPACE_ZS:
1599 switch (format) {
1600 case PIPE_FORMAT_Z16_UNORM:
1601 return V_008F14_IMG_DATA_FORMAT_16;
1602 case PIPE_FORMAT_X24S8_UINT:
1603 case PIPE_FORMAT_S8X24_UINT:
1604 /*
1605 * Implemented as an 8_8_8_8 data format to fix texture
1606 * gathers in stencil sampling. This affects at least
1607 * GL45-CTS.texture_cube_map_array.sampling on VI.
1608 */
1609 if (sscreen->info.chip_class <= VI)
1610 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1611
1612 if (format == PIPE_FORMAT_X24S8_UINT)
1613 return V_008F14_IMG_DATA_FORMAT_8_24;
1614 else
1615 return V_008F14_IMG_DATA_FORMAT_24_8;
1616 case PIPE_FORMAT_Z24X8_UNORM:
1617 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
1618 return V_008F14_IMG_DATA_FORMAT_8_24;
1619 case PIPE_FORMAT_X8Z24_UNORM:
1620 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
1621 return V_008F14_IMG_DATA_FORMAT_24_8;
1622 case PIPE_FORMAT_S8_UINT:
1623 return V_008F14_IMG_DATA_FORMAT_8;
1624 case PIPE_FORMAT_Z32_FLOAT:
1625 return V_008F14_IMG_DATA_FORMAT_32;
1626 case PIPE_FORMAT_X32_S8X24_UINT:
1627 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
1628 return V_008F14_IMG_DATA_FORMAT_X24_8_32;
1629 default:
1630 goto out_unknown;
1631 }
1632
1633 case UTIL_FORMAT_COLORSPACE_YUV:
1634 goto out_unknown; /* TODO */
1635
1636 case UTIL_FORMAT_COLORSPACE_SRGB:
1637 if (desc->nr_channels != 4 && desc->nr_channels != 1)
1638 goto out_unknown;
1639 break;
1640
1641 default:
1642 break;
1643 }
1644
1645 if (desc->layout == UTIL_FORMAT_LAYOUT_RGTC) {
1646 if (!sscreen->info.has_format_bc1_through_bc7)
1647 goto out_unknown;
1648
1649 switch (format) {
1650 case PIPE_FORMAT_RGTC1_SNORM:
1651 case PIPE_FORMAT_LATC1_SNORM:
1652 case PIPE_FORMAT_RGTC1_UNORM:
1653 case PIPE_FORMAT_LATC1_UNORM:
1654 return V_008F14_IMG_DATA_FORMAT_BC4;
1655 case PIPE_FORMAT_RGTC2_SNORM:
1656 case PIPE_FORMAT_LATC2_SNORM:
1657 case PIPE_FORMAT_RGTC2_UNORM:
1658 case PIPE_FORMAT_LATC2_UNORM:
1659 return V_008F14_IMG_DATA_FORMAT_BC5;
1660 default:
1661 goto out_unknown;
1662 }
1663 }
1664
1665 if (desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
1666 (sscreen->info.family == CHIP_STONEY ||
1667 sscreen->info.family == CHIP_VEGA10 ||
1668 sscreen->info.family == CHIP_RAVEN)) {
1669 switch (format) {
1670 case PIPE_FORMAT_ETC1_RGB8:
1671 case PIPE_FORMAT_ETC2_RGB8:
1672 case PIPE_FORMAT_ETC2_SRGB8:
1673 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB;
1674 case PIPE_FORMAT_ETC2_RGB8A1:
1675 case PIPE_FORMAT_ETC2_SRGB8A1:
1676 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1;
1677 case PIPE_FORMAT_ETC2_RGBA8:
1678 case PIPE_FORMAT_ETC2_SRGBA8:
1679 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA;
1680 case PIPE_FORMAT_ETC2_R11_UNORM:
1681 case PIPE_FORMAT_ETC2_R11_SNORM:
1682 return V_008F14_IMG_DATA_FORMAT_ETC2_R;
1683 case PIPE_FORMAT_ETC2_RG11_UNORM:
1684 case PIPE_FORMAT_ETC2_RG11_SNORM:
1685 return V_008F14_IMG_DATA_FORMAT_ETC2_RG;
1686 default:
1687 goto out_unknown;
1688 }
1689 }
1690
1691 if (desc->layout == UTIL_FORMAT_LAYOUT_BPTC) {
1692 if (!sscreen->info.has_format_bc1_through_bc7)
1693 goto out_unknown;
1694
1695 switch (format) {
1696 case PIPE_FORMAT_BPTC_RGBA_UNORM:
1697 case PIPE_FORMAT_BPTC_SRGBA:
1698 return V_008F14_IMG_DATA_FORMAT_BC7;
1699 case PIPE_FORMAT_BPTC_RGB_FLOAT:
1700 case PIPE_FORMAT_BPTC_RGB_UFLOAT:
1701 return V_008F14_IMG_DATA_FORMAT_BC6;
1702 default:
1703 goto out_unknown;
1704 }
1705 }
1706
1707 if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
1708 switch (format) {
1709 case PIPE_FORMAT_R8G8_B8G8_UNORM:
1710 case PIPE_FORMAT_G8R8_B8R8_UNORM:
1711 return V_008F14_IMG_DATA_FORMAT_GB_GR;
1712 case PIPE_FORMAT_G8R8_G8B8_UNORM:
1713 case PIPE_FORMAT_R8G8_R8B8_UNORM:
1714 return V_008F14_IMG_DATA_FORMAT_BG_RG;
1715 default:
1716 goto out_unknown;
1717 }
1718 }
1719
1720 if (desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
1721 if (!sscreen->info.has_format_bc1_through_bc7)
1722 goto out_unknown;
1723
1724 switch (format) {
1725 case PIPE_FORMAT_DXT1_RGB:
1726 case PIPE_FORMAT_DXT1_RGBA:
1727 case PIPE_FORMAT_DXT1_SRGB:
1728 case PIPE_FORMAT_DXT1_SRGBA:
1729 return V_008F14_IMG_DATA_FORMAT_BC1;
1730 case PIPE_FORMAT_DXT3_RGBA:
1731 case PIPE_FORMAT_DXT3_SRGBA:
1732 return V_008F14_IMG_DATA_FORMAT_BC2;
1733 case PIPE_FORMAT_DXT5_RGBA:
1734 case PIPE_FORMAT_DXT5_SRGBA:
1735 return V_008F14_IMG_DATA_FORMAT_BC3;
1736 default:
1737 goto out_unknown;
1738 }
1739 }
1740
1741 if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
1742 return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
1743 } else if (format == PIPE_FORMAT_R11G11B10_FLOAT) {
1744 return V_008F14_IMG_DATA_FORMAT_10_11_11;
1745 }
1746
1747 /* R8G8Bx_SNORM - TODO CxV8U8 */
1748
1749 /* hw cannot support mixed formats (except depth/stencil, since only
1750 * depth is read).*/
1751 if (desc->is_mixed && desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS)
1752 goto out_unknown;
1753
1754 /* See whether the components are of the same size. */
1755 for (i = 1; i < desc->nr_channels; i++) {
1756 uniform = uniform && desc->channel[0].size == desc->channel[i].size;
1757 }
1758
1759 /* Non-uniform formats. */
1760 if (!uniform) {
1761 switch(desc->nr_channels) {
1762 case 3:
1763 if (desc->channel[0].size == 5 &&
1764 desc->channel[1].size == 6 &&
1765 desc->channel[2].size == 5) {
1766 return V_008F14_IMG_DATA_FORMAT_5_6_5;
1767 }
1768 goto out_unknown;
1769 case 4:
1770 if (desc->channel[0].size == 5 &&
1771 desc->channel[1].size == 5 &&
1772 desc->channel[2].size == 5 &&
1773 desc->channel[3].size == 1) {
1774 return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
1775 }
1776 if (desc->channel[0].size == 1 &&
1777 desc->channel[1].size == 5 &&
1778 desc->channel[2].size == 5 &&
1779 desc->channel[3].size == 5) {
1780 return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
1781 }
1782 if (desc->channel[0].size == 10 &&
1783 desc->channel[1].size == 10 &&
1784 desc->channel[2].size == 10 &&
1785 desc->channel[3].size == 2) {
1786 return V_008F14_IMG_DATA_FORMAT_2_10_10_10;
1787 }
1788 goto out_unknown;
1789 }
1790 goto out_unknown;
1791 }
1792
1793 if (first_non_void < 0 || first_non_void > 3)
1794 goto out_unknown;
1795
1796 /* uniform formats */
1797 switch (desc->channel[first_non_void].size) {
1798 case 4:
1799 switch (desc->nr_channels) {
1800 #if 0 /* Not supported for render targets */
1801 case 2:
1802 return V_008F14_IMG_DATA_FORMAT_4_4;
1803 #endif
1804 case 4:
1805 return V_008F14_IMG_DATA_FORMAT_4_4_4_4;
1806 }
1807 break;
1808 case 8:
1809 switch (desc->nr_channels) {
1810 case 1:
1811 return V_008F14_IMG_DATA_FORMAT_8;
1812 case 2:
1813 return V_008F14_IMG_DATA_FORMAT_8_8;
1814 case 4:
1815 return V_008F14_IMG_DATA_FORMAT_8_8_8_8;
1816 }
1817 break;
1818 case 16:
1819 switch (desc->nr_channels) {
1820 case 1:
1821 return V_008F14_IMG_DATA_FORMAT_16;
1822 case 2:
1823 return V_008F14_IMG_DATA_FORMAT_16_16;
1824 case 4:
1825 return V_008F14_IMG_DATA_FORMAT_16_16_16_16;
1826 }
1827 break;
1828 case 32:
1829 switch (desc->nr_channels) {
1830 case 1:
1831 return V_008F14_IMG_DATA_FORMAT_32;
1832 case 2:
1833 return V_008F14_IMG_DATA_FORMAT_32_32;
1834 #if 0 /* Not supported for render targets */
1835 case 3:
1836 return V_008F14_IMG_DATA_FORMAT_32_32_32;
1837 #endif
1838 case 4:
1839 return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
1840 }
1841 }
1842
1843 out_unknown:
1844 return ~0;
1845 }
1846
1847 static unsigned si_tex_wrap(unsigned wrap)
1848 {
1849 switch (wrap) {
1850 default:
1851 case PIPE_TEX_WRAP_REPEAT:
1852 return V_008F30_SQ_TEX_WRAP;
1853 case PIPE_TEX_WRAP_CLAMP:
1854 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER;
1855 case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1856 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1857 case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1858 return V_008F30_SQ_TEX_CLAMP_BORDER;
1859 case PIPE_TEX_WRAP_MIRROR_REPEAT:
1860 return V_008F30_SQ_TEX_MIRROR;
1861 case PIPE_TEX_WRAP_MIRROR_CLAMP:
1862 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1863 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1864 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1865 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1866 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER;
1867 }
1868 }
1869
1870 static unsigned si_tex_mipfilter(unsigned filter)
1871 {
1872 switch (filter) {
1873 case PIPE_TEX_MIPFILTER_NEAREST:
1874 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1875 case PIPE_TEX_MIPFILTER_LINEAR:
1876 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1877 default:
1878 case PIPE_TEX_MIPFILTER_NONE:
1879 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1880 }
1881 }
1882
1883 static unsigned si_tex_compare(unsigned compare)
1884 {
1885 switch (compare) {
1886 default:
1887 case PIPE_FUNC_NEVER:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1889 case PIPE_FUNC_LESS:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1891 case PIPE_FUNC_EQUAL:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1893 case PIPE_FUNC_LEQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1895 case PIPE_FUNC_GREATER:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1897 case PIPE_FUNC_NOTEQUAL:
1898 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1899 case PIPE_FUNC_GEQUAL:
1900 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1901 case PIPE_FUNC_ALWAYS:
1902 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1903 }
1904 }
1905
1906 static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
1907 unsigned view_target, unsigned nr_samples)
1908 {
1909 unsigned res_target = tex->buffer.b.b.target;
1910
1911 if (view_target == PIPE_TEXTURE_CUBE ||
1912 view_target == PIPE_TEXTURE_CUBE_ARRAY)
1913 res_target = view_target;
1914 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1915 else if (res_target == PIPE_TEXTURE_CUBE ||
1916 res_target == PIPE_TEXTURE_CUBE_ARRAY)
1917 res_target = PIPE_TEXTURE_2D_ARRAY;
1918
1919 /* GFX9 allocates 1D textures as 2D. */
1920 if ((res_target == PIPE_TEXTURE_1D ||
1921 res_target == PIPE_TEXTURE_1D_ARRAY) &&
1922 sscreen->info.chip_class >= GFX9 &&
1923 tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
1924 if (res_target == PIPE_TEXTURE_1D)
1925 res_target = PIPE_TEXTURE_2D;
1926 else
1927 res_target = PIPE_TEXTURE_2D_ARRAY;
1928 }
1929
1930 switch (res_target) {
1931 default:
1932 case PIPE_TEXTURE_1D:
1933 return V_008F1C_SQ_RSRC_IMG_1D;
1934 case PIPE_TEXTURE_1D_ARRAY:
1935 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY;
1936 case PIPE_TEXTURE_2D:
1937 case PIPE_TEXTURE_RECT:
1938 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA :
1939 V_008F1C_SQ_RSRC_IMG_2D;
1940 case PIPE_TEXTURE_2D_ARRAY:
1941 return nr_samples > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY :
1942 V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
1943 case PIPE_TEXTURE_3D:
1944 return V_008F1C_SQ_RSRC_IMG_3D;
1945 case PIPE_TEXTURE_CUBE:
1946 case PIPE_TEXTURE_CUBE_ARRAY:
1947 return V_008F1C_SQ_RSRC_IMG_CUBE;
1948 }
1949 }
1950
1951 /*
1952 * Format support testing
1953 */
1954
1955 static bool si_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
1956 {
1957 const struct util_format_description *desc = util_format_description(format);
1958 if (!desc)
1959 return false;
1960
1961 return si_translate_texformat(screen, format, desc,
1962 util_format_get_first_non_void_channel(format)) != ~0U;
1963 }
1964
1965 static uint32_t si_translate_buffer_dataformat(struct pipe_screen *screen,
1966 const struct util_format_description *desc,
1967 int first_non_void)
1968 {
1969 int i;
1970
1971 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
1972 return V_008F0C_BUF_DATA_FORMAT_10_11_11;
1973
1974 assert(first_non_void >= 0);
1975
1976 if (desc->nr_channels == 4 &&
1977 desc->channel[0].size == 10 &&
1978 desc->channel[1].size == 10 &&
1979 desc->channel[2].size == 10 &&
1980 desc->channel[3].size == 2)
1981 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10;
1982
1983 /* See whether the components are of the same size. */
1984 for (i = 0; i < desc->nr_channels; i++) {
1985 if (desc->channel[first_non_void].size != desc->channel[i].size)
1986 return V_008F0C_BUF_DATA_FORMAT_INVALID;
1987 }
1988
1989 switch (desc->channel[first_non_void].size) {
1990 case 8:
1991 switch (desc->nr_channels) {
1992 case 1:
1993 case 3: /* 3 loads */
1994 return V_008F0C_BUF_DATA_FORMAT_8;
1995 case 2:
1996 return V_008F0C_BUF_DATA_FORMAT_8_8;
1997 case 4:
1998 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8;
1999 }
2000 break;
2001 case 16:
2002 switch (desc->nr_channels) {
2003 case 1:
2004 case 3: /* 3 loads */
2005 return V_008F0C_BUF_DATA_FORMAT_16;
2006 case 2:
2007 return V_008F0C_BUF_DATA_FORMAT_16_16;
2008 case 4:
2009 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16;
2010 }
2011 break;
2012 case 32:
2013 switch (desc->nr_channels) {
2014 case 1:
2015 return V_008F0C_BUF_DATA_FORMAT_32;
2016 case 2:
2017 return V_008F0C_BUF_DATA_FORMAT_32_32;
2018 case 3:
2019 return V_008F0C_BUF_DATA_FORMAT_32_32_32;
2020 case 4:
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2022 }
2023 break;
2024 case 64:
2025 /* Legacy double formats. */
2026 switch (desc->nr_channels) {
2027 case 1: /* 1 load */
2028 return V_008F0C_BUF_DATA_FORMAT_32_32;
2029 case 2: /* 1 load */
2030 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2031 case 3: /* 3 loads */
2032 return V_008F0C_BUF_DATA_FORMAT_32_32;
2033 case 4: /* 2 loads */
2034 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32;
2035 }
2036 break;
2037 }
2038
2039 return V_008F0C_BUF_DATA_FORMAT_INVALID;
2040 }
2041
2042 static uint32_t si_translate_buffer_numformat(struct pipe_screen *screen,
2043 const struct util_format_description *desc,
2044 int first_non_void)
2045 {
2046 if (desc->format == PIPE_FORMAT_R11G11B10_FLOAT)
2047 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2048
2049 assert(first_non_void >= 0);
2050
2051 switch (desc->channel[first_non_void].type) {
2052 case UTIL_FORMAT_TYPE_SIGNED:
2053 case UTIL_FORMAT_TYPE_FIXED:
2054 if (desc->channel[first_non_void].size >= 32 ||
2055 desc->channel[first_non_void].pure_integer)
2056 return V_008F0C_BUF_NUM_FORMAT_SINT;
2057 else if (desc->channel[first_non_void].normalized)
2058 return V_008F0C_BUF_NUM_FORMAT_SNORM;
2059 else
2060 return V_008F0C_BUF_NUM_FORMAT_SSCALED;
2061 break;
2062 case UTIL_FORMAT_TYPE_UNSIGNED:
2063 if (desc->channel[first_non_void].size >= 32 ||
2064 desc->channel[first_non_void].pure_integer)
2065 return V_008F0C_BUF_NUM_FORMAT_UINT;
2066 else if (desc->channel[first_non_void].normalized)
2067 return V_008F0C_BUF_NUM_FORMAT_UNORM;
2068 else
2069 return V_008F0C_BUF_NUM_FORMAT_USCALED;
2070 break;
2071 case UTIL_FORMAT_TYPE_FLOAT:
2072 default:
2073 return V_008F0C_BUF_NUM_FORMAT_FLOAT;
2074 }
2075 }
2076
2077 static unsigned si_is_vertex_format_supported(struct pipe_screen *screen,
2078 enum pipe_format format,
2079 unsigned usage)
2080 {
2081 const struct util_format_description *desc;
2082 int first_non_void;
2083 unsigned data_format;
2084
2085 assert((usage & ~(PIPE_BIND_SHADER_IMAGE |
2086 PIPE_BIND_SAMPLER_VIEW |
2087 PIPE_BIND_VERTEX_BUFFER)) == 0);
2088
2089 desc = util_format_description(format);
2090 if (!desc)
2091 return 0;
2092
2093 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2094 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2095 * for read-only access (with caveats surrounding bounds checks), but
2096 * obviously fails for write access which we have to implement for
2097 * shader images. Luckily, OpenGL doesn't expect this to be supported
2098 * anyway, and so the only impact is on PBO uploads / downloads, which
2099 * shouldn't be expected to be fast for GL_RGB anyway.
2100 */
2101 if (desc->block.bits == 3 * 8 ||
2102 desc->block.bits == 3 * 16) {
2103 if (usage & (PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW)) {
2104 usage &= ~(PIPE_BIND_SHADER_IMAGE | PIPE_BIND_SAMPLER_VIEW);
2105 if (!usage)
2106 return 0;
2107 }
2108 }
2109
2110 first_non_void = util_format_get_first_non_void_channel(format);
2111 data_format = si_translate_buffer_dataformat(screen, desc, first_non_void);
2112 if (data_format == V_008F0C_BUF_DATA_FORMAT_INVALID)
2113 return 0;
2114
2115 return usage;
2116 }
2117
2118 static bool si_is_colorbuffer_format_supported(enum pipe_format format)
2119 {
2120 return si_translate_colorformat(format) != V_028C70_COLOR_INVALID &&
2121 si_translate_colorswap(format, false) != ~0U;
2122 }
2123
2124 static bool si_is_zs_format_supported(enum pipe_format format)
2125 {
2126 return si_translate_dbformat(format) != V_028040_Z_INVALID;
2127 }
2128
2129 static boolean si_is_format_supported(struct pipe_screen *screen,
2130 enum pipe_format format,
2131 enum pipe_texture_target target,
2132 unsigned sample_count,
2133 unsigned storage_sample_count,
2134 unsigned usage)
2135 {
2136 struct si_screen *sscreen = (struct si_screen *)screen;
2137 unsigned retval = 0;
2138
2139 if (target >= PIPE_MAX_TEXTURE_TYPES) {
2140 PRINT_ERR("r600: unsupported texture type %d\n", target);
2141 return false;
2142 }
2143
2144 if (MAX2(1, sample_count) < MAX2(1, storage_sample_count))
2145 return false;
2146
2147 if (sample_count > 1) {
2148 if (!screen->get_param(screen, PIPE_CAP_TEXTURE_MULTISAMPLE))
2149 return false;
2150
2151 if (usage & PIPE_BIND_SHADER_IMAGE)
2152 return false;
2153
2154 /* Only power-of-two sample counts are supported. */
2155 if (!util_is_power_of_two_or_zero(sample_count) ||
2156 !util_is_power_of_two_or_zero(storage_sample_count))
2157 return false;
2158
2159 /* MSAA support without framebuffer attachments. */
2160 if (format == PIPE_FORMAT_NONE && sample_count <= 16)
2161 return true;
2162
2163 if (!sscreen->info.has_eqaa_surface_allocator ||
2164 util_format_is_depth_or_stencil(format)) {
2165 /* Color without EQAA or depth/stencil. */
2166 if (sample_count > 8 ||
2167 sample_count != storage_sample_count)
2168 return false;
2169 } else {
2170 /* Color with EQAA. */
2171 if (sample_count > 16 ||
2172 storage_sample_count > 8)
2173 return false;
2174 }
2175 }
2176
2177 if (usage & (PIPE_BIND_SAMPLER_VIEW |
2178 PIPE_BIND_SHADER_IMAGE)) {
2179 if (target == PIPE_BUFFER) {
2180 retval |= si_is_vertex_format_supported(
2181 screen, format, usage & (PIPE_BIND_SAMPLER_VIEW |
2182 PIPE_BIND_SHADER_IMAGE));
2183 } else {
2184 if (si_is_sampler_format_supported(screen, format))
2185 retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
2186 PIPE_BIND_SHADER_IMAGE);
2187 }
2188 }
2189
2190 if ((usage & (PIPE_BIND_RENDER_TARGET |
2191 PIPE_BIND_DISPLAY_TARGET |
2192 PIPE_BIND_SCANOUT |
2193 PIPE_BIND_SHARED |
2194 PIPE_BIND_BLENDABLE)) &&
2195 si_is_colorbuffer_format_supported(format)) {
2196 retval |= usage &
2197 (PIPE_BIND_RENDER_TARGET |
2198 PIPE_BIND_DISPLAY_TARGET |
2199 PIPE_BIND_SCANOUT |
2200 PIPE_BIND_SHARED);
2201 if (!util_format_is_pure_integer(format) &&
2202 !util_format_is_depth_or_stencil(format))
2203 retval |= usage & PIPE_BIND_BLENDABLE;
2204 }
2205
2206 if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
2207 si_is_zs_format_supported(format)) {
2208 retval |= PIPE_BIND_DEPTH_STENCIL;
2209 }
2210
2211 if (usage & PIPE_BIND_VERTEX_BUFFER) {
2212 retval |= si_is_vertex_format_supported(screen, format,
2213 PIPE_BIND_VERTEX_BUFFER);
2214 }
2215
2216 if ((usage & PIPE_BIND_LINEAR) &&
2217 !util_format_is_compressed(format) &&
2218 !(usage & PIPE_BIND_DEPTH_STENCIL))
2219 retval |= PIPE_BIND_LINEAR;
2220
2221 return retval == usage;
2222 }
2223
2224 /*
2225 * framebuffer handling
2226 */
2227
2228 static void si_choose_spi_color_formats(struct si_surface *surf,
2229 unsigned format, unsigned swap,
2230 unsigned ntype, bool is_depth)
2231 {
2232 /* Alpha is needed for alpha-to-coverage.
2233 * Blending may be with or without alpha.
2234 */
2235 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
2236 unsigned alpha = 0; /* exports alpha, but may not support blending */
2237 unsigned blend = 0; /* supports blending, but may not export alpha */
2238 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
2239
2240 /* Choose the SPI color formats. These are required values for RB+.
2241 * Other chips have multiple choices, though they are not necessarily better.
2242 */
2243 switch (format) {
2244 case V_028C70_COLOR_5_6_5:
2245 case V_028C70_COLOR_1_5_5_5:
2246 case V_028C70_COLOR_5_5_5_1:
2247 case V_028C70_COLOR_4_4_4_4:
2248 case V_028C70_COLOR_10_11_11:
2249 case V_028C70_COLOR_11_11_10:
2250 case V_028C70_COLOR_8:
2251 case V_028C70_COLOR_8_8:
2252 case V_028C70_COLOR_8_8_8_8:
2253 case V_028C70_COLOR_10_10_10_2:
2254 case V_028C70_COLOR_2_10_10_10:
2255 if (ntype == V_028C70_NUMBER_UINT)
2256 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2257 else if (ntype == V_028C70_NUMBER_SINT)
2258 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2259 else
2260 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2261 break;
2262
2263 case V_028C70_COLOR_16:
2264 case V_028C70_COLOR_16_16:
2265 case V_028C70_COLOR_16_16_16_16:
2266 if (ntype == V_028C70_NUMBER_UNORM ||
2267 ntype == V_028C70_NUMBER_SNORM) {
2268 /* UNORM16 and SNORM16 don't support blending */
2269 if (ntype == V_028C70_NUMBER_UNORM)
2270 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
2271 else
2272 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
2273
2274 /* Use 32 bits per channel for blending. */
2275 if (format == V_028C70_COLOR_16) {
2276 if (swap == V_028C70_SWAP_STD) { /* R */
2277 blend = V_028714_SPI_SHADER_32_R;
2278 blend_alpha = V_028714_SPI_SHADER_32_AR;
2279 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2280 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2281 else
2282 assert(0);
2283 } else if (format == V_028C70_COLOR_16_16) {
2284 if (swap == V_028C70_SWAP_STD) { /* RG */
2285 blend = V_028714_SPI_SHADER_32_GR;
2286 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2287 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2288 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
2289 else
2290 assert(0);
2291 } else /* 16_16_16_16 */
2292 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2293 } else if (ntype == V_028C70_NUMBER_UINT)
2294 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
2295 else if (ntype == V_028C70_NUMBER_SINT)
2296 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
2297 else if (ntype == V_028C70_NUMBER_FLOAT)
2298 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
2299 else
2300 assert(0);
2301 break;
2302
2303 case V_028C70_COLOR_32:
2304 if (swap == V_028C70_SWAP_STD) { /* R */
2305 blend = normal = V_028714_SPI_SHADER_32_R;
2306 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
2307 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
2308 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2309 else
2310 assert(0);
2311 break;
2312
2313 case V_028C70_COLOR_32_32:
2314 if (swap == V_028C70_SWAP_STD) { /* RG */
2315 blend = normal = V_028714_SPI_SHADER_32_GR;
2316 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
2317 } else if (swap == V_028C70_SWAP_ALT) /* RA */
2318 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
2319 else
2320 assert(0);
2321 break;
2322
2323 case V_028C70_COLOR_32_32_32_32:
2324 case V_028C70_COLOR_8_24:
2325 case V_028C70_COLOR_24_8:
2326 case V_028C70_COLOR_X24_8_32_FLOAT:
2327 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2328 break;
2329
2330 default:
2331 assert(0);
2332 return;
2333 }
2334
2335 /* The DB->CB copy needs 32_ABGR. */
2336 if (is_depth)
2337 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
2338
2339 surf->spi_shader_col_format = normal;
2340 surf->spi_shader_col_format_alpha = alpha;
2341 surf->spi_shader_col_format_blend = blend;
2342 surf->spi_shader_col_format_blend_alpha = blend_alpha;
2343 }
2344
2345 static void si_initialize_color_surface(struct si_context *sctx,
2346 struct si_surface *surf)
2347 {
2348 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2349 unsigned color_info, color_attrib;
2350 unsigned format, swap, ntype, endian;
2351 const struct util_format_description *desc;
2352 int firstchan;
2353 unsigned blend_clamp = 0, blend_bypass = 0;
2354
2355 desc = util_format_description(surf->base.format);
2356 for (firstchan = 0; firstchan < 4; firstchan++) {
2357 if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
2358 break;
2359 }
2360 }
2361 if (firstchan == 4 || desc->channel[firstchan].type == UTIL_FORMAT_TYPE_FLOAT) {
2362 ntype = V_028C70_NUMBER_FLOAT;
2363 } else {
2364 ntype = V_028C70_NUMBER_UNORM;
2365 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
2366 ntype = V_028C70_NUMBER_SRGB;
2367 else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_SIGNED) {
2368 if (desc->channel[firstchan].pure_integer) {
2369 ntype = V_028C70_NUMBER_SINT;
2370 } else {
2371 assert(desc->channel[firstchan].normalized);
2372 ntype = V_028C70_NUMBER_SNORM;
2373 }
2374 } else if (desc->channel[firstchan].type == UTIL_FORMAT_TYPE_UNSIGNED) {
2375 if (desc->channel[firstchan].pure_integer) {
2376 ntype = V_028C70_NUMBER_UINT;
2377 } else {
2378 assert(desc->channel[firstchan].normalized);
2379 ntype = V_028C70_NUMBER_UNORM;
2380 }
2381 }
2382 }
2383
2384 format = si_translate_colorformat(surf->base.format);
2385 if (format == V_028C70_COLOR_INVALID) {
2386 PRINT_ERR("Invalid CB format: %d, disabling CB.\n", surf->base.format);
2387 }
2388 assert(format != V_028C70_COLOR_INVALID);
2389 swap = si_translate_colorswap(surf->base.format, false);
2390 endian = si_colorformat_endian_swap(format);
2391
2392 /* blend clamp should be set for all NORM/SRGB types */
2393 if (ntype == V_028C70_NUMBER_UNORM ||
2394 ntype == V_028C70_NUMBER_SNORM ||
2395 ntype == V_028C70_NUMBER_SRGB)
2396 blend_clamp = 1;
2397
2398 /* set blend bypass according to docs if SINT/UINT or
2399 8/24 COLOR variants */
2400 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2401 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2402 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2403 blend_clamp = 0;
2404 blend_bypass = 1;
2405 }
2406
2407 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) {
2408 if (format == V_028C70_COLOR_8 ||
2409 format == V_028C70_COLOR_8_8 ||
2410 format == V_028C70_COLOR_8_8_8_8)
2411 surf->color_is_int8 = true;
2412 else if (format == V_028C70_COLOR_10_10_10_2 ||
2413 format == V_028C70_COLOR_2_10_10_10)
2414 surf->color_is_int10 = true;
2415 }
2416
2417 color_info = S_028C70_FORMAT(format) |
2418 S_028C70_COMP_SWAP(swap) |
2419 S_028C70_BLEND_CLAMP(blend_clamp) |
2420 S_028C70_BLEND_BYPASS(blend_bypass) |
2421 S_028C70_SIMPLE_FLOAT(1) |
2422 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2423 ntype != V_028C70_NUMBER_SNORM &&
2424 ntype != V_028C70_NUMBER_SRGB &&
2425 format != V_028C70_COLOR_8_24 &&
2426 format != V_028C70_COLOR_24_8) |
2427 S_028C70_NUMBER_TYPE(ntype) |
2428 S_028C70_ENDIAN(endian);
2429
2430 /* Intensity is implemented as Red, so treat it that way. */
2431 color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
2432 util_format_is_intensity(surf->base.format));
2433
2434 if (tex->buffer.b.b.nr_samples > 1) {
2435 unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
2436 unsigned log_fragments = util_logbase2(tex->buffer.b.b.nr_storage_samples);
2437
2438 color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2439 S_028C74_NUM_FRAGMENTS(log_fragments);
2440
2441 if (tex->surface.fmask_size) {
2442 color_info |= S_028C70_COMPRESSION(1);
2443 unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
2444
2445 if (sctx->chip_class == SI) {
2446 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2447 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2448 }
2449 }
2450 }
2451
2452 if (sctx->chip_class >= VI) {
2453 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
2454 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
2455
2456 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
2457 64 for APU because all of our APUs to date use DIMMs which have
2458 a request granularity size of 64B while all other chips have a
2459 32B request size */
2460 if (!sctx->screen->info.has_dedicated_vram)
2461 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
2462
2463 if (tex->buffer.b.b.nr_storage_samples > 1) {
2464 if (tex->surface.bpe == 1)
2465 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
2466 else if (tex->surface.bpe == 2)
2467 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
2468 }
2469
2470 surf->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2471 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
2472 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2473 }
2474
2475 /* This must be set for fast clear to work without FMASK. */
2476 if (!tex->surface.fmask_size && sctx->chip_class == SI) {
2477 unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
2478 color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2479 }
2480
2481 unsigned color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
2482 S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
2483
2484 if (sctx->chip_class >= GFX9) {
2485 unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
2486
2487 color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
2488 color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2489 S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
2490 surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
2491 S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
2492 S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
2493 }
2494
2495 surf->cb_color_view = color_view;
2496 surf->cb_color_info = color_info;
2497 surf->cb_color_attrib = color_attrib;
2498
2499 /* Determine pixel shader export format */
2500 si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
2501
2502 surf->color_initialized = true;
2503 }
2504
2505 static void si_init_depth_surface(struct si_context *sctx,
2506 struct si_surface *surf)
2507 {
2508 struct si_texture *tex = (struct si_texture*)surf->base.texture;
2509 unsigned level = surf->base.u.tex.level;
2510 unsigned format, stencil_format;
2511 uint32_t z_info, s_info;
2512
2513 format = si_translate_dbformat(tex->db_render_format);
2514 stencil_format = tex->surface.has_stencil ?
2515 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2516
2517 assert(format != V_028040_Z_INVALID);
2518 if (format == V_028040_Z_INVALID)
2519 PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
2520
2521 surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
2522 S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
2523 surf->db_htile_data_base = 0;
2524 surf->db_htile_surface = 0;
2525
2526 if (sctx->chip_class >= GFX9) {
2527 assert(tex->surface.u.gfx9.surf_offset == 0);
2528 surf->db_depth_base = tex->buffer.gpu_address >> 8;
2529 surf->db_stencil_base = (tex->buffer.gpu_address +
2530 tex->surface.u.gfx9.stencil_offset) >> 8;
2531 z_info = S_028038_FORMAT(format) |
2532 S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
2533 S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
2534 S_028038_MAXMIP(tex->buffer.b.b.last_level);
2535 s_info = S_02803C_FORMAT(stencil_format) |
2536 S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
2537 surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
2538 surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
2539 surf->db_depth_view |= S_028008_MIPID(level);
2540 surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
2541 S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
2542
2543 if (si_htile_enabled(tex, level)) {
2544 z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
2545 S_028038_ALLOW_EXPCLEAR(1);
2546
2547 if (tex->tc_compatible_htile) {
2548 unsigned max_zplanes = 4;
2549
2550 if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
2551 tex->buffer.b.b.nr_samples > 1)
2552 max_zplanes = 2;
2553
2554 z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
2555 S_028038_ITERATE_FLUSH(1);
2556 s_info |= S_02803C_ITERATE_FLUSH(1);
2557 }
2558
2559 if (tex->surface.has_stencil) {
2560 /* Stencil buffer workaround ported from the SI-CI-VI code.
2561 * See that for explanation.
2562 */
2563 s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
2564 } else {
2565 /* Use all HTILE for depth if there's no stencil. */
2566 s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2567 }
2568
2569 surf->db_htile_data_base = (tex->buffer.gpu_address +
2570 tex->htile_offset) >> 8;
2571 surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2572 S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
2573 S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
2574 }
2575 } else {
2576 /* SI-CI-VI */
2577 struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
2578
2579 assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
2580
2581 surf->db_depth_base = (tex->buffer.gpu_address +
2582 tex->surface.u.legacy.level[level].offset) >> 8;
2583 surf->db_stencil_base = (tex->buffer.gpu_address +
2584 tex->surface.u.legacy.stencil_level[level].offset) >> 8;
2585
2586 z_info = S_028040_FORMAT(format) |
2587 S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
2588 s_info = S_028044_FORMAT(stencil_format);
2589 surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
2590
2591 if (sctx->chip_class >= CIK) {
2592 struct radeon_info *info = &sctx->screen->info;
2593 unsigned index = tex->surface.u.legacy.tiling_index[level];
2594 unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
2595 unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
2596 unsigned tile_mode = info->si_tile_mode_array[index];
2597 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2598 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2599
2600 surf->db_depth_info |=
2601 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2602 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2603 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2604 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2605 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2606 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2607 z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2608 s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2609 } else {
2610 unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
2611 z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2612 tile_mode_index = si_tile_mode_index(tex, level, true);
2613 s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2614 }
2615
2616 surf->db_depth_size = S_028058_PITCH_TILE_MAX((levelinfo->nblk_x / 8) - 1) |
2617 S_028058_HEIGHT_TILE_MAX((levelinfo->nblk_y / 8) - 1);
2618 surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
2619 levelinfo->nblk_y) / 64 - 1);
2620
2621 if (si_htile_enabled(tex, level)) {
2622 z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2623 S_028040_ALLOW_EXPCLEAR(1);
2624
2625 if (tex->surface.has_stencil) {
2626 /* Workaround: For a not yet understood reason, the
2627 * combination of MSAA, fast stencil clear and stencil
2628 * decompress messes with subsequent stencil buffer
2629 * uses. Problem was reproduced on Verde, Bonaire,
2630 * Tonga, and Carrizo.
2631 *
2632 * Disabling EXPCLEAR works around the problem.
2633 *
2634 * Check piglit's arb_texture_multisample-stencil-clear
2635 * test if you want to try changing this.
2636 */
2637 if (tex->buffer.b.b.nr_samples <= 1)
2638 s_info |= S_028044_ALLOW_EXPCLEAR(1);
2639 } else if (!tex->tc_compatible_htile) {
2640 /* Use all of the htile_buffer for depth if there's no stencil.
2641 * This must not be set when TC-compatible HTILE is enabled
2642 * due to a hw bug.
2643 */
2644 s_info |= S_028044_TILE_STENCIL_DISABLE(1);
2645 }
2646
2647 surf->db_htile_data_base = (tex->buffer.gpu_address +
2648 tex->htile_offset) >> 8;
2649 surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
2650
2651 if (tex->tc_compatible_htile) {
2652 surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
2653
2654 /* 0 = full compression. N = only compress up to N-1 Z planes. */
2655 if (tex->buffer.b.b.nr_samples <= 1)
2656 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2657 else if (tex->buffer.b.b.nr_samples <= 4)
2658 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2659 else
2660 z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2661 }
2662 }
2663 }
2664
2665 surf->db_z_info = z_info;
2666 surf->db_stencil_info = s_info;
2667
2668 surf->depth_initialized = true;
2669 }
2670
2671 void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
2672 {
2673 if (sctx->decompression_enabled)
2674 return;
2675
2676 if (sctx->framebuffer.state.zsbuf) {
2677 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
2678 struct si_texture *tex = (struct si_texture *)surf->texture;
2679
2680 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2681
2682 if (tex->surface.has_stencil)
2683 tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
2684 }
2685
2686 unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
2687 while (compressed_cb_mask) {
2688 unsigned i = u_bit_scan(&compressed_cb_mask);
2689 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2690 struct si_texture *tex = (struct si_texture*)surf->texture;
2691
2692 if (tex->surface.fmask_size)
2693 tex->dirty_level_mask |= 1 << surf->u.tex.level;
2694 if (tex->dcc_gather_statistics)
2695 tex->separate_dcc_dirty = true;
2696 }
2697 }
2698
2699 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *state)
2700 {
2701 for (int i = 0; i < state->nr_cbufs; ++i) {
2702 struct si_surface *surf = NULL;
2703 struct si_texture *tex;
2704
2705 if (!state->cbufs[i])
2706 continue;
2707 surf = (struct si_surface*)state->cbufs[i];
2708 tex = (struct si_texture*)surf->base.texture;
2709
2710 p_atomic_dec(&tex->framebuffers_bound);
2711 }
2712 }
2713
2714 static void si_set_framebuffer_state(struct pipe_context *ctx,
2715 const struct pipe_framebuffer_state *state)
2716 {
2717 struct si_context *sctx = (struct si_context *)ctx;
2718 struct si_surface *surf = NULL;
2719 struct si_texture *tex;
2720 bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
2721 unsigned old_nr_samples = sctx->framebuffer.nr_samples;
2722 unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
2723 bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
2724 bool old_has_stencil =
2725 old_has_zsbuf &&
2726 ((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
2727 bool unbound = false;
2728 int i;
2729
2730 /* Reject zero-sized framebuffers due to a hw bug on SI that occurs
2731 * when PA_SU_HARDWARE_SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
2732 * We could implement the full workaround here, but it's a useless case.
2733 */
2734 if ((!state->width || !state->height) && (state->nr_cbufs || state->zsbuf)) {
2735 unreachable("the framebuffer shouldn't have zero area");
2736 return;
2737 }
2738
2739 si_update_fb_dirtiness_after_rendering(sctx);
2740
2741 for (i = 0; i < sctx->framebuffer.state.nr_cbufs; i++) {
2742 if (!sctx->framebuffer.state.cbufs[i])
2743 continue;
2744
2745 tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
2746 if (tex->dcc_gather_statistics)
2747 vi_separate_dcc_stop_query(sctx, tex);
2748 }
2749
2750 /* Disable DCC if the formats are incompatible. */
2751 for (i = 0; i < state->nr_cbufs; i++) {
2752 if (!state->cbufs[i])
2753 continue;
2754
2755 surf = (struct si_surface*)state->cbufs[i];
2756 tex = (struct si_texture*)surf->base.texture;
2757
2758 if (!surf->dcc_incompatible)
2759 continue;
2760
2761 /* Since the DCC decompression calls back into set_framebuffer-
2762 * _state, we need to unbind the framebuffer, so that
2763 * vi_separate_dcc_stop_query isn't called twice with the same
2764 * color buffer.
2765 */
2766 if (!unbound) {
2767 util_copy_framebuffer_state(&sctx->framebuffer.state, NULL);
2768 unbound = true;
2769 }
2770
2771 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2772 if (!si_texture_disable_dcc(sctx, tex))
2773 si_decompress_dcc(sctx, tex);
2774
2775 surf->dcc_incompatible = false;
2776 }
2777
2778 /* Only flush TC when changing the framebuffer state, because
2779 * the only client not using TC that can change textures is
2780 * the framebuffer.
2781 *
2782 * Wait for compute shaders because of possible transitions:
2783 * - FB write -> shader read
2784 * - shader write -> FB read
2785 *
2786 * DB caches are flushed on demand (using si_decompress_textures).
2787 *
2788 * When MSAA is enabled, CB and TC caches are flushed on demand
2789 * (after FMASK decompression). Shader write -> FB read transitions
2790 * cannot happen for MSAA textures, because MSAA shader images are
2791 * not supported.
2792 *
2793 * Only flush and wait for CB if there is actually a bound color buffer.
2794 */
2795 if (sctx->framebuffer.uncompressed_cb_mask)
2796 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
2797 sctx->framebuffer.CB_has_shader_readable_metadata);
2798
2799 sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
2800
2801 /* u_blitter doesn't invoke depth decompression when it does multiple
2802 * blits in a row, but the only case when it matters for DB is when
2803 * doing generate_mipmap. So here we flush DB manually between
2804 * individual generate_mipmap blits.
2805 * Note that lower mipmap levels aren't compressed.
2806 */
2807 if (sctx->generate_mipmap_for_depth) {
2808 si_make_DB_shader_coherent(sctx, 1, false,
2809 sctx->framebuffer.DB_has_shader_readable_metadata);
2810 } else if (sctx->chip_class == GFX9) {
2811 /* It appears that DB metadata "leaks" in a sequence of:
2812 * - depth clear
2813 * - DCC decompress for shader image writes (with DB disabled)
2814 * - render with DEPTH_BEFORE_SHADER=1
2815 * Flushing DB metadata works around the problem.
2816 */
2817 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB_META;
2818 }
2819
2820 /* Take the maximum of the old and new count. If the new count is lower,
2821 * dirtying is needed to disable the unbound colorbuffers.
2822 */
2823 sctx->framebuffer.dirty_cbufs |=
2824 (1 << MAX2(sctx->framebuffer.state.nr_cbufs, state->nr_cbufs)) - 1;
2825 sctx->framebuffer.dirty_zsbuf |= sctx->framebuffer.state.zsbuf != state->zsbuf;
2826
2827 si_dec_framebuffer_counters(&sctx->framebuffer.state);
2828 util_copy_framebuffer_state(&sctx->framebuffer.state, state);
2829
2830 sctx->framebuffer.colorbuf_enabled_4bit = 0;
2831 sctx->framebuffer.spi_shader_col_format = 0;
2832 sctx->framebuffer.spi_shader_col_format_alpha = 0;
2833 sctx->framebuffer.spi_shader_col_format_blend = 0;
2834 sctx->framebuffer.spi_shader_col_format_blend_alpha = 0;
2835 sctx->framebuffer.color_is_int8 = 0;
2836 sctx->framebuffer.color_is_int10 = 0;
2837
2838 sctx->framebuffer.compressed_cb_mask = 0;
2839 sctx->framebuffer.uncompressed_cb_mask = 0;
2840 sctx->framebuffer.nr_samples = util_framebuffer_get_num_samples(state);
2841 sctx->framebuffer.nr_color_samples = sctx->framebuffer.nr_samples;
2842 sctx->framebuffer.log_samples = util_logbase2(sctx->framebuffer.nr_samples);
2843 sctx->framebuffer.any_dst_linear = false;
2844 sctx->framebuffer.CB_has_shader_readable_metadata = false;
2845 sctx->framebuffer.DB_has_shader_readable_metadata = false;
2846
2847 for (i = 0; i < state->nr_cbufs; i++) {
2848 if (!state->cbufs[i])
2849 continue;
2850
2851 surf = (struct si_surface*)state->cbufs[i];
2852 tex = (struct si_texture*)surf->base.texture;
2853
2854 if (!surf->color_initialized) {
2855 si_initialize_color_surface(sctx, surf);
2856 }
2857
2858 sctx->framebuffer.colorbuf_enabled_4bit |= 0xf << (i * 4);
2859 sctx->framebuffer.spi_shader_col_format |=
2860 surf->spi_shader_col_format << (i * 4);
2861 sctx->framebuffer.spi_shader_col_format_alpha |=
2862 surf->spi_shader_col_format_alpha << (i * 4);
2863 sctx->framebuffer.spi_shader_col_format_blend |=
2864 surf->spi_shader_col_format_blend << (i * 4);
2865 sctx->framebuffer.spi_shader_col_format_blend_alpha |=
2866 surf->spi_shader_col_format_blend_alpha << (i * 4);
2867
2868 if (surf->color_is_int8)
2869 sctx->framebuffer.color_is_int8 |= 1 << i;
2870 if (surf->color_is_int10)
2871 sctx->framebuffer.color_is_int10 |= 1 << i;
2872
2873 if (tex->surface.fmask_size)
2874 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2875 else
2876 sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
2877
2878 /* Don't update nr_color_samples for non-AA buffers.
2879 * (e.g. destination of MSAA resolve)
2880 */
2881 if (tex->buffer.b.b.nr_samples >= 2 &&
2882 tex->buffer.b.b.nr_storage_samples < tex->buffer.b.b.nr_samples) {
2883 sctx->framebuffer.nr_color_samples =
2884 MIN2(sctx->framebuffer.nr_color_samples,
2885 tex->buffer.b.b.nr_storage_samples);
2886 sctx->framebuffer.nr_color_samples =
2887 MAX2(1, sctx->framebuffer.nr_color_samples);
2888 }
2889
2890 if (tex->surface.is_linear)
2891 sctx->framebuffer.any_dst_linear = true;
2892
2893 if (vi_dcc_enabled(tex, surf->base.u.tex.level))
2894 sctx->framebuffer.CB_has_shader_readable_metadata = true;
2895
2896 si_context_add_resource_size(sctx, surf->base.texture);
2897
2898 p_atomic_inc(&tex->framebuffers_bound);
2899
2900 if (tex->dcc_gather_statistics) {
2901 /* Dirty tracking must be enabled for DCC usage analysis. */
2902 sctx->framebuffer.compressed_cb_mask |= 1 << i;
2903 vi_separate_dcc_start_query(sctx, tex);
2904 }
2905 }
2906
2907 struct si_texture *zstex = NULL;
2908
2909 if (state->zsbuf) {
2910 surf = (struct si_surface*)state->zsbuf;
2911 zstex = (struct si_texture*)surf->base.texture;
2912
2913 if (!surf->depth_initialized) {
2914 si_init_depth_surface(sctx, surf);
2915 }
2916
2917 if (vi_tc_compat_htile_enabled(zstex, surf->base.u.tex.level))
2918 sctx->framebuffer.DB_has_shader_readable_metadata = true;
2919
2920 si_context_add_resource_size(sctx, surf->base.texture);
2921 }
2922
2923 si_update_ps_colorbuf0_slot(sctx);
2924 si_update_poly_offset_state(sctx);
2925 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
2926 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
2927
2928 if (sctx->screen->dpbb_allowed)
2929 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
2930
2931 if (sctx->framebuffer.any_dst_linear != old_any_dst_linear)
2932 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2933
2934 if (sctx->screen->has_out_of_order_rast &&
2935 (sctx->framebuffer.colorbuf_enabled_4bit != old_colorbuf_enabled_4bit ||
2936 !!sctx->framebuffer.state.zsbuf != old_has_zsbuf ||
2937 (zstex && zstex->surface.has_stencil != old_has_stencil)))
2938 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2939
2940 if (sctx->framebuffer.nr_samples != old_nr_samples) {
2941 struct pipe_constant_buffer constbuf = {0};
2942
2943 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
2944 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
2945
2946 constbuf.buffer = sctx->sample_pos_buffer;
2947
2948 /* Set sample locations as fragment shader constants. */
2949 switch (sctx->framebuffer.nr_samples) {
2950 case 1:
2951 constbuf.buffer_offset = 0;
2952 break;
2953 case 2:
2954 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x2 -
2955 (ubyte*)sctx->sample_positions.x1;
2956 break;
2957 case 4:
2958 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x4 -
2959 (ubyte*)sctx->sample_positions.x1;
2960 break;
2961 case 8:
2962 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x8 -
2963 (ubyte*)sctx->sample_positions.x1;
2964 break;
2965 case 16:
2966 constbuf.buffer_offset = (ubyte*)sctx->sample_positions.x16 -
2967 (ubyte*)sctx->sample_positions.x1;
2968 break;
2969 default:
2970 PRINT_ERR("Requested an invalid number of samples %i.\n",
2971 sctx->framebuffer.nr_samples);
2972 assert(0);
2973 }
2974 constbuf.buffer_size = sctx->framebuffer.nr_samples * 2 * 4;
2975 si_set_rw_buffer(sctx, SI_PS_CONST_SAMPLE_POSITIONS, &constbuf);
2976
2977 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
2978 }
2979
2980 sctx->do_update_shaders = true;
2981
2982 if (!sctx->decompression_enabled) {
2983 /* Prevent textures decompression when the framebuffer state
2984 * changes come from the decompression passes themselves.
2985 */
2986 sctx->need_check_render_feedback = true;
2987 }
2988 }
2989
2990 static void si_emit_framebuffer_state(struct si_context *sctx)
2991 {
2992 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2993 struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
2994 unsigned i, nr_cbufs = state->nr_cbufs;
2995 struct si_texture *tex = NULL;
2996 struct si_surface *cb = NULL;
2997 unsigned cb_color_info = 0;
2998
2999 /* Colorbuffers. */
3000 for (i = 0; i < nr_cbufs; i++) {
3001 uint64_t cb_color_base, cb_color_fmask, cb_color_cmask, cb_dcc_base;
3002 unsigned cb_color_attrib;
3003
3004 if (!(sctx->framebuffer.dirty_cbufs & (1 << i)))
3005 continue;
3006
3007 cb = (struct si_surface*)state->cbufs[i];
3008 if (!cb) {
3009 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,
3010 S_028C70_FORMAT(V_028C70_COLOR_INVALID));
3011 continue;
3012 }
3013
3014 tex = (struct si_texture *)cb->base.texture;
3015 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3016 &tex->buffer, RADEON_USAGE_READWRITE,
3017 tex->buffer.b.b.nr_samples > 1 ?
3018 RADEON_PRIO_COLOR_BUFFER_MSAA :
3019 RADEON_PRIO_COLOR_BUFFER);
3020
3021 if (tex->cmask_buffer && tex->cmask_buffer != &tex->buffer) {
3022 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3023 tex->cmask_buffer, RADEON_USAGE_READWRITE,
3024 RADEON_PRIO_SEPARATE_META);
3025 }
3026
3027 if (tex->dcc_separate_buffer)
3028 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3029 tex->dcc_separate_buffer,
3030 RADEON_USAGE_READWRITE,
3031 RADEON_PRIO_SEPARATE_META);
3032
3033 /* Compute mutable surface parameters. */
3034 cb_color_base = tex->buffer.gpu_address >> 8;
3035 cb_color_fmask = 0;
3036 cb_color_cmask = tex->cmask_base_address_reg;
3037 cb_dcc_base = 0;
3038 cb_color_info = cb->cb_color_info | tex->cb_color_info;
3039 cb_color_attrib = cb->cb_color_attrib;
3040
3041 if (cb->base.u.tex.level > 0)
3042 cb_color_info &= C_028C70_FAST_CLEAR;
3043
3044 if (tex->surface.fmask_size) {
3045 cb_color_fmask = (tex->buffer.gpu_address + tex->fmask_offset) >> 8;
3046 cb_color_fmask |= tex->surface.fmask_tile_swizzle;
3047 }
3048
3049 /* Set up DCC. */
3050 if (vi_dcc_enabled(tex, cb->base.u.tex.level)) {
3051 bool is_msaa_resolve_dst = state->cbufs[0] &&
3052 state->cbufs[0]->texture->nr_samples > 1 &&
3053 state->cbufs[1] == &cb->base &&
3054 state->cbufs[1]->texture->nr_samples <= 1;
3055
3056 if (!is_msaa_resolve_dst)
3057 cb_color_info |= S_028C70_DCC_ENABLE(1);
3058
3059 cb_dcc_base = ((!tex->dcc_separate_buffer ? tex->buffer.gpu_address : 0) +
3060 tex->dcc_offset) >> 8;
3061 cb_dcc_base |= tex->surface.tile_swizzle;
3062 }
3063
3064 if (sctx->chip_class >= GFX9) {
3065 struct gfx9_surf_meta_flags meta;
3066
3067 if (tex->dcc_offset)
3068 meta = tex->surface.u.gfx9.dcc;
3069 else
3070 meta = tex->surface.u.gfx9.cmask;
3071
3072 /* Set mutable surface parameters. */
3073 cb_color_base += tex->surface.u.gfx9.surf_offset >> 8;
3074 cb_color_base |= tex->surface.tile_swizzle;
3075 if (!tex->surface.fmask_size)
3076 cb_color_fmask = cb_color_base;
3077 if (cb->base.u.tex.level > 0)
3078 cb_color_cmask = cb_color_base;
3079 cb_color_attrib |= S_028C74_COLOR_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
3080 S_028C74_FMASK_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode) |
3081 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3082 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3083
3084 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C, 15);
3085 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3086 radeon_emit(cs, S_028C64_BASE_256B(cb_color_base >> 32)); /* CB_COLOR0_BASE_EXT */
3087 radeon_emit(cs, cb->cb_color_attrib2); /* CB_COLOR0_ATTRIB2 */
3088 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3089 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3090 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3091 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3092 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3093 radeon_emit(cs, S_028C80_BASE_256B(cb_color_cmask >> 32)); /* CB_COLOR0_CMASK_BASE_EXT */
3094 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3095 radeon_emit(cs, S_028C88_BASE_256B(cb_color_fmask >> 32)); /* CB_COLOR0_FMASK_BASE_EXT */
3096 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3097 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3098 radeon_emit(cs, cb_dcc_base); /* CB_COLOR0_DCC_BASE */
3099 radeon_emit(cs, S_028C98_BASE_256B(cb_dcc_base >> 32)); /* CB_COLOR0_DCC_BASE_EXT */
3100
3101 radeon_set_context_reg(cs, R_0287A0_CB_MRT0_EPITCH + i * 4,
3102 S_0287A0_EPITCH(tex->surface.u.gfx9.surf.epitch));
3103 } else {
3104 /* Compute mutable surface parameters (SI-CI-VI). */
3105 const struct legacy_surf_level *level_info =
3106 &tex->surface.u.legacy.level[cb->base.u.tex.level];
3107 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3108 unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
3109
3110 cb_color_base += level_info->offset >> 8;
3111 /* Only macrotiled modes can set tile swizzle. */
3112 if (level_info->mode == RADEON_SURF_MODE_2D)
3113 cb_color_base |= tex->surface.tile_swizzle;
3114
3115 if (!tex->surface.fmask_size)
3116 cb_color_fmask = cb_color_base;
3117 if (cb->base.u.tex.level > 0)
3118 cb_color_cmask = cb_color_base;
3119 if (cb_dcc_base)
3120 cb_dcc_base += level_info->dcc_offset >> 8;
3121
3122 pitch_tile_max = level_info->nblk_x / 8 - 1;
3123 slice_tile_max = level_info->nblk_x *
3124 level_info->nblk_y / 64 - 1;
3125 tile_mode_index = si_tile_mode_index(tex, cb->base.u.tex.level, false);
3126
3127 cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3128 cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3129 cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3130
3131 if (tex->surface.fmask_size) {
3132 if (sctx->chip_class >= CIK)
3133 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(tex->surface.u.legacy.fmask.pitch_in_pixels / 8 - 1);
3134 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3135 cb_color_fmask_slice = S_028C88_TILE_MAX(tex->surface.u.legacy.fmask.slice_tile_max);
3136 } else {
3137 /* This must be set for fast clear to work without FMASK. */
3138 if (sctx->chip_class >= CIK)
3139 cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3140 cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3141 cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3142 }
3143
3144 radeon_set_context_reg_seq(cs, R_028C60_CB_COLOR0_BASE + i * 0x3C,
3145 sctx->chip_class >= VI ? 14 : 13);
3146 radeon_emit(cs, cb_color_base); /* CB_COLOR0_BASE */
3147 radeon_emit(cs, cb_color_pitch); /* CB_COLOR0_PITCH */
3148 radeon_emit(cs, cb_color_slice); /* CB_COLOR0_SLICE */
3149 radeon_emit(cs, cb->cb_color_view); /* CB_COLOR0_VIEW */
3150 radeon_emit(cs, cb_color_info); /* CB_COLOR0_INFO */
3151 radeon_emit(cs, cb_color_attrib); /* CB_COLOR0_ATTRIB */
3152 radeon_emit(cs, cb->cb_dcc_control); /* CB_COLOR0_DCC_CONTROL */
3153 radeon_emit(cs, cb_color_cmask); /* CB_COLOR0_CMASK */
3154 radeon_emit(cs, tex->surface.u.legacy.cmask_slice_tile_max); /* CB_COLOR0_CMASK_SLICE */
3155 radeon_emit(cs, cb_color_fmask); /* CB_COLOR0_FMASK */
3156 radeon_emit(cs, cb_color_fmask_slice); /* CB_COLOR0_FMASK_SLICE */
3157 radeon_emit(cs, tex->color_clear_value[0]); /* CB_COLOR0_CLEAR_WORD0 */
3158 radeon_emit(cs, tex->color_clear_value[1]); /* CB_COLOR0_CLEAR_WORD1 */
3159
3160 if (sctx->chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
3161 radeon_emit(cs, cb_dcc_base);
3162 }
3163 }
3164 for (; i < 8 ; i++)
3165 if (sctx->framebuffer.dirty_cbufs & (1 << i))
3166 radeon_set_context_reg(cs, R_028C70_CB_COLOR0_INFO + i * 0x3C, 0);
3167
3168 /* ZS buffer. */
3169 if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
3170 struct si_surface *zb = (struct si_surface*)state->zsbuf;
3171 struct si_texture *tex = (struct si_texture*)zb->base.texture;
3172
3173 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
3174 &tex->buffer, RADEON_USAGE_READWRITE,
3175 zb->base.texture->nr_samples > 1 ?
3176 RADEON_PRIO_DEPTH_BUFFER_MSAA :
3177 RADEON_PRIO_DEPTH_BUFFER);
3178
3179 if (sctx->chip_class >= GFX9) {
3180 radeon_set_context_reg_seq(cs, R_028014_DB_HTILE_DATA_BASE, 3);
3181 radeon_emit(cs, zb->db_htile_data_base); /* DB_HTILE_DATA_BASE */
3182 radeon_emit(cs, S_028018_BASE_HI(zb->db_htile_data_base >> 32)); /* DB_HTILE_DATA_BASE_HI */
3183 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3184
3185 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
3186 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3187 S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3188 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3189 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3190 radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
3191 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3192 radeon_emit(cs, S_02804C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_READ_BASE_HI */
3193 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3194 radeon_emit(cs, S_028054_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_WRITE_BASE_HI */
3195 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3196 radeon_emit(cs, S_02805C_BASE_HI(zb->db_stencil_base >> 32)); /* DB_STENCIL_WRITE_BASE_HI */
3197
3198 radeon_set_context_reg_seq(cs, R_028068_DB_Z_INFO2, 2);
3199 radeon_emit(cs, zb->db_z_info2); /* DB_Z_INFO2 */
3200 radeon_emit(cs, zb->db_stencil_info2); /* DB_STENCIL_INFO2 */
3201 } else {
3202 radeon_set_context_reg(cs, R_028014_DB_HTILE_DATA_BASE, zb->db_htile_data_base);
3203
3204 radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
3205 radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
3206 radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
3207 S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
3208 radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
3209 radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
3210 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
3211 radeon_emit(cs, zb->db_depth_base); /* DB_Z_WRITE_BASE */
3212 radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_WRITE_BASE */
3213 radeon_emit(cs, zb->db_depth_size); /* DB_DEPTH_SIZE */
3214 radeon_emit(cs, zb->db_depth_slice); /* DB_DEPTH_SLICE */
3215 }
3216
3217 radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
3218 radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
3219 radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
3220
3221 radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
3222 radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
3223 } else if (sctx->framebuffer.dirty_zsbuf) {
3224 if (sctx->chip_class >= GFX9)
3225 radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 2);
3226 else
3227 radeon_set_context_reg_seq(cs, R_028040_DB_Z_INFO, 2);
3228
3229 radeon_emit(cs, S_028040_FORMAT(V_028040_Z_INVALID)); /* DB_Z_INFO */
3230 radeon_emit(cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */
3231 }
3232
3233 /* Framebuffer dimensions. */
3234 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3235 radeon_set_context_reg(cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,
3236 S_028208_BR_X(state->width) | S_028208_BR_Y(state->height));
3237
3238 if (sctx->screen->dfsm_allowed) {
3239 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3240 radeon_emit(cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));
3241 }
3242
3243 sctx->framebuffer.dirty_cbufs = 0;
3244 sctx->framebuffer.dirty_zsbuf = false;
3245 }
3246
3247 static void si_emit_msaa_sample_locs(struct si_context *sctx)
3248 {
3249 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3250 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3251 unsigned nr_samples = sctx->framebuffer.nr_samples;
3252 bool has_msaa_sample_loc_bug = sctx->screen->has_msaa_sample_loc_bug;
3253
3254 /* Smoothing (only possible with nr_samples == 1) uses the same
3255 * sample locations as the MSAA it simulates.
3256 */
3257 if (nr_samples <= 1 && sctx->smoothing_enabled)
3258 nr_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3259
3260 /* On Polaris, the small primitive filter uses the sample locations
3261 * even when MSAA is off, so we need to make sure they're set to 0.
3262 */
3263 if (has_msaa_sample_loc_bug)
3264 nr_samples = MAX2(nr_samples, 1);
3265
3266 if (nr_samples != sctx->sample_locs_num_samples) {
3267 sctx->sample_locs_num_samples = nr_samples;
3268 si_emit_sample_locations(cs, nr_samples);
3269 }
3270
3271 if (sctx->family >= CHIP_POLARIS10) {
3272 unsigned small_prim_filter_cntl =
3273 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3274 /* line bug */
3275 S_028830_LINE_FILTER_DISABLE(sctx->family <= CHIP_POLARIS12);
3276
3277 /* The alternative of setting sample locations to 0 would
3278 * require a DB flush to avoid Z errors, see
3279 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3280 */
3281 if (has_msaa_sample_loc_bug &&
3282 sctx->framebuffer.nr_samples > 1 &&
3283 !rs->multisample_enable)
3284 small_prim_filter_cntl &= C_028830_SMALL_PRIM_FILTER_ENABLE;
3285
3286 radeon_opt_set_context_reg(sctx,
3287 R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
3288 SI_TRACKED_PA_SU_SMALL_PRIM_FILTER_CNTL,
3289 small_prim_filter_cntl);
3290 }
3291
3292 /* The exclusion bits can be set to improve rasterization efficiency
3293 * if no sample lies on the pixel boundary (-8 sample offset).
3294 */
3295 bool exclusion = sctx->chip_class >= CIK &&
3296 (!rs->multisample_enable || nr_samples != 16);
3297 radeon_opt_set_context_reg(sctx, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3298 SI_TRACKED_PA_SU_PRIM_FILTER_CNTL,
3299 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3300 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3301 }
3302
3303 static bool si_out_of_order_rasterization(struct si_context *sctx)
3304 {
3305 struct si_state_blend *blend = sctx->queued.named.blend;
3306 struct si_state_dsa *dsa = sctx->queued.named.dsa;
3307
3308 if (!sctx->screen->has_out_of_order_rast)
3309 return false;
3310
3311 unsigned colormask = sctx->framebuffer.colorbuf_enabled_4bit;
3312
3313 if (blend) {
3314 colormask &= blend->cb_target_enabled_4bit;
3315 } else {
3316 colormask = 0;
3317 }
3318
3319 /* Conservative: No logic op. */
3320 if (colormask && blend->logicop_enable)
3321 return false;
3322
3323 struct si_dsa_order_invariance dsa_order_invariant = {
3324 .zs = true, .pass_set = true, .pass_last = false
3325 };
3326
3327 if (sctx->framebuffer.state.zsbuf) {
3328 struct si_texture *zstex =
3329 (struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
3330 bool has_stencil = zstex->surface.has_stencil;
3331 dsa_order_invariant = dsa->order_invariance[has_stencil];
3332 if (!dsa_order_invariant.zs)
3333 return false;
3334
3335 /* The set of PS invocations is always order invariant,
3336 * except when early Z/S tests are requested. */
3337 if (sctx->ps_shader.cso &&
3338 sctx->ps_shader.cso->info.writes_memory &&
3339 sctx->ps_shader.cso->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] &&
3340 !dsa_order_invariant.pass_set)
3341 return false;
3342
3343 if (sctx->num_perfect_occlusion_queries != 0 &&
3344 !dsa_order_invariant.pass_set)
3345 return false;
3346 }
3347
3348 if (!colormask)
3349 return true;
3350
3351 unsigned blendmask = colormask & blend->blend_enable_4bit;
3352
3353 if (blendmask) {
3354 /* Only commutative blending. */
3355 if (blendmask & ~blend->commutative_4bit)
3356 return false;
3357
3358 if (!dsa_order_invariant.pass_set)
3359 return false;
3360 }
3361
3362 if (colormask & ~blendmask) {
3363 if (!dsa_order_invariant.pass_last)
3364 return false;
3365 }
3366
3367 return true;
3368 }
3369
3370 static void si_emit_msaa_config(struct si_context *sctx)
3371 {
3372 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3373 unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
3374 /* 33% faster rendering to linear color buffers */
3375 bool dst_is_linear = sctx->framebuffer.any_dst_linear;
3376 bool out_of_order_rast = si_out_of_order_rasterization(sctx);
3377 unsigned sc_mode_cntl_1 =
3378 S_028A4C_WALK_SIZE(dst_is_linear) |
3379 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear) |
3380 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
3381 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
3382 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3383 /* always 1: */
3384 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3385 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3386 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3387 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3388 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3389 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3390 unsigned db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3391 S_028804_INCOHERENT_EQAA_READS(1) |
3392 S_028804_INTERPOLATE_COMP_Z(1) |
3393 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
3394 unsigned coverage_samples, color_samples, z_samples;
3395
3396 /* S: Coverage samples (up to 16x):
3397 * - Scan conversion samples (PA_SC_AA_CONFIG.MSAA_NUM_SAMPLES)
3398 * - CB FMASK samples (CB_COLORi_ATTRIB.NUM_SAMPLES)
3399 *
3400 * Z: Z/S samples (up to 8x, must be <= coverage samples and >= color samples):
3401 * - Value seen by DB (DB_Z_INFO.NUM_SAMPLES)
3402 * - Value seen by CB, must be correct even if Z/S is unbound (DB_EQAA.MAX_ANCHOR_SAMPLES)
3403 * # Missing samples are derived from Z planes if Z is compressed (up to 16x quality), or
3404 * # from the closest defined sample if Z is uncompressed (same quality as the number of
3405 * # Z samples).
3406 *
3407 * F: Color samples (up to 8x, must be <= coverage samples):
3408 * - CB color samples (CB_COLORi_ATTRIB.NUM_FRAGMENTS)
3409 * - PS iter samples (DB_EQAA.PS_ITER_SAMPLES)
3410 *
3411 * Can be anything between coverage and color samples:
3412 * - SampleMaskIn samples (PA_SC_AA_CONFIG.MSAA_EXPOSED_SAMPLES)
3413 * - SampleMaskOut samples (DB_EQAA.MASK_EXPORT_NUM_SAMPLES)
3414 * - Alpha-to-coverage samples (DB_EQAA.ALPHA_TO_MASK_NUM_SAMPLES)
3415 * - Occlusion query samples (DB_COUNT_CONTROL.SAMPLE_RATE)
3416 * # All are currently set the same as coverage samples.
3417 *
3418 * If color samples < coverage samples, FMASK has a higher bpp to store an "unknown"
3419 * flag for undefined color samples. A shader-based resolve must handle unknowns
3420 * or mask them out with AND. Unknowns can also be guessed from neighbors via
3421 * an edge-detect shader-based resolve, which is required to make "color samples = 1"
3422 * useful. The CB resolve always drops unknowns.
3423 *
3424 * Sensible AA configurations:
3425 * EQAA 16s 8z 8f - might look the same as 16x MSAA if Z is compressed
3426 * EQAA 16s 8z 4f - might look the same as 16x MSAA if Z is compressed
3427 * EQAA 16s 4z 4f - might look the same as 16x MSAA if Z is compressed
3428 * EQAA 8s 8z 8f = 8x MSAA
3429 * EQAA 8s 8z 4f - might look the same as 8x MSAA
3430 * EQAA 8s 8z 2f - might look the same as 8x MSAA with low-density geometry
3431 * EQAA 8s 4z 4f - might look the same as 8x MSAA if Z is compressed
3432 * EQAA 8s 4z 2f - might look the same as 8x MSAA with low-density geometry if Z is compressed
3433 * EQAA 4s 4z 4f = 4x MSAA
3434 * EQAA 4s 4z 2f - might look the same as 4x MSAA with low-density geometry
3435 * EQAA 2s 2z 2f = 2x MSAA
3436 */
3437 if (sctx->framebuffer.nr_samples > 1) {
3438 coverage_samples = sctx->framebuffer.nr_samples;
3439 color_samples = sctx->framebuffer.nr_color_samples;
3440
3441 if (sctx->framebuffer.state.zsbuf) {
3442 z_samples = sctx->framebuffer.state.zsbuf->texture->nr_samples;
3443 z_samples = MAX2(1, z_samples);
3444 } else {
3445 z_samples = coverage_samples;
3446 }
3447 } else if (sctx->smoothing_enabled) {
3448 coverage_samples = color_samples = z_samples = SI_NUM_SMOOTH_AA_SAMPLES;
3449 } else {
3450 coverage_samples = color_samples = z_samples = 1;
3451 }
3452
3453 /* Required by OpenGL line rasterization.
3454 *
3455 * TODO: We should also enable perpendicular endcaps for AA lines,
3456 * but that requires implementing line stippling in the pixel
3457 * shader. SC can only do line stippling with axis-aligned
3458 * endcaps.
3459 */
3460 unsigned sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3461 unsigned sc_aa_config = 0;
3462
3463 if (coverage_samples > 1) {
3464 /* distance from the pixel center, indexed by log2(nr_samples) */
3465 static unsigned max_dist[] = {
3466 0, /* unused */
3467 4, /* 2x MSAA */
3468 6, /* 4x MSAA */
3469 7, /* 8x MSAA */
3470 8, /* 16x MSAA */
3471 };
3472 unsigned log_samples = util_logbase2(coverage_samples);
3473 unsigned log_z_samples = util_logbase2(z_samples);
3474 unsigned ps_iter_samples = si_get_ps_iter_samples(sctx);
3475 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
3476
3477 sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1);
3478 sc_aa_config = S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
3479 S_028BE0_MAX_SAMPLE_DIST(max_dist[log_samples]) |
3480 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples);
3481
3482 if (sctx->framebuffer.nr_samples > 1) {
3483 db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
3484 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
3485 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
3486 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
3487 sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
3488 } else if (sctx->smoothing_enabled) {
3489 db_eqaa |= S_028804_OVERRASTERIZATION_AMOUNT(log_samples);
3490 }
3491 }
3492
3493 /* R_028BDC_PA_SC_LINE_CNTL, R_028BE0_PA_SC_AA_CONFIG */
3494 radeon_opt_set_context_reg2(sctx, R_028BDC_PA_SC_LINE_CNTL,
3495 SI_TRACKED_PA_SC_LINE_CNTL, sc_line_cntl,
3496 sc_aa_config);
3497 /* R_028804_DB_EQAA */
3498 radeon_opt_set_context_reg(sctx, R_028804_DB_EQAA, SI_TRACKED_DB_EQAA,
3499 db_eqaa);
3500 /* R_028A4C_PA_SC_MODE_CNTL_1 */
3501 radeon_opt_set_context_reg(sctx, R_028A4C_PA_SC_MODE_CNTL_1,
3502 SI_TRACKED_PA_SC_MODE_CNTL_1, sc_mode_cntl_1);
3503
3504 /* GFX9: Flush DFSM when the AA mode changes. */
3505 if (sctx->screen->dfsm_allowed) {
3506 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3507 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3508 }
3509 }
3510
3511 void si_update_ps_iter_samples(struct si_context *sctx)
3512 {
3513 if (sctx->framebuffer.nr_samples > 1)
3514 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3515 if (sctx->screen->dpbb_allowed)
3516 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3517 }
3518
3519 static void si_set_min_samples(struct pipe_context *ctx, unsigned min_samples)
3520 {
3521 struct si_context *sctx = (struct si_context *)ctx;
3522
3523 /* The hardware can only do sample shading with 2^n samples. */
3524 min_samples = util_next_power_of_two(min_samples);
3525
3526 if (sctx->ps_iter_samples == min_samples)
3527 return;
3528
3529 sctx->ps_iter_samples = min_samples;
3530 sctx->do_update_shaders = true;
3531
3532 si_update_ps_iter_samples(sctx);
3533 }
3534
3535 /*
3536 * Samplers
3537 */
3538
3539 /**
3540 * Build the sampler view descriptor for a buffer texture.
3541 * @param state 256-bit descriptor; only the high 128 bits are filled in
3542 */
3543 void
3544 si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
3545 enum pipe_format format,
3546 unsigned offset, unsigned size,
3547 uint32_t *state)
3548 {
3549 const struct util_format_description *desc;
3550 int first_non_void;
3551 unsigned stride;
3552 unsigned num_records;
3553 unsigned num_format, data_format;
3554
3555 desc = util_format_description(format);
3556 first_non_void = util_format_get_first_non_void_channel(format);
3557 stride = desc->block.bits / 8;
3558 num_format = si_translate_buffer_numformat(&screen->b, desc, first_non_void);
3559 data_format = si_translate_buffer_dataformat(&screen->b, desc, first_non_void);
3560
3561 num_records = size / stride;
3562 num_records = MIN2(num_records, (buf->b.b.width0 - offset) / stride);
3563
3564 /* The NUM_RECORDS field has a different meaning depending on the chip,
3565 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3566 *
3567 * SI-CIK:
3568 * - If STRIDE == 0, it's in byte units.
3569 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3570 *
3571 * VI:
3572 * - For SMEM and STRIDE == 0, it's in byte units.
3573 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3574 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3575 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3576 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3577 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3578 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3579 * That way the same descriptor can be used by both SMEM and VMEM.
3580 *
3581 * GFX9:
3582 * - For SMEM and STRIDE == 0, it's in byte units.
3583 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3584 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3585 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3586 */
3587 if (screen->info.chip_class >= GFX9)
3588 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3589 * from STRIDE to bytes. This works around it by setting
3590 * NUM_RECORDS to at least the size of one element, so that
3591 * the first element is readable when IDXEN == 0.
3592 *
3593 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3594 * IDXEN is enforced?
3595 */
3596 num_records = num_records ? MAX2(num_records, stride) : 0;
3597 else if (screen->info.chip_class == VI)
3598 num_records *= stride;
3599
3600 state[4] = 0;
3601 state[5] = S_008F04_STRIDE(stride);
3602 state[6] = num_records;
3603 state[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc->swizzle[0])) |
3604 S_008F0C_DST_SEL_Y(si_map_swizzle(desc->swizzle[1])) |
3605 S_008F0C_DST_SEL_Z(si_map_swizzle(desc->swizzle[2])) |
3606 S_008F0C_DST_SEL_W(si_map_swizzle(desc->swizzle[3])) |
3607 S_008F0C_NUM_FORMAT(num_format) |
3608 S_008F0C_DATA_FORMAT(data_format);
3609 }
3610
3611 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
3612 {
3613 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3614
3615 if (swizzle[3] == PIPE_SWIZZLE_X) {
3616 /* For the pre-defined border color values (white, opaque
3617 * black, transparent black), the only thing that matters is
3618 * that the alpha channel winds up in the correct place
3619 * (because the RGB channels are all the same) so either of
3620 * these enumerations will work.
3621 */
3622 if (swizzle[2] == PIPE_SWIZZLE_Y)
3623 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
3624 else
3625 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
3626 } else if (swizzle[0] == PIPE_SWIZZLE_X) {
3627 if (swizzle[1] == PIPE_SWIZZLE_Y)
3628 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
3629 else
3630 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
3631 } else if (swizzle[1] == PIPE_SWIZZLE_X) {
3632 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
3633 } else if (swizzle[2] == PIPE_SWIZZLE_X) {
3634 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
3635 }
3636
3637 return bc_swizzle;
3638 }
3639
3640 /**
3641 * Build the sampler view descriptor for a texture.
3642 */
3643 void
3644 si_make_texture_descriptor(struct si_screen *screen,
3645 struct si_texture *tex,
3646 bool sampler,
3647 enum pipe_texture_target target,
3648 enum pipe_format pipe_format,
3649 const unsigned char state_swizzle[4],
3650 unsigned first_level, unsigned last_level,
3651 unsigned first_layer, unsigned last_layer,
3652 unsigned width, unsigned height, unsigned depth,
3653 uint32_t *state,
3654 uint32_t *fmask_state)
3655 {
3656 struct pipe_resource *res = &tex->buffer.b.b;
3657 const struct util_format_description *desc;
3658 unsigned char swizzle[4];
3659 int first_non_void;
3660 unsigned num_format, data_format, type, num_samples;
3661 uint64_t va;
3662
3663 desc = util_format_description(pipe_format);
3664
3665 num_samples = desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS ?
3666 MAX2(1, res->nr_samples) :
3667 MAX2(1, res->nr_storage_samples);
3668
3669 if (desc->colorspace == UTIL_FORMAT_COLORSPACE_ZS) {
3670 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
3671 const unsigned char swizzle_yyyy[4] = {1, 1, 1, 1};
3672 const unsigned char swizzle_wwww[4] = {3, 3, 3, 3};
3673
3674 switch (pipe_format) {
3675 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3676 case PIPE_FORMAT_X32_S8X24_UINT:
3677 case PIPE_FORMAT_X8Z24_UNORM:
3678 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3679 break;
3680 case PIPE_FORMAT_X24S8_UINT:
3681 /*
3682 * X24S8 is implemented as an 8_8_8_8 data format, to
3683 * fix texture gathers. This affects at least
3684 * GL45-CTS.texture_cube_map_array.sampling on VI.
3685 */
3686 if (screen->info.chip_class <= VI)
3687 util_format_compose_swizzles(swizzle_wwww, state_swizzle, swizzle);
3688 else
3689 util_format_compose_swizzles(swizzle_yyyy, state_swizzle, swizzle);
3690 break;
3691 default:
3692 util_format_compose_swizzles(swizzle_xxxx, state_swizzle, swizzle);
3693 }
3694 } else {
3695 util_format_compose_swizzles(desc->swizzle, state_swizzle, swizzle);
3696 }
3697
3698 first_non_void = util_format_get_first_non_void_channel(pipe_format);
3699
3700 switch (pipe_format) {
3701 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
3702 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3703 break;
3704 default:
3705 if (first_non_void < 0) {
3706 if (util_format_is_compressed(pipe_format)) {
3707 switch (pipe_format) {
3708 case PIPE_FORMAT_DXT1_SRGB:
3709 case PIPE_FORMAT_DXT1_SRGBA:
3710 case PIPE_FORMAT_DXT3_SRGBA:
3711 case PIPE_FORMAT_DXT5_SRGBA:
3712 case PIPE_FORMAT_BPTC_SRGBA:
3713 case PIPE_FORMAT_ETC2_SRGB8:
3714 case PIPE_FORMAT_ETC2_SRGB8A1:
3715 case PIPE_FORMAT_ETC2_SRGBA8:
3716 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3717 break;
3718 case PIPE_FORMAT_RGTC1_SNORM:
3719 case PIPE_FORMAT_LATC1_SNORM:
3720 case PIPE_FORMAT_RGTC2_SNORM:
3721 case PIPE_FORMAT_LATC2_SNORM:
3722 case PIPE_FORMAT_ETC2_R11_SNORM:
3723 case PIPE_FORMAT_ETC2_RG11_SNORM:
3724 /* implies float, so use SNORM/UNORM to determine
3725 whether data is signed or not */
3726 case PIPE_FORMAT_BPTC_RGB_FLOAT:
3727 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3728 break;
3729 default:
3730 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3731 break;
3732 }
3733 } else if (desc->layout == UTIL_FORMAT_LAYOUT_SUBSAMPLED) {
3734 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3735 } else {
3736 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3737 }
3738 } else if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB) {
3739 num_format = V_008F14_IMG_NUM_FORMAT_SRGB;
3740 } else {
3741 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3742
3743 switch (desc->channel[first_non_void].type) {
3744 case UTIL_FORMAT_TYPE_FLOAT:
3745 num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
3746 break;
3747 case UTIL_FORMAT_TYPE_SIGNED:
3748 if (desc->channel[first_non_void].normalized)
3749 num_format = V_008F14_IMG_NUM_FORMAT_SNORM;
3750 else if (desc->channel[first_non_void].pure_integer)
3751 num_format = V_008F14_IMG_NUM_FORMAT_SINT;
3752 else
3753 num_format = V_008F14_IMG_NUM_FORMAT_SSCALED;
3754 break;
3755 case UTIL_FORMAT_TYPE_UNSIGNED:
3756 if (desc->channel[first_non_void].normalized)
3757 num_format = V_008F14_IMG_NUM_FORMAT_UNORM;
3758 else if (desc->channel[first_non_void].pure_integer)
3759 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3760 else
3761 num_format = V_008F14_IMG_NUM_FORMAT_USCALED;
3762 }
3763 }
3764 }
3765
3766 data_format = si_translate_texformat(&screen->b, pipe_format, desc, first_non_void);
3767 if (data_format == ~0) {
3768 data_format = 0;
3769 }
3770
3771 /* S8 with Z32 HTILE needs a special format. */
3772 if (screen->info.chip_class >= GFX9 &&
3773 pipe_format == PIPE_FORMAT_S8_UINT &&
3774 tex->tc_compatible_htile)
3775 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
3776
3777 if (!sampler &&
3778 (res->target == PIPE_TEXTURE_CUBE ||
3779 res->target == PIPE_TEXTURE_CUBE_ARRAY ||
3780 (screen->info.chip_class <= VI &&
3781 res->target == PIPE_TEXTURE_3D))) {
3782 /* For the purpose of shader images, treat cube maps and 3D
3783 * textures as 2D arrays. For 3D textures, the address
3784 * calculations for mipmaps are different, so we rely on the
3785 * caller to effectively disable mipmaps.
3786 */
3787 type = V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
3788
3789 assert(res->target != PIPE_TEXTURE_3D || (first_level == 0 && last_level == 0));
3790 } else {
3791 type = si_tex_dim(screen, tex, target, num_samples);
3792 }
3793
3794 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
3795 height = 1;
3796 depth = res->array_size;
3797 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
3798 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
3799 if (sampler || res->target != PIPE_TEXTURE_3D)
3800 depth = res->array_size;
3801 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
3802 depth = res->array_size / 6;
3803
3804 state[0] = 0;
3805 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
3806 S_008F14_NUM_FORMAT_GFX6(num_format));
3807 state[2] = (S_008F18_WIDTH(width - 1) |
3808 S_008F18_HEIGHT(height - 1) |
3809 S_008F18_PERF_MOD(4));
3810 state[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
3811 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
3812 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
3813 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
3814 S_008F1C_BASE_LEVEL(num_samples > 1 ? 0 : first_level) |
3815 S_008F1C_LAST_LEVEL(num_samples > 1 ?
3816 util_logbase2(num_samples) :
3817 last_level) |
3818 S_008F1C_TYPE(type));
3819 state[4] = 0;
3820 state[5] = S_008F24_BASE_ARRAY(first_layer);
3821 state[6] = 0;
3822 state[7] = 0;
3823
3824 if (screen->info.chip_class >= GFX9) {
3825 unsigned bc_swizzle = gfx9_border_color_swizzle(desc->swizzle);
3826
3827 /* Depth is the the last accessible layer on Gfx9.
3828 * The hw doesn't need to know the total number of layers.
3829 */
3830 if (type == V_008F1C_SQ_RSRC_IMG_3D)
3831 state[4] |= S_008F20_DEPTH(depth - 1);
3832 else
3833 state[4] |= S_008F20_DEPTH(last_layer);
3834
3835 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
3836 state[5] |= S_008F24_MAX_MIP(num_samples > 1 ?
3837 util_logbase2(num_samples) :
3838 tex->buffer.b.b.last_level);
3839 } else {
3840 state[3] |= S_008F1C_POW2_PAD(res->last_level > 0);
3841 state[4] |= S_008F20_DEPTH(depth - 1);
3842 state[5] |= S_008F24_LAST_ARRAY(last_layer);
3843 }
3844
3845 if (tex->dcc_offset) {
3846 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(pipe_format));
3847 } else {
3848 /* The last dword is unused by hw. The shader uses it to clear
3849 * bits in the first dword of sampler state.
3850 */
3851 if (screen->info.chip_class <= CIK && res->nr_samples <= 1) {
3852 if (first_level == last_level)
3853 state[7] = C_008F30_MAX_ANISO_RATIO;
3854 else
3855 state[7] = 0xffffffff;
3856 }
3857 }
3858
3859 /* Initialize the sampler view for FMASK. */
3860 if (tex->surface.fmask_size) {
3861 uint32_t data_format, num_format;
3862
3863 va = tex->buffer.gpu_address + tex->fmask_offset;
3864
3865 #define FMASK(s,f) (((unsigned)(MAX2(1, s)) * 16) + (MAX2(1, f)))
3866 if (screen->info.chip_class >= GFX9) {
3867 data_format = V_008F14_IMG_DATA_FORMAT_FMASK;
3868 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3869 case FMASK(2,1):
3870 num_format = V_008F14_IMG_FMASK_8_2_1;
3871 break;
3872 case FMASK(2,2):
3873 num_format = V_008F14_IMG_FMASK_8_2_2;
3874 break;
3875 case FMASK(4,1):
3876 num_format = V_008F14_IMG_FMASK_8_4_1;
3877 break;
3878 case FMASK(4,2):
3879 num_format = V_008F14_IMG_FMASK_8_4_2;
3880 break;
3881 case FMASK(4,4):
3882 num_format = V_008F14_IMG_FMASK_8_4_4;
3883 break;
3884 case FMASK(8,1):
3885 num_format = V_008F14_IMG_FMASK_8_8_1;
3886 break;
3887 case FMASK(8,2):
3888 num_format = V_008F14_IMG_FMASK_16_8_2;
3889 break;
3890 case FMASK(8,4):
3891 num_format = V_008F14_IMG_FMASK_32_8_4;
3892 break;
3893 case FMASK(8,8):
3894 num_format = V_008F14_IMG_FMASK_32_8_8;
3895 break;
3896 case FMASK(16,1):
3897 num_format = V_008F14_IMG_FMASK_16_16_1;
3898 break;
3899 case FMASK(16,2):
3900 num_format = V_008F14_IMG_FMASK_32_16_2;
3901 break;
3902 case FMASK(16,4):
3903 num_format = V_008F14_IMG_FMASK_64_16_4;
3904 break;
3905 case FMASK(16,8):
3906 num_format = V_008F14_IMG_FMASK_64_16_8;
3907 break;
3908 default:
3909 unreachable("invalid nr_samples");
3910 }
3911 } else {
3912 switch (FMASK(res->nr_samples, res->nr_storage_samples)) {
3913 case FMASK(2,1):
3914 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F1;
3915 break;
3916 case FMASK(2,2):
3917 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
3918 break;
3919 case FMASK(4,1):
3920 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F1;
3921 break;
3922 case FMASK(4,2):
3923 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F2;
3924 break;
3925 case FMASK(4,4):
3926 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
3927 break;
3928 case FMASK(8,1):
3929 data_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S8_F1;
3930 break;
3931 case FMASK(8,2):
3932 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S8_F2;
3933 break;
3934 case FMASK(8,4):
3935 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F4;
3936 break;
3937 case FMASK(8,8):
3938 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
3939 break;
3940 case FMASK(16,1):
3941 data_format = V_008F14_IMG_DATA_FORMAT_FMASK16_S16_F1;
3942 break;
3943 case FMASK(16,2):
3944 data_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S16_F2;
3945 break;
3946 case FMASK(16,4):
3947 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F4;
3948 break;
3949 case FMASK(16,8):
3950 data_format = V_008F14_IMG_DATA_FORMAT_FMASK64_S16_F8;
3951 break;
3952 default:
3953 unreachable("invalid nr_samples");
3954 }
3955 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
3956 }
3957 #undef FMASK
3958
3959 fmask_state[0] = (va >> 8) | tex->surface.fmask_tile_swizzle;
3960 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
3961 S_008F14_DATA_FORMAT_GFX6(data_format) |
3962 S_008F14_NUM_FORMAT_GFX6(num_format);
3963 fmask_state[2] = S_008F18_WIDTH(width - 1) |
3964 S_008F18_HEIGHT(height - 1);
3965 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
3966 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
3967 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
3968 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
3969 S_008F1C_TYPE(si_tex_dim(screen, tex, target, 0));
3970 fmask_state[4] = 0;
3971 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
3972 fmask_state[6] = 0;
3973 fmask_state[7] = 0;
3974
3975 if (screen->info.chip_class >= GFX9) {
3976 fmask_state[3] |= S_008F1C_SW_MODE(tex->surface.u.gfx9.fmask.swizzle_mode);
3977 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
3978 S_008F20_PITCH_GFX9(tex->surface.u.gfx9.fmask.epitch);
3979 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(tex->surface.u.gfx9.cmask.pipe_aligned) |
3980 S_008F24_META_RB_ALIGNED(tex->surface.u.gfx9.cmask.rb_aligned);
3981 } else {
3982 fmask_state[3] |= S_008F1C_TILING_INDEX(tex->surface.u.legacy.fmask.tiling_index);
3983 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
3984 S_008F20_PITCH_GFX6(tex->surface.u.legacy.fmask.pitch_in_pixels - 1);
3985 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
3986 }
3987 }
3988 }
3989
3990 /**
3991 * Create a sampler view.
3992 *
3993 * @param ctx context
3994 * @param texture texture
3995 * @param state sampler view template
3996 * @param width0 width0 override (for compressed textures as int)
3997 * @param height0 height0 override (for compressed textures as int)
3998 * @param force_level set the base address to the level (for compressed textures)
3999 */
4000 struct pipe_sampler_view *
4001 si_create_sampler_view_custom(struct pipe_context *ctx,
4002 struct pipe_resource *texture,
4003 const struct pipe_sampler_view *state,
4004 unsigned width0, unsigned height0,
4005 unsigned force_level)
4006 {
4007 struct si_context *sctx = (struct si_context*)ctx;
4008 struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
4009 struct si_texture *tex = (struct si_texture*)texture;
4010 unsigned base_level, first_level, last_level;
4011 unsigned char state_swizzle[4];
4012 unsigned height, depth, width;
4013 unsigned last_layer = state->u.tex.last_layer;
4014 enum pipe_format pipe_format;
4015 const struct legacy_surf_level *surflevel;
4016
4017 if (!view)
4018 return NULL;
4019
4020 /* initialize base object */
4021 view->base = *state;
4022 view->base.texture = NULL;
4023 view->base.reference.count = 1;
4024 view->base.context = ctx;
4025
4026 assert(texture);
4027 pipe_resource_reference(&view->base.texture, texture);
4028
4029 if (state->format == PIPE_FORMAT_X24S8_UINT ||
4030 state->format == PIPE_FORMAT_S8X24_UINT ||
4031 state->format == PIPE_FORMAT_X32_S8X24_UINT ||
4032 state->format == PIPE_FORMAT_S8_UINT)
4033 view->is_stencil_sampler = true;
4034
4035 /* Buffer resource. */
4036 if (texture->target == PIPE_BUFFER) {
4037 si_make_buffer_descriptor(sctx->screen,
4038 r600_resource(texture),
4039 state->format,
4040 state->u.buf.offset,
4041 state->u.buf.size,
4042 view->state);
4043 return &view->base;
4044 }
4045
4046 state_swizzle[0] = state->swizzle_r;
4047 state_swizzle[1] = state->swizzle_g;
4048 state_swizzle[2] = state->swizzle_b;
4049 state_swizzle[3] = state->swizzle_a;
4050
4051 base_level = 0;
4052 first_level = state->u.tex.first_level;
4053 last_level = state->u.tex.last_level;
4054 width = width0;
4055 height = height0;
4056 depth = texture->depth0;
4057
4058 if (sctx->chip_class <= VI && force_level) {
4059 assert(force_level == first_level &&
4060 force_level == last_level);
4061 base_level = force_level;
4062 first_level = 0;
4063 last_level = 0;
4064 width = u_minify(width, force_level);
4065 height = u_minify(height, force_level);
4066 depth = u_minify(depth, force_level);
4067 }
4068
4069 /* This is not needed if state trackers set last_layer correctly. */
4070 if (state->target == PIPE_TEXTURE_1D ||
4071 state->target == PIPE_TEXTURE_2D ||
4072 state->target == PIPE_TEXTURE_RECT ||
4073 state->target == PIPE_TEXTURE_CUBE)
4074 last_layer = state->u.tex.first_layer;
4075
4076 /* Texturing with separate depth and stencil. */
4077 pipe_format = state->format;
4078
4079 /* Depth/stencil texturing sometimes needs separate texture. */
4080 if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
4081 if (!tex->flushed_depth_texture &&
4082 !si_init_flushed_depth_texture(ctx, texture, NULL)) {
4083 pipe_resource_reference(&view->base.texture, NULL);
4084 FREE(view);
4085 return NULL;
4086 }
4087
4088 assert(tex->flushed_depth_texture);
4089
4090 /* Override format for the case where the flushed texture
4091 * contains only Z or only S.
4092 */
4093 if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
4094 pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
4095
4096 tex = tex->flushed_depth_texture;
4097 }
4098
4099 surflevel = tex->surface.u.legacy.level;
4100
4101 if (tex->db_compatible) {
4102 if (!view->is_stencil_sampler)
4103 pipe_format = tex->db_render_format;
4104
4105 switch (pipe_format) {
4106 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
4107 pipe_format = PIPE_FORMAT_Z32_FLOAT;
4108 break;
4109 case PIPE_FORMAT_X8Z24_UNORM:
4110 case PIPE_FORMAT_S8_UINT_Z24_UNORM:
4111 /* Z24 is always stored like this for DB
4112 * compatibility.
4113 */
4114 pipe_format = PIPE_FORMAT_Z24X8_UNORM;
4115 break;
4116 case PIPE_FORMAT_X24S8_UINT:
4117 case PIPE_FORMAT_S8X24_UINT:
4118 case PIPE_FORMAT_X32_S8X24_UINT:
4119 pipe_format = PIPE_FORMAT_S8_UINT;
4120 surflevel = tex->surface.u.legacy.stencil_level;
4121 break;
4122 default:;
4123 }
4124 }
4125
4126 view->dcc_incompatible =
4127 vi_dcc_formats_are_incompatible(texture,
4128 state->u.tex.first_level,
4129 state->format);
4130
4131 si_make_texture_descriptor(sctx->screen, tex, true,
4132 state->target, pipe_format, state_swizzle,
4133 first_level, last_level,
4134 state->u.tex.first_layer, last_layer,
4135 width, height, depth,
4136 view->state, view->fmask_state);
4137
4138 unsigned num_format = G_008F14_NUM_FORMAT_GFX6(view->state[1]);
4139 view->is_integer =
4140 num_format == V_008F14_IMG_NUM_FORMAT_USCALED ||
4141 num_format == V_008F14_IMG_NUM_FORMAT_SSCALED ||
4142 num_format == V_008F14_IMG_NUM_FORMAT_UINT ||
4143 num_format == V_008F14_IMG_NUM_FORMAT_SINT;
4144 view->base_level_info = &surflevel[base_level];
4145 view->base_level = base_level;
4146 view->block_width = util_format_get_blockwidth(pipe_format);
4147 return &view->base;
4148 }
4149
4150 static struct pipe_sampler_view *
4151 si_create_sampler_view(struct pipe_context *ctx,
4152 struct pipe_resource *texture,
4153 const struct pipe_sampler_view *state)
4154 {
4155 return si_create_sampler_view_custom(ctx, texture, state,
4156 texture ? texture->width0 : 0,
4157 texture ? texture->height0 : 0, 0);
4158 }
4159
4160 static void si_sampler_view_destroy(struct pipe_context *ctx,
4161 struct pipe_sampler_view *state)
4162 {
4163 struct si_sampler_view *view = (struct si_sampler_view *)state;
4164
4165 pipe_resource_reference(&state->texture, NULL);
4166 FREE(view);
4167 }
4168
4169 static bool wrap_mode_uses_border_color(unsigned wrap, bool linear_filter)
4170 {
4171 return wrap == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
4172 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER ||
4173 (linear_filter &&
4174 (wrap == PIPE_TEX_WRAP_CLAMP ||
4175 wrap == PIPE_TEX_WRAP_MIRROR_CLAMP));
4176 }
4177
4178 static uint32_t si_translate_border_color(struct si_context *sctx,
4179 const struct pipe_sampler_state *state,
4180 const union pipe_color_union *color,
4181 bool is_integer)
4182 {
4183 bool linear_filter = state->min_img_filter != PIPE_TEX_FILTER_NEAREST ||
4184 state->mag_img_filter != PIPE_TEX_FILTER_NEAREST;
4185
4186 if (!wrap_mode_uses_border_color(state->wrap_s, linear_filter) &&
4187 !wrap_mode_uses_border_color(state->wrap_t, linear_filter) &&
4188 !wrap_mode_uses_border_color(state->wrap_r, linear_filter))
4189 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4190
4191 #define simple_border_types(elt) \
4192 do { \
4193 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4194 color->elt[2] == 0 && color->elt[3] == 0) \
4195 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
4196 if (color->elt[0] == 0 && color->elt[1] == 0 && \
4197 color->elt[2] == 0 && color->elt[3] == 1) \
4198 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
4199 if (color->elt[0] == 1 && color->elt[1] == 1 && \
4200 color->elt[2] == 1 && color->elt[3] == 1) \
4201 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4202 } while (false)
4203
4204 if (is_integer)
4205 simple_border_types(ui);
4206 else
4207 simple_border_types(f);
4208
4209 #undef simple_border_types
4210
4211 int i;
4212
4213 /* Check if the border has been uploaded already. */
4214 for (i = 0; i < sctx->border_color_count; i++)
4215 if (memcmp(&sctx->border_color_table[i], color,
4216 sizeof(*color)) == 0)
4217 break;
4218
4219 if (i >= SI_MAX_BORDER_COLORS) {
4220 /* Getting 4096 unique border colors is very unlikely. */
4221 fprintf(stderr, "radeonsi: The border color table is full. "
4222 "Any new border colors will be just black. "
4223 "Please file a bug.\n");
4224 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK);
4225 }
4226
4227 if (i == sctx->border_color_count) {
4228 /* Upload a new border color. */
4229 memcpy(&sctx->border_color_table[i], color,
4230 sizeof(*color));
4231 util_memcpy_cpu_to_le32(&sctx->border_color_map[i],
4232 color, sizeof(*color));
4233 sctx->border_color_count++;
4234 }
4235
4236 return S_008F3C_BORDER_COLOR_PTR(i) |
4237 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER);
4238 }
4239
4240 static inline int S_FIXED(float value, unsigned frac_bits)
4241 {
4242 return value * (1 << frac_bits);
4243 }
4244
4245 static inline unsigned si_tex_filter(unsigned filter, unsigned max_aniso)
4246 {
4247 if (filter == PIPE_TEX_FILTER_LINEAR)
4248 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
4249 : V_008F38_SQ_TEX_XY_FILTER_BILINEAR;
4250 else
4251 return max_aniso > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
4252 : V_008F38_SQ_TEX_XY_FILTER_POINT;
4253 }
4254
4255 static inline unsigned si_tex_aniso_filter(unsigned filter)
4256 {
4257 if (filter < 2)
4258 return 0;
4259 if (filter < 4)
4260 return 1;
4261 if (filter < 8)
4262 return 2;
4263 if (filter < 16)
4264 return 3;
4265 return 4;
4266 }
4267
4268 static void *si_create_sampler_state(struct pipe_context *ctx,
4269 const struct pipe_sampler_state *state)
4270 {
4271 struct si_context *sctx = (struct si_context *)ctx;
4272 struct si_screen *sscreen = sctx->screen;
4273 struct si_sampler_state *rstate = CALLOC_STRUCT(si_sampler_state);
4274 unsigned max_aniso = sscreen->force_aniso >= 0 ? sscreen->force_aniso
4275 : state->max_anisotropy;
4276 unsigned max_aniso_ratio = si_tex_aniso_filter(max_aniso);
4277 union pipe_color_union clamped_border_color;
4278
4279 if (!rstate) {
4280 return NULL;
4281 }
4282
4283 #ifdef DEBUG
4284 rstate->magic = SI_SAMPLER_STATE_MAGIC;
4285 #endif
4286 rstate->val[0] = (S_008F30_CLAMP_X(si_tex_wrap(state->wrap_s)) |
4287 S_008F30_CLAMP_Y(si_tex_wrap(state->wrap_t)) |
4288 S_008F30_CLAMP_Z(si_tex_wrap(state->wrap_r)) |
4289 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4290 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state->compare_func)) |
4291 S_008F30_FORCE_UNNORMALIZED(!state->normalized_coords) |
4292 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4293 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4294 S_008F30_DISABLE_CUBE_WRAP(!state->seamless_cube_map) |
4295 S_008F30_COMPAT_MODE(sctx->chip_class >= VI));
4296 rstate->val[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 8)) |
4297 S_008F34_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 8)) |
4298 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4299 rstate->val[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 8)) |
4300 S_008F38_XY_MAG_FILTER(si_tex_filter(state->mag_img_filter, max_aniso)) |
4301 S_008F38_XY_MIN_FILTER(si_tex_filter(state->min_img_filter, max_aniso)) |
4302 S_008F38_MIP_FILTER(si_tex_mipfilter(state->min_mip_filter)) |
4303 S_008F38_MIP_POINT_PRECLAMP(0) |
4304 S_008F38_DISABLE_LSB_CEIL(sctx->chip_class <= VI) |
4305 S_008F38_FILTER_PREC_FIX(1) |
4306 S_008F38_ANISO_OVERRIDE(sctx->chip_class >= VI));
4307 rstate->val[3] = si_translate_border_color(sctx, state, &state->border_color, false);
4308
4309 /* Create sampler resource for integer textures. */
4310 memcpy(rstate->integer_val, rstate->val, sizeof(rstate->val));
4311 rstate->integer_val[3] = si_translate_border_color(sctx, state, &state->border_color, true);
4312
4313 /* Create sampler resource for upgraded depth textures. */
4314 memcpy(rstate->upgraded_depth_val, rstate->val, sizeof(rstate->val));
4315
4316 for (unsigned i = 0; i < 4; ++i) {
4317 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4318 * when the border color is 1.0. */
4319 clamped_border_color.f[i] = CLAMP(state->border_color.f[0], 0, 1);
4320 }
4321
4322 if (memcmp(&state->border_color, &clamped_border_color, sizeof(clamped_border_color)) == 0)
4323 rstate->upgraded_depth_val[3] |= S_008F3C_UPGRADED_DEPTH(1);
4324 else
4325 rstate->upgraded_depth_val[3] =
4326 si_translate_border_color(sctx, state, &clamped_border_color, false) |
4327 S_008F3C_UPGRADED_DEPTH(1);
4328
4329 return rstate;
4330 }
4331
4332 static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
4333 {
4334 struct si_context *sctx = (struct si_context *)ctx;
4335
4336 if (sctx->sample_mask == (uint16_t)sample_mask)
4337 return;
4338
4339 sctx->sample_mask = sample_mask;
4340 si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
4341 }
4342
4343 static void si_emit_sample_mask(struct si_context *sctx)
4344 {
4345 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4346 unsigned mask = sctx->sample_mask;
4347
4348 /* Needed for line and polygon smoothing as well as for the Polaris
4349 * small primitive filter. We expect the state tracker to take care of
4350 * this for us.
4351 */
4352 assert(mask == 0xffff || sctx->framebuffer.nr_samples > 1 ||
4353 (mask & 1 && sctx->blitter->running));
4354
4355 radeon_set_context_reg_seq(cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
4356 radeon_emit(cs, mask | (mask << 16));
4357 radeon_emit(cs, mask | (mask << 16));
4358 }
4359
4360 static void si_delete_sampler_state(struct pipe_context *ctx, void *state)
4361 {
4362 #ifdef DEBUG
4363 struct si_sampler_state *s = state;
4364
4365 assert(s->magic == SI_SAMPLER_STATE_MAGIC);
4366 s->magic = 0;
4367 #endif
4368 free(state);
4369 }
4370
4371 /*
4372 * Vertex elements & buffers
4373 */
4374
4375 static void *si_create_vertex_elements(struct pipe_context *ctx,
4376 unsigned count,
4377 const struct pipe_vertex_element *elements)
4378 {
4379 struct si_screen *sscreen = (struct si_screen*)ctx->screen;
4380 struct si_vertex_elements *v = CALLOC_STRUCT(si_vertex_elements);
4381 bool used[SI_NUM_VERTEX_BUFFERS] = {};
4382 int i;
4383
4384 assert(count <= SI_MAX_ATTRIBS);
4385 if (!v)
4386 return NULL;
4387
4388 v->count = count;
4389 v->desc_list_byte_size = align(count * 16, SI_CPDMA_ALIGNMENT);
4390
4391 for (i = 0; i < count; ++i) {
4392 const struct util_format_description *desc;
4393 const struct util_format_channel_description *channel;
4394 unsigned data_format, num_format;
4395 int first_non_void;
4396 unsigned vbo_index = elements[i].vertex_buffer_index;
4397 unsigned char swizzle[4];
4398
4399 if (vbo_index >= SI_NUM_VERTEX_BUFFERS) {
4400 FREE(v);
4401 return NULL;
4402 }
4403
4404 if (elements[i].instance_divisor) {
4405 v->uses_instance_divisors = true;
4406 v->instance_divisors[i] = elements[i].instance_divisor;
4407
4408 if (v->instance_divisors[i] == 1)
4409 v->instance_divisor_is_one |= 1u << i;
4410 else
4411 v->instance_divisor_is_fetched |= 1u << i;
4412 }
4413
4414 if (!used[vbo_index]) {
4415 v->first_vb_use_mask |= 1 << i;
4416 used[vbo_index] = true;
4417 }
4418
4419 desc = util_format_description(elements[i].src_format);
4420 first_non_void = util_format_get_first_non_void_channel(elements[i].src_format);
4421 data_format = si_translate_buffer_dataformat(ctx->screen, desc, first_non_void);
4422 num_format = si_translate_buffer_numformat(ctx->screen, desc, first_non_void);
4423 channel = first_non_void >= 0 ? &desc->channel[first_non_void] : NULL;
4424 memcpy(swizzle, desc->swizzle, sizeof(swizzle));
4425
4426 v->format_size[i] = desc->block.bits / 8;
4427 v->src_offset[i] = elements[i].src_offset;
4428 v->vertex_buffer_index[i] = vbo_index;
4429
4430 /* The hardware always treats the 2-bit alpha channel as
4431 * unsigned, so a shader workaround is needed. The affected
4432 * chips are VI and older except Stoney (GFX8.1).
4433 */
4434 if (data_format == V_008F0C_BUF_DATA_FORMAT_2_10_10_10 &&
4435 sscreen->info.chip_class <= VI &&
4436 sscreen->info.family != CHIP_STONEY) {
4437 if (num_format == V_008F0C_BUF_NUM_FORMAT_SNORM) {
4438 v->fix_fetch[i] = SI_FIX_FETCH_A2_SNORM;
4439 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SSCALED) {
4440 v->fix_fetch[i] = SI_FIX_FETCH_A2_SSCALED;
4441 } else if (num_format == V_008F0C_BUF_NUM_FORMAT_SINT) {
4442 /* This isn't actually used in OpenGL. */
4443 v->fix_fetch[i] = SI_FIX_FETCH_A2_SINT;
4444 }
4445 } else if (channel && channel->type == UTIL_FORMAT_TYPE_FIXED) {
4446 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4447 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_FIXED;
4448 else
4449 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_FIXED;
4450 } else if (channel && channel->size == 32 && !channel->pure_integer) {
4451 if (channel->type == UTIL_FORMAT_TYPE_SIGNED) {
4452 if (channel->normalized) {
4453 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4454 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_SNORM;
4455 else
4456 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SNORM;
4457 } else {
4458 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_SSCALED;
4459 }
4460 } else if (channel->type == UTIL_FORMAT_TYPE_UNSIGNED) {
4461 if (channel->normalized) {
4462 if (desc->swizzle[3] == PIPE_SWIZZLE_1)
4463 v->fix_fetch[i] = SI_FIX_FETCH_RGBX_32_UNORM;
4464 else
4465 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_UNORM;
4466 } else {
4467 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_32_USCALED;
4468 }
4469 }
4470 } else if (channel && channel->size == 64 &&
4471 channel->type == UTIL_FORMAT_TYPE_FLOAT) {
4472 switch (desc->nr_channels) {
4473 case 1:
4474 case 2:
4475 v->fix_fetch[i] = SI_FIX_FETCH_RG_64_FLOAT;
4476 swizzle[0] = PIPE_SWIZZLE_X;
4477 swizzle[1] = PIPE_SWIZZLE_Y;
4478 swizzle[2] = desc->nr_channels == 2 ? PIPE_SWIZZLE_Z : PIPE_SWIZZLE_0;
4479 swizzle[3] = desc->nr_channels == 2 ? PIPE_SWIZZLE_W : PIPE_SWIZZLE_0;
4480 break;
4481 case 3:
4482 v->fix_fetch[i] = SI_FIX_FETCH_RGB_64_FLOAT;
4483 swizzle[0] = PIPE_SWIZZLE_X; /* 3 loads */
4484 swizzle[1] = PIPE_SWIZZLE_Y;
4485 swizzle[2] = PIPE_SWIZZLE_0;
4486 swizzle[3] = PIPE_SWIZZLE_0;
4487 break;
4488 case 4:
4489 v->fix_fetch[i] = SI_FIX_FETCH_RGBA_64_FLOAT;
4490 swizzle[0] = PIPE_SWIZZLE_X; /* 2 loads */
4491 swizzle[1] = PIPE_SWIZZLE_Y;
4492 swizzle[2] = PIPE_SWIZZLE_Z;
4493 swizzle[3] = PIPE_SWIZZLE_W;
4494 break;
4495 default:
4496 assert(0);
4497 }
4498 } else if (channel && desc->nr_channels == 3) {
4499 assert(desc->swizzle[0] == PIPE_SWIZZLE_X);
4500
4501 if (channel->size == 8) {
4502 if (channel->pure_integer)
4503 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8_INT;
4504 else
4505 v->fix_fetch[i] = SI_FIX_FETCH_RGB_8;
4506 } else if (channel->size == 16) {
4507 if (channel->pure_integer)
4508 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16_INT;
4509 else
4510 v->fix_fetch[i] = SI_FIX_FETCH_RGB_16;
4511 }
4512 }
4513
4514 v->rsrc_word3[i] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle[0])) |
4515 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
4516 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
4517 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
4518 S_008F0C_NUM_FORMAT(num_format) |
4519 S_008F0C_DATA_FORMAT(data_format);
4520 }
4521 return v;
4522 }
4523
4524 static void si_bind_vertex_elements(struct pipe_context *ctx, void *state)
4525 {
4526 struct si_context *sctx = (struct si_context *)ctx;
4527 struct si_vertex_elements *old = sctx->vertex_elements;
4528 struct si_vertex_elements *v = (struct si_vertex_elements*)state;
4529
4530 sctx->vertex_elements = v;
4531 sctx->vertex_buffers_dirty = true;
4532
4533 if (v &&
4534 (!old ||
4535 old->count != v->count ||
4536 old->uses_instance_divisors != v->uses_instance_divisors ||
4537 v->uses_instance_divisors || /* we don't check which divisors changed */
4538 memcmp(old->fix_fetch, v->fix_fetch, sizeof(v->fix_fetch[0]) * v->count)))
4539 sctx->do_update_shaders = true;
4540
4541 if (v && v->instance_divisor_is_fetched) {
4542 struct pipe_constant_buffer cb;
4543
4544 cb.buffer = NULL;
4545 cb.user_buffer = v->instance_divisors;
4546 cb.buffer_offset = 0;
4547 cb.buffer_size = sizeof(uint32_t) * v->count;
4548 si_set_rw_buffer(sctx, SI_VS_CONST_INSTANCE_DIVISORS, &cb);
4549 }
4550 }
4551
4552 static void si_delete_vertex_element(struct pipe_context *ctx, void *state)
4553 {
4554 struct si_context *sctx = (struct si_context *)ctx;
4555
4556 if (sctx->vertex_elements == state)
4557 sctx->vertex_elements = NULL;
4558 FREE(state);
4559 }
4560
4561 static void si_set_vertex_buffers(struct pipe_context *ctx,
4562 unsigned start_slot, unsigned count,
4563 const struct pipe_vertex_buffer *buffers)
4564 {
4565 struct si_context *sctx = (struct si_context *)ctx;
4566 struct pipe_vertex_buffer *dst = sctx->vertex_buffer + start_slot;
4567 int i;
4568
4569 assert(start_slot + count <= ARRAY_SIZE(sctx->vertex_buffer));
4570
4571 if (buffers) {
4572 for (i = 0; i < count; i++) {
4573 const struct pipe_vertex_buffer *src = buffers + i;
4574 struct pipe_vertex_buffer *dsti = dst + i;
4575 struct pipe_resource *buf = src->buffer.resource;
4576
4577 pipe_resource_reference(&dsti->buffer.resource, buf);
4578 dsti->buffer_offset = src->buffer_offset;
4579 dsti->stride = src->stride;
4580 si_context_add_resource_size(sctx, buf);
4581 if (buf)
4582 r600_resource(buf)->bind_history |= PIPE_BIND_VERTEX_BUFFER;
4583 }
4584 } else {
4585 for (i = 0; i < count; i++) {
4586 pipe_resource_reference(&dst[i].buffer.resource, NULL);
4587 }
4588 }
4589 sctx->vertex_buffers_dirty = true;
4590 }
4591
4592 /*
4593 * Misc
4594 */
4595
4596 static void si_set_tess_state(struct pipe_context *ctx,
4597 const float default_outer_level[4],
4598 const float default_inner_level[2])
4599 {
4600 struct si_context *sctx = (struct si_context *)ctx;
4601 struct pipe_constant_buffer cb;
4602 float array[8];
4603
4604 memcpy(array, default_outer_level, sizeof(float) * 4);
4605 memcpy(array+4, default_inner_level, sizeof(float) * 2);
4606
4607 cb.buffer = NULL;
4608 cb.user_buffer = NULL;
4609 cb.buffer_size = sizeof(array);
4610
4611 si_upload_const_buffer(sctx, (struct r600_resource**)&cb.buffer,
4612 (void*)array, sizeof(array),
4613 &cb.buffer_offset);
4614
4615 si_set_rw_buffer(sctx, SI_HS_CONST_DEFAULT_TESS_LEVELS, &cb);
4616 pipe_resource_reference(&cb.buffer, NULL);
4617 }
4618
4619 static void si_texture_barrier(struct pipe_context *ctx, unsigned flags)
4620 {
4621 struct si_context *sctx = (struct si_context *)ctx;
4622
4623 si_update_fb_dirtiness_after_rendering(sctx);
4624
4625 /* Multisample surfaces are flushed in si_decompress_textures. */
4626 if (sctx->framebuffer.uncompressed_cb_mask)
4627 si_make_CB_shader_coherent(sctx, sctx->framebuffer.nr_samples,
4628 sctx->framebuffer.CB_has_shader_readable_metadata);
4629 }
4630
4631 /* This only ensures coherency for shader image/buffer stores. */
4632 static void si_memory_barrier(struct pipe_context *ctx, unsigned flags)
4633 {
4634 struct si_context *sctx = (struct si_context *)ctx;
4635
4636 /* Subsequent commands must wait for all shader invocations to
4637 * complete. */
4638 sctx->flags |= SI_CONTEXT_PS_PARTIAL_FLUSH |
4639 SI_CONTEXT_CS_PARTIAL_FLUSH;
4640
4641 if (flags & PIPE_BARRIER_CONSTANT_BUFFER)
4642 sctx->flags |= SI_CONTEXT_INV_SMEM_L1 |
4643 SI_CONTEXT_INV_VMEM_L1;
4644
4645 if (flags & (PIPE_BARRIER_VERTEX_BUFFER |
4646 PIPE_BARRIER_SHADER_BUFFER |
4647 PIPE_BARRIER_TEXTURE |
4648 PIPE_BARRIER_IMAGE |
4649 PIPE_BARRIER_STREAMOUT_BUFFER |
4650 PIPE_BARRIER_GLOBAL_BUFFER)) {
4651 /* As far as I can tell, L1 contents are written back to L2
4652 * automatically at end of shader, but the contents of other
4653 * L1 caches might still be stale. */
4654 sctx->flags |= SI_CONTEXT_INV_VMEM_L1;
4655 }
4656
4657 if (flags & PIPE_BARRIER_INDEX_BUFFER) {
4658 /* Indices are read through TC L2 since VI.
4659 * L1 isn't used.
4660 */
4661 if (sctx->screen->info.chip_class <= CIK)
4662 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4663 }
4664
4665 /* MSAA color, any depth and any stencil are flushed in
4666 * si_decompress_textures when needed.
4667 */
4668 if (flags & PIPE_BARRIER_FRAMEBUFFER &&
4669 sctx->framebuffer.uncompressed_cb_mask) {
4670 sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_CB;
4671
4672 if (sctx->chip_class <= VI)
4673 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4674 }
4675
4676 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4677 if (sctx->screen->info.chip_class <= VI &&
4678 flags & PIPE_BARRIER_INDIRECT_BUFFER)
4679 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
4680 }
4681
4682 static void *si_create_blend_custom(struct si_context *sctx, unsigned mode)
4683 {
4684 struct pipe_blend_state blend;
4685
4686 memset(&blend, 0, sizeof(blend));
4687 blend.independent_blend_enable = true;
4688 blend.rt[0].colormask = 0xf;
4689 return si_create_blend_state_mode(&sctx->b, &blend, mode);
4690 }
4691
4692 static void si_init_config(struct si_context *sctx);
4693
4694 void si_init_state_functions(struct si_context *sctx)
4695 {
4696 sctx->atoms.s.framebuffer.emit = si_emit_framebuffer_state;
4697 sctx->atoms.s.msaa_sample_locs.emit = si_emit_msaa_sample_locs;
4698 sctx->atoms.s.db_render_state.emit = si_emit_db_render_state;
4699 sctx->atoms.s.dpbb_state.emit = si_emit_dpbb_state;
4700 sctx->atoms.s.msaa_config.emit = si_emit_msaa_config;
4701 sctx->atoms.s.sample_mask.emit = si_emit_sample_mask;
4702 sctx->atoms.s.cb_render_state.emit = si_emit_cb_render_state;
4703 sctx->atoms.s.blend_color.emit = si_emit_blend_color;
4704 sctx->atoms.s.clip_regs.emit = si_emit_clip_regs;
4705 sctx->atoms.s.clip_state.emit = si_emit_clip_state;
4706 sctx->atoms.s.stencil_ref.emit = si_emit_stencil_ref;
4707
4708 sctx->b.create_blend_state = si_create_blend_state;
4709 sctx->b.bind_blend_state = si_bind_blend_state;
4710 sctx->b.delete_blend_state = si_delete_blend_state;
4711 sctx->b.set_blend_color = si_set_blend_color;
4712
4713 sctx->b.create_rasterizer_state = si_create_rs_state;
4714 sctx->b.bind_rasterizer_state = si_bind_rs_state;
4715 sctx->b.delete_rasterizer_state = si_delete_rs_state;
4716
4717 sctx->b.create_depth_stencil_alpha_state = si_create_dsa_state;
4718 sctx->b.bind_depth_stencil_alpha_state = si_bind_dsa_state;
4719 sctx->b.delete_depth_stencil_alpha_state = si_delete_dsa_state;
4720
4721 sctx->custom_dsa_flush = si_create_db_flush_dsa(sctx);
4722 sctx->custom_blend_resolve = si_create_blend_custom(sctx, V_028808_CB_RESOLVE);
4723 sctx->custom_blend_fmask_decompress = si_create_blend_custom(sctx, V_028808_CB_FMASK_DECOMPRESS);
4724 sctx->custom_blend_eliminate_fastclear = si_create_blend_custom(sctx, V_028808_CB_ELIMINATE_FAST_CLEAR);
4725 sctx->custom_blend_dcc_decompress = si_create_blend_custom(sctx, V_028808_CB_DCC_DECOMPRESS);
4726
4727 sctx->b.set_clip_state = si_set_clip_state;
4728 sctx->b.set_stencil_ref = si_set_stencil_ref;
4729
4730 sctx->b.set_framebuffer_state = si_set_framebuffer_state;
4731
4732 sctx->b.create_sampler_state = si_create_sampler_state;
4733 sctx->b.delete_sampler_state = si_delete_sampler_state;
4734
4735 sctx->b.create_sampler_view = si_create_sampler_view;
4736 sctx->b.sampler_view_destroy = si_sampler_view_destroy;
4737
4738 sctx->b.set_sample_mask = si_set_sample_mask;
4739
4740 sctx->b.create_vertex_elements_state = si_create_vertex_elements;
4741 sctx->b.bind_vertex_elements_state = si_bind_vertex_elements;
4742 sctx->b.delete_vertex_elements_state = si_delete_vertex_element;
4743 sctx->b.set_vertex_buffers = si_set_vertex_buffers;
4744
4745 sctx->b.texture_barrier = si_texture_barrier;
4746 sctx->b.memory_barrier = si_memory_barrier;
4747 sctx->b.set_min_samples = si_set_min_samples;
4748 sctx->b.set_tess_state = si_set_tess_state;
4749
4750 sctx->b.set_active_query_state = si_set_active_query_state;
4751
4752 sctx->b.draw_vbo = si_draw_vbo;
4753
4754 si_init_config(sctx);
4755 }
4756
4757 void si_init_screen_state_functions(struct si_screen *sscreen)
4758 {
4759 sscreen->b.is_format_supported = si_is_format_supported;
4760 }
4761
4762 static void si_set_grbm_gfx_index(struct si_context *sctx,
4763 struct si_pm4_state *pm4, unsigned value)
4764 {
4765 unsigned reg = sctx->chip_class >= CIK ? R_030800_GRBM_GFX_INDEX :
4766 R_00802C_GRBM_GFX_INDEX;
4767 si_pm4_set_reg(pm4, reg, value);
4768 }
4769
4770 static void si_set_grbm_gfx_index_se(struct si_context *sctx,
4771 struct si_pm4_state *pm4, unsigned se)
4772 {
4773 assert(se == ~0 || se < sctx->screen->info.max_se);
4774 si_set_grbm_gfx_index(sctx, pm4,
4775 (se == ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4776 S_030800_SE_INDEX(se)) |
4777 S_030800_SH_BROADCAST_WRITES(1) |
4778 S_030800_INSTANCE_BROADCAST_WRITES(1));
4779 }
4780
4781 static void
4782 si_write_harvested_raster_configs(struct si_context *sctx,
4783 struct si_pm4_state *pm4,
4784 unsigned raster_config,
4785 unsigned raster_config_1)
4786 {
4787 unsigned num_se = MAX2(sctx->screen->info.max_se, 1);
4788 unsigned raster_config_se[4];
4789 unsigned se;
4790
4791 ac_get_harvested_configs(&sctx->screen->info,
4792 raster_config,
4793 &raster_config_1,
4794 raster_config_se);
4795
4796 for (se = 0; se < num_se; se++) {
4797 si_set_grbm_gfx_index_se(sctx, pm4, se);
4798 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se[se]);
4799 }
4800 si_set_grbm_gfx_index(sctx, pm4, ~0);
4801
4802 if (sctx->chip_class >= CIK) {
4803 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1);
4804 }
4805 }
4806
4807 static void si_set_raster_config(struct si_context *sctx, struct si_pm4_state *pm4)
4808 {
4809 struct si_screen *sscreen = sctx->screen;
4810 unsigned num_rb = MIN2(sscreen->info.num_render_backends, 16);
4811 unsigned rb_mask = sscreen->info.enabled_rb_mask;
4812 unsigned raster_config = sscreen->pa_sc_raster_config;
4813 unsigned raster_config_1 = sscreen->pa_sc_raster_config_1;
4814
4815 if (!rb_mask || util_bitcount(rb_mask) >= num_rb) {
4816 /* Always use the default config when all backends are enabled
4817 * (or when we failed to determine the enabled backends).
4818 */
4819 si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
4820 raster_config);
4821 if (sctx->chip_class >= CIK)
4822 si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
4823 raster_config_1);
4824 } else {
4825 si_write_harvested_raster_configs(sctx, pm4, raster_config, raster_config_1);
4826 }
4827 }
4828
4829 static void si_init_config(struct si_context *sctx)
4830 {
4831 struct si_screen *sscreen = sctx->screen;
4832 uint64_t border_color_va = sctx->border_color_buffer->gpu_address;
4833 bool has_clear_state = sscreen->has_clear_state;
4834 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
4835
4836 /* Only SI can disable CLEAR_STATE for now. */
4837 assert(has_clear_state || sscreen->info.chip_class == SI);
4838
4839 if (!pm4)
4840 return;
4841
4842 si_pm4_cmd_begin(pm4, PKT3_CONTEXT_CONTROL);
4843 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_LOAD_ENABLE(1));
4844 si_pm4_cmd_add(pm4, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4845 si_pm4_cmd_end(pm4, false);
4846
4847 if (has_clear_state) {
4848 si_pm4_cmd_begin(pm4, PKT3_CLEAR_STATE);
4849 si_pm4_cmd_add(pm4, 0);
4850 si_pm4_cmd_end(pm4, false);
4851 }
4852
4853 if (sctx->chip_class <= VI)
4854 si_set_raster_config(sctx, pm4);
4855
4856 si_pm4_set_reg(pm4, R_028A18_VGT_HOS_MAX_TESS_LEVEL, fui(64));
4857 if (!has_clear_state)
4858 si_pm4_set_reg(pm4, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, fui(0));
4859
4860 /* FIXME calculate these values somehow ??? */
4861 if (sctx->chip_class <= VI) {
4862 si_pm4_set_reg(pm4, R_028A54_VGT_GS_PER_ES, SI_GS_PER_ES);
4863 si_pm4_set_reg(pm4, R_028A58_VGT_ES_PER_GS, 0x40);
4864 }
4865
4866 if (!has_clear_state) {
4867 si_pm4_set_reg(pm4, R_028A5C_VGT_GS_PER_VS, 0x2);
4868 si_pm4_set_reg(pm4, R_028A8C_VGT_PRIMITIVEID_RESET, 0x0);
4869 si_pm4_set_reg(pm4, R_028B98_VGT_STRMOUT_BUFFER_CONFIG, 0x0);
4870 }
4871
4872 si_pm4_set_reg(pm4, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 1);
4873 if (!has_clear_state)
4874 si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0);
4875 if (sctx->chip_class < CIK)
4876 si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) |
4877 S_008A14_CLIP_VTX_REORDER_ENA(1));
4878
4879 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4880 * I don't know why. Deduced by trial and error.
4881 */
4882 if (sctx->chip_class <= CIK) {
4883 si_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
4884 si_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
4885 si_pm4_set_reg(pm4, R_028240_PA_SC_GENERIC_SCISSOR_TL, S_028240_WINDOW_OFFSET_DISABLE(1));
4886 si_pm4_set_reg(pm4, R_028244_PA_SC_GENERIC_SCISSOR_BR,
4887 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4888 si_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
4889 si_pm4_set_reg(pm4, R_028034_PA_SC_SCREEN_SCISSOR_BR,
4890 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4891 }
4892
4893 if (!has_clear_state) {
4894 si_pm4_set_reg(pm4, R_028230_PA_SC_EDGERULE,
4895 S_028230_ER_TRI(0xA) |
4896 S_028230_ER_POINT(0xA) |
4897 S_028230_ER_RECT(0xA) |
4898 /* Required by DX10_DIAMOND_TEST_ENA: */
4899 S_028230_ER_LINE_LR(0x1A) |
4900 S_028230_ER_LINE_RL(0x26) |
4901 S_028230_ER_LINE_TB(0xA) |
4902 S_028230_ER_LINE_BT(0xA));
4903 si_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
4904 si_pm4_set_reg(pm4, R_028AC0_DB_SRESULTS_COMPARE_STATE0, 0x0);
4905 si_pm4_set_reg(pm4, R_028AC4_DB_SRESULTS_COMPARE_STATE1, 0x0);
4906 si_pm4_set_reg(pm4, R_028AC8_DB_PRELOAD_CONTROL, 0x0);
4907 si_pm4_set_reg(pm4, R_02800C_DB_RENDER_OVERRIDE, 0);
4908 }
4909
4910 if (sctx->chip_class >= GFX9) {
4911 si_pm4_set_reg(pm4, R_030920_VGT_MAX_VTX_INDX, ~0);
4912 si_pm4_set_reg(pm4, R_030924_VGT_MIN_VTX_INDX, 0);
4913 si_pm4_set_reg(pm4, R_030928_VGT_INDX_OFFSET, 0);
4914 } else {
4915 /* These registers, when written, also overwrite the CLEAR_STATE
4916 * context, so we can't rely on CLEAR_STATE setting them.
4917 * It would be an issue if there was another UMD changing them.
4918 */
4919 si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0);
4920 si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0);
4921 si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, 0);
4922 }
4923
4924 if (sctx->chip_class >= CIK) {
4925 if (sctx->chip_class >= GFX9) {
4926 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4927 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4928 } else {
4929 si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
4930 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4931 si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
4932 S_00B41C_WAVE_LIMIT(0x3F));
4933 si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
4934 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
4935
4936 /* If this is 0, Bonaire can hang even if GS isn't being used.
4937 * Other chips are unaffected. These are suboptimal values,
4938 * but we don't use on-chip GS.
4939 */
4940 si_pm4_set_reg(pm4, R_028A44_VGT_GS_ONCHIP_CNTL,
4941 S_028A44_ES_VERTS_PER_SUBGRP(64) |
4942 S_028A44_GS_PRIMS_PER_SUBGRP(4));
4943 }
4944 si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
4945 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
4946
4947 /* Compute LATE_ALLOC_VS.LIMIT. */
4948 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
4949 unsigned late_alloc_limit; /* The limit is per SH. */
4950
4951 if (sctx->family == CHIP_KABINI) {
4952 late_alloc_limit = 0; /* Potential hang on Kabini. */
4953 } else if (num_cu_per_sh <= 4) {
4954 /* Too few available compute units per SH. Disallowing
4955 * VS to run on one CU could hurt us more than late VS
4956 * allocation would help.
4957 *
4958 * 2 is the highest safe number that allows us to keep
4959 * all CUs enabled.
4960 */
4961 late_alloc_limit = 2;
4962 } else {
4963 /* This is a good initial value, allowing 1 late_alloc
4964 * wave per SIMD on num_cu - 2.
4965 */
4966 late_alloc_limit = (num_cu_per_sh - 2) * 4;
4967
4968 /* The limit is 0-based, so 0 means 1. */
4969 assert(late_alloc_limit > 0 && late_alloc_limit <= 64);
4970 late_alloc_limit -= 1;
4971 }
4972
4973 /* VS can't execute on one CU if the limit is > 2. */
4974 si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
4975 S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
4976 S_00B118_WAVE_LIMIT(0x3F));
4977 si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
4978 S_00B11C_LIMIT(late_alloc_limit));
4979 si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
4980 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
4981 }
4982
4983 if (sctx->chip_class >= VI) {
4984 unsigned vgt_tess_distribution;
4985
4986 vgt_tess_distribution =
4987 S_028B50_ACCUM_ISOLINE(32) |
4988 S_028B50_ACCUM_TRI(11) |
4989 S_028B50_ACCUM_QUAD(11) |
4990 S_028B50_DONUT_SPLIT(16);
4991
4992 /* Testing with Unigine Heaven extreme tesselation yielded best results
4993 * with TRAP_SPLIT = 3.
4994 */
4995 if (sctx->family == CHIP_FIJI ||
4996 sctx->family >= CHIP_POLARIS10)
4997 vgt_tess_distribution |= S_028B50_TRAP_SPLIT(3);
4998
4999 si_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION, vgt_tess_distribution);
5000 } else if (!has_clear_state) {
5001 si_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
5002 si_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
5003 }
5004
5005 si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, border_color_va >> 8);
5006 if (sctx->chip_class >= CIK) {
5007 si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI,
5008 S_028084_ADDRESS(border_color_va >> 40));
5009 }
5010 si_pm4_add_bo(pm4, sctx->border_color_buffer, RADEON_USAGE_READ,
5011 RADEON_PRIO_BORDER_COLORS);
5012
5013 if (sctx->chip_class >= GFX9) {
5014 unsigned num_se = sscreen->info.max_se;
5015 unsigned pc_lines = 0;
5016
5017 switch (sctx->family) {
5018 case CHIP_VEGA10:
5019 case CHIP_VEGA12:
5020 case CHIP_VEGA20:
5021 pc_lines = 4096;
5022 break;
5023 case CHIP_RAVEN:
5024 pc_lines = 1024;
5025 break;
5026 default:
5027 assert(0);
5028 }
5029
5030 si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
5031 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
5032 S_028C48_MAX_PRIM_PER_BATCH(1023));
5033 si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
5034 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5035 si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);
5036 }
5037
5038 si_pm4_upload_indirect_buffer(sctx, pm4);
5039 sctx->init_config = pm4;
5040 }