2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include "radeon/r600_cs.h"
28 #include "radeon/r600_query.h"
30 #include "util/u_dual_blend.h"
31 #include "util/u_format.h"
32 #include "util/u_format_s3tc.h"
33 #include "util/u_memory.h"
34 #include "util/u_resource.h"
35 #include "util/u_upload_mgr.h"
37 /* Initialize an external atom (owned by ../radeon). */
39 si_init_external_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
40 struct r600_atom
**list_elem
)
42 atom
->id
= list_elem
- sctx
->atoms
.array
;
46 /* Initialize an atom owned by radeonsi. */
47 void si_init_atom(struct si_context
*sctx
, struct r600_atom
*atom
,
48 struct r600_atom
**list_elem
,
49 void (*emit_func
)(struct si_context
*ctx
, struct r600_atom
*state
))
51 atom
->emit
= (void*)emit_func
;
52 atom
->id
= list_elem
- sctx
->atoms
.array
;
56 static unsigned si_map_swizzle(unsigned swizzle
)
60 return V_008F0C_SQ_SEL_Y
;
62 return V_008F0C_SQ_SEL_Z
;
64 return V_008F0C_SQ_SEL_W
;
66 return V_008F0C_SQ_SEL_0
;
68 return V_008F0C_SQ_SEL_1
;
69 default: /* PIPE_SWIZZLE_X */
70 return V_008F0C_SQ_SEL_X
;
74 /* 12.4 fixed-point */
75 static unsigned si_pack_float_12p4(float x
)
78 x
>= 4096 ? 0xffff : x
* 16;
82 * Inferred framebuffer and blender state.
84 * CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
85 * if there is not enough PS outputs.
87 static void si_emit_cb_render_state(struct si_context
*sctx
, struct r600_atom
*atom
)
89 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
90 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
91 /* CB_COLORn_INFO.FORMAT=INVALID should disable unbound colorbuffers,
92 * but you never know. */
93 uint32_t cb_target_mask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
97 cb_target_mask
&= blend
->cb_target_mask
;
99 /* Avoid a hang that happens when dual source blending is enabled
100 * but there is not enough color outputs. This is undefined behavior,
101 * so disable color writes completely.
103 * Reproducible with Unigine Heaven 4.0 and drirc missing.
105 if (blend
&& blend
->dual_src_blend
&&
106 sctx
->ps_shader
.cso
&&
107 (sctx
->ps_shader
.cso
->info
.colors_written
& 0x3) != 0x3)
110 radeon_set_context_reg(cs
, R_028238_CB_TARGET_MASK
, cb_target_mask
);
112 /* GFX9: Flush DFSM when CB_TARGET_MASK changes.
113 * I think we don't have to do anything between IBs.
115 if (sctx
->screen
->dfsm_allowed
&&
116 sctx
->last_cb_target_mask
!= cb_target_mask
) {
117 sctx
->last_cb_target_mask
= cb_target_mask
;
119 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
120 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
123 /* RB+ register settings. */
124 if (sctx
->screen
->b
.rbplus_allowed
) {
125 unsigned spi_shader_col_format
=
126 sctx
->ps_shader
.cso
?
127 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
128 unsigned sx_ps_downconvert
= 0;
129 unsigned sx_blend_opt_epsilon
= 0;
130 unsigned sx_blend_opt_control
= 0;
132 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
133 struct r600_surface
*surf
=
134 (struct r600_surface
*)sctx
->framebuffer
.state
.cbufs
[i
];
135 unsigned format
, swap
, spi_format
, colormask
;
136 bool has_alpha
, has_rgb
;
141 format
= G_028C70_FORMAT(surf
->cb_color_info
);
142 swap
= G_028C70_COMP_SWAP(surf
->cb_color_info
);
143 spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
144 colormask
= (cb_target_mask
>> (i
* 4)) & 0xf;
146 /* Set if RGB and A are present. */
147 has_alpha
= !G_028C74_FORCE_DST_ALPHA_1(surf
->cb_color_attrib
);
149 if (format
== V_028C70_COLOR_8
||
150 format
== V_028C70_COLOR_16
||
151 format
== V_028C70_COLOR_32
)
152 has_rgb
= !has_alpha
;
156 /* Check the colormask and export format. */
157 if (!(colormask
& (PIPE_MASK_RGBA
& ~PIPE_MASK_A
)))
159 if (!(colormask
& PIPE_MASK_A
))
162 if (spi_format
== V_028714_SPI_SHADER_ZERO
) {
167 /* Disable value checking for disabled channels. */
169 sx_blend_opt_control
|= S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i
* 4);
171 sx_blend_opt_control
|= S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i
* 4);
173 /* Enable down-conversion for 32bpp and smaller formats. */
175 case V_028C70_COLOR_8
:
176 case V_028C70_COLOR_8_8
:
177 case V_028C70_COLOR_8_8_8_8
:
178 /* For 1 and 2-channel formats, use the superset thereof. */
179 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
||
180 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
181 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
182 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_8_8_8_8
<< (i
* 4);
183 sx_blend_opt_epsilon
|= V_028758_8BIT_FORMAT
<< (i
* 4);
187 case V_028C70_COLOR_5_6_5
:
188 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
189 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_5_6_5
<< (i
* 4);
190 sx_blend_opt_epsilon
|= V_028758_6BIT_FORMAT
<< (i
* 4);
194 case V_028C70_COLOR_1_5_5_5
:
195 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
196 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_1_5_5_5
<< (i
* 4);
197 sx_blend_opt_epsilon
|= V_028758_5BIT_FORMAT
<< (i
* 4);
201 case V_028C70_COLOR_4_4_4_4
:
202 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
203 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_4_4_4_4
<< (i
* 4);
204 sx_blend_opt_epsilon
|= V_028758_4BIT_FORMAT
<< (i
* 4);
208 case V_028C70_COLOR_32
:
209 if (swap
== V_028C70_SWAP_STD
&&
210 spi_format
== V_028714_SPI_SHADER_32_R
)
211 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_R
<< (i
* 4);
212 else if (swap
== V_028C70_SWAP_ALT_REV
&&
213 spi_format
== V_028714_SPI_SHADER_32_AR
)
214 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_32_A
<< (i
* 4);
217 case V_028C70_COLOR_16
:
218 case V_028C70_COLOR_16_16
:
219 /* For 1-channel formats, use the superset thereof. */
220 if (spi_format
== V_028714_SPI_SHADER_UNORM16_ABGR
||
221 spi_format
== V_028714_SPI_SHADER_SNORM16_ABGR
||
222 spi_format
== V_028714_SPI_SHADER_UINT16_ABGR
||
223 spi_format
== V_028714_SPI_SHADER_SINT16_ABGR
) {
224 if (swap
== V_028C70_SWAP_STD
||
225 swap
== V_028C70_SWAP_STD_REV
)
226 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_GR
<< (i
* 4);
228 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_16_16_AR
<< (i
* 4);
232 case V_028C70_COLOR_10_11_11
:
233 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
234 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_10_11_11
<< (i
* 4);
235 sx_blend_opt_epsilon
|= V_028758_11BIT_FORMAT
<< (i
* 4);
239 case V_028C70_COLOR_2_10_10_10
:
240 if (spi_format
== V_028714_SPI_SHADER_FP16_ABGR
) {
241 sx_ps_downconvert
|= V_028754_SX_RT_EXPORT_2_10_10_10
<< (i
* 4);
242 sx_blend_opt_epsilon
|= V_028758_10BIT_FORMAT
<< (i
* 4);
248 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
249 radeon_emit(cs
, sx_ps_downconvert
); /* R_028754_SX_PS_DOWNCONVERT */
250 radeon_emit(cs
, sx_blend_opt_epsilon
); /* R_028758_SX_BLEND_OPT_EPSILON */
251 radeon_emit(cs
, sx_blend_opt_control
); /* R_02875C_SX_BLEND_OPT_CONTROL */
252 } else if (sctx
->screen
->b
.has_rbplus
) {
253 radeon_set_context_reg_seq(cs
, R_028754_SX_PS_DOWNCONVERT
, 3);
254 radeon_emit(cs
, 0); /* R_028754_SX_PS_DOWNCONVERT */
255 radeon_emit(cs
, 0); /* R_028758_SX_BLEND_OPT_EPSILON */
256 radeon_emit(cs
, 0); /* R_02875C_SX_BLEND_OPT_CONTROL */
264 static uint32_t si_translate_blend_function(int blend_func
)
266 switch (blend_func
) {
268 return V_028780_COMB_DST_PLUS_SRC
;
269 case PIPE_BLEND_SUBTRACT
:
270 return V_028780_COMB_SRC_MINUS_DST
;
271 case PIPE_BLEND_REVERSE_SUBTRACT
:
272 return V_028780_COMB_DST_MINUS_SRC
;
274 return V_028780_COMB_MIN_DST_SRC
;
276 return V_028780_COMB_MAX_DST_SRC
;
278 R600_ERR("Unknown blend function %d\n", blend_func
);
285 static uint32_t si_translate_blend_factor(int blend_fact
)
287 switch (blend_fact
) {
288 case PIPE_BLENDFACTOR_ONE
:
289 return V_028780_BLEND_ONE
;
290 case PIPE_BLENDFACTOR_SRC_COLOR
:
291 return V_028780_BLEND_SRC_COLOR
;
292 case PIPE_BLENDFACTOR_SRC_ALPHA
:
293 return V_028780_BLEND_SRC_ALPHA
;
294 case PIPE_BLENDFACTOR_DST_ALPHA
:
295 return V_028780_BLEND_DST_ALPHA
;
296 case PIPE_BLENDFACTOR_DST_COLOR
:
297 return V_028780_BLEND_DST_COLOR
;
298 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
299 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
300 case PIPE_BLENDFACTOR_CONST_COLOR
:
301 return V_028780_BLEND_CONSTANT_COLOR
;
302 case PIPE_BLENDFACTOR_CONST_ALPHA
:
303 return V_028780_BLEND_CONSTANT_ALPHA
;
304 case PIPE_BLENDFACTOR_ZERO
:
305 return V_028780_BLEND_ZERO
;
306 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
307 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
308 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
309 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
310 case PIPE_BLENDFACTOR_INV_DST_ALPHA
:
311 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
312 case PIPE_BLENDFACTOR_INV_DST_COLOR
:
313 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
314 case PIPE_BLENDFACTOR_INV_CONST_COLOR
:
315 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
316 case PIPE_BLENDFACTOR_INV_CONST_ALPHA
:
317 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
318 case PIPE_BLENDFACTOR_SRC1_COLOR
:
319 return V_028780_BLEND_SRC1_COLOR
;
320 case PIPE_BLENDFACTOR_SRC1_ALPHA
:
321 return V_028780_BLEND_SRC1_ALPHA
;
322 case PIPE_BLENDFACTOR_INV_SRC1_COLOR
:
323 return V_028780_BLEND_INV_SRC1_COLOR
;
324 case PIPE_BLENDFACTOR_INV_SRC1_ALPHA
:
325 return V_028780_BLEND_INV_SRC1_ALPHA
;
327 R600_ERR("Bad blend factor %d not supported!\n", blend_fact
);
334 static uint32_t si_translate_blend_opt_function(int blend_func
)
336 switch (blend_func
) {
338 return V_028760_OPT_COMB_ADD
;
339 case PIPE_BLEND_SUBTRACT
:
340 return V_028760_OPT_COMB_SUBTRACT
;
341 case PIPE_BLEND_REVERSE_SUBTRACT
:
342 return V_028760_OPT_COMB_REVSUBTRACT
;
344 return V_028760_OPT_COMB_MIN
;
346 return V_028760_OPT_COMB_MAX
;
348 return V_028760_OPT_COMB_BLEND_DISABLED
;
352 static uint32_t si_translate_blend_opt_factor(int blend_fact
, bool is_alpha
)
354 switch (blend_fact
) {
355 case PIPE_BLENDFACTOR_ZERO
:
356 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
357 case PIPE_BLENDFACTOR_ONE
:
358 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
359 case PIPE_BLENDFACTOR_SRC_COLOR
:
360 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
361 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
362 case PIPE_BLENDFACTOR_INV_SRC_COLOR
:
363 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
364 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
365 case PIPE_BLENDFACTOR_SRC_ALPHA
:
366 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
367 case PIPE_BLENDFACTOR_INV_SRC_ALPHA
:
368 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
369 case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
:
370 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
371 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
373 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
377 static void si_blend_check_commutativity(struct si_screen
*sscreen
,
378 struct si_state_blend
*blend
,
379 enum pipe_blend_func func
,
380 enum pipe_blendfactor src
,
381 enum pipe_blendfactor dst
,
384 /* Src factor is allowed when it does not depend on Dst */
385 static const uint32_t src_allowed
=
386 (1u << PIPE_BLENDFACTOR_ONE
) |
387 (1u << PIPE_BLENDFACTOR_SRC_COLOR
) |
388 (1u << PIPE_BLENDFACTOR_SRC_ALPHA
) |
389 (1u << PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
) |
390 (1u << PIPE_BLENDFACTOR_CONST_COLOR
) |
391 (1u << PIPE_BLENDFACTOR_CONST_ALPHA
) |
392 (1u << PIPE_BLENDFACTOR_SRC1_COLOR
) |
393 (1u << PIPE_BLENDFACTOR_SRC1_ALPHA
) |
394 (1u << PIPE_BLENDFACTOR_ZERO
) |
395 (1u << PIPE_BLENDFACTOR_INV_SRC_COLOR
) |
396 (1u << PIPE_BLENDFACTOR_INV_SRC_ALPHA
) |
397 (1u << PIPE_BLENDFACTOR_INV_CONST_COLOR
) |
398 (1u << PIPE_BLENDFACTOR_INV_CONST_ALPHA
) |
399 (1u << PIPE_BLENDFACTOR_INV_SRC1_COLOR
) |
400 (1u << PIPE_BLENDFACTOR_INV_SRC1_ALPHA
);
402 if (dst
== PIPE_BLENDFACTOR_ONE
&&
403 (src_allowed
& (1u << src
))) {
404 /* Addition is commutative, but floating point addition isn't
405 * associative: subtle changes can be introduced via different
408 * Out-of-order is also non-deterministic, which means that
409 * this breaks OpenGL invariance requirements. So only enable
410 * out-of-order additive blending if explicitly allowed by a
413 if (func
== PIPE_BLEND_MAX
|| func
== PIPE_BLEND_MIN
||
414 (func
== PIPE_BLEND_ADD
&& sscreen
->commutative_blend_add
))
415 blend
->commutative_4bit
|= chanmask
;
420 * Get rid of DST in the blend factors by commuting the operands:
421 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
423 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
424 unsigned *dst_factor
, unsigned expected_dst
,
425 unsigned replacement_src
)
427 if (*src_factor
== expected_dst
&&
428 *dst_factor
== PIPE_BLENDFACTOR_ZERO
) {
429 *src_factor
= PIPE_BLENDFACTOR_ZERO
;
430 *dst_factor
= replacement_src
;
432 /* Commuting the operands requires reversing subtractions. */
433 if (*func
== PIPE_BLEND_SUBTRACT
)
434 *func
= PIPE_BLEND_REVERSE_SUBTRACT
;
435 else if (*func
== PIPE_BLEND_REVERSE_SUBTRACT
)
436 *func
= PIPE_BLEND_SUBTRACT
;
440 static bool si_blend_factor_uses_dst(unsigned factor
)
442 return factor
== PIPE_BLENDFACTOR_DST_COLOR
||
443 factor
== PIPE_BLENDFACTOR_DST_ALPHA
||
444 factor
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
445 factor
== PIPE_BLENDFACTOR_INV_DST_ALPHA
||
446 factor
== PIPE_BLENDFACTOR_INV_DST_COLOR
;
449 static void *si_create_blend_state_mode(struct pipe_context
*ctx
,
450 const struct pipe_blend_state
*state
,
453 struct si_context
*sctx
= (struct si_context
*)ctx
;
454 struct si_state_blend
*blend
= CALLOC_STRUCT(si_state_blend
);
455 struct si_pm4_state
*pm4
= &blend
->pm4
;
456 uint32_t sx_mrt_blend_opt
[8] = {0};
457 uint32_t color_control
= 0;
462 blend
->alpha_to_coverage
= state
->alpha_to_coverage
;
463 blend
->alpha_to_one
= state
->alpha_to_one
;
464 blend
->dual_src_blend
= util_blend_state_is_dual(state
, 0);
465 blend
->logicop_enable
= state
->logicop_enable
;
467 if (state
->logicop_enable
) {
468 color_control
|= S_028808_ROP3(state
->logicop_func
| (state
->logicop_func
<< 4));
470 color_control
|= S_028808_ROP3(0xcc);
473 si_pm4_set_reg(pm4
, R_028B70_DB_ALPHA_TO_MASK
,
474 S_028B70_ALPHA_TO_MASK_ENABLE(state
->alpha_to_coverage
) |
475 S_028B70_ALPHA_TO_MASK_OFFSET0(2) |
476 S_028B70_ALPHA_TO_MASK_OFFSET1(2) |
477 S_028B70_ALPHA_TO_MASK_OFFSET2(2) |
478 S_028B70_ALPHA_TO_MASK_OFFSET3(2));
480 if (state
->alpha_to_coverage
)
481 blend
->need_src_alpha_4bit
|= 0xf;
483 blend
->cb_target_mask
= 0;
484 blend
->cb_target_enabled_4bit
= 0;
486 for (int i
= 0; i
< 8; i
++) {
487 /* state->rt entries > 0 only written if independent blending */
488 const int j
= state
->independent_blend_enable
? i
: 0;
490 unsigned eqRGB
= state
->rt
[j
].rgb_func
;
491 unsigned srcRGB
= state
->rt
[j
].rgb_src_factor
;
492 unsigned dstRGB
= state
->rt
[j
].rgb_dst_factor
;
493 unsigned eqA
= state
->rt
[j
].alpha_func
;
494 unsigned srcA
= state
->rt
[j
].alpha_src_factor
;
495 unsigned dstA
= state
->rt
[j
].alpha_dst_factor
;
497 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
498 unsigned blend_cntl
= 0;
500 sx_mrt_blend_opt
[i
] =
501 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) |
502 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
504 /* Only set dual source blending for MRT0 to avoid a hang. */
505 if (i
>= 1 && blend
->dual_src_blend
) {
506 /* Vulkan does this for dual source blending. */
508 blend_cntl
|= S_028780_ENABLE(1);
510 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
514 /* Only addition and subtraction equations are supported with
515 * dual source blending.
517 if (blend
->dual_src_blend
&&
518 (eqRGB
== PIPE_BLEND_MIN
|| eqRGB
== PIPE_BLEND_MAX
||
519 eqA
== PIPE_BLEND_MIN
|| eqA
== PIPE_BLEND_MAX
)) {
520 assert(!"Unsupported equation for dual source blending");
521 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
525 /* cb_render_state will disable unused ones */
526 blend
->cb_target_mask
|= (unsigned)state
->rt
[j
].colormask
<< (4 * i
);
527 if (state
->rt
[j
].colormask
)
528 blend
->cb_target_enabled_4bit
|= 0xf << (4 * i
);
530 if (!state
->rt
[j
].colormask
|| !state
->rt
[j
].blend_enable
) {
531 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
535 si_blend_check_commutativity(sctx
->screen
, blend
,
536 eqRGB
, srcRGB
, dstRGB
, 0x7 << (4 * i
));
537 si_blend_check_commutativity(sctx
->screen
, blend
,
538 eqA
, srcA
, dstA
, 0x8 << (4 * i
));
540 /* Blending optimizations for RB+.
541 * These transformations don't change the behavior.
543 * First, get rid of DST in the blend factors:
544 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
546 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
547 PIPE_BLENDFACTOR_DST_COLOR
,
548 PIPE_BLENDFACTOR_SRC_COLOR
);
549 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
550 PIPE_BLENDFACTOR_DST_COLOR
,
551 PIPE_BLENDFACTOR_SRC_COLOR
);
552 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
553 PIPE_BLENDFACTOR_DST_ALPHA
,
554 PIPE_BLENDFACTOR_SRC_ALPHA
);
556 /* Look up the ideal settings from tables. */
557 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
558 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
559 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
560 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
562 /* Handle interdependencies. */
563 if (si_blend_factor_uses_dst(srcRGB
))
564 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
565 if (si_blend_factor_uses_dst(srcA
))
566 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
568 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
&&
569 (dstRGB
== PIPE_BLENDFACTOR_ZERO
||
570 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
571 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
))
572 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
574 /* Set the final value. */
575 sx_mrt_blend_opt
[i
] =
576 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
577 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
578 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
579 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
580 S_028760_ALPHA_DST_OPT(dstA_opt
) |
581 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
583 /* Set blend state. */
584 blend_cntl
|= S_028780_ENABLE(1);
585 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
586 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
587 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
589 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
590 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
591 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
592 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
593 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
595 si_pm4_set_reg(pm4
, R_028780_CB_BLEND0_CONTROL
+ i
* 4, blend_cntl
);
597 blend
->blend_enable_4bit
|= 0xfu
<< (i
* 4);
599 /* This is only important for formats without alpha. */
600 if (srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
601 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA
||
602 srcRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
603 dstRGB
== PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE
||
604 srcRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
||
605 dstRGB
== PIPE_BLENDFACTOR_INV_SRC_ALPHA
)
606 blend
->need_src_alpha_4bit
|= 0xfu
<< (i
* 4);
609 if (blend
->cb_target_mask
) {
610 color_control
|= S_028808_MODE(mode
);
612 color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
615 if (sctx
->screen
->b
.has_rbplus
) {
616 /* Disable RB+ blend optimizations for dual source blending.
619 if (blend
->dual_src_blend
) {
620 for (int i
= 0; i
< 8; i
++) {
621 sx_mrt_blend_opt
[i
] =
622 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
623 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
627 for (int i
= 0; i
< 8; i
++)
628 si_pm4_set_reg(pm4
, R_028760_SX_MRT0_BLEND_OPT
+ i
* 4,
629 sx_mrt_blend_opt
[i
]);
631 /* RB+ doesn't work with dual source blending, logic op, and RESOLVE. */
632 if (blend
->dual_src_blend
|| state
->logicop_enable
||
633 mode
== V_028808_CB_RESOLVE
)
634 color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
637 si_pm4_set_reg(pm4
, R_028808_CB_COLOR_CONTROL
, color_control
);
641 static void *si_create_blend_state(struct pipe_context
*ctx
,
642 const struct pipe_blend_state
*state
)
644 return si_create_blend_state_mode(ctx
, state
, V_028808_CB_NORMAL
);
647 static void si_bind_blend_state(struct pipe_context
*ctx
, void *state
)
649 struct si_context
*sctx
= (struct si_context
*)ctx
;
650 struct si_state_blend
*old_blend
= sctx
->queued
.named
.blend
;
651 struct si_state_blend
*blend
= (struct si_state_blend
*)state
;
657 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
658 old_blend
->dual_src_blend
!= blend
->dual_src_blend
)
659 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
661 si_pm4_bind_state(sctx
, blend
, state
);
664 old_blend
->cb_target_mask
!= blend
->cb_target_mask
||
665 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
666 old_blend
->alpha_to_one
!= blend
->alpha_to_one
||
667 old_blend
->dual_src_blend
!= blend
->dual_src_blend
||
668 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
669 old_blend
->need_src_alpha_4bit
!= blend
->need_src_alpha_4bit
)
670 sctx
->do_update_shaders
= true;
672 if (sctx
->screen
->dpbb_allowed
&&
674 old_blend
->alpha_to_coverage
!= blend
->alpha_to_coverage
||
675 old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
676 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
))
677 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
679 if (sctx
->screen
->has_out_of_order_rast
&&
681 (old_blend
->blend_enable_4bit
!= blend
->blend_enable_4bit
||
682 old_blend
->cb_target_enabled_4bit
!= blend
->cb_target_enabled_4bit
||
683 old_blend
->commutative_4bit
!= blend
->commutative_4bit
||
684 old_blend
->logicop_enable
!= blend
->logicop_enable
)))
685 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
688 static void si_delete_blend_state(struct pipe_context
*ctx
, void *state
)
690 struct si_context
*sctx
= (struct si_context
*)ctx
;
691 si_pm4_delete_state(sctx
, blend
, (struct si_state_blend
*)state
);
694 static void si_set_blend_color(struct pipe_context
*ctx
,
695 const struct pipe_blend_color
*state
)
697 struct si_context
*sctx
= (struct si_context
*)ctx
;
698 static const struct pipe_blend_color zeros
;
700 sctx
->blend_color
.state
= *state
;
701 sctx
->blend_color
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
702 si_mark_atom_dirty(sctx
, &sctx
->blend_color
.atom
);
705 static void si_emit_blend_color(struct si_context
*sctx
, struct r600_atom
*atom
)
707 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
709 radeon_set_context_reg_seq(cs
, R_028414_CB_BLEND_RED
, 4);
710 radeon_emit_array(cs
, (uint32_t*)sctx
->blend_color
.state
.color
, 4);
717 static void si_set_clip_state(struct pipe_context
*ctx
,
718 const struct pipe_clip_state
*state
)
720 struct si_context
*sctx
= (struct si_context
*)ctx
;
721 struct pipe_constant_buffer cb
;
722 static const struct pipe_clip_state zeros
;
724 if (memcmp(&sctx
->clip_state
.state
, state
, sizeof(*state
)) == 0)
727 sctx
->clip_state
.state
= *state
;
728 sctx
->clip_state
.any_nonzeros
= memcmp(state
, &zeros
, sizeof(*state
)) != 0;
729 si_mark_atom_dirty(sctx
, &sctx
->clip_state
.atom
);
732 cb
.user_buffer
= state
->ucp
;
733 cb
.buffer_offset
= 0;
734 cb
.buffer_size
= 4*4*8;
735 si_set_rw_buffer(sctx
, SI_VS_CONST_CLIP_PLANES
, &cb
);
736 pipe_resource_reference(&cb
.buffer
, NULL
);
739 static void si_emit_clip_state(struct si_context
*sctx
, struct r600_atom
*atom
)
741 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
743 radeon_set_context_reg_seq(cs
, R_0285BC_PA_CL_UCP_0_X
, 6*4);
744 radeon_emit_array(cs
, (uint32_t*)sctx
->clip_state
.state
.ucp
, 6*4);
747 static void si_emit_clip_regs(struct si_context
*sctx
, struct r600_atom
*atom
)
749 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
750 struct si_shader
*vs
= si_get_vs_state(sctx
);
751 struct si_shader_selector
*vs_sel
= vs
->selector
;
752 struct tgsi_shader_info
*info
= &vs_sel
->info
;
753 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
754 unsigned window_space
=
755 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
756 unsigned clipdist_mask
= vs_sel
->clipdist_mask
;
757 unsigned ucp_mask
= clipdist_mask
? 0 : rs
->clip_plane_enable
& SIX_BITS
;
758 unsigned culldist_mask
= vs_sel
->culldist_mask
;
761 if (vs
->key
.opt
.clip_disable
) {
762 assert(!info
->culldist_writemask
);
766 total_mask
= clipdist_mask
| culldist_mask
;
768 /* Clip distances on points have no effect, so need to be implemented
769 * as cull distances. This applies for the clipvertex case as well.
771 * Setting this for primitives other than points should have no adverse
774 clipdist_mask
&= rs
->clip_plane_enable
;
775 culldist_mask
|= clipdist_mask
;
777 radeon_set_context_reg(cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
778 vs_sel
->pa_cl_vs_out_cntl
|
779 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0F) != 0) |
780 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xF0) != 0) |
781 clipdist_mask
| (culldist_mask
<< 8));
782 radeon_set_context_reg(cs
, R_028810_PA_CL_CLIP_CNTL
,
783 rs
->pa_cl_clip_cntl
|
785 S_028810_CLIP_DISABLE(window_space
));
789 * inferred state between framebuffer and rasterizer
791 static void si_update_poly_offset_state(struct si_context
*sctx
)
793 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
795 if (!rs
|| !rs
->uses_poly_offset
|| !sctx
->framebuffer
.state
.zsbuf
) {
796 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
800 /* Use the user format, not db_render_format, so that the polygon
801 * offset behaves as expected by applications.
803 switch (sctx
->framebuffer
.state
.zsbuf
->texture
->format
) {
804 case PIPE_FORMAT_Z16_UNORM
:
805 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[0]);
807 default: /* 24-bit */
808 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[1]);
810 case PIPE_FORMAT_Z32_FLOAT
:
811 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
812 si_pm4_bind_state(sctx
, poly_offset
, &rs
->pm4_poly_offset
[2]);
821 static uint32_t si_translate_fill(uint32_t func
)
824 case PIPE_POLYGON_MODE_FILL
:
825 return V_028814_X_DRAW_TRIANGLES
;
826 case PIPE_POLYGON_MODE_LINE
:
827 return V_028814_X_DRAW_LINES
;
828 case PIPE_POLYGON_MODE_POINT
:
829 return V_028814_X_DRAW_POINTS
;
832 return V_028814_X_DRAW_POINTS
;
836 static void *si_create_rs_state(struct pipe_context
*ctx
,
837 const struct pipe_rasterizer_state
*state
)
839 struct si_screen
*sscreen
= ((struct si_context
*)ctx
)->screen
;
840 struct si_state_rasterizer
*rs
= CALLOC_STRUCT(si_state_rasterizer
);
841 struct si_pm4_state
*pm4
= &rs
->pm4
;
843 float psize_min
, psize_max
;
849 rs
->scissor_enable
= state
->scissor
;
850 rs
->clip_halfz
= state
->clip_halfz
;
851 rs
->two_side
= state
->light_twoside
;
852 rs
->multisample_enable
= state
->multisample
;
853 rs
->force_persample_interp
= state
->force_persample_interp
;
854 rs
->clip_plane_enable
= state
->clip_plane_enable
;
855 rs
->line_stipple_enable
= state
->line_stipple_enable
;
856 rs
->poly_stipple_enable
= state
->poly_stipple_enable
;
857 rs
->line_smooth
= state
->line_smooth
;
858 rs
->line_width
= state
->line_width
;
859 rs
->poly_smooth
= state
->poly_smooth
;
860 rs
->uses_poly_offset
= state
->offset_point
|| state
->offset_line
||
862 rs
->clamp_fragment_color
= state
->clamp_fragment_color
;
863 rs
->clamp_vertex_color
= state
->clamp_vertex_color
;
864 rs
->flatshade
= state
->flatshade
;
865 rs
->sprite_coord_enable
= state
->sprite_coord_enable
;
866 rs
->rasterizer_discard
= state
->rasterizer_discard
;
867 rs
->pa_sc_line_stipple
= state
->line_stipple_enable
?
868 S_028A0C_LINE_PATTERN(state
->line_stipple_pattern
) |
869 S_028A0C_REPEAT_COUNT(state
->line_stipple_factor
) : 0;
870 rs
->pa_cl_clip_cntl
=
871 S_028810_DX_CLIP_SPACE_DEF(state
->clip_halfz
) |
872 S_028810_ZCLIP_NEAR_DISABLE(!state
->depth_clip
) |
873 S_028810_ZCLIP_FAR_DISABLE(!state
->depth_clip
) |
874 S_028810_DX_RASTERIZATION_KILL(state
->rasterizer_discard
) |
875 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
877 si_pm4_set_reg(pm4
, R_0286D4_SPI_INTERP_CONTROL_0
,
878 S_0286D4_FLAT_SHADE_ENA(1) |
879 S_0286D4_PNT_SPRITE_ENA(1) |
880 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
881 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
882 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
883 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
884 S_0286D4_PNT_SPRITE_TOP_1(state
->sprite_coord_mode
!= PIPE_SPRITE_COORD_UPPER_LEFT
));
886 /* point size 12.4 fixed point */
887 tmp
= (unsigned)(state
->point_size
* 8.0);
888 si_pm4_set_reg(pm4
, R_028A00_PA_SU_POINT_SIZE
, S_028A00_HEIGHT(tmp
) | S_028A00_WIDTH(tmp
));
890 if (state
->point_size_per_vertex
) {
891 psize_min
= util_get_min_point_size(state
);
894 /* Force the point size to be as if the vertex output was disabled. */
895 psize_min
= state
->point_size
;
896 psize_max
= state
->point_size
;
898 rs
->max_point_size
= psize_max
;
900 /* Divide by two, because 0.5 = 1 pixel. */
901 si_pm4_set_reg(pm4
, R_028A04_PA_SU_POINT_MINMAX
,
902 S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min
/2)) |
903 S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max
/2)));
905 si_pm4_set_reg(pm4
, R_028A08_PA_SU_LINE_CNTL
,
906 S_028A08_WIDTH(si_pack_float_12p4(state
->line_width
/2)));
907 si_pm4_set_reg(pm4
, R_028A48_PA_SC_MODE_CNTL_0
,
908 S_028A48_LINE_STIPPLE_ENABLE(state
->line_stipple_enable
) |
909 S_028A48_MSAA_ENABLE(state
->multisample
||
910 state
->poly_smooth
||
911 state
->line_smooth
) |
912 S_028A48_VPORT_SCISSOR_ENABLE(1) |
913 S_028A48_ALTERNATE_RBS_PER_TILE(sscreen
->b
.chip_class
>= GFX9
));
915 si_pm4_set_reg(pm4
, R_028BE4_PA_SU_VTX_CNTL
,
916 S_028BE4_PIX_CENTER(state
->half_pixel_center
) |
917 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
919 si_pm4_set_reg(pm4
, R_028B7C_PA_SU_POLY_OFFSET_CLAMP
, fui(state
->offset_clamp
));
920 si_pm4_set_reg(pm4
, R_028814_PA_SU_SC_MODE_CNTL
,
921 S_028814_PROVOKING_VTX_LAST(!state
->flatshade_first
) |
922 S_028814_CULL_FRONT((state
->cull_face
& PIPE_FACE_FRONT
) ? 1 : 0) |
923 S_028814_CULL_BACK((state
->cull_face
& PIPE_FACE_BACK
) ? 1 : 0) |
924 S_028814_FACE(!state
->front_ccw
) |
925 S_028814_POLY_OFFSET_FRONT_ENABLE(util_get_offset(state
, state
->fill_front
)) |
926 S_028814_POLY_OFFSET_BACK_ENABLE(util_get_offset(state
, state
->fill_back
)) |
927 S_028814_POLY_OFFSET_PARA_ENABLE(state
->offset_point
|| state
->offset_line
) |
928 S_028814_POLY_MODE(state
->fill_front
!= PIPE_POLYGON_MODE_FILL
||
929 state
->fill_back
!= PIPE_POLYGON_MODE_FILL
) |
930 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(state
->fill_front
)) |
931 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(state
->fill_back
)));
933 if (!rs
->uses_poly_offset
)
936 rs
->pm4_poly_offset
= CALLOC(3, sizeof(struct si_pm4_state
));
937 if (!rs
->pm4_poly_offset
) {
942 /* Precalculate polygon offset states for 16-bit, 24-bit, and 32-bit zbuffers. */
943 for (i
= 0; i
< 3; i
++) {
944 struct si_pm4_state
*pm4
= &rs
->pm4_poly_offset
[i
];
945 float offset_units
= state
->offset_units
;
946 float offset_scale
= state
->offset_scale
* 16.0f
;
947 uint32_t pa_su_poly_offset_db_fmt_cntl
= 0;
949 if (!state
->offset_units_unscaled
) {
951 case 0: /* 16-bit zbuffer */
952 offset_units
*= 4.0f
;
953 pa_su_poly_offset_db_fmt_cntl
=
954 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
956 case 1: /* 24-bit zbuffer */
957 offset_units
*= 2.0f
;
958 pa_su_poly_offset_db_fmt_cntl
=
959 S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
961 case 2: /* 32-bit zbuffer */
962 offset_units
*= 1.0f
;
963 pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
964 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
969 si_pm4_set_reg(pm4
, R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE
,
971 si_pm4_set_reg(pm4
, R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET
,
973 si_pm4_set_reg(pm4
, R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE
,
975 si_pm4_set_reg(pm4
, R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET
,
977 si_pm4_set_reg(pm4
, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL
,
978 pa_su_poly_offset_db_fmt_cntl
);
984 static void si_bind_rs_state(struct pipe_context
*ctx
, void *state
)
986 struct si_context
*sctx
= (struct si_context
*)ctx
;
987 struct si_state_rasterizer
*old_rs
=
988 (struct si_state_rasterizer
*)sctx
->queued
.named
.rasterizer
;
989 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
994 if (!old_rs
|| old_rs
->multisample_enable
!= rs
->multisample_enable
) {
995 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
997 /* Update the small primitive filter workaround if necessary. */
998 if (sctx
->screen
->has_msaa_sample_loc_bug
&&
999 sctx
->framebuffer
.nr_samples
> 1)
1000 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
1003 sctx
->current_vs_state
&= C_VS_STATE_CLAMP_VERTEX_COLOR
;
1004 sctx
->current_vs_state
|= S_VS_STATE_CLAMP_VERTEX_COLOR(rs
->clamp_vertex_color
);
1006 si_pm4_bind_state(sctx
, rasterizer
, rs
);
1007 si_update_poly_offset_state(sctx
);
1010 (old_rs
->scissor_enable
!= rs
->scissor_enable
||
1011 old_rs
->line_width
!= rs
->line_width
||
1012 old_rs
->max_point_size
!= rs
->max_point_size
)) {
1013 sctx
->scissors
.dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1014 si_mark_atom_dirty(sctx
, &sctx
->scissors
.atom
);
1018 old_rs
->clip_halfz
!= rs
->clip_halfz
) {
1019 sctx
->viewports
.depth_range_dirty_mask
= (1 << SI_MAX_VIEWPORTS
) - 1;
1020 si_mark_atom_dirty(sctx
, &sctx
->viewports
.atom
);
1024 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1025 old_rs
->pa_cl_clip_cntl
!= rs
->pa_cl_clip_cntl
)
1026 si_mark_atom_dirty(sctx
, &sctx
->clip_regs
);
1028 sctx
->ia_multi_vgt_param_key
.u
.line_stipple_enabled
=
1029 rs
->line_stipple_enable
;
1032 old_rs
->clip_plane_enable
!= rs
->clip_plane_enable
||
1033 old_rs
->rasterizer_discard
!= rs
->rasterizer_discard
||
1034 old_rs
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
1035 old_rs
->flatshade
!= rs
->flatshade
||
1036 old_rs
->two_side
!= rs
->two_side
||
1037 old_rs
->multisample_enable
!= rs
->multisample_enable
||
1038 old_rs
->poly_stipple_enable
!= rs
->poly_stipple_enable
||
1039 old_rs
->poly_smooth
!= rs
->poly_smooth
||
1040 old_rs
->line_smooth
!= rs
->line_smooth
||
1041 old_rs
->clamp_fragment_color
!= rs
->clamp_fragment_color
||
1042 old_rs
->force_persample_interp
!= rs
->force_persample_interp
)
1043 sctx
->do_update_shaders
= true;
1046 static void si_delete_rs_state(struct pipe_context
*ctx
, void *state
)
1048 struct si_context
*sctx
= (struct si_context
*)ctx
;
1049 struct si_state_rasterizer
*rs
= (struct si_state_rasterizer
*)state
;
1051 if (sctx
->queued
.named
.rasterizer
== state
)
1052 si_pm4_bind_state(sctx
, poly_offset
, NULL
);
1054 FREE(rs
->pm4_poly_offset
);
1055 si_pm4_delete_state(sctx
, rasterizer
, rs
);
1059 * infeered state between dsa and stencil ref
1061 static void si_emit_stencil_ref(struct si_context
*sctx
, struct r600_atom
*atom
)
1063 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1064 struct pipe_stencil_ref
*ref
= &sctx
->stencil_ref
.state
;
1065 struct si_dsa_stencil_ref_part
*dsa
= &sctx
->stencil_ref
.dsa_part
;
1067 radeon_set_context_reg_seq(cs
, R_028430_DB_STENCILREFMASK
, 2);
1068 radeon_emit(cs
, S_028430_STENCILTESTVAL(ref
->ref_value
[0]) |
1069 S_028430_STENCILMASK(dsa
->valuemask
[0]) |
1070 S_028430_STENCILWRITEMASK(dsa
->writemask
[0]) |
1071 S_028430_STENCILOPVAL(1));
1072 radeon_emit(cs
, S_028434_STENCILTESTVAL_BF(ref
->ref_value
[1]) |
1073 S_028434_STENCILMASK_BF(dsa
->valuemask
[1]) |
1074 S_028434_STENCILWRITEMASK_BF(dsa
->writemask
[1]) |
1075 S_028434_STENCILOPVAL_BF(1));
1078 static void si_set_stencil_ref(struct pipe_context
*ctx
,
1079 const struct pipe_stencil_ref
*state
)
1081 struct si_context
*sctx
= (struct si_context
*)ctx
;
1083 if (memcmp(&sctx
->stencil_ref
.state
, state
, sizeof(*state
)) == 0)
1086 sctx
->stencil_ref
.state
= *state
;
1087 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1095 static uint32_t si_translate_stencil_op(int s_op
)
1098 case PIPE_STENCIL_OP_KEEP
:
1099 return V_02842C_STENCIL_KEEP
;
1100 case PIPE_STENCIL_OP_ZERO
:
1101 return V_02842C_STENCIL_ZERO
;
1102 case PIPE_STENCIL_OP_REPLACE
:
1103 return V_02842C_STENCIL_REPLACE_TEST
;
1104 case PIPE_STENCIL_OP_INCR
:
1105 return V_02842C_STENCIL_ADD_CLAMP
;
1106 case PIPE_STENCIL_OP_DECR
:
1107 return V_02842C_STENCIL_SUB_CLAMP
;
1108 case PIPE_STENCIL_OP_INCR_WRAP
:
1109 return V_02842C_STENCIL_ADD_WRAP
;
1110 case PIPE_STENCIL_OP_DECR_WRAP
:
1111 return V_02842C_STENCIL_SUB_WRAP
;
1112 case PIPE_STENCIL_OP_INVERT
:
1113 return V_02842C_STENCIL_INVERT
;
1115 R600_ERR("Unknown stencil op %d", s_op
);
1122 static bool si_dsa_writes_stencil(const struct pipe_stencil_state
*s
)
1124 return s
->enabled
&& s
->writemask
&&
1125 (s
->fail_op
!= PIPE_STENCIL_OP_KEEP
||
1126 s
->zfail_op
!= PIPE_STENCIL_OP_KEEP
||
1127 s
->zpass_op
!= PIPE_STENCIL_OP_KEEP
);
1130 static bool si_order_invariant_stencil_op(enum pipe_stencil_op op
)
1132 /* REPLACE is normally order invariant, except when the stencil
1133 * reference value is written by the fragment shader. Tracking this
1134 * interaction does not seem worth the effort, so be conservative. */
1135 return op
!= PIPE_STENCIL_OP_INCR
&&
1136 op
!= PIPE_STENCIL_OP_DECR
&&
1137 op
!= PIPE_STENCIL_OP_REPLACE
;
1140 /* Compute whether, assuming Z writes are disabled, this stencil state is order
1141 * invariant in the sense that the set of passing fragments as well as the
1142 * final stencil buffer result does not depend on the order of fragments. */
1143 static bool si_order_invariant_stencil_state(const struct pipe_stencil_state
*state
)
1145 return !state
->enabled
|| !state
->writemask
||
1146 /* The following assumes that Z writes are disabled. */
1147 (state
->func
== PIPE_FUNC_ALWAYS
&&
1148 si_order_invariant_stencil_op(state
->zpass_op
) &&
1149 si_order_invariant_stencil_op(state
->zfail_op
)) ||
1150 (state
->func
== PIPE_FUNC_NEVER
&&
1151 si_order_invariant_stencil_op(state
->fail_op
));
1154 static void *si_create_dsa_state(struct pipe_context
*ctx
,
1155 const struct pipe_depth_stencil_alpha_state
*state
)
1157 struct si_context
*sctx
= (struct si_context
*)ctx
;
1158 struct si_state_dsa
*dsa
= CALLOC_STRUCT(si_state_dsa
);
1159 struct si_pm4_state
*pm4
= &dsa
->pm4
;
1160 unsigned db_depth_control
;
1161 uint32_t db_stencil_control
= 0;
1167 dsa
->stencil_ref
.valuemask
[0] = state
->stencil
[0].valuemask
;
1168 dsa
->stencil_ref
.valuemask
[1] = state
->stencil
[1].valuemask
;
1169 dsa
->stencil_ref
.writemask
[0] = state
->stencil
[0].writemask
;
1170 dsa
->stencil_ref
.writemask
[1] = state
->stencil
[1].writemask
;
1172 db_depth_control
= S_028800_Z_ENABLE(state
->depth
.enabled
) |
1173 S_028800_Z_WRITE_ENABLE(state
->depth
.writemask
) |
1174 S_028800_ZFUNC(state
->depth
.func
) |
1175 S_028800_DEPTH_BOUNDS_ENABLE(state
->depth
.bounds_test
);
1178 if (state
->stencil
[0].enabled
) {
1179 db_depth_control
|= S_028800_STENCIL_ENABLE(1);
1180 db_depth_control
|= S_028800_STENCILFUNC(state
->stencil
[0].func
);
1181 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(state
->stencil
[0].fail_op
));
1182 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(state
->stencil
[0].zpass_op
));
1183 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(state
->stencil
[0].zfail_op
));
1185 if (state
->stencil
[1].enabled
) {
1186 db_depth_control
|= S_028800_BACKFACE_ENABLE(1);
1187 db_depth_control
|= S_028800_STENCILFUNC_BF(state
->stencil
[1].func
);
1188 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(state
->stencil
[1].fail_op
));
1189 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(state
->stencil
[1].zpass_op
));
1190 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(state
->stencil
[1].zfail_op
));
1195 if (state
->alpha
.enabled
) {
1196 dsa
->alpha_func
= state
->alpha
.func
;
1198 si_pm4_set_reg(pm4
, R_00B030_SPI_SHADER_USER_DATA_PS_0
+
1199 SI_SGPR_ALPHA_REF
* 4, fui(state
->alpha
.ref_value
));
1201 dsa
->alpha_func
= PIPE_FUNC_ALWAYS
;
1204 si_pm4_set_reg(pm4
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
1205 if (state
->stencil
[0].enabled
)
1206 si_pm4_set_reg(pm4
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
1207 if (state
->depth
.bounds_test
) {
1208 si_pm4_set_reg(pm4
, R_028020_DB_DEPTH_BOUNDS_MIN
, fui(state
->depth
.bounds_min
));
1209 si_pm4_set_reg(pm4
, R_028024_DB_DEPTH_BOUNDS_MAX
, fui(state
->depth
.bounds_max
));
1212 dsa
->depth_enabled
= state
->depth
.enabled
;
1213 dsa
->depth_write_enabled
= state
->depth
.enabled
&&
1214 state
->depth
.writemask
;
1215 dsa
->stencil_enabled
= state
->stencil
[0].enabled
;
1216 dsa
->stencil_write_enabled
= state
->stencil
[0].enabled
&&
1217 (si_dsa_writes_stencil(&state
->stencil
[0]) ||
1218 si_dsa_writes_stencil(&state
->stencil
[1]));
1219 dsa
->db_can_write
= dsa
->depth_write_enabled
||
1220 dsa
->stencil_write_enabled
;
1222 bool zfunc_is_ordered
=
1223 state
->depth
.func
== PIPE_FUNC_NEVER
||
1224 state
->depth
.func
== PIPE_FUNC_LESS
||
1225 state
->depth
.func
== PIPE_FUNC_LEQUAL
||
1226 state
->depth
.func
== PIPE_FUNC_GREATER
||
1227 state
->depth
.func
== PIPE_FUNC_GEQUAL
;
1229 bool nozwrite_and_order_invariant_stencil
=
1230 !dsa
->db_can_write
||
1231 (!dsa
->depth_write_enabled
&&
1232 si_order_invariant_stencil_state(&state
->stencil
[0]) &&
1233 si_order_invariant_stencil_state(&state
->stencil
[1]));
1235 dsa
->order_invariance
[1].zs
=
1236 nozwrite_and_order_invariant_stencil
||
1237 (!dsa
->stencil_write_enabled
&& zfunc_is_ordered
);
1238 dsa
->order_invariance
[0].zs
= !dsa
->depth_write_enabled
|| zfunc_is_ordered
;
1240 dsa
->order_invariance
[1].pass_set
=
1241 nozwrite_and_order_invariant_stencil
||
1242 (!dsa
->stencil_write_enabled
&&
1243 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1244 state
->depth
.func
== PIPE_FUNC_NEVER
));
1245 dsa
->order_invariance
[0].pass_set
=
1246 !dsa
->depth_write_enabled
||
1247 (state
->depth
.func
== PIPE_FUNC_ALWAYS
||
1248 state
->depth
.func
== PIPE_FUNC_NEVER
);
1250 dsa
->order_invariance
[1].pass_last
=
1251 sctx
->screen
->assume_no_z_fights
&&
1252 !dsa
->stencil_write_enabled
&&
1253 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1254 dsa
->order_invariance
[0].pass_last
=
1255 sctx
->screen
->assume_no_z_fights
&&
1256 dsa
->depth_write_enabled
&& zfunc_is_ordered
;
1261 static void si_bind_dsa_state(struct pipe_context
*ctx
, void *state
)
1263 struct si_context
*sctx
= (struct si_context
*)ctx
;
1264 struct si_state_dsa
*old_dsa
= sctx
->queued
.named
.dsa
;
1265 struct si_state_dsa
*dsa
= state
;
1270 si_pm4_bind_state(sctx
, dsa
, dsa
);
1272 if (memcmp(&dsa
->stencil_ref
, &sctx
->stencil_ref
.dsa_part
,
1273 sizeof(struct si_dsa_stencil_ref_part
)) != 0) {
1274 sctx
->stencil_ref
.dsa_part
= dsa
->stencil_ref
;
1275 si_mark_atom_dirty(sctx
, &sctx
->stencil_ref
.atom
);
1278 if (!old_dsa
|| old_dsa
->alpha_func
!= dsa
->alpha_func
)
1279 sctx
->do_update_shaders
= true;
1281 if (sctx
->screen
->dpbb_allowed
&&
1283 (old_dsa
->depth_enabled
!= dsa
->depth_enabled
||
1284 old_dsa
->stencil_enabled
!= dsa
->stencil_enabled
||
1285 old_dsa
->db_can_write
!= dsa
->db_can_write
)))
1286 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
1288 if (sctx
->screen
->has_out_of_order_rast
&&
1290 memcmp(old_dsa
->order_invariance
, dsa
->order_invariance
,
1291 sizeof(old_dsa
->order_invariance
))))
1292 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1295 static void si_delete_dsa_state(struct pipe_context
*ctx
, void *state
)
1297 struct si_context
*sctx
= (struct si_context
*)ctx
;
1298 si_pm4_delete_state(sctx
, dsa
, (struct si_state_dsa
*)state
);
1301 static void *si_create_db_flush_dsa(struct si_context
*sctx
)
1303 struct pipe_depth_stencil_alpha_state dsa
= {};
1305 return sctx
->b
.b
.create_depth_stencil_alpha_state(&sctx
->b
.b
, &dsa
);
1308 /* DB RENDER STATE */
1310 static void si_set_active_query_state(struct pipe_context
*ctx
, boolean enable
)
1312 struct si_context
*sctx
= (struct si_context
*)ctx
;
1314 /* Pipeline stat & streamout queries. */
1316 sctx
->b
.flags
&= ~R600_CONTEXT_STOP_PIPELINE_STATS
;
1317 sctx
->b
.flags
|= R600_CONTEXT_START_PIPELINE_STATS
;
1319 sctx
->b
.flags
&= ~R600_CONTEXT_START_PIPELINE_STATS
;
1320 sctx
->b
.flags
|= R600_CONTEXT_STOP_PIPELINE_STATS
;
1323 /* Occlusion queries. */
1324 if (sctx
->occlusion_queries_disabled
!= !enable
) {
1325 sctx
->occlusion_queries_disabled
= !enable
;
1326 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1330 static void si_set_occlusion_query_state(struct pipe_context
*ctx
,
1332 bool old_perfect_enable
)
1334 struct si_context
*sctx
= (struct si_context
*)ctx
;
1336 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
1338 bool perfect_enable
= sctx
->b
.num_perfect_occlusion_queries
!= 0;
1340 if (perfect_enable
!= old_perfect_enable
)
1341 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
1344 static void si_save_qbo_state(struct pipe_context
*ctx
, struct r600_qbo_state
*st
)
1346 struct si_context
*sctx
= (struct si_context
*)ctx
;
1348 st
->saved_compute
= sctx
->cs_shader_state
.program
;
1350 si_get_pipe_constant_buffer(sctx
, PIPE_SHADER_COMPUTE
, 0, &st
->saved_const0
);
1351 si_get_shader_buffers(sctx
, PIPE_SHADER_COMPUTE
, 0, 3, st
->saved_ssbo
);
1354 static void si_emit_db_render_state(struct si_context
*sctx
, struct r600_atom
*state
)
1356 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
1357 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1358 unsigned db_shader_control
;
1360 radeon_set_context_reg_seq(cs
, R_028000_DB_RENDER_CONTROL
, 2);
1362 /* DB_RENDER_CONTROL */
1363 if (sctx
->dbcb_depth_copy_enabled
||
1364 sctx
->dbcb_stencil_copy_enabled
) {
1366 S_028000_DEPTH_COPY(sctx
->dbcb_depth_copy_enabled
) |
1367 S_028000_STENCIL_COPY(sctx
->dbcb_stencil_copy_enabled
) |
1368 S_028000_COPY_CENTROID(1) |
1369 S_028000_COPY_SAMPLE(sctx
->dbcb_copy_sample
));
1370 } else if (sctx
->db_flush_depth_inplace
|| sctx
->db_flush_stencil_inplace
) {
1372 S_028000_DEPTH_COMPRESS_DISABLE(sctx
->db_flush_depth_inplace
) |
1373 S_028000_STENCIL_COMPRESS_DISABLE(sctx
->db_flush_stencil_inplace
));
1376 S_028000_DEPTH_CLEAR_ENABLE(sctx
->db_depth_clear
) |
1377 S_028000_STENCIL_CLEAR_ENABLE(sctx
->db_stencil_clear
));
1380 /* DB_COUNT_CONTROL (occlusion queries) */
1381 if (sctx
->b
.num_occlusion_queries
> 0 &&
1382 !sctx
->occlusion_queries_disabled
) {
1383 bool perfect
= sctx
->b
.num_perfect_occlusion_queries
> 0;
1385 if (sctx
->b
.chip_class
>= CIK
) {
1387 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1388 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
) |
1389 S_028004_ZPASS_ENABLE(1) |
1390 S_028004_SLICE_EVEN_ENABLE(1) |
1391 S_028004_SLICE_ODD_ENABLE(1));
1394 S_028004_PERFECT_ZPASS_COUNTS(perfect
) |
1395 S_028004_SAMPLE_RATE(sctx
->framebuffer
.log_samples
));
1398 /* Disable occlusion queries. */
1399 if (sctx
->b
.chip_class
>= CIK
) {
1402 radeon_emit(cs
, S_028004_ZPASS_INCREMENT_DISABLE(1));
1406 /* DB_RENDER_OVERRIDE2 */
1407 radeon_set_context_reg(cs
, R_028010_DB_RENDER_OVERRIDE2
,
1408 S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(sctx
->db_depth_disable_expclear
) |
1409 S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(sctx
->db_stencil_disable_expclear
) |
1410 S_028010_DECOMPRESS_Z_ON_FLUSH(sctx
->framebuffer
.nr_samples
>= 4));
1412 db_shader_control
= sctx
->ps_db_shader_control
;
1414 /* Bug workaround for smoothing (overrasterization) on SI. */
1415 if (sctx
->b
.chip_class
== SI
&& sctx
->smoothing_enabled
) {
1416 db_shader_control
&= C_02880C_Z_ORDER
;
1417 db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
);
1420 /* Disable the gl_SampleMask fragment shader output if MSAA is disabled. */
1421 if (!rs
|| !rs
->multisample_enable
)
1422 db_shader_control
&= C_02880C_MASK_EXPORT_ENABLE
;
1424 if (sctx
->screen
->b
.has_rbplus
&&
1425 !sctx
->screen
->b
.rbplus_allowed
)
1426 db_shader_control
|= S_02880C_DUAL_QUAD_DISABLE(1);
1428 radeon_set_context_reg(cs
, R_02880C_DB_SHADER_CONTROL
,
1433 * format translation
1435 static uint32_t si_translate_colorformat(enum pipe_format format
)
1437 const struct util_format_description
*desc
= util_format_description(format
);
1439 return V_028C70_COLOR_INVALID
;
1441 #define HAS_SIZE(x,y,z,w) \
1442 (desc->channel[0].size == (x) && desc->channel[1].size == (y) && \
1443 desc->channel[2].size == (z) && desc->channel[3].size == (w))
1445 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1446 return V_028C70_COLOR_10_11_11
;
1448 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1449 return V_028C70_COLOR_INVALID
;
1451 /* hw cannot support mixed formats (except depth/stencil, since
1452 * stencil is not written to). */
1453 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1454 return V_028C70_COLOR_INVALID
;
1456 switch (desc
->nr_channels
) {
1458 switch (desc
->channel
[0].size
) {
1460 return V_028C70_COLOR_8
;
1462 return V_028C70_COLOR_16
;
1464 return V_028C70_COLOR_32
;
1468 if (desc
->channel
[0].size
== desc
->channel
[1].size
) {
1469 switch (desc
->channel
[0].size
) {
1471 return V_028C70_COLOR_8_8
;
1473 return V_028C70_COLOR_16_16
;
1475 return V_028C70_COLOR_32_32
;
1477 } else if (HAS_SIZE(8,24,0,0)) {
1478 return V_028C70_COLOR_24_8
;
1479 } else if (HAS_SIZE(24,8,0,0)) {
1480 return V_028C70_COLOR_8_24
;
1484 if (HAS_SIZE(5,6,5,0)) {
1485 return V_028C70_COLOR_5_6_5
;
1486 } else if (HAS_SIZE(32,8,24,0)) {
1487 return V_028C70_COLOR_X24_8_32_FLOAT
;
1491 if (desc
->channel
[0].size
== desc
->channel
[1].size
&&
1492 desc
->channel
[0].size
== desc
->channel
[2].size
&&
1493 desc
->channel
[0].size
== desc
->channel
[3].size
) {
1494 switch (desc
->channel
[0].size
) {
1496 return V_028C70_COLOR_4_4_4_4
;
1498 return V_028C70_COLOR_8_8_8_8
;
1500 return V_028C70_COLOR_16_16_16_16
;
1502 return V_028C70_COLOR_32_32_32_32
;
1504 } else if (HAS_SIZE(5,5,5,1)) {
1505 return V_028C70_COLOR_1_5_5_5
;
1506 } else if (HAS_SIZE(1,5,5,5)) {
1507 return V_028C70_COLOR_5_5_5_1
;
1508 } else if (HAS_SIZE(10,10,10,2)) {
1509 return V_028C70_COLOR_2_10_10_10
;
1513 return V_028C70_COLOR_INVALID
;
1516 static uint32_t si_colorformat_endian_swap(uint32_t colorformat
)
1518 if (SI_BIG_ENDIAN
) {
1519 switch(colorformat
) {
1520 /* 8-bit buffers. */
1521 case V_028C70_COLOR_8
:
1522 return V_028C70_ENDIAN_NONE
;
1524 /* 16-bit buffers. */
1525 case V_028C70_COLOR_5_6_5
:
1526 case V_028C70_COLOR_1_5_5_5
:
1527 case V_028C70_COLOR_4_4_4_4
:
1528 case V_028C70_COLOR_16
:
1529 case V_028C70_COLOR_8_8
:
1530 return V_028C70_ENDIAN_8IN16
;
1532 /* 32-bit buffers. */
1533 case V_028C70_COLOR_8_8_8_8
:
1534 case V_028C70_COLOR_2_10_10_10
:
1535 case V_028C70_COLOR_8_24
:
1536 case V_028C70_COLOR_24_8
:
1537 case V_028C70_COLOR_16_16
:
1538 return V_028C70_ENDIAN_8IN32
;
1540 /* 64-bit buffers. */
1541 case V_028C70_COLOR_16_16_16_16
:
1542 return V_028C70_ENDIAN_8IN16
;
1544 case V_028C70_COLOR_32_32
:
1545 return V_028C70_ENDIAN_8IN32
;
1547 /* 128-bit buffers. */
1548 case V_028C70_COLOR_32_32_32_32
:
1549 return V_028C70_ENDIAN_8IN32
;
1551 return V_028C70_ENDIAN_NONE
; /* Unsupported. */
1554 return V_028C70_ENDIAN_NONE
;
1558 static uint32_t si_translate_dbformat(enum pipe_format format
)
1561 case PIPE_FORMAT_Z16_UNORM
:
1562 return V_028040_Z_16
;
1563 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1564 case PIPE_FORMAT_X8Z24_UNORM
:
1565 case PIPE_FORMAT_Z24X8_UNORM
:
1566 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1567 return V_028040_Z_24
; /* deprecated on SI */
1568 case PIPE_FORMAT_Z32_FLOAT
:
1569 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1570 return V_028040_Z_32_FLOAT
;
1572 return V_028040_Z_INVALID
;
1577 * Texture translation
1580 static uint32_t si_translate_texformat(struct pipe_screen
*screen
,
1581 enum pipe_format format
,
1582 const struct util_format_description
*desc
,
1585 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1586 bool enable_compressed_formats
= (sscreen
->b
.info
.drm_major
== 2 &&
1587 sscreen
->b
.info
.drm_minor
>= 31) ||
1588 sscreen
->b
.info
.drm_major
== 3;
1589 bool uniform
= true;
1592 /* Colorspace (return non-RGB formats directly). */
1593 switch (desc
->colorspace
) {
1594 /* Depth stencil formats */
1595 case UTIL_FORMAT_COLORSPACE_ZS
:
1597 case PIPE_FORMAT_Z16_UNORM
:
1598 return V_008F14_IMG_DATA_FORMAT_16
;
1599 case PIPE_FORMAT_X24S8_UINT
:
1600 case PIPE_FORMAT_S8X24_UINT
:
1602 * Implemented as an 8_8_8_8 data format to fix texture
1603 * gathers in stencil sampling. This affects at least
1604 * GL45-CTS.texture_cube_map_array.sampling on VI.
1606 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1607 case PIPE_FORMAT_Z24X8_UNORM
:
1608 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1609 return V_008F14_IMG_DATA_FORMAT_8_24
;
1610 case PIPE_FORMAT_X8Z24_UNORM
:
1611 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1612 return V_008F14_IMG_DATA_FORMAT_24_8
;
1613 case PIPE_FORMAT_S8_UINT
:
1614 return V_008F14_IMG_DATA_FORMAT_8
;
1615 case PIPE_FORMAT_Z32_FLOAT
:
1616 return V_008F14_IMG_DATA_FORMAT_32
;
1617 case PIPE_FORMAT_X32_S8X24_UINT
:
1618 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1619 return V_008F14_IMG_DATA_FORMAT_X24_8_32
;
1624 case UTIL_FORMAT_COLORSPACE_YUV
:
1625 goto out_unknown
; /* TODO */
1627 case UTIL_FORMAT_COLORSPACE_SRGB
:
1628 if (desc
->nr_channels
!= 4 && desc
->nr_channels
!= 1)
1636 if (desc
->layout
== UTIL_FORMAT_LAYOUT_RGTC
) {
1637 if (!enable_compressed_formats
)
1641 case PIPE_FORMAT_RGTC1_SNORM
:
1642 case PIPE_FORMAT_LATC1_SNORM
:
1643 case PIPE_FORMAT_RGTC1_UNORM
:
1644 case PIPE_FORMAT_LATC1_UNORM
:
1645 return V_008F14_IMG_DATA_FORMAT_BC4
;
1646 case PIPE_FORMAT_RGTC2_SNORM
:
1647 case PIPE_FORMAT_LATC2_SNORM
:
1648 case PIPE_FORMAT_RGTC2_UNORM
:
1649 case PIPE_FORMAT_LATC2_UNORM
:
1650 return V_008F14_IMG_DATA_FORMAT_BC5
;
1656 if (desc
->layout
== UTIL_FORMAT_LAYOUT_ETC
&&
1657 (sscreen
->b
.family
== CHIP_STONEY
||
1658 sscreen
->b
.chip_class
>= GFX9
)) {
1660 case PIPE_FORMAT_ETC1_RGB8
:
1661 case PIPE_FORMAT_ETC2_RGB8
:
1662 case PIPE_FORMAT_ETC2_SRGB8
:
1663 return V_008F14_IMG_DATA_FORMAT_ETC2_RGB
;
1664 case PIPE_FORMAT_ETC2_RGB8A1
:
1665 case PIPE_FORMAT_ETC2_SRGB8A1
:
1666 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA1
;
1667 case PIPE_FORMAT_ETC2_RGBA8
:
1668 case PIPE_FORMAT_ETC2_SRGBA8
:
1669 return V_008F14_IMG_DATA_FORMAT_ETC2_RGBA
;
1670 case PIPE_FORMAT_ETC2_R11_UNORM
:
1671 case PIPE_FORMAT_ETC2_R11_SNORM
:
1672 return V_008F14_IMG_DATA_FORMAT_ETC2_R
;
1673 case PIPE_FORMAT_ETC2_RG11_UNORM
:
1674 case PIPE_FORMAT_ETC2_RG11_SNORM
:
1675 return V_008F14_IMG_DATA_FORMAT_ETC2_RG
;
1681 if (desc
->layout
== UTIL_FORMAT_LAYOUT_BPTC
) {
1682 if (!enable_compressed_formats
)
1686 case PIPE_FORMAT_BPTC_RGBA_UNORM
:
1687 case PIPE_FORMAT_BPTC_SRGBA
:
1688 return V_008F14_IMG_DATA_FORMAT_BC7
;
1689 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
1690 case PIPE_FORMAT_BPTC_RGB_UFLOAT
:
1691 return V_008F14_IMG_DATA_FORMAT_BC6
;
1697 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
1699 case PIPE_FORMAT_R8G8_B8G8_UNORM
:
1700 case PIPE_FORMAT_G8R8_B8R8_UNORM
:
1701 return V_008F14_IMG_DATA_FORMAT_GB_GR
;
1702 case PIPE_FORMAT_G8R8_G8B8_UNORM
:
1703 case PIPE_FORMAT_R8G8_R8B8_UNORM
:
1704 return V_008F14_IMG_DATA_FORMAT_BG_RG
;
1710 if (desc
->layout
== UTIL_FORMAT_LAYOUT_S3TC
) {
1711 if (!enable_compressed_formats
)
1715 case PIPE_FORMAT_DXT1_RGB
:
1716 case PIPE_FORMAT_DXT1_RGBA
:
1717 case PIPE_FORMAT_DXT1_SRGB
:
1718 case PIPE_FORMAT_DXT1_SRGBA
:
1719 return V_008F14_IMG_DATA_FORMAT_BC1
;
1720 case PIPE_FORMAT_DXT3_RGBA
:
1721 case PIPE_FORMAT_DXT3_SRGBA
:
1722 return V_008F14_IMG_DATA_FORMAT_BC2
;
1723 case PIPE_FORMAT_DXT5_RGBA
:
1724 case PIPE_FORMAT_DXT5_SRGBA
:
1725 return V_008F14_IMG_DATA_FORMAT_BC3
;
1731 if (format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) {
1732 return V_008F14_IMG_DATA_FORMAT_5_9_9_9
;
1733 } else if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) {
1734 return V_008F14_IMG_DATA_FORMAT_10_11_11
;
1737 /* R8G8Bx_SNORM - TODO CxV8U8 */
1739 /* hw cannot support mixed formats (except depth/stencil, since only
1741 if (desc
->is_mixed
&& desc
->colorspace
!= UTIL_FORMAT_COLORSPACE_ZS
)
1744 /* See whether the components are of the same size. */
1745 for (i
= 1; i
< desc
->nr_channels
; i
++) {
1746 uniform
= uniform
&& desc
->channel
[0].size
== desc
->channel
[i
].size
;
1749 /* Non-uniform formats. */
1751 switch(desc
->nr_channels
) {
1753 if (desc
->channel
[0].size
== 5 &&
1754 desc
->channel
[1].size
== 6 &&
1755 desc
->channel
[2].size
== 5) {
1756 return V_008F14_IMG_DATA_FORMAT_5_6_5
;
1760 if (desc
->channel
[0].size
== 5 &&
1761 desc
->channel
[1].size
== 5 &&
1762 desc
->channel
[2].size
== 5 &&
1763 desc
->channel
[3].size
== 1) {
1764 return V_008F14_IMG_DATA_FORMAT_1_5_5_5
;
1766 if (desc
->channel
[0].size
== 1 &&
1767 desc
->channel
[1].size
== 5 &&
1768 desc
->channel
[2].size
== 5 &&
1769 desc
->channel
[3].size
== 5) {
1770 return V_008F14_IMG_DATA_FORMAT_5_5_5_1
;
1772 if (desc
->channel
[0].size
== 10 &&
1773 desc
->channel
[1].size
== 10 &&
1774 desc
->channel
[2].size
== 10 &&
1775 desc
->channel
[3].size
== 2) {
1776 return V_008F14_IMG_DATA_FORMAT_2_10_10_10
;
1783 if (first_non_void
< 0 || first_non_void
> 3)
1786 /* uniform formats */
1787 switch (desc
->channel
[first_non_void
].size
) {
1789 switch (desc
->nr_channels
) {
1790 #if 0 /* Not supported for render targets */
1792 return V_008F14_IMG_DATA_FORMAT_4_4
;
1795 return V_008F14_IMG_DATA_FORMAT_4_4_4_4
;
1799 switch (desc
->nr_channels
) {
1801 return V_008F14_IMG_DATA_FORMAT_8
;
1803 return V_008F14_IMG_DATA_FORMAT_8_8
;
1805 return V_008F14_IMG_DATA_FORMAT_8_8_8_8
;
1809 switch (desc
->nr_channels
) {
1811 return V_008F14_IMG_DATA_FORMAT_16
;
1813 return V_008F14_IMG_DATA_FORMAT_16_16
;
1815 return V_008F14_IMG_DATA_FORMAT_16_16_16_16
;
1819 switch (desc
->nr_channels
) {
1821 return V_008F14_IMG_DATA_FORMAT_32
;
1823 return V_008F14_IMG_DATA_FORMAT_32_32
;
1824 #if 0 /* Not supported for render targets */
1826 return V_008F14_IMG_DATA_FORMAT_32_32_32
;
1829 return V_008F14_IMG_DATA_FORMAT_32_32_32_32
;
1834 /* R600_ERR("Unable to handle texformat %d %s\n", format, util_format_name(format)); */
1838 static unsigned si_tex_wrap(unsigned wrap
)
1842 case PIPE_TEX_WRAP_REPEAT
:
1843 return V_008F30_SQ_TEX_WRAP
;
1844 case PIPE_TEX_WRAP_CLAMP
:
1845 return V_008F30_SQ_TEX_CLAMP_HALF_BORDER
;
1846 case PIPE_TEX_WRAP_CLAMP_TO_EDGE
:
1847 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
1848 case PIPE_TEX_WRAP_CLAMP_TO_BORDER
:
1849 return V_008F30_SQ_TEX_CLAMP_BORDER
;
1850 case PIPE_TEX_WRAP_MIRROR_REPEAT
:
1851 return V_008F30_SQ_TEX_MIRROR
;
1852 case PIPE_TEX_WRAP_MIRROR_CLAMP
:
1853 return V_008F30_SQ_TEX_MIRROR_ONCE_HALF_BORDER
;
1854 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE
:
1855 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
1856 case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
:
1857 return V_008F30_SQ_TEX_MIRROR_ONCE_BORDER
;
1861 static unsigned si_tex_mipfilter(unsigned filter
)
1864 case PIPE_TEX_MIPFILTER_NEAREST
:
1865 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
1866 case PIPE_TEX_MIPFILTER_LINEAR
:
1867 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
1869 case PIPE_TEX_MIPFILTER_NONE
:
1870 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
1874 static unsigned si_tex_compare(unsigned compare
)
1878 case PIPE_FUNC_NEVER
:
1879 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
1880 case PIPE_FUNC_LESS
:
1881 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
1882 case PIPE_FUNC_EQUAL
:
1883 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
1884 case PIPE_FUNC_LEQUAL
:
1885 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
1886 case PIPE_FUNC_GREATER
:
1887 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
1888 case PIPE_FUNC_NOTEQUAL
:
1889 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
1890 case PIPE_FUNC_GEQUAL
:
1891 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
1892 case PIPE_FUNC_ALWAYS
:
1893 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
1897 static unsigned si_tex_dim(struct si_screen
*sscreen
, struct r600_texture
*rtex
,
1898 unsigned view_target
, unsigned nr_samples
)
1900 unsigned res_target
= rtex
->resource
.b
.b
.target
;
1902 if (view_target
== PIPE_TEXTURE_CUBE
||
1903 view_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1904 res_target
= view_target
;
1905 /* If interpreting cubemaps as something else, set 2D_ARRAY. */
1906 else if (res_target
== PIPE_TEXTURE_CUBE
||
1907 res_target
== PIPE_TEXTURE_CUBE_ARRAY
)
1908 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1910 /* GFX9 allocates 1D textures as 2D. */
1911 if ((res_target
== PIPE_TEXTURE_1D
||
1912 res_target
== PIPE_TEXTURE_1D_ARRAY
) &&
1913 sscreen
->b
.chip_class
>= GFX9
&&
1914 rtex
->surface
.u
.gfx9
.resource_type
== RADEON_RESOURCE_2D
) {
1915 if (res_target
== PIPE_TEXTURE_1D
)
1916 res_target
= PIPE_TEXTURE_2D
;
1918 res_target
= PIPE_TEXTURE_2D_ARRAY
;
1921 switch (res_target
) {
1923 case PIPE_TEXTURE_1D
:
1924 return V_008F1C_SQ_RSRC_IMG_1D
;
1925 case PIPE_TEXTURE_1D_ARRAY
:
1926 return V_008F1C_SQ_RSRC_IMG_1D_ARRAY
;
1927 case PIPE_TEXTURE_2D
:
1928 case PIPE_TEXTURE_RECT
:
1929 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA
:
1930 V_008F1C_SQ_RSRC_IMG_2D
;
1931 case PIPE_TEXTURE_2D_ARRAY
:
1932 return nr_samples
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
:
1933 V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
1934 case PIPE_TEXTURE_3D
:
1935 return V_008F1C_SQ_RSRC_IMG_3D
;
1936 case PIPE_TEXTURE_CUBE
:
1937 case PIPE_TEXTURE_CUBE_ARRAY
:
1938 return V_008F1C_SQ_RSRC_IMG_CUBE
;
1943 * Format support testing
1946 static bool si_is_sampler_format_supported(struct pipe_screen
*screen
, enum pipe_format format
)
1948 const struct util_format_description
*desc
= util_format_description(format
);
1952 return si_translate_texformat(screen
, format
, desc
,
1953 util_format_get_first_non_void_channel(format
)) != ~0U;
1956 static uint32_t si_translate_buffer_dataformat(struct pipe_screen
*screen
,
1957 const struct util_format_description
*desc
,
1962 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
1963 return V_008F0C_BUF_DATA_FORMAT_10_11_11
;
1965 assert(first_non_void
>= 0);
1967 if (desc
->nr_channels
== 4 &&
1968 desc
->channel
[0].size
== 10 &&
1969 desc
->channel
[1].size
== 10 &&
1970 desc
->channel
[2].size
== 10 &&
1971 desc
->channel
[3].size
== 2)
1972 return V_008F0C_BUF_DATA_FORMAT_2_10_10_10
;
1974 /* See whether the components are of the same size. */
1975 for (i
= 0; i
< desc
->nr_channels
; i
++) {
1976 if (desc
->channel
[first_non_void
].size
!= desc
->channel
[i
].size
)
1977 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
1980 switch (desc
->channel
[first_non_void
].size
) {
1982 switch (desc
->nr_channels
) {
1984 case 3: /* 3 loads */
1985 return V_008F0C_BUF_DATA_FORMAT_8
;
1987 return V_008F0C_BUF_DATA_FORMAT_8_8
;
1989 return V_008F0C_BUF_DATA_FORMAT_8_8_8_8
;
1993 switch (desc
->nr_channels
) {
1995 case 3: /* 3 loads */
1996 return V_008F0C_BUF_DATA_FORMAT_16
;
1998 return V_008F0C_BUF_DATA_FORMAT_16_16
;
2000 return V_008F0C_BUF_DATA_FORMAT_16_16_16_16
;
2004 switch (desc
->nr_channels
) {
2006 return V_008F0C_BUF_DATA_FORMAT_32
;
2008 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2010 return V_008F0C_BUF_DATA_FORMAT_32_32_32
;
2012 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2016 /* Legacy double formats. */
2017 switch (desc
->nr_channels
) {
2018 case 1: /* 1 load */
2019 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2020 case 2: /* 1 load */
2021 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2022 case 3: /* 3 loads */
2023 return V_008F0C_BUF_DATA_FORMAT_32_32
;
2024 case 4: /* 2 loads */
2025 return V_008F0C_BUF_DATA_FORMAT_32_32_32_32
;
2030 return V_008F0C_BUF_DATA_FORMAT_INVALID
;
2033 static uint32_t si_translate_buffer_numformat(struct pipe_screen
*screen
,
2034 const struct util_format_description
*desc
,
2037 if (desc
->format
== PIPE_FORMAT_R11G11B10_FLOAT
)
2038 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2040 assert(first_non_void
>= 0);
2042 switch (desc
->channel
[first_non_void
].type
) {
2043 case UTIL_FORMAT_TYPE_SIGNED
:
2044 case UTIL_FORMAT_TYPE_FIXED
:
2045 if (desc
->channel
[first_non_void
].size
>= 32 ||
2046 desc
->channel
[first_non_void
].pure_integer
)
2047 return V_008F0C_BUF_NUM_FORMAT_SINT
;
2048 else if (desc
->channel
[first_non_void
].normalized
)
2049 return V_008F0C_BUF_NUM_FORMAT_SNORM
;
2051 return V_008F0C_BUF_NUM_FORMAT_SSCALED
;
2053 case UTIL_FORMAT_TYPE_UNSIGNED
:
2054 if (desc
->channel
[first_non_void
].size
>= 32 ||
2055 desc
->channel
[first_non_void
].pure_integer
)
2056 return V_008F0C_BUF_NUM_FORMAT_UINT
;
2057 else if (desc
->channel
[first_non_void
].normalized
)
2058 return V_008F0C_BUF_NUM_FORMAT_UNORM
;
2060 return V_008F0C_BUF_NUM_FORMAT_USCALED
;
2062 case UTIL_FORMAT_TYPE_FLOAT
:
2064 return V_008F0C_BUF_NUM_FORMAT_FLOAT
;
2068 static unsigned si_is_vertex_format_supported(struct pipe_screen
*screen
,
2069 enum pipe_format format
,
2072 const struct util_format_description
*desc
;
2074 unsigned data_format
;
2076 assert((usage
& ~(PIPE_BIND_SHADER_IMAGE
|
2077 PIPE_BIND_SAMPLER_VIEW
|
2078 PIPE_BIND_VERTEX_BUFFER
)) == 0);
2080 desc
= util_format_description(format
);
2084 /* There are no native 8_8_8 or 16_16_16 data formats, and we currently
2085 * select 8_8_8_8 and 16_16_16_16 instead. This works reasonably well
2086 * for read-only access (with caveats surrounding bounds checks), but
2087 * obviously fails for write access which we have to implement for
2088 * shader images. Luckily, OpenGL doesn't expect this to be supported
2089 * anyway, and so the only impact is on PBO uploads / downloads, which
2090 * shouldn't be expected to be fast for GL_RGB anyway.
2092 if (desc
->block
.bits
== 3 * 8 ||
2093 desc
->block
.bits
== 3 * 16) {
2094 if (usage
& (PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
)) {
2095 usage
&= ~(PIPE_BIND_SHADER_IMAGE
| PIPE_BIND_SAMPLER_VIEW
);
2101 first_non_void
= util_format_get_first_non_void_channel(format
);
2102 data_format
= si_translate_buffer_dataformat(screen
, desc
, first_non_void
);
2103 if (data_format
== V_008F0C_BUF_DATA_FORMAT_INVALID
)
2109 static bool si_is_colorbuffer_format_supported(enum pipe_format format
)
2111 return si_translate_colorformat(format
) != V_028C70_COLOR_INVALID
&&
2112 si_translate_colorswap(format
, false) != ~0U;
2115 static bool si_is_zs_format_supported(enum pipe_format format
)
2117 return si_translate_dbformat(format
) != V_028040_Z_INVALID
;
2120 static boolean
si_is_format_supported(struct pipe_screen
*screen
,
2121 enum pipe_format format
,
2122 enum pipe_texture_target target
,
2123 unsigned sample_count
,
2126 unsigned retval
= 0;
2128 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
2129 R600_ERR("r600: unsupported texture type %d\n", target
);
2133 if (!util_format_is_supported(format
, usage
))
2136 if (sample_count
> 1) {
2137 if (!screen
->get_param(screen
, PIPE_CAP_TEXTURE_MULTISAMPLE
))
2140 if (usage
& PIPE_BIND_SHADER_IMAGE
)
2143 switch (sample_count
) {
2149 if (format
== PIPE_FORMAT_NONE
)
2158 if (usage
& (PIPE_BIND_SAMPLER_VIEW
|
2159 PIPE_BIND_SHADER_IMAGE
)) {
2160 if (target
== PIPE_BUFFER
) {
2161 retval
|= si_is_vertex_format_supported(
2162 screen
, format
, usage
& (PIPE_BIND_SAMPLER_VIEW
|
2163 PIPE_BIND_SHADER_IMAGE
));
2165 if (si_is_sampler_format_supported(screen
, format
))
2166 retval
|= usage
& (PIPE_BIND_SAMPLER_VIEW
|
2167 PIPE_BIND_SHADER_IMAGE
);
2171 if ((usage
& (PIPE_BIND_RENDER_TARGET
|
2172 PIPE_BIND_DISPLAY_TARGET
|
2175 PIPE_BIND_BLENDABLE
)) &&
2176 si_is_colorbuffer_format_supported(format
)) {
2178 (PIPE_BIND_RENDER_TARGET
|
2179 PIPE_BIND_DISPLAY_TARGET
|
2182 if (!util_format_is_pure_integer(format
) &&
2183 !util_format_is_depth_or_stencil(format
))
2184 retval
|= usage
& PIPE_BIND_BLENDABLE
;
2187 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
2188 si_is_zs_format_supported(format
)) {
2189 retval
|= PIPE_BIND_DEPTH_STENCIL
;
2192 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
2193 retval
|= si_is_vertex_format_supported(screen
, format
,
2194 PIPE_BIND_VERTEX_BUFFER
);
2197 if ((usage
& PIPE_BIND_LINEAR
) &&
2198 !util_format_is_compressed(format
) &&
2199 !(usage
& PIPE_BIND_DEPTH_STENCIL
))
2200 retval
|= PIPE_BIND_LINEAR
;
2202 return retval
== usage
;
2206 * framebuffer handling
2209 static void si_choose_spi_color_formats(struct r600_surface
*surf
,
2210 unsigned format
, unsigned swap
,
2211 unsigned ntype
, bool is_depth
)
2213 /* Alpha is needed for alpha-to-coverage.
2214 * Blending may be with or without alpha.
2216 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
2217 unsigned alpha
= 0; /* exports alpha, but may not support blending */
2218 unsigned blend
= 0; /* supports blending, but may not export alpha */
2219 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
2221 /* Choose the SPI color formats. These are required values for RB+.
2222 * Other chips have multiple choices, though they are not necessarily better.
2225 case V_028C70_COLOR_5_6_5
:
2226 case V_028C70_COLOR_1_5_5_5
:
2227 case V_028C70_COLOR_5_5_5_1
:
2228 case V_028C70_COLOR_4_4_4_4
:
2229 case V_028C70_COLOR_10_11_11
:
2230 case V_028C70_COLOR_11_11_10
:
2231 case V_028C70_COLOR_8
:
2232 case V_028C70_COLOR_8_8
:
2233 case V_028C70_COLOR_8_8_8_8
:
2234 case V_028C70_COLOR_10_10_10_2
:
2235 case V_028C70_COLOR_2_10_10_10
:
2236 if (ntype
== V_028C70_NUMBER_UINT
)
2237 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2238 else if (ntype
== V_028C70_NUMBER_SINT
)
2239 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2241 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2244 case V_028C70_COLOR_16
:
2245 case V_028C70_COLOR_16_16
:
2246 case V_028C70_COLOR_16_16_16_16
:
2247 if (ntype
== V_028C70_NUMBER_UNORM
||
2248 ntype
== V_028C70_NUMBER_SNORM
) {
2249 /* UNORM16 and SNORM16 don't support blending */
2250 if (ntype
== V_028C70_NUMBER_UNORM
)
2251 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
2253 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
2255 /* Use 32 bits per channel for blending. */
2256 if (format
== V_028C70_COLOR_16
) {
2257 if (swap
== V_028C70_SWAP_STD
) { /* R */
2258 blend
= V_028714_SPI_SHADER_32_R
;
2259 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2260 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2261 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2264 } else if (format
== V_028C70_COLOR_16_16
) {
2265 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2266 blend
= V_028714_SPI_SHADER_32_GR
;
2267 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2268 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2269 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2272 } else /* 16_16_16_16 */
2273 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2274 } else if (ntype
== V_028C70_NUMBER_UINT
)
2275 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
2276 else if (ntype
== V_028C70_NUMBER_SINT
)
2277 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
2278 else if (ntype
== V_028C70_NUMBER_FLOAT
)
2279 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
2284 case V_028C70_COLOR_32
:
2285 if (swap
== V_028C70_SWAP_STD
) { /* R */
2286 blend
= normal
= V_028714_SPI_SHADER_32_R
;
2287 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
2288 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
2289 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2294 case V_028C70_COLOR_32_32
:
2295 if (swap
== V_028C70_SWAP_STD
) { /* RG */
2296 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
2297 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
2298 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
2299 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
2304 case V_028C70_COLOR_32_32_32_32
:
2305 case V_028C70_COLOR_8_24
:
2306 case V_028C70_COLOR_24_8
:
2307 case V_028C70_COLOR_X24_8_32_FLOAT
:
2308 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2316 /* The DB->CB copy needs 32_ABGR. */
2318 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
2320 surf
->spi_shader_col_format
= normal
;
2321 surf
->spi_shader_col_format_alpha
= alpha
;
2322 surf
->spi_shader_col_format_blend
= blend
;
2323 surf
->spi_shader_col_format_blend_alpha
= blend_alpha
;
2326 static void si_initialize_color_surface(struct si_context
*sctx
,
2327 struct r600_surface
*surf
)
2329 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2330 unsigned color_info
, color_attrib
, color_view
;
2331 unsigned format
, swap
, ntype
, endian
;
2332 const struct util_format_description
*desc
;
2334 unsigned blend_clamp
= 0, blend_bypass
= 0;
2336 color_view
= S_028C6C_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2337 S_028C6C_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2339 desc
= util_format_description(surf
->base
.format
);
2340 for (firstchan
= 0; firstchan
< 4; firstchan
++) {
2341 if (desc
->channel
[firstchan
].type
!= UTIL_FORMAT_TYPE_VOID
) {
2345 if (firstchan
== 4 || desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_FLOAT
) {
2346 ntype
= V_028C70_NUMBER_FLOAT
;
2348 ntype
= V_028C70_NUMBER_UNORM
;
2349 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
)
2350 ntype
= V_028C70_NUMBER_SRGB
;
2351 else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_SIGNED
) {
2352 if (desc
->channel
[firstchan
].pure_integer
) {
2353 ntype
= V_028C70_NUMBER_SINT
;
2355 assert(desc
->channel
[firstchan
].normalized
);
2356 ntype
= V_028C70_NUMBER_SNORM
;
2358 } else if (desc
->channel
[firstchan
].type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
2359 if (desc
->channel
[firstchan
].pure_integer
) {
2360 ntype
= V_028C70_NUMBER_UINT
;
2362 assert(desc
->channel
[firstchan
].normalized
);
2363 ntype
= V_028C70_NUMBER_UNORM
;
2368 format
= si_translate_colorformat(surf
->base
.format
);
2369 if (format
== V_028C70_COLOR_INVALID
) {
2370 R600_ERR("Invalid CB format: %d, disabling CB.\n", surf
->base
.format
);
2372 assert(format
!= V_028C70_COLOR_INVALID
);
2373 swap
= si_translate_colorswap(surf
->base
.format
, false);
2374 endian
= si_colorformat_endian_swap(format
);
2376 /* blend clamp should be set for all NORM/SRGB types */
2377 if (ntype
== V_028C70_NUMBER_UNORM
||
2378 ntype
== V_028C70_NUMBER_SNORM
||
2379 ntype
== V_028C70_NUMBER_SRGB
)
2382 /* set blend bypass according to docs if SINT/UINT or
2383 8/24 COLOR variants */
2384 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2385 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2386 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2391 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) {
2392 if (format
== V_028C70_COLOR_8
||
2393 format
== V_028C70_COLOR_8_8
||
2394 format
== V_028C70_COLOR_8_8_8_8
)
2395 surf
->color_is_int8
= true;
2396 else if (format
== V_028C70_COLOR_10_10_10_2
||
2397 format
== V_028C70_COLOR_2_10_10_10
)
2398 surf
->color_is_int10
= true;
2401 color_info
= S_028C70_FORMAT(format
) |
2402 S_028C70_COMP_SWAP(swap
) |
2403 S_028C70_BLEND_CLAMP(blend_clamp
) |
2404 S_028C70_BLEND_BYPASS(blend_bypass
) |
2405 S_028C70_SIMPLE_FLOAT(1) |
2406 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2407 ntype
!= V_028C70_NUMBER_SNORM
&&
2408 ntype
!= V_028C70_NUMBER_SRGB
&&
2409 format
!= V_028C70_COLOR_8_24
&&
2410 format
!= V_028C70_COLOR_24_8
) |
2411 S_028C70_NUMBER_TYPE(ntype
) |
2412 S_028C70_ENDIAN(endian
);
2414 /* Intensity is implemented as Red, so treat it that way. */
2415 color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == PIPE_SWIZZLE_1
||
2416 util_format_is_intensity(surf
->base
.format
));
2418 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2419 unsigned log_samples
= util_logbase2(rtex
->resource
.b
.b
.nr_samples
);
2421 color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2422 S_028C74_NUM_FRAGMENTS(log_samples
);
2424 if (rtex
->fmask
.size
) {
2425 color_info
|= S_028C70_COMPRESSION(1);
2426 unsigned fmask_bankh
= util_logbase2(rtex
->fmask
.bank_height
);
2428 if (sctx
->b
.chip_class
== SI
) {
2429 /* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
2430 color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2435 surf
->cb_color_view
= color_view
;
2436 surf
->cb_color_info
= color_info
;
2437 surf
->cb_color_attrib
= color_attrib
;
2439 if (sctx
->b
.chip_class
>= VI
) {
2440 unsigned max_uncompressed_block_size
= 2;
2442 if (rtex
->resource
.b
.b
.nr_samples
> 1) {
2443 if (rtex
->surface
.bpe
== 1)
2444 max_uncompressed_block_size
= 0;
2445 else if (rtex
->surface
.bpe
== 2)
2446 max_uncompressed_block_size
= 1;
2449 surf
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2450 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2453 /* This must be set for fast clear to work without FMASK. */
2454 if (!rtex
->fmask
.size
&& sctx
->b
.chip_class
== SI
) {
2455 unsigned bankh
= util_logbase2(rtex
->surface
.u
.legacy
.bankh
);
2456 surf
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
2459 if (sctx
->b
.chip_class
>= GFX9
) {
2460 unsigned mip0_depth
= util_max_layer(&rtex
->resource
.b
.b
, 0);
2462 surf
->cb_color_view
|= S_028C6C_MIP_LEVEL(surf
->base
.u
.tex
.level
);
2463 surf
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
2464 S_028C74_RESOURCE_TYPE(rtex
->surface
.u
.gfx9
.resource_type
);
2465 surf
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(surf
->width0
- 1) |
2466 S_028C68_MIP0_HEIGHT(surf
->height0
- 1) |
2467 S_028C68_MAX_MIP(rtex
->resource
.b
.b
.last_level
);
2470 /* Determine pixel shader export format */
2471 si_choose_spi_color_formats(surf
, format
, swap
, ntype
, rtex
->is_depth
);
2473 surf
->color_initialized
= true;
2476 static void si_init_depth_surface(struct si_context
*sctx
,
2477 struct r600_surface
*surf
)
2479 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->base
.texture
;
2480 unsigned level
= surf
->base
.u
.tex
.level
;
2481 unsigned format
, stencil_format
;
2482 uint32_t z_info
, s_info
;
2484 format
= si_translate_dbformat(rtex
->db_render_format
);
2485 stencil_format
= rtex
->surface
.has_stencil
?
2486 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
2488 assert(format
!= V_028040_Z_INVALID
);
2489 if (format
== V_028040_Z_INVALID
)
2490 R600_ERR("Invalid DB format: %d, disabling DB.\n", rtex
->resource
.b
.b
.format
);
2492 surf
->db_depth_view
= S_028008_SLICE_START(surf
->base
.u
.tex
.first_layer
) |
2493 S_028008_SLICE_MAX(surf
->base
.u
.tex
.last_layer
);
2494 surf
->db_htile_data_base
= 0;
2495 surf
->db_htile_surface
= 0;
2497 if (sctx
->b
.chip_class
>= GFX9
) {
2498 assert(rtex
->surface
.u
.gfx9
.surf_offset
== 0);
2499 surf
->db_depth_base
= rtex
->resource
.gpu_address
>> 8;
2500 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2501 rtex
->surface
.u
.gfx9
.stencil_offset
) >> 8;
2502 z_info
= S_028038_FORMAT(format
) |
2503 S_028038_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
)) |
2504 S_028038_SW_MODE(rtex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2505 S_028038_MAXMIP(rtex
->resource
.b
.b
.last_level
);
2506 s_info
= S_02803C_FORMAT(stencil_format
) |
2507 S_02803C_SW_MODE(rtex
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
2508 surf
->db_z_info2
= S_028068_EPITCH(rtex
->surface
.u
.gfx9
.surf
.epitch
);
2509 surf
->db_stencil_info2
= S_02806C_EPITCH(rtex
->surface
.u
.gfx9
.stencil
.epitch
);
2510 surf
->db_depth_view
|= S_028008_MIPID(level
);
2511 surf
->db_depth_size
= S_02801C_X_MAX(rtex
->resource
.b
.b
.width0
- 1) |
2512 S_02801C_Y_MAX(rtex
->resource
.b
.b
.height0
- 1);
2514 if (r600_htile_enabled(rtex
, level
)) {
2515 z_info
|= S_028038_TILE_SURFACE_ENABLE(1) |
2516 S_028038_ALLOW_EXPCLEAR(1);
2518 if (rtex
->tc_compatible_htile
) {
2519 unsigned max_zplanes
= 4;
2521 if (rtex
->db_render_format
== PIPE_FORMAT_Z16_UNORM
&&
2522 rtex
->resource
.b
.b
.nr_samples
> 1)
2525 z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
2526 S_028038_ITERATE_FLUSH(1);
2527 s_info
|= S_02803C_ITERATE_FLUSH(1);
2530 if (rtex
->surface
.has_stencil
) {
2531 /* Stencil buffer workaround ported from the SI-CI-VI code.
2532 * See that for explanation.
2534 s_info
|= S_02803C_ALLOW_EXPCLEAR(rtex
->resource
.b
.b
.nr_samples
<= 1);
2536 /* Use all HTILE for depth if there's no stencil. */
2537 s_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
2540 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2541 rtex
->htile_offset
) >> 8;
2542 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
2543 S_028ABC_PIPE_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
2544 S_028ABC_RB_ALIGNED(rtex
->surface
.u
.gfx9
.htile
.rb_aligned
);
2548 struct legacy_surf_level
*levelinfo
= &rtex
->surface
.u
.legacy
.level
[level
];
2550 assert(levelinfo
->nblk_x
% 8 == 0 && levelinfo
->nblk_y
% 8 == 0);
2552 surf
->db_depth_base
= (rtex
->resource
.gpu_address
+
2553 rtex
->surface
.u
.legacy
.level
[level
].offset
) >> 8;
2554 surf
->db_stencil_base
= (rtex
->resource
.gpu_address
+
2555 rtex
->surface
.u
.legacy
.stencil_level
[level
].offset
) >> 8;
2557 z_info
= S_028040_FORMAT(format
) |
2558 S_028040_NUM_SAMPLES(util_logbase2(rtex
->resource
.b
.b
.nr_samples
));
2559 s_info
= S_028044_FORMAT(stencil_format
);
2560 surf
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!rtex
->tc_compatible_htile
);
2562 if (sctx
->b
.chip_class
>= CIK
) {
2563 struct radeon_info
*info
= &sctx
->screen
->b
.info
;
2564 unsigned index
= rtex
->surface
.u
.legacy
.tiling_index
[level
];
2565 unsigned stencil_index
= rtex
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2566 unsigned macro_index
= rtex
->surface
.u
.legacy
.macro_tile_index
;
2567 unsigned tile_mode
= info
->si_tile_mode_array
[index
];
2568 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
2569 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
2571 surf
->db_depth_info
|=
2572 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
2573 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
2574 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
2575 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
2576 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
2577 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
2578 z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
2579 s_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
2581 unsigned tile_mode_index
= si_tile_mode_index(rtex
, level
, false);
2582 z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
2583 tile_mode_index
= si_tile_mode_index(rtex
, level
, true);
2584 s_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
2587 surf
->db_depth_size
= S_028058_PITCH_TILE_MAX((levelinfo
->nblk_x
/ 8) - 1) |
2588 S_028058_HEIGHT_TILE_MAX((levelinfo
->nblk_y
/ 8) - 1);
2589 surf
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((levelinfo
->nblk_x
*
2590 levelinfo
->nblk_y
) / 64 - 1);
2592 if (r600_htile_enabled(rtex
, level
)) {
2593 z_info
|= S_028040_TILE_SURFACE_ENABLE(1) |
2594 S_028040_ALLOW_EXPCLEAR(1);
2596 if (rtex
->surface
.has_stencil
) {
2597 /* Workaround: For a not yet understood reason, the
2598 * combination of MSAA, fast stencil clear and stencil
2599 * decompress messes with subsequent stencil buffer
2600 * uses. Problem was reproduced on Verde, Bonaire,
2601 * Tonga, and Carrizo.
2603 * Disabling EXPCLEAR works around the problem.
2605 * Check piglit's arb_texture_multisample-stencil-clear
2606 * test if you want to try changing this.
2608 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2609 s_info
|= S_028044_ALLOW_EXPCLEAR(1);
2610 } else if (!rtex
->tc_compatible_htile
) {
2611 /* Use all of the htile_buffer for depth if there's no stencil.
2612 * This must not be set when TC-compatible HTILE is enabled
2615 s_info
|= S_028044_TILE_STENCIL_DISABLE(1);
2618 surf
->db_htile_data_base
= (rtex
->resource
.gpu_address
+
2619 rtex
->htile_offset
) >> 8;
2620 surf
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
2622 if (rtex
->tc_compatible_htile
) {
2623 surf
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
2625 if (rtex
->resource
.b
.b
.nr_samples
<= 1)
2626 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
2627 else if (rtex
->resource
.b
.b
.nr_samples
<= 4)
2628 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
2630 z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
2635 surf
->db_z_info
= z_info
;
2636 surf
->db_stencil_info
= s_info
;
2638 surf
->depth_initialized
= true;
2641 void si_update_fb_dirtiness_after_rendering(struct si_context
*sctx
)
2643 if (sctx
->decompression_enabled
)
2646 if (sctx
->framebuffer
.state
.zsbuf
) {
2647 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.zsbuf
;
2648 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2650 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2652 if (rtex
->surface
.has_stencil
)
2653 rtex
->stencil_dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2656 unsigned compressed_cb_mask
= sctx
->framebuffer
.compressed_cb_mask
;
2657 while (compressed_cb_mask
) {
2658 unsigned i
= u_bit_scan(&compressed_cb_mask
);
2659 struct pipe_surface
*surf
= sctx
->framebuffer
.state
.cbufs
[i
];
2660 struct r600_texture
*rtex
= (struct r600_texture
*)surf
->texture
;
2662 if (rtex
->fmask
.size
)
2663 rtex
->dirty_level_mask
|= 1 << surf
->u
.tex
.level
;
2664 if (rtex
->dcc_gather_statistics
)
2665 rtex
->separate_dcc_dirty
= true;
2669 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state
*state
)
2671 for (int i
= 0; i
< state
->nr_cbufs
; ++i
) {
2672 struct r600_surface
*surf
= NULL
;
2673 struct r600_texture
*rtex
;
2675 if (!state
->cbufs
[i
])
2677 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2678 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2680 p_atomic_dec(&rtex
->framebuffers_bound
);
2684 static void si_set_framebuffer_state(struct pipe_context
*ctx
,
2685 const struct pipe_framebuffer_state
*state
)
2687 struct si_context
*sctx
= (struct si_context
*)ctx
;
2688 struct pipe_constant_buffer constbuf
= {0};
2689 struct r600_surface
*surf
= NULL
;
2690 struct r600_texture
*rtex
;
2691 bool old_any_dst_linear
= sctx
->framebuffer
.any_dst_linear
;
2692 unsigned old_nr_samples
= sctx
->framebuffer
.nr_samples
;
2693 unsigned old_colorbuf_enabled_4bit
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
2694 bool old_has_zsbuf
= !!sctx
->framebuffer
.state
.zsbuf
;
2695 bool old_has_stencil
=
2697 ((struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
)->surface
.has_stencil
;
2698 bool unbound
= false;
2701 si_update_fb_dirtiness_after_rendering(sctx
);
2703 for (i
= 0; i
< sctx
->framebuffer
.state
.nr_cbufs
; i
++) {
2704 if (!sctx
->framebuffer
.state
.cbufs
[i
])
2707 rtex
= (struct r600_texture
*)sctx
->framebuffer
.state
.cbufs
[i
]->texture
;
2708 if (rtex
->dcc_gather_statistics
)
2709 vi_separate_dcc_stop_query(ctx
, rtex
);
2712 /* Disable DCC if the formats are incompatible. */
2713 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2714 if (!state
->cbufs
[i
])
2717 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2718 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2720 if (!surf
->dcc_incompatible
)
2723 /* Since the DCC decompression calls back into set_framebuffer-
2724 * _state, we need to unbind the framebuffer, so that
2725 * vi_separate_dcc_stop_query isn't called twice with the same
2729 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, NULL
);
2733 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2734 if (!si_texture_disable_dcc(&sctx
->b
, rtex
))
2735 sctx
->b
.decompress_dcc(ctx
, rtex
);
2737 surf
->dcc_incompatible
= false;
2740 /* Only flush TC when changing the framebuffer state, because
2741 * the only client not using TC that can change textures is
2744 * Wait for compute shaders because of possible transitions:
2745 * - FB write -> shader read
2746 * - shader write -> FB read
2748 * DB caches are flushed on demand (using si_decompress_textures).
2750 * When MSAA is enabled, CB and TC caches are flushed on demand
2751 * (after FMASK decompression). Shader write -> FB read transitions
2752 * cannot happen for MSAA textures, because MSAA shader images are
2755 * Only flush and wait for CB if there is actually a bound color buffer.
2757 if (sctx
->framebuffer
.nr_samples
<= 1 &&
2758 sctx
->framebuffer
.state
.nr_cbufs
)
2759 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
2760 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
2762 sctx
->b
.flags
|= SI_CONTEXT_CS_PARTIAL_FLUSH
;
2764 /* u_blitter doesn't invoke depth decompression when it does multiple
2765 * blits in a row, but the only case when it matters for DB is when
2766 * doing generate_mipmap. So here we flush DB manually between
2767 * individual generate_mipmap blits.
2768 * Note that lower mipmap levels aren't compressed.
2770 if (sctx
->generate_mipmap_for_depth
) {
2771 si_make_DB_shader_coherent(sctx
, 1, false,
2772 sctx
->framebuffer
.DB_has_shader_readable_metadata
);
2773 } else if (sctx
->b
.chip_class
== GFX9
) {
2774 /* It appears that DB metadata "leaks" in a sequence of:
2776 * - DCC decompress for shader image writes (with DB disabled)
2777 * - render with DEPTH_BEFORE_SHADER=1
2778 * Flushing DB metadata works around the problem.
2780 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_DB_META
;
2783 /* Take the maximum of the old and new count. If the new count is lower,
2784 * dirtying is needed to disable the unbound colorbuffers.
2786 sctx
->framebuffer
.dirty_cbufs
|=
2787 (1 << MAX2(sctx
->framebuffer
.state
.nr_cbufs
, state
->nr_cbufs
)) - 1;
2788 sctx
->framebuffer
.dirty_zsbuf
|= sctx
->framebuffer
.state
.zsbuf
!= state
->zsbuf
;
2790 si_dec_framebuffer_counters(&sctx
->framebuffer
.state
);
2791 util_copy_framebuffer_state(&sctx
->framebuffer
.state
, state
);
2793 sctx
->framebuffer
.colorbuf_enabled_4bit
= 0;
2794 sctx
->framebuffer
.spi_shader_col_format
= 0;
2795 sctx
->framebuffer
.spi_shader_col_format_alpha
= 0;
2796 sctx
->framebuffer
.spi_shader_col_format_blend
= 0;
2797 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
= 0;
2798 sctx
->framebuffer
.color_is_int8
= 0;
2799 sctx
->framebuffer
.color_is_int10
= 0;
2801 sctx
->framebuffer
.compressed_cb_mask
= 0;
2802 sctx
->framebuffer
.nr_samples
= util_framebuffer_get_num_samples(state
);
2803 sctx
->framebuffer
.log_samples
= util_logbase2(sctx
->framebuffer
.nr_samples
);
2804 sctx
->framebuffer
.any_dst_linear
= false;
2805 sctx
->framebuffer
.CB_has_shader_readable_metadata
= false;
2806 sctx
->framebuffer
.DB_has_shader_readable_metadata
= false;
2808 for (i
= 0; i
< state
->nr_cbufs
; i
++) {
2809 if (!state
->cbufs
[i
])
2812 surf
= (struct r600_surface
*)state
->cbufs
[i
];
2813 rtex
= (struct r600_texture
*)surf
->base
.texture
;
2815 if (!surf
->color_initialized
) {
2816 si_initialize_color_surface(sctx
, surf
);
2819 sctx
->framebuffer
.colorbuf_enabled_4bit
|= 0xf << (i
* 4);
2820 sctx
->framebuffer
.spi_shader_col_format
|=
2821 surf
->spi_shader_col_format
<< (i
* 4);
2822 sctx
->framebuffer
.spi_shader_col_format_alpha
|=
2823 surf
->spi_shader_col_format_alpha
<< (i
* 4);
2824 sctx
->framebuffer
.spi_shader_col_format_blend
|=
2825 surf
->spi_shader_col_format_blend
<< (i
* 4);
2826 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
|=
2827 surf
->spi_shader_col_format_blend_alpha
<< (i
* 4);
2829 if (surf
->color_is_int8
)
2830 sctx
->framebuffer
.color_is_int8
|= 1 << i
;
2831 if (surf
->color_is_int10
)
2832 sctx
->framebuffer
.color_is_int10
|= 1 << i
;
2834 if (rtex
->fmask
.size
) {
2835 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2838 if (rtex
->surface
.is_linear
)
2839 sctx
->framebuffer
.any_dst_linear
= true;
2841 if (vi_dcc_enabled(rtex
, surf
->base
.u
.tex
.level
))
2842 sctx
->framebuffer
.CB_has_shader_readable_metadata
= true;
2844 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2846 p_atomic_inc(&rtex
->framebuffers_bound
);
2848 if (rtex
->dcc_gather_statistics
) {
2849 /* Dirty tracking must be enabled for DCC usage analysis. */
2850 sctx
->framebuffer
.compressed_cb_mask
|= 1 << i
;
2851 vi_separate_dcc_start_query(ctx
, rtex
);
2855 struct r600_texture
*zstex
= NULL
;
2858 surf
= (struct r600_surface
*)state
->zsbuf
;
2859 zstex
= (struct r600_texture
*)surf
->base
.texture
;
2861 if (!surf
->depth_initialized
) {
2862 si_init_depth_surface(sctx
, surf
);
2865 if (vi_tc_compat_htile_enabled(zstex
, surf
->base
.u
.tex
.level
))
2866 sctx
->framebuffer
.DB_has_shader_readable_metadata
= true;
2868 r600_context_add_resource_size(ctx
, surf
->base
.texture
);
2871 si_update_poly_offset_state(sctx
);
2872 si_mark_atom_dirty(sctx
, &sctx
->cb_render_state
);
2873 si_mark_atom_dirty(sctx
, &sctx
->framebuffer
.atom
);
2875 if (sctx
->screen
->dpbb_allowed
)
2876 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
2878 if (sctx
->framebuffer
.any_dst_linear
!= old_any_dst_linear
)
2879 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2881 if (sctx
->screen
->has_out_of_order_rast
&&
2882 (sctx
->framebuffer
.colorbuf_enabled_4bit
!= old_colorbuf_enabled_4bit
||
2883 !!sctx
->framebuffer
.state
.zsbuf
!= old_has_zsbuf
||
2884 (zstex
&& zstex
->surface
.has_stencil
!= old_has_stencil
)))
2885 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2887 if (sctx
->framebuffer
.nr_samples
!= old_nr_samples
) {
2888 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
2889 si_mark_atom_dirty(sctx
, &sctx
->db_render_state
);
2891 /* Set sample locations as fragment shader constants. */
2892 switch (sctx
->framebuffer
.nr_samples
) {
2894 constbuf
.user_buffer
= sctx
->sample_locations_1x
;
2897 constbuf
.user_buffer
= sctx
->sample_locations_2x
;
2900 constbuf
.user_buffer
= sctx
->sample_locations_4x
;
2903 constbuf
.user_buffer
= sctx
->sample_locations_8x
;
2906 constbuf
.user_buffer
= sctx
->sample_locations_16x
;
2909 R600_ERR("Requested an invalid number of samples %i.\n",
2910 sctx
->framebuffer
.nr_samples
);
2913 constbuf
.buffer_size
= sctx
->framebuffer
.nr_samples
* 2 * 4;
2914 si_set_rw_buffer(sctx
, SI_PS_CONST_SAMPLE_POSITIONS
, &constbuf
);
2916 si_mark_atom_dirty(sctx
, &sctx
->msaa_sample_locs
.atom
);
2919 sctx
->do_update_shaders
= true;
2921 if (!sctx
->decompression_enabled
) {
2922 /* Prevent textures decompression when the framebuffer state
2923 * changes come from the decompression passes themselves.
2925 sctx
->need_check_render_feedback
= true;
2929 static void si_emit_framebuffer_state(struct si_context
*sctx
, struct r600_atom
*atom
)
2931 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
2932 struct pipe_framebuffer_state
*state
= &sctx
->framebuffer
.state
;
2933 unsigned i
, nr_cbufs
= state
->nr_cbufs
;
2934 struct r600_texture
*tex
= NULL
;
2935 struct r600_surface
*cb
= NULL
;
2936 unsigned cb_color_info
= 0;
2939 for (i
= 0; i
< nr_cbufs
; i
++) {
2940 uint64_t cb_color_base
, cb_color_fmask
, cb_dcc_base
;
2941 unsigned cb_color_attrib
;
2943 if (!(sctx
->framebuffer
.dirty_cbufs
& (1 << i
)))
2946 cb
= (struct r600_surface
*)state
->cbufs
[i
];
2948 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C,
2949 S_028C70_FORMAT(V_028C70_COLOR_INVALID
));
2953 tex
= (struct r600_texture
*)cb
->base
.texture
;
2954 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2955 &tex
->resource
, RADEON_USAGE_READWRITE
,
2956 tex
->resource
.b
.b
.nr_samples
> 1 ?
2957 RADEON_PRIO_COLOR_BUFFER_MSAA
:
2958 RADEON_PRIO_COLOR_BUFFER
);
2960 if (tex
->cmask_buffer
&& tex
->cmask_buffer
!= &tex
->resource
) {
2961 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2962 tex
->cmask_buffer
, RADEON_USAGE_READWRITE
,
2966 if (tex
->dcc_separate_buffer
)
2967 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
2968 tex
->dcc_separate_buffer
,
2969 RADEON_USAGE_READWRITE
,
2972 /* Compute mutable surface parameters. */
2973 cb_color_base
= tex
->resource
.gpu_address
>> 8;
2976 cb_color_info
= cb
->cb_color_info
| tex
->cb_color_info
;
2977 cb_color_attrib
= cb
->cb_color_attrib
;
2979 if (tex
->fmask
.size
) {
2980 cb_color_fmask
= (tex
->resource
.gpu_address
+ tex
->fmask
.offset
) >> 8;
2981 cb_color_fmask
|= tex
->fmask
.tile_swizzle
;
2985 if (vi_dcc_enabled(tex
, cb
->base
.u
.tex
.level
)) {
2986 bool is_msaa_resolve_dst
= state
->cbufs
[0] &&
2987 state
->cbufs
[0]->texture
->nr_samples
> 1 &&
2988 state
->cbufs
[1] == &cb
->base
&&
2989 state
->cbufs
[1]->texture
->nr_samples
<= 1;
2991 if (!is_msaa_resolve_dst
)
2992 cb_color_info
|= S_028C70_DCC_ENABLE(1);
2994 cb_dcc_base
= ((!tex
->dcc_separate_buffer
? tex
->resource
.gpu_address
: 0) +
2995 tex
->dcc_offset
) >> 8;
2996 cb_dcc_base
|= tex
->surface
.tile_swizzle
;
2999 if (sctx
->b
.chip_class
>= GFX9
) {
3000 struct gfx9_surf_meta_flags meta
;
3002 if (tex
->dcc_offset
)
3003 meta
= tex
->surface
.u
.gfx9
.dcc
;
3005 meta
= tex
->surface
.u
.gfx9
.cmask
;
3007 /* Set mutable surface parameters. */
3008 cb_color_base
+= tex
->surface
.u
.gfx9
.surf_offset
>> 8;
3009 cb_color_base
|= tex
->surface
.tile_swizzle
;
3010 if (!tex
->fmask
.size
)
3011 cb_color_fmask
= cb_color_base
;
3012 cb_color_attrib
|= S_028C74_COLOR_SW_MODE(tex
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3013 S_028C74_FMASK_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3014 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3015 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3017 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C, 15);
3018 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3019 radeon_emit(cs
, cb_color_base
>> 32); /* CB_COLOR0_BASE_EXT */
3020 radeon_emit(cs
, cb
->cb_color_attrib2
); /* CB_COLOR0_ATTRIB2 */
3021 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3022 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3023 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3024 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3025 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3026 radeon_emit(cs
, tex
->cmask
.base_address_reg
>> 32); /* CB_COLOR0_CMASK_BASE_EXT */
3027 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3028 radeon_emit(cs
, cb_color_fmask
>> 32); /* CB_COLOR0_FMASK_BASE_EXT */
3029 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3030 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3031 radeon_emit(cs
, cb_dcc_base
); /* CB_COLOR0_DCC_BASE */
3032 radeon_emit(cs
, cb_dcc_base
>> 32); /* CB_COLOR0_DCC_BASE_EXT */
3034 radeon_set_context_reg(cs
, R_0287A0_CB_MRT0_EPITCH
+ i
* 4,
3035 S_0287A0_EPITCH(tex
->surface
.u
.gfx9
.surf
.epitch
));
3037 /* Compute mutable surface parameters (SI-CI-VI). */
3038 const struct legacy_surf_level
*level_info
=
3039 &tex
->surface
.u
.legacy
.level
[cb
->base
.u
.tex
.level
];
3040 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3041 unsigned cb_color_pitch
, cb_color_slice
, cb_color_fmask_slice
;
3043 cb_color_base
+= level_info
->offset
>> 8;
3044 /* Only macrotiled modes can set tile swizzle. */
3045 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3046 cb_color_base
|= tex
->surface
.tile_swizzle
;
3048 if (!tex
->fmask
.size
)
3049 cb_color_fmask
= cb_color_base
;
3051 cb_dcc_base
+= level_info
->dcc_offset
>> 8;
3053 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3054 slice_tile_max
= level_info
->nblk_x
*
3055 level_info
->nblk_y
/ 64 - 1;
3056 tile_mode_index
= si_tile_mode_index(tex
, cb
->base
.u
.tex
.level
, false);
3058 cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3059 cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3060 cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3062 if (tex
->fmask
.size
) {
3063 if (sctx
->b
.chip_class
>= CIK
)
3064 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(tex
->fmask
.pitch_in_pixels
/ 8 - 1);
3065 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tex
->fmask
.tile_mode_index
);
3066 cb_color_fmask_slice
= S_028C88_TILE_MAX(tex
->fmask
.slice_tile_max
);
3068 /* This must be set for fast clear to work without FMASK. */
3069 if (sctx
->b
.chip_class
>= CIK
)
3070 cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3071 cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3072 cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3075 radeon_set_context_reg_seq(cs
, R_028C60_CB_COLOR0_BASE
+ i
* 0x3C,
3076 sctx
->b
.chip_class
>= VI
? 14 : 13);
3077 radeon_emit(cs
, cb_color_base
); /* CB_COLOR0_BASE */
3078 radeon_emit(cs
, cb_color_pitch
); /* CB_COLOR0_PITCH */
3079 radeon_emit(cs
, cb_color_slice
); /* CB_COLOR0_SLICE */
3080 radeon_emit(cs
, cb
->cb_color_view
); /* CB_COLOR0_VIEW */
3081 radeon_emit(cs
, cb_color_info
); /* CB_COLOR0_INFO */
3082 radeon_emit(cs
, cb_color_attrib
); /* CB_COLOR0_ATTRIB */
3083 radeon_emit(cs
, cb
->cb_dcc_control
); /* CB_COLOR0_DCC_CONTROL */
3084 radeon_emit(cs
, tex
->cmask
.base_address_reg
); /* CB_COLOR0_CMASK */
3085 radeon_emit(cs
, tex
->cmask
.slice_tile_max
); /* CB_COLOR0_CMASK_SLICE */
3086 radeon_emit(cs
, cb_color_fmask
); /* CB_COLOR0_FMASK */
3087 radeon_emit(cs
, cb_color_fmask_slice
); /* CB_COLOR0_FMASK_SLICE */
3088 radeon_emit(cs
, tex
->color_clear_value
[0]); /* CB_COLOR0_CLEAR_WORD0 */
3089 radeon_emit(cs
, tex
->color_clear_value
[1]); /* CB_COLOR0_CLEAR_WORD1 */
3091 if (sctx
->b
.chip_class
>= VI
) /* R_028C94_CB_COLOR0_DCC_BASE */
3092 radeon_emit(cs
, cb_dcc_base
);
3096 if (sctx
->framebuffer
.dirty_cbufs
& (1 << i
))
3097 radeon_set_context_reg(cs
, R_028C70_CB_COLOR0_INFO
+ i
* 0x3C, 0);
3100 if (state
->zsbuf
&& sctx
->framebuffer
.dirty_zsbuf
) {
3101 struct r600_surface
*zb
= (struct r600_surface
*)state
->zsbuf
;
3102 struct r600_texture
*rtex
= (struct r600_texture
*)zb
->base
.texture
;
3104 radeon_add_to_buffer_list(&sctx
->b
, &sctx
->b
.gfx
,
3105 &rtex
->resource
, RADEON_USAGE_READWRITE
,
3106 zb
->base
.texture
->nr_samples
> 1 ?
3107 RADEON_PRIO_DEPTH_BUFFER_MSAA
:
3108 RADEON_PRIO_DEPTH_BUFFER
);
3110 if (sctx
->b
.chip_class
>= GFX9
) {
3111 radeon_set_context_reg_seq(cs
, R_028014_DB_HTILE_DATA_BASE
, 3);
3112 radeon_emit(cs
, zb
->db_htile_data_base
); /* DB_HTILE_DATA_BASE */
3113 radeon_emit(cs
, zb
->db_htile_data_base
>> 32); /* DB_HTILE_DATA_BASE_HI */
3114 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3116 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 10);
3117 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3118 S_028038_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3119 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3120 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3121 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_READ_BASE_HI */
3122 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3123 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_READ_BASE_HI */
3124 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3125 radeon_emit(cs
, zb
->db_depth_base
>> 32); /* DB_Z_WRITE_BASE_HI */
3126 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3127 radeon_emit(cs
, zb
->db_stencil_base
>> 32); /* DB_STENCIL_WRITE_BASE_HI */
3129 radeon_set_context_reg_seq(cs
, R_028068_DB_Z_INFO2
, 2);
3130 radeon_emit(cs
, zb
->db_z_info2
); /* DB_Z_INFO2 */
3131 radeon_emit(cs
, zb
->db_stencil_info2
); /* DB_STENCIL_INFO2 */
3133 radeon_set_context_reg(cs
, R_028014_DB_HTILE_DATA_BASE
, zb
->db_htile_data_base
);
3135 radeon_set_context_reg_seq(cs
, R_02803C_DB_DEPTH_INFO
, 9);
3136 radeon_emit(cs
, zb
->db_depth_info
); /* DB_DEPTH_INFO */
3137 radeon_emit(cs
, zb
->db_z_info
| /* DB_Z_INFO */
3138 S_028040_ZRANGE_PRECISION(rtex
->depth_clear_value
!= 0));
3139 radeon_emit(cs
, zb
->db_stencil_info
); /* DB_STENCIL_INFO */
3140 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_READ_BASE */
3141 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_READ_BASE */
3142 radeon_emit(cs
, zb
->db_depth_base
); /* DB_Z_WRITE_BASE */
3143 radeon_emit(cs
, zb
->db_stencil_base
); /* DB_STENCIL_WRITE_BASE */
3144 radeon_emit(cs
, zb
->db_depth_size
); /* DB_DEPTH_SIZE */
3145 radeon_emit(cs
, zb
->db_depth_slice
); /* DB_DEPTH_SLICE */
3148 radeon_set_context_reg_seq(cs
, R_028028_DB_STENCIL_CLEAR
, 2);
3149 radeon_emit(cs
, rtex
->stencil_clear_value
); /* R_028028_DB_STENCIL_CLEAR */
3150 radeon_emit(cs
, fui(rtex
->depth_clear_value
)); /* R_02802C_DB_DEPTH_CLEAR */
3152 radeon_set_context_reg(cs
, R_028008_DB_DEPTH_VIEW
, zb
->db_depth_view
);
3153 radeon_set_context_reg(cs
, R_028ABC_DB_HTILE_SURFACE
, zb
->db_htile_surface
);
3154 } else if (sctx
->framebuffer
.dirty_zsbuf
) {
3155 if (sctx
->b
.chip_class
>= GFX9
)
3156 radeon_set_context_reg_seq(cs
, R_028038_DB_Z_INFO
, 2);
3158 radeon_set_context_reg_seq(cs
, R_028040_DB_Z_INFO
, 2);
3160 radeon_emit(cs
, S_028040_FORMAT(V_028040_Z_INVALID
)); /* DB_Z_INFO */
3161 radeon_emit(cs
, S_028044_FORMAT(V_028044_STENCIL_INVALID
)); /* DB_STENCIL_INFO */
3164 /* Framebuffer dimensions. */
3165 /* PA_SC_WINDOW_SCISSOR_TL is set in si_init_config() */
3166 radeon_set_context_reg(cs
, R_028208_PA_SC_WINDOW_SCISSOR_BR
,
3167 S_028208_BR_X(state
->width
) | S_028208_BR_Y(state
->height
));
3169 if (sctx
->screen
->dfsm_allowed
) {
3170 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3171 radeon_emit(cs
, EVENT_TYPE(V_028A90_BREAK_BATCH
) | EVENT_INDEX(0));
3174 sctx
->framebuffer
.dirty_cbufs
= 0;
3175 sctx
->framebuffer
.dirty_zsbuf
= false;
3178 static void si_emit_msaa_sample_locs(struct si_context
*sctx
,
3179 struct r600_atom
*atom
)
3181 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3182 unsigned nr_samples
= sctx
->framebuffer
.nr_samples
;
3183 bool has_msaa_sample_loc_bug
= sctx
->screen
->has_msaa_sample_loc_bug
;
3185 /* Smoothing (only possible with nr_samples == 1) uses the same
3186 * sample locations as the MSAA it simulates.
3188 if (nr_samples
<= 1 && sctx
->smoothing_enabled
)
3189 nr_samples
= SI_NUM_SMOOTH_AA_SAMPLES
;
3191 /* On Polaris, the small primitive filter uses the sample locations
3192 * even when MSAA is off, so we need to make sure they're set to 0.
3194 if (has_msaa_sample_loc_bug
)
3195 nr_samples
= MAX2(nr_samples
, 1);
3197 if (nr_samples
!= sctx
->msaa_sample_locs
.nr_samples
) {
3198 sctx
->msaa_sample_locs
.nr_samples
= nr_samples
;
3199 si_emit_sample_locations(cs
, nr_samples
);
3202 if (sctx
->b
.family
>= CHIP_POLARIS10
) {
3203 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3204 unsigned small_prim_filter_cntl
=
3205 S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
3207 S_028830_LINE_FILTER_DISABLE(sctx
->b
.family
<= CHIP_POLARIS12
);
3209 /* The alternative of setting sample locations to 0 would
3210 * require a DB flush to avoid Z errors, see
3211 * https://bugs.freedesktop.org/show_bug.cgi?id=96908
3213 if (has_msaa_sample_loc_bug
&&
3214 sctx
->framebuffer
.nr_samples
> 1 &&
3215 rs
&& !rs
->multisample_enable
)
3216 small_prim_filter_cntl
&= C_028830_SMALL_PRIM_FILTER_ENABLE
;
3218 radeon_set_context_reg(cs
, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL
,
3219 small_prim_filter_cntl
);
3223 static bool si_out_of_order_rasterization(struct si_context
*sctx
)
3225 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
3226 struct si_state_dsa
*dsa
= sctx
->queued
.named
.dsa
;
3228 if (!sctx
->screen
->has_out_of_order_rast
)
3231 unsigned colormask
= sctx
->framebuffer
.colorbuf_enabled_4bit
;
3234 colormask
&= blend
->cb_target_enabled_4bit
;
3239 /* Conservative: No logic op. */
3240 if (colormask
&& blend
->logicop_enable
)
3243 struct si_dsa_order_invariance dsa_order_invariant
= {
3244 .zs
= true, .pass_set
= true, .pass_last
= false
3247 if (sctx
->framebuffer
.state
.zsbuf
) {
3248 struct r600_texture
*zstex
=
3249 (struct r600_texture
*)sctx
->framebuffer
.state
.zsbuf
->texture
;
3250 bool has_stencil
= zstex
->surface
.has_stencil
;
3251 dsa_order_invariant
= dsa
->order_invariance
[has_stencil
];
3252 if (!dsa_order_invariant
.zs
)
3255 /* The set of PS invocations is always order invariant,
3256 * except when early Z/S tests are requested. */
3257 if (sctx
->ps_shader
.cso
&&
3258 sctx
->ps_shader
.cso
->info
.writes_memory
&&
3259 sctx
->ps_shader
.cso
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] &&
3260 !dsa_order_invariant
.pass_set
)
3263 if (sctx
->b
.num_perfect_occlusion_queries
!= 0 &&
3264 !dsa_order_invariant
.pass_set
)
3271 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
3274 /* Only commutative blending. */
3275 if (blendmask
& ~blend
->commutative_4bit
)
3278 if (!dsa_order_invariant
.pass_set
)
3282 if (colormask
& ~blendmask
) {
3283 if (!dsa_order_invariant
.pass_last
)
3290 static void si_emit_msaa_config(struct si_context
*sctx
, struct r600_atom
*atom
)
3292 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
3293 unsigned num_tile_pipes
= sctx
->screen
->b
.info
.num_tile_pipes
;
3294 /* 33% faster rendering to linear color buffers */
3295 bool dst_is_linear
= sctx
->framebuffer
.any_dst_linear
;
3296 bool out_of_order_rast
= si_out_of_order_rasterization(sctx
);
3297 unsigned sc_mode_cntl_1
=
3298 S_028A4C_WALK_SIZE(dst_is_linear
) |
3299 S_028A4C_WALK_FENCE_ENABLE(!dst_is_linear
) |
3300 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
3301 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
3302 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
3304 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
3305 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
3306 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
3307 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
3308 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
3309 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
3311 int setup_samples
= sctx
->framebuffer
.nr_samples
> 1 ? sctx
->framebuffer
.nr_samples
:
3312 sctx
->smoothing_enabled
? SI_NUM_SMOOTH_AA_SAMPLES
: 0;
3314 /* Required by OpenGL line rasterization.
3316 * TODO: We should also enable perpendicular endcaps for AA lines,
3317 * but that requires implementing line stippling in the pixel
3318 * shader. SC can only do line stippling with axis-aligned
3321 unsigned sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
3323 if (setup_samples
> 1) {
3324 /* distance from the pixel center, indexed by log2(nr_samples) */
3325 static unsigned max_dist
[] = {
3332 unsigned log_samples
= util_logbase2(setup_samples
);
3333 unsigned log_ps_iter_samples
=
3334 util_logbase2(util_next_power_of_two(sctx
->ps_iter_samples
));
3336 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3337 radeon_emit(cs
, sc_line_cntl
|
3338 S_028BDC_EXPAND_LINE_WIDTH(1)); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3339 radeon_emit(cs
, S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
3340 S_028BE0_MAX_SAMPLE_DIST(max_dist
[log_samples
]) |
3341 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
)); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3343 if (sctx
->framebuffer
.nr_samples
> 1) {
3344 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3345 S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
3346 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
3347 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
3348 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
) |
3349 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3350 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3351 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3352 S_028A4C_PS_ITER_SAMPLE(sctx
->ps_iter_samples
> 1) |
3354 } else if (sctx
->smoothing_enabled
) {
3355 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3356 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3357 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1) |
3358 S_028804_OVERRASTERIZATION_AMOUNT(log_samples
));
3359 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3363 radeon_set_context_reg_seq(cs
, R_028BDC_PA_SC_LINE_CNTL
, 2);
3364 radeon_emit(cs
, sc_line_cntl
); /* CM_R_028BDC_PA_SC_LINE_CNTL */
3365 radeon_emit(cs
, 0); /* CM_R_028BE0_PA_SC_AA_CONFIG */
3367 radeon_set_context_reg(cs
, R_028804_DB_EQAA
,
3368 S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
3369 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1));
3370 radeon_set_context_reg(cs
, R_028A4C_PA_SC_MODE_CNTL_1
,
3374 /* GFX9: Flush DFSM when the AA mode changes. */
3375 if (sctx
->screen
->dfsm_allowed
) {
3376 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3377 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3381 static void si_set_min_samples(struct pipe_context
*ctx
, unsigned min_samples
)
3383 struct si_context
*sctx
= (struct si_context
*)ctx
;
3385 if (sctx
->ps_iter_samples
== min_samples
)
3388 sctx
->ps_iter_samples
= min_samples
;
3389 sctx
->do_update_shaders
= true;
3391 if (sctx
->framebuffer
.nr_samples
> 1)
3392 si_mark_atom_dirty(sctx
, &sctx
->msaa_config
);
3393 if (sctx
->screen
->dpbb_allowed
)
3394 si_mark_atom_dirty(sctx
, &sctx
->dpbb_state
);
3402 * Build the sampler view descriptor for a buffer texture.
3403 * @param state 256-bit descriptor; only the high 128 bits are filled in
3406 si_make_buffer_descriptor(struct si_screen
*screen
, struct r600_resource
*buf
,
3407 enum pipe_format format
,
3408 unsigned offset
, unsigned size
,
3411 const struct util_format_description
*desc
;
3414 unsigned num_records
;
3415 unsigned num_format
, data_format
;
3417 desc
= util_format_description(format
);
3418 first_non_void
= util_format_get_first_non_void_channel(format
);
3419 stride
= desc
->block
.bits
/ 8;
3420 num_format
= si_translate_buffer_numformat(&screen
->b
.b
, desc
, first_non_void
);
3421 data_format
= si_translate_buffer_dataformat(&screen
->b
.b
, desc
, first_non_void
);
3423 num_records
= size
/ stride
;
3424 num_records
= MIN2(num_records
, (buf
->b
.b
.width0
- offset
) / stride
);
3426 /* The NUM_RECORDS field has a different meaning depending on the chip,
3427 * instruction type, STRIDE, and SWIZZLE_ENABLE.
3430 * - If STRIDE == 0, it's in byte units.
3431 * - If STRIDE != 0, it's in units of STRIDE, used with inst.IDXEN.
3434 * - For SMEM and STRIDE == 0, it's in byte units.
3435 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3436 * - For VMEM and STRIDE == 0 or SWIZZLE_ENABLE == 0, it's in byte units.
3437 * - For VMEM and STRIDE != 0 and SWIZZLE_ENABLE == 1, it's in units of STRIDE.
3438 * NOTE: There is incompatibility between VMEM and SMEM opcodes due to SWIZZLE_-
3439 * ENABLE. The workaround is to set STRIDE = 0 if SWIZZLE_ENABLE == 0 when
3440 * using SMEM. This can be done in the shader by clearing STRIDE with s_and.
3441 * That way the same descriptor can be used by both SMEM and VMEM.
3444 * - For SMEM and STRIDE == 0, it's in byte units.
3445 * - For SMEM and STRIDE != 0, it's in units of STRIDE.
3446 * - For VMEM and inst.IDXEN == 0 or STRIDE == 0, it's in byte units.
3447 * - For VMEM and inst.IDXEN == 1 and STRIDE != 0, it's in units of STRIDE.
3449 if (screen
->b
.chip_class
>= GFX9
)
3450 /* When vindex == 0, LLVM sets IDXEN = 0, thus changing units
3451 * from STRIDE to bytes. This works around it by setting
3452 * NUM_RECORDS to at least the size of one element, so that
3453 * the first element is readable when IDXEN == 0.
3455 * TODO: Fix this in LLVM, but do we need a new intrinsic where
3456 * IDXEN is enforced?
3458 num_records
= num_records
? MAX2(num_records
, stride
) : 0;
3459 else if (screen
->b
.chip_class
== VI
)
3460 num_records
*= stride
;
3463 state
[5] = S_008F04_STRIDE(stride
);
3464 state
[6] = num_records
;
3465 state
[7] = S_008F0C_DST_SEL_X(si_map_swizzle(desc
->swizzle
[0])) |
3466 S_008F0C_DST_SEL_Y(si_map_swizzle(desc
->swizzle
[1])) |
3467 S_008F0C_DST_SEL_Z(si_map_swizzle(desc
->swizzle
[2])) |
3468 S_008F0C_DST_SEL_W(si_map_swizzle(desc
->swizzle
[3])) |
3469 S_008F0C_NUM_FORMAT(num_format
) |
3470 S_008F0C_DATA_FORMAT(data_format
);
3473 static unsigned gfx9_border_color_swizzle(const unsigned char swizzle
[4])
3475 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3477 if (swizzle
[3] == PIPE_SWIZZLE_X
) {
3478 /* For the pre-defined border color values (white, opaque
3479 * black, transparent black), the only thing that matters is
3480 * that the alpha channel winds up in the correct place
3481 * (because the RGB channels are all the same) so either of
3482 * these enumerations will work.
3484 if (swizzle
[2] == PIPE_SWIZZLE_Y
)
3485 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
3487 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
3488 } else if (swizzle
[0] == PIPE_SWIZZLE_X
) {
3489 if (swizzle
[1] == PIPE_SWIZZLE_Y
)
3490 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
3492 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
3493 } else if (swizzle
[1] == PIPE_SWIZZLE_X
) {
3494 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
3495 } else if (swizzle
[2] == PIPE_SWIZZLE_X
) {
3496 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
3503 * Build the sampler view descriptor for a texture.
3506 si_make_texture_descriptor(struct si_screen
*screen
,
3507 struct r600_texture
*tex
,
3509 enum pipe_texture_target target
,
3510 enum pipe_format pipe_format
,
3511 const unsigned char state_swizzle
[4],
3512 unsigned first_level
, unsigned last_level
,
3513 unsigned first_layer
, unsigned last_layer
,
3514 unsigned width
, unsigned height
, unsigned depth
,
3516 uint32_t *fmask_state
)
3518 struct pipe_resource
*res
= &tex
->resource
.b
.b
;
3519 const struct util_format_description
*desc
;
3520 unsigned char swizzle
[4];
3522 unsigned num_format
, data_format
, type
;
3525 desc
= util_format_description(pipe_format
);
3527 if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_ZS
) {
3528 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
3529 const unsigned char swizzle_yyyy
[4] = {1, 1, 1, 1};
3530 const unsigned char swizzle_wwww
[4] = {3, 3, 3, 3};
3532 switch (pipe_format
) {
3533 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3534 case PIPE_FORMAT_X32_S8X24_UINT
:
3535 case PIPE_FORMAT_X8Z24_UNORM
:
3536 util_format_compose_swizzles(swizzle_yyyy
, state_swizzle
, swizzle
);
3538 case PIPE_FORMAT_X24S8_UINT
:
3540 * X24S8 is implemented as an 8_8_8_8 data format, to
3541 * fix texture gathers. This affects at least
3542 * GL45-CTS.texture_cube_map_array.sampling on VI.
3544 util_format_compose_swizzles(swizzle_wwww
, state_swizzle
, swizzle
);
3547 util_format_compose_swizzles(swizzle_xxxx
, state_swizzle
, swizzle
);
3550 util_format_compose_swizzles(desc
->swizzle
, state_swizzle
, swizzle
);
3553 first_non_void
= util_format_get_first_non_void_channel(pipe_format
);
3555 switch (pipe_format
) {
3556 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3557 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3560 if (first_non_void
< 0) {
3561 if (util_format_is_compressed(pipe_format
)) {
3562 switch (pipe_format
) {
3563 case PIPE_FORMAT_DXT1_SRGB
:
3564 case PIPE_FORMAT_DXT1_SRGBA
:
3565 case PIPE_FORMAT_DXT3_SRGBA
:
3566 case PIPE_FORMAT_DXT5_SRGBA
:
3567 case PIPE_FORMAT_BPTC_SRGBA
:
3568 case PIPE_FORMAT_ETC2_SRGB8
:
3569 case PIPE_FORMAT_ETC2_SRGB8A1
:
3570 case PIPE_FORMAT_ETC2_SRGBA8
:
3571 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3573 case PIPE_FORMAT_RGTC1_SNORM
:
3574 case PIPE_FORMAT_LATC1_SNORM
:
3575 case PIPE_FORMAT_RGTC2_SNORM
:
3576 case PIPE_FORMAT_LATC2_SNORM
:
3577 case PIPE_FORMAT_ETC2_R11_SNORM
:
3578 case PIPE_FORMAT_ETC2_RG11_SNORM
:
3579 /* implies float, so use SNORM/UNORM to determine
3580 whether data is signed or not */
3581 case PIPE_FORMAT_BPTC_RGB_FLOAT
:
3582 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3585 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3588 } else if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
) {
3589 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3591 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3593 } else if (desc
->colorspace
== UTIL_FORMAT_COLORSPACE_SRGB
) {
3594 num_format
= V_008F14_IMG_NUM_FORMAT_SRGB
;
3596 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3598 switch (desc
->channel
[first_non_void
].type
) {
3599 case UTIL_FORMAT_TYPE_FLOAT
:
3600 num_format
= V_008F14_IMG_NUM_FORMAT_FLOAT
;
3602 case UTIL_FORMAT_TYPE_SIGNED
:
3603 if (desc
->channel
[first_non_void
].normalized
)
3604 num_format
= V_008F14_IMG_NUM_FORMAT_SNORM
;
3605 else if (desc
->channel
[first_non_void
].pure_integer
)
3606 num_format
= V_008F14_IMG_NUM_FORMAT_SINT
;
3608 num_format
= V_008F14_IMG_NUM_FORMAT_SSCALED
;
3610 case UTIL_FORMAT_TYPE_UNSIGNED
:
3611 if (desc
->channel
[first_non_void
].normalized
)
3612 num_format
= V_008F14_IMG_NUM_FORMAT_UNORM
;
3613 else if (desc
->channel
[first_non_void
].pure_integer
)
3614 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3616 num_format
= V_008F14_IMG_NUM_FORMAT_USCALED
;
3621 data_format
= si_translate_texformat(&screen
->b
.b
, pipe_format
, desc
, first_non_void
);
3622 if (data_format
== ~0) {
3626 /* S8 with Z32 HTILE needs a special format. */
3627 if (screen
->b
.chip_class
>= GFX9
&&
3628 pipe_format
== PIPE_FORMAT_S8_UINT
&&
3629 tex
->tc_compatible_htile
)
3630 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
3633 (res
->target
== PIPE_TEXTURE_CUBE
||
3634 res
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
3635 (screen
->b
.chip_class
<= VI
&&
3636 res
->target
== PIPE_TEXTURE_3D
))) {
3637 /* For the purpose of shader images, treat cube maps and 3D
3638 * textures as 2D arrays. For 3D textures, the address
3639 * calculations for mipmaps are different, so we rely on the
3640 * caller to effectively disable mipmaps.
3642 type
= V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
3644 assert(res
->target
!= PIPE_TEXTURE_3D
|| (first_level
== 0 && last_level
== 0));
3646 type
= si_tex_dim(screen
, tex
, target
, res
->nr_samples
);
3649 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
3651 depth
= res
->array_size
;
3652 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
3653 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
3654 if (sampler
|| res
->target
!= PIPE_TEXTURE_3D
)
3655 depth
= res
->array_size
;
3656 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
3657 depth
= res
->array_size
/ 6;
3660 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
3661 S_008F14_NUM_FORMAT_GFX6(num_format
));
3662 state
[2] = (S_008F18_WIDTH(width
- 1) |
3663 S_008F18_HEIGHT(height
- 1) |
3664 S_008F18_PERF_MOD(4));
3665 state
[3] = (S_008F1C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
3666 S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
3667 S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
3668 S_008F1C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
3669 S_008F1C_BASE_LEVEL(res
->nr_samples
> 1 ?
3671 S_008F1C_LAST_LEVEL(res
->nr_samples
> 1 ?
3672 util_logbase2(res
->nr_samples
) :
3674 S_008F1C_TYPE(type
));
3676 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3680 if (screen
->b
.chip_class
>= GFX9
) {
3681 unsigned bc_swizzle
= gfx9_border_color_swizzle(desc
->swizzle
);
3683 /* Depth is the the last accessible layer on Gfx9.
3684 * The hw doesn't need to know the total number of layers.
3686 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
3687 state
[4] |= S_008F20_DEPTH(depth
- 1);
3689 state
[4] |= S_008F20_DEPTH(last_layer
);
3691 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
3692 state
[5] |= S_008F24_MAX_MIP(res
->nr_samples
> 1 ?
3693 util_logbase2(res
->nr_samples
) :
3694 tex
->resource
.b
.b
.last_level
);
3696 state
[3] |= S_008F1C_POW2_PAD(res
->last_level
> 0);
3697 state
[4] |= S_008F20_DEPTH(depth
- 1);
3698 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3701 if (tex
->dcc_offset
) {
3702 unsigned swap
= si_translate_colorswap(pipe_format
, false);
3704 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
3706 /* The last dword is unused by hw. The shader uses it to clear
3707 * bits in the first dword of sampler state.
3709 if (screen
->b
.chip_class
<= CIK
&& res
->nr_samples
<= 1) {
3710 if (first_level
== last_level
)
3711 state
[7] = C_008F30_MAX_ANISO_RATIO
;
3713 state
[7] = 0xffffffff;
3717 /* Initialize the sampler view for FMASK. */
3718 if (tex
->fmask
.size
) {
3719 uint32_t data_format
, num_format
;
3721 va
= tex
->resource
.gpu_address
+ tex
->fmask
.offset
;
3723 if (screen
->b
.chip_class
>= GFX9
) {
3724 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
3725 switch (res
->nr_samples
) {
3727 num_format
= V_008F14_IMG_FMASK_8_2_2
;
3730 num_format
= V_008F14_IMG_FMASK_8_4_4
;
3733 num_format
= V_008F14_IMG_FMASK_32_8_8
;
3736 unreachable("invalid nr_samples");
3739 switch (res
->nr_samples
) {
3741 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
3744 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
3747 data_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
3750 unreachable("invalid nr_samples");
3752 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
3755 fmask_state
[0] = (va
>> 8) | tex
->fmask
.tile_swizzle
;
3756 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
3757 S_008F14_DATA_FORMAT_GFX6(data_format
) |
3758 S_008F14_NUM_FORMAT_GFX6(num_format
);
3759 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
3760 S_008F18_HEIGHT(height
- 1);
3761 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
3762 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
3763 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
3764 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
3765 S_008F1C_TYPE(si_tex_dim(screen
, tex
, target
, 0));
3767 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
3771 if (screen
->b
.chip_class
>= GFX9
) {
3772 fmask_state
[3] |= S_008F1C_SW_MODE(tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
);
3773 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
3774 S_008F20_PITCH_GFX9(tex
->surface
.u
.gfx9
.fmask
.epitch
);
3775 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.pipe_aligned
) |
3776 S_008F24_META_RB_ALIGNED(tex
->surface
.u
.gfx9
.cmask
.rb_aligned
);
3778 fmask_state
[3] |= S_008F1C_TILING_INDEX(tex
->fmask
.tile_mode_index
);
3779 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
3780 S_008F20_PITCH_GFX6(tex
->fmask
.pitch_in_pixels
- 1);
3781 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
3787 * Create a sampler view.
3789 * @param ctx context
3790 * @param texture texture
3791 * @param state sampler view template
3792 * @param width0 width0 override (for compressed textures as int)
3793 * @param height0 height0 override (for compressed textures as int)
3794 * @param force_level set the base address to the level (for compressed textures)
3796 struct pipe_sampler_view
*
3797 si_create_sampler_view_custom(struct pipe_context
*ctx
,
3798 struct pipe_resource
*texture
,
3799 const struct pipe_sampler_view
*state
,
3800 unsigned width0
, unsigned height0
,
3801 unsigned force_level
)
3803 struct si_context
*sctx
= (struct si_context
*)ctx
;
3804 struct si_sampler_view
*view
= CALLOC_STRUCT(si_sampler_view
);
3805 struct r600_texture
*tmp
= (struct r600_texture
*)texture
;
3806 unsigned base_level
, first_level
, last_level
;
3807 unsigned char state_swizzle
[4];
3808 unsigned height
, depth
, width
;
3809 unsigned last_layer
= state
->u
.tex
.last_layer
;
3810 enum pipe_format pipe_format
;
3811 const struct legacy_surf_level
*surflevel
;
3816 /* initialize base object */
3817 view
->base
= *state
;
3818 view
->base
.texture
= NULL
;
3819 view
->base
.reference
.count
= 1;
3820 view
->base
.context
= ctx
;
3823 pipe_resource_reference(&view
->base
.texture
, texture
);
3825 if (state
->format
== PIPE_FORMAT_X24S8_UINT
||
3826 state
->format
== PIPE_FORMAT_S8X24_UINT
||
3827 state
->format
== PIPE_FORMAT_X32_S8X24_UINT
||
3828 state
->format
== PIPE_FORMAT_S8_UINT
)
3829 view
->is_stencil_sampler
= true;
3831 /* Buffer resource. */
3832 if (texture
->target
== PIPE_BUFFER
) {
3833 si_make_buffer_descriptor(sctx
->screen
,
3834 (struct r600_resource
*)texture
,
3836 state
->u
.buf
.offset
,
3842 state_swizzle
[0] = state
->swizzle_r
;
3843 state_swizzle
[1] = state
->swizzle_g
;
3844 state_swizzle
[2] = state
->swizzle_b
;
3845 state_swizzle
[3] = state
->swizzle_a
;
3848 first_level
= state
->u
.tex
.first_level
;
3849 last_level
= state
->u
.tex
.last_level
;
3852 depth
= texture
->depth0
;
3854 if (sctx
->b
.chip_class
<= VI
&& force_level
) {
3855 assert(force_level
== first_level
&&
3856 force_level
== last_level
);
3857 base_level
= force_level
;
3860 width
= u_minify(width
, force_level
);
3861 height
= u_minify(height
, force_level
);
3862 depth
= u_minify(depth
, force_level
);
3865 /* This is not needed if state trackers set last_layer correctly. */
3866 if (state
->target
== PIPE_TEXTURE_1D
||
3867 state
->target
== PIPE_TEXTURE_2D
||
3868 state
->target
== PIPE_TEXTURE_RECT
||
3869 state
->target
== PIPE_TEXTURE_CUBE
)
3870 last_layer
= state
->u
.tex
.first_layer
;
3872 /* Texturing with separate depth and stencil. */
3873 pipe_format
= state
->format
;
3875 /* Depth/stencil texturing sometimes needs separate texture. */
3876 if (tmp
->is_depth
&& !r600_can_sample_zs(tmp
, view
->is_stencil_sampler
)) {
3877 if (!tmp
->flushed_depth_texture
&&
3878 !si_init_flushed_depth_texture(ctx
, texture
, NULL
)) {
3879 pipe_resource_reference(&view
->base
.texture
, NULL
);
3884 assert(tmp
->flushed_depth_texture
);
3886 /* Override format for the case where the flushed texture
3887 * contains only Z or only S.
3889 if (tmp
->flushed_depth_texture
->resource
.b
.b
.format
!= tmp
->resource
.b
.b
.format
)
3890 pipe_format
= tmp
->flushed_depth_texture
->resource
.b
.b
.format
;
3892 tmp
= tmp
->flushed_depth_texture
;
3895 surflevel
= tmp
->surface
.u
.legacy
.level
;
3897 if (tmp
->db_compatible
) {
3898 if (!view
->is_stencil_sampler
)
3899 pipe_format
= tmp
->db_render_format
;
3901 switch (pipe_format
) {
3902 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
3903 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
3905 case PIPE_FORMAT_X8Z24_UNORM
:
3906 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
3907 /* Z24 is always stored like this for DB
3910 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
3912 case PIPE_FORMAT_X24S8_UINT
:
3913 case PIPE_FORMAT_S8X24_UINT
:
3914 case PIPE_FORMAT_X32_S8X24_UINT
:
3915 pipe_format
= PIPE_FORMAT_S8_UINT
;
3916 surflevel
= tmp
->surface
.u
.legacy
.stencil_level
;
3922 view
->dcc_incompatible
=
3923 vi_dcc_formats_are_incompatible(texture
,
3924 state
->u
.tex
.first_level
,
3927 si_make_texture_descriptor(sctx
->screen
, tmp
, true,
3928 state
->target
, pipe_format
, state_swizzle
,
3929 first_level
, last_level
,
3930 state
->u
.tex
.first_layer
, last_layer
,
3931 width
, height
, depth
,
3932 view
->state
, view
->fmask_state
);
3934 unsigned num_format
= G_008F14_NUM_FORMAT_GFX6(view
->state
[1]);
3936 num_format
== V_008F14_IMG_NUM_FORMAT_USCALED
||
3937 num_format
== V_008F14_IMG_NUM_FORMAT_SSCALED
||
3938 num_format
== V_008F14_IMG_NUM_FORMAT_UINT
||
3939 num_format
== V_008F14_IMG_NUM_FORMAT_SINT
;
3940 view
->base_level_info
= &surflevel
[base_level
];
3941 view
->base_level
= base_level
;
3942 view
->block_width
= util_format_get_blockwidth(pipe_format
);
3946 static struct pipe_sampler_view
*
3947 si_create_sampler_view(struct pipe_context
*ctx
,
3948 struct pipe_resource
*texture
,
3949 const struct pipe_sampler_view
*state
)
3951 return si_create_sampler_view_custom(ctx
, texture
, state
,
3952 texture
? texture
->width0
: 0,
3953 texture
? texture
->height0
: 0, 0);
3956 static void si_sampler_view_destroy(struct pipe_context
*ctx
,
3957 struct pipe_sampler_view
*state
)
3959 struct si_sampler_view
*view
= (struct si_sampler_view
*)state
;
3961 pipe_resource_reference(&state
->texture
, NULL
);
3965 static bool wrap_mode_uses_border_color(unsigned wrap
, bool linear_filter
)
3967 return wrap
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
3968 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER
||
3970 (wrap
== PIPE_TEX_WRAP_CLAMP
||
3971 wrap
== PIPE_TEX_WRAP_MIRROR_CLAMP
));
3974 static uint32_t si_translate_border_color(struct si_context
*sctx
,
3975 const struct pipe_sampler_state
*state
,
3976 const union pipe_color_union
*color
,
3979 bool linear_filter
= state
->min_img_filter
!= PIPE_TEX_FILTER_NEAREST
||
3980 state
->mag_img_filter
!= PIPE_TEX_FILTER_NEAREST
;
3982 if (!wrap_mode_uses_border_color(state
->wrap_s
, linear_filter
) &&
3983 !wrap_mode_uses_border_color(state
->wrap_t
, linear_filter
) &&
3984 !wrap_mode_uses_border_color(state
->wrap_r
, linear_filter
))
3985 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
3987 #define simple_border_types(elt) \
3989 if (color->elt[0] == 0 && color->elt[1] == 0 && \
3990 color->elt[2] == 0 && color->elt[3] == 0) \
3991 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK); \
3992 if (color->elt[0] == 0 && color->elt[1] == 0 && \
3993 color->elt[2] == 0 && color->elt[3] == 1) \
3994 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK); \
3995 if (color->elt[0] == 1 && color->elt[1] == 1 && \
3996 color->elt[2] == 1 && color->elt[3] == 1) \
3997 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE); \
4001 simple_border_types(ui
);
4003 simple_border_types(f
);
4005 #undef simple_border_types
4009 /* Check if the border has been uploaded already. */
4010 for (i
= 0; i
< sctx
->border_color_count
; i
++)
4011 if (memcmp(&sctx
->border_color_table
[i
], color
,
4012 sizeof(*color
)) == 0)
4015 if (i
>= SI_MAX_BORDER_COLORS
) {
4016 /* Getting 4096 unique border colors is very unlikely. */
4017 fprintf(stderr
, "radeonsi: The border color table is full. "
4018 "Any new border colors will be just black. "
4019 "Please file a bug.\n");
4020 return S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
);
4023 if (i
== sctx
->border_color_count
) {
4024 /* Upload a new border color. */
4025 memcpy(&sctx
->border_color_table
[i
], color
,
4027 util_memcpy_cpu_to_le32(&sctx
->border_color_map
[i
],
4028 color
, sizeof(*color
));
4029 sctx
->border_color_count
++;
4032 return S_008F3C_BORDER_COLOR_PTR(i
) |
4033 S_008F3C_BORDER_COLOR_TYPE(V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
);
4036 static void *si_create_sampler_state(struct pipe_context
*ctx
,
4037 const struct pipe_sampler_state
*state
)
4039 struct si_context
*sctx
= (struct si_context
*)ctx
;
4040 struct r600_common_screen
*rscreen
= sctx
->b
.screen
;
4041 struct si_sampler_state
*rstate
= CALLOC_STRUCT(si_sampler_state
);
4042 unsigned max_aniso
= rscreen
->force_aniso
>= 0 ? rscreen
->force_aniso
4043 : state
->max_anisotropy
;
4044 unsigned max_aniso_ratio
= r600_tex_aniso_filter(max_aniso
);
4045 union pipe_color_union clamped_border_color
;
4052 rstate
->magic
= SI_SAMPLER_STATE_MAGIC
;
4054 rstate
->val
[0] = (S_008F30_CLAMP_X(si_tex_wrap(state
->wrap_s
)) |
4055 S_008F30_CLAMP_Y(si_tex_wrap(state
->wrap_t
)) |
4056 S_008F30_CLAMP_Z(si_tex_wrap(state
->wrap_r
)) |
4057 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4058 S_008F30_DEPTH_COMPARE_FUNC(si_tex_compare(state
->compare_func
)) |
4059 S_008F30_FORCE_UNNORMALIZED(!state
->normalized_coords
) |
4060 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4061 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4062 S_008F30_DISABLE_CUBE_WRAP(!state
->seamless_cube_map
) |
4063 S_008F30_COMPAT_MODE(sctx
->b
.chip_class
>= VI
));
4064 rstate
->val
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(state
->min_lod
, 0, 15), 8)) |
4065 S_008F34_MAX_LOD(S_FIXED(CLAMP(state
->max_lod
, 0, 15), 8)) |
4066 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4067 rstate
->val
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(state
->lod_bias
, -16, 16), 8)) |
4068 S_008F38_XY_MAG_FILTER(eg_tex_filter(state
->mag_img_filter
, max_aniso
)) |
4069 S_008F38_XY_MIN_FILTER(eg_tex_filter(state
->min_img_filter
, max_aniso
)) |
4070 S_008F38_MIP_FILTER(si_tex_mipfilter(state
->min_mip_filter
)) |
4071 S_008F38_MIP_POINT_PRECLAMP(0) |
4072 S_008F38_DISABLE_LSB_CEIL(sctx
->b
.chip_class
<= VI
) |
4073 S_008F38_FILTER_PREC_FIX(1) |
4074 S_008F38_ANISO_OVERRIDE(sctx
->b
.chip_class
>= VI
));
4075 rstate
->val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, false);
4077 /* Create sampler resource for integer textures. */
4078 memcpy(rstate
->integer_val
, rstate
->val
, sizeof(rstate
->val
));
4079 rstate
->integer_val
[3] = si_translate_border_color(sctx
, state
, &state
->border_color
, true);
4081 /* Create sampler resource for upgraded depth textures. */
4082 memcpy(rstate
->upgraded_depth_val
, rstate
->val
, sizeof(rstate
->val
));
4084 for (unsigned i
= 0; i
< 4; ++i
) {
4085 /* Use channel 0 on purpose, so that we can use OPAQUE_WHITE
4086 * when the border color is 1.0. */
4087 clamped_border_color
.f
[i
] = CLAMP(state
->border_color
.f
[0], 0, 1);
4090 if (memcmp(&state
->border_color
, &clamped_border_color
, sizeof(clamped_border_color
)) == 0)
4091 rstate
->upgraded_depth_val
[3] |= S_008F3C_UPGRADED_DEPTH(1);
4093 rstate
->upgraded_depth_val
[3] =
4094 si_translate_border_color(sctx
, state
, &clamped_border_color
, false) |
4095 S_008F3C_UPGRADED_DEPTH(1);
4100 static void si_set_sample_mask(struct pipe_context
*ctx
, unsigned sample_mask
)
4102 struct si_context
*sctx
= (struct si_context
*)ctx
;
4104 if (sctx
->sample_mask
.sample_mask
== (uint16_t)sample_mask
)
4107 sctx
->sample_mask
.sample_mask
= sample_mask
;
4108 si_mark_atom_dirty(sctx
, &sctx
->sample_mask
.atom
);
4111 static void si_emit_sample_mask(struct si_context
*sctx
, struct r600_atom
*atom
)
4113 struct radeon_winsys_cs
*cs
= sctx
->b
.gfx
.cs
;
4114 unsigned mask
= sctx
->sample_mask
.sample_mask
;
4116 /* Needed for line and polygon smoothing as well as for the Polaris
4117 * small primitive filter. We expect the state tracker to take care of
4120 assert(mask
== 0xffff || sctx
->framebuffer
.nr_samples
> 1 ||
4121 (mask
& 1 && sctx
->blitter
->running
));
4123 radeon_set_context_reg_seq(cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
4124 radeon_emit(cs
, mask
| (mask
<< 16));
4125 radeon_emit(cs
, mask
| (mask
<< 16));
4128 static void si_delete_sampler_state(struct pipe_context
*ctx
, void *state
)
4131 struct si_sampler_state
*s
= state
;
4133 assert(s
->magic
== SI_SAMPLER_STATE_MAGIC
);
4140 * Vertex elements & buffers
4143 static void *si_create_vertex_elements(struct pipe_context
*ctx
,
4145 const struct pipe_vertex_element
*elements
)
4147 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
4148 struct si_vertex_elements
*v
= CALLOC_STRUCT(si_vertex_elements
);
4149 bool used
[SI_NUM_VERTEX_BUFFERS
] = {};
4152 assert(count
<= SI_MAX_ATTRIBS
);
4157 v
->desc_list_byte_size
= align(count
* 16, SI_CPDMA_ALIGNMENT
);
4159 for (i
= 0; i
< count
; ++i
) {
4160 const struct util_format_description
*desc
;
4161 const struct util_format_channel_description
*channel
;
4162 unsigned data_format
, num_format
;
4164 unsigned vbo_index
= elements
[i
].vertex_buffer_index
;
4165 unsigned char swizzle
[4];
4167 if (vbo_index
>= SI_NUM_VERTEX_BUFFERS
) {
4172 if (elements
[i
].instance_divisor
) {
4173 v
->uses_instance_divisors
= true;
4174 v
->instance_divisors
[i
] = elements
[i
].instance_divisor
;
4176 if (v
->instance_divisors
[i
] == 1)
4177 v
->instance_divisor_is_one
|= 1u << i
;
4179 v
->instance_divisor_is_fetched
|= 1u << i
;
4182 if (!used
[vbo_index
]) {
4183 v
->first_vb_use_mask
|= 1 << i
;
4184 used
[vbo_index
] = true;
4187 desc
= util_format_description(elements
[i
].src_format
);
4188 first_non_void
= util_format_get_first_non_void_channel(elements
[i
].src_format
);
4189 data_format
= si_translate_buffer_dataformat(ctx
->screen
, desc
, first_non_void
);
4190 num_format
= si_translate_buffer_numformat(ctx
->screen
, desc
, first_non_void
);
4191 channel
= first_non_void
>= 0 ? &desc
->channel
[first_non_void
] : NULL
;
4192 memcpy(swizzle
, desc
->swizzle
, sizeof(swizzle
));
4194 v
->format_size
[i
] = desc
->block
.bits
/ 8;
4195 v
->src_offset
[i
] = elements
[i
].src_offset
;
4196 v
->vertex_buffer_index
[i
] = vbo_index
;
4198 /* The hardware always treats the 2-bit alpha channel as
4199 * unsigned, so a shader workaround is needed. The affected
4200 * chips are VI and older except Stoney (GFX8.1).
4202 if (data_format
== V_008F0C_BUF_DATA_FORMAT_2_10_10_10
&&
4203 sscreen
->b
.chip_class
<= VI
&&
4204 sscreen
->b
.family
!= CHIP_STONEY
) {
4205 if (num_format
== V_008F0C_BUF_NUM_FORMAT_SNORM
) {
4206 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SNORM
;
4207 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SSCALED
) {
4208 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SSCALED
;
4209 } else if (num_format
== V_008F0C_BUF_NUM_FORMAT_SINT
) {
4210 /* This isn't actually used in OpenGL. */
4211 v
->fix_fetch
[i
] = SI_FIX_FETCH_A2_SINT
;
4213 } else if (channel
&& channel
->type
== UTIL_FORMAT_TYPE_FIXED
) {
4214 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4215 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_FIXED
;
4217 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_FIXED
;
4218 } else if (channel
&& channel
->size
== 32 && !channel
->pure_integer
) {
4219 if (channel
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
4220 if (channel
->normalized
) {
4221 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4222 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_SNORM
;
4224 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SNORM
;
4226 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_SSCALED
;
4228 } else if (channel
->type
== UTIL_FORMAT_TYPE_UNSIGNED
) {
4229 if (channel
->normalized
) {
4230 if (desc
->swizzle
[3] == PIPE_SWIZZLE_1
)
4231 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBX_32_UNORM
;
4233 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_UNORM
;
4235 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_32_USCALED
;
4238 } else if (channel
&& channel
->size
== 64 &&
4239 channel
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
4240 switch (desc
->nr_channels
) {
4243 v
->fix_fetch
[i
] = SI_FIX_FETCH_RG_64_FLOAT
;
4244 swizzle
[0] = PIPE_SWIZZLE_X
;
4245 swizzle
[1] = PIPE_SWIZZLE_Y
;
4246 swizzle
[2] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_Z
: PIPE_SWIZZLE_0
;
4247 swizzle
[3] = desc
->nr_channels
== 2 ? PIPE_SWIZZLE_W
: PIPE_SWIZZLE_0
;
4250 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_64_FLOAT
;
4251 swizzle
[0] = PIPE_SWIZZLE_X
; /* 3 loads */
4252 swizzle
[1] = PIPE_SWIZZLE_Y
;
4253 swizzle
[2] = PIPE_SWIZZLE_0
;
4254 swizzle
[3] = PIPE_SWIZZLE_0
;
4257 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGBA_64_FLOAT
;
4258 swizzle
[0] = PIPE_SWIZZLE_X
; /* 2 loads */
4259 swizzle
[1] = PIPE_SWIZZLE_Y
;
4260 swizzle
[2] = PIPE_SWIZZLE_Z
;
4261 swizzle
[3] = PIPE_SWIZZLE_W
;
4266 } else if (channel
&& desc
->nr_channels
== 3) {
4267 assert(desc
->swizzle
[0] == PIPE_SWIZZLE_X
);
4269 if (channel
->size
== 8) {
4270 if (channel
->pure_integer
)
4271 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8_INT
;
4273 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_8
;
4274 } else if (channel
->size
== 16) {
4275 if (channel
->pure_integer
)
4276 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16_INT
;
4278 v
->fix_fetch
[i
] = SI_FIX_FETCH_RGB_16
;
4282 v
->rsrc_word3
[i
] = S_008F0C_DST_SEL_X(si_map_swizzle(swizzle
[0])) |
4283 S_008F0C_DST_SEL_Y(si_map_swizzle(swizzle
[1])) |
4284 S_008F0C_DST_SEL_Z(si_map_swizzle(swizzle
[2])) |
4285 S_008F0C_DST_SEL_W(si_map_swizzle(swizzle
[3])) |
4286 S_008F0C_NUM_FORMAT(num_format
) |
4287 S_008F0C_DATA_FORMAT(data_format
);
4292 static void si_bind_vertex_elements(struct pipe_context
*ctx
, void *state
)
4294 struct si_context
*sctx
= (struct si_context
*)ctx
;
4295 struct si_vertex_elements
*old
= sctx
->vertex_elements
;
4296 struct si_vertex_elements
*v
= (struct si_vertex_elements
*)state
;
4298 sctx
->vertex_elements
= v
;
4299 sctx
->vertex_buffers_dirty
= true;
4303 old
->count
!= v
->count
||
4304 old
->uses_instance_divisors
!= v
->uses_instance_divisors
||
4305 v
->uses_instance_divisors
|| /* we don't check which divisors changed */
4306 memcmp(old
->fix_fetch
, v
->fix_fetch
, sizeof(v
->fix_fetch
[0]) * v
->count
)))
4307 sctx
->do_update_shaders
= true;
4309 if (v
&& v
->instance_divisor_is_fetched
) {
4310 struct pipe_constant_buffer cb
;
4313 cb
.user_buffer
= v
->instance_divisors
;
4314 cb
.buffer_offset
= 0;
4315 cb
.buffer_size
= sizeof(uint32_t) * v
->count
;
4316 si_set_rw_buffer(sctx
, SI_VS_CONST_INSTANCE_DIVISORS
, &cb
);
4320 static void si_delete_vertex_element(struct pipe_context
*ctx
, void *state
)
4322 struct si_context
*sctx
= (struct si_context
*)ctx
;
4324 if (sctx
->vertex_elements
== state
)
4325 sctx
->vertex_elements
= NULL
;
4329 static void si_set_vertex_buffers(struct pipe_context
*ctx
,
4330 unsigned start_slot
, unsigned count
,
4331 const struct pipe_vertex_buffer
*buffers
)
4333 struct si_context
*sctx
= (struct si_context
*)ctx
;
4334 struct pipe_vertex_buffer
*dst
= sctx
->vertex_buffer
+ start_slot
;
4337 assert(start_slot
+ count
<= ARRAY_SIZE(sctx
->vertex_buffer
));
4340 for (i
= 0; i
< count
; i
++) {
4341 const struct pipe_vertex_buffer
*src
= buffers
+ i
;
4342 struct pipe_vertex_buffer
*dsti
= dst
+ i
;
4343 struct pipe_resource
*buf
= src
->buffer
.resource
;
4345 pipe_resource_reference(&dsti
->buffer
.resource
, buf
);
4346 dsti
->buffer_offset
= src
->buffer_offset
;
4347 dsti
->stride
= src
->stride
;
4348 r600_context_add_resource_size(ctx
, buf
);
4350 r600_resource(buf
)->bind_history
|= PIPE_BIND_VERTEX_BUFFER
;
4353 for (i
= 0; i
< count
; i
++) {
4354 pipe_resource_reference(&dst
[i
].buffer
.resource
, NULL
);
4357 sctx
->vertex_buffers_dirty
= true;
4364 static void si_set_tess_state(struct pipe_context
*ctx
,
4365 const float default_outer_level
[4],
4366 const float default_inner_level
[2])
4368 struct si_context
*sctx
= (struct si_context
*)ctx
;
4369 struct pipe_constant_buffer cb
;
4372 memcpy(array
, default_outer_level
, sizeof(float) * 4);
4373 memcpy(array
+4, default_inner_level
, sizeof(float) * 2);
4376 cb
.user_buffer
= NULL
;
4377 cb
.buffer_size
= sizeof(array
);
4379 si_upload_const_buffer(sctx
, (struct r600_resource
**)&cb
.buffer
,
4380 (void*)array
, sizeof(array
),
4383 si_set_rw_buffer(sctx
, SI_HS_CONST_DEFAULT_TESS_LEVELS
, &cb
);
4384 pipe_resource_reference(&cb
.buffer
, NULL
);
4387 static void si_texture_barrier(struct pipe_context
*ctx
, unsigned flags
)
4389 struct si_context
*sctx
= (struct si_context
*)ctx
;
4391 si_update_fb_dirtiness_after_rendering(sctx
);
4393 /* Multisample surfaces are flushed in si_decompress_textures. */
4394 if (sctx
->framebuffer
.nr_samples
<= 1 &&
4395 sctx
->framebuffer
.state
.nr_cbufs
)
4396 si_make_CB_shader_coherent(sctx
, sctx
->framebuffer
.nr_samples
,
4397 sctx
->framebuffer
.CB_has_shader_readable_metadata
);
4400 /* This only ensures coherency for shader image/buffer stores. */
4401 static void si_memory_barrier(struct pipe_context
*ctx
, unsigned flags
)
4403 struct si_context
*sctx
= (struct si_context
*)ctx
;
4405 /* Subsequent commands must wait for all shader invocations to
4407 sctx
->b
.flags
|= SI_CONTEXT_PS_PARTIAL_FLUSH
|
4408 SI_CONTEXT_CS_PARTIAL_FLUSH
;
4410 if (flags
& PIPE_BARRIER_CONSTANT_BUFFER
)
4411 sctx
->b
.flags
|= SI_CONTEXT_INV_SMEM_L1
|
4412 SI_CONTEXT_INV_VMEM_L1
;
4414 if (flags
& (PIPE_BARRIER_VERTEX_BUFFER
|
4415 PIPE_BARRIER_SHADER_BUFFER
|
4416 PIPE_BARRIER_TEXTURE
|
4417 PIPE_BARRIER_IMAGE
|
4418 PIPE_BARRIER_STREAMOUT_BUFFER
|
4419 PIPE_BARRIER_GLOBAL_BUFFER
)) {
4420 /* As far as I can tell, L1 contents are written back to L2
4421 * automatically at end of shader, but the contents of other
4422 * L1 caches might still be stale. */
4423 sctx
->b
.flags
|= SI_CONTEXT_INV_VMEM_L1
;
4426 if (flags
& PIPE_BARRIER_INDEX_BUFFER
) {
4427 /* Indices are read through TC L2 since VI.
4430 if (sctx
->screen
->b
.chip_class
<= CIK
)
4431 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4434 /* MSAA color, any depth and any stencil are flushed in
4435 * si_decompress_textures when needed.
4437 if (flags
& PIPE_BARRIER_FRAMEBUFFER
&&
4438 sctx
->framebuffer
.nr_samples
<= 1 &&
4439 sctx
->framebuffer
.state
.nr_cbufs
) {
4440 sctx
->b
.flags
|= SI_CONTEXT_FLUSH_AND_INV_CB
;
4442 if (sctx
->b
.chip_class
<= VI
)
4443 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4446 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
4447 if (sctx
->screen
->b
.chip_class
<= VI
&&
4448 flags
& PIPE_BARRIER_INDIRECT_BUFFER
)
4449 sctx
->b
.flags
|= SI_CONTEXT_WRITEBACK_GLOBAL_L2
;
4452 static void *si_create_blend_custom(struct si_context
*sctx
, unsigned mode
)
4454 struct pipe_blend_state blend
;
4456 memset(&blend
, 0, sizeof(blend
));
4457 blend
.independent_blend_enable
= true;
4458 blend
.rt
[0].colormask
= 0xf;
4459 return si_create_blend_state_mode(&sctx
->b
.b
, &blend
, mode
);
4462 static void si_need_gfx_cs_space(struct pipe_context
*ctx
, unsigned num_dw
,
4463 bool include_draw_vbo
)
4465 si_need_cs_space((struct si_context
*)ctx
);
4468 static void si_init_config(struct si_context
*sctx
);
4470 void si_init_state_functions(struct si_context
*sctx
)
4472 si_init_external_atom(sctx
, &sctx
->b
.render_cond_atom
, &sctx
->atoms
.s
.render_cond
);
4473 si_init_external_atom(sctx
, &sctx
->streamout
.begin_atom
, &sctx
->atoms
.s
.streamout_begin
);
4474 si_init_external_atom(sctx
, &sctx
->streamout
.enable_atom
, &sctx
->atoms
.s
.streamout_enable
);
4475 si_init_external_atom(sctx
, &sctx
->scissors
.atom
, &sctx
->atoms
.s
.scissors
);
4476 si_init_external_atom(sctx
, &sctx
->viewports
.atom
, &sctx
->atoms
.s
.viewports
);
4478 si_init_atom(sctx
, &sctx
->framebuffer
.atom
, &sctx
->atoms
.s
.framebuffer
, si_emit_framebuffer_state
);
4479 si_init_atom(sctx
, &sctx
->msaa_sample_locs
.atom
, &sctx
->atoms
.s
.msaa_sample_locs
, si_emit_msaa_sample_locs
);
4480 si_init_atom(sctx
, &sctx
->db_render_state
, &sctx
->atoms
.s
.db_render_state
, si_emit_db_render_state
);
4481 si_init_atom(sctx
, &sctx
->dpbb_state
, &sctx
->atoms
.s
.dpbb_state
, si_emit_dpbb_state
);
4482 si_init_atom(sctx
, &sctx
->msaa_config
, &sctx
->atoms
.s
.msaa_config
, si_emit_msaa_config
);
4483 si_init_atom(sctx
, &sctx
->sample_mask
.atom
, &sctx
->atoms
.s
.sample_mask
, si_emit_sample_mask
);
4484 si_init_atom(sctx
, &sctx
->cb_render_state
, &sctx
->atoms
.s
.cb_render_state
, si_emit_cb_render_state
);
4485 si_init_atom(sctx
, &sctx
->blend_color
.atom
, &sctx
->atoms
.s
.blend_color
, si_emit_blend_color
);
4486 si_init_atom(sctx
, &sctx
->clip_regs
, &sctx
->atoms
.s
.clip_regs
, si_emit_clip_regs
);
4487 si_init_atom(sctx
, &sctx
->clip_state
.atom
, &sctx
->atoms
.s
.clip_state
, si_emit_clip_state
);
4488 si_init_atom(sctx
, &sctx
->stencil_ref
.atom
, &sctx
->atoms
.s
.stencil_ref
, si_emit_stencil_ref
);
4490 sctx
->b
.b
.create_blend_state
= si_create_blend_state
;
4491 sctx
->b
.b
.bind_blend_state
= si_bind_blend_state
;
4492 sctx
->b
.b
.delete_blend_state
= si_delete_blend_state
;
4493 sctx
->b
.b
.set_blend_color
= si_set_blend_color
;
4495 sctx
->b
.b
.create_rasterizer_state
= si_create_rs_state
;
4496 sctx
->b
.b
.bind_rasterizer_state
= si_bind_rs_state
;
4497 sctx
->b
.b
.delete_rasterizer_state
= si_delete_rs_state
;
4499 sctx
->b
.b
.create_depth_stencil_alpha_state
= si_create_dsa_state
;
4500 sctx
->b
.b
.bind_depth_stencil_alpha_state
= si_bind_dsa_state
;
4501 sctx
->b
.b
.delete_depth_stencil_alpha_state
= si_delete_dsa_state
;
4503 sctx
->custom_dsa_flush
= si_create_db_flush_dsa(sctx
);
4504 sctx
->custom_blend_resolve
= si_create_blend_custom(sctx
, V_028808_CB_RESOLVE
);
4505 sctx
->custom_blend_fmask_decompress
= si_create_blend_custom(sctx
, V_028808_CB_FMASK_DECOMPRESS
);
4506 sctx
->custom_blend_eliminate_fastclear
= si_create_blend_custom(sctx
, V_028808_CB_ELIMINATE_FAST_CLEAR
);
4507 sctx
->custom_blend_dcc_decompress
= si_create_blend_custom(sctx
, V_028808_CB_DCC_DECOMPRESS
);
4509 sctx
->b
.b
.set_clip_state
= si_set_clip_state
;
4510 sctx
->b
.b
.set_stencil_ref
= si_set_stencil_ref
;
4512 sctx
->b
.b
.set_framebuffer_state
= si_set_framebuffer_state
;
4514 sctx
->b
.b
.create_sampler_state
= si_create_sampler_state
;
4515 sctx
->b
.b
.delete_sampler_state
= si_delete_sampler_state
;
4517 sctx
->b
.b
.create_sampler_view
= si_create_sampler_view
;
4518 sctx
->b
.b
.sampler_view_destroy
= si_sampler_view_destroy
;
4520 sctx
->b
.b
.set_sample_mask
= si_set_sample_mask
;
4522 sctx
->b
.b
.create_vertex_elements_state
= si_create_vertex_elements
;
4523 sctx
->b
.b
.bind_vertex_elements_state
= si_bind_vertex_elements
;
4524 sctx
->b
.b
.delete_vertex_elements_state
= si_delete_vertex_element
;
4525 sctx
->b
.b
.set_vertex_buffers
= si_set_vertex_buffers
;
4527 sctx
->b
.b
.texture_barrier
= si_texture_barrier
;
4528 sctx
->b
.b
.memory_barrier
= si_memory_barrier
;
4529 sctx
->b
.b
.set_min_samples
= si_set_min_samples
;
4530 sctx
->b
.b
.set_tess_state
= si_set_tess_state
;
4532 sctx
->b
.b
.set_active_query_state
= si_set_active_query_state
;
4533 sctx
->b
.set_occlusion_query_state
= si_set_occlusion_query_state
;
4534 sctx
->b
.save_qbo_state
= si_save_qbo_state
;
4535 sctx
->b
.need_gfx_cs_space
= si_need_gfx_cs_space
;
4537 sctx
->b
.b
.draw_vbo
= si_draw_vbo
;
4539 si_init_config(sctx
);
4542 static uint32_t si_get_bo_metadata_word1(struct r600_common_screen
*rscreen
)
4544 return (ATI_VENDOR_ID
<< 16) | rscreen
->info
.pci_id
;
4547 static void si_query_opaque_metadata(struct r600_common_screen
*rscreen
,
4548 struct r600_texture
*rtex
,
4549 struct radeon_bo_metadata
*md
)
4551 struct si_screen
*sscreen
= (struct si_screen
*)rscreen
;
4552 struct pipe_resource
*res
= &rtex
->resource
.b
.b
;
4553 static const unsigned char swizzle
[] = {
4559 uint32_t desc
[8], i
;
4560 bool is_array
= util_resource_is_array_texture(res
);
4562 /* DRM 2.x.x doesn't support this. */
4563 if (rscreen
->info
.drm_major
!= 3)
4566 assert(rtex
->dcc_separate_buffer
== NULL
);
4567 assert(rtex
->fmask
.size
== 0);
4569 /* Metadata image format format version 1:
4570 * [0] = 1 (metadata format identifier)
4571 * [1] = (VENDOR_ID << 16) | PCI_ID
4572 * [2:9] = image descriptor for the whole resource
4573 * [2] is always 0, because the base address is cleared
4574 * [9] is the DCC offset bits [39:8] from the beginning of
4576 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
4579 md
->metadata
[0] = 1; /* metadata image format version 1 */
4581 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
4582 md
->metadata
[1] = si_get_bo_metadata_word1(rscreen
);
4584 si_make_texture_descriptor(sscreen
, rtex
, true,
4585 res
->target
, res
->format
,
4586 swizzle
, 0, res
->last_level
, 0,
4587 is_array
? res
->array_size
- 1 : 0,
4588 res
->width0
, res
->height0
, res
->depth0
,
4591 si_set_mutable_tex_desc_fields(sscreen
, rtex
, &rtex
->surface
.u
.legacy
.level
[0],
4592 0, 0, rtex
->surface
.blk_w
, false, desc
);
4594 /* Clear the base address and set the relative DCC offset. */
4596 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
4597 desc
[7] = rtex
->dcc_offset
>> 8;
4599 /* Dwords [2:9] contain the image descriptor. */
4600 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
4601 md
->size_metadata
= 10 * 4;
4603 /* Dwords [10:..] contain the mipmap level offsets. */
4604 if (rscreen
->chip_class
<= VI
) {
4605 for (i
= 0; i
<= res
->last_level
; i
++)
4606 md
->metadata
[10+i
] = rtex
->surface
.u
.legacy
.level
[i
].offset
>> 8;
4608 md
->size_metadata
+= (1 + res
->last_level
) * 4;
4612 static void si_apply_opaque_metadata(struct r600_common_screen
*rscreen
,
4613 struct r600_texture
*rtex
,
4614 struct radeon_bo_metadata
*md
)
4616 uint32_t *desc
= &md
->metadata
[2];
4618 if (rscreen
->chip_class
< VI
)
4621 /* Return if DCC is enabled. The texture should be set up with it
4624 if (md
->size_metadata
>= 11 * 4 &&
4625 md
->metadata
[0] != 0 &&
4626 md
->metadata
[1] == si_get_bo_metadata_word1(rscreen
) &&
4627 G_008F28_COMPRESSION_EN(desc
[6])) {
4628 assert(rtex
->dcc_offset
== ((uint64_t)desc
[7] << 8));
4632 /* Disable DCC. These are always set by texture_from_handle and must
4635 rtex
->dcc_offset
= 0;
4638 void si_init_screen_state_functions(struct si_screen
*sscreen
)
4640 sscreen
->b
.b
.is_format_supported
= si_is_format_supported
;
4641 sscreen
->b
.query_opaque_metadata
= si_query_opaque_metadata
;
4642 sscreen
->b
.apply_opaque_metadata
= si_apply_opaque_metadata
;
4645 static void si_set_grbm_gfx_index(struct si_context
*sctx
,
4646 struct si_pm4_state
*pm4
, unsigned value
)
4648 unsigned reg
= sctx
->b
.chip_class
>= CIK
? R_030800_GRBM_GFX_INDEX
:
4650 si_pm4_set_reg(pm4
, reg
, value
);
4653 static void si_set_grbm_gfx_index_se(struct si_context
*sctx
,
4654 struct si_pm4_state
*pm4
, unsigned se
)
4656 assert(se
== ~0 || se
< sctx
->screen
->b
.info
.max_se
);
4657 si_set_grbm_gfx_index(sctx
, pm4
,
4658 (se
== ~0 ? S_030800_SE_BROADCAST_WRITES(1) :
4659 S_030800_SE_INDEX(se
)) |
4660 S_030800_SH_BROADCAST_WRITES(1) |
4661 S_030800_INSTANCE_BROADCAST_WRITES(1));
4665 si_write_harvested_raster_configs(struct si_context
*sctx
,
4666 struct si_pm4_state
*pm4
,
4667 unsigned raster_config
,
4668 unsigned raster_config_1
)
4670 unsigned sh_per_se
= MAX2(sctx
->screen
->b
.info
.max_sh_per_se
, 1);
4671 unsigned num_se
= MAX2(sctx
->screen
->b
.info
.max_se
, 1);
4672 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4673 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4674 unsigned rb_per_pkr
= MIN2(num_rb
/ num_se
/ sh_per_se
, 2);
4675 unsigned rb_per_se
= num_rb
/ num_se
;
4676 unsigned se_mask
[4];
4679 se_mask
[0] = ((1 << rb_per_se
) - 1);
4680 se_mask
[1] = (se_mask
[0] << rb_per_se
);
4681 se_mask
[2] = (se_mask
[1] << rb_per_se
);
4682 se_mask
[3] = (se_mask
[2] << rb_per_se
);
4684 se_mask
[0] &= rb_mask
;
4685 se_mask
[1] &= rb_mask
;
4686 se_mask
[2] &= rb_mask
;
4687 se_mask
[3] &= rb_mask
;
4689 assert(num_se
== 1 || num_se
== 2 || num_se
== 4);
4690 assert(sh_per_se
== 1 || sh_per_se
== 2);
4691 assert(rb_per_pkr
== 1 || rb_per_pkr
== 2);
4693 /* XXX: I can't figure out what the *_XSEL and *_YSEL
4694 * fields are for, so I'm leaving them as their default
4697 for (se
= 0; se
< num_se
; se
++) {
4698 unsigned raster_config_se
= raster_config
;
4699 unsigned pkr0_mask
= ((1 << rb_per_pkr
) - 1) << (se
* rb_per_se
);
4700 unsigned pkr1_mask
= pkr0_mask
<< rb_per_pkr
;
4701 int idx
= (se
/ 2) * 2;
4703 if ((num_se
> 1) && (!se_mask
[idx
] || !se_mask
[idx
+ 1])) {
4704 raster_config_se
&= C_028350_SE_MAP
;
4706 if (!se_mask
[idx
]) {
4708 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_3
);
4711 S_028350_SE_MAP(V_028350_RASTER_CONFIG_SE_MAP_0
);
4715 pkr0_mask
&= rb_mask
;
4716 pkr1_mask
&= rb_mask
;
4717 if (rb_per_se
> 2 && (!pkr0_mask
|| !pkr1_mask
)) {
4718 raster_config_se
&= C_028350_PKR_MAP
;
4722 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_3
);
4725 S_028350_PKR_MAP(V_028350_RASTER_CONFIG_PKR_MAP_0
);
4729 if (rb_per_se
>= 2) {
4730 unsigned rb0_mask
= 1 << (se
* rb_per_se
);
4731 unsigned rb1_mask
= rb0_mask
<< 1;
4733 rb0_mask
&= rb_mask
;
4734 rb1_mask
&= rb_mask
;
4735 if (!rb0_mask
|| !rb1_mask
) {
4736 raster_config_se
&= C_028350_RB_MAP_PKR0
;
4740 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_3
);
4743 S_028350_RB_MAP_PKR0(V_028350_RASTER_CONFIG_RB_MAP_0
);
4747 if (rb_per_se
> 2) {
4748 rb0_mask
= 1 << (se
* rb_per_se
+ rb_per_pkr
);
4749 rb1_mask
= rb0_mask
<< 1;
4750 rb0_mask
&= rb_mask
;
4751 rb1_mask
&= rb_mask
;
4752 if (!rb0_mask
|| !rb1_mask
) {
4753 raster_config_se
&= C_028350_RB_MAP_PKR1
;
4757 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_3
);
4760 S_028350_RB_MAP_PKR1(V_028350_RASTER_CONFIG_RB_MAP_0
);
4766 si_set_grbm_gfx_index_se(sctx
, pm4
, se
);
4767 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
, raster_config_se
);
4769 si_set_grbm_gfx_index(sctx
, pm4
, ~0);
4771 if (sctx
->b
.chip_class
>= CIK
) {
4772 if ((num_se
> 2) && ((!se_mask
[0] && !se_mask
[1]) ||
4773 (!se_mask
[2] && !se_mask
[3]))) {
4774 raster_config_1
&= C_028354_SE_PAIR_MAP
;
4776 if (!se_mask
[0] && !se_mask
[1]) {
4778 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_3
);
4781 S_028354_SE_PAIR_MAP(V_028354_RASTER_CONFIG_SE_PAIR_MAP_0
);
4785 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
, raster_config_1
);
4789 static void si_set_raster_config(struct si_context
*sctx
, struct si_pm4_state
*pm4
)
4791 struct si_screen
*sscreen
= sctx
->screen
;
4792 unsigned num_rb
= MIN2(sctx
->screen
->b
.info
.num_render_backends
, 16);
4793 unsigned rb_mask
= sctx
->screen
->b
.info
.enabled_rb_mask
;
4794 unsigned raster_config
, raster_config_1
;
4796 switch (sctx
->b
.family
) {
4799 raster_config
= 0x2a00126a;
4800 raster_config_1
= 0x00000000;
4803 raster_config
= 0x0000124a;
4804 raster_config_1
= 0x00000000;
4807 raster_config
= 0x00000082;
4808 raster_config_1
= 0x00000000;
4811 raster_config
= 0x00000000;
4812 raster_config_1
= 0x00000000;
4815 raster_config
= 0x16000012;
4816 raster_config_1
= 0x00000000;
4819 raster_config
= 0x3a00161a;
4820 raster_config_1
= 0x0000002e;
4823 if (sscreen
->b
.info
.cik_macrotile_mode_array
[0] == 0x000000e8) {
4824 /* old kernels with old tiling config */
4825 raster_config
= 0x16000012;
4826 raster_config_1
= 0x0000002a;
4828 raster_config
= 0x3a00161a;
4829 raster_config_1
= 0x0000002e;
4832 case CHIP_POLARIS10
:
4833 raster_config
= 0x16000012;
4834 raster_config_1
= 0x0000002a;
4836 case CHIP_POLARIS11
:
4837 case CHIP_POLARIS12
:
4838 raster_config
= 0x16000012;
4839 raster_config_1
= 0x00000000;
4842 raster_config
= 0x16000012;
4843 raster_config_1
= 0x0000002a;
4847 raster_config
= 0x00000000;
4849 raster_config
= 0x00000002;
4850 raster_config_1
= 0x00000000;
4853 raster_config
= 0x00000002;
4854 raster_config_1
= 0x00000000;
4857 /* KV should be 0x00000002, but that causes problems with radeon */
4858 raster_config
= 0x00000000; /* 0x00000002 */
4859 raster_config_1
= 0x00000000;
4864 raster_config
= 0x00000000;
4865 raster_config_1
= 0x00000000;
4869 "radeonsi: Unknown GPU, using 0 for raster_config\n");
4870 raster_config
= 0x00000000;
4871 raster_config_1
= 0x00000000;
4874 if (!rb_mask
|| util_bitcount(rb_mask
) >= num_rb
) {
4875 /* Always use the default config when all backends are enabled
4876 * (or when we failed to determine the enabled backends).
4878 si_pm4_set_reg(pm4
, R_028350_PA_SC_RASTER_CONFIG
,
4880 if (sctx
->b
.chip_class
>= CIK
)
4881 si_pm4_set_reg(pm4
, R_028354_PA_SC_RASTER_CONFIG_1
,
4884 si_write_harvested_raster_configs(sctx
, pm4
, raster_config
, raster_config_1
);
4888 static void si_init_config(struct si_context
*sctx
)
4890 struct si_screen
*sscreen
= sctx
->screen
;
4891 uint64_t border_color_va
= sctx
->border_color_buffer
->gpu_address
;
4892 bool has_clear_state
= sscreen
->has_clear_state
;
4893 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
4895 /* Only SI can disable CLEAR_STATE for now. */
4896 assert(has_clear_state
|| sscreen
->b
.chip_class
== SI
);
4901 si_pm4_cmd_begin(pm4
, PKT3_CONTEXT_CONTROL
);
4902 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_LOAD_ENABLE(1));
4903 si_pm4_cmd_add(pm4
, CONTEXT_CONTROL_SHADOW_ENABLE(1));
4904 si_pm4_cmd_end(pm4
, false);
4906 if (has_clear_state
) {
4907 si_pm4_cmd_begin(pm4
, PKT3_CLEAR_STATE
);
4908 si_pm4_cmd_add(pm4
, 0);
4909 si_pm4_cmd_end(pm4
, false);
4912 if (sctx
->b
.chip_class
<= VI
)
4913 si_set_raster_config(sctx
, pm4
);
4915 si_pm4_set_reg(pm4
, R_028A18_VGT_HOS_MAX_TESS_LEVEL
, fui(64));
4916 if (!has_clear_state
)
4917 si_pm4_set_reg(pm4
, R_028A1C_VGT_HOS_MIN_TESS_LEVEL
, fui(0));
4919 /* FIXME calculate these values somehow ??? */
4920 if (sctx
->b
.chip_class
<= VI
) {
4921 si_pm4_set_reg(pm4
, R_028A54_VGT_GS_PER_ES
, SI_GS_PER_ES
);
4922 si_pm4_set_reg(pm4
, R_028A58_VGT_ES_PER_GS
, 0x40);
4925 if (!has_clear_state
) {
4926 si_pm4_set_reg(pm4
, R_028A5C_VGT_GS_PER_VS
, 0x2);
4927 si_pm4_set_reg(pm4
, R_028A8C_VGT_PRIMITIVEID_RESET
, 0x0);
4928 si_pm4_set_reg(pm4
, R_028B98_VGT_STRMOUT_BUFFER_CONFIG
, 0x0);
4931 si_pm4_set_reg(pm4
, R_028AA0_VGT_INSTANCE_STEP_RATE_0
, 1);
4932 if (!has_clear_state
)
4933 si_pm4_set_reg(pm4
, R_028AB8_VGT_VTX_CNT_EN
, 0x0);
4934 if (sctx
->b
.chip_class
< CIK
)
4935 si_pm4_set_reg(pm4
, R_008A14_PA_CL_ENHANCE
, S_008A14_NUM_CLIP_SEQ(3) |
4936 S_008A14_CLIP_VTX_REORDER_ENA(1));
4938 si_pm4_set_reg(pm4
, R_028BD4_PA_SC_CENTROID_PRIORITY_0
, 0x76543210);
4939 si_pm4_set_reg(pm4
, R_028BD8_PA_SC_CENTROID_PRIORITY_1
, 0xfedcba98);
4941 if (!has_clear_state
)
4942 si_pm4_set_reg(pm4
, R_02882C_PA_SU_PRIM_FILTER_CNTL
, 0);
4944 /* CLEAR_STATE doesn't clear these correctly on certain generations.
4945 * I don't know why. Deduced by trial and error.
4947 if (sctx
->b
.chip_class
<= CIK
) {
4948 si_pm4_set_reg(pm4
, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET
, 0);
4949 si_pm4_set_reg(pm4
, R_028204_PA_SC_WINDOW_SCISSOR_TL
, S_028204_WINDOW_OFFSET_DISABLE(1));
4950 si_pm4_set_reg(pm4
, R_028240_PA_SC_GENERIC_SCISSOR_TL
, S_028240_WINDOW_OFFSET_DISABLE(1));
4951 si_pm4_set_reg(pm4
, R_028244_PA_SC_GENERIC_SCISSOR_BR
,
4952 S_028244_BR_X(16384) | S_028244_BR_Y(16384));
4953 si_pm4_set_reg(pm4
, R_028030_PA_SC_SCREEN_SCISSOR_TL
, 0);
4954 si_pm4_set_reg(pm4
, R_028034_PA_SC_SCREEN_SCISSOR_BR
,
4955 S_028034_BR_X(16384) | S_028034_BR_Y(16384));
4958 if (!has_clear_state
) {
4959 si_pm4_set_reg(pm4
, R_02820C_PA_SC_CLIPRECT_RULE
, 0xFFFF);
4960 si_pm4_set_reg(pm4
, R_028230_PA_SC_EDGERULE
,
4961 S_028230_ER_TRI(0xA) |
4962 S_028230_ER_POINT(0xA) |
4963 S_028230_ER_RECT(0xA) |
4964 /* Required by DX10_DIAMOND_TEST_ENA: */
4965 S_028230_ER_LINE_LR(0x1A) |
4966 S_028230_ER_LINE_RL(0x26) |
4967 S_028230_ER_LINE_TB(0xA) |
4968 S_028230_ER_LINE_BT(0xA));
4969 /* PA_SU_HARDWARE_SCREEN_OFFSET must be 0 due to hw bug on SI */
4970 si_pm4_set_reg(pm4
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
, 0);
4971 si_pm4_set_reg(pm4
, R_028820_PA_CL_NANINF_CNTL
, 0);
4972 si_pm4_set_reg(pm4
, R_028AC0_DB_SRESULTS_COMPARE_STATE0
, 0x0);
4973 si_pm4_set_reg(pm4
, R_028AC4_DB_SRESULTS_COMPARE_STATE1
, 0x0);
4974 si_pm4_set_reg(pm4
, R_028AC8_DB_PRELOAD_CONTROL
, 0x0);
4975 si_pm4_set_reg(pm4
, R_02800C_DB_RENDER_OVERRIDE
, 0);
4978 if (sctx
->b
.chip_class
>= GFX9
) {
4979 si_pm4_set_reg(pm4
, R_030920_VGT_MAX_VTX_INDX
, ~0);
4980 si_pm4_set_reg(pm4
, R_030924_VGT_MIN_VTX_INDX
, 0);
4981 si_pm4_set_reg(pm4
, R_030928_VGT_INDX_OFFSET
, 0);
4983 /* These registers, when written, also overwrite the CLEAR_STATE
4984 * context, so we can't rely on CLEAR_STATE setting them.
4985 * It would be an issue if there was another UMD changing them.
4987 si_pm4_set_reg(pm4
, R_028400_VGT_MAX_VTX_INDX
, ~0);
4988 si_pm4_set_reg(pm4
, R_028404_VGT_MIN_VTX_INDX
, 0);
4989 si_pm4_set_reg(pm4
, R_028408_VGT_INDX_OFFSET
, 0);
4992 if (sctx
->b
.chip_class
>= CIK
) {
4993 if (sctx
->b
.chip_class
>= GFX9
) {
4994 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
4995 S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
4997 si_pm4_set_reg(pm4
, R_00B51C_SPI_SHADER_PGM_RSRC3_LS
,
4998 S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
4999 si_pm4_set_reg(pm4
, R_00B41C_SPI_SHADER_PGM_RSRC3_HS
,
5000 S_00B41C_WAVE_LIMIT(0x3F));
5001 si_pm4_set_reg(pm4
, R_00B31C_SPI_SHADER_PGM_RSRC3_ES
,
5002 S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
5004 /* If this is 0, Bonaire can hang even if GS isn't being used.
5005 * Other chips are unaffected. These are suboptimal values,
5006 * but we don't use on-chip GS.
5008 si_pm4_set_reg(pm4
, R_028A44_VGT_GS_ONCHIP_CNTL
,
5009 S_028A44_ES_VERTS_PER_SUBGRP(64) |
5010 S_028A44_GS_PRIMS_PER_SUBGRP(4));
5012 si_pm4_set_reg(pm4
, R_00B21C_SPI_SHADER_PGM_RSRC3_GS
,
5013 S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
5015 /* Compute LATE_ALLOC_VS.LIMIT. */
5016 unsigned num_cu_per_sh
= sscreen
->b
.info
.num_good_compute_units
/
5017 (sscreen
->b
.info
.max_se
*
5018 sscreen
->b
.info
.max_sh_per_se
);
5019 unsigned late_alloc_limit
; /* The limit is per SH. */
5021 if (sctx
->b
.family
== CHIP_KABINI
) {
5022 late_alloc_limit
= 0; /* Potential hang on Kabini. */
5023 } else if (num_cu_per_sh
<= 4) {
5024 /* Too few available compute units per SH. Disallowing
5025 * VS to run on one CU could hurt us more than late VS
5026 * allocation would help.
5028 * 2 is the highest safe number that allows us to keep
5031 late_alloc_limit
= 2;
5033 /* This is a good initial value, allowing 1 late_alloc
5034 * wave per SIMD on num_cu - 2.
5036 late_alloc_limit
= (num_cu_per_sh
- 2) * 4;
5038 /* The limit is 0-based, so 0 means 1. */
5039 assert(late_alloc_limit
> 0 && late_alloc_limit
<= 64);
5040 late_alloc_limit
-= 1;
5043 /* VS can't execute on one CU if the limit is > 2. */
5044 si_pm4_set_reg(pm4
, R_00B118_SPI_SHADER_PGM_RSRC3_VS
,
5045 S_00B118_CU_EN(late_alloc_limit
> 2 ? 0xfffe : 0xffff) |
5046 S_00B118_WAVE_LIMIT(0x3F));
5047 si_pm4_set_reg(pm4
, R_00B11C_SPI_SHADER_LATE_ALLOC_VS
,
5048 S_00B11C_LIMIT(late_alloc_limit
));
5049 si_pm4_set_reg(pm4
, R_00B01C_SPI_SHADER_PGM_RSRC3_PS
,
5050 S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
5053 if (sctx
->b
.chip_class
>= VI
) {
5054 unsigned vgt_tess_distribution
;
5056 si_pm4_set_reg(pm4
, R_028424_CB_DCC_CONTROL
,
5057 S_028424_OVERWRITE_COMBINER_MRT_SHARING_DISABLE(1) |
5058 S_028424_OVERWRITE_COMBINER_WATERMARK(4));
5060 vgt_tess_distribution
=
5061 S_028B50_ACCUM_ISOLINE(32) |
5062 S_028B50_ACCUM_TRI(11) |
5063 S_028B50_ACCUM_QUAD(11) |
5064 S_028B50_DONUT_SPLIT(16);
5066 /* Testing with Unigine Heaven extreme tesselation yielded best results
5067 * with TRAP_SPLIT = 3.
5069 if (sctx
->b
.family
== CHIP_FIJI
||
5070 sctx
->b
.family
>= CHIP_POLARIS10
)
5071 vgt_tess_distribution
|= S_028B50_TRAP_SPLIT(3);
5073 si_pm4_set_reg(pm4
, R_028B50_VGT_TESS_DISTRIBUTION
, vgt_tess_distribution
);
5074 } else if (!has_clear_state
) {
5075 si_pm4_set_reg(pm4
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
, 14);
5076 si_pm4_set_reg(pm4
, R_028C5C_VGT_OUT_DEALLOC_CNTL
, 16);
5079 si_pm4_set_reg(pm4
, R_028080_TA_BC_BASE_ADDR
, border_color_va
>> 8);
5080 if (sctx
->b
.chip_class
>= CIK
)
5081 si_pm4_set_reg(pm4
, R_028084_TA_BC_BASE_ADDR_HI
, border_color_va
>> 40);
5082 si_pm4_add_bo(pm4
, sctx
->border_color_buffer
, RADEON_USAGE_READ
,
5083 RADEON_PRIO_BORDER_COLORS
);
5085 if (sctx
->b
.chip_class
>= GFX9
) {
5086 unsigned num_se
= sscreen
->b
.info
.max_se
;
5087 unsigned pc_lines
= 0;
5089 switch (sctx
->b
.family
) {
5100 si_pm4_set_reg(pm4
, R_028C48_PA_SC_BINNER_CNTL_1
,
5101 S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines
/ (4 * num_se
))) |
5102 S_028C48_MAX_PRIM_PER_BATCH(1023));
5103 si_pm4_set_reg(pm4
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
5104 S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
5105 si_pm4_set_reg(pm4
, R_030968_VGT_INSTANCE_BASE_ID
, 0);
5108 si_pm4_upload_indirect_buffer(sctx
, pm4
);
5109 sctx
->init_config
= pm4
;